| rjw | 6c1fd8f | 2022-11-30 14:33:01 +0800 | [diff] [blame] | 1 | /***************************************************************************** |
| 2 | * Copyright Statement: |
| 3 | * -------------------- |
| 4 | * This software is protected by Copyright and the information contained |
| 5 | * herein is confidential. The software may not be copied and the information |
| 6 | * contained herein may not be used or disclosed except with the written |
| 7 | * permission of MediaTek Inc. (C) 2016 |
| 8 | * |
| 9 | * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES |
| 10 | * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE") |
| 11 | * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON |
| 12 | * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES, |
| 13 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF |
| 14 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT. |
| 15 | * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE |
| 16 | * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR |
| 17 | * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH |
| 18 | * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO |
| 19 | * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S |
| 20 | * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM. |
| 21 | * |
| 22 | * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE |
| 23 | * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE, |
| 24 | * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE, |
| 25 | * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO |
| 26 | * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. |
| 27 | * |
| 28 | * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE |
| 29 | * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF |
| 30 | * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND |
| 31 | * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER |
| 32 | * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC). |
| 33 | * |
| 34 | *****************************************************************************/ |
| 35 | #ifndef _CPH_C2K_RXDFE_H_ |
| 36 | #define _CPH_C2K_RXDFE_H_ |
| 37 | |
| 38 | |
| 39 | typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */ |
| 40 | typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */ |
| 41 | typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */ |
| 42 | typedef volatile unsigned short APBDATA; /* APB data is 16 bits */ |
| 43 | typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */ |
| 44 | typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */ |
| 45 | typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */ |
| 46 | typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */ |
| 47 | typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */ |
| 48 | |
| 49 | |
| 50 | #define RXDFE_FC_ACT_REG_BASE (0xA70C0000) |
| 51 | |
| 52 | #define RXDFE_FC_ACT_end (RXDFE_FC_ACT_REG_BASE + 0x01A0 + 1*4) |
| 53 | |
| 54 | |
| 55 | |
| 56 | #define RXDFE_FC_P_SWAP ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0000)) |
| 57 | #define RXDFE_FC_A_SWAP_P0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0004)) |
| 58 | #define RXDFE_FC_MS_WB_0_P0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0008)) |
| 59 | #define RXDFE_FC_MS_WB_1_P0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x000C)) |
| 60 | #define RXDFE_FC_A_SWAP_P1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0010)) |
| 61 | #define RXDFE_FC_MS_WB_0_P1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0014)) |
| 62 | #define RXDFE_FC_MS_WB_1_P1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0018)) |
| 63 | #define RXDFE_FC_P_CON_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x001C)) |
| 64 | #define RXDFE_FC_SW_DCOC_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0020)) |
| 65 | #define RXDFE_FC_P_CON_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0024)) |
| 66 | #define RXDFE_FC_SW_DCOC_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0028)) |
| 67 | #define RXDFE_FC_P_CON_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x002C)) |
| 68 | #define RXDFE_FC_SW_DCOC_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0030)) |
| 69 | #define RXDFE_FC_P_CON_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0034)) |
| 70 | #define RXDFE_FC_SW_DCOC_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0038)) |
| 71 | #define RXDFE_FC_C_CON_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x003C)) |
| 72 | #define RXDFE_FC_SW_DAGC_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0040)) |
| 73 | #define RXDFE_FC_SW_CS_DAGC_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0044)) |
| 74 | #define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0048)) |
| 75 | #define RXDFE_FC_C_CON_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x004C)) |
| 76 | #define RXDFE_FC_SW_DAGC_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0050)) |
| 77 | #define RXDFE_FC_SW_CS_DAGC_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0054)) |
| 78 | #define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0058)) |
| 79 | #define RXDFE_FC_C_CON_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x005C)) |
| 80 | #define RXDFE_FC_SW_DAGC_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0060)) |
| 81 | #define RXDFE_FC_SW_CS_DAGC_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0064)) |
| 82 | #define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0068)) |
| 83 | #define RXDFE_FC_C_CON_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x006C)) |
| 84 | #define RXDFE_FC_SW_DAGC_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0070)) |
| 85 | #define RXDFE_FC_SW_CS_DAGC_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0074)) |
| 86 | #define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0078)) |
| 87 | #define RXDFE_FC_FDPM_0_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x007C)) |
| 88 | #define RXDFE_FC_FDPM_1_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0080)) |
| 89 | #define RXDFE_FC_FDPM_2_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0084)) |
| 90 | #define RXDFE_FC_RFEQ_0_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0088)) |
| 91 | #define RXDFE_FC_RFEQ_1_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x008C)) |
| 92 | #define RXDFE_FC_RFEQ_2_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0090)) |
| 93 | #define RXDFE_FC_RFEQ_3_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0094)) |
| 94 | #define RXDFE_FC_RFEQ_4_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0098)) |
| 95 | #define RXDFE_FC_IQC_P0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x009C)) |
| 96 | #define RXDFE_FC_FDPM_0_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00A0)) |
| 97 | #define RXDFE_FC_FDPM_1_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00A4)) |
| 98 | #define RXDFE_FC_FDPM_2_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00A8)) |
| 99 | #define RXDFE_FC_RFEQ_0_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00AC)) |
| 100 | #define RXDFE_FC_RFEQ_1_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00B0)) |
| 101 | #define RXDFE_FC_RFEQ_2_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00B4)) |
| 102 | #define RXDFE_FC_RFEQ_3_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00B8)) |
| 103 | #define RXDFE_FC_RFEQ_4_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00BC)) |
| 104 | #define RXDFE_FC_IQC_P0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00C0)) |
| 105 | #define RXDFE_FC_FDPM_0_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00C4)) |
| 106 | #define RXDFE_FC_FDPM_1_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00C8)) |
| 107 | #define RXDFE_FC_FDPM_2_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00CC)) |
| 108 | #define RXDFE_FC_RFEQ_0_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00D0)) |
| 109 | #define RXDFE_FC_RFEQ_1_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00D4)) |
| 110 | #define RXDFE_FC_RFEQ_2_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00D8)) |
| 111 | #define RXDFE_FC_RFEQ_3_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00DC)) |
| 112 | #define RXDFE_FC_RFEQ_4_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00E0)) |
| 113 | #define RXDFE_FC_IQC_P1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00E4)) |
| 114 | #define RXDFE_FC_FDPM_0_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00E8)) |
| 115 | #define RXDFE_FC_FDPM_1_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00EC)) |
| 116 | #define RXDFE_FC_FDPM_2_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00F0)) |
| 117 | #define RXDFE_FC_RFEQ_0_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00F4)) |
| 118 | #define RXDFE_FC_RFEQ_1_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00F8)) |
| 119 | #define RXDFE_FC_RFEQ_2_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x00FC)) |
| 120 | #define RXDFE_FC_RFEQ_3_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0100)) |
| 121 | #define RXDFE_FC_RFEQ_4_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0104)) |
| 122 | #define RXDFE_FC_IQC_P1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0108)) |
| 123 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x010C + (n)*4)) //n is from 0 to 3 |
| 124 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x011C + (n)*4)) //n is from 0 to 3 |
| 125 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x012C + (n)*4)) //n is from 0 to 3 |
| 126 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x013C + (n)*4)) //n is from 0 to 3 |
| 127 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x014C + (n)*4)) //n is from 0 to 3 |
| 128 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x015C + (n)*4)) //n is from 0 to 3 |
| 129 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x016C + (n)*4)) //n is from 0 to 3 |
| 130 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1(n) ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x017C + (n)*4)) //n is from 0 to 3 |
| 131 | #define RXDFE_FC_NCO_C0_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x018C)) |
| 132 | #define RXDFE_FC_NCO_C0_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0190)) |
| 133 | #define RXDFE_FC_NCO_C1_A0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0194)) |
| 134 | #define RXDFE_FC_NCO_C1_A1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x0198)) |
| 135 | #define RXDFE_FC_NCO_MBSFN_C0 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x019C)) |
| 136 | #define RXDFE_FC_NCO_MBSFN_C1 ((APBADDR32)(RXDFE_FC_ACT_REG_BASE + 0x01A0)) |
| 137 | |
| 138 | |
| 139 | #define RXDFE_FC_P_SWAP_P_SWAP_LSB (0) |
| 140 | #define RXDFE_FC_P_SWAP_P_SWAP_WIDTH (1) |
| 141 | #define RXDFE_FC_P_SWAP_P_SWAP_MASK (0x00000001) |
| 142 | #define RXDFE_FC_P_SWAP_P_SWAP_BIT (0x00000001) |
| 143 | |
| 144 | #define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_LSB (0) |
| 145 | #define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_WIDTH (1) |
| 146 | #define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_MASK (0x00000001) |
| 147 | #define RXDFE_FC_A_SWAP_P0_A_SWAP_P0_BIT (0x00000001) |
| 148 | |
| 149 | #define RXDFE_FC_MS_WB_0_P0_WB_COEF_3_P0_LSB (24) |
| 150 | #define RXDFE_FC_MS_WB_0_P0_WB_COEF_3_P0_WIDTH (7) |
| 151 | #define RXDFE_FC_MS_WB_0_P0_WB_COEF_3_P0_MASK (0x7F000000) |
| 152 | |
| 153 | #define RXDFE_FC_MS_WB_0_P0_WB_COEF_2_P0_LSB (16) |
| 154 | #define RXDFE_FC_MS_WB_0_P0_WB_COEF_2_P0_WIDTH (7) |
| 155 | #define RXDFE_FC_MS_WB_0_P0_WB_COEF_2_P0_MASK (0x007F0000) |
| 156 | |
| 157 | #define RXDFE_FC_MS_WB_0_P0_WB_COEF_1_P0_LSB (8) |
| 158 | #define RXDFE_FC_MS_WB_0_P0_WB_COEF_1_P0_WIDTH (7) |
| 159 | #define RXDFE_FC_MS_WB_0_P0_WB_COEF_1_P0_MASK (0x00007F00) |
| 160 | |
| 161 | #define RXDFE_FC_MS_WB_0_P0_WB_COEF_0_P0_LSB (0) |
| 162 | #define RXDFE_FC_MS_WB_0_P0_WB_COEF_0_P0_WIDTH (7) |
| 163 | #define RXDFE_FC_MS_WB_0_P0_WB_COEF_0_P0_MASK (0x0000007F) |
| 164 | |
| 165 | #define RXDFE_FC_MS_WB_1_P0_WB_COEF_4_P0_LSB (0) |
| 166 | #define RXDFE_FC_MS_WB_1_P0_WB_COEF_4_P0_WIDTH (7) |
| 167 | #define RXDFE_FC_MS_WB_1_P0_WB_COEF_4_P0_MASK (0x0000007F) |
| 168 | |
| 169 | #define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_LSB (0) |
| 170 | #define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_WIDTH (1) |
| 171 | #define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_MASK (0x00000001) |
| 172 | #define RXDFE_FC_A_SWAP_P1_A_SWAP_P1_BIT (0x00000001) |
| 173 | |
| 174 | #define RXDFE_FC_MS_WB_0_P1_WB_COEF_3_P1_LSB (24) |
| 175 | #define RXDFE_FC_MS_WB_0_P1_WB_COEF_3_P1_WIDTH (7) |
| 176 | #define RXDFE_FC_MS_WB_0_P1_WB_COEF_3_P1_MASK (0x7F000000) |
| 177 | |
| 178 | #define RXDFE_FC_MS_WB_0_P1_WB_COEF_2_P1_LSB (16) |
| 179 | #define RXDFE_FC_MS_WB_0_P1_WB_COEF_2_P1_WIDTH (7) |
| 180 | #define RXDFE_FC_MS_WB_0_P1_WB_COEF_2_P1_MASK (0x007F0000) |
| 181 | |
| 182 | #define RXDFE_FC_MS_WB_0_P1_WB_COEF_1_P1_LSB (8) |
| 183 | #define RXDFE_FC_MS_WB_0_P1_WB_COEF_1_P1_WIDTH (7) |
| 184 | #define RXDFE_FC_MS_WB_0_P1_WB_COEF_1_P1_MASK (0x00007F00) |
| 185 | |
| 186 | #define RXDFE_FC_MS_WB_0_P1_WB_COEF_0_P1_LSB (0) |
| 187 | #define RXDFE_FC_MS_WB_0_P1_WB_COEF_0_P1_WIDTH (7) |
| 188 | #define RXDFE_FC_MS_WB_0_P1_WB_COEF_0_P1_MASK (0x0000007F) |
| 189 | |
| 190 | #define RXDFE_FC_MS_WB_1_P1_WB_COEF_4_P1_LSB (0) |
| 191 | #define RXDFE_FC_MS_WB_1_P1_WB_COEF_4_P1_WIDTH (7) |
| 192 | #define RXDFE_FC_MS_WB_1_P1_WB_COEF_4_P1_MASK (0x0000007F) |
| 193 | |
| 194 | #define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_LSB (20) |
| 195 | #define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_WIDTH (1) |
| 196 | #define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_MASK (0x00100000) |
| 197 | #define RXDFE_FC_P_CON_P0_A0_SW_DCOC_COMP_EN_P0_A0_BIT (0x00100000) |
| 198 | |
| 199 | #define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_LSB (15) |
| 200 | #define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_WIDTH (1) |
| 201 | #define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_MASK (0x00008000) |
| 202 | #define RXDFE_FC_P_CON_P0_A0_P_FDPM_EN_P0_A0_BIT (0x00008000) |
| 203 | |
| 204 | #define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_LSB (14) |
| 205 | #define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_WIDTH (1) |
| 206 | #define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_MASK (0x00004000) |
| 207 | #define RXDFE_FC_P_CON_P0_A0_P_RFEQ_EN_P0_A0_BIT (0x00004000) |
| 208 | |
| 209 | #define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_LSB (13) |
| 210 | #define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_WIDTH (1) |
| 211 | #define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_MASK (0x00002000) |
| 212 | #define RXDFE_FC_P_CON_P0_A0_P_IQC_EN_P0_A0_BIT (0x00002000) |
| 213 | |
| 214 | #define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_LSB (12) |
| 215 | #define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_WIDTH (1) |
| 216 | #define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_MASK (0x00001000) |
| 217 | #define RXDFE_FC_P_CON_P0_A0_P_NBIF_EN_P0_A0_BIT (0x00001000) |
| 218 | |
| 219 | #define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_LSB (10) |
| 220 | #define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_WIDTH (1) |
| 221 | #define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_MASK (0x00000400) |
| 222 | #define RXDFE_FC_P_CON_P0_A0_Q_INV_P0_A0_BIT (0x00000400) |
| 223 | |
| 224 | #define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_LSB (9) |
| 225 | #define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_WIDTH (1) |
| 226 | #define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_MASK (0x00000200) |
| 227 | #define RXDFE_FC_P_CON_P0_A0_I_INV_P0_A0_BIT (0x00000200) |
| 228 | |
| 229 | #define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_LSB (8) |
| 230 | #define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_WIDTH (1) |
| 231 | #define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_MASK (0x00000100) |
| 232 | #define RXDFE_FC_P_CON_P0_A0_IQ_SWAP_P0_A0_BIT (0x00000100) |
| 233 | |
| 234 | #define RXDFE_FC_P_CON_P0_A0_ADC_MODE_P0_A0_LSB (4) |
| 235 | #define RXDFE_FC_P_CON_P0_A0_ADC_MODE_P0_A0_WIDTH (4) |
| 236 | #define RXDFE_FC_P_CON_P0_A0_ADC_MODE_P0_A0_MASK (0x000000F0) |
| 237 | |
| 238 | #define RXDFE_FC_P_CON_P0_A0_P_MODE_P0_A0_LSB (0) |
| 239 | #define RXDFE_FC_P_CON_P0_A0_P_MODE_P0_A0_WIDTH (4) |
| 240 | #define RXDFE_FC_P_CON_P0_A0_P_MODE_P0_A0_MASK (0x0000000F) |
| 241 | |
| 242 | #define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_Q_P0_A0_LSB (16) |
| 243 | #define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_Q_P0_A0_WIDTH (15) |
| 244 | #define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_Q_P0_A0_MASK (0x7FFF0000) |
| 245 | |
| 246 | #define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_I_P0_A0_LSB (0) |
| 247 | #define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_I_P0_A0_WIDTH (15) |
| 248 | #define RXDFE_FC_SW_DCOC_P0_A0_SW_DCOC_COMP_I_P0_A0_MASK (0x00007FFF) |
| 249 | |
| 250 | #define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_LSB (20) |
| 251 | #define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_WIDTH (1) |
| 252 | #define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_MASK (0x00100000) |
| 253 | #define RXDFE_FC_P_CON_P0_A1_SW_DCOC_COMP_EN_P0_A1_BIT (0x00100000) |
| 254 | |
| 255 | #define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_LSB (15) |
| 256 | #define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_WIDTH (1) |
| 257 | #define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_MASK (0x00008000) |
| 258 | #define RXDFE_FC_P_CON_P0_A1_P_FDPM_EN_P0_A1_BIT (0x00008000) |
| 259 | |
| 260 | #define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_LSB (14) |
| 261 | #define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_WIDTH (1) |
| 262 | #define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_MASK (0x00004000) |
| 263 | #define RXDFE_FC_P_CON_P0_A1_P_RFEQ_EN_P0_A1_BIT (0x00004000) |
| 264 | |
| 265 | #define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_LSB (13) |
| 266 | #define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_WIDTH (1) |
| 267 | #define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_MASK (0x00002000) |
| 268 | #define RXDFE_FC_P_CON_P0_A1_P_IQC_EN_P0_A1_BIT (0x00002000) |
| 269 | |
| 270 | #define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_LSB (12) |
| 271 | #define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_WIDTH (1) |
| 272 | #define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_MASK (0x00001000) |
| 273 | #define RXDFE_FC_P_CON_P0_A1_P_NBIF_EN_P0_A1_BIT (0x00001000) |
| 274 | |
| 275 | #define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_LSB (10) |
| 276 | #define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_WIDTH (1) |
| 277 | #define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_MASK (0x00000400) |
| 278 | #define RXDFE_FC_P_CON_P0_A1_Q_INV_P0_A1_BIT (0x00000400) |
| 279 | |
| 280 | #define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_LSB (9) |
| 281 | #define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_WIDTH (1) |
| 282 | #define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_MASK (0x00000200) |
| 283 | #define RXDFE_FC_P_CON_P0_A1_I_INV_P0_A1_BIT (0x00000200) |
| 284 | |
| 285 | #define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_LSB (8) |
| 286 | #define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_WIDTH (1) |
| 287 | #define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_MASK (0x00000100) |
| 288 | #define RXDFE_FC_P_CON_P0_A1_IQ_SWAP_P0_A1_BIT (0x00000100) |
| 289 | |
| 290 | #define RXDFE_FC_P_CON_P0_A1_ADC_MODE_P0_A1_LSB (4) |
| 291 | #define RXDFE_FC_P_CON_P0_A1_ADC_MODE_P0_A1_WIDTH (4) |
| 292 | #define RXDFE_FC_P_CON_P0_A1_ADC_MODE_P0_A1_MASK (0x000000F0) |
| 293 | |
| 294 | #define RXDFE_FC_P_CON_P0_A1_P_MODE_P0_A1_LSB (0) |
| 295 | #define RXDFE_FC_P_CON_P0_A1_P_MODE_P0_A1_WIDTH (4) |
| 296 | #define RXDFE_FC_P_CON_P0_A1_P_MODE_P0_A1_MASK (0x0000000F) |
| 297 | |
| 298 | #define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_Q_P0_A1_LSB (16) |
| 299 | #define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_Q_P0_A1_WIDTH (15) |
| 300 | #define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_Q_P0_A1_MASK (0x7FFF0000) |
| 301 | |
| 302 | #define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_I_P0_A1_LSB (0) |
| 303 | #define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_I_P0_A1_WIDTH (15) |
| 304 | #define RXDFE_FC_SW_DCOC_P0_A1_SW_DCOC_COMP_I_P0_A1_MASK (0x00007FFF) |
| 305 | |
| 306 | #define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_LSB (20) |
| 307 | #define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_WIDTH (1) |
| 308 | #define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_MASK (0x00100000) |
| 309 | #define RXDFE_FC_P_CON_P1_A0_SW_DCOC_COMP_EN_P1_A0_BIT (0x00100000) |
| 310 | |
| 311 | #define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_LSB (15) |
| 312 | #define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_WIDTH (1) |
| 313 | #define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_MASK (0x00008000) |
| 314 | #define RXDFE_FC_P_CON_P1_A0_P_FDPM_EN_P1_A0_BIT (0x00008000) |
| 315 | |
| 316 | #define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_LSB (14) |
| 317 | #define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_WIDTH (1) |
| 318 | #define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_MASK (0x00004000) |
| 319 | #define RXDFE_FC_P_CON_P1_A0_P_RFEQ_EN_P1_A0_BIT (0x00004000) |
| 320 | |
| 321 | #define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_LSB (13) |
| 322 | #define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_WIDTH (1) |
| 323 | #define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_MASK (0x00002000) |
| 324 | #define RXDFE_FC_P_CON_P1_A0_P_IQC_EN_P1_A0_BIT (0x00002000) |
| 325 | |
| 326 | #define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_LSB (12) |
| 327 | #define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_WIDTH (1) |
| 328 | #define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_MASK (0x00001000) |
| 329 | #define RXDFE_FC_P_CON_P1_A0_P_NBIF_EN_P1_A0_BIT (0x00001000) |
| 330 | |
| 331 | #define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_LSB (10) |
| 332 | #define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_WIDTH (1) |
| 333 | #define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_MASK (0x00000400) |
| 334 | #define RXDFE_FC_P_CON_P1_A0_Q_INV_P1_A0_BIT (0x00000400) |
| 335 | |
| 336 | #define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_LSB (9) |
| 337 | #define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_WIDTH (1) |
| 338 | #define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_MASK (0x00000200) |
| 339 | #define RXDFE_FC_P_CON_P1_A0_I_INV_P1_A0_BIT (0x00000200) |
| 340 | |
| 341 | #define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_LSB (8) |
| 342 | #define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_WIDTH (1) |
| 343 | #define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_MASK (0x00000100) |
| 344 | #define RXDFE_FC_P_CON_P1_A0_IQ_SWAP_P1_A0_BIT (0x00000100) |
| 345 | |
| 346 | #define RXDFE_FC_P_CON_P1_A0_ADC_MODE_P1_A0_LSB (4) |
| 347 | #define RXDFE_FC_P_CON_P1_A0_ADC_MODE_P1_A0_WIDTH (4) |
| 348 | #define RXDFE_FC_P_CON_P1_A0_ADC_MODE_P1_A0_MASK (0x000000F0) |
| 349 | |
| 350 | #define RXDFE_FC_P_CON_P1_A0_P_MODE_P1_A0_LSB (0) |
| 351 | #define RXDFE_FC_P_CON_P1_A0_P_MODE_P1_A0_WIDTH (4) |
| 352 | #define RXDFE_FC_P_CON_P1_A0_P_MODE_P1_A0_MASK (0x0000000F) |
| 353 | |
| 354 | #define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_Q_P1_A0_LSB (16) |
| 355 | #define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_Q_P1_A0_WIDTH (15) |
| 356 | #define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_Q_P1_A0_MASK (0x7FFF0000) |
| 357 | |
| 358 | #define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_I_P1_A0_LSB (0) |
| 359 | #define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_I_P1_A0_WIDTH (15) |
| 360 | #define RXDFE_FC_SW_DCOC_P1_A0_SW_DCOC_COMP_I_P1_A0_MASK (0x00007FFF) |
| 361 | |
| 362 | #define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_LSB (20) |
| 363 | #define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_WIDTH (1) |
| 364 | #define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_MASK (0x00100000) |
| 365 | #define RXDFE_FC_P_CON_P1_A1_SW_DCOC_COMP_EN_P1_A1_BIT (0x00100000) |
| 366 | |
| 367 | #define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_LSB (15) |
| 368 | #define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_WIDTH (1) |
| 369 | #define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_MASK (0x00008000) |
| 370 | #define RXDFE_FC_P_CON_P1_A1_P_FDPM_EN_P1_A1_BIT (0x00008000) |
| 371 | |
| 372 | #define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_LSB (14) |
| 373 | #define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_WIDTH (1) |
| 374 | #define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_MASK (0x00004000) |
| 375 | #define RXDFE_FC_P_CON_P1_A1_P_RFEQ_EN_P1_A1_BIT (0x00004000) |
| 376 | |
| 377 | #define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_LSB (13) |
| 378 | #define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_WIDTH (1) |
| 379 | #define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_MASK (0x00002000) |
| 380 | #define RXDFE_FC_P_CON_P1_A1_P_IQC_EN_P1_A1_BIT (0x00002000) |
| 381 | |
| 382 | #define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_LSB (12) |
| 383 | #define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_WIDTH (1) |
| 384 | #define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_MASK (0x00001000) |
| 385 | #define RXDFE_FC_P_CON_P1_A1_P_NBIF_EN_P1_A1_BIT (0x00001000) |
| 386 | |
| 387 | #define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_LSB (10) |
| 388 | #define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_WIDTH (1) |
| 389 | #define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_MASK (0x00000400) |
| 390 | #define RXDFE_FC_P_CON_P1_A1_Q_INV_P1_A1_BIT (0x00000400) |
| 391 | |
| 392 | #define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_LSB (9) |
| 393 | #define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_WIDTH (1) |
| 394 | #define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_MASK (0x00000200) |
| 395 | #define RXDFE_FC_P_CON_P1_A1_I_INV_P1_A1_BIT (0x00000200) |
| 396 | |
| 397 | #define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_LSB (8) |
| 398 | #define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_WIDTH (1) |
| 399 | #define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_MASK (0x00000100) |
| 400 | #define RXDFE_FC_P_CON_P1_A1_IQ_SWAP_P1_A1_BIT (0x00000100) |
| 401 | |
| 402 | #define RXDFE_FC_P_CON_P1_A1_ADC_MODE_P1_A1_LSB (4) |
| 403 | #define RXDFE_FC_P_CON_P1_A1_ADC_MODE_P1_A1_WIDTH (4) |
| 404 | #define RXDFE_FC_P_CON_P1_A1_ADC_MODE_P1_A1_MASK (0x000000F0) |
| 405 | |
| 406 | #define RXDFE_FC_P_CON_P1_A1_P_MODE_P1_A1_LSB (0) |
| 407 | #define RXDFE_FC_P_CON_P1_A1_P_MODE_P1_A1_WIDTH (4) |
| 408 | #define RXDFE_FC_P_CON_P1_A1_P_MODE_P1_A1_MASK (0x0000000F) |
| 409 | |
| 410 | #define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_Q_P1_A1_LSB (16) |
| 411 | #define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_Q_P1_A1_WIDTH (15) |
| 412 | #define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_Q_P1_A1_MASK (0x7FFF0000) |
| 413 | |
| 414 | #define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_I_P1_A1_LSB (0) |
| 415 | #define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_I_P1_A1_WIDTH (15) |
| 416 | #define RXDFE_FC_SW_DCOC_P1_A1_SW_DCOC_COMP_I_P1_A1_MASK (0x00007FFF) |
| 417 | |
| 418 | #define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_LSB (22) |
| 419 | #define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_WIDTH (1) |
| 420 | #define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_MASK (0x00400000) |
| 421 | #define RXDFE_FC_C_CON_C0_A0_SW_NCO_LNA_COMP_EN_C0_A0_BIT (0x00400000) |
| 422 | |
| 423 | #define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_LSB (21) |
| 424 | #define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_WIDTH (1) |
| 425 | #define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_MASK (0x00200000) |
| 426 | #define RXDFE_FC_C_CON_C0_A0_SW_DAGC_EN_C0_A0_BIT (0x00200000) |
| 427 | |
| 428 | #define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_LSB (20) |
| 429 | #define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_WIDTH (1) |
| 430 | #define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_MASK (0x00100000) |
| 431 | #define RXDFE_FC_C_CON_C0_A0_SW_CS_DAGC_EN_C0_A0_BIT (0x00100000) |
| 432 | |
| 433 | #define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_LSB (13) |
| 434 | #define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_WIDTH (1) |
| 435 | #define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_MASK (0x00002000) |
| 436 | #define RXDFE_FC_C_CON_C0_A0_C_NCO_MBSFN_EN_C0_A0_BIT (0x00002000) |
| 437 | |
| 438 | #define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_LSB (12) |
| 439 | #define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_WIDTH (1) |
| 440 | #define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_MASK (0x00001000) |
| 441 | #define RXDFE_FC_C_CON_C0_A0_C_NCO_EN_C0_A0_BIT (0x00001000) |
| 442 | |
| 443 | #define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_LSB (8) |
| 444 | #define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_WIDTH (1) |
| 445 | #define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_MASK (0x00000100) |
| 446 | #define RXDFE_FC_C_CON_C0_A0_MU_GEN_C2K_MODE_C0_A0_BIT (0x00000100) |
| 447 | |
| 448 | #define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_LSB (4) |
| 449 | #define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_WIDTH (1) |
| 450 | #define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_MASK (0x00000010) |
| 451 | #define RXDFE_FC_C_CON_C0_A0_C_IN_SEL_C0_A0_BIT (0x00000010) |
| 452 | |
| 453 | #define RXDFE_FC_C_CON_C0_A0_C_MODE_C0_A0_LSB (0) |
| 454 | #define RXDFE_FC_C_CON_C0_A0_C_MODE_C0_A0_WIDTH (4) |
| 455 | #define RXDFE_FC_C_CON_C0_A0_C_MODE_C0_A0_MASK (0x0000000F) |
| 456 | |
| 457 | #define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_EXP_C0_A0_LSB (8) |
| 458 | #define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_EXP_C0_A0_WIDTH (5) |
| 459 | #define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_EXP_C0_A0_MASK (0x00001F00) |
| 460 | |
| 461 | #define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_MAN_C0_A0_LSB (0) |
| 462 | #define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_MAN_C0_A0_WIDTH (7) |
| 463 | #define RXDFE_FC_SW_DAGC_C0_A0_SW_DAGC_MAN_C0_A0_MASK (0x0000007F) |
| 464 | |
| 465 | #define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_EXP_C0_A0_LSB (8) |
| 466 | #define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_EXP_C0_A0_WIDTH (5) |
| 467 | #define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_EXP_C0_A0_MASK (0x00001F00) |
| 468 | |
| 469 | #define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_MAN_C0_A0_LSB (0) |
| 470 | #define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_MAN_C0_A0_WIDTH (7) |
| 471 | #define RXDFE_FC_SW_CS_DAGC_C0_A0_SW_CS_DAGC_MAN_C0_A0_MASK (0x0000007F) |
| 472 | |
| 473 | #define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0_SW_NCO_LNA_COMP_C0_A0_LSB (0) |
| 474 | #define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0_SW_NCO_LNA_COMP_C0_A0_WIDTH (23) |
| 475 | #define RXDFE_FC_SW_NCO_LNA_COMP_C0_A0_SW_NCO_LNA_COMP_C0_A0_MASK (0x007FFFFF) |
| 476 | |
| 477 | #define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_LSB (22) |
| 478 | #define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_WIDTH (1) |
| 479 | #define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_MASK (0x00400000) |
| 480 | #define RXDFE_FC_C_CON_C0_A1_SW_NCO_LNA_COMP_EN_C0_A1_BIT (0x00400000) |
| 481 | |
| 482 | #define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_LSB (21) |
| 483 | #define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_WIDTH (1) |
| 484 | #define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_MASK (0x00200000) |
| 485 | #define RXDFE_FC_C_CON_C0_A1_SW_DAGC_EN_C0_A1_BIT (0x00200000) |
| 486 | |
| 487 | #define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_LSB (20) |
| 488 | #define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_WIDTH (1) |
| 489 | #define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_MASK (0x00100000) |
| 490 | #define RXDFE_FC_C_CON_C0_A1_SW_CS_DAGC_EN_C0_A1_BIT (0x00100000) |
| 491 | |
| 492 | #define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_LSB (13) |
| 493 | #define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_WIDTH (1) |
| 494 | #define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_MASK (0x00002000) |
| 495 | #define RXDFE_FC_C_CON_C0_A1_C_NCO_MBSFN_EN_C0_A1_BIT (0x00002000) |
| 496 | |
| 497 | #define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_LSB (12) |
| 498 | #define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_WIDTH (1) |
| 499 | #define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_MASK (0x00001000) |
| 500 | #define RXDFE_FC_C_CON_C0_A1_C_NCO_EN_C0_A1_BIT (0x00001000) |
| 501 | |
| 502 | #define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_LSB (8) |
| 503 | #define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_WIDTH (1) |
| 504 | #define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_MASK (0x00000100) |
| 505 | #define RXDFE_FC_C_CON_C0_A1_MU_GEN_C2K_MODE_C0_A1_BIT (0x00000100) |
| 506 | |
| 507 | #define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_LSB (4) |
| 508 | #define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_WIDTH (1) |
| 509 | #define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_MASK (0x00000010) |
| 510 | #define RXDFE_FC_C_CON_C0_A1_C_IN_SEL_C0_A1_BIT (0x00000010) |
| 511 | |
| 512 | #define RXDFE_FC_C_CON_C0_A1_C_MODE_C0_A1_LSB (0) |
| 513 | #define RXDFE_FC_C_CON_C0_A1_C_MODE_C0_A1_WIDTH (4) |
| 514 | #define RXDFE_FC_C_CON_C0_A1_C_MODE_C0_A1_MASK (0x0000000F) |
| 515 | |
| 516 | #define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_EXP_C0_A1_LSB (8) |
| 517 | #define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_EXP_C0_A1_WIDTH (5) |
| 518 | #define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_EXP_C0_A1_MASK (0x00001F00) |
| 519 | |
| 520 | #define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_MAN_C0_A1_LSB (0) |
| 521 | #define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_MAN_C0_A1_WIDTH (7) |
| 522 | #define RXDFE_FC_SW_DAGC_C0_A1_SW_DAGC_MAN_C0_A1_MASK (0x0000007F) |
| 523 | |
| 524 | #define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_EXP_C0_A1_LSB (8) |
| 525 | #define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_EXP_C0_A1_WIDTH (5) |
| 526 | #define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_EXP_C0_A1_MASK (0x00001F00) |
| 527 | |
| 528 | #define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_MAN_C0_A1_LSB (0) |
| 529 | #define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_MAN_C0_A1_WIDTH (7) |
| 530 | #define RXDFE_FC_SW_CS_DAGC_C0_A1_SW_CS_DAGC_MAN_C0_A1_MASK (0x0000007F) |
| 531 | |
| 532 | #define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1_SW_NCO_LNA_COMP_C0_A1_LSB (0) |
| 533 | #define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1_SW_NCO_LNA_COMP_C0_A1_WIDTH (23) |
| 534 | #define RXDFE_FC_SW_NCO_LNA_COMP_C0_A1_SW_NCO_LNA_COMP_C0_A1_MASK (0x007FFFFF) |
| 535 | |
| 536 | #define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_LSB (22) |
| 537 | #define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_WIDTH (1) |
| 538 | #define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_MASK (0x00400000) |
| 539 | #define RXDFE_FC_C_CON_C1_A0_SW_NCO_LNA_COMP_EN_C1_A0_BIT (0x00400000) |
| 540 | |
| 541 | #define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_LSB (21) |
| 542 | #define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_WIDTH (1) |
| 543 | #define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_MASK (0x00200000) |
| 544 | #define RXDFE_FC_C_CON_C1_A0_SW_DAGC_EN_C1_A0_BIT (0x00200000) |
| 545 | |
| 546 | #define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_LSB (20) |
| 547 | #define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_WIDTH (1) |
| 548 | #define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_MASK (0x00100000) |
| 549 | #define RXDFE_FC_C_CON_C1_A0_SW_CS_DAGC_EN_C1_A0_BIT (0x00100000) |
| 550 | |
| 551 | #define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_LSB (13) |
| 552 | #define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_WIDTH (1) |
| 553 | #define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_MASK (0x00002000) |
| 554 | #define RXDFE_FC_C_CON_C1_A0_C_NCO_MBSFN_EN_C1_A0_BIT (0x00002000) |
| 555 | |
| 556 | #define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_LSB (12) |
| 557 | #define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_WIDTH (1) |
| 558 | #define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_MASK (0x00001000) |
| 559 | #define RXDFE_FC_C_CON_C1_A0_C_NCO_EN_C1_A0_BIT (0x00001000) |
| 560 | |
| 561 | #define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_LSB (8) |
| 562 | #define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_WIDTH (1) |
| 563 | #define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_MASK (0x00000100) |
| 564 | #define RXDFE_FC_C_CON_C1_A0_MU_GEN_C2K_MODE_C1_A0_BIT (0x00000100) |
| 565 | |
| 566 | #define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_LSB (4) |
| 567 | #define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_WIDTH (1) |
| 568 | #define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_MASK (0x00000010) |
| 569 | #define RXDFE_FC_C_CON_C1_A0_C_IN_SEL_C1_A0_BIT (0x00000010) |
| 570 | |
| 571 | #define RXDFE_FC_C_CON_C1_A0_C_MODE_C1_A0_LSB (0) |
| 572 | #define RXDFE_FC_C_CON_C1_A0_C_MODE_C1_A0_WIDTH (4) |
| 573 | #define RXDFE_FC_C_CON_C1_A0_C_MODE_C1_A0_MASK (0x0000000F) |
| 574 | |
| 575 | #define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_EXP_C1_A0_LSB (8) |
| 576 | #define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_EXP_C1_A0_WIDTH (5) |
| 577 | #define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_EXP_C1_A0_MASK (0x00001F00) |
| 578 | |
| 579 | #define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_MAN_C1_A0_LSB (0) |
| 580 | #define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_MAN_C1_A0_WIDTH (7) |
| 581 | #define RXDFE_FC_SW_DAGC_C1_A0_SW_DAGC_MAN_C1_A0_MASK (0x0000007F) |
| 582 | |
| 583 | #define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_EXP_C1_A0_LSB (8) |
| 584 | #define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_EXP_C1_A0_WIDTH (5) |
| 585 | #define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_EXP_C1_A0_MASK (0x00001F00) |
| 586 | |
| 587 | #define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_MAN_C1_A0_LSB (0) |
| 588 | #define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_MAN_C1_A0_WIDTH (7) |
| 589 | #define RXDFE_FC_SW_CS_DAGC_C1_A0_SW_CS_DAGC_MAN_C1_A0_MASK (0x0000007F) |
| 590 | |
| 591 | #define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0_SW_NCO_LNA_COMP_C1_A0_LSB (0) |
| 592 | #define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0_SW_NCO_LNA_COMP_C1_A0_WIDTH (23) |
| 593 | #define RXDFE_FC_SW_NCO_LNA_COMP_C1_A0_SW_NCO_LNA_COMP_C1_A0_MASK (0x007FFFFF) |
| 594 | |
| 595 | #define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_LSB (22) |
| 596 | #define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_WIDTH (1) |
| 597 | #define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_MASK (0x00400000) |
| 598 | #define RXDFE_FC_C_CON_C1_A1_SW_NCO_LNA_COMP_EN_C1_A1_BIT (0x00400000) |
| 599 | |
| 600 | #define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_LSB (21) |
| 601 | #define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_WIDTH (1) |
| 602 | #define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_MASK (0x00200000) |
| 603 | #define RXDFE_FC_C_CON_C1_A1_SW_DAGC_EN_C1_A1_BIT (0x00200000) |
| 604 | |
| 605 | #define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_LSB (20) |
| 606 | #define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_WIDTH (1) |
| 607 | #define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_MASK (0x00100000) |
| 608 | #define RXDFE_FC_C_CON_C1_A1_SW_CS_DAGC_EN_C1_A1_BIT (0x00100000) |
| 609 | |
| 610 | #define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_LSB (13) |
| 611 | #define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_WIDTH (1) |
| 612 | #define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_MASK (0x00002000) |
| 613 | #define RXDFE_FC_C_CON_C1_A1_C_NCO_MBSFN_EN_C1_A1_BIT (0x00002000) |
| 614 | |
| 615 | #define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_LSB (12) |
| 616 | #define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_WIDTH (1) |
| 617 | #define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_MASK (0x00001000) |
| 618 | #define RXDFE_FC_C_CON_C1_A1_C_NCO_EN_C1_A1_BIT (0x00001000) |
| 619 | |
| 620 | #define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_LSB (8) |
| 621 | #define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_WIDTH (1) |
| 622 | #define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_MASK (0x00000100) |
| 623 | #define RXDFE_FC_C_CON_C1_A1_MU_GEN_C2K_MODE_C1_A1_BIT (0x00000100) |
| 624 | |
| 625 | #define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_LSB (4) |
| 626 | #define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_WIDTH (1) |
| 627 | #define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_MASK (0x00000010) |
| 628 | #define RXDFE_FC_C_CON_C1_A1_C_IN_SEL_C1_A1_BIT (0x00000010) |
| 629 | |
| 630 | #define RXDFE_FC_C_CON_C1_A1_C_MODE_C1_A1_LSB (0) |
| 631 | #define RXDFE_FC_C_CON_C1_A1_C_MODE_C1_A1_WIDTH (4) |
| 632 | #define RXDFE_FC_C_CON_C1_A1_C_MODE_C1_A1_MASK (0x0000000F) |
| 633 | |
| 634 | #define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_EXP_C1_A1_LSB (8) |
| 635 | #define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_EXP_C1_A1_WIDTH (5) |
| 636 | #define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_EXP_C1_A1_MASK (0x00001F00) |
| 637 | |
| 638 | #define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_MAN_C1_A1_LSB (0) |
| 639 | #define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_MAN_C1_A1_WIDTH (7) |
| 640 | #define RXDFE_FC_SW_DAGC_C1_A1_SW_DAGC_MAN_C1_A1_MASK (0x0000007F) |
| 641 | |
| 642 | #define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_EXP_C1_A1_LSB (8) |
| 643 | #define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_EXP_C1_A1_WIDTH (5) |
| 644 | #define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_EXP_C1_A1_MASK (0x00001F00) |
| 645 | |
| 646 | #define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_MAN_C1_A1_LSB (0) |
| 647 | #define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_MAN_C1_A1_WIDTH (7) |
| 648 | #define RXDFE_FC_SW_CS_DAGC_C1_A1_SW_CS_DAGC_MAN_C1_A1_MASK (0x0000007F) |
| 649 | |
| 650 | #define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1_SW_NCO_LNA_COMP_C1_A1_LSB (0) |
| 651 | #define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1_SW_NCO_LNA_COMP_C1_A1_WIDTH (23) |
| 652 | #define RXDFE_FC_SW_NCO_LNA_COMP_C1_A1_SW_NCO_LNA_COMP_C1_A1_MASK (0x007FFFFF) |
| 653 | |
| 654 | #define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_1_P0_A0_LSB (16) |
| 655 | #define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_1_P0_A0_WIDTH (11) |
| 656 | #define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_1_P0_A0_MASK (0x07FF0000) |
| 657 | |
| 658 | #define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_0_P0_A0_LSB (0) |
| 659 | #define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_0_P0_A0_WIDTH (11) |
| 660 | #define RXDFE_FC_FDPM_0_P0_A0_FDPM_COEF_Q_0_P0_A0_MASK (0x000007FF) |
| 661 | |
| 662 | #define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_3_P0_A0_LSB (16) |
| 663 | #define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_3_P0_A0_WIDTH (11) |
| 664 | #define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_3_P0_A0_MASK (0x07FF0000) |
| 665 | |
| 666 | #define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_2_P0_A0_LSB (0) |
| 667 | #define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_2_P0_A0_WIDTH (11) |
| 668 | #define RXDFE_FC_FDPM_1_P0_A0_FDPM_COEF_Q_2_P0_A0_MASK (0x000007FF) |
| 669 | |
| 670 | #define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_LSB (31) |
| 671 | #define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_WIDTH (1) |
| 672 | #define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_MASK (0x80000000) |
| 673 | #define RXDFE_FC_FDPM_2_P0_A0_FDPM_EN_P0_A0_BIT (0x80000000) |
| 674 | |
| 675 | #define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_LSB (28) |
| 676 | #define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_WIDTH (1) |
| 677 | #define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_MASK (0x10000000) |
| 678 | #define RXDFE_FC_FDPM_2_P0_A0_FDPM_TAP_SEL_P0_A0_BIT (0x10000000) |
| 679 | |
| 680 | #define RXDFE_FC_FDPM_2_P0_A0_FDPM_COEF_Q_4_P0_A0_LSB (0) |
| 681 | #define RXDFE_FC_FDPM_2_P0_A0_FDPM_COEF_Q_4_P0_A0_WIDTH (11) |
| 682 | #define RXDFE_FC_FDPM_2_P0_A0_FDPM_COEF_Q_4_P0_A0_MASK (0x000007FF) |
| 683 | |
| 684 | #define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_02_P0_A0_LSB (20) |
| 685 | #define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_02_P0_A0_WIDTH (9) |
| 686 | #define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_02_P0_A0_MASK (0x1FF00000) |
| 687 | |
| 688 | #define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_01_P0_A0_LSB (10) |
| 689 | #define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_01_P0_A0_WIDTH (9) |
| 690 | #define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_01_P0_A0_MASK (0x0007FC00) |
| 691 | |
| 692 | #define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_00_P0_A0_LSB (0) |
| 693 | #define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_00_P0_A0_WIDTH (9) |
| 694 | #define RXDFE_FC_RFEQ_0_P0_A0_RFEQ_COEF_00_P0_A0_MASK (0x000001FF) |
| 695 | |
| 696 | #define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_05_P0_A0_LSB (20) |
| 697 | #define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_05_P0_A0_WIDTH (9) |
| 698 | #define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_05_P0_A0_MASK (0x1FF00000) |
| 699 | |
| 700 | #define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_04_P0_A0_LSB (10) |
| 701 | #define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_04_P0_A0_WIDTH (9) |
| 702 | #define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_04_P0_A0_MASK (0x0007FC00) |
| 703 | |
| 704 | #define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_03_P0_A0_LSB (0) |
| 705 | #define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_03_P0_A0_WIDTH (9) |
| 706 | #define RXDFE_FC_RFEQ_1_P0_A0_RFEQ_COEF_03_P0_A0_MASK (0x000001FF) |
| 707 | |
| 708 | #define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_08_P0_A0_LSB (20) |
| 709 | #define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_08_P0_A0_WIDTH (9) |
| 710 | #define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_08_P0_A0_MASK (0x1FF00000) |
| 711 | |
| 712 | #define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_07_P0_A0_LSB (10) |
| 713 | #define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_07_P0_A0_WIDTH (9) |
| 714 | #define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_07_P0_A0_MASK (0x0007FC00) |
| 715 | |
| 716 | #define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_06_P0_A0_LSB (0) |
| 717 | #define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_06_P0_A0_WIDTH (9) |
| 718 | #define RXDFE_FC_RFEQ_2_P0_A0_RFEQ_COEF_06_P0_A0_MASK (0x000001FF) |
| 719 | |
| 720 | #define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_11_P0_A0_LSB (20) |
| 721 | #define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_11_P0_A0_WIDTH (9) |
| 722 | #define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_11_P0_A0_MASK (0x1FF00000) |
| 723 | |
| 724 | #define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_10_P0_A0_LSB (10) |
| 725 | #define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_10_P0_A0_WIDTH (9) |
| 726 | #define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_10_P0_A0_MASK (0x0007FC00) |
| 727 | |
| 728 | #define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_09_P0_A0_LSB (0) |
| 729 | #define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_09_P0_A0_WIDTH (9) |
| 730 | #define RXDFE_FC_RFEQ_3_P0_A0_RFEQ_COEF_09_P0_A0_MASK (0x000001FF) |
| 731 | |
| 732 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_LSB (31) |
| 733 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_WIDTH (1) |
| 734 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_MASK (0x80000000) |
| 735 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_EN_P0_A0_BIT (0x80000000) |
| 736 | |
| 737 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_LSB (30) |
| 738 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_WIDTH (1) |
| 739 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_MASK (0x40000000) |
| 740 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_TAP_SEL_P0_A0_BIT (0x40000000) |
| 741 | |
| 742 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_RND_SEL_P0_A0_LSB (28) |
| 743 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_RND_SEL_P0_A0_WIDTH (2) |
| 744 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_RND_SEL_P0_A0_MASK (0x30000000) |
| 745 | |
| 746 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_13_P0_A0_LSB (10) |
| 747 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_13_P0_A0_WIDTH (9) |
| 748 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_13_P0_A0_MASK (0x0007FC00) |
| 749 | |
| 750 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_12_P0_A0_LSB (0) |
| 751 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_12_P0_A0_WIDTH (9) |
| 752 | #define RXDFE_FC_RFEQ_4_P0_A0_RFEQ_COEF_12_P0_A0_MASK (0x000001FF) |
| 753 | |
| 754 | #define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_LSB (31) |
| 755 | #define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_WIDTH (1) |
| 756 | #define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_MASK (0x80000000) |
| 757 | #define RXDFE_FC_IQC_P0_A0_IQC_EN_P0_A0_BIT (0x80000000) |
| 758 | |
| 759 | #define RXDFE_FC_IQC_P0_A0_IQC_PHASE_P0_A0_LSB (8) |
| 760 | #define RXDFE_FC_IQC_P0_A0_IQC_PHASE_P0_A0_WIDTH (7) |
| 761 | #define RXDFE_FC_IQC_P0_A0_IQC_PHASE_P0_A0_MASK (0x00007F00) |
| 762 | |
| 763 | #define RXDFE_FC_IQC_P0_A0_IQC_GAIN_P0_A0_LSB (0) |
| 764 | #define RXDFE_FC_IQC_P0_A0_IQC_GAIN_P0_A0_WIDTH (8) |
| 765 | #define RXDFE_FC_IQC_P0_A0_IQC_GAIN_P0_A0_MASK (0x000000FF) |
| 766 | |
| 767 | #define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_1_P0_A1_LSB (16) |
| 768 | #define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_1_P0_A1_WIDTH (11) |
| 769 | #define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_1_P0_A1_MASK (0x07FF0000) |
| 770 | |
| 771 | #define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_0_P0_A1_LSB (0) |
| 772 | #define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_0_P0_A1_WIDTH (11) |
| 773 | #define RXDFE_FC_FDPM_0_P0_A1_FDPM_COEF_Q_0_P0_A1_MASK (0x000007FF) |
| 774 | |
| 775 | #define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_3_P0_A1_LSB (16) |
| 776 | #define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_3_P0_A1_WIDTH (11) |
| 777 | #define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_3_P0_A1_MASK (0x07FF0000) |
| 778 | |
| 779 | #define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_2_P0_A1_LSB (0) |
| 780 | #define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_2_P0_A1_WIDTH (11) |
| 781 | #define RXDFE_FC_FDPM_1_P0_A1_FDPM_COEF_Q_2_P0_A1_MASK (0x000007FF) |
| 782 | |
| 783 | #define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_LSB (31) |
| 784 | #define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_WIDTH (1) |
| 785 | #define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_MASK (0x80000000) |
| 786 | #define RXDFE_FC_FDPM_2_P0_A1_FDPM_EN_P0_A1_BIT (0x80000000) |
| 787 | |
| 788 | #define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_LSB (28) |
| 789 | #define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_WIDTH (1) |
| 790 | #define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_MASK (0x10000000) |
| 791 | #define RXDFE_FC_FDPM_2_P0_A1_FDPM_TAP_SEL_P0_A1_BIT (0x10000000) |
| 792 | |
| 793 | #define RXDFE_FC_FDPM_2_P0_A1_FDPM_COEF_Q_4_P0_A1_LSB (0) |
| 794 | #define RXDFE_FC_FDPM_2_P0_A1_FDPM_COEF_Q_4_P0_A1_WIDTH (11) |
| 795 | #define RXDFE_FC_FDPM_2_P0_A1_FDPM_COEF_Q_4_P0_A1_MASK (0x000007FF) |
| 796 | |
| 797 | #define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_02_P0_A1_LSB (20) |
| 798 | #define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_02_P0_A1_WIDTH (9) |
| 799 | #define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_02_P0_A1_MASK (0x1FF00000) |
| 800 | |
| 801 | #define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_01_P0_A1_LSB (10) |
| 802 | #define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_01_P0_A1_WIDTH (9) |
| 803 | #define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_01_P0_A1_MASK (0x0007FC00) |
| 804 | |
| 805 | #define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_00_P0_A1_LSB (0) |
| 806 | #define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_00_P0_A1_WIDTH (9) |
| 807 | #define RXDFE_FC_RFEQ_0_P0_A1_RFEQ_COEF_00_P0_A1_MASK (0x000001FF) |
| 808 | |
| 809 | #define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_05_P0_A1_LSB (20) |
| 810 | #define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_05_P0_A1_WIDTH (9) |
| 811 | #define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_05_P0_A1_MASK (0x1FF00000) |
| 812 | |
| 813 | #define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_04_P0_A1_LSB (10) |
| 814 | #define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_04_P0_A1_WIDTH (9) |
| 815 | #define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_04_P0_A1_MASK (0x0007FC00) |
| 816 | |
| 817 | #define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_03_P0_A1_LSB (0) |
| 818 | #define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_03_P0_A1_WIDTH (9) |
| 819 | #define RXDFE_FC_RFEQ_1_P0_A1_RFEQ_COEF_03_P0_A1_MASK (0x000001FF) |
| 820 | |
| 821 | #define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_08_P0_A1_LSB (20) |
| 822 | #define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_08_P0_A1_WIDTH (9) |
| 823 | #define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_08_P0_A1_MASK (0x1FF00000) |
| 824 | |
| 825 | #define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_07_P0_A1_LSB (10) |
| 826 | #define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_07_P0_A1_WIDTH (9) |
| 827 | #define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_07_P0_A1_MASK (0x0007FC00) |
| 828 | |
| 829 | #define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_06_P0_A1_LSB (0) |
| 830 | #define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_06_P0_A1_WIDTH (9) |
| 831 | #define RXDFE_FC_RFEQ_2_P0_A1_RFEQ_COEF_06_P0_A1_MASK (0x000001FF) |
| 832 | |
| 833 | #define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_11_P0_A1_LSB (20) |
| 834 | #define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_11_P0_A1_WIDTH (9) |
| 835 | #define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_11_P0_A1_MASK (0x1FF00000) |
| 836 | |
| 837 | #define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_10_P0_A1_LSB (10) |
| 838 | #define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_10_P0_A1_WIDTH (9) |
| 839 | #define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_10_P0_A1_MASK (0x0007FC00) |
| 840 | |
| 841 | #define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_09_P0_A1_LSB (0) |
| 842 | #define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_09_P0_A1_WIDTH (9) |
| 843 | #define RXDFE_FC_RFEQ_3_P0_A1_RFEQ_COEF_09_P0_A1_MASK (0x000001FF) |
| 844 | |
| 845 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_LSB (31) |
| 846 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_WIDTH (1) |
| 847 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_MASK (0x80000000) |
| 848 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_EN_P0_A1_BIT (0x80000000) |
| 849 | |
| 850 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_LSB (30) |
| 851 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_WIDTH (1) |
| 852 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_MASK (0x40000000) |
| 853 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_TAP_SEL_P0_A1_BIT (0x40000000) |
| 854 | |
| 855 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_RND_SEL_P0_A1_LSB (28) |
| 856 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_RND_SEL_P0_A1_WIDTH (2) |
| 857 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_RND_SEL_P0_A1_MASK (0x30000000) |
| 858 | |
| 859 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_13_P0_A1_LSB (10) |
| 860 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_13_P0_A1_WIDTH (9) |
| 861 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_13_P0_A1_MASK (0x0007FC00) |
| 862 | |
| 863 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_12_P0_A1_LSB (0) |
| 864 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_12_P0_A1_WIDTH (9) |
| 865 | #define RXDFE_FC_RFEQ_4_P0_A1_RFEQ_COEF_12_P0_A1_MASK (0x000001FF) |
| 866 | |
| 867 | #define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_LSB (31) |
| 868 | #define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_WIDTH (1) |
| 869 | #define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_MASK (0x80000000) |
| 870 | #define RXDFE_FC_IQC_P0_A1_IQC_EN_P0_A1_BIT (0x80000000) |
| 871 | |
| 872 | #define RXDFE_FC_IQC_P0_A1_IQC_PHASE_P0_A1_LSB (8) |
| 873 | #define RXDFE_FC_IQC_P0_A1_IQC_PHASE_P0_A1_WIDTH (7) |
| 874 | #define RXDFE_FC_IQC_P0_A1_IQC_PHASE_P0_A1_MASK (0x00007F00) |
| 875 | |
| 876 | #define RXDFE_FC_IQC_P0_A1_IQC_GAIN_P0_A1_LSB (0) |
| 877 | #define RXDFE_FC_IQC_P0_A1_IQC_GAIN_P0_A1_WIDTH (8) |
| 878 | #define RXDFE_FC_IQC_P0_A1_IQC_GAIN_P0_A1_MASK (0x000000FF) |
| 879 | |
| 880 | #define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_1_P1_A0_LSB (16) |
| 881 | #define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_1_P1_A0_WIDTH (11) |
| 882 | #define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_1_P1_A0_MASK (0x07FF0000) |
| 883 | |
| 884 | #define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_0_P1_A0_LSB (0) |
| 885 | #define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_0_P1_A0_WIDTH (11) |
| 886 | #define RXDFE_FC_FDPM_0_P1_A0_FDPM_COEF_Q_0_P1_A0_MASK (0x000007FF) |
| 887 | |
| 888 | #define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_3_P1_A0_LSB (16) |
| 889 | #define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_3_P1_A0_WIDTH (11) |
| 890 | #define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_3_P1_A0_MASK (0x07FF0000) |
| 891 | |
| 892 | #define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_2_P1_A0_LSB (0) |
| 893 | #define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_2_P1_A0_WIDTH (11) |
| 894 | #define RXDFE_FC_FDPM_1_P1_A0_FDPM_COEF_Q_2_P1_A0_MASK (0x000007FF) |
| 895 | |
| 896 | #define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_LSB (31) |
| 897 | #define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_WIDTH (1) |
| 898 | #define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_MASK (0x80000000) |
| 899 | #define RXDFE_FC_FDPM_2_P1_A0_FDPM_EN_P1_A0_BIT (0x80000000) |
| 900 | |
| 901 | #define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_LSB (28) |
| 902 | #define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_WIDTH (1) |
| 903 | #define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_MASK (0x10000000) |
| 904 | #define RXDFE_FC_FDPM_2_P1_A0_FDPM_TAP_SEL_P1_A0_BIT (0x10000000) |
| 905 | |
| 906 | #define RXDFE_FC_FDPM_2_P1_A0_FDPM_COEF_Q_4_P1_A0_LSB (0) |
| 907 | #define RXDFE_FC_FDPM_2_P1_A0_FDPM_COEF_Q_4_P1_A0_WIDTH (11) |
| 908 | #define RXDFE_FC_FDPM_2_P1_A0_FDPM_COEF_Q_4_P1_A0_MASK (0x000007FF) |
| 909 | |
| 910 | #define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_02_P1_A0_LSB (20) |
| 911 | #define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_02_P1_A0_WIDTH (9) |
| 912 | #define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_02_P1_A0_MASK (0x1FF00000) |
| 913 | |
| 914 | #define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_01_P1_A0_LSB (10) |
| 915 | #define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_01_P1_A0_WIDTH (9) |
| 916 | #define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_01_P1_A0_MASK (0x0007FC00) |
| 917 | |
| 918 | #define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_00_P1_A0_LSB (0) |
| 919 | #define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_00_P1_A0_WIDTH (9) |
| 920 | #define RXDFE_FC_RFEQ_0_P1_A0_RFEQ_COEF_00_P1_A0_MASK (0x000001FF) |
| 921 | |
| 922 | #define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_05_P1_A0_LSB (20) |
| 923 | #define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_05_P1_A0_WIDTH (9) |
| 924 | #define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_05_P1_A0_MASK (0x1FF00000) |
| 925 | |
| 926 | #define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_04_P1_A0_LSB (10) |
| 927 | #define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_04_P1_A0_WIDTH (9) |
| 928 | #define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_04_P1_A0_MASK (0x0007FC00) |
| 929 | |
| 930 | #define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_03_P1_A0_LSB (0) |
| 931 | #define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_03_P1_A0_WIDTH (9) |
| 932 | #define RXDFE_FC_RFEQ_1_P1_A0_RFEQ_COEF_03_P1_A0_MASK (0x000001FF) |
| 933 | |
| 934 | #define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_08_P1_A0_LSB (20) |
| 935 | #define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_08_P1_A0_WIDTH (9) |
| 936 | #define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_08_P1_A0_MASK (0x1FF00000) |
| 937 | |
| 938 | #define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_07_P1_A0_LSB (10) |
| 939 | #define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_07_P1_A0_WIDTH (9) |
| 940 | #define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_07_P1_A0_MASK (0x0007FC00) |
| 941 | |
| 942 | #define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_06_P1_A0_LSB (0) |
| 943 | #define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_06_P1_A0_WIDTH (9) |
| 944 | #define RXDFE_FC_RFEQ_2_P1_A0_RFEQ_COEF_06_P1_A0_MASK (0x000001FF) |
| 945 | |
| 946 | #define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_11_P1_A0_LSB (20) |
| 947 | #define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_11_P1_A0_WIDTH (9) |
| 948 | #define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_11_P1_A0_MASK (0x1FF00000) |
| 949 | |
| 950 | #define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_10_P1_A0_LSB (10) |
| 951 | #define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_10_P1_A0_WIDTH (9) |
| 952 | #define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_10_P1_A0_MASK (0x0007FC00) |
| 953 | |
| 954 | #define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_09_P1_A0_LSB (0) |
| 955 | #define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_09_P1_A0_WIDTH (9) |
| 956 | #define RXDFE_FC_RFEQ_3_P1_A0_RFEQ_COEF_09_P1_A0_MASK (0x000001FF) |
| 957 | |
| 958 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_LSB (31) |
| 959 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_WIDTH (1) |
| 960 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_MASK (0x80000000) |
| 961 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_EN_P1_A0_BIT (0x80000000) |
| 962 | |
| 963 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_LSB (30) |
| 964 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_WIDTH (1) |
| 965 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_MASK (0x40000000) |
| 966 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_TAP_SEL_P1_A0_BIT (0x40000000) |
| 967 | |
| 968 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_RND_SEL_P1_A0_LSB (28) |
| 969 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_RND_SEL_P1_A0_WIDTH (2) |
| 970 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_RND_SEL_P1_A0_MASK (0x30000000) |
| 971 | |
| 972 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_13_P1_A0_LSB (10) |
| 973 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_13_P1_A0_WIDTH (9) |
| 974 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_13_P1_A0_MASK (0x0007FC00) |
| 975 | |
| 976 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_12_P1_A0_LSB (0) |
| 977 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_12_P1_A0_WIDTH (9) |
| 978 | #define RXDFE_FC_RFEQ_4_P1_A0_RFEQ_COEF_12_P1_A0_MASK (0x000001FF) |
| 979 | |
| 980 | #define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_LSB (31) |
| 981 | #define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_WIDTH (1) |
| 982 | #define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_MASK (0x80000000) |
| 983 | #define RXDFE_FC_IQC_P1_A0_IQC_EN_P1_A0_BIT (0x80000000) |
| 984 | |
| 985 | #define RXDFE_FC_IQC_P1_A0_IQC_PHASE_P1_A0_LSB (8) |
| 986 | #define RXDFE_FC_IQC_P1_A0_IQC_PHASE_P1_A0_WIDTH (7) |
| 987 | #define RXDFE_FC_IQC_P1_A0_IQC_PHASE_P1_A0_MASK (0x00007F00) |
| 988 | |
| 989 | #define RXDFE_FC_IQC_P1_A0_IQC_GAIN_P1_A0_LSB (0) |
| 990 | #define RXDFE_FC_IQC_P1_A0_IQC_GAIN_P1_A0_WIDTH (8) |
| 991 | #define RXDFE_FC_IQC_P1_A0_IQC_GAIN_P1_A0_MASK (0x000000FF) |
| 992 | |
| 993 | #define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_1_P1_A1_LSB (16) |
| 994 | #define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_1_P1_A1_WIDTH (11) |
| 995 | #define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_1_P1_A1_MASK (0x07FF0000) |
| 996 | |
| 997 | #define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_0_P1_A1_LSB (0) |
| 998 | #define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_0_P1_A1_WIDTH (11) |
| 999 | #define RXDFE_FC_FDPM_0_P1_A1_FDPM_COEF_Q_0_P1_A1_MASK (0x000007FF) |
| 1000 | |
| 1001 | #define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_3_P1_A1_LSB (16) |
| 1002 | #define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_3_P1_A1_WIDTH (11) |
| 1003 | #define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_3_P1_A1_MASK (0x07FF0000) |
| 1004 | |
| 1005 | #define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_2_P1_A1_LSB (0) |
| 1006 | #define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_2_P1_A1_WIDTH (11) |
| 1007 | #define RXDFE_FC_FDPM_1_P1_A1_FDPM_COEF_Q_2_P1_A1_MASK (0x000007FF) |
| 1008 | |
| 1009 | #define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_LSB (31) |
| 1010 | #define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_WIDTH (1) |
| 1011 | #define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_MASK (0x80000000) |
| 1012 | #define RXDFE_FC_FDPM_2_P1_A1_FDPM_EN_P1_A1_BIT (0x80000000) |
| 1013 | |
| 1014 | #define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_LSB (28) |
| 1015 | #define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_WIDTH (1) |
| 1016 | #define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_MASK (0x10000000) |
| 1017 | #define RXDFE_FC_FDPM_2_P1_A1_FDPM_TAP_SEL_P1_A1_BIT (0x10000000) |
| 1018 | |
| 1019 | #define RXDFE_FC_FDPM_2_P1_A1_FDPM_COEF_Q_4_P1_A1_LSB (0) |
| 1020 | #define RXDFE_FC_FDPM_2_P1_A1_FDPM_COEF_Q_4_P1_A1_WIDTH (11) |
| 1021 | #define RXDFE_FC_FDPM_2_P1_A1_FDPM_COEF_Q_4_P1_A1_MASK (0x000007FF) |
| 1022 | |
| 1023 | #define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_02_P1_A1_LSB (20) |
| 1024 | #define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_02_P1_A1_WIDTH (9) |
| 1025 | #define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_02_P1_A1_MASK (0x1FF00000) |
| 1026 | |
| 1027 | #define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_01_P1_A1_LSB (10) |
| 1028 | #define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_01_P1_A1_WIDTH (9) |
| 1029 | #define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_01_P1_A1_MASK (0x0007FC00) |
| 1030 | |
| 1031 | #define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_00_P1_A1_LSB (0) |
| 1032 | #define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_00_P1_A1_WIDTH (9) |
| 1033 | #define RXDFE_FC_RFEQ_0_P1_A1_RFEQ_COEF_00_P1_A1_MASK (0x000001FF) |
| 1034 | |
| 1035 | #define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_05_P1_A1_LSB (20) |
| 1036 | #define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_05_P1_A1_WIDTH (9) |
| 1037 | #define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_05_P1_A1_MASK (0x1FF00000) |
| 1038 | |
| 1039 | #define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_04_P1_A1_LSB (10) |
| 1040 | #define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_04_P1_A1_WIDTH (9) |
| 1041 | #define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_04_P1_A1_MASK (0x0007FC00) |
| 1042 | |
| 1043 | #define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_03_P1_A1_LSB (0) |
| 1044 | #define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_03_P1_A1_WIDTH (9) |
| 1045 | #define RXDFE_FC_RFEQ_1_P1_A1_RFEQ_COEF_03_P1_A1_MASK (0x000001FF) |
| 1046 | |
| 1047 | #define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_08_P1_A1_LSB (20) |
| 1048 | #define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_08_P1_A1_WIDTH (9) |
| 1049 | #define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_08_P1_A1_MASK (0x1FF00000) |
| 1050 | |
| 1051 | #define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_07_P1_A1_LSB (10) |
| 1052 | #define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_07_P1_A1_WIDTH (9) |
| 1053 | #define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_07_P1_A1_MASK (0x0007FC00) |
| 1054 | |
| 1055 | #define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_06_P1_A1_LSB (0) |
| 1056 | #define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_06_P1_A1_WIDTH (9) |
| 1057 | #define RXDFE_FC_RFEQ_2_P1_A1_RFEQ_COEF_06_P1_A1_MASK (0x000001FF) |
| 1058 | |
| 1059 | #define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_11_P1_A1_LSB (20) |
| 1060 | #define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_11_P1_A1_WIDTH (9) |
| 1061 | #define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_11_P1_A1_MASK (0x1FF00000) |
| 1062 | |
| 1063 | #define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_10_P1_A1_LSB (10) |
| 1064 | #define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_10_P1_A1_WIDTH (9) |
| 1065 | #define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_10_P1_A1_MASK (0x0007FC00) |
| 1066 | |
| 1067 | #define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_09_P1_A1_LSB (0) |
| 1068 | #define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_09_P1_A1_WIDTH (9) |
| 1069 | #define RXDFE_FC_RFEQ_3_P1_A1_RFEQ_COEF_09_P1_A1_MASK (0x000001FF) |
| 1070 | |
| 1071 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_LSB (31) |
| 1072 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_WIDTH (1) |
| 1073 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_MASK (0x80000000) |
| 1074 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_EN_P1_A1_BIT (0x80000000) |
| 1075 | |
| 1076 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_LSB (30) |
| 1077 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_WIDTH (1) |
| 1078 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_MASK (0x40000000) |
| 1079 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_TAP_SEL_P1_A1_BIT (0x40000000) |
| 1080 | |
| 1081 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_RND_SEL_P1_A1_LSB (28) |
| 1082 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_RND_SEL_P1_A1_WIDTH (2) |
| 1083 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_RND_SEL_P1_A1_MASK (0x30000000) |
| 1084 | |
| 1085 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_13_P1_A1_LSB (10) |
| 1086 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_13_P1_A1_WIDTH (9) |
| 1087 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_13_P1_A1_MASK (0x0007FC00) |
| 1088 | |
| 1089 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_12_P1_A1_LSB (0) |
| 1090 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_12_P1_A1_WIDTH (9) |
| 1091 | #define RXDFE_FC_RFEQ_4_P1_A1_RFEQ_COEF_12_P1_A1_MASK (0x000001FF) |
| 1092 | |
| 1093 | #define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_LSB (31) |
| 1094 | #define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_WIDTH (1) |
| 1095 | #define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_MASK (0x80000000) |
| 1096 | #define RXDFE_FC_IQC_P1_A1_IQC_EN_P1_A1_BIT (0x80000000) |
| 1097 | |
| 1098 | #define RXDFE_FC_IQC_P1_A1_IQC_PHASE_P1_A1_LSB (8) |
| 1099 | #define RXDFE_FC_IQC_P1_A1_IQC_PHASE_P1_A1_WIDTH (7) |
| 1100 | #define RXDFE_FC_IQC_P1_A1_IQC_PHASE_P1_A1_MASK (0x00007F00) |
| 1101 | |
| 1102 | #define RXDFE_FC_IQC_P1_A1_IQC_GAIN_P1_A1_LSB (0) |
| 1103 | #define RXDFE_FC_IQC_P1_A1_IQC_GAIN_P1_A1_WIDTH (8) |
| 1104 | #define RXDFE_FC_IQC_P1_A1_IQC_GAIN_P1_A1_MASK (0x000000FF) |
| 1105 | |
| 1106 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_Q_P0_A0_LSB (16) |
| 1107 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_Q_P0_A0_WIDTH (15) |
| 1108 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_Q_P0_A0_MASK (0x7FFF0000) |
| 1109 | |
| 1110 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_I_P0_A0_LSB (0) |
| 1111 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_I_P0_A0_WIDTH (15) |
| 1112 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A0_NBIF_SPUR_PARA_A_I_P0_A0_MASK (0x00007FFF) |
| 1113 | |
| 1114 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_LSB (31) |
| 1115 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_WIDTH (1) |
| 1116 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_MASK (0x80000000) |
| 1117 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_EN_P0_A0_BIT (0x80000000) |
| 1118 | |
| 1119 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_PARA_P_P0_A0_LSB (0) |
| 1120 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_PARA_P_P0_A0_WIDTH (3) |
| 1121 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A0_NBIF_SPUR_PARA_P_P0_A0_MASK (0x00000007) |
| 1122 | |
| 1123 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_Q_P0_A1_LSB (16) |
| 1124 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_Q_P0_A1_WIDTH (15) |
| 1125 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_Q_P0_A1_MASK (0x7FFF0000) |
| 1126 | |
| 1127 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_I_P0_A1_LSB (0) |
| 1128 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_I_P0_A1_WIDTH (15) |
| 1129 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P0_A1_NBIF_SPUR_PARA_A_I_P0_A1_MASK (0x00007FFF) |
| 1130 | |
| 1131 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_LSB (31) |
| 1132 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_WIDTH (1) |
| 1133 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_MASK (0x80000000) |
| 1134 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_EN_P0_A1_BIT (0x80000000) |
| 1135 | |
| 1136 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_PARA_P_P0_A1_LSB (0) |
| 1137 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_PARA_P_P0_A1_WIDTH (3) |
| 1138 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P0_A1_NBIF_SPUR_PARA_P_P0_A1_MASK (0x00000007) |
| 1139 | |
| 1140 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_Q_P1_A0_LSB (16) |
| 1141 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_Q_P1_A0_WIDTH (15) |
| 1142 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_Q_P1_A0_MASK (0x7FFF0000) |
| 1143 | |
| 1144 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_I_P1_A0_LSB (0) |
| 1145 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_I_P1_A0_WIDTH (15) |
| 1146 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A0_NBIF_SPUR_PARA_A_I_P1_A0_MASK (0x00007FFF) |
| 1147 | |
| 1148 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_LSB (31) |
| 1149 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_WIDTH (1) |
| 1150 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_MASK (0x80000000) |
| 1151 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_EN_P1_A0_BIT (0x80000000) |
| 1152 | |
| 1153 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_PARA_P_P1_A0_LSB (0) |
| 1154 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_PARA_P_P1_A0_WIDTH (3) |
| 1155 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A0_NBIF_SPUR_PARA_P_P1_A0_MASK (0x00000007) |
| 1156 | |
| 1157 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_Q_P1_A1_LSB (16) |
| 1158 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_Q_P1_A1_WIDTH (15) |
| 1159 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_Q_P1_A1_MASK (0x7FFF0000) |
| 1160 | |
| 1161 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_I_P1_A1_LSB (0) |
| 1162 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_I_P1_A1_WIDTH (15) |
| 1163 | #define RXDFE_FC_NBIF_SPUR_PARA_A_P1_A1_NBIF_SPUR_PARA_A_I_P1_A1_MASK (0x00007FFF) |
| 1164 | |
| 1165 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_LSB (31) |
| 1166 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_WIDTH (1) |
| 1167 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_MASK (0x80000000) |
| 1168 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_EN_P1_A1_BIT (0x80000000) |
| 1169 | |
| 1170 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_PARA_P_P1_A1_LSB (0) |
| 1171 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_PARA_P_P1_A1_WIDTH (3) |
| 1172 | #define RXDFE_FC_NBIF_SPUR_PARA_P_P1_A1_NBIF_SPUR_PARA_P_P1_A1_MASK (0x00000007) |
| 1173 | |
| 1174 | #define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_LSB (31) |
| 1175 | #define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_WIDTH (1) |
| 1176 | #define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_MASK (0x80000000) |
| 1177 | #define RXDFE_FC_NCO_C0_A0_NCO_EN_C0_A0_BIT (0x80000000) |
| 1178 | |
| 1179 | #define RXDFE_FC_NCO_C0_A0_NCO_PHASE_STEP_C0_A0_LSB (0) |
| 1180 | #define RXDFE_FC_NCO_C0_A0_NCO_PHASE_STEP_C0_A0_WIDTH (23) |
| 1181 | #define RXDFE_FC_NCO_C0_A0_NCO_PHASE_STEP_C0_A0_MASK (0x007FFFFF) |
| 1182 | |
| 1183 | #define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_LSB (31) |
| 1184 | #define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_WIDTH (1) |
| 1185 | #define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_MASK (0x80000000) |
| 1186 | #define RXDFE_FC_NCO_C0_A1_NCO_EN_C0_A1_BIT (0x80000000) |
| 1187 | |
| 1188 | #define RXDFE_FC_NCO_C0_A1_NCO_PHASE_STEP_C0_A1_LSB (0) |
| 1189 | #define RXDFE_FC_NCO_C0_A1_NCO_PHASE_STEP_C0_A1_WIDTH (23) |
| 1190 | #define RXDFE_FC_NCO_C0_A1_NCO_PHASE_STEP_C0_A1_MASK (0x007FFFFF) |
| 1191 | |
| 1192 | #define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_LSB (31) |
| 1193 | #define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_WIDTH (1) |
| 1194 | #define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_MASK (0x80000000) |
| 1195 | #define RXDFE_FC_NCO_C1_A0_NCO_EN_C1_A0_BIT (0x80000000) |
| 1196 | |
| 1197 | #define RXDFE_FC_NCO_C1_A0_NCO_PHASE_STEP_C1_A0_LSB (0) |
| 1198 | #define RXDFE_FC_NCO_C1_A0_NCO_PHASE_STEP_C1_A0_WIDTH (23) |
| 1199 | #define RXDFE_FC_NCO_C1_A0_NCO_PHASE_STEP_C1_A0_MASK (0x007FFFFF) |
| 1200 | |
| 1201 | #define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_LSB (31) |
| 1202 | #define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_WIDTH (1) |
| 1203 | #define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_MASK (0x80000000) |
| 1204 | #define RXDFE_FC_NCO_C1_A1_NCO_EN_C1_A1_BIT (0x80000000) |
| 1205 | |
| 1206 | #define RXDFE_FC_NCO_C1_A1_NCO_PHASE_STEP_C1_A1_LSB (0) |
| 1207 | #define RXDFE_FC_NCO_C1_A1_NCO_PHASE_STEP_C1_A1_WIDTH (23) |
| 1208 | #define RXDFE_FC_NCO_C1_A1_NCO_PHASE_STEP_C1_A1_MASK (0x007FFFFF) |
| 1209 | |
| 1210 | #define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_LSB (31) |
| 1211 | #define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_WIDTH (1) |
| 1212 | #define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_MASK (0x80000000) |
| 1213 | #define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_EN_C0_BIT (0x80000000) |
| 1214 | |
| 1215 | #define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_PHASE_STEP_C0_LSB (0) |
| 1216 | #define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_PHASE_STEP_C0_WIDTH (23) |
| 1217 | #define RXDFE_FC_NCO_MBSFN_C0_NCO_MBSFN_PHASE_STEP_C0_MASK (0x007FFFFF) |
| 1218 | |
| 1219 | #define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_LSB (31) |
| 1220 | #define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_WIDTH (1) |
| 1221 | #define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_MASK (0x80000000) |
| 1222 | #define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_EN_C1_BIT (0x80000000) |
| 1223 | |
| 1224 | #define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_PHASE_STEP_C1_LSB (0) |
| 1225 | #define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_PHASE_STEP_C1_WIDTH (23) |
| 1226 | #define RXDFE_FC_NCO_MBSFN_C1_NCO_MBSFN_PHASE_STEP_C1_MASK (0x007FFFFF) |
| 1227 | |
| 1228 | |
| 1229 | #endif //#ifndef _CPH_C2K_RXDFE_H_ |