Blame - mcu/interface/l1/cl1/common/HW/cphdfesysglbconfigreg1.h - T800_MD

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/*****************************************************************************

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* Copyright Statement:

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* --------------------

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* This software is protected by Copyright and the information contained

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* herein is confidential. The software may not be copied and the information

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* contained herein may not be used or disclosed except with the written

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*

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* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES

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* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")

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* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON

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* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,

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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF

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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.

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* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE

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* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR

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* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH

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* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO

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* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S

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* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.

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*

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* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE

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* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,

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* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,

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* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO

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* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.

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*

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* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE

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* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF

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* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND

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* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER

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* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).

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*

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*****************************************************************************/

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#ifndef _CPH_DFESYS_GLBCON_CONFIG1_H_

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#define _CPH_DFESYS_GLBCON_CONFIG1_H_

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typedef volatile unsigned short* SRAMADDR; /* SRAM addr is 16 bits */

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typedef volatile unsigned short SRAMDATA; /* SRAM data is 16 bits */

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typedef volatile unsigned short* APBADDR; /* APB addr is 16 bits */

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typedef volatile unsigned short APBDATA; /* APB data is 16 bits */

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typedef volatile unsigned long* APBADDR32; /* APB addr is 32 bits */

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typedef volatile unsigned long APBDATA32; /* APB data is 32 bits */

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typedef volatile unsigned short* DPRAMADDR; /* DPRAM addr is 16 bits */

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typedef volatile signed short* DPRAMADDR_S; /* DPRAM addr is 16 bits */

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typedef volatile unsigned short DPRAMDATA; /* DPRAM data is 16 bits */

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#define DFESYS_GLB_CON_CONFIG1_REG_BASE (0xA8bd0000)

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#define DFESYS_GLB_CON_CONFIG1_end (DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0218 + 1*4)

#define TXDFE_D_BSRP_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0008))

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#define TXDFE_D_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0010))

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#define TXDFE_D_F156M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0014))

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#define TXDFE_D_F26M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0018))

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#define TXDFE_D_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x001c))

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#define TPC_D_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0020))

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#define TPC_D_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0024))

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#define FDD_TTR_F13M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0030))

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#define TDD_TTR_F6P5M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0040))

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#define LTE_TTR0_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0050))

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#define LTE_TTR1_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0054))

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#define LTE_TTR2_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0058))

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#define NR_TTR0_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0070))

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#define NR_TTR1_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0074))

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#define NR_TTR2_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0078))

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#define NR_TTR3_F312M_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x007c))

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#define SERDES_COS_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00a0))

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#define SERDES_ACNT_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00a4))

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#define SERDES_L3_TX_FREE_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00a8))

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#define SERDES_L3_RX_FREE_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00ac))

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#define SERDES_MISC_FREE_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00b0))

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#define SERDES_GLB_OFF_BUS_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00b4))

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#define DIGRF_OFF_HW_SW_RESET ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00bc))

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#define F312M_DEBUG_BUS ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00c0))

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#define F312M_DEBUG_BUS2 ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00c4))

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#define DFESYS_DEBUG_TRIG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x00c8))

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#define RXDFE_F312M_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0100))

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#define RXDFE_F156M_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0104))

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#define RXDFE_F26M_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0108))

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#define SERDES_SWRST0_STARTB ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0200))

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#define SERDES_SWRST1_STARTB ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0204))

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#define DBG_FLAG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0208))

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#define DBG_TRIG_SEL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x020c))

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#define DFESYS_MAS_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0210))

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#define DFESYS_SLB_BUS_CK_SW_CKCTRL ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0214))

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#define D_GDMA_CK_SW_CKEN ((APBADDR32)(DFESYS_GLB_CON_CONFIG1_REG_BASE + 0x0218))

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_LSB (6)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_WIDTH (1)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_MASK (0x00000040)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN6_BIT (0x00000040)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_LSB (5)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_WIDTH (1)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_MASK (0x00000020)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN5_BIT (0x00000020)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_LSB (4)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_WIDTH (1)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_MASK (0x00000010)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN4_BIT (0x00000010)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_LSB (3)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_WIDTH (1)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_MASK (0x00000008)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN3_BIT (0x00000008)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_LSB (2)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_WIDTH (1)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_MASK (0x00000004)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN2_BIT (0x00000004)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_LSB (1)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_WIDTH (1)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_MASK (0x00000002)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN1_BIT (0x00000002)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_LSB (0)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_WIDTH (1)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_MASK (0x00000001)

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#define TXDFE_D_BSRP_SW_CKEN_TXDFE_D_BSRP_SW_CKEN0_BIT (0x00000001)

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#define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_LSB (0)

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#define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_WIDTH (1)

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#define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_MASK (0x00000001)

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#define TXDFE_D_F312M_SW_CKEN_TXDFE_D_F312M_SW_CKEN_BIT (0x00000001)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_LSB (6)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_WIDTH (1)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_MASK (0x00000040)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN6_BIT (0x00000040)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_LSB (5)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_WIDTH (1)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_MASK (0x00000020)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN5_BIT (0x00000020)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_LSB (4)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_WIDTH (1)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_MASK (0x00000010)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN4_BIT (0x00000010)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_LSB (3)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_WIDTH (1)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_MASK (0x00000008)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN3_BIT (0x00000008)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_LSB (2)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_WIDTH (1)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_MASK (0x00000004)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN2_BIT (0x00000004)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_LSB (1)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_WIDTH (1)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_MASK (0x00000002)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN1_BIT (0x00000002)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_LSB (0)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_WIDTH (1)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_MASK (0x00000001)

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#define TXDFE_D_F156M_SW_CKEN_TXDFE_D_F156M_SW_CKEN0_BIT (0x00000001)

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#define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_LSB (0)

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#define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_WIDTH (1)

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#define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_MASK (0x00000001)

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#define TXDFE_D_F26M_SW_CKEN_TXDFE_D_F26M_SW_CKEN_BIT (0x00000001)

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#define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_LSB (0)

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#define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_WIDTH (1)

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#define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_MASK (0x00000001)

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#define TXDFE_D_SW_RESET_TXDFE_D_SW_RESET_BIT (0x00000001)

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#define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_LSB (1)

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#define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_WIDTH (1)

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#define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_MASK (0x00000002)

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#define TPC_D_CK_SW_CKEN_TPC_F312M_BCLK_CK_SW_CKEN_BIT (0x00000002)

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#define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_LSB (0)

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#define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_WIDTH (1)

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#define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_MASK (0x00000001)

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#define TPC_D_CK_SW_CKEN_TPC_F312M_GATED_BCLK_CK_SW_CKEN_BIT (0x00000001)

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#define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_LSB (1)

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#define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_WIDTH (1)

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#define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_MASK (0x00000002)

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#define TPC_D_CK_SW_CKCTRL_TPC_F312M_BCLK_CK_SW_CKCTRL_BIT (0x00000002)

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#define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_LSB (0)

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#define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_WIDTH (1)

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#define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_MASK (0x00000001)

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#define TPC_D_CK_SW_CKCTRL_TPC_F312M_GATED_BCLK_CK_SW_CKCTRL_BIT (0x00000001)

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#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_LSB (0)

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#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_WIDTH (1)

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#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_MASK (0x00000001)

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#define FDD_TTR_F13M_SW_CKEN_FDD_TTR_F13M_SW_CKEN_BIT (0x00000001)

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#define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_LSB (0)

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#define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_WIDTH (1)

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#define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_MASK (0x00000001)

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#define TDD_TTR_F6P5M_SW_CKEN_TDD_TTR_F6P5M_SW_CKEN_BIT (0x00000001)

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#define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_LSB (0)

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#define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_WIDTH (1)

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#define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_MASK (0x00000001)

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#define LTE_TTR0_F312M_SW_CKEN_LTE_TTR0_F312M_SW_CKEN_BIT (0x00000001)

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#define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_LSB (0)

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#define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_WIDTH (1)

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#define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_MASK (0x00000001)

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#define LTE_TTR1_F312M_SW_CKEN_LTE_TTR1_F312M_SW_CKEN_BIT (0x00000001)

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#define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_LSB (0)

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#define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_WIDTH (1)

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#define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_MASK (0x00000001)

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#define lte_ttr2_f312m_sw_cken_lte_ttr2_f312m_sw_cken_BIT (0x00000001)

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#define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_LSB (0)

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#define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_WIDTH (1)

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#define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_MASK (0x00000001)

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#define NR_TTR0_F312M_SW_CKEN_NR_TTR0_F312M_SW_CKEN_BIT (0x00000001)

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#define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_LSB (0)

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#define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_WIDTH (1)

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#define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_MASK (0x00000001)

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#define NR_TTR1_F312M_SW_CKEN_NR_TTR1_F312M_SW_CKEN_BIT (0x00000001)

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#define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_LSB (0)

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#define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_WIDTH (1)

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#define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_MASK (0x00000001)

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#define NR_TTR2_F312M_SW_CKEN_NR_TTR2_F312M_SW_CKEN_BIT (0x00000001)

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#define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_LSB (0)

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#define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_WIDTH (1)

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#define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_MASK (0x00000001)

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#define NR_TTR3_F312M_SW_CKEN_NR_TTR3_F312M_SW_CKEN_BIT (0x00000001)

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#define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_LSB (0)

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#define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_WIDTH (1)

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#define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_MASK (0x00000001)

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#define SERDES_COS_CK_SW_CKEN_SERDES_COS_CK_SW_CKEN_BIT (0x00000001)

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#define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_LSB (0)

250

#define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_WIDTH (1)

251

#define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_MASK (0x00000001)

252

#define SERDES_ACNT_CK_SW_CKEN_SERDES_ACNT_CK_SW_CKEN_BIT (0x00000001)

253

254

#define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_LSB (0)

255

#define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_WIDTH (1)

256

#define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_MASK (0x00000001)

257

#define SERDES_L3_TX_FREE_CK_SW_CKEN_SERDES_L3_TX_FREE_CK_SW_CKEN_BIT (0x00000001)

258

259

#define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_LSB (0)

260

#define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_WIDTH (1)

261

#define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_MASK (0x00000001)

262

#define SERDES_L3_RX_FREE_CK_SW_CKEN_SERDES_L3_RX_FREE_CK_SW_CKEN_BIT (0x00000001)

263

264

#define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_LSB (0)

265

#define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_WIDTH (1)

266

#define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_MASK (0x00000001)

267

#define SERDES_MISC_FREE_CK_SW_CKEN_SERDES_MISC_FREE_CK_SW_CKEN_BIT (0x00000001)

268

269

#define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_LSB (0)

270

#define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_WIDTH (1)

271

#define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_MASK (0x00000001)

272

#define SERDES_GLB_OFF_BUS_CK_SW_CKEN_SERDES_GLB_OFF_BUS_CK_SW_CKEN_BIT (0x00000001)

273

274

#define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_LSB (0)

275

#define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_WIDTH (1)

276

#define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_MASK (0x00000001)

277

#define DIGRF_OFF_HW_SW_RESET_DIGRF_OFF_HW_SW_RESET_BIT (0x00000001)

278

279

#define F312M_DEBUG_BUS_F312M_DEBUG_BUS_LSB (0)

280

#define F312M_DEBUG_BUS_F312M_DEBUG_BUS_WIDTH (32)

281

#define F312M_DEBUG_BUS_F312M_DEBUG_BUS_MASK (0xFFFFFFFF)

282

283

#define F312M_DEBUG_BUS2_F312M_DEBUG_BUS2_LSB (0)

284

#define F312M_DEBUG_BUS2_F312M_DEBUG_BUS2_WIDTH (32)

285

#define F312M_DEBUG_BUS2_F312M_DEBUG_BUS2_MASK (0xFFFFFFFF)

286

287

#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_LSB (0)

288

#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_WIDTH (5)

289

#define DEBUG_TRIG_SEL_DEBUG_TRIG_SEL_MASK (0x0000001F)

290

291

#define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_LSB (0)

292

#define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_WIDTH (1)

293

#define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_MASK (0x00000001)

294

#define RXDFE_F312M_CK_SW_CKEN_RXDFE_F312M_CK_SW_CKEN_BIT (0x00000001)

295

296

#define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_LSB (0)

297

#define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_WIDTH (1)

298

#define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_MASK (0x00000001)

299

#define RXDFE_F156M_CK_SW_CKEN_RXDFE_F156M_CK_SW_CKEN_BIT (0x00000001)

300

301

#define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_LSB (0)

302

#define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_WIDTH (1)

303

#define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_MASK (0x00000001)

304

#define RXDFE_F26M_CK_SW_CKEN_RXDFE_F26M_CK_SW_CKEN_BIT (0x00000001)

305

306

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_LSB (13)

307

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_WIDTH (1)

308

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_MASK (0x00002000)

309

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN6_SWRST_STARTB_BIT (0x00002000)

310

311

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_LSB (12)

312

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_WIDTH (1)

313

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_MASK (0x00001000)

314

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN5_SWRST_STARTB_BIT (0x00001000)

315

316

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_LSB (11)

317

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_WIDTH (1)

318

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_MASK (0x00000800)

319

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN4_SWRST_STARTB_BIT (0x00000800)

320

321

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_LSB (10)

322

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_WIDTH (1)

323

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_MASK (0x00000400)

324

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN3_SWRST_STARTB_BIT (0x00000400)

325

326

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_LSB (9)

327

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_WIDTH (1)

328

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_MASK (0x00000200)

329

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN2_SWRST_STARTB_BIT (0x00000200)

330

331

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_LSB (8)

332

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_WIDTH (1)

333

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_MASK (0x00000100)

334

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN1_SWRST_STARTB_BIT (0x00000100)

335

336

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_LSB (7)

337

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_WIDTH (1)

338

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_MASK (0x00000080)

339

#define SERDES_SWRST0_STARTB_SERDES_STRM_IN0_SWRST_STARTB_BIT (0x00000080)

340

341

#define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_LSB (6)

342

#define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_WIDTH (1)

343

#define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_MASK (0x00000040)

344

#define SERDES_SWRST0_STARTB_SERDES_COS_OUT_SWRST_STARTB_BIT (0x00000040)

345

346

#define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_LSB (5)

347

#define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_WIDTH (1)

348

#define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_MASK (0x00000020)

349

#define SERDES_SWRST0_STARTB_SERDES_COS_IN_SWRST_STARTB_BIT (0x00000020)

350

351

#define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_LSB (4)

352

#define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_WIDTH (1)

353

#define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_MASK (0x00000010)

354

#define SERDES_SWRST0_STARTB_SERDES_L3_TX_SWRST_STARTB_BIT (0x00000010)

355

356

#define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_LSB (3)

357

#define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_WIDTH (1)

358

#define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_MASK (0x00000008)

359

#define SERDES_SWRST0_STARTB_SERDES_L3_RX_SWRST_STARTB_BIT (0x00000008)

360

361

#define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_LSB (2)

362

#define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_WIDTH (1)

363

#define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_MASK (0x00000004)

364

#define SERDES_SWRST0_STARTB_SERDES_L2_SWRST_STARTB_BIT (0x00000004)

365

366

#define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_LSB (1)

367

#define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_WIDTH (1)

368

#define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_MASK (0x00000002)

369

#define SERDES_SWRST0_STARTB_SERDES_L1_SWRST_STARTB_BIT (0x00000002)

370

371

#define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_LSB (0)

372

#define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_WIDTH (1)

373

#define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_MASK (0x00000001)

374

#define SERDES_SWRST0_STARTB_SERDES_MISC_SWRST_STARTB_BIT (0x00000001)

375

376

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_LSB (15)

377

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_WIDTH (1)

378

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_MASK (0x00008000)

379

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT15_SWRST_STARTB_BIT (0x00008000)

380

381

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_LSB (14)

382

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_WIDTH (1)

383

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_MASK (0x00004000)

384

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT14_SWRST_STARTB_BIT (0x00004000)

385

386

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_LSB (13)

387

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_WIDTH (1)

388

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_MASK (0x00002000)

389

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT13_SWRST_STARTB_BIT (0x00002000)

390

391

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_LSB (12)

392

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_WIDTH (1)

393

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_MASK (0x00001000)

394

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT12_SWRST_STARTB_BIT (0x00001000)

395

396

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_LSB (11)

397

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_WIDTH (1)

398

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_MASK (0x00000800)

399

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT11_SWRST_STARTB_BIT (0x00000800)

400

401

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_LSB (10)

402

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_WIDTH (1)

403

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_MASK (0x00000400)

404

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT10_SWRST_STARTB_BIT (0x00000400)

405

406

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_LSB (9)

407

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_WIDTH (1)

408

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_MASK (0x00000200)

409

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT9_SWRST_STARTB_BIT (0x00000200)

410

411

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_LSB (8)

412

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_WIDTH (1)

413

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_MASK (0x00000100)

414

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT8_SWRST_STARTB_BIT (0x00000100)

415

416

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_LSB (7)

417

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_WIDTH (1)

418

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_MASK (0x00000080)

419

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT7_SWRST_STARTB_BIT (0x00000080)

420

421

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_LSB (6)

422

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_WIDTH (1)

423

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_MASK (0x00000040)

424

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT6_SWRST_STARTB_BIT (0x00000040)

425

426

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_LSB (5)

427

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_WIDTH (1)

428

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_MASK (0x00000020)

429

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT5_SWRST_STARTB_BIT (0x00000020)

430

431

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_LSB (4)

432

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_WIDTH (1)

433

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_MASK (0x00000010)

434

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT4_SWRST_STARTB_BIT (0x00000010)

435

436

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_LSB (3)

437

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_WIDTH (1)

438

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_MASK (0x00000008)

439

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT3_SWRST_STARTB_BIT (0x00000008)

440

441

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_LSB (2)

442

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_WIDTH (1)

443

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_MASK (0x00000004)

444

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT2_SWRST_STARTB_BIT (0x00000004)

445

446

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_LSB (1)

447

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_WIDTH (1)

448

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_MASK (0x00000002)

449

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT1_SWRST_STARTB_BIT (0x00000002)

450

451

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_LSB (0)

452

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_WIDTH (1)

453

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_MASK (0x00000001)

454

#define SERDES_SWRST1_STARTB_SERDES_STRM_OUT0_SWRST_STARTB_BIT (0x00000001)

455

456

#define DBG_FLAG_SEL_DBG_FLAG3_SEL_LSB (24)

457

#define DBG_FLAG_SEL_DBG_FLAG3_SEL_WIDTH (8)

458

#define DBG_FLAG_SEL_DBG_FLAG3_SEL_MASK (0xFF000000)

459

460

#define DBG_FLAG_SEL_DBG_FLAG2_SEL_LSB (16)

461

#define DBG_FLAG_SEL_DBG_FLAG2_SEL_WIDTH (8)

462

#define DBG_FLAG_SEL_DBG_FLAG2_SEL_MASK (0x00FF0000)

463

464

#define DBG_FLAG_SEL_DBG_FLAG1_SEL_LSB (8)

465

#define DBG_FLAG_SEL_DBG_FLAG1_SEL_WIDTH (8)

466

#define DBG_FLAG_SEL_DBG_FLAG1_SEL_MASK (0x0000FF00)

467

468

#define DBG_FLAG_SEL_DBG_FLAG0_SEL_LSB (0)

469

#define DBG_FLAG_SEL_DBG_FLAG0_SEL_WIDTH (8)

470

#define DBG_FLAG_SEL_DBG_FLAG0_SEL_MASK (0x000000FF)

471

472

#define DBG_TRIG_SEL_DBG_TRIG_SEL_LSB (0)

473

#define DBG_TRIG_SEL_DBG_TRIG_SEL_WIDTH (8)

474

#define DBG_TRIG_SEL_DBG_TRIG_SEL_MASK (0x000000FF)

475

476

#define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_LSB (0)

477

#define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_WIDTH (1)

478

#define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_MASK (0x00000001)

479

#define DFESYS_MAS_BUS_CK_SW_CKCTRL_DFESYS_MAS_BUS_CK_SW_CKCTRL_BIT (0x00000001)

480

481

#define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_LSB (0)

482

#define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_WIDTH (1)

483

#define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_MASK (0x00000001)

484

#define DFESYS_SLB_BUS_CK_SW_CKCTRL_DFESYS_SLV_BUS_CK_CSW_CKCTRL_BIT (0x00000001)

485

486

#define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_LSB (0)

487

#define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_WIDTH (1)

488

#define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_MASK (0x00000001)

489

#define D_GDMA_CK_SW_CKEN_D_GDMA_CK_SW_CKEN_BIT (0x00000001)

490

491

492

#endif //#ifndef _EL1D_REG_ELBRUS_H_