[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/custom/system/Template/Readme.txt b/mcu/custom/system/Template/Readme.txt
new file mode 100644
index 0000000..8ce4629
--- /dev/null
+++ b/mcu/custom/system/Template/Readme.txt
@@ -0,0 +1,16 @@
+[Note]
+
+For any modification of *.h.template or *.c.template, there are some rules to follow as below:
+
+1. tools\sysgen2.pl replaces the pattern [AUTOGEN_xxx] in templates every time you perform m sysgen, sys_auto_gen or new.
+In this pattern, xxx means A-Z, a-z, 0-9, and _ .
+xxx will be the function name in sysgen2.pl.
+
+2. If you want to comment this pattern in templates, kindly use
+#if 0
+#endif
+to comment it.
+
+3. Files under custom\system\[Project]\ with the pattern:[MOLY12345678], [MAUI_12345678] or [MANUAL-CHECKIN] still won't be replaced by the templates.
+
+4. The template folder can't accept xxx.c and xxx.c.template which exist simultaneously.
\ No newline at end of file
diff --git a/mcu/custom/system/Template/custom_config.c b/mcu/custom/system/Template/custom_config.c
new file mode 100644
index 0000000..a1303c0
--- /dev/null
+++ b/mcu/custom/system/Template/custom_config.c
@@ -0,0 +1,340 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2006
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * custom_config.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file contain definition of custom component module configuration variables, and routines
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*************************************************************************
+ * Include Statements
+ *************************************************************************/
+#include "kal_general_types.h"
+#include "kal_public_api.h"
+#include "kal_public_defs.h"
+#include "kal_internal_api.h"
+#include "kal_internal_def.h"
+#include "task_config.h"
+#include "kal_user_mem.h"
+
+/*************************************************************************
+* FUNCTION
+* custom_configmem()
+*
+* DESCRIPTION
+* This routine configure
+*
+* a. system total memory usage
+* Task's stack, external queue, control buffer entries etc.
+* Any one who attempts to create new task or enlarge control
+* buffer size should fine tune the value!
+*
+* b. system total debug memory usage
+* Valid for DEBUG_KAL + DEBUG_[some items, ITC, BUF etc]
+*
+* PARAMETERS
+* system_mem_sz - system all memory usage
+* debug_mem_sz - system all debug memory usage
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+
+#ifdef __MTK_TARGET__
+ #include "sys_mem_size.h"
+#else
+ #include "sys_mem_size_modis.h"
+#endif /*__MTK_TARGET__*/
+
+
+/*Debug mem pool before sys mem for easy debug in case sys mem overflow*/
+
+#if defined(DEBUG_KAL)
+static kal_uint32 Debug_Mem_Pool[(GLOBAL_DEBUG_MEM_SIZE
+#if defined(__KTEST__)
++ 1024 /*pool for profiling tests*/
+#endif
+)/sizeof(kal_uint32)];
+#endif /* DEBUG_KAL */
+
+static kal_uint32 System_Mem_Pool[(GLOBAL_MEM_SIZE + CUSTOM_CFG_GLOBAL_MEM_SIZE_IN_BYTES
+
+#if defined(ATEST_ENABLE)
++(10*1024)
+#endif
+#if defined(__KTEST__)
++(5*1024)
+#endif
+) / sizeof(kal_uint32)];
+
+
+void
+custom_configmem(kal_uint32 *system_mem_sz, kal_uint32** system_mem_addr,
+ kal_uint32 *debug_mem_sz, kal_uint32** debug_mem_addr)
+{
+ *system_mem_sz = sizeof(System_Mem_Pool);
+ *system_mem_addr = System_Mem_Pool;
+
+#if defined(DEBUG_KAL)
+ *debug_mem_addr = Debug_Mem_Pool;
+ *debug_mem_sz = sizeof(Debug_Mem_Pool);
+#else
+ *debug_mem_addr = (kal_uint32 *)0;
+ *debug_mem_sz = 0;
+#endif
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_config_libc_heap()
+*
+* DESCRIPTION
+* This routine configure libc heap size & location.
+*
+* PARAMETERS
+*
+* RETURNS
+* heap size & heap location. if heap_size return 0, then no heap is
+* initialized.
+*
+* GLOBALS AFFECTED
+*
+*************************************************************************/
+#ifdef __GADGET_SUPPORT__
+#define GLOBAL_LIBC_HEAP_SIZE 10240
+#else
+#define GLOBAL_LIBC_HEAP_SIZE 65536 /* 64K Heap for newlib */
+#endif
+#if GLOBAL_LIBC_HEAP_SIZE != 0
+/* if we don't define heap, we won't define a symbol call System_Libc_Heap
+ * using this method, we can detect whether system allow to use
+ * malloc/free/realloc/calloc
+ */
+kal_uint32 System_Libc_Heap[GLOBAL_LIBC_HEAP_SIZE/sizeof(kal_uint32)];
+#endif
+void custom_config_libc_heap(kal_uint32 *heap_size, void **heap_addr)
+{
+#if GLOBAL_LIBC_HEAP_SIZE == 0
+ *heap_size = 0;
+ *heap_addr = 0;
+#else
+ *heap_size = sizeof(System_Libc_Heap);
+ *heap_addr = System_Libc_Heap;
+#endif
+}
+
diff --git a/mcu/custom/system/Template/custom_demp.c b/mcu/custom/system/Template/custom_demp.c
new file mode 100644
index 0000000..e1d1a0c
--- /dev/null
+++ b/mcu/custom/system/Template/custom_demp.c
@@ -0,0 +1,212 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2006
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * custom_config.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file contain definition of custom component module configuration variables, and routines
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*************************************************************************
+ * Include Statements
+ *************************************************************************/
+#include "kal_general_types.h"
+#include "kal_public_api.h"
+#include "kal_public_defs.h"
+#include "custom_FeatureConfig.h"
+
+/*************************************************************************
+* FUNCTION
+* custom_config_demp_page
+*
+* DESCRIPTION
+* This routine configures pages for demand paging.
+*
+* PARAMETERS
+* page - returned pointer to control blocks
+* pool - returned pointer to page pool
+* pool_size - returned pointer to page pool size
+*
+* RETURNS
+* 0 fo success; -1 for failure.
+*
+************************************************************************/
+#if defined(__DEMAND_PAGING__)
+
+#if defined(CONFIG_DEMAND_PAGE_SHARE_POOL_SIZE)
+ #define DEMP_PAGE_SHARE_POOL_SIZE CONFIG_DEMAND_PAGE_SHARE_POOL_SIZE
+#else /* CONFIG_DEMAND_PAGE_SHARE_POOL_SIZE */
+
+#if defined(__DEMAND_PAGING_V2__)
+#if defined(MT6268) || defined(MT6268A) || defined(MT6268H) || defined(MT6268T)
+ #define DEMP_PAGE_SHARE_POOL_SIZE (2560 * 1024)
+ #define DEMP_MIN_SHARE_POOL_SIZE (2048 * 1024)
+#else
+ #define DEMP_PAGE_SHARE_POOL_SIZE (2560 * 1024)
+ #define DEMP_MIN_SHARE_POOL_SIZE (2048 * 1024)
+#endif
+#else /*__DEMAND_PAGING_V2__*/
+ #define DEMP_PAGE_SHARE_POOL_SIZE (2048 * 1024)
+ #define DEMP_MIN_SHARE_POOL_SIZE (2048 * 1024)
+#endif /*__DEMAND_PAGING_V2__*/
+#endif /* CONFIG_DEMAND_PAGE_SHARE_POOL_SIZE */
+
+#define DEMP_PAGE_POOL_SIZE (TOTAL_MAX_LOCK_SIZE + DEMP_PAGE_SHARE_POOL_SIZE)
+
+#if DEMP_MIN_SHARE_POOL_SIZE > DEMP_PAGE_SHARE_POOL_SIZE
+ #error "Pool size is smaller than minimum size!"
+#endif
+
+#if defined (__DEMAND_PAGING_PERFORMANCE_PROFILING__)
+
+/* define page pool */
+#if defined(__MTK_TARGET__)
+#pragma arm section zidata = "NONCACHEDZI"
+// KeTing: To support change demand page pool on the fly, set to max allowable page by default
+//static __align((2 << PAGE_CLUSTER) * 1024) kal_uint32 DEMP_PAGE_POOL[DEMP_PAGE_POOL_SIZE / 4];
+static __align((2 << PAGE_CLUSTER) * 1024) kal_uint32 DEMP_PAGE_POOL[DEMP_PAGE_POOL_MAX_SIZE / 4];
+#pragma arm section zidata
+#else
+//static kal_uint32 DEMP_PAGE_POOL[DEMP_PAGE_POOL_SIZE / 4];
+static kal_uint32 DEMP_PAGE_POOL[DEMP_PAGE_POOL_MAX_SIZE / 4];
+#endif /* MTK_TARGET */
+
+/* define the control block for pages */
+//static demp_page_t DEMP_PAGE_LIST[DEMP_PAGE_POOL_SIZE >> (PAGE_SHIFT_2K + (PAGE_CLUSTER - 1))];
+static demp_page_t DEMP_PAGE_LIST[DEMP_PAGE_POOL_MAX_SIZE >> (PAGE_SHIFT_2K + (PAGE_CLUSTER - 1))];
+
+#else /* __DEMAND_PAGING_PERFORMANCE_PROFILING__ */
+
+/* define page pool */
+#if defined(__MTK_TARGET__)
+#pragma arm section zidata = "NONCACHEDZI"
+static __align((2 << PAGE_CLUSTER) * 1024) kal_uint32 DEMP_PAGE_POOL[DEMP_PAGE_POOL_SIZE / 4];
+#pragma arm section zidata
+#else
+static kal_uint32 DEMP_PAGE_POOL[DEMP_PAGE_POOL_SIZE / 4];
+#endif /* MTK_TARGET */
+
+/* define the control block for pages */
+static demp_page_t DEMP_PAGE_LIST[DEMP_PAGE_POOL_SIZE >> (PAGE_SHIFT_2K + (PAGE_CLUSTER - 1))];
+
+#endif /* __DEMAND_PAGING_PERFORMANCE_PROFILING__ */
+
+#endif /* __DEMAND_PAGING__ */
+
+kal_int32
+custom_config_demp_page(kal_uint32 **list, kal_uint32 **pool, kal_uint32 *pool_size)
+{
+#if defined(__DEMAND_PAGING__)
+
+ if (list != NULL) {
+ *list = (kal_uint32 *)DEMP_PAGE_LIST;
+ } else {
+ return -1;
+ }
+
+ if (pool != NULL) {
+ *pool = (kal_uint32 *)DEMP_PAGE_POOL;
+ } else {
+ return -1;
+ }
+
+ if (pool_size != NULL) {
+ *pool_size = DEMP_PAGE_POOL_SIZE;
+ } else {
+ return -1;
+ }
+
+ return 0;
+
+#else /* __DEMAND_PAGING__ */
+
+ return -1;
+
+#endif /* __DEMAND_PAGING__ */
+}
+
diff --git a/mcu/custom/system/Template/custom_demp.h.template b/mcu/custom/system/Template/custom_demp.h.template
new file mode 100644
index 0000000..27bb4d5
--- /dev/null
+++ b/mcu/custom/system/Template/custom_demp.h.template
@@ -0,0 +1,112 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2006
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * custom_demp.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file Demand Paging related definitions
+ *
+ * Author:
+ * -------
+ * Timon Lu (mtk03814) [AUTOGEN_GenVersion]
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * $Revision$
+ * $Modtime$
+ * $Log$
+ *
+ * 03 08 2012 qmei.yang
+ * [MAUI_03145378] [SystemService][Auto-Gen][Sys Gen][scatGen][Internal Refinement] Phase in AutoGen new flow to support GCC
+ * .
+ *
+ * 01 30 2012 qmei.yang
+ * [MAUI_03120516] [SystemService][Auto-Gen][Sys Gen][scatGen][Internal Refinement] Refactory sysgen2.pl
+ * sysgen2.pl v1.42
+ * scatInfo.pm v0.01
+ * sysgenUtility.pm v0.15
+ * FileInfo.pm v0.04
+ * custom_demp.h.template
+ * custom_scatstruct.c.template
+ * custom_scatstruct.h.template
+ * custom_blconfig.c.template
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __CUSTOM_DEMP_H__
+#define __CUSTOM_DEMP_H__
+
+/*******************************************************************************
+ * Define constants.
+ *******************************************************************************/
+
+/* DEMP bin type declaration */
+typedef enum
+{
+ DEMP_MAIN, /* should be the first type */
+#if defined(__MBA_ON_DEMAND__)
+[AUTOGEN_DEMP_H_Gen_MBA_LIST]
+#endif /* __MBA_ON_DEMAND__ */
+ /* more resource bin could be added */
+
+ DEMP_BIN_NUM
+} demp_bin_type;
+
+/* DEMP bin size declaration (MB) */
+#define DEMP_MAIN_BIN_SIZE [AUTOGEN_DEMP_H_Gen_DEMP_MAIN_BINSIZE]
+#if defined(__MBA_ON_DEMAND__)
+[AUTOGEN_DEMP_H_Gen_MBA_BINSIZE_LIST]
+#define DEMP_TOTAL_BIN_SIZE (DEMP_MAIN_BIN_SIZE[AUTOGEN_DEMP_H_Gen_DEMP_MBA_BINSIZE])
+#else /* __MBA_ON_DEMAND__ */
+#define DEMP_TOTAL_BIN_SIZE DEMP_MAIN_BIN_SIZE
+#endif /* __MBA_ON_DEMAND__ */
+
+#define DEMP_BLOCK_PER_MB 64 /* 1MB / 16KB = 64 */
+
+#endif /* __CUSTOM_DEMP_H__ */
diff --git a/mcu/custom/system/Template/custom_dl2cmgr.c.template b/mcu/custom/system/Template/custom_dl2cmgr.c.template
new file mode 100644
index 0000000..b1ff1b7
--- /dev/null
+++ b/mcu/custom/system/Template/custom_dl2cmgr.c.template
@@ -0,0 +1,91 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2006
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * custom_dl2cmgr.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file declares symbols used for L2Cache Lock.
+ *
+ * Author:
+ * -------
+ * Yao.Liu (mtk15073)
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * $Revision$
+ * $Modtime$
+ * $Log$
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "kal_general_types.h"
+#include "custom_dl2cmgr.h"
+
+//extern related linker symbols
+[AUTOGEN_DL2CMGR_H_Gen_SECTION_LINKER_SYMBOL]
+
+/*************************************************************************
+* DATA
+* dl2cm_linker_symbol
+*
+* DESCRIPTION
+* This array is used to record the L2Cache Lock section info
+*
+* PARAMETERS
+*
+* dl2cm_linker_symbol[x][0]: The base address of input section.
+* dl2cm_linker_symbol[x][0]: The end address of input section.
+* dl2cm_linker_symbol[x][0]: The attribute of input section. 0:RO; 1:RW.
+*
+*************************************************************************/
+const kal_uint32 dl2cm_linker_symbol[L2CACHE_LOCK_SECTION_NUM][3] = {
+[AUTOGEN_DL2CMGR_H_Gen_LINKER_SYMBOL_ARRAY]
+};
+
+
diff --git a/mcu/custom/system/Template/custom_dl2cmgr.h.template b/mcu/custom/system/Template/custom_dl2cmgr.h.template
new file mode 100644
index 0000000..7be9edf
--- /dev/null
+++ b/mcu/custom/system/Template/custom_dl2cmgr.h.template
@@ -0,0 +1,75 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2006
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * custom_dl2cmgr.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file declares symbols used for L2Cache Lock.
+ *
+ * Author:
+ * -------
+ * Yao.Liu (mtk15073)
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * $Revision$
+ * $Modtime$
+ * $Log$
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _CUSTOM_DL2CMGR_H
+#define _CUSTOM_DL2CMGR_H
+
+
+typedef enum {
+[AUTOGEN_DL2CMGR_H_Gen_SECTION_ID_ENUM]
+} dl2cm_section_id;
+
+#endif /* _CUSTOM_DL2CMGR_H */
\ No newline at end of file
diff --git a/mcu/custom/system/Template/custom_dummy_ref.c b/mcu/custom/system/Template/custom_dummy_ref.c
new file mode 100644
index 0000000..5382074
--- /dev/null
+++ b/mcu/custom/system/Template/custom_dummy_ref.c
@@ -0,0 +1,137 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2006
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * custom_dymmy_ref.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file contain dummy reference functions
+ *
+ * Author:
+ * -------
+ *
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*************************************************************************
+ * Include Statements
+ *************************************************************************/
+#include "kal_general_types.h"
+#include "kal_public_api.h"
+#include "kal_public_defs.h"
+
+/*************************************************************************
+ * External Function Declaration
+ *************************************************************************/
+
+
+/*************************************************************************
+* FUNCTION
+* custom_dummy_ref
+*
+* DESCRIPTION
+* This function will call dummy reference function for avoiding some shared variable
+* be garbage collection by linker
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* None
+*
+* GLOBALS AFFECTED
+*
+*
+*************************************************************************/
+void custom_dummy_ref(void)
+{
+/* 1) Please extern your dummy reference function rather than include the header file
+ to avoid compiler report "can't find header files"
+ 2) Do not use any compiler option to wrap your function in this function
+ i.e. you must compil your function in all project except 'basic' project
+*/
+ extern void MD2G_DRV_SHAREBUF_DUMMY_REF( void );
+
+ MD2G_DRV_SHAREBUF_DUMMY_REF();
+}
+
diff --git a/mcu/custom/system/Template/custom_emi_offset.h.template b/mcu/custom/system/Template/custom_emi_offset.h.template
new file mode 100644
index 0000000..d8f860c
--- /dev/null
+++ b/mcu/custom/system/Template/custom_emi_offset.h.template
@@ -0,0 +1,94 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2006
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * custom_emi_offset.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file defines MD total size.
+ *
+ * Author:
+ * -------
+ * Qmei Yang (mtk03726) [AUTOGEN_GenVersion]
+ *
+
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * $Revision$
+ * $Modtime$
+ * $Log$
+ *
+ * 11 13 2014 jerry.chang
+ * [MOLY00084326] checkin common custom file to MOLY.W14.42.LTE.p2
+ * rollback to MOLY.W14.42.LTE.p2
+ *
+ * 09 09 2014 guo-huei.chang
+ * [MOLY00078093] [MT6290][ROUTER] RMPU offset setting
+ * update emi offset for MT6290
+ *
+ * 05 03 2013 qmei.yang
+ * [MOLY00021466] [MT6290 Bring-up][SystemService][Auto-Gen][Request For Design Change] Gen custom_emi_offset.h for referring by MT6290 bootloader
+ * .
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+
+ ****************************************************************************/
+
+#ifndef __CUSTOM_EMI_OFFSET_H__
+#define __CUSTOM_EMI_OFFSET_H__
+
+#define MD_SIZE [AUTOGEN_EMI_OFFSET_H_Gen_MD_SIZE]
+#if defined(MT6290)
+ /*offset should be 128k aligned */
+ #define EMI_APMCU_OFFSET 0
+ #define EMI_APPERI_OFFSET 0
+#else
+ #define EMI_APMCU_OFFSET
+ #define EMI_APPERI_OFFSET
+#endif
+
+#endif
diff --git a/mcu/custom/system/Template/custom_img_config.c b/mcu/custom/system/Template/custom_img_config.c
new file mode 100644
index 0000000..7bddba0
--- /dev/null
+++ b/mcu/custom/system/Template/custom_img_config.c
@@ -0,0 +1,85 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2006
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * custom_img_config.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file implements image information feature.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
diff --git a/mcu/custom/system/Template/custom_img_config.h.template b/mcu/custom/system/Template/custom_img_config.h.template
new file mode 100644
index 0000000..774211d
--- /dev/null
+++ b/mcu/custom/system/Template/custom_img_config.h.template
@@ -0,0 +1,292 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2006
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * custom_img_config.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the FOTA (Firmware Over the Air) related setting.
+ *
+ * Author:
+ * -------
+ * Carlos Yeh (mtk02377) system auto generatorm0.25 + scatFrame m0.01 + sysGenUtility m0.10
+ *
+
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * $Revision$
+ * $Modtime$
+ * $Log$
+ *
+ * 01 20 2015 raymondwt.chen
+ * [MOLY00091518] [System Service][MOLY Kernel Internal Request] Clean build warning
+ * .Remove and organize bootloader/security code
+ *
+ * 08 07 2013 peiwen.qing
+ * [MOLY00032860] Set max size of MOLY image to 16MB
+ * .
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+
+ ****************************************************************************/
+
+#ifndef __CUSTOM_IMG_CONFIG_H__
+#define __CUSTOM_IMG_CONFIG_H__
+
+#include "kal_general_types.h"
+#include "custom_FeatureConfig.h"
+
+/****************************************************************************
+ Following definitions are used to configure flash memory arrangement for Bootloader image
+
+ Item 1. the maximum size of FOTA bootloader image
+
+ ****************************************************************************/
+#define BL_IMG_MAX_SIZE (0x40000)
+
+/****************************************************************************
+ Following definitions are used to configure flash memory arrangement for FOTA Engine image
+
+ Item 1. the base address of FOTA update engine image
+
+ Item 2. the maximum available flash memory size for update engine image
+
+ Item 3. the maximum available flash memory size for update engine image back up
+
+ Item 4. the maximum flash memory area for bootloader to search update engine image
+
+ Item 5. the execution start address for bootloader to place update engine image
+ Note: This value MUST be the same with scatter file setting
+
+ ****************************************************************************/
+#define FOTA_UE_FLASH_BASE_ADDRESS (0) //[_IMG_CFG_H_Gen_FOTA_UE_BASE]
+
+#define FOTA_UE_RESIDENT_FLASH_SPACE_SIZE (0) //[_IMG_CFG_H_Gen_FOTA_UE_RESIDENT_SIZE]
+
+#define FOTA_UE_BACKUP_FLASH_SPACE_SIZE (0) //[_IMG_CFG_H_Gen_FOTA_UE_BACKUP_SIZE]
+
+#define FOTA_UE_SEARCH_RANGE_SIZE (0x400000)
+
+#define FOTA_UE_EXECUTION_BASE (0) // [_IMG_CFG_H_Gen_FOTA_UE_EXECUTION_BASE]
+/****************************************************************************
+ Following definitions are used to configure flash memory arrangement for MAUI image
+
+ Item 1. the number of MAUI image binary parts
+
+ Item 2. the start address and maximum available flash memory size for each MAUI image
+ Note: This maximum available value specifies the size of flash memory that a image can
+ occupy except reserved flash blocks specified in Item 7. The start address should
+ be synchronized with the begin address of each image binary during update/delta
+ package generation process.
+
+ Item 3. the start address of flash storage reserved for update package
+
+ Item 4. the size of flash storage reserved for update package
+
+ Item 5. the start address of back up area for update purpose
+
+ Item 6. the maximum flash block number in update package area
+
+ Item 7. the size of back up area for update purpose
+ Note: Certain FOTA solution, like RedBend, requires a dedicate flash space to back up flash
+ content during update process. In contrast, some colution, such as Bitfone, would use
+ leftover flash blocks that are not occupied by firmware image as back up area. In this case,
+ the value of maximum available flash memory has to be increased to compensate back up
+ requirement.
+
+ Item 8. the flash blocks reserved for flash management
+ Note: This value specifies the amount of blocks that must be reseerved from
+ the gap between maximum avilable flash size, Item2, and the flash memory size
+ really occupied by firmware image.
+
+ ****************************************************************************/
+
+#define FOTA_MAUI_IMAGE_AMOUNT (1)
+#if defined(_NAND_FLASH_BOOTING_) || defined(__EMMC_BOOTING__)
+ #define MAX_LENGTH_ROM (0x01000000)
+ #define MAX_LENGTH_SECONDARY_ROM (0xFFFFFFFF)
+ #define MAX_LENGTH_DEMAND_PAGING_ROM0 (0xFFFFFFFF)
+ #define MAX_LENGTH_DSP_ROM (0xFFFFFFFF)
+#else /* _NAND_FLASH_BOOTING_ || __EMMC_BOOTING__ */
+ #define MAX_LENGTH_ROM (0xFFFFFFFF)
+#endif /* _NAND_FLASH_BOOTING_ || __EMMC_BOOTING__ */
+
+//[_IMG_CFG_H_Gen_IMG_DEFINITION] +
+#if defined(__MTK_TARGET__)
+
+#define MAUI_LOAD_ADDRESS_ROM ((kal_uint32)0)
+
+#else /* __MTK_TARGET__ */
+
+#define MAUI_LOAD_ADDRESS_ROM ((kal_uint32)0)
+
+#endif /* __MTK_TARGET__ */
+
+#define FOTA_MAUI_FLASH_SPACE { {MAUI_LOAD_ADDRESS_ROM, MAX_LENGTH_ROM, 0x0}, \
+ END_MAUI_INFO}
+
+//[_IMG_CFG_H_Gen_IMG_DEFINITION] -
+
+#define FOTA_PACKAGE_STORAGE_BASE (0) //[_IMG_CFG_H_Gen_PKG_STORAGE_BASE]
+
+#define FOTA_PACKAGE_STORAGE_SIZE (0) //[_IMG_CFG_H_Gen_PKG_STORAGE_SIZE]
+
+#define FOTA_PACKAGE_BLOCK_NUMBER (0) //[_IMG_CFG_H_Gen_PKG_BLOCK_NUM]
+
+#define FOTA_BACKUP_STORAGE_BASE (0) //[_IMG_CFG_H_Gen_BACKUP_STORAGE_BASE]
+
+#define FOTA_BACKUP_STORAGE_SIZE (0) //[_IMG_CFG_H_Gen_BACKUP_STORAGE_SIZE]
+
+#define FOTA_RESERVED_FLASH_BLOCKS (5)
+
+/****************************************************************************
+ Following definitions are used for MAUI image manageemt
+
+ Item 1. the size of mapping table for MAUI ROM image
+
+ Item 2. the size of mapping table for FUE ROM image
+
+ ****************************************************************************/
+#define FOTA_MAUI_MAPPING_TABLE_SIZE (0x800)
+
+/****************************************************************************
+ Following definitions are used for NAND flash device configuration
+
+ Item 1. the maximum page size of supported NAND flash device
+
+ ****************************************************************************/
+#define FOTA_FLASH_MAX_PAGE_SIZE (0x800)
+
+/****************************************************************************
+ Following definitions are used for FUE update process
+
+ Item 1. the maximum heap size for FUE
+
+ ****************************************************************************/
+#define FOTA_CUSTOM_POOL_SIZE (0x200000)
+
+/****************************************************************************
+ Following definitions are used for FOTA update package certification flow
+
+ Item 1. the maximum length of message authentication code (in bytes)
+
+ Item 2. the maximum length of key to encrypt message authentication code (in bytes)
+
+ ****************************************************************************/
+#define FOTA_CUSTOM_PACKAGE_MAC_SIZE (20)
+
+#define FOTA_CUSTOM_PACKAGE_SIG_SIZE (128)
+
+#define FOTA_CUSTOM_PACKAGE_KEY_MAX_LEN (128)
+
+#define FOTA_EXTRA_RESERVED_BLOCKS (5)
+
+/* Following data structure should be modified according to requirements in adoption of third partys solution */
+#define __FUE_DUMMY_UPDATE_SUPPORT__
+
+#if defined(__FUE_DUMMY_UPDATE_SUPPORT__)
+
+/*
+ * !CAUTION! size of FOTA_Custom_Update_Info MUST be equal to 88 bytes
+ */
+typedef struct {
+ kal_uint32 FOTA_test_info1;
+ kal_uint32 FOTA_test_info2;
+ kal_uint32 FOTA_test_info3;
+ kal_uint32 FOTA_test_info4;
+ kal_uint32 FOTA_test_padding[18];
+} FOTA_Custom_Update_Info;
+
+#elif defined(__FUE_HP_SUPPORT__)
+
+#include "Hp_update.h"
+
+#elif defined(__FUE_REDBEND_SUPPORT__)
+
+#include "RedBend_update.h"
+
+#else
+
+#error "Unsupported FOTA update information!!"
+
+#endif /* __FUE_DUMMY_UPDATE_SUPPORT__ */
+
+typedef struct {
+ kal_uint32 m_pkg_mod_key_len;
+ kal_char m_pkg_mod_key[(FOTA_CUSTOM_PACKAGE_KEY_MAX_LEN<<1)+1];
+ kal_uint32 m_pkg_exp_key_len;
+ kal_char m_pkg_exp_key[(FOTA_CUSTOM_PACKAGE_KEY_MAX_LEN<<1)+1];
+} FOTA_Custom_Package_Certificate_st;
+/****************************************************************************
+ Following definitions are used for CBR region attribute
+
+ Item 1. the block used for store CBR data. Each Normal block will occupy 2 physical blocks
+
+ Item 2. the block used for bad block replacement on NAND flash. For the device, it should be zero
+
+ Total blocks occupied by CBR will be CBR_REGION_NORMAL_BLOCK_NUM*2+CBR_REGION_SPARE_BLOCK_NUM
+ ****************************************************************************/
+#define CBR_REGION_NORMAL_BLOCK_NUM [AUTOGEN_IMG_CFG_H_Gen_CBR_NORMAL_BLOCK_NUM]
+
+#define CBR_REGION_SPARE_BLOCK_NUM [AUTOGEN_IMG_CFG_H_Gen_CBR_SPARE_BLOCK_NUM]
+
+
+/****************************************************************************
+ Following definitions are used for searching MAUI ROM in the flash
+
+ Item 1. The address in the flash where MAUI binary resides
+
+ Item 2. The address in the flash where Factory binary resides
+
+ ****************************************************************************/
+#define MAUI_ROM_START_ADDR 0x00020000
+
+#define FACTORY_ROM_START_ADDR 0x00010000
+
+
+#endif /* __CUSTOM_IMG_CONFIG_H__ */
diff --git a/mcu/custom/system/Template/custom_mmu_conf.h.template b/mcu/custom/system/Template/custom_mmu_conf.h.template
new file mode 100644
index 0000000..3a8dd62
--- /dev/null
+++ b/mcu/custom/system/Template/custom_mmu_conf.h.template
@@ -0,0 +1,73 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2006
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * custom_scatstruct.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file declares MMU table
+ *
+ * Author:
+ * -------
+ * Tero Jarko (mtk00602) system auto generator u0.21_UMOLY + sysGenUtility LR12_v0.04
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * $Revision$
+ * $Modtime$
+ * $Log$
+ *
+ * 02 23 2016 tero.jarkko
+ * [MOLY00165406] [LR12][SystemService][Auto-Gen][Internal Refinement][MT6292][MMU]Generate MMU configuration by AutoGen
+ *
+ * Added generated MMU table info
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#define MMU_TABLE /*Even:|ADDREDSS | SIZE| CCA |CORE| Odd:|ADDREDSS | SIZE| CCA |CORE|*/ \
+[AUTOGEN_SCAT_H_Gen_MMU_TABLE]
+
+#define MMU_TABLE_SIZE [AUTOGEN_SCAT_H_Gen_MMU_TABLE_SIZE]
diff --git a/mcu/custom/system/Template/custom_scatstruct.c.template b/mcu/custom/system/Template/custom_scatstruct.c.template
new file mode 100644
index 0000000..8b5610d
--- /dev/null
+++ b/mcu/custom/system/Template/custom_scatstruct.c.template
@@ -0,0 +1,2050 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2006
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * custom_scatstruct.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file provides the scatter file dependent APIs
+ *
+ * Author:
+ * -------
+ * Claudia Lo (mtk01876) [AUTOGEN_GenVersion]
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * $Revision$
+ * $Modtime$
+ * $Log$
+ *
+ * 09 03 2020 yao.liu
+ * [MOLY00566717] [Gen97] Add a function to query if the region is on EMI.
+ * [NR15.R3.MP] Add an API to query if the region is on EMI.
+ *
+ * 12 03 2019 yao.liu
+ * [MOLY00463184] [System Service][MOLY Kernel Internal Request] Enhance exception flow security
+ * [VMOLY] Add custom_query_MCURO_HWRW_region API for exception.
+ *
+ * 09 03 2019 yao.liu
+ * [MOLY00434510] Memory Dump 2.0
+ * [VMOLY] Memory dump 2.0 - SYS_MEM part.
+ *
+ * 08 09 2019 yao.liu
+ * [MOLY00430396] [Build error] Solve Mercury build error of custom_scatstruct.c.
+ * [Vmoly]Solve build error of custom_scatstruct.c.
+ *
+ * 05 23 2019 yao.liu
+ * [MOLY00408580] [VMOLY] Linker script changes for LTO.
+ * [VMOLY] Adjust lds for LTO feature.
+ *
+ * 04 29 2019 yao.liu
+ * [MOLY00383168] [System Service][MOLY Kernel Internal Request] Merge minidump code from UMOLYE to VMOLY
+ * [VMOLY] Porting mini dump.
+ *
+ * 01 14 2019 frank.hu
+ * [MOLY00363660] [Auto-Gen] Merge 2 links to 1 link to save more build time.
+ *
+ * VMOLY.DEV.SEPT - Merge 2Links -> 1Link.
+ *
+ * 10 23 2018 frank.hu
+ * [MOLY00360260] VMOLY GEN97 Eiger Build error.
+ * resolve Gen97 build error.
+ *
+ * 10 22 2018 tero.jarkko
+ * [MOLY00356148] [Gen97][SystemService][AutoGen]Provided SIB area query API
+ *
+ * .
+ *
+ * 10 18 2018 tero.jarkko
+ * [MOLY00359671] [Gen97][SystemService][AutoGen]SS_EXT_CSIF and NL1_EXT_CSIF API implementation
+ *
+ * .
+ *
+ * 09 28 2018 tero.jarkko
+ * [MOLY00356148] [Gen97][SystemService][AutoGen]Provided SIB area query API
+ *
+ * .
+ *
+ * 09 21 2018 tero.jarkko
+ * [MOLY00330320] [Gen97][SystemService][AutoGen] Adjusted MT6297 memory map
+ *
+ * .
+ *
+ * 08 14 2018 tero.jarkko
+ * [MOLY00345457] [Gen97][SystemService][AutoGen]MT6297 merge
+ *
+ * .
+ *
+ * 03 12 2018 tero.jarkko
+ * [MOLY00313013] [Gen97][SystemService][Auto-Gen]Fixed MT6297 build error
+ *
+ * .
+ *
+ * 02 27 2018 tero.jarkko
+ * [MOLY00310353] [Gen95][System Service][Auto-Gen]Static L2C locked input sections are placed into EMI
+ *
+ * .
+ *
+ * 12 17 2017 tero.jarkko
+ * [MOLY00296714] [SystemService][Auto-Gen][MT3967] Autogen support for MT3967
+ *
+ * .
+ *
+ * 12 17 2017 tero.jarkko
+ * [MOLY00296714] [SystemService][Auto-Gen][MT3967] Autogen support for MT3967
+ *
+ * .
+ *
+ * 12 17 2017 tero.jarkko
+ * [MOLY00296714] [SystemService][Auto-Gen][MT3967] Autogen support for MT3967
+ *
+ * .
+ *
+ * 12 17 2017 tero.jarkko
+ * [MOLY00296714] [SystemService][Auto-Gen][MT3967] Autogen support for MT3967
+ *
+ * .
+ *
+ * 11 08 2017 tero.jarkko
+ * [MOLY00288451] [MT6295M][SystemService][Autogen] Fixed MT6295M build error
+ *
+ * .
+ *
+ * 09 08 2017 tero.jarkko
+ * [MOLY00268904] [System Service][MOLY Kernel Internal Request]for fatal 0x9, modify custom_query_code_region to work similarly as custom_query_dump_region.
+ *
+ * .
+ *
+ * 08 16 2017 carl.kao
+ * [MOLY00247878] [Gen93] [SystemService] [Auto-Gen] [DSMGR] Fix SYS_SVC/DSMGR build warning
+ * .
+ *
+ * 07 25 2017 carl.kao
+ * [MOLY00265930] [Gen93] [SystemService] [Auto-Gen] AMMS DRDI stage 3 (integrate AMMS with MD DRDI)
+ * [AMMS STAGE 3/DRDI] main code
+ *
+ * 07 05 2017 tero.jarkko
+ * [MOLY00258516] [Gen93][SystemService][Auto-Gen]custom query code region generated by autogen
+ *
+ * .
+ *
+ * 06 28 2017 tero.jarkko
+ * [MOLY00260386] [Gen93][AutoGen]Remove custom_scatstruct.c build warning
+ *
+ * .
+ *
+ * 05 10 2017 tero.jarkko
+ * [MOLY00248620] [Gen93][SystemService][Auto-Gen] Assert in Dynamic L2C loack area seen as breakpoint
+ *
+ * .
+ *
+ * 05 04 2017 carl.kao
+ * [MOLY00246779] [BIANCO] Enable ASM addon,SWTR and stream mode
+ * Remove unused API : custom_get_MaxAvailableMemorySegment
+ *
+ * 04 07 2017 carl.kao
+ * [MOLY00240094] [Gen93] [SystemService] [Auto-Gen] Refine setting of EMI RMPU for Gen93
+ * .
+ *
+ * 03 28 2017 tero.jarkko
+ * [MOLY00238285] [Gen93/LR13][SystemService][Auto-Gen][MT6763]Custom query code region for ADT
+ *
+ * .
+ *
+ * 02 13 2017 tero.jarkko
+ * [MOLY00229329] [Gen93/LR13][SystemService][Auto-Gen]L2C code query fixed
+ *
+ * .
+ *
+ * 01 25 2017 hw.jheng
+ * [MOLY00226817] [System Service] Shrink SWLA Size for Gen93 2 Cores, total 4 MB.
+ *
+ * 01 23 2017 tero.jarkko
+ * [MOLY00226093] [Gen93/LR13][SystemService][Auto-Gen][Bianco Bring-up]Modify SPRAM size and address
+ *
+ * .
+ *
+ * 01 18 2017 tero.jarkko
+ * [MOLY00225631] [Gen93/LR13][SystemService][Auto-Gen]Added L2C code check
+ *
+ * .
+ *
+ * 01 04 2017 kari.suvanto
+ * [MOLY00196319] [System Service][MOLY Kernel Internal Request]Umoly merge
+ * sst: fix nested exception at cache invalidation
+ *
+ * 10 27 2016 tero.jarkko
+ * [MOLY00187425] [LR12][SystemService][Auto-Gen] custom_query_code_region refined
+ *
+ * .
+ *
+ * 09 30 2016 carl.kao
+ * [MOLY00205905] [LR12][SystemService][Auto-Gen] Whitney TCM only load
+ * .
+ *
+ * 09 06 2016 tero.jarkko
+ * [MOLY00201797] [Gen93/LR13][SystemService][Auto-Gen] Hardcode lds for Gen93 layout
+ *
+ * .
+ *
+ * 06 28 2016 carl.kao
+ * [MOLY00179472] [SYSTEM SERVICE][KAL] Fix KAL build warning
+ * Fix CUSTOM lib build warning
+ *
+ * 06 20 2016 carl.kao
+ * [MOLY00174068] [LR13][SystemService][Auto-Gen] 93 lds
+ * New 93 image layout for MPU setting
+ *
+ * 05 23 2016 carl.kao
+ * [MOLY00180706] [LR12] [SystemService] [Auto-Gen] SWLA space requirement
+ * SWLA 3MB -> 6MB (still using NC)
+ *
+ * 04 13 2016 carl.kao
+ * [MOLY00174068] [LR13][SystemService][Auto-Gen] 93 lds
+ * Do not use ISPRAM2, DSPRAM2 and L2SRAM in 93
+ *
+ * 03 11 2016 carl.kao
+ * [MOLY00160518] [LR12] [SYSTEM SERVICE] [KAL] [IPC] Fix converity warning in UMOLY TRUNK
+ * .
+ *
+ * 03 04 2016 carl.kao
+ * [MOLY00146830] [System Service][MOLY Kernel Internal Request][LR12] SMP SWLA/SWTR modification
+ * .
+ *
+ * 03 03 2016 carl.kao
+ * [MOLY00167331] [LR12] [SystemService] [Auto-Gen] [DSMGR] Set DSPRAM and ISPRAM to DSM_UNINIT_STAMP during boot
+ * .
+ *
+ * 02 25 2016 tero.jarkko
+ * [MOLY00166535] [LR12][SystemService][Auto-Gen] [Internal Refinement][MT6292] custom_query_dump_region
+ *
+ * .
+ *
+ * 02 24 2016 tero.jarkko
+ * [MOLY00164073] [LR12][SystemService][Auto-Gen] [Internal Refinement][MT6292] [sysGen2] Generate custom_scatstruct.c using sysGen2
+ *
+ * Added L2SRAM_L2NC and L2SRAM_L2C functions
+ *
+ * 02 16 2016 tero.jarkko
+ * [MOLY00165076] [LR12][SystemService][Auto-Gen] [Internal Refinement][MT6292] [sysGen2] Support custom_query_dynamic_code_region
+ *
+ * .
+ *
+ * 02 04 2016 tero.jarkko
+ * [MOLY00164073] [LR12][SystemService][Auto-Gen] [Internal Refinement][MT6292] [sysGen2] Generate custom_scatstruct.c using sysGen2
+ *
+ * custom_ram_mk_info
+ *
+ * 02 03 2016 tero.jarkko
+ * [MOLY00164073] [LR12][SystemService][Auto-Gen] [Internal Refinement][MT6292] [sysGen2] Generate custom_scatstruct.c using sysGen2
+ *
+ * L2SRAM_L2NC base and length functions added
+ *
+ * 02 02 2016 tero.jarkko
+ * [MOLY00164073] [LR12][SystemService][Auto-Gen] [Internal Refinement][MT6292] [sysGen2] Generate custom_scatstruct.c using sysGen2
+ *
+ * .
+ *
+ * 01 18 2016 carl.kao
+ * [MOLY00159955] [LR12][SystemService][Auto-Gen] remove core 3 SPRAM and make SPRAM APIs more robust
+ * .
+ *
+ * 01 14 2016 tero.jarkko
+ * [MOLY00160038] [LR12][SystemService][Auto-Gen] [Internal Refinement][MT6292] Support for custom_get_dump_info
+ *
+ * Fixed custom_get_dump_info dynamically cached default uncached region comparation
+ *
+ * 01 13 2016 tero.jarkko
+ * [MOLY00160038] [LR12][SystemService][Auto-Gen] [Internal Refinement][MT6292] Support for custom_get_dump_info
+ *
+ * Added support for core specific cached address info in custom_get_dump_info
+ *
+ * 01 12 2016 qmei.yang
+ * [MOLY00151351] [SystemService][DebuggingSuite][Internal Refinement][92] Support full exception flow framework
+ *
+ * .
+ *
+ * 01 11 2016 qmei.yang
+ * [MOLY00151351] [SystemService][DebuggingSuite][Internal Refinement][92] Support full exception flow framework
+ * .
+ *
+ * 12 29 2015 carl.kao
+ * [MOLY00154292] [LR12][SystemService][Auto-Gen] Enable the feature: embed VoLTE core bin address and size information to MD header
+ * .
+ *
+ * 12 23 2015 carl.kao
+ * [MOLY00154292] [LR12][SystemService][Auto-Gen] Enable the feature: embed VoLTE core bin address and size information to MD header
+ * Rename CACHED_EXTSRAM_VOLTE_CORE_ZI to CACHED_EXTSRAM_ZI_VOLTE_CORE3
+ *
+ * 11 12 2015 carl.kao
+ * [MOLY00148842] [LR12][SystemService][Auto-Gen] 92 lds, for Full region ready, Code in Right Location
+ * Support VoLTE core section
+ *
+ * 11 11 2015 carl.kao
+ * [MOLY00148842] [LR12][SystemService][Auto-Gen] 92 lds, for Full region ready, Code in Right Location
+ * New image layout for "Full region ready, Code in Right Location"
+ *
+ * 09 21 2015 carl.kao
+ * [MOLY00136979] [92][SYSTEM SERVICE][KAL][IPC] Fix KAL build fail
+ * custom_scat
+ *
+ * 08 28 2015 carl.kao
+ * [MOLY00136979] [92][SYSTEM SERVICE][KAL][IPC] Fix KAL build fail
+ * .
+ *
+ * 08 26 2015 carl.kao
+ * [MOLY00138715] [92] [SystemService][Auto-Gen] Remove legacy linker symbol
+ * .
+ *
+ * 07 07 2015 carl.kao
+ * [MOLY00126388] [UMOLY] [SYSTEM SERVICE][KAL][DSMGR] Add dsmgr to pcore
+ * .
+ *
+ * 07 03 2015 carl.kao
+ * [MOLY00125736] [MT6755][BRINGUP_FIRSTCALL] [SystemService][Auto-Gen] add custom_get_L1CORE_INTSRAM_Base and custom_get_L1CORE_INTSRAM_End
+ * get l1core tcm base and length
+ *
+ * 06 15 2015 carl.kao
+ * [MOLY00121235] [TK6291] [SystemService][Auto-Gen][Request For Design Change] Query TCM base and end address
+ * .
+ *
+ * 04 16 2015 carl.kao
+ * [MOLY00106652] [TK6291] [SystemService][Auto-Gen] add a dynamic switchable default cached MCU-RW, HW-RW section
+ * add 4 sections for EMI RMPU
+ * 1) (MCU RO, MDHW RW) DNC
+ * 2) (MCU RO, MDHW RW) NC
+ * 3) (MCU RW, MDHW RW) DNC
+ * 4) (MCU RW, MDHW RW) NC
+ *
+ * 02 24 2015 qmei.yang
+ * [MOLY00096717] [SystemService][DebuggingSuite][Internal Refinement] Support to dump l1core l2sram
+ * .
+ *
+ * 02 24 2015 qmei.yang
+ * [MOLY00096717] [SystemService][DebuggingSuite][Internal Refinement] Support to dump l1core l2sram
+ * .
+ *
+ * 12 23 2014 carl.kao
+ * [MOLY00088578] [TK6291] [SystemService] [Auto-Gen] Support L2SRAM section (in L1CORE)
+ * aa.
+ *
+ * 12 22 2014 carl.kao
+ * [MOLY00087532] [Denali-1] [SystemService][Auto-Gen] Refactor AutoGen Code and Remove Legacy Code
+ * .
+ *
+ * 12 22 2014 carl.kao
+ * [MOLY00087532] [Denali-1] [SystemService][Auto-Gen] Refactor AutoGen Code and Remove Legacy Code
+ * .
+ *
+ * 12 02 2014 carl.kao
+ * [MOLY00086328] [TK6291] [SystemService][Auto-Gen] Refine custom_get_l1core_dump_info()
+ * .
+ *
+ * 11 28 2014 carl.kao
+ * [MOLY00085983] [TK6291] [SystemService][Auto-Gen] Merge ATCM and BTCM as a single TCM
+ * .
+ *
+ * 11 15 2014 carl.kao
+ * [MOLY00083302] [SYSTEM SERVICE][TASK CONFIG] Merge code from MT6291_DEV
+ * mcu/pcore
+ *
+ * 11 06 2014 carl.kao
+ * [MOLY00083492] [TK6291] [SystemService][Auto-Gen][Request For Design Change] Add custom_get_MD_RAMEnd() for MPU
+ * Add custom_get_MD_RAMEnd() for PCORE MPU
+ *
+ * 09 11 2014 qmei.yang
+ * [MOLY00078623] [SystemService][DebuggingSuite][Internal Refinement][MT6291] Support memory dump
+ * .
+ *
+ * 07 31 2014 carl.kao
+ * [MOLY00074124] [SystemService][DebuggingSuite][MT6291] Support multi-core exception
+ * dump L1CORE region by PCORE
+ *
+ * 04 07 2014 carl.kao
+ * [MOLY00061797] [SYSTEM SERVICE] porting features from U3G_TK6280_DEV and MOLY.U3G.90IT.DEV branches
+ * 9) Rename "l1dsp" to "l1core", "L1DSP" to "L1CORE"
+ *
+ * 04 02 2014 carl.kao
+ * [MOLY00061134] [SYSTEM SERVICE][AutoGen] AutoGen for MT6291
+ * 1) pcore sysGen2.
+ * 2) Remove useless secure region query API
+ *
+ * 06 25 2013 qmei.yang
+ * [MOLY00025806] [SystemService][Auto-Gen][Request For Design Change] Support COPRO
+ * support COPRO_arm7's L1Cache
+ *
+ * 04 26 2013 qmei.yang
+ * [MOLY00020542] [SystemService][MOLY] To remove useless input sections by the request
+ * support SWLA space as well
+ *
+ * 04 09 2013 qmei.yang
+ * [MOLY00013707] [SystemService][Auto-Gen][Request For Design Change] Support code integrity for offline SST
+ * .
+ *
+ * 10 31 2012 qmei.yang
+ * [MOLY00005605] [SystemService][Auto-Gen][Request For Design Change][sysgen2] Create new API: custom_get_DSPTXRX_MaxSize()
+ * .
+ *
+ * 08 27 2012 qmei.yang
+ * [MOLY00001774] [SystemService][Region_Init][Internal Refinement] Support MT6577 region init and remove useless regions and compile option
+ * .
+ *
+ * 07 26 2012 qmei.yang
+ * [MOLY00001213] [SystemService][Auto-Gen][Internal Refinement] Fix GCC warnings
+ * .
+ *
+ * 05 28 2012 qmei.yang
+ * [MAUI_03164047] [SystemService][Auto-Gen][GCC][Internal Refinement] support AutoGen on GCC
+ * Support GCC to use attribute instead of pragma
+ *
+ * 05 10 2012 qmei.yang
+ * [MAUI_03182425] [Reason]sync codes between modem_dev and 11B
+ * .
+ *
+ * 04 16 2012 qmei.yang
+ * [MAUI_03169203] [SystemService][Auto-Gen][Request For Design Change] Add 3 objs into TCM and put 3 functions to TCM on MT6280
+ * add 3 functions to TCM
+ *
+ * 03 08 2012 qmei.yang
+ * [MAUI_03145378] [SystemService][Auto-Gen][Sys Gen][scatGen][Internal Refinement] Phase in AutoGen new flow to support GCC
+ * .
+ *
+ * 02 15 2012 qmei.yang
+ * [MAUI_03130553] [SystemService][Auto-Gen][Sys Gen][scatGen][Internal Refinement] Support cmmgen sync with sysgen2
+ * Modify custom_query_dump_region() API
+ *
+ * 02 15 2012 qmei.yang
+ * [MAUI_03130553] [SystemService][Auto-Gen][Sys Gen][scatGen][Internal Refinement] Support cmmgen sync with sysgen2
+ * Modify custom_query_dump_region() API
+ *
+ * 01 31 2012 qmei.yang
+ * [MAUI_03120516] [SystemService][Auto-Gen][Sys Gen][scatGen][Internal Refinement] Refactory sysgen2.pl
+ * .
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#include "kal_general_types.h"
+#include "kal_iram_section_defs.h"
+
+#include "init.h"
+#include "cache_sw_int.h"
+#include "cache_sw.h"
+#include "custom_scatstruct.h"
+
+#ifdef __MTK_TARGET__
+extern kal_uint32 custom_get_fat_addr();
+extern kal_uint32 custom_get_fat_len();
+extern kal_uint32 INT_RetrieveFlashBaseAddr(void);
+/*******************************************************************************
+ * Define import global data.
+ *******************************************************************************/
+
+[AUTOGEN_SCAT_C_Gen_REGION_SYMBOL]
+
+
+#define NUM_AVAILABLE_CORE (2)
+
+/***temp************************************************************************/
+DECLARE_NOINLINE kal_uint32 scat_max(kal_uint32 A1, kal_uint32 A2)
+{
+ return ( ((A1)>=(A2)) ? (A1) : (A2) );
+}
+
+#if !(defined(__MD95__) || defined(__MD97__) || defined(__MD97P__))
+#define LoadBase(ID, spram_index) Load$$##ID##SPRAM##spram_index##$$Base
+#define ImageBase(ID, spram_index) Image$$##ID##SPRAM##spram_index##$$Base
+#define ImageLimit(ID, spram_index) Image$$##ID##SPRAM##spram_index##$$Limit
+#define ImageLength(ID, spram_index) Image$$##ID##SPRAM##spram_index##$$Length
+#define ImagePhyLength(ID, spram_index) Image$$##ID##SPRAM##spram_index##_PHYSICAL_BOUNDARY$$Length
+#define ImageZIBase(ID, spram_index) Image$$##ID##SPRAM##spram_index##$$ZI$$Base
+#define ImageZILimit(ID, spram_index) Image$$##ID##SPRAM##spram_index##$$ZI$$Limit
+#define ImageZILength(ID, spram_index) Image$$##ID##SPRAM##spram_index##$$ZI$$Length
+
+
+#define SPRAM_LINKER_SYMBOL_DEFINE(spram_index) \
+ extern kal_uint32 LoadBase(I, spram_index); \
+ extern kal_uint32 ImageBase(I, spram_index); \
+ extern kal_uint32 ImageLimit(I, spram_index); \
+ extern kal_uint32 ImageLength(I, spram_index); \
+ extern kal_uint32 LoadBase(D, spram_index); \
+ extern kal_uint32 ImageBase(D, spram_index); \
+ extern kal_uint32 ImageLimit(D, spram_index); \
+ extern kal_uint32 ImageLength(D, spram_index); \
+ extern kal_uint32 ImageZIBase(D, spram_index); \
+ extern kal_uint32 ImageZILimit(D, spram_index); \
+ extern kal_uint32 ImageZILength(D, spram_index);
+
+
+SPRAM_LINKER_SYMBOL_DEFINE(0)
+SPRAM_LINKER_SYMBOL_DEFINE(1)
+
+
+static const kal_uint32 _ispram_load_addr[NUM_AVAILABLE_CORE] = {(kal_uint32)&LoadBase(I,0), (kal_uint32)&LoadBase(I,1)};
+static const kal_uint32 _ispram_start_addr[NUM_AVAILABLE_CORE] = {(kal_uint32)&ImageBase(I,0), (kal_uint32)&ImageBase(I,1)};
+static const kal_uint32 _ispram_end_addr[NUM_AVAILABLE_CORE] = {(kal_uint32)&ImageLimit(I,0), (kal_uint32)&ImageLimit(I,1)};
+
+static const kal_uint32 _dspram_load_addr[NUM_AVAILABLE_CORE] = {(kal_uint32)&LoadBase(D,0), (kal_uint32)&LoadBase(D,1)};
+static const kal_uint32 _dspram_start_addr[NUM_AVAILABLE_CORE] = {(kal_uint32)&ImageBase(D,0), (kal_uint32)&ImageBase(D,1)};
+static const kal_uint32 _dspram_end_addr[NUM_AVAILABLE_CORE] = {(kal_uint32)&ImageLimit(D,0), (kal_uint32)&ImageLimit(D,1)};
+static const kal_uint32 _dspram_zi_start_addr[NUM_AVAILABLE_CORE]= {(kal_uint32)&ImageZIBase(D,0), (kal_uint32)&ImageZIBase(D,1)};
+static const kal_uint32 _dspram_zi_end_addr[NUM_AVAILABLE_CORE] = {(kal_uint32)&ImageZILimit(D,0), (kal_uint32)&ImageZILimit(D,1)};
+static const kal_uint32 _dspram_phy_length[NUM_AVAILABLE_CORE] = {(kal_uint32)&ImagePhyLength(D,0), (kal_uint32)&ImagePhyLength(D,1)};
+#endif
+[AUTOGEN_SCAT_C_Gen_ARRAY_DYNAMIC_CODE_REGION]
+
+[AUTOGEN_SCAT_C_Gen_ARRAY_CODE_REGIONS]
+
+[AUTOGEN_SCAT_C_Gen_ARRAY_MCURO_HWRW_REGIONS]
+/***temp************************************************************************/
+#if !(defined(__MD97__) || defined(__MD97P__))
+typedef struct dump_info_str {
+ kal_uint32 start;
+ kal_uint32 end;
+ kal_uint8 op;
+
+}dump_info_str;
+
+static dump_info_str dump_info[] = {
+ [AUTOGEN_SCAT_C_Gen_TEMPLATE_CORE0_CACHEABLE_ASSING],
+ [AUTOGEN_SCAT_C_Gen_TEMPLATE_CORE1_CACHEABLE_ASSING]
+};
+#endif
+/*******************************************************************************
+ * Define import global data.
+ *******************************************************************************/
+
+#if defined(__ARM9_MMU__) || defined(__ARM11_MMU__)
+
+/* define pool size for fine page table and coarse page table */
+/* CPT : 1 (TCM)
+ * + 4 * (number of continous dynamic CACHEABLE default non-cacheable region)
+ * + 4 * (number of continous dynamic CACHEABLE default cacheable region)
+ * + 4 * (number of continous CACHED region)
+ * + 4 * (number of continous CACHED code region)
+ * + 2 * (number of non-cacched EXTSRAM RW region)
+ * + 2 * (number of non-cacched EXTSRAM RO region)
+ * + 1 (DSP_TX DSP_RX ... )
+ * + (number of ROM - 1)
+ * + 2 (at the beginning and at the end of FAT)
+ * */
+#if defined(__ARM9_MMU__)
+[AUTOGEN_SCAT_C_Gen_ARM9_PT_POOLSIZE]
+#elif defined(__ARM11_MMU__)
+[AUTOGEN_SCAT_C_Gen_ARM11_PT_POOLSIZE]
+#endif /* __ARM11_MMU__ */
+
+#if defined(__ARM9_MMU__)
+/* memory pool of fine page table */
+#if (MAX_FPT_POOL_SIZE > 0)
+__PT_Aligned(4 * 1024) static kal_uint32 FPT_POOL[MAX_FPT_POOL_SIZE / 4];
+#endif /* MAX_FPT_POOL_SIZE > 0 */
+#endif /* __ARM9_MMU__ */
+/* memory pool of coarse page table */
+__PT_Aligned(1024) static kal_uint32 CPT_POOL[MAX_CPT_POOL_SIZE / 4];
+
+#endif /* __ARM9_MMU__ || __ARM11_MMU__ */
+
+#if defined(__DYNAMIC_SWITCH_CACHEABILITY__)
+
+[AUTOGEN_SCAT_C_Gen_ARRAY_EXTSRAM_REGION]
+
+#endif /* __DYNAMIC_SWITCH_CACHEABILITY__ */
+
+#if defined(__MD97__) || defined(__MD97P__)
+static EXTSRAM_REGION_INFO_T SIB_AREA_REGION[2] = {{ (kal_uint32)&Image$$SIB_AREA$$Base, (kal_uint32)&Image$$SIB_AREA$$Length},{0,0}};
+#endif
+
+#if defined(__ARM9_MMU__) || defined(__ARM11_MMU__)
+#if defined(__ARM9_MMU__)
+/*************************************************************************
+* FUNCTION
+* custom_query_fpt_pool
+*
+* DESCRIPTION
+* This function gets the address and size of fpt pool.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_int32 custom_query_fpt_pool(kal_uint32 **pool, kal_uint32 *pool_size)
+{
+#if (MAX_FPT_POOL_SIZE > 0)
+ *pool = FPT_POOL;
+ *pool_size = MAX_FPT_POOL_SIZE;
+#else /* MAX_FPT_POOL_SIZE > 0 */
+ *pool = NULL;
+ *pool_size = 0;
+#endif /* MAX_FPT_POOL_SIZE > 0 */
+
+ return 0;
+}
+#endif /* __ARM9_MMU__ */
+
+/*************************************************************************
+* FUNCTION
+* custom_query_cpt_pool
+*
+* DESCRIPTION
+* This function gets the address and size of cpt pool.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_int32 custom_query_cpt_pool(kal_uint32 **pool, kal_uint32 *pool_size)
+{
+ *pool = CPT_POOL;
+ *pool_size = MAX_CPT_POOL_SIZE;
+
+ return 0;
+}
+
+#endif /* __ARM9_MMU__ || __ARM11_MMU__ */
+
+#if defined(__DYNAMIC_SWITCH_CACHEABILITY__)
+
+/************************************************************************
+* FUNCTION
+* custom_query_dynamic_cached_extsram_default_nc_region
+*
+* DESCRIPTION
+* This function gets info of dynamic cached default non-cached EXT SRAM regions.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_int32 custom_query_dynamic_cached_extsram_default_nc_region(EXTSRAM_REGION_INFO_T **region)
+{
+ *region = DYNAMIC_CACHED_EXTSRAM_DNC_REGION;
+
+ return 0;
+}
+
+/************************************************************************
+* FUNCTION
+* custom_query_dynamic_cached_extsram_default_c_region
+*
+* DESCRIPTION
+* This function gets info of dynamic cached default cached EXT SRAM regions.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_int32 custom_query_dynamic_cached_extsram_default_c_region(EXTSRAM_REGION_INFO_T **region)
+{
+ *region = DYNAMIC_CACHED_EXTSRAM_DC_REGION;
+
+ return 0;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_query_cached_extsram_region
+*
+* DESCRIPTION
+* This function gets info of cached EXT SRAM regions.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_int32 custom_query_cached_extsram_region(EXTSRAM_REGION_INFO_T **region)
+{
+ *region = CACHED_EXTSRAM_REGION;
+
+ return 0;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_query_cached_extsram_code_region
+*
+* DESCRIPTION
+* This function gets info of cached EXT SRAM code regions.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+__TCMROCODE
+kal_int32 custom_query_cached_extsram_code_region(EXTSRAM_REGION_INFO_T **region)
+{
+ *region = CACHED_EXTSRAM_CODE_REGION;
+
+ return 0;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_query_noncached_extsram_region
+*
+* DESCRIPTION
+* This function gets info of non-cached RW EXT SRAM regions.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+__TCMROCODE
+kal_int32 custom_query_noncached_extsram_region(EXTSRAM_REGION_INFO_T **region)
+{
+ *region = NONCACHED_EXTSRAM_REGION;
+
+ return 0;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_query_noncached_extsram_ro_region
+*
+* DESCRIPTION
+* This function gets info of non-cached RO EXT SRAM regions.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+__TCMROCODE
+kal_int32 custom_query_noncached_extsram_ro_region(EXTSRAM_REGION_INFO_T **region)
+{
+ *region = NONCACHED_EXTSRAM_RO_REGION;
+
+ return 0;
+}
+#endif /* __DYNAMIC_SWITCH_CACHEABILITY__ */
+
+/*************************************************************************
+* FUNCTION
+* custom_query_dynamic_code_region
+*
+* DESCRIPTION
+* This function gets info of dynamic code regions.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_int32 custom_query_dynamic_code_region(DYNAMIC_CODE_MEM_T core_id,DYNAMIC_CODE_REGION_INFO_T **region)
+{
+ switch(core_id)
+ {
+ case DC_ISPRAM0:
+ *region = (DYNAMIC_CODE_REGION_INFO_T *)ISPRAM0_CODE_SECTIONS;
+ break;
+ case DC_ISPRAM1:
+ *region = (DYNAMIC_CODE_REGION_INFO_T *)ISPRAM1_CODE_SECTIONS;
+ break;
+ default:
+ *region = (DYNAMIC_CODE_REGION_INFO_T *)0;
+ return -1;
+ }
+ return 0;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* custom_get_1st_ROM_ROMBase
+*
+* DESCRIPTION
+* Retrieve the base address of the 1st ROM (Load View)
+* This function must sync with scatter file structure
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_1st_ROM_ROMBase(void)
+{
+ kal_uint32 address = (kal_uint32)&Image$$[AUTOGEN_SCAT_C_Gen_RegionName_EV_1stROM_BEGIN]$$Base;
+ address = MAP2CREGPA(address);
+ return address;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_1st_ROM_ROMLength
+*
+* DESCRIPTION
+* Retrieve the actual ROM length of 1st ROM (Load View)
+* This function must sync with scatter file structure
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_1st_ROM_ROMLength(void)
+{
+ kal_uint32 ROMLength = 0;
+ kal_uint32 ROM_Regions[] = {
+[AUTOGEN_SCAT_C_Gen_TEMPLATE_1stROM_LENGTH]};
+ kal_uint32 index;
+ kal_uint32 address = 0 ;
+ kal_uint32 length = 0;
+ for(index = 0; index < (sizeof(ROM_Regions)/sizeof(kal_uint32));index=index+2){
+ if (!index) {
+ if ( (MAP2CREGPA(ROM_Regions[index])+MAP2CREGPA(ROM_Regions[index+1])) > (address+length) ) {
+ address = MAP2CREGPA(ROM_Regions[index]);
+ length = MAP2CREGPA(ROM_Regions[index+1]);
+ }
+ } else {
+ address = MAP2CREGPA(ROM_Regions[index]);
+ length = MAP2CREGPA(ROM_Regions[index+1]);
+ }
+ }
+
+ ROMLength = address + length;
+ return ROMLength;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_1st_ROM_RAMBase
+*
+* DESCRIPTION
+* Retrieve the RAM base address of the 1st ROM (Load View)
+* This function must sync with scatter file structure
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_1st_ROM_RAMBase(void)
+{
+ return [AUTOGEN_SCAT_C_Gen_TEMPLATE_1stRAM_BEGIN];
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_1st_ROM_RAMLength
+*
+* DESCRIPTION
+* Retrieve the actual RAM length of 1st ROM (Load View)
+* This function must sync with scatter file structure
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_1st_ROM_RAMLength(void)
+{
+ kal_uint32 RAMLength = 0;
+
+ return RAMLength;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_1st_ROM_RAMEnd
+*
+* DESCRIPTION
+* Retrieve the actual end address of 1st ROM (Exec View)
+* This function must sync with scatter file structure
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_1st_ROM_RAMEnd(void)
+{
+ kal_uint32 EndAddr = 0;
+
+ EndAddr = (kal_uint32)&Image$$[AUTOGEN_SCAT_C_Gen_RegionName_EV_1stRAM_END]$$ZI$$Limit;
+
+ return EndAddr;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_1st_ROM_LoadEnd
+*
+* DESCRIPTION
+* Retrieve the actual end address of 1st ROM (Load View)
+* This function must sync with scatter file structure
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_1st_ROM_LoadEnd(void)
+{
+ kal_uint32 EndAddr = 0;
+
+ EndAddr = (kal_uint32)&Load$$[AUTOGEN_SCAT_C_Gen_RegionName_EV_1stROM_END]$$Base;
+ EndAddr += (kal_uint32)&Image$$[AUTOGEN_SCAT_C_Gen_RegionName_EV_1stROM_END]$$Length;
+
+ return EndAddr;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_1st_ROM_MCURWBase
+*
+* DESCRIPTION
+* Retrieve the base address for MDMCU_RW MDHR_RO base, keyword, EXTSRAM and non-MCURO
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_1st_ROM_MCURWBase(void)
+{
+ kal_uint32 BaseAddr = 0;
+
+ BaseAddr = (kal_uint32)&Image$$[AUTOGEN_SCAT_C_Gen_TEMPLATE_1st_MCURW_SECTION]$$Base;
+
+ return BaseAddr;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* custom_get_ISPRAM_Load_Base
+*
+* DESCRIPTION
+* Retrieve the base view address of ISPRAM by core id
+*
+* PARAMETERS
+* core id
+*
+* RETURNS
+*
+*************************************************************************/
+kal_status custom_get_ISPRAM_Load_Base(kal_uint8 core_id, kal_uint32 *ret_addr)
+{
+#if !(defined(__MD95__) || defined(__MD97__) || defined(__MD97P__))
+ if (core_id<NUM_AVAILABLE_CORE)
+ {
+ *ret_addr = _ispram_load_addr[core_id];
+ return KAL_SUCCESS;
+ }
+#endif
+ *ret_addr = 0;
+ return KAL_ERROR;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_ISPRAM_CODE_Base
+*
+* DESCRIPTION
+* Retrieve the execution view base address of ISPRAM code by core id
+*
+* PARAMETERS
+* core id
+*
+* RETURNS
+*
+*************************************************************************/
+kal_status custom_get_ISPRAM_CODE_Base(kal_uint8 core_id, kal_uint32 *ret_addr)
+{
+#if !(defined(__MD95__) || defined(__MD97__) || defined(__MD97P__))
+ if (core_id<NUM_AVAILABLE_CORE)
+ {
+ *ret_addr = _ispram_start_addr[core_id];
+ return KAL_SUCCESS;
+ }
+#endif
+ *ret_addr = 0;
+ return KAL_ERROR;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_ISPRAM_End
+*
+* DESCRIPTION
+* Retrieve the execution view end address of ISPRAM code by core id
+*
+* PARAMETERS
+* core id
+*
+* RETURNS
+*
+*************************************************************************/
+kal_status custom_get_ISPRAM_CODE_End(kal_uint8 core_id, kal_uint32 *ret_addr)
+{
+#if !(defined(__MD95__) || defined(__MD97__) || defined(__MD97P__))
+ if (core_id<NUM_AVAILABLE_CORE)
+ {
+ *ret_addr = _ispram_end_addr[core_id];
+ return KAL_SUCCESS;
+ }
+#endif
+ *ret_addr = 0;
+ return KAL_ERROR;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_ISPRAM_Base
+*
+* DESCRIPTION
+* Retrieve the execution view base address of ISPRAM by core id
+*
+* PARAMETERS
+* core id
+*
+* RETURNS
+*
+*************************************************************************/
+kal_status custom_get_ISPRAM_Base(kal_uint8 core_id, kal_uint32 *ret_addr)
+{
+ return custom_get_ISPRAM_CODE_Base(core_id, ret_addr);
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_ISPRAM_End
+*
+* DESCRIPTION
+* Retrieve the execution view end address of ISPRAM by core id
+*
+* PARAMETERS
+* core id
+*
+* RETURNS
+*
+*************************************************************************/
+kal_status custom_get_ISPRAM_End(kal_uint8 core_id, kal_uint32 *ret_addr)
+{
+#if !(defined(__MD95__) || defined(__MD97__) || defined(__MD97P__))
+ extern kal_uint32 Image$$ISPRAM$$Length ;
+
+ kal_status ret;
+ kal_uint32 base;
+
+ ret = custom_get_ISPRAM_Base(core_id, &base);
+ if (KAL_SUCCESS!=ret)
+ {
+ *ret_addr = 0;
+ return ret;
+ }
+
+ if (core_id<NUM_AVAILABLE_CORE)
+ {
+ *ret_addr = base + (kal_uint32) &Image$$ISPRAM$$Length ; /*we assume the length of all ISPRAMs are the same */
+ return KAL_SUCCESS;
+ }
+#endif
+ *ret_addr = 0;
+ return KAL_ERROR;
+}
+
+
+
+/*************************************************************************
+* FUNCTION
+* custom_get_DSPRAM_Load_Base
+*
+* DESCRIPTION
+* Retrieve the base view address of DSPRAM by core id
+*
+* PARAMETERS
+* core id
+*
+* RETURNS
+*
+*************************************************************************/
+kal_status custom_get_DSPRAM_Load_Base(kal_uint8 core_id, kal_uint32 *ret_addr)
+{
+#if !(defined(__MD95__) || defined(__MD97__) || defined(__MD97P__))
+ if (core_id<NUM_AVAILABLE_CORE)
+ {
+ *ret_addr = _dspram_load_addr[core_id];
+ return KAL_SUCCESS;
+ }
+#endif
+ *ret_addr = 0;
+ return KAL_ERROR;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_DSPRAM_DATA_Base
+*
+* DESCRIPTION
+* Retrieve the execution view base address of DSPRAM RW by core id
+*
+* PARAMETERS
+* core id
+*
+* RETURNS
+*
+*************************************************************************/
+kal_status custom_get_DSPRAM_DATA_Base(kal_uint8 core_id, kal_uint32 *ret_addr)
+{
+#if !(defined(__MD95__) || defined(__MD97__) || defined(__MD97P__))
+ if (core_id<NUM_AVAILABLE_CORE)
+ {
+ *ret_addr = _dspram_start_addr[core_id];
+ return KAL_SUCCESS;
+ }
+#endif
+ *ret_addr = 0;
+ return KAL_ERROR;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_DSPRAM_DATA_End
+*
+* DESCRIPTION
+* Retrieve the execution view end address of DSPRAM RW by core id
+*
+* PARAMETERS
+* core id
+*
+* RETURNS
+*
+*************************************************************************/
+kal_status custom_get_DSPRAM_DATA_End(kal_uint8 core_id, kal_uint32 *ret_addr)
+{
+#if !(defined(__MD95__) || defined(__MD97__) || defined(__MD97P__))
+ if (core_id<NUM_AVAILABLE_CORE)
+ {
+ *ret_addr = _dspram_end_addr[core_id];
+ return KAL_SUCCESS;
+ }
+#endif
+ *ret_addr = 0;
+ return KAL_ERROR;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* custom_get_DSPRAM_DATA_ZI_Base
+*
+* DESCRIPTION
+* Retrieve the execution view base address of DSPRAM ZI by core id
+*
+* PARAMETERS
+* core id
+*
+* RETURNS
+*
+*************************************************************************/
+kal_status custom_get_DSPRAM_DATA_ZI_Base(kal_uint8 core_id, kal_uint32 *ret_addr)
+{
+#if !(defined(__MD95__) || defined(__MD97__) || defined(__MD97P__))
+ if (core_id<NUM_AVAILABLE_CORE)
+ {
+ *ret_addr = _dspram_zi_start_addr[core_id];
+ return KAL_SUCCESS;
+ }
+#endif
+ *ret_addr = 0;
+ return KAL_ERROR;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_DSPRAM_DATA_ZI_End
+*
+* DESCRIPTION
+* Retrieve the execution view end address of DSPRAM ZI by core id
+*
+* PARAMETERS
+* core id
+*
+* RETURNS
+*
+*************************************************************************/
+kal_status custom_get_DSPRAM_DATA_ZI_End(kal_uint8 core_id, kal_uint32 *ret_addr)
+{
+#if !(defined(__MD95__) || defined(__MD97__) || defined(__MD97P__))
+ if (core_id<NUM_AVAILABLE_CORE)
+ {
+ *ret_addr = _dspram_zi_end_addr[core_id];
+ return KAL_SUCCESS;
+ }
+#endif
+ *ret_addr = 0;
+ return KAL_ERROR;
+}
+
+
+
+/*************************************************************************
+* FUNCTION
+* custom_get_DSPRAM_Base
+*
+* DESCRIPTION
+* Retrieve the execution view base address of DSPRAM by core id
+*
+* PARAMETERS
+* core id
+*
+* RETURNS
+*
+*************************************************************************/
+kal_status custom_get_DSPRAM_Base(kal_uint8 core_id, kal_uint32 *ret_addr)
+{
+ return custom_get_DSPRAM_DATA_Base(core_id, ret_addr);
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_ISPRAM_End
+*
+* DESCRIPTION
+* Retrieve the execution view end address of DSPRAM by core id
+*
+* PARAMETERS
+* core id
+*
+* RETURNS
+*
+*************************************************************************/
+kal_status custom_get_DSPRAM_End(kal_uint8 core_id, kal_uint32 *ret_addr)
+{
+#if !(defined(__MD95__) || defined(__MD97__) || defined(__MD97P__))
+ kal_status ret;
+ kal_uint32 base;
+
+ ret = custom_get_DSPRAM_Base(core_id, &base);
+ if (KAL_SUCCESS!=ret)
+ {
+ *ret_addr = 0;
+ return ret;
+ }
+
+ if (core_id<NUM_AVAILABLE_CORE)
+ {
+ *ret_addr = base + (kal_uint32) _dspram_phy_length[core_id];
+ return KAL_SUCCESS;
+ }
+#endif
+ *ret_addr = 0;
+ return KAL_ERROR;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_DYNAMIC_SECTION_L2CACHE_LOCK_Base
+*
+* DESCRIPTION
+* Retrieve the base of DYNAMIC L2CACHE LOCK
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_int32 custom_get_DYNAMIC_SECTION_L2CACHE_LOCK_Base(void)
+{
+#if defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+ return 0;
+#else
+ extern kal_uint32 DYNAMIC_SECTION_L2CACHE_LOCK_0$$Base;
+
+ return (kal_uint32) &DYNAMIC_SECTION_L2CACHE_LOCK_0$$Base;
+#endif
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_DYNAMIC_SECTION_L2CACHE_LOCK_Length
+*
+* DESCRIPTION
+* Retrieve the end of DYNAMIC L2CACHE LOCK
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_int32 custom_get_DYNAMIC_SECTION_L2CACHE_LOCK_RW_Base(void)
+{
+ extern kal_uint32 DYNAMIC_SECTION_L2CACHE_LOCK_0_DATA$$Base;
+
+ return (kal_uint32) &DYNAMIC_SECTION_L2CACHE_LOCK_0_DATA$$Base;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_L2CACHE_LOCK_Base
+*
+* DESCRIPTION
+* Retrieve the base of L2CACHE LOCK
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_int32 custom_get_L2CACHE_LOCK_Base(void)
+{
+#if defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+ return 0;
+#else
+ extern kal_uint32 L2CACHE_LOCK$$Base;
+
+ return (kal_uint32) &L2CACHE_LOCK$$Base;
+#endif
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_L2CACHE_LOCK_End
+*
+* DESCRIPTION
+* Retrieve the end of L2CACHE LOCK
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_int32 custom_get_L2CACHE_LOCK_End(void)
+{
+ extern kal_uint32 L2CACHE_LOCK$$Limit;
+
+ return (kal_uint32) &L2CACHE_LOCK$$Limit;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_L2CACHE_LOCK_Length
+*
+* DESCRIPTION
+* Retrieve the end of L2CACHE LOCK
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_int32 custom_get_L2CACHE_LOCK_Length(void)
+{
+#if defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+ return 0;
+#else
+ extern kal_uint32 L2CACHE_LOCK$$Length;
+
+ return (kal_uint32) &L2CACHE_LOCK$$Length;
+#endif
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_L2CACHE_LOCK_Length
+*
+* DESCRIPTION
+* Retrieve the end of L2CACHE LOCK
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_int32 custom_get_L2CACHE_LOCK_RW_Base(void)
+{
+ extern kal_uint32 L2CACHE_LOCK_DATA$$Base;
+
+ return (kal_uint32) &L2CACHE_LOCK_DATA$$Base;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_DSPTXRX_Base
+*
+* DESCRIPTION
+* Retrieve the lowest base address of DSP_TX or DSP_RX
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_int32 custom_get_DSPTXRX_Base(void)
+{
+ return [AUTOGEN_SCAT_C_Gen_TEMPLATE_DSPTXRX_BEGIN];
+}
+/*************************************************************************
+* FUNCTION
+* custom_get_DSPTXRX_MaxSize
+*
+* DESCRIPTION
+* Retrieve the reserved size of DSP_TX plus DSP_RX
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_int32 custom_get_DSPTXRX_MaxSize(void)
+{
+ return [AUTOGEN_SCAT_C_Gen_TEMPLATE_DSPTXRX_MAXSIZE];
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_FAT_StartAddr
+*
+* DESCRIPTION
+* Retrieve FAT base address
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_FAT_StartAddr(void)
+{
+ return (custom_get_fat_addr() | INT_RetrieveFlashBaseAddr());
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_FAT_Length
+*
+* DESCRIPTION
+* Retrieve FAT length
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_FAT_Length(void)
+{
+ return custom_get_fat_len();
+}
+
+kal_uint32 custom_get_MD_RAMEnd(void)
+{
+ kal_uint32 EndAddr = 0;
+
+ extern kal_uint32 Image$$DUMMY_END$$Base;
+ EndAddr = (kal_uint32)&Image$$DUMMY_END$$Base;
+
+ return EndAddr;
+}
+
+
+
+/*************************************************************************
+* FUNCTION
+* custom_mk_ram_info
+*
+* DESCRIPTION
+* This function builds up EXTSRAM info tables.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+#if defined(__ARM9_MMU__) || defined(__ARM11_MMU__) || defined(__MTK_MMU__) || defined(__CR4__) || defined(__MTK_MMU_V2__) || defined(__MIPS_IA__) || defined(__MIPS_I7200__)
+kal_int32 custom_mk_ram_info()
+{
+ /* This table contains all dynamic cacheable default non-cacheable regions. */
+[AUTOGEN_SCAT_C_Gen_TEMPLATE_EXTSRAM_REGION_DYNAMIC_DNC_ASSIGN]
+
+ /* This table contains all dynamic cacheable default cacheable regions. */
+[AUTOGEN_SCAT_C_Gen_TEMPLATE_EXTSRAM_REGION_DYNAMIC_DC_ASSIGN]
+
+ /* This table contains all cached regions. */
+[AUTOGEN_SCAT_C_Gen_TEMPLATE_EXTSRAM_REGION_CACHED_RW_ASSIGN]
+
+ /* This table contains all cached code regions. */
+[AUTOGEN_SCAT_C_Gen_TEMPLATE_EXTSRAM_REGION_CACHED_RO_ASSIGN]
+
+ /* This table contains all non-cached rw regions. */
+[AUTOGEN_SCAT_C_Gen_TEMPLATE_EXTSRAM_REGION_NONCACHED_RW_ASSIGN]
+
+ /* This table contains all non-cached ro regions. */
+[AUTOGEN_SCAT_C_Gen_TEMPLATE_EXTSRAM_REGION_NONCACHED_RO_ASSIGN]
+
+
+ return 0;
+}
+#endif /* __ARM9_MMU__ || __ARM11_MMU__ || __MTK_MMU__ || __CR4__ || __MTK_MMU_V2__ || __MIPS_IA__*/
+
+
+/*************************************************************************
+* FUNCTION
+* custom_get_NVRAM_LTABLE_Base
+*
+* DESCRIPTION
+* Retrieve the base address of NVRAM_LTABLE
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_NVRAM_LTABLE_Base(void)
+{
+ return [AUTOGEN_SCAT_C_Gen_TEMPLATE_NVRAM_BASE];
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_NVRAM_LTABLE_Length
+*
+* DESCRIPTION
+* Retrieve the length of NVRAM_LTABLE
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_NVRAM_LTABLE_Length(void)
+{
+ return [AUTOGEN_SCAT_C_Gen_TEMPLATE_NVRAM_LENGTH];
+}
+
+
+/*************************************************************************
+* FUNCTION
+* custom_get_VOLTE_CORE_ZI_base
+*
+* DESCRIPTION
+* Retrieve the base of CACHED_EXTSRAM_ZI_VOLTE_CORE3 section
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_VOLTE_CORE_ZI_base(void)
+{
+ extern kal_uint32 Image$$CACHED_EXTSRAM_ZI_VOLTE_CORE3$$Base;
+
+ return (kal_uint32) &Image$$CACHED_EXTSRAM_ZI_VOLTE_CORE3$$Base;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* custom_get_VOLTE_CORE_ZI_End
+*
+* DESCRIPTION
+* Retrieve the end of CACHED_EXTSRAM_ZI_VOLTE_CORE3 section
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_VOLTE_CORE_ZI_End(void)
+{
+ extern kal_uint32 Image$$CACHED_EXTSRAM_ZI_VOLTE_CORE3$$ZI$$Limit;
+
+ return (kal_uint32) &Image$$CACHED_EXTSRAM_ZI_VOLTE_CORE3$$ZI$$Limit;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* custom_query_dump_region
+*
+* DESCRIPTION
+* This function builds up the table of DUMP REGIONs.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_query_dump_region(EXTSRAM_REGION_INFO_T* region)
+{
+[AUTOGEN_SCAT_C_Gen_TEMPLATE_DUMP_REGION_ASSIGN]
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_query_dump_region_without_UC_ROM
+*
+* DESCRIPTION
+* This function builds up the table of DUMP REGIONs without UC_ROM.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_query_dump_region_without_UC_ROM(EXTSRAM_REGION_INFO_T* region)
+{
+[AUTOGEN_SCAT_C_Gen_TEMPLATE_DUMP_REGION_NO_UC_ROM_ASSIGN]
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_query_dump_region_ROM
+*
+* DESCRIPTION
+* This function builds up the table of DUMP ROM REGIONs.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_query_dump_region_ROM(EXTSRAM_REGION_INFO_T* region)
+{
+[AUTOGEN_SCAT_C_Gen_TEMPLATE_DUMP_REGION_ROM_ASSIGN]
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_query_dump_region_PA
+*
+* DESCRIPTION
+* This function builds up the table of DUMP PA REGIONs.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_query_dump_region_PA(EXTSRAM_REGION_INFO_T* region)
+{
+[AUTOGEN_SCAT_C_Gen_TEMPLATE_DUMP_REGION_PA_ASSIGN]
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_query_dump_region_VA
+*
+* DESCRIPTION
+* This function builds up the table of DUMP VA REGIONs.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_query_dump_region_VA(EXTSRAM_REGION_INFO_T* region)
+{
+[AUTOGEN_SCAT_C_Gen_TEMPLATE_DUMP_REGION_VA_ASSIGN]
+}
+
+kal_uint8 custom_get_dump_info(kal_uint32 *address)
+{
+#if defined(__MD97__) || defined(__MD97P__)
+ return DUMP_OP_NONE;
+#else
+ extern kal_uint32 sst_get_main_exception_core(void);
+
+ kal_uint32 nCachedPrefix;
+ kal_uint32 nonCacheAddr;
+ kal_uint32 CachedAddr = (*address);
+ kal_uint8 op = DUMP_OP_NONE;
+ kal_uint32 index = 0;
+ nCachedPrefix = [AUTOGEN_SCAT_C_Gen_TEMPLATE_CACHEABLE_PREFIX];
+
+ if ( ((CachedAddr & 0xF0000000) ^ nCachedPrefix) == 0) /*if it's cached address*/
+ {
+ nonCacheAddr = CachedAddr & (~nCachedPrefix);
+ for (index = 0; index < (sizeof(dump_info)/sizeof(dump_info_str));index++)
+ {
+ //size check, if start==end then empty section
+ if ((dump_info[index].start&0x0FFFFFFF) == (dump_info[index].end&0x0FFFFFFF))
+ continue;
+
+ if ( (((dump_info[index].start&0x0FFFFFFF)|nCachedPrefix)<= CachedAddr) &&
+ (CachedAddr <= ((dump_info[index].end&0x0FFFFFFF)|nCachedPrefix)) )
+ {
+ op = dump_info[index].op;
+ (*address) = nonCacheAddr;
+ break;
+ }
+ }
+ }
+ if ((op == (sst_get_main_exception_core()+1)) && (op != DUMP_OP_NONE))
+ {
+ op = DUMP_OP_NONE;
+ }
+ return op;
+#endif
+}
+
+
+/*************************************************************************
+* FUNCTION
+* custom_query_code_region
+*
+* DESCRIPTION
+* This function is t judge if the symbol address is in code region.
+*
+* PARAMETERS
+* core_id
+* RETURNS
+*
+*************************************************************************/
+kal_bool custom_query_code_region(kal_uint32 code_addr, kal_uint32 core_id)
+{
+ kal_uint32 index = 0;
+ while((CODE_SECTIONS[index][0] !=0) || (CODE_SECTIONS[index][1] !=0))
+ {
+ if( (CODE_SECTIONS[index][0] <= code_addr) && (code_addr < (CODE_SECTIONS[index][0]+CODE_SECTIONS[index][1])))
+ {
+ return KAL_TRUE;
+ }
+ index++;
+ }
+ return KAL_FALSE;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_query_MCURO_HWRW_region
+*
+* DESCRIPTION
+* This function is t judge if the given address is in MCURO_HWRW region.
+*
+* PARAMETERS
+* symbol_addr
+* RETURNS
+*
+*************************************************************************/
+kal_bool custom_query_MCURO_HWRW_region(kal_uint32 symbol_addr)
+{
+ kal_uint32 index = 0;
+ while((MCURO_HWRW_SECTIONS[index][0] !=0) || ((MCURO_HWRW_SECTIONS[index][1] - MCURO_HWRW_SECTIONS[index][0]) !=0))
+ {
+ if( (MCURO_HWRW_SECTIONS[index][0] <= symbol_addr) && (symbol_addr < MCURO_HWRW_SECTIONS[index][1]))
+ {
+ return KAL_TRUE;
+ }
+ index++;
+ }
+ return KAL_FALSE;
+}
+
+
+/*************************************************************************
+* FUNCTION
+* custom_query_EMI_RMPU_region_info
+*
+* DESCRIPTION
+* This function gets info of EMI RMPU for setting to BUS MPU
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_query_EMI_RMPU_region_info(EMI_MPU_REGION_INFO_T **region)
+{
+ /*
+ * Please align below setting to @aEMI_MPU_config in EMI_MPIinfo.pm
+ */
+ extern kal_uint32 Image$$MCURO_HWRW$$Base;
+ extern kal_uint32 Image$$DUMMY_END$$Base;
+ static EMI_MPU_REGION_INFO_T EMI_MPU_REGION[5] =
+ {
+ {(kal_uint32)&Image$$ROM_GFH$$Base, 0, EMI_MPU_MDMCU_RO, EMI_MPU_MDHW_RO},
+ {(kal_uint32)&Image$$MCURO_HWRW$$Base, 0, EMI_MPU_MDMCU_RO, EMI_MPU_MDHW_RW},
+ {(kal_uint32)&Image$$EXTSRAM$$Base, 0, EMI_MPU_MDMCU_RW, EMI_MPU_MDHW_RO},
+ {(kal_uint32)&Image$$EXTSRAM_MCURW_HWRW$$Base, 0, EMI_MPU_MDMCU_RW, EMI_MPU_MDHW_RW},
+ {(kal_uint32)&Image$$DUMMY_END$$Base, 0, EMI_MPU_INVALIDE, EMI_MPU_INVALIDE}
+ };
+
+ kal_uint32 i=1, num_of_region;
+
+ num_of_region = sizeof(EMI_MPU_REGION)/sizeof(EMI_MPU_REGION_INFO_T);
+
+ EMI_MPU_REGION[0].addr = EMI_MPU_REGION[0].addr & 0x0FFFFFFF;
+
+ for(i=1; i<num_of_region; ++i)
+ {
+ EMI_MPU_REGION[i].addr = EMI_MPU_REGION[i].addr & 0x0FFFFFFF;
+ EMI_MPU_REGION[i-1].len = EMI_MPU_REGION[i].addr - EMI_MPU_REGION[i-1].addr;
+ }
+
+ *region = EMI_MPU_REGION;
+
+ return (num_of_region-1);
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_SIB_AREA_region
+*
+* DESCRIPTION
+* Retrieve the SIB area regions info
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_int32 custom_get_SIB_AREA_region(EXTSRAM_REGION_INFO_T **region)
+{
+#if defined(__MD97__) || defined(__MD97P__)
+ *region = SIB_AREA_REGION;
+#else
+ (void)region; //avoid warnings;
+#endif
+
+ return 0;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_SS_EXT_CSIF_Base
+*
+* DESCRIPTION
+* Retrieve the base of SS_EXT_CSIF section
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_SS_EXT_CSIF_Base(void)
+{
+#if defined(__MD97__) || defined(__MD97P__)
+ extern kal_uint32 Image$$MCURW_HWRW_DNC_SS_EXT_CSIF$$Base;
+ return (kal_uint32) &Image$$MCURW_HWRW_DNC_SS_EXT_CSIF$$Base;
+#else
+ return 0;
+#endif
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_SS_EXT_CSIF_End
+*
+* DESCRIPTION
+* Retrieve the end of SS_EXT_CSIF section
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_SS_EXT_CSIF_End(void)
+{
+#if defined(__MD97__) || defined(__MD97P__)
+ extern kal_uint32 Image$$MCURW_HWRW_DNC_SS_EXT_CSIF$$Limit;
+ return (kal_uint32) &Image$$MCURW_HWRW_DNC_SS_EXT_CSIF$$Limit;
+#else
+ return 0;
+#endif
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_NL1_EXT_CSIF_Base
+*
+* DESCRIPTION
+* Retrieve the base of NL1_EXT_CSIF section
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_NL1_EXT_CSIF_Base(void)
+{
+#if defined(__MD97__) || defined(__MD97P__)
+ extern kal_uint32 Image$$MCURW_HWRW_DNC_NL1_EXT_CSIF$$Base;
+ return (kal_uint32) &Image$$MCURW_HWRW_DNC_NL1_EXT_CSIF$$Base;
+#else
+ return 0;
+#endif
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_get_NL1_EXT_CSIF_End
+*
+* DESCRIPTION
+* Retrieve the end of NL1_EXT_CSIF section
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+kal_uint32 custom_get_NL1_EXT_CSIF_End(void)
+{
+#if defined(__MD97__) || defined(__MD97P__)
+ extern kal_uint32 Image$$MCURW_HWRW_DNC_NL1_EXT_CSIF$$Limit;
+ return (kal_uint32) &Image$$MCURW_HWRW_DNC_NL1_EXT_CSIF$$Limit;
+#else
+ return 0;
+#endif
+}
+
+/*************************************************************************
+* FUNCTION
+* dummy_referene_func
+*
+* DESCRIPTION
+* Avoid removing the following linker symbols by garbage collection.
+* If some new symbols only used for post-gen are added, please add them to the funtion.
+*
+* PARAMETERS
+*
+* RETURNS
+*
+*************************************************************************/
+__attribute__((noinline, used)) void dummy_referene_func(void)
+{
+ volatile kal_uint32 dummy;
+
+ extern kal_uint32 Image$$MCURO_HWRW$$Base;
+ dummy = (kal_uint32)&Image$$MCURO_HWRW$$Base;
+ extern kal_uint32 Image$$DUMMY_END$$Base;
+ dummy = (kal_uint32)&Image$$DUMMY_END$$Base;
+ extern kal_uint32 Image$$ROM_SIGNATURE_SECTION$$Length;
+ dummy = (kal_uint32)&Image$$ROM_SIGNATURE_SECTION$$Length;
+ extern kal_uint32 Image$$ROM_SIGNATURE_SECTION$$ZI$$Length;
+ dummy = (kal_uint32)&Image$$ROM_SIGNATURE_SECTION$$ZI$$Length;
+ extern kal_uint32 Load$$ROM_SIGNATURE_SECTION$$Base;
+ dummy = (kal_uint32)&Load$$ROM_SIGNATURE_SECTION$$Base;
+
+ (void)dummy;
+}
+
+/*************************************************************************
+* FUNCTION
+* custom_query_EMI_region
+*
+* DESCRIPTION
+* This function is to judge if the region is allocated on EMI.
+*
+* PARAMETERS
+* region_addr
+* RETURNS
+*
+*************************************************************************/
+kal_bool custom_query_EMI_region(kal_uint32 region_addr)
+{
+ kal_uint32 bank_prefix = region_addr >> 28;
+ if( bank_prefix==0 || bank_prefix==2 || bank_prefix==4 || bank_prefix==6 ){
+ return KAL_TRUE;
+ }else if( (bank_prefix==1 || bank_prefix==3 || bank_prefix==7 || bank_prefix==9) && (( region_addr & 0x0FFFFFFF) < 0x0F000000) ){
+ return KAL_TRUE;
+ }
+ return KAL_FALSE;
+}
+
+
+/* to be removed */
+kal_uint32 custom_get_L2SRAM_L2NC_CODE_base(void)
+{
+ return 0;
+}
+
+/* to be removed */
+kal_uint32 custom_get_L2SRAM_L2NC_CODE_load_base(void)
+{
+ return 0;
+}
+
+/* to be removed */
+kal_uint32 custom_get_L2SRAM_L2NC_CODE_Length(void)
+{
+ return 0;
+}
+
+/* to be removed */
+kal_uint32 custom_get_L2SRAM_L2C_CODE_base(void)
+{
+#if !(defined(__MD97__) || defined(__MD97P__))
+ return 0;
+#else
+ return (kal_uint32) &Image$$L2SRAM_L2C_CODE$$Base;
+#endif
+}
+
+/* to be removed */
+kal_uint32 custom_get_L2SRAM_L2C_CODE_load_base(void)
+{
+#if !(defined(__MD97__) || defined(__MD97P__))
+ return 0;
+#else
+ return (kal_uint32) &Load$$L2SRAM_L2C_CODE$$Base;
+#endif
+}
+
+/* to be removed */
+kal_uint32 custom_get_L2SRAM_L2C_CODE_Length(void)
+{
+#if !(defined(__MD97__) || defined(__MD97P__))
+ return 0;
+#else
+ return (kal_uint32)&Image$$L2SRAM_L2C_CODE$$Length;
+#endif
+}
+
+/* to be removed */
+kal_uint32 custom_get_INTSRAMCODE_Base(void)
+{
+ return 0;
+}
+
+#endif /* __MTK_TARGET__ */
diff --git a/mcu/custom/system/Template/custom_scatstruct.h.template b/mcu/custom/system/Template/custom_scatstruct.h.template
new file mode 100644
index 0000000..8a80c28
--- /dev/null
+++ b/mcu/custom/system/Template/custom_scatstruct.h.template
@@ -0,0 +1,430 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2006
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * custom_scatstruct.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file declares the scatter file dependent APIs
+ *
+ * Author:
+ * -------
+ * Claudia Lo (mtk01876) [AUTOGEN_GenVersion]
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * $Revision$
+ * $Modtime$
+ * $Log$
+ *
+ * 09 03 2020 yao.liu
+ * [MOLY00566717] [Gen97] Add a function to query if the region is on EMI.
+ * [NR15.R3.MP] Add an API to query if the region is on EMI.
+ *
+ * 12 03 2019 yao.liu
+ * [MOLY00463184] [System Service][MOLY Kernel Internal Request] Enhance exception flow security
+ * [VMOLY] Add custom_query_MCURO_HWRW_region API for exception.
+ *
+ * 09 03 2019 yao.liu
+ * [MOLY00434510] Memory Dump 2.0
+ * [VMOLY] Memory dump 2.0 - SYS_MEM part.
+ *
+ * 04 29 2019 yao.liu
+ * [MOLY00383168] [System Service][MOLY Kernel Internal Request] Merge minidump code from UMOLYE to VMOLY
+ * [VMOLY] Porting mini dump.
+ *
+ * 10 22 2018 tero.jarkko
+ * [MOLY00356148] [Gen97][SystemService][AutoGen]Provided SIB area query API
+ *
+ * .
+ *
+ * 10 18 2018 tero.jarkko
+ * [MOLY00359671] [Gen97][SystemService][AutoGen]SS_EXT_CSIF and NL1_EXT_CSIF API implementation
+ *
+ * .
+ *
+ * 09 28 2018 tero.jarkko
+ * [MOLY00356148] [Gen97][SystemService][AutoGen]Provided SIB area query API
+ *
+ * .
+ *
+ * 05 04 2017 carl.kao
+ * [MOLY00246779] [BIANCO] Enable ASM addon,SWTR and stream mode
+ * Remove unused API : custom_get_MaxAvailableMemorySegment
+ *
+ * 04 07 2017 carl.kao
+ * [MOLY00240094] [Gen93] [SystemService] [Auto-Gen] Refine setting of EMI RMPU for Gen93
+ * .
+ *
+ * 02 24 2016 tero.jarkko
+ * [MOLY00164073] [LR12][SystemService][Auto-Gen] [Internal Refinement][MT6292] [sysGen2] Generate custom_scatstruct.c using sysGen2
+ *
+ * Added L2SRAM_L2NC and L2SRAM_L2C functions
+ *
+ * 02 18 2016 tero.jarkko
+ * [MOLY00165076] [LR12][SystemService][Auto-Gen] [Internal Refinement][MT6292] [sysGen2] Support custom_query_dynamic_code_region
+ *
+ * .
+ *
+ * 02 16 2016 tero.jarkko
+ * [MOLY00165076] [LR12][SystemService][Auto-Gen] [Internal Refinement][MT6292] [sysGen2] Support custom_query_dynamic_code_region
+ *
+ * .
+ *
+ * 02 04 2016 tero.jarkko
+ * [MOLY00164073] [LR12][SystemService][Auto-Gen] [Internal Refinement][MT6292] [sysGen2] Generate custom_scatstruct.c using sysGen2
+ *
+ * custom_ram_mk_info
+ *
+ * 02 03 2016 tero.jarkko
+ * [MOLY00164073] [LR12][SystemService][Auto-Gen] [Internal Refinement][MT6292] [sysGen2] Generate custom_scatstruct.c using sysGen2
+ *
+ * L2SRAM_L2NC base and length functions added
+ *
+ * 02 02 2016 tero.jarkko
+ * [MOLY00164073] [LR12][SystemService][Auto-Gen] [Internal Refinement][MT6292] [sysGen2] Generate custom_scatstruct.c using sysGen2
+ *
+ * .
+ *
+ * 01 18 2016 carl.kao
+ * [MOLY00159955] [LR12][SystemService][Auto-Gen] remove core 3 SPRAM and make SPRAM APIs more robust
+ * .
+ *
+ * 01 12 2016 qmei.yang
+ * [MOLY00151351] [SystemService][DebuggingSuite][Internal Refinement][92] Support full exception flow framework
+ *
+ * .
+ *
+ * 01 11 2016 qmei.yang
+ * [MOLY00151351] [SystemService][DebuggingSuite][Internal Refinement][92] Support full exception flow framework
+ * .
+ *
+ * 11 12 2015 carl.kao
+ * [MOLY00148842] [LR12][SystemService][Auto-Gen] 92 lds, for Full region ready, Code in Right Location
+ * Support VoLTE core section
+ *
+ * 11 11 2015 carl.kao
+ * [MOLY00148842] [LR12][SystemService][Auto-Gen] 92 lds, for Full region ready, Code in Right Location
+ * New image layout for "Full region ready, Code in Right Location"
+ *
+ * 07 03 2015 carl.kao
+ * [MOLY00125736] [MT6755][BRINGUP_FIRSTCALL] [SystemService][Auto-Gen] add custom_get_L1CORE_INTSRAM_Base and custom_get_L1CORE_INTSRAM_End
+ * get l1core tcm base and length
+ *
+ * 06 15 2015 carl.kao
+ * [MOLY00121235] [TK6291] [SystemService][Auto-Gen][Request For Design Change] Query TCM base and end address
+ * .
+ *
+ * 04 16 2015 carl.kao
+ * [MOLY00106652] [TK6291] [SystemService][Auto-Gen] add a dynamic switchable default cached MCU-RW, HW-RW section
+ * add 4 sections for EMI RMPU
+ * 1) (MCU RO, MDHW RW) DNC
+ * 2) (MCU RO, MDHW RW) NC
+ * 3) (MCU RW, MDHW RW) DNC
+ * 4) (MCU RW, MDHW RW) NC
+ *
+ * 02 24 2015 qmei.yang
+ * [MOLY00096717] [SystemService][DebuggingSuite][Internal Refinement] Support to dump l1core l2sram
+ * .
+ *
+ * 12 23 2014 carl.kao
+ * [MOLY00088578] [TK6291] [SystemService] [Auto-Gen] Support L2SRAM section (in L1CORE)
+ * aa.
+ *
+ * 12 22 2014 carl.kao
+ * [MOLY00087532] [Denali-1] [SystemService][Auto-Gen] Refactor AutoGen Code and Remove Legacy Code
+ * .
+ *
+ * 12 22 2014 carl.kao
+ * [MOLY00087532] [Denali-1] [SystemService][Auto-Gen] Refactor AutoGen Code and Remove Legacy Code
+ * .
+ * 11 06 2014 carl.kao
+ * [MOLY00083492] [TK6291] [SystemService][Auto-Gen][Request For Design Change] Add custom_get_MD_RAMEnd() for MPU
+ * Add custom_get_MD_RAMEnd() for PCORE MPU
+ *
+ * 11 06 2014 carl.kao
+ * [MOLY00083492] [TK6291] [SystemService][Auto-Gen][Request For Design Change] Add custom_get_MD_RAMEnd() for MPU
+ * .
+ *
+ * 09 11 2014 qmei.yang
+ * [MOLY00078623] [SystemService][DebuggingSuite][Internal Refinement][MT6291] Support memory dump
+ * .
+ *
+ * 08 27 2014 carl.kao
+ * [MOLY00077388] [MT6291] [SystemService][Auto-Gen][Request For Design Change] Support multi-core exception
+ * fix build fail
+ *
+ * 07 31 2014 carl.kao
+ * [MOLY00074124] [SystemService][DebuggingSuite][MT6291] Support multi-core exception
+ * dump L1CORE region by PCORE
+ *
+ * 04 07 2014 carl.kao
+ * [MOLY00061797] [SYSTEM SERVICE] porting features from U3G_TK6280_DEV and MOLY.U3G.90IT.DEV branches
+ * fix build error in config lib
+ *
+ * 04 07 2014 carl.kao
+ * [MOLY00061797] [SYSTEM SERVICE] porting features from U3G_TK6280_DEV and MOLY.U3G.90IT.DEV branches
+ * 9) Rename "l1dsp" to "l1core", "L1DSP" to "L1CORE"
+ *
+ * 04 02 2014 carl.kao
+ * [MOLY00061134] [SYSTEM SERVICE][AutoGen] AutoGen for MT6291
+ * 1) pcore sysGen2.
+ * 2) Remove useless secure region query API
+ *
+ * 02 25 2014 qmei.yang
+ * [MOLY00057421] [SystemService][Auto-Gen][Internal Refinement] Remove useless secure region query api
+ * .
+ *
+ * 06 25 2013 qmei.yang
+ * [MOLY00025806] [SystemService][Auto-Gen][Request For Design Change] Support COPRO
+ * support COPRO_arm7's L1Cache
+ *
+ * 04 26 2013 qmei.yang
+ * [MOLY00020542] [SystemService][MOLY] To remove useless input sections by the request
+ * support SWLA space as well
+ *
+ * 10 31 2012 qmei.yang
+ * [MOLY00005605] [SystemService][Auto-Gen][Request For Design Change][sysgen2] Create new API: custom_get_DSPTXRX_MaxSize()
+ * .
+ *
+ * 08 27 2012 qmei.yang
+ * [MOLY00001774] [SystemService][Region_Init][Internal Refinement] Support MT6577 region init and remove useless regions and compile option
+ * .
+ *
+ * 05 10 2012 qmei.yang
+ * [MAUI_03182425] [Reason]sync codes between modem_dev and 11B
+ * .
+ *
+ * 03 08 2012 qmei.yang
+ * [MAUI_03145378] [SystemService][Auto-Gen][Sys Gen][scatGen][Internal Refinement] Phase in AutoGen new flow to support GCC
+ * .
+ *
+ * 02 15 2012 qmei.yang
+ * [MAUI_03130553] [SystemService][Auto-Gen][Sys Gen][scatGen][Internal Refinement] Support cmmgen sync with sysgen2
+ * Modify custom_query_dump_region() API
+ *
+ * 01 30 2012 qmei.yang
+ * [MAUI_03120516] [SystemService][Auto-Gen][Sys Gen][scatGen][Internal Refinement] Refactory sysgen2.pl
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _CUSTOM_SCATSTRUCT_H
+#define _CUSTOM_SCATSTRUCT_H
+
+#include "kal_general_types.h"
+#include "init.h"
+
+typedef enum
+{
+ DUMP_OP_NONE = 0,
+ DUMP_OP_CORE0_CACHE = 1,
+ DUMP_OP_CORE1_CACHE = 2,
+ DUMP_OP_CORE2_CACHE = 3,
+ DUMP_OP_CORE3_CACHE = 4,
+} DUMP_OP_T;
+
+typedef enum
+{
+ DC_ISPRAM0 = 0,
+ DC_ISPRAM1,
+ DC_ISPRAM2,
+ DC_L2SRAM,
+ DC_MEM_MAX,
+} DYNAMIC_CODE_MEM_T;
+
+
+typedef enum
+{
+ EMI_MPU_INVALIDE = 0,
+ EMI_MPU_MDMCU_NO_ACCESS = 10,
+ EMI_MPU_MDMCU_RO,
+ EMI_MPU_MDMCU_RW,
+ EMI_MPU_MDMCU_MAX,
+ EMI_MPU_MDHW_NO_ACCESS = 20,
+ EMI_MPU_MDHW_RO,
+ EMI_MPU_MDHW_RW,
+ EMI_MPU_MDHW_MAX,
+} EMI_MPU_REGION_ATTRIBUTE;
+
+
+typedef struct DYNAMIC_CODE_REGION_INFO_STRUCT
+{
+ kal_uint32 addr;
+ kal_uint32 load_addr;
+ kal_uint32 len;
+} DYNAMIC_CODE_REGION_INFO_T;
+
+
+typedef struct EMI_MPU_REGION_INFO_STRUCT
+{
+ kal_uint32 addr;
+ kal_uint32 len;
+ EMI_MPU_REGION_ATTRIBUTE mdmcu_attr;
+ EMI_MPU_REGION_ATTRIBUTE mchw_attr;
+} EMI_MPU_REGION_INFO_T;
+
+
+#if defined (__MTK_TARGET__)
+ #define __TCMROCODE __attribute__ ((section ("INTSRAM_ROCODE")))
+ #define __TCMRODATA __attribute__ ((section ("INTSRAM_RODATA")))
+ #define __TCMRW __attribute__ ((section ("INTSRAM_RW")))
+ #define __TCMZI __attribute__ ((zero_init, section ("INTSRAM_ZI")))
+ #define __PT_Aligned(x) __attribute__ ((section("PAGETABLE"), aligned(x)))
+ #define __NONCACHEDZI __attribute__ ((zero_init, section ("NONCACHEDZI")))
+ #define __NONCACHEDZI_MCURW_HWRW __attribute__ ((section ("MCURW_HWRW_NC_ZI")))
+#else
+ #define __TCMROCODE
+ #define __TCMRODATA
+ #define __TCMRW
+ #define __TCMZI
+ #define __PT_Aligned(x)
+ #define __NONCACHEDZI
+ #define __NONCACHEDZI
+#endif
+
+#ifdef __MTK_TARGET__
+#define DUMP_REGION_COUNT [AUTOGEN_SCAT_H_Gen_DUMP_REGION_COUNT]
+extern kal_uint32 custom_query_dump_region(EXTSRAM_REGION_INFO_T* region);
+extern kal_uint32 custom_query_dump_region_without_UC_ROM(EXTSRAM_REGION_INFO_T* region);
+extern kal_uint32 custom_query_dump_region_ROM(EXTSRAM_REGION_INFO_T* region);
+extern kal_uint32 custom_query_dump_region_PA(EXTSRAM_REGION_INFO_T* region);
+extern kal_uint32 custom_query_dump_region_VA(EXTSRAM_REGION_INFO_T* region);
+extern kal_uint8 custom_get_dump_info(kal_uint32 *address);
+
+#if defined(__ARM9_MMU__) || defined(__ARM11_MMU__)
+#if defined(__ARM9_MMU__)
+extern kal_int32 custom_query_fpt_pool(kal_uint32 **pool, kal_uint32 *pool_size);
+#endif /* __ARM9_MMU__ */
+extern kal_int32 custom_query_cpt_pool(kal_uint32 **pool, kal_uint32 *pool_size);
+#endif /* __ARM9_MMU__ || __ARM11_MMU__ */
+
+#if defined(__DYNAMIC_SWITCH_CACHEABILITY__)
+extern kal_int32 custom_query_dynamic_cached_extsram_default_nc_region(EXTSRAM_REGION_INFO_T **region);
+extern kal_int32 custom_query_dynamic_cached_extsram_default_c_region(EXTSRAM_REGION_INFO_T **region);
+extern kal_int32 custom_query_cached_extsram_region(EXTSRAM_REGION_INFO_T **region);
+extern kal_int32 custom_query_cached_extsram_code_region(EXTSRAM_REGION_INFO_T **region);
+extern kal_int32 custom_query_noncached_extsram_region(EXTSRAM_REGION_INFO_T **region);
+extern kal_int32 custom_query_noncached_extsram_ro_region(EXTSRAM_REGION_INFO_T **region);
+#endif /* __DYNAMIC_SWITCH_CACHEABILITY__ */
+
+
+#if defined(__DSP_FCORE4__)
+extern kal_int32 custom_query_mcu_cacheable_dsp_cacheable_region(EXTSRAM_REGION_INFO_T **region);
+extern kal_int32 custom_query_mcu_cacheable_dsp_noncacheable_region(EXTSRAM_REGION_INFO_T **region);
+extern kal_int32 custom_query_mcu_noncacheable_dsp_cacheable_region(EXTSRAM_REGION_INFO_T **region);
+extern kal_int32 custom_query_mcu_noncacheable_dsp_noncacheable_region(EXTSRAM_REGION_INFO_T **region);
+#endif /* __DSP_FCORE4__ */
+
+extern kal_uint32 custom_get_1st_ROM_ROMBase(void);
+extern kal_uint32 custom_get_1st_ROM_ROMLength(void);
+extern kal_uint32 custom_get_1st_ROM_RAMBase(void);
+extern kal_uint32 custom_get_1st_ROM_RAMLength(void);
+extern kal_uint32 custom_get_1st_ROM_RAMEnd(void);
+extern kal_uint32 custom_get_1st_ROM_LoadEnd(void);
+
+
+extern kal_status custom_get_ISPRAM_Load_Base(kal_uint8 core_id, kal_uint32 *ret_addr);
+extern kal_status custom_get_ISPRAM_CODE_Base(kal_uint8 core_id, kal_uint32 *ret_addr);
+extern kal_status custom_get_ISPRAM_CODE_End(kal_uint8 core_id, kal_uint32 *ret_addr);
+extern kal_status custom_get_ISPRAM_Base(kal_uint8 core_id, kal_uint32 *ret_addr);
+extern kal_status custom_get_ISPRAM_End(kal_uint8 core_id, kal_uint32 *ret_addr);
+
+extern kal_status custom_get_DSPRAM_Load_Base(kal_uint8 core_id, kal_uint32 *ret_addr);
+extern kal_status custom_get_DSPRAM_DATA_Base(kal_uint8 core_id, kal_uint32 *ret_addr);
+extern kal_status custom_get_DSPRAM_DATA_End(kal_uint8 core_id, kal_uint32 *ret_addr);
+extern kal_status custom_get_DSPRAM_DATA_ZI_Base(kal_uint8 core_id, kal_uint32 *ret_addr);
+extern kal_status custom_get_DSPRAM_DATA_ZI_End(kal_uint8 core_id, kal_uint32 *ret_addr);
+extern kal_status custom_get_DSPRAM_Base(kal_uint8 core_id, kal_uint32 *ret_addr);
+extern kal_status custom_get_DSPRAM_End(kal_uint8 core_id, kal_uint32 *ret_addr);
+
+extern kal_bool custom_query_code_region(kal_uint32 code_addr, kal_uint32 core_id);
+extern kal_bool custom_query_MCURO_HWRW_region(kal_uint32 symbol_addr);
+extern kal_int32 custom_query_dynamic_code_region(DYNAMIC_CODE_MEM_T core_id,DYNAMIC_CODE_REGION_INFO_T **region);
+
+extern kal_int32 custom_get_DSPTXRX_Base(void);
+extern kal_int32 custom_get_DSPTXRX_MaxSize(void);
+extern kal_uint32 custom_get_NVRAM_LTABLE_Base(void);
+extern kal_uint32 custom_get_NVRAM_LTABLE_Length(void);
+
+extern kal_uint32 custom_get_VOLTE_CORE_ZI_base(void);
+extern kal_uint32 custom_get_VOLTE_CORE_ZI_End(void);
+
+extern kal_uint32 custom_get_L2SRAM_L2NC_CODE_base(void);
+extern kal_uint32 custom_get_L2SRAM_L2NC_CODE_load_base(void);
+extern kal_uint32 custom_get_L2SRAM_L2NC_CODE_Length(void);
+extern kal_uint32 custom_get_L2SRAM_L2NC_DATA_base(void);
+extern kal_uint32 custom_get_L2SRAM_L2NC_DATA_load_base(void);
+extern kal_uint32 custom_get_L2SRAM_L2NC_DATA_Length(void);
+extern kal_uint32 custom_get_L2SRAM_L2NC_DATA_ZI_base(void);
+extern kal_uint32 custom_get_L2SRAM_L2NC_DATA_ZI_Length(void);
+extern kal_uint32 custom_get_L2SRAM_L2C_CODE_base(void);
+extern kal_uint32 custom_get_L2SRAM_L2C_CODE_load_base(void);
+extern kal_uint32 custom_get_L2SRAM_L2C_CODE_Length(void);
+extern kal_uint32 custom_get_L2SRAM_L2C_DATA_base(void);
+extern kal_uint32 custom_get_L2SRAM_L2C_DATA_load_base(void);
+extern kal_uint32 custom_get_L2SRAM_L2C_DATA_Length(void);
+extern kal_uint32 custom_get_L2SRAM_L2C_DATA_ZI_base(void);
+extern kal_uint32 custom_get_L2SRAM_L2C_DATA_ZI_Length(void);
+extern kal_uint32 custom_query_EMI_RMPU_region_info(EMI_MPU_REGION_INFO_T **region);
+extern kal_int32 custom_get_SIB_AREA_region(EXTSRAM_REGION_INFO_T **region);
+extern kal_uint32 custom_get_SS_EXT_CSIF_Base(void);
+extern kal_uint32 custom_get_SS_EXT_CSIF_End(void);
+extern kal_uint32 custom_get_NL1_EXT_CSIF_Base(void);
+extern kal_uint32 custom_get_NL1_EXT_CSIF_End(void);
+extern kal_bool custom_query_EMI_region(kal_uint32 region_addr);
+extern kal_uint32 custom_get_MD_RAMEnd(void);
+
+
+#if defined(__ARM9_MMU__) || defined(__ARM11_MMU__) || defined(__MTK_MMU__) || defined(__CR4__) || defined(__MTK_MMU_V2__) || defined(__MIPS_IA__)
+extern kal_int32 custom_mk_ram_info(void);
+#endif /* __ARM9_MMU__ || __ARM11_MMU__ || __MTK_MMU__ || __CR4__ || __MTK_MMU_V2__ || __MIPS_IA__ */
+
+
+#endif /* __MTK_TARGET__ */
+
+#endif /* _CUSTOM_SCATSTRUCT_H */
diff --git a/mcu/custom/system/Template/lds_config/InputSectionRule.txt b/mcu/custom/system/Template/lds_config/InputSectionRule.txt
new file mode 100644
index 0000000..cea4a3f
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSectionRule.txt
@@ -0,0 +1,85 @@
+ [Rule]
+Functions(ROCODE) or Variables(ROData, RW, ZI) can only be wrapped
+in the following input section name with specific conditions:
+<TCM>
+1. To put ROCODE into TCM, please use INTSRAM_ROCODE
+ To put RODATA into TCM, please use INTSRAM_RODATA
+ To put RW into TCM, please use INTSRAM_RW
+ To put ZI into TCM, please use INTSRAM_ZI
+
+<NON CACHEABLE Region>
+2. To put RW into Non Cacheable Region, please use NONCACHEDRW
+ To put ZI into Non Cacheable Region, please use NONCACHEDZI
+
+<DYNAMIC CACHEABLE Default NONCACHEABLE Region>
+3. To put RW into DYNAMIC CACHEABLE Default NONCACHEABLE Region, please use DYNAMICCACHEABLERW_NC
+ To put ZI into DYNAMIC CACHEABLE Default NONCACHEABLE Region, please use DYNAMICCACHEABLEZI_NC
+
+<CACHEABLE Region>
+4. To put ROCODE and RODATA into CACHEABLE region, please do not use any input section name
+ To put RW into CACHEABLE region, do not use any input section name
+ To put ZI into CACHEABLE region, do not use any input section name
+
+<DYNAMIC CACHEABLE Default CACHEABLE Region>
+5. To put RW into DYNAMIC CACHEABLE Default CACHEABLE Region, please use DYNAMICCACHEABLERW_C
+ To put ZI into DYNAMIC CACHEABLE Default CACHEABLE Region, please use DYNAMICCACHEABLEZI_C
+
+For any other requirements, please contact with linker script manager directly.
+
+
+ [How to modify?]
+
+1. To move a function-ABC into a specific region by XXX, you can use:
+__attribute__ ((section ("XXX")))
+void ABC() { ... }
+
+e.g. For moving the function ABC into TCM, you can write as below:
+__attribute__ ((section ("INTSRAM_ROCODE")))
+void ABC() { ... }
+
+
+2. To move a RW variable ABC into a specific region by XXX, you can use:
+__attribute__ ((section ("XXX")))
+int ABC = 10;
+
+e.g. For moving the RW variable ABC into NONCACHEABLE region, you can write as below:
+__attribute__ ((section ("NONCACHEDRW")))
+int ABC = 10;
+
+
+3. To move a ZI variable ABC into a specific region by XXX, you can use:
+__attribute__ ((section ("XXX")))
+int ABC;
+
+e.g. For moving the ZI variable ABC into CACHEABLE region, you can write as below:
+just not to add anything in front of your variable:
+int ABC;
+
+ [FAQ]
+
+1. How to designate a symbol into specific region(e.g. EX_UINIT)
+ in Bootloader but not in MAUI?
+=> Use #if defined(__MINI_BOOTLOADER__) to wrap the symbol.
+ e.g.
+#if defined(__MINI_BOOTLOADER__)
+__attribute__ ((section ("EX_UINIT")))
+#endif
+int ABC = 10;
+
+2. How to designate a symbol into specific region(e.g. EX_UINIT)
+ in Ext_Bootloader but not in MAUI?
+=> Use #if defined(__EXT_BOOTLOADER__) to wrap the symbol.
+ e.g.
+#if defined(__EXT_BOOTLOADER__)
+__attribute__ ((section ("EX_UINIT")))
+#endif
+int ABC = 10;
+
+3. How to designate a symbol into specific region(e.g. NONCACHEDRW)
+ in MAUI but not in Bootloader or Ext_Bootloader?
+=> Use #if !defined(__UBL__) to wrap the symbol.
+ e.g.
+#if defined(__MTK_TARGET__) && !defined(__UBL__)
+__attribute__ ((section ("NONCACHEDRW")))
+#endif
+int ABC = 10;
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/AUROM/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/AUROM/Common.txt
new file mode 100644
index 0000000..2723275
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/AUROM/Common.txt
@@ -0,0 +1,35 @@
+ INT_VECTOR_CODE$$Base = .;
+ *(MIPS_BOOTROM)
+ *bootarm_gcc.obj* (INT_VECTOR_CODE)
+ . = ALIGN(16);
+ INT_VECTOR_CODE$$Limit = .;
+ INT_VECTOR_CODE$$Length = ABSOLUTE(INT_VECTOR_CODE$$Limit - INT_VECTOR_CODE$$Base);
+
+ . = ALIGN(4);
+ BR_EXT$$Base = .;
+ * (BR_EXT_HEAD)
+ * (BR_EXT)
+ . = ALIGN(4);
+ BR_EXT$$Limit = .;
+ BR_EXT$$Length = ABSOLUTE(BR_EXT$$Limit - BR_EXT$$Base);
+
+ . = ALIGN(4);
+ BROM_EXT_SIGNATURE_SECTION$$Base = .;
+ * (BROM_EXT_SIGNATURE_SECTION)
+ . = ALIGN(4);
+ BROM_EXT_SIGNATURE_SECTION$$Limit = .;
+ BROM_EXT_SIGNATURE_SECTION$$Length = ABSOLUTE(BROM_EXT_SIGNATURE_SECTION$$Limit - BROM_EXT_SIGNATURE_SECTION$$Base);
+
+ . = ALIGN(4);
+ AUROM_ROCODE$$Base = .;
+ * (AUROM_ROCODE)
+ . = ALIGN(4);
+ AUROM_ROCODE$$Limit = .;
+ AUROM_ROCODE$$Length = ABSOLUTE(AUROM_ROCODE$$Limit - AUROM_ROCODE$$Base);
+
+ . = ALIGN(4);
+ AUROM_RODATA$$Base = .; /* RODATA should be put in the end of ROM section. CGA will not parsing symbols after this linker symbol */
+ * (AUROM_RODATA)
+ . = ALIGN(4);
+ AUROM_RODATA$$Limit = .;
+ AUROM_RODATA$$Length = ABSOLUTE(AUROM_RODATA$$Limit - AUROM_RODATA$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM/Common.txt
new file mode 100644
index 0000000..f2530f6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM/Common.txt
@@ -0,0 +1,152 @@
+ STACK_INIT$$Base = . ;
+ *stack_init.obj* (.data)
+ *stack_init.obj* (.sdata)
+ STACK_INIT$$Limit = . ;
+ STACK_INIT$$Length = ABSOLUTE(STACK_INIT$$Limit - STACK_INIT$$Base);
+
+#if ((defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)) && (defined(__MD97__) || defined(__MD97P__)))
+ ESL_TEST_RW$$Base = .;
+
+#if defined(__CPUEVAL__)
+ *esl_profile.obj* (.data*)
+ *spv_drv.obj* (.data*)
+ . = ALIGN(64);
+ *libcpueval.a* (.text*)
+#endif
+
+#if defined(__ESL_BENCHMARK_COREMARK_L2CACHE_LOCK__)
+ *core_list_join.obj* (.data*)
+ *core_main.obj* (.data*)
+ *core_matrix.obj* (.data*)
+ *core_state.obj* (.data*)
+ *core_util.obj* (.data*)
+ *core_portme.obj* (.data*)
+#endif
+
+#if defined(__ESL_BENCHMARK_DHRYSTONE_L2CACHE_LOCK__)
+ *dhry_1.obj* (.data*)
+ *dhry_2.obj* (.data*)
+#endif
+
+ ESL_TEST_RW$$Limit = .;
+ ESL_TEST_RW$$Length = ABSOLUTE( ESL_TEST_RW$$Limit - ESL_TEST_RW$$Base);
+
+ . = ALIGN(64);
+ SECTION_L2CACHE_LOCK_ESL_RWDATA$$Base = .;
+ * (SECTION_L2CACHE_LOCK_ESL_RWDATA*)
+ . = ALIGN(64);
+ SECTION_L2CACHE_LOCK_ESL_RWDATA$$Limit = .;
+ SECTION_L2CACHE_LOCK_ESL_RWDATA$$Length = ABSOLUTE( SECTION_L2CACHE_LOCK_ESL_RWDATA$$Limit - SECTION_L2CACHE_LOCK_ESL_RWDATA$$Base);
+
+#endif
+
+ * (.data*)
+ * (FORCE_EMI_DATA) /* for PAE */
+ KEEP(* (Keep_DATA))
+ * (CACHED_EXTSRAM_RW)
+
+ __preinit_array_start = .;
+ KEEP (*(.preinit_array))
+ __preinit_array_end = .;
+
+ /*. = ALIGN(4);*/
+ __init_array_start = .;
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array))
+ __init_array_end = .;
+ /*. = ALIGN(4);*/
+ KEEP(*(.fini))
+
+ /*. = ALIGN(4);*/
+ __fini_array_start = .;
+ KEEP (*(.fini_array))
+ KEEP (*(SORT(.fini_array.*)))
+ __fini_array_end = .;
+
+ /*. = ALIGN(4);*/
+ __CTOR_LIST__ = .;
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+
+ * (.tm_clone_table)
+
+ RELEASE_VERNO_RW$$Base = .;
+ * (RELEASE_VERNO_RW)
+ RELEASE_VERNO_RW$$Limit = .;
+ RELEASE_VERNO_RW$$Length = ABSOLUTE(RELEASE_VERNO_RW$$Limit - RELEASE_VERNO_RW$$Base);
+ RELEASE_BRANCH_RW$$Base = .;
+ * (RELEASE_BRANCH_RW)
+ RELEASE_BRANCH_RW$$Limit = .;
+ RELEASE_BRANCH_RW$$Length = ABSOLUTE(RELEASE_BRANCH_RW$$Limit - RELEASE_BRANCH_RW$$Base);
+ BUILD_TIME_RW$$Base = .;
+ * (BUILD_TIME_RW)
+ BUILD_TIME_RW$$Limit = .;
+ BUILD_TIME_RW$$Length = ABSOLUTE(BUILD_TIME_RW$$Limit - BUILD_TIME_RW$$Base);
+
+ /***** remap to EMI in 92 *****/
+ * (INTSRAM_RODATA* INTSRAM_RW*)
+ * (INTERNBLOCK2_RW)
+ * (EMIINITRW)
+ * (L2SRAM_RW)
+#if defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+ _gp_0 = ABSOLUTE(. + 0x8000);
+ SDATA0$$Base = . ;
+ * (.sdata_0)
+ * (.sdata_0.*)
+ SDATA0$$Limit = . ;
+ SDATA0$$ZI$$Base = . ;
+ * (.sbss_0)
+ * (.sbss_0.*)
+ SDATA0$$ZI$$Limit = . ;
+#ifdef __MD95__
+ * (DSPRAM_RW_CORE0*)
+#endif
+ . = ALIGN(8);
+ _gp_1 = ABSOLUTE(. + 0x8000);
+ SDATA1$$Base = . ;
+ * (.sdata_1)
+ * (.sdata_1.*)
+ SDATA1$$Limit = . ;
+ SDATA1$$ZI$$Base = . ;
+ * (.sbss_1)
+ * (.sbss_1.*)
+ SDATA1$$ZI$$Limit = . ;
+#if defined(__MD97__) || defined(__MD97P__)
+ * (L2CACHE_LOCK_RW)
+#endif
+#ifdef __MD95__
+ * (DSPRAM_RW_CORE0*)
+#endif
+ . = ALIGN(8);
+#endif
+ /***** remap to EMI in 92 *****/
+
+
+ /********************** A. need to be confirmed in 93 **********************/
+ /********************** B. need to be moved to right section in 93 **********************/
+ /********************** C. will be removed in 93 **********************/
+ * (DYNAMIC_SECTION_L2SRAM_UBIN_W_RW)
+ * (DYNAMIC_SECTION_L2SRAM_UBIN_T_RW)
+ * (DATA_CORE2)
+#if !(defined(__MD97__) || defined(__MD97P__))
+ * (L2SRAM_L2C_RW)
+ * (L2SRAM_L2NC_RW)
+#endif
+ _gp_2 = ABSOLUTE(. + 0x8000);
+ SDATA2$$Base = . ;
+ * (.sdata_2)
+ * (.sdata_2.*)
+ SDATA2$$Limit = . ;
+ SDATA2$$ZI$$Base = . ;
+ * (.sbss_2)
+ * (.sbss_2.*)
+ SDATA2$$ZI$$Limit = . ;
+#ifndef __MD95__
+ * (DSPRAM_RW_CORE2*)
+#endif
+ . = ALIGN(8);
+
+
+ * (.sdata*)
+ _gp = . ;
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE0/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE0/Common.txt
new file mode 100644
index 0000000..71a9946
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE0/Common.txt
@@ -0,0 +1,5 @@
+ CACHED_EXTSRAM_CORE0$$Base = .;
+ * (DATA_CORE0) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ CACHED_EXTSRAM_CORE0$$Limit = .;
+ CACHED_EXTSRAM_CORE0$$Length = ABSOLUTE(CACHED_EXTSRAM_CORE0$$Limit - CACHED_EXTSRAM_CORE0$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE0_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE0_ZI/Common.txt
new file mode 100644
index 0000000..b0f2e19
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE0_ZI/Common.txt
@@ -0,0 +1,5 @@
+ CACHED_EXTSRAM_CORE0$$ZI$$Base = .;
+ * (BSS_CORE0) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ CACHED_EXTSRAM_CORE0$$ZI$$Limit = .;
+ CACHED_EXTSRAM_CORE0$$ZI$$Length = ABSOLUTE(CACHED_EXTSRAM_CORE0$$ZI$$Limit - CACHED_EXTSRAM_CORE0$$ZI$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE1/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE1/Common.txt
new file mode 100644
index 0000000..14d9171
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE1/Common.txt
@@ -0,0 +1,5 @@
+ CACHED_EXTSRAM_CORE1$$Base = .;
+ * (DATA_CORE1) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ CACHED_EXTSRAM_CORE1$$Limit = .;
+ CACHED_EXTSRAM_CORE1$$Length = ABSOLUTE(CACHED_EXTSRAM_CORE1$$Limit - CACHED_EXTSRAM_CORE1$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE1_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE1_ZI/Common.txt
new file mode 100644
index 0000000..af3899d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE1_ZI/Common.txt
@@ -0,0 +1,5 @@
+ CACHED_EXTSRAM_CORE1$$ZI$$Base = .;
+ * (BSS_CORE1) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ CACHED_EXTSRAM_CORE1$$ZI$$Limit = .;
+ CACHED_EXTSRAM_CORE1$$ZI$$Length = ABSOLUTE(CACHED_EXTSRAM_CORE1$$ZI$$Limit - CACHED_EXTSRAM_CORE1$$ZI$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE2/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE2/Common.txt
new file mode 100644
index 0000000..dfe46cf
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE2/Common.txt
@@ -0,0 +1,5 @@
+ CACHED_EXTSRAM_CORE2$$Base = .;
+ * (DATA_CORE2) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ CACHED_EXTSRAM_CORE2$$Limit = .;
+ CACHED_EXTSRAM_CORE2$$Length = ABSOLUTE(CACHED_EXTSRAM_CORE2$$Limit - CACHED_EXTSRAM_CORE2$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE2_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE2_ZI/Common.txt
new file mode 100644
index 0000000..e745fc3
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_CORE2_ZI/Common.txt
@@ -0,0 +1,5 @@
+ CACHED_EXTSRAM_CORE2$$ZI$$Base = .;
+ * (BSS_CORE2) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ CACHED_EXTSRAM_CORE2$$ZI$$Limit = .;
+ CACHED_EXTSRAM_CORE2$$ZI$$Length = ABSOLUTE(CACHED_EXTSRAM_CORE2$$ZI$$Limit - CACHED_EXTSRAM_CORE2$$ZI$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW/Common.txt
new file mode 100644
index 0000000..04aa239
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW/Common.txt
@@ -0,0 +1 @@
+ * (IOCU2_NON_ALLOC_MCURW_HWRW_C_RW)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI/Common.txt
new file mode 100644
index 0000000..e353048
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI/Common.txt
@@ -0,0 +1 @@
+ * (IOCU2_NON_ALLOC_MCURW_HWRW_C_ZI)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_00/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_00/Common.txt
new file mode 100644
index 0000000..1dfc822
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_00/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_00_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_01/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_01/Common.txt
new file mode 100644
index 0000000..cd8359d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_01/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_01_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_02/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_02/Common.txt
new file mode 100644
index 0000000..0366b21
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_02/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_02_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_03/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_03/Common.txt
new file mode 100644
index 0000000..f393d39
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_03/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_03_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_04/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_04/Common.txt
new file mode 100644
index 0000000..debbc2b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_04/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_04_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_05/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_05/Common.txt
new file mode 100644
index 0000000..017050d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_05/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_05_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_06/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_06/Common.txt
new file mode 100644
index 0000000..f2a5d64
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_06/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_06_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_07/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_07/Common.txt
new file mode 100644
index 0000000..ba36dc2
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_07/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_07_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_08/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_08/Common.txt
new file mode 100644
index 0000000..34a2886
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_08/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_08_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_09/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_09/Common.txt
new file mode 100644
index 0000000..588ee72
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_09/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_09_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_10/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_10/Common.txt
new file mode 100644
index 0000000..4e586b3
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_10/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_10_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_11/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_11/Common.txt
new file mode 100644
index 0000000..51e21a1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_11/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_11_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_12/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_12/Common.txt
new file mode 100644
index 0000000..1bab575
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_12/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_12_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_13/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_13/Common.txt
new file mode 100644
index 0000000..c663a3d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_13/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_13_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_14/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_14/Common.txt
new file mode 100644
index 0000000..da1f2a9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_14/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_14_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_15/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_15/Common.txt
new file mode 100644
index 0000000..899eca2
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_15/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU2_15_NON_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_ULTRA_DATA/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_ULTRA_DATA/Common.txt
new file mode 100644
index 0000000..8083fc5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_ULTRA_DATA/Common.txt
@@ -0,0 +1,3 @@
+ . = ALIGN(64);
+ *(CACHED_EXTSRAM_IOCU2_ULTRA_DATA_RO)
+ *(CACHED_EXTSRAM_IOCU2_ULTRA_DATA_RW)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_ULTRA_DATA_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_ULTRA_DATA_ZI/Common.txt
new file mode 100644
index 0000000..f7e6ae6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU2_ULTRA_DATA_ZI/Common.txt
@@ -0,0 +1 @@
+ *(CACHED_EXTSRAM_IOCU2_ULTRA_DATA_ZI)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_00/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_00/Common.txt
new file mode 100644
index 0000000..4387d29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_00/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU3_00_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_01/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_01/Common.txt
new file mode 100644
index 0000000..ad2c2cc
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_01/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU3_01_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_02/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_02/Common.txt
new file mode 100644
index 0000000..2da19a5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_02/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU3_02_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_03/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_03/Common.txt
new file mode 100644
index 0000000..ecaf96d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_03/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU3_03_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_04/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_04/Common.txt
new file mode 100644
index 0000000..09424b3
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_04/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU3_04_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_05/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_05/Common.txt
new file mode 100644
index 0000000..c976f3e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_05/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU3_05_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_06/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_06/Common.txt
new file mode 100644
index 0000000..c20140f
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_06/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU3_06_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_07/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_07/Common.txt
new file mode 100644
index 0000000..96614e9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_07/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU3_07_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_08/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_08/Common.txt
new file mode 100644
index 0000000..ba80a56
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_08/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU3_08_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_09/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_09/Common.txt
new file mode 100644
index 0000000..6811264
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_09/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU3_09_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_10/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_10/Common.txt
new file mode 100644
index 0000000..15e8d7e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_10/Common.txt
@@ -0,0 +1,2 @@
+ * (IOCU3_10_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_11/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_11/Common.txt
new file mode 100644
index 0000000..2fa7ea6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_11/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU3_11_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_12/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_12/Common.txt
new file mode 100644
index 0000000..7defe4c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_12/Common.txt
@@ -0,0 +1,2 @@
+ * (IOCU3_12_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_13/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_13/Common.txt
new file mode 100644
index 0000000..b118191
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_13/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU3_13_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_14/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_14/Common.txt
new file mode 100644
index 0000000..bd7bb38
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_14/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU3_14_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_15/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_15/Common.txt
new file mode 100644
index 0000000..d6624af
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_15/Common.txt
@@ -0,0 +1,3 @@
+ * (IOCU3_15_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
+ . = ALIGN(0x10000);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_READ_ALLOC_MCURW_HWRW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_READ_ALLOC_MCURW_HWRW/Common.txt
new file mode 100644
index 0000000..18736ec
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_READ_ALLOC_MCURW_HWRW/Common.txt
@@ -0,0 +1 @@
+ * (IOCU3_READ_ALLOC_MCURW_HWRW_C_RW)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_READ_ALLOC_MCURW_HWRW_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_READ_ALLOC_MCURW_HWRW_ZI/Common.txt
new file mode 100644
index 0000000..9238d18
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_READ_ALLOC_MCURW_HWRW_ZI/Common.txt
@@ -0,0 +1,2 @@
+ * (IOCU3_READ_ALLOC_MCURW_HWRW_C_ZI)
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_READ_WRITE_ALLOC_MCURW_HWRW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_READ_WRITE_ALLOC_MCURW_HWRW/Common.txt
new file mode 100644
index 0000000..1646cef
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_READ_WRITE_ALLOC_MCURW_HWRW/Common.txt
@@ -0,0 +1 @@
+ * (IOCU3_READ_WRITE_ALLOC_MCURW_HWRW_C_RW)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_READ_WRITE_ALLOC_MCURW_HWRW_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_READ_WRITE_ALLOC_MCURW_HWRW_ZI/Common.txt
new file mode 100644
index 0000000..fca3620
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_READ_WRITE_ALLOC_MCURW_HWRW_ZI/Common.txt
@@ -0,0 +1 @@
+ * (IOCU3_READ_WRITE_ALLOC_MCURW_HWRW_C_ZI)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_ULTRA_DATA/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_ULTRA_DATA/Common.txt
new file mode 100644
index 0000000..a836b29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_ULTRA_DATA/Common.txt
@@ -0,0 +1,3 @@
+ . = ALIGN(64);
+ *(CACHED_EXTSRAM_IOCU3_ULTRA_DATA_RO)
+ *(CACHED_EXTSRAM_IOCU3_ULTRA_DATA_RW)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_ULTRA_DATA_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_ULTRA_DATA_ZI/Common.txt
new file mode 100644
index 0000000..f7e6ae6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU3_ULTRA_DATA_ZI/Common.txt
@@ -0,0 +1 @@
+ *(CACHED_EXTSRAM_IOCU2_ULTRA_DATA_ZI)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU_READ_ALLOC_MCURW_HWRW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU_READ_ALLOC_MCURW_HWRW/Common.txt
new file mode 100755
index 0000000..b1018b3
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU_READ_ALLOC_MCURW_HWRW/Common.txt
@@ -0,0 +1 @@
+ * (IOCU_READ_ALLOC_MCURW_HWRW_C_RW)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU_READ_ALLOC_MCURW_HWRW_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU_READ_ALLOC_MCURW_HWRW_ZI/Common.txt
new file mode 100755
index 0000000..5f96593
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_IOCU_READ_ALLOC_MCURW_HWRW_ZI/Common.txt
@@ -0,0 +1 @@
+ * (IOCU_READ_ALLOC_MCURW_HWRW_C_ZI)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_L2CACHE_LOCK_DATA/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_L2CACHE_LOCK_DATA/Common.txt
new file mode 100644
index 0000000..a55aede
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_L2CACHE_LOCK_DATA/Common.txt
@@ -0,0 +1,27 @@
+ . = ALIGN(0x8000); /* align base to 32KB = 0x8000 */
+ L2CACHE_LOCK$$Base = .;
+ /* COMMON ROCODE, RODATA */
+ . = ALIGN(64);
+ L2CACHE_LOCK_ROCODE$$Base = .;
+ *lib_a-memcpy.o (.text)
+ *lib_a-memset.o (.text)
+ L2CACHE_LOCK_ITC_ROCODE$$Base = .;
+ *kal_hw_itc.obj (L2CACHE_LOCK_ROCODE)
+ L2CACHE_LOCK_ITC_ROCODE$$Limit = .;
+ L2CACHE_LOCK_ITC_ROCODE$$Length = ABSOLUTE(L2CACHE_LOCK_ITC_ROCODE$$Limit - L2CACHE_LOCK_ITC_ROCODE$$Base);
+ * (L2CACHE_LOCK_ROCODE*) /* L2 cache lock! align base and end to 64 bytes */
+ . = ALIGN(64);
+ * (L2CACHE_LOCK_RODATA) /* protect by MPU with ROCODE */
+ . = ALIGN(64);
+ L2CACHE_LOCK_ROCODE$$Limit = .;
+ L2CACHE_LOCK_ROCODE$$Length = ABSOLUTE(L2CACHE_LOCK_ROCODE$$Limit - L2CACHE_LOCK_ROCODE$$Base);
+
+ /* COMMON RW */
+ . = ALIGN(64);
+ L2CACHE_LOCK_DATA$$Base = .;
+ * (L2CACHE_LOCK_RW) /* L2 cache lock! align base and end to 64 bytes */
+ . = ALIGN(64);
+ L2CACHE_LOCK_DATA$$Limit = .;
+ L2CACHE_LOCK_DATA$$Length = ABSOLUTE(L2CACHE_LOCK_DATA$$Limit - L2CACHE_LOCK_DATA$$Base);
+
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_L2CACHE_LOCK_DATA_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_L2CACHE_LOCK_DATA_ZI/Common.txt
new file mode 100644
index 0000000..c43b117
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_L2CACHE_LOCK_DATA_ZI/Common.txt
@@ -0,0 +1,14 @@
+ /* COMMON ZI */
+ . = ALIGN(64);
+ L2CACHE_LOCK_ZI$$Base = .;
+ * (L2CACHE_LOCK_ZI) /* L2 cache lock! align base and end to 64 bytes */
+ . = ALIGN(64);
+ L2CACHE_LOCK_ZI$$Limit = .;
+ L2CACHE_LOCK_ZI$$Length = ABSOLUTE(L2CACHE_LOCK_ZI$$Limit - L2CACHE_LOCK_ZI$$Base);
+
+#if defined (__ESL_MASE__) || defined (__GEN93_SPV_UFPS_LOAD__)
+ . = ALIGN(0x8000); /* align end to 32KB = 0x8000 */
+#endif
+ L2CACHE_LOCK$$Limit = .;
+ L2CACHE_LOCK$$Length = ABSOLUTE(L2CACHE_LOCK$$Limit - L2CACHE_LOCK$$Base);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_L2CACHE_LOCK_RO/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_L2CACHE_LOCK_RO/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_L2CACHE_LOCK_RO/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00/Common.txt
new file mode 100644
index 0000000..d176655
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET0.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_01/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_01/Common.txt
new file mode 100644
index 0000000..1c45d07
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_01/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET1.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_02/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_02/Common.txt
new file mode 100644
index 0000000..847a337
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_02/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET2.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_03/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_03/Common.txt
new file mode 100644
index 0000000..8114c69
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_03/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET3.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_04/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_04/Common.txt
new file mode 100644
index 0000000..be3026c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_04/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET4.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_05/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_05/Common.txt
new file mode 100644
index 0000000..3d9f7b2
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_05/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET5.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_06/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_06/Common.txt
new file mode 100644
index 0000000..a14d85b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_06/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET6.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_07/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_07/Common.txt
new file mode 100644
index 0000000..81e52b5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_07/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET7.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_08/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_08/Common.txt
new file mode 100644
index 0000000..60f3b43
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_08/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET8.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_09/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_09/Common.txt
new file mode 100644
index 0000000..330e97a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_09/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET9.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_10/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_10/Common.txt
new file mode 100644
index 0000000..b65839b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_10/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET10.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_11/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_11/Common.txt
new file mode 100644
index 0000000..476c00e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_11/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET11.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_12/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_12/Common.txt
new file mode 100644
index 0000000..6ab45f4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_12/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET12.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_13/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_13/Common.txt
new file mode 100644
index 0000000..44191c5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_13/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET13.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_14/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_14/Common.txt
new file mode 100644
index 0000000..ab744a2
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_14/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET14.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_15/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_15/Common.txt
new file mode 100644
index 0000000..b292166
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_15/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET15.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_16/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_16/Common.txt
new file mode 100644
index 0000000..178b074
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_16/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET16.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_17/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_17/Common.txt
new file mode 100644
index 0000000..6ea050e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_17/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET17.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_18/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_18/Common.txt
new file mode 100644
index 0000000..102f71b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_18/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET18.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_19/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_19/Common.txt
new file mode 100644
index 0000000..54d64e9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_19/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET19.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_20/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_20/Common.txt
new file mode 100644
index 0000000..e011aec
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_20/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET20.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_21/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_21/Common.txt
new file mode 100644
index 0000000..82efa09
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_21/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET21.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_22/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_22/Common.txt
new file mode 100644
index 0000000..52f6934
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_22/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET22.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_23/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_23/Common.txt
new file mode 100644
index 0000000..fad5b44
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_23/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET23.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_24/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_24/Common.txt
new file mode 100644
index 0000000..96c56bb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_24/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET24.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_25/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_25/Common.txt
new file mode 100644
index 0000000..75aaa60
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_25/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET25.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_26/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_26/Common.txt
new file mode 100644
index 0000000..a143eaa
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_26/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET26.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_27/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_27/Common.txt
new file mode 100644
index 0000000..e4d2735
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_27/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET27.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_28/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_28/Common.txt
new file mode 100644
index 0000000..f5d50c0
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_28/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET28.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_29/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_29/Common.txt
new file mode 100644
index 0000000..81ed955
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_29/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET29.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_30/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_30/Common.txt
new file mode 100644
index 0000000..e7b4ffb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_30/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET30.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_31/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_31/Common.txt
new file mode 100644
index 0000000..6b2dc1e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_31/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET31.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_32/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_32/Common.txt
new file mode 100644
index 0000000..8bbaa54
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_32/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET32.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_33/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_33/Common.txt
new file mode 100644
index 0000000..343be70
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_33/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET33.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_34/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_34/Common.txt
new file mode 100644
index 0000000..324041a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_34/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET34.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_35/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_35/Common.txt
new file mode 100644
index 0000000..e4a1377
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_35/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET35.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_36/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_36/Common.txt
new file mode 100644
index 0000000..1f2976b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_36/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET36.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_37/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_37/Common.txt
new file mode 100644
index 0000000..8e76fb1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_37/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET37.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_38/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_38/Common.txt
new file mode 100644
index 0000000..fa16542
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_38/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET38.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_39/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_39/Common.txt
new file mode 100644
index 0000000..674ea2b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_39/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET39.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_40/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_40/Common.txt
new file mode 100644
index 0000000..357bc71
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_40/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET40.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_41/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_41/Common.txt
new file mode 100644
index 0000000..dbc028c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_41/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET41.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_42/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_42/Common.txt
new file mode 100644
index 0000000..b496698
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_42/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET42.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_43/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_43/Common.txt
new file mode 100644
index 0000000..3d41e4a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_43/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET43.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_44/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_44/Common.txt
new file mode 100644
index 0000000..8e1d881
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_44/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET44.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_45/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_45/Common.txt
new file mode 100644
index 0000000..2eec8c1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_45/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET45.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_46/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_46/Common.txt
new file mode 100644
index 0000000..b78e8ce
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_46/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET46.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_47/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_47/Common.txt
new file mode 100644
index 0000000..eb47784
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_47/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET47.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_48/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_48/Common.txt
new file mode 100644
index 0000000..2aea73b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_48/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET48.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_49/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_49/Common.txt
new file mode 100644
index 0000000..30fbd3c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_49/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET49.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_50/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_50/Common.txt
new file mode 100644
index 0000000..549913e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_50/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET50.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_51/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_51/Common.txt
new file mode 100644
index 0000000..109ed62
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_51/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET51.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_52/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_52/Common.txt
new file mode 100644
index 0000000..90e4432
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_52/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET52.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_53/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_53/Common.txt
new file mode 100644
index 0000000..0d805f4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_53/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET53.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_54/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_54/Common.txt
new file mode 100644
index 0000000..f5469b7
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_54/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET54.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_55/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_55/Common.txt
new file mode 100644
index 0000000..259456b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_55/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET55.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_56/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_56/Common.txt
new file mode 100644
index 0000000..65a42c0
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_56/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET56.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_57/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_57/Common.txt
new file mode 100644
index 0000000..3f8e2a0
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_57/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET57.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_58/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_58/Common.txt
new file mode 100644
index 0000000..e9b9178
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_58/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET58.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_59/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_59/Common.txt
new file mode 100644
index 0000000..2d14708
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_59/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET59.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_60/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_60/Common.txt
new file mode 100644
index 0000000..3c9d664
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_60/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET60.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_61/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_61/Common.txt
new file mode 100644
index 0000000..3d54bf8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_61/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET61.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_62/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_62/Common.txt
new file mode 100644
index 0000000..a9a2a6e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_62/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET62.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_63/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_63/Common.txt
new file mode 100644
index 0000000..852e5c8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_63/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.2G.SET63.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00/Common.txt
new file mode 100644
index 0000000..6f7dcb4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET0.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_01/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_01/Common.txt
new file mode 100644
index 0000000..48b5ec5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_01/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET1.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_02/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_02/Common.txt
new file mode 100644
index 0000000..05436ce
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_02/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET2.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_03/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_03/Common.txt
new file mode 100644
index 0000000..f4cf48e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_03/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET3.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_04/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_04/Common.txt
new file mode 100644
index 0000000..2b91c56
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_04/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET4.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_05/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_05/Common.txt
new file mode 100644
index 0000000..f5c38ba
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_05/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET5.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_06/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_06/Common.txt
new file mode 100644
index 0000000..918497f
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_06/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET6.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_07/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_07/Common.txt
new file mode 100644
index 0000000..3218571
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_07/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET7.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_08/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_08/Common.txt
new file mode 100644
index 0000000..c3bdf70
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_08/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET8.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_09/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_09/Common.txt
new file mode 100644
index 0000000..92669db
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_09/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET9.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_10/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_10/Common.txt
new file mode 100644
index 0000000..643ec46
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_10/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET10.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_11/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_11/Common.txt
new file mode 100644
index 0000000..1d04cc1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_11/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET11.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_12/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_12/Common.txt
new file mode 100644
index 0000000..490ab62
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_12/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET12.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_13/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_13/Common.txt
new file mode 100644
index 0000000..b1e2e3d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_13/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET13.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_14/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_14/Common.txt
new file mode 100644
index 0000000..ae3a710
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_14/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET14.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_15/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_15/Common.txt
new file mode 100644
index 0000000..e03803f
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_15/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET15.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_16/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_16/Common.txt
new file mode 100644
index 0000000..d56f03a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_16/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET16.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_17/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_17/Common.txt
new file mode 100644
index 0000000..43313db
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_17/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET17.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_18/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_18/Common.txt
new file mode 100644
index 0000000..47319a4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_18/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET18.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_19/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_19/Common.txt
new file mode 100644
index 0000000..972382d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_19/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET19.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_20/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_20/Common.txt
new file mode 100644
index 0000000..ee3bf64
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_20/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET20.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_21/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_21/Common.txt
new file mode 100644
index 0000000..135a372
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_21/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET21.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_22/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_22/Common.txt
new file mode 100644
index 0000000..d2bc3f8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_22/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET22.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_23/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_23/Common.txt
new file mode 100644
index 0000000..b324f25
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_23/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET23.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_24/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_24/Common.txt
new file mode 100644
index 0000000..30d93fc
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_24/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET24.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_25/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_25/Common.txt
new file mode 100644
index 0000000..a65871d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_25/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET25.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_26/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_26/Common.txt
new file mode 100644
index 0000000..e6ba142
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_26/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET26.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_27/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_27/Common.txt
new file mode 100644
index 0000000..a230bc8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_27/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET27.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_28/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_28/Common.txt
new file mode 100644
index 0000000..1d5b9bb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_28/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET28.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_29/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_29/Common.txt
new file mode 100644
index 0000000..8e61b59
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_29/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET29.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_30/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_30/Common.txt
new file mode 100644
index 0000000..f5572f5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_30/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET30.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_31/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_31/Common.txt
new file mode 100644
index 0000000..6643c35
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_31/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET31.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_32/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_32/Common.txt
new file mode 100644
index 0000000..7afb735
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_32/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET32.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_33/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_33/Common.txt
new file mode 100644
index 0000000..4f3ee45
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_33/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET33.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_34/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_34/Common.txt
new file mode 100644
index 0000000..e75d617
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_34/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET34.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_35/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_35/Common.txt
new file mode 100644
index 0000000..85ea649
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_35/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET35.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_36/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_36/Common.txt
new file mode 100644
index 0000000..378609b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_36/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET36.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_37/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_37/Common.txt
new file mode 100644
index 0000000..1bd8443
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_37/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET37.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_38/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_38/Common.txt
new file mode 100644
index 0000000..c114dd5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_38/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET38.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_39/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_39/Common.txt
new file mode 100644
index 0000000..003adc5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_39/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET39.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_40/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_40/Common.txt
new file mode 100644
index 0000000..ba963c8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_40/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET40.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_41/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_41/Common.txt
new file mode 100644
index 0000000..b25039b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_41/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET41.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_42/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_42/Common.txt
new file mode 100644
index 0000000..c5915b9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_42/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET42.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_43/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_43/Common.txt
new file mode 100644
index 0000000..46751d0
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_43/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET43.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_44/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_44/Common.txt
new file mode 100644
index 0000000..b0efba0
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_44/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET44.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_45/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_45/Common.txt
new file mode 100644
index 0000000..8fcdf5d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_45/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET45.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_46/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_46/Common.txt
new file mode 100644
index 0000000..351170f
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_46/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET46.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_47/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_47/Common.txt
new file mode 100644
index 0000000..2915337
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_47/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET47.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_48/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_48/Common.txt
new file mode 100644
index 0000000..b54f43c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_48/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET48.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_49/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_49/Common.txt
new file mode 100644
index 0000000..41b9c1d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_49/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET49.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_50/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_50/Common.txt
new file mode 100644
index 0000000..ba5a240
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_50/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET50.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_51/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_51/Common.txt
new file mode 100644
index 0000000..a7af732
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_51/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET51.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_52/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_52/Common.txt
new file mode 100644
index 0000000..d09d70e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_52/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET52.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_53/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_53/Common.txt
new file mode 100644
index 0000000..8f4c923
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_53/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET53.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_54/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_54/Common.txt
new file mode 100644
index 0000000..63d65b1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_54/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET54.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_55/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_55/Common.txt
new file mode 100644
index 0000000..8a6bb9e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_55/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET55.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_56/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_56/Common.txt
new file mode 100644
index 0000000..d574f65
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_56/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET56.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_57/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_57/Common.txt
new file mode 100644
index 0000000..2854a3e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_57/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET57.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_58/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_58/Common.txt
new file mode 100644
index 0000000..c887e6d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_58/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET58.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_59/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_59/Common.txt
new file mode 100644
index 0000000..b18e987
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_59/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET59.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_60/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_60/Common.txt
new file mode 100644
index 0000000..13d7d07
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_60/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET60.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_61/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_61/Common.txt
new file mode 100644
index 0000000..51c7ddc
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_61/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET61.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_62/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_62/Common.txt
new file mode 100644
index 0000000..7084f58
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_62/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET62.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_63/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_63/Common.txt
new file mode 100644
index 0000000..5889ae2
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_63/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GFDD.SET63.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00/Common.txt
new file mode 100644
index 0000000..1b32482
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET0.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_01/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_01/Common.txt
new file mode 100644
index 0000000..1011cbc
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_01/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET1.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_02/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_02/Common.txt
new file mode 100644
index 0000000..f3717fa
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_02/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET2.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_03/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_03/Common.txt
new file mode 100644
index 0000000..06ff512
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_03/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET3.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_04/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_04/Common.txt
new file mode 100644
index 0000000..e6018e8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_04/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET4.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_05/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_05/Common.txt
new file mode 100644
index 0000000..e15404b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_05/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET5.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_06/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_06/Common.txt
new file mode 100644
index 0000000..ec25457
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_06/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET6.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_07/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_07/Common.txt
new file mode 100644
index 0000000..3073322
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_07/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET7.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_08/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_08/Common.txt
new file mode 100644
index 0000000..20bd5d7
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_08/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET8.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_09/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_09/Common.txt
new file mode 100644
index 0000000..6e263e6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_09/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET9.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_10/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_10/Common.txt
new file mode 100644
index 0000000..a52ab45
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_10/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET10.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_11/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_11/Common.txt
new file mode 100644
index 0000000..64880de
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_11/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET11.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_12/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_12/Common.txt
new file mode 100644
index 0000000..0b7dfcf
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_12/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET12.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_13/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_13/Common.txt
new file mode 100644
index 0000000..2514da2
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_13/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET13.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_14/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_14/Common.txt
new file mode 100644
index 0000000..b49e9e2
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_14/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET14.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_15/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_15/Common.txt
new file mode 100644
index 0000000..e703ca8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_15/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET15.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_16/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_16/Common.txt
new file mode 100644
index 0000000..d3b8c38
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_16/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET16.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_17/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_17/Common.txt
new file mode 100644
index 0000000..95e87d8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_17/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET17.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_18/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_18/Common.txt
new file mode 100644
index 0000000..95f41fb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_18/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET18.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_19/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_19/Common.txt
new file mode 100644
index 0000000..822a3f6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_19/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET19.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_20/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_20/Common.txt
new file mode 100644
index 0000000..680290b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_20/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET20.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_21/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_21/Common.txt
new file mode 100644
index 0000000..511dafb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_21/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET21.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_22/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_22/Common.txt
new file mode 100644
index 0000000..ea40369
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_22/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET22.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_23/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_23/Common.txt
new file mode 100644
index 0000000..b20331a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_23/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET23.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_24/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_24/Common.txt
new file mode 100644
index 0000000..1fef481
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_24/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET24.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_25/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_25/Common.txt
new file mode 100644
index 0000000..50ab0aa
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_25/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET25.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_26/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_26/Common.txt
new file mode 100644
index 0000000..b7a72a1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_26/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET26.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_27/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_27/Common.txt
new file mode 100644
index 0000000..9c5108b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_27/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET27.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_28/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_28/Common.txt
new file mode 100644
index 0000000..f1e7475
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_28/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET28.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_29/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_29/Common.txt
new file mode 100644
index 0000000..fac6a2b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_29/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET29.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_30/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_30/Common.txt
new file mode 100644
index 0000000..21c220a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_30/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET30.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_31/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_31/Common.txt
new file mode 100644
index 0000000..1d72552
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_31/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET31.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_32/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_32/Common.txt
new file mode 100644
index 0000000..6824e51
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_32/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET32.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_33/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_33/Common.txt
new file mode 100644
index 0000000..36b4f5c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_33/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET33.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_34/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_34/Common.txt
new file mode 100644
index 0000000..2cc769c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_34/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET34.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_35/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_35/Common.txt
new file mode 100644
index 0000000..cec54d8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_35/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET35.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_36/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_36/Common.txt
new file mode 100644
index 0000000..93f2184
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_36/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET36.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_37/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_37/Common.txt
new file mode 100644
index 0000000..a9b2439
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_37/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET37.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_38/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_38/Common.txt
new file mode 100644
index 0000000..d9a71c9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_38/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET38.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_39/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_39/Common.txt
new file mode 100644
index 0000000..e49f488
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_39/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET39.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_40/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_40/Common.txt
new file mode 100644
index 0000000..c54befd
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_40/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET40.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_41/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_41/Common.txt
new file mode 100644
index 0000000..92439d2
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_41/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET41.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_42/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_42/Common.txt
new file mode 100644
index 0000000..76ce012
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_42/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET42.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_43/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_43/Common.txt
new file mode 100644
index 0000000..0bdb722
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_43/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET43.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_44/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_44/Common.txt
new file mode 100644
index 0000000..f617ee4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_44/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET44.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_45/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_45/Common.txt
new file mode 100644
index 0000000..62bf4ec
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_45/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET45.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_46/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_46/Common.txt
new file mode 100644
index 0000000..2ed9245
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_46/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET46.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_47/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_47/Common.txt
new file mode 100644
index 0000000..8c17d0a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_47/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET47.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_48/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_48/Common.txt
new file mode 100644
index 0000000..24b2949
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_48/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET48.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_49/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_49/Common.txt
new file mode 100644
index 0000000..2ce5c77
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_49/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET49.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_50/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_50/Common.txt
new file mode 100644
index 0000000..f68a189
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_50/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET50.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_51/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_51/Common.txt
new file mode 100644
index 0000000..0e1920d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_51/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET51.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_52/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_52/Common.txt
new file mode 100644
index 0000000..c30e66c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_52/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET52.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_53/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_53/Common.txt
new file mode 100644
index 0000000..4485448
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_53/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET53.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_54/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_54/Common.txt
new file mode 100644
index 0000000..754107f
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_54/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET54.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_55/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_55/Common.txt
new file mode 100644
index 0000000..3aaf7d8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_55/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET55.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_56/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_56/Common.txt
new file mode 100644
index 0000000..65276aa
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_56/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET56.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_57/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_57/Common.txt
new file mode 100644
index 0000000..8cc1be8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_57/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET57.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_58/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_58/Common.txt
new file mode 100644
index 0000000..a6ccdd2
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_58/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET58.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_59/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_59/Common.txt
new file mode 100644
index 0000000..10117f4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_59/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET59.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_60/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_60/Common.txt
new file mode 100644
index 0000000..6715373
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_60/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET60.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_61/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_61/Common.txt
new file mode 100644
index 0000000..7df3c0d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_61/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET61.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_62/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_62/Common.txt
new file mode 100644
index 0000000..c90aafb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_62/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET62.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_63/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_63/Common.txt
new file mode 100644
index 0000000..f4473e7
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_63/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.3GTDD.SET63.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00/Common.txt
new file mode 100644
index 0000000..2a9dec2
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET0.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_01/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_01/Common.txt
new file mode 100644
index 0000000..f1dacc4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_01/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET1.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_02/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_02/Common.txt
new file mode 100644
index 0000000..f480754
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_02/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET2.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_03/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_03/Common.txt
new file mode 100644
index 0000000..5ee1f87
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_03/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET3.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_04/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_04/Common.txt
new file mode 100644
index 0000000..ce3b327
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_04/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET4.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_05/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_05/Common.txt
new file mode 100644
index 0000000..a52e5e7
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_05/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET5.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_06/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_06/Common.txt
new file mode 100644
index 0000000..cc52038
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_06/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET6.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_07/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_07/Common.txt
new file mode 100644
index 0000000..626e99e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_07/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET7.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_08/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_08/Common.txt
new file mode 100644
index 0000000..2337be4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_08/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET8.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_09/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_09/Common.txt
new file mode 100644
index 0000000..0761eee
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_09/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET9.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_10/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_10/Common.txt
new file mode 100644
index 0000000..d19a370
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_10/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET10.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_11/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_11/Common.txt
new file mode 100644
index 0000000..ee2217c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_11/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET11.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_12/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_12/Common.txt
new file mode 100644
index 0000000..966f61d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_12/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET12.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_13/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_13/Common.txt
new file mode 100644
index 0000000..94c0e9f
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_13/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET13.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_14/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_14/Common.txt
new file mode 100644
index 0000000..e05bea9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_14/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET14.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_15/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_15/Common.txt
new file mode 100644
index 0000000..80321cd
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_15/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET15.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_16/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_16/Common.txt
new file mode 100644
index 0000000..69789d4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_16/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET16.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_17/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_17/Common.txt
new file mode 100644
index 0000000..7080a28
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_17/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET17.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_18/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_18/Common.txt
new file mode 100644
index 0000000..51ed01f
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_18/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET18.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_19/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_19/Common.txt
new file mode 100644
index 0000000..4bb0ae0
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_19/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET19.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_20/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_20/Common.txt
new file mode 100644
index 0000000..0410cde
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_20/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET20.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_21/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_21/Common.txt
new file mode 100644
index 0000000..b0d7dd7
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_21/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET21.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_22/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_22/Common.txt
new file mode 100644
index 0000000..cd86ebc
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_22/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET22.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_23/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_23/Common.txt
new file mode 100644
index 0000000..59e8858
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_23/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET23.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_24/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_24/Common.txt
new file mode 100644
index 0000000..f4e50f8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_24/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET24.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_25/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_25/Common.txt
new file mode 100644
index 0000000..e8928f1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_25/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET25.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_26/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_26/Common.txt
new file mode 100644
index 0000000..2a74fcc
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_26/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET26.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_27/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_27/Common.txt
new file mode 100644
index 0000000..ec14583
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_27/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET27.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_28/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_28/Common.txt
new file mode 100644
index 0000000..1c00db9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_28/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET28.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_29/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_29/Common.txt
new file mode 100644
index 0000000..9c9258e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_29/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET29.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_30/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_30/Common.txt
new file mode 100644
index 0000000..ea4b568
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_30/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET30.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_31/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_31/Common.txt
new file mode 100644
index 0000000..0111ac2
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_31/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET31.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_32/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_32/Common.txt
new file mode 100644
index 0000000..82e3a0e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_32/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET32.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_33/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_33/Common.txt
new file mode 100644
index 0000000..473fd74
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_33/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET33.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_34/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_34/Common.txt
new file mode 100644
index 0000000..412c179
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_34/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET34.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_35/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_35/Common.txt
new file mode 100644
index 0000000..0ef4c79
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_35/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET35.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_36/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_36/Common.txt
new file mode 100644
index 0000000..e0183b4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_36/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET36.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_37/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_37/Common.txt
new file mode 100644
index 0000000..7646f60
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_37/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET37.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_38/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_38/Common.txt
new file mode 100644
index 0000000..89a3dec
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_38/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET38.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_39/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_39/Common.txt
new file mode 100644
index 0000000..8744189
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_39/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET39.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_40/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_40/Common.txt
new file mode 100644
index 0000000..fb84fa1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_40/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET40.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_41/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_41/Common.txt
new file mode 100644
index 0000000..113e725
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_41/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET41.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_42/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_42/Common.txt
new file mode 100644
index 0000000..1239627
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_42/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET42.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_43/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_43/Common.txt
new file mode 100644
index 0000000..8bc0bba
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_43/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET43.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_44/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_44/Common.txt
new file mode 100644
index 0000000..244b8db
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_44/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET44.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_45/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_45/Common.txt
new file mode 100644
index 0000000..7918090
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_45/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET45.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_46/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_46/Common.txt
new file mode 100644
index 0000000..c025088
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_46/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET46.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_47/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_47/Common.txt
new file mode 100644
index 0000000..53d5bf6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_47/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET47.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_48/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_48/Common.txt
new file mode 100644
index 0000000..dabe8fd
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_48/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET48.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_49/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_49/Common.txt
new file mode 100644
index 0000000..f049686
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_49/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET49.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_50/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_50/Common.txt
new file mode 100644
index 0000000..156ed81
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_50/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET50.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_51/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_51/Common.txt
new file mode 100644
index 0000000..a1ec944
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_51/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET51.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_52/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_52/Common.txt
new file mode 100644
index 0000000..cb549e4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_52/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET52.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_53/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_53/Common.txt
new file mode 100644
index 0000000..56bc4bb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_53/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET53.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_54/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_54/Common.txt
new file mode 100644
index 0000000..103bad6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_54/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET54.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_55/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_55/Common.txt
new file mode 100644
index 0000000..d8d8858
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_55/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET55.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_56/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_56/Common.txt
new file mode 100644
index 0000000..18524ca
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_56/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET56.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_57/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_57/Common.txt
new file mode 100644
index 0000000..d0056a4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_57/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET57.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_58/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_58/Common.txt
new file mode 100644
index 0000000..0e1e3ce
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_58/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET58.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_59/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_59/Common.txt
new file mode 100644
index 0000000..810f471
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_59/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET59.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_60/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_60/Common.txt
new file mode 100644
index 0000000..9da1b3a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_60/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET60.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_61/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_61/Common.txt
new file mode 100644
index 0000000..95be068
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_61/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET61.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_62/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_62/Common.txt
new file mode 100644
index 0000000..16481bc
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_62/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET62.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_63/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_63/Common.txt
new file mode 100644
index 0000000..530f638
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_63/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.C2K.SET63.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00/Common.txt
new file mode 100644
index 0000000..96d1dc2
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET0.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_01/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_01/Common.txt
new file mode 100644
index 0000000..4ee0e8d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_01/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET1.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_02/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_02/Common.txt
new file mode 100644
index 0000000..0a4b529
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_02/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET2.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_03/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_03/Common.txt
new file mode 100644
index 0000000..7fc7190
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_03/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET3.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_04/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_04/Common.txt
new file mode 100644
index 0000000..8161b20
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_04/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET4.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_05/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_05/Common.txt
new file mode 100644
index 0000000..0aa5848
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_05/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET5.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_06/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_06/Common.txt
new file mode 100644
index 0000000..dd9027f
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_06/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET6.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_07/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_07/Common.txt
new file mode 100644
index 0000000..dd804a1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_07/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET7.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_08/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_08/Common.txt
new file mode 100644
index 0000000..6b8f60a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_08/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET8.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_09/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_09/Common.txt
new file mode 100644
index 0000000..407668e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_09/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET9.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_10/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_10/Common.txt
new file mode 100644
index 0000000..1b75b88
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_10/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET10.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_11/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_11/Common.txt
new file mode 100644
index 0000000..aeff2aa
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_11/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET11.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_12/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_12/Common.txt
new file mode 100644
index 0000000..10e960d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_12/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET12.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_13/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_13/Common.txt
new file mode 100644
index 0000000..154789b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_13/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET13.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_14/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_14/Common.txt
new file mode 100644
index 0000000..a70bc6b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_14/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET14.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_15/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_15/Common.txt
new file mode 100644
index 0000000..6f1cd82
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_15/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET15.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_16/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_16/Common.txt
new file mode 100644
index 0000000..6dcd3d1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_16/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET16.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_17/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_17/Common.txt
new file mode 100644
index 0000000..5e95d2e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_17/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET17.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_18/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_18/Common.txt
new file mode 100644
index 0000000..6ad9d7a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_18/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET18.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_19/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_19/Common.txt
new file mode 100644
index 0000000..e6e9de5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_19/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET19.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_20/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_20/Common.txt
new file mode 100644
index 0000000..4be366c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_20/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET20.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_21/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_21/Common.txt
new file mode 100644
index 0000000..dd47cbe
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_21/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET21.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_22/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_22/Common.txt
new file mode 100644
index 0000000..ae68031
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_22/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET22.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_23/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_23/Common.txt
new file mode 100644
index 0000000..423f8b3
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_23/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET23.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_24/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_24/Common.txt
new file mode 100644
index 0000000..1eca019
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_24/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET24.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_25/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_25/Common.txt
new file mode 100644
index 0000000..3b994ce
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_25/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET25.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_26/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_26/Common.txt
new file mode 100644
index 0000000..8a661d1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_26/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET26.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_27/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_27/Common.txt
new file mode 100644
index 0000000..52f0540
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_27/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET27.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_28/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_28/Common.txt
new file mode 100644
index 0000000..c500c7a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_28/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET28.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_29/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_29/Common.txt
new file mode 100644
index 0000000..b5fa38a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_29/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET29.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_30/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_30/Common.txt
new file mode 100644
index 0000000..cd78580
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_30/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET30.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_31/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_31/Common.txt
new file mode 100644
index 0000000..00d8b25
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_31/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET31.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_32/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_32/Common.txt
new file mode 100644
index 0000000..3784f52
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_32/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET32.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_33/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_33/Common.txt
new file mode 100644
index 0000000..f3b8181
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_33/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET33.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_34/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_34/Common.txt
new file mode 100644
index 0000000..34f19ad
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_34/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET34.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_35/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_35/Common.txt
new file mode 100644
index 0000000..bbfc712
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_35/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET35.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_36/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_36/Common.txt
new file mode 100644
index 0000000..f626b0d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_36/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET36.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_37/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_37/Common.txt
new file mode 100644
index 0000000..f292359
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_37/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET37.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_38/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_38/Common.txt
new file mode 100644
index 0000000..a3ca98e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_38/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET38.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_39/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_39/Common.txt
new file mode 100644
index 0000000..c253cad
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_39/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET39.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_40/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_40/Common.txt
new file mode 100644
index 0000000..99d6a85
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_40/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET40.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_41/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_41/Common.txt
new file mode 100644
index 0000000..13639be
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_41/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET41.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_42/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_42/Common.txt
new file mode 100644
index 0000000..788b214
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_42/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET42.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_43/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_43/Common.txt
new file mode 100644
index 0000000..bb15776
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_43/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET43.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_44/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_44/Common.txt
new file mode 100644
index 0000000..f518f26
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_44/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET44.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_45/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_45/Common.txt
new file mode 100644
index 0000000..2b3c305
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_45/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET45.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_46/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_46/Common.txt
new file mode 100644
index 0000000..e61dca2
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_46/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET46.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_47/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_47/Common.txt
new file mode 100644
index 0000000..2f74d0a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_47/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET47.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_48/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_48/Common.txt
new file mode 100644
index 0000000..e219afb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_48/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET48.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_49/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_49/Common.txt
new file mode 100644
index 0000000..3be2667
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_49/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET49.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_50/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_50/Common.txt
new file mode 100644
index 0000000..6130168
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_50/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET50.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_51/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_51/Common.txt
new file mode 100644
index 0000000..c93bf16
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_51/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET51.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_52/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_52/Common.txt
new file mode 100644
index 0000000..33bc5df
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_52/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET52.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_53/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_53/Common.txt
new file mode 100644
index 0000000..833ecb5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_53/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET53.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_54/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_54/Common.txt
new file mode 100644
index 0000000..5425d58
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_54/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET54.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_55/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_55/Common.txt
new file mode 100644
index 0000000..9e5145f
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_55/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET55.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_56/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_56/Common.txt
new file mode 100644
index 0000000..16595f7
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_56/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET56.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_57/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_57/Common.txt
new file mode 100644
index 0000000..5b5adc1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_57/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET57.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_58/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_58/Common.txt
new file mode 100644
index 0000000..afa6801
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_58/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET58.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_59/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_59/Common.txt
new file mode 100644
index 0000000..f2a25f7
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_59/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET59.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_60/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_60/Common.txt
new file mode 100644
index 0000000..27f33b5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_60/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET60.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_61/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_61/Common.txt
new file mode 100644
index 0000000..8abc756
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_61/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET61.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_62/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_62/Common.txt
new file mode 100644
index 0000000..5e16ae9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_62/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET62.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_63/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_63/Common.txt
new file mode 100644
index 0000000..0ce6d94
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_63/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.LTE.SET63.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00/Common.txt
new file mode 100644
index 0000000..214db41
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET0.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_01/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_01/Common.txt
new file mode 100644
index 0000000..c8fa0f6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_01/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET1.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_02/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_02/Common.txt
new file mode 100644
index 0000000..787bcfb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_02/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET2.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_03/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_03/Common.txt
new file mode 100644
index 0000000..9769801
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_03/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET3.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_04/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_04/Common.txt
new file mode 100644
index 0000000..da63816
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_04/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET4.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_05/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_05/Common.txt
new file mode 100644
index 0000000..5f5b6dd
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_05/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET5.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_06/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_06/Common.txt
new file mode 100644
index 0000000..14aafe5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_06/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET6.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_07/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_07/Common.txt
new file mode 100644
index 0000000..78b420d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_07/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET7.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_08/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_08/Common.txt
new file mode 100644
index 0000000..ed855f4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_08/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET8.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_09/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_09/Common.txt
new file mode 100644
index 0000000..b2a22c0
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_09/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET9.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_10/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_10/Common.txt
new file mode 100644
index 0000000..ffc4574
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_10/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET10.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_11/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_11/Common.txt
new file mode 100644
index 0000000..9bca6c2
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_11/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET11.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_12/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_12/Common.txt
new file mode 100644
index 0000000..f4c619c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_12/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET12.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_13/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_13/Common.txt
new file mode 100644
index 0000000..cccce4a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_13/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET13.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_14/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_14/Common.txt
new file mode 100644
index 0000000..1a67c73
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_14/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET14.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_15/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_15/Common.txt
new file mode 100644
index 0000000..5e8fa1e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_15/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET15.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_16/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_16/Common.txt
new file mode 100644
index 0000000..a6df489
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_16/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET16.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_17/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_17/Common.txt
new file mode 100644
index 0000000..3807ea0
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_17/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET17.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_18/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_18/Common.txt
new file mode 100644
index 0000000..0aced15
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_18/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET18.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_19/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_19/Common.txt
new file mode 100644
index 0000000..107f430
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_19/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET19.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_20/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_20/Common.txt
new file mode 100644
index 0000000..4a463df
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_20/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET20.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_21/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_21/Common.txt
new file mode 100644
index 0000000..20c52b1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_21/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET21.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_22/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_22/Common.txt
new file mode 100644
index 0000000..b944f3b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_22/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET22.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_23/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_23/Common.txt
new file mode 100644
index 0000000..73dd023
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_23/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET23.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_24/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_24/Common.txt
new file mode 100644
index 0000000..5ef4a51
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_24/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET24.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_25/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_25/Common.txt
new file mode 100644
index 0000000..4a4a011
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_25/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET25.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_26/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_26/Common.txt
new file mode 100644
index 0000000..614479e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_26/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET26.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_27/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_27/Common.txt
new file mode 100644
index 0000000..d740629
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_27/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET27.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_28/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_28/Common.txt
new file mode 100644
index 0000000..c08e6aa
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_28/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET28.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_29/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_29/Common.txt
new file mode 100644
index 0000000..c432cfe
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_29/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET29.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_30/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_30/Common.txt
new file mode 100644
index 0000000..d9a49be
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_30/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET30.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_31/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_31/Common.txt
new file mode 100644
index 0000000..008cae8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_31/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET31.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_32/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_32/Common.txt
new file mode 100644
index 0000000..96fc510
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_32/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET32.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_33/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_33/Common.txt
new file mode 100644
index 0000000..631ed79
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_33/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET33.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_34/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_34/Common.txt
new file mode 100644
index 0000000..1aefffe
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_34/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET34.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_35/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_35/Common.txt
new file mode 100644
index 0000000..8610b94
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_35/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET35.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_36/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_36/Common.txt
new file mode 100644
index 0000000..e4c8ee6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_36/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET36.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_37/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_37/Common.txt
new file mode 100644
index 0000000..ed56cd3
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_37/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET37.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_38/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_38/Common.txt
new file mode 100644
index 0000000..0cb6e00
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_38/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET38.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_39/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_39/Common.txt
new file mode 100644
index 0000000..e57593f
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_39/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET39.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_40/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_40/Common.txt
new file mode 100644
index 0000000..944f87e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_40/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET40.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_41/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_41/Common.txt
new file mode 100644
index 0000000..4131e04
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_41/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET41.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_42/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_42/Common.txt
new file mode 100644
index 0000000..de7f405
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_42/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET42.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_43/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_43/Common.txt
new file mode 100644
index 0000000..1933214
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_43/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET43.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_44/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_44/Common.txt
new file mode 100644
index 0000000..fa47ce6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_44/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET44.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_45/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_45/Common.txt
new file mode 100644
index 0000000..339db0d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_45/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET45.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_46/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_46/Common.txt
new file mode 100644
index 0000000..e317788
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_46/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET46.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_47/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_47/Common.txt
new file mode 100644
index 0000000..c78bc7c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_47/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET47.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_48/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_48/Common.txt
new file mode 100644
index 0000000..8e22dfc
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_48/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET48.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_49/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_49/Common.txt
new file mode 100644
index 0000000..16ec5e7
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_49/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET49.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_50/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_50/Common.txt
new file mode 100644
index 0000000..90bb0e4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_50/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET50.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_51/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_51/Common.txt
new file mode 100644
index 0000000..9121257
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_51/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET51.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_52/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_52/Common.txt
new file mode 100644
index 0000000..f3952d6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_52/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET52.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_53/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_53/Common.txt
new file mode 100644
index 0000000..885cc42
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_53/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET53.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_54/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_54/Common.txt
new file mode 100644
index 0000000..415e9a6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_54/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET54.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_55/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_55/Common.txt
new file mode 100644
index 0000000..acd1b6e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_55/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET55.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_56/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_56/Common.txt
new file mode 100644
index 0000000..c22bdfb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_56/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET56.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_57/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_57/Common.txt
new file mode 100644
index 0000000..118a218
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_57/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET57.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_58/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_58/Common.txt
new file mode 100644
index 0000000..fe38c28
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_58/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET58.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_59/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_59/Common.txt
new file mode 100644
index 0000000..9b9bf5c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_59/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET59.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_60/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_60/Common.txt
new file mode 100644
index 0000000..7b21bf6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_60/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET60.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_61/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_61/Common.txt
new file mode 100644
index 0000000..5bb6321
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_61/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET61.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_62/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_62/Common.txt
new file mode 100644
index 0000000..c414e5b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_62/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET62.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_63/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_63/Common.txt
new file mode 100644
index 0000000..d059414
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_63/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.MMRF.SET63.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00/Common.txt
new file mode 100644
index 0000000..f5d85c1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET0.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_01/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_01/Common.txt
new file mode 100644
index 0000000..844e831
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_01/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET1.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_02/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_02/Common.txt
new file mode 100644
index 0000000..e4a631c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_02/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET2.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_03/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_03/Common.txt
new file mode 100644
index 0000000..9052ee3
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_03/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET3.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_04/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_04/Common.txt
new file mode 100644
index 0000000..ccc2533
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_04/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET4.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_05/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_05/Common.txt
new file mode 100644
index 0000000..81cf3ab
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_05/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET5.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_06/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_06/Common.txt
new file mode 100644
index 0000000..231fcd4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_06/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET6.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_07/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_07/Common.txt
new file mode 100644
index 0000000..5dd264a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_07/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET7.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_08/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_08/Common.txt
new file mode 100644
index 0000000..994924d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_08/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET8.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_09/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_09/Common.txt
new file mode 100644
index 0000000..73a4500
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_09/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET9.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_10/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_10/Common.txt
new file mode 100644
index 0000000..fc71492
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_10/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET10.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_11/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_11/Common.txt
new file mode 100644
index 0000000..38a923d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_11/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET11.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_12/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_12/Common.txt
new file mode 100644
index 0000000..31a464c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_12/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET12.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_13/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_13/Common.txt
new file mode 100644
index 0000000..3384797
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_13/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET13.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_14/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_14/Common.txt
new file mode 100644
index 0000000..1b7ef52
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_14/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET14.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_15/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_15/Common.txt
new file mode 100644
index 0000000..4607fdc
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_15/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET15.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_16/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_16/Common.txt
new file mode 100644
index 0000000..3e0f607
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_16/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET16.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_17/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_17/Common.txt
new file mode 100644
index 0000000..d558c3f
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_17/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET17.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_18/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_18/Common.txt
new file mode 100644
index 0000000..df25ec7
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_18/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET18.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_19/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_19/Common.txt
new file mode 100644
index 0000000..7e91a59
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_19/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET19.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_20/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_20/Common.txt
new file mode 100644
index 0000000..a8b65cf
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_20/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET20.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_21/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_21/Common.txt
new file mode 100644
index 0000000..79855bb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_21/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET21.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_22/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_22/Common.txt
new file mode 100644
index 0000000..779a97c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_22/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET22.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_23/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_23/Common.txt
new file mode 100644
index 0000000..87c7bb5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_23/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET23.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_24/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_24/Common.txt
new file mode 100644
index 0000000..75c7ccb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_24/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET24.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_25/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_25/Common.txt
new file mode 100644
index 0000000..71b6b43
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_25/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET25.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_26/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_26/Common.txt
new file mode 100644
index 0000000..d5ea44e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_26/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET26.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_27/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_27/Common.txt
new file mode 100644
index 0000000..bc65bd3
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_27/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET27.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_28/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_28/Common.txt
new file mode 100644
index 0000000..b7ee48e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_28/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET28.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_29/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_29/Common.txt
new file mode 100644
index 0000000..499678f
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_29/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET29.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_30/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_30/Common.txt
new file mode 100644
index 0000000..eda6b19
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_30/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET30.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_31/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_31/Common.txt
new file mode 100644
index 0000000..9221860
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_31/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET31.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_32/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_32/Common.txt
new file mode 100644
index 0000000..de41f37
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_32/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET32.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_33/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_33/Common.txt
new file mode 100644
index 0000000..7076fe1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_33/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET33.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_34/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_34/Common.txt
new file mode 100644
index 0000000..bf108e8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_34/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET34.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_35/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_35/Common.txt
new file mode 100644
index 0000000..989e166
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_35/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET35.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_36/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_36/Common.txt
new file mode 100644
index 0000000..8b5b65d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_36/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET36.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_37/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_37/Common.txt
new file mode 100644
index 0000000..dbbe7e6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_37/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET37.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_38/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_38/Common.txt
new file mode 100644
index 0000000..9967ba7
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_38/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET38.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_39/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_39/Common.txt
new file mode 100644
index 0000000..3bdf784
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_39/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET39.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_40/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_40/Common.txt
new file mode 100644
index 0000000..e257553
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_40/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET40.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_41/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_41/Common.txt
new file mode 100644
index 0000000..295cfb6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_41/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET41.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_42/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_42/Common.txt
new file mode 100644
index 0000000..3566981
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_42/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET42.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_43/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_43/Common.txt
new file mode 100644
index 0000000..7370d7c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_43/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET43.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_44/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_44/Common.txt
new file mode 100644
index 0000000..9d53b40
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_44/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET44.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_45/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_45/Common.txt
new file mode 100644
index 0000000..20fd5e8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_45/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET45.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_46/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_46/Common.txt
new file mode 100644
index 0000000..7c25a60
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_46/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET46.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_47/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_47/Common.txt
new file mode 100644
index 0000000..1c9f9a9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_47/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET47.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_48/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_48/Common.txt
new file mode 100644
index 0000000..6731741
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_48/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET48.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_49/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_49/Common.txt
new file mode 100644
index 0000000..dd588e5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_49/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET49.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_50/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_50/Common.txt
new file mode 100644
index 0000000..d09c453
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_50/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET50.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_51/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_51/Common.txt
new file mode 100644
index 0000000..b8108c9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_51/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET51.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_52/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_52/Common.txt
new file mode 100644
index 0000000..11c3ef7
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_52/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET52.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_53/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_53/Common.txt
new file mode 100644
index 0000000..08ff312
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_53/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET53.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_54/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_54/Common.txt
new file mode 100644
index 0000000..24f0f64
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_54/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET54.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_55/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_55/Common.txt
new file mode 100644
index 0000000..4b34383
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_55/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET55.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_56/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_56/Common.txt
new file mode 100644
index 0000000..5d9aba9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_56/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET56.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_57/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_57/Common.txt
new file mode 100644
index 0000000..a750d33
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_57/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET57.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_58/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_58/Common.txt
new file mode 100644
index 0000000..73d6db9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_58/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET58.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_59/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_59/Common.txt
new file mode 100644
index 0000000..cf49c66
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_59/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET59.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_60/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_60/Common.txt
new file mode 100644
index 0000000..39d2f53
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_60/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET60.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_61/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_61/Common.txt
new file mode 100644
index 0000000..57c077d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_61/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET61.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_62/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_62/Common.txt
new file mode 100644
index 0000000..036cd1c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_62/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET62.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_63/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_63/Common.txt
new file mode 100644
index 0000000..3eb4b50
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_63/Common.txt
@@ -0,0 +1,3 @@
+ * (DRDIRODATA.NR.SET63.*)
+ LONG(0); /* dummy word for avoiding empty section */
+ . = ALIGN(CACHELINESIZE); /* align base and len to cacheline size alignment*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_ZI/Common.txt
new file mode 100644
index 0000000..3f68f8d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURO_HWRW_ZI/Common.txt
@@ -0,0 +1 @@
+ * (MCURO_HWRW_C_NOINIT)
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURW_HWRW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURW_HWRW/Common.txt
new file mode 100644
index 0000000..593dcf8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURW_HWRW/Common.txt
@@ -0,0 +1 @@
+ * (MCURW_HWRW_C_RW)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURW_HWRW_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURW_HWRW_ZI/Common.txt
new file mode 100644
index 0000000..dd8c6e7
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_MCURW_HWRW_ZI/Common.txt
@@ -0,0 +1 @@
+ * (MCURW_HWRW_C_ZI)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_NVRAM_LTABLE/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_NVRAM_LTABLE/Common.txt
new file mode 100644
index 0000000..1e72bf2
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_NVRAM_LTABLE/Common.txt
@@ -0,0 +1,19 @@
+ _nvram_ltable$$Base = .;
+ * (_nvram_ltable)
+ /* KEEP(* (_nvram_ltable)) */
+ _nvram_ltable$$Limit = .;
+ _nvram_ltable$$Length = ABSOLUTE(_nvram_ltable$$Limit - _nvram_ltable$$Base);
+ _indirect_init$$Base = .;
+ * (_indirect_init)
+ /* KEEP(* (_indirect_init)) */
+ _indirect_init$$Limit = .;
+ _indirect_init$$Length = ABSOLUTE(_indirect_init$$Limit - _indirect_init$$Base);
+ _fs_filetable$$Base = .;
+ * (_fs_filetable)
+ /* KEEP(* (_fs_filetable)) */
+ _fs_filetable$$Limit = .;
+ _fs_filetable$$Length = ABSOLUTE(_fs_filetable$$Limit - _fs_filetable$$Base);
+ _nvram_callback_tbl$$Base = .;
+ * (_nvram_callback_tbl)
+ _nvram_callback_tbl$$Limit = .;
+ _nvram_callback_tbl$$Length = ABSOLUTE(_nvram_callback_tbl$$Limit - _nvram_callback_tbl$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_PREINIT_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_PREINIT_ZI/Common.txt
new file mode 100644
index 0000000..9654253
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_PREINIT_ZI/Common.txt
@@ -0,0 +1 @@
+ * (CACHED_EXTSRAM_PREINIT_ZI)
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_ULTRA_CODE/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_ULTRA_CODE/Common.txt
new file mode 100644
index 0000000..dedd41a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_ULTRA_CODE/Common.txt
@@ -0,0 +1 @@
+ *(CACHED_EXTSRAM_ULTRA_CODE)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_ULTRA_DATA/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_ULTRA_DATA/Common.txt
new file mode 100644
index 0000000..0cf268c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_ULTRA_DATA/Common.txt
@@ -0,0 +1,3 @@
+ . = ALIGN(64);
+ *(CACHED_EXTSRAM_ULTRA_DATA_RW)
+ *(CACHED_EXTSRAM_ULTRA_DATA_RO)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_ULTRA_DATA_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_ULTRA_DATA_ZI/Common.txt
new file mode 100644
index 0000000..e4225e8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_ULTRA_DATA_ZI/Common.txt
@@ -0,0 +1 @@
+ *(CACHED_EXTSRAM_ULTRA_DATA_ZI)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_WT/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_WT/Common.txt
new file mode 100644
index 0000000..3ac2f75
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_WT/Common.txt
@@ -0,0 +1 @@
+ * (CACHED_EXTSRAM_WT)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_WT_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_WT_ZI/Common.txt
new file mode 100644
index 0000000..a5e8fc7
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_WT_ZI/Common.txt
@@ -0,0 +1 @@
+ * (CACHED_EXTSRAM_WT_ZI)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_ZI/Common.txt
new file mode 100644
index 0000000..7af21a5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_ZI/Common.txt
@@ -0,0 +1,55 @@
+ * (CACHED_EXTSRAM_NOINIT)
+ . = ALIGN(4);
+ STACK_INIT$$ZI$$Base = . ;
+ *stack_init.obj* (.sbss)
+ *stack_init.obj* (.bss)
+ STACK_INIT$$ZI$$Limit = . ;
+ STACK_INIT$$ZI$$Length = ABSOLUTE(STACK_INIT$$ZI$$Limit - STACK_INIT$$ZI$$Base);
+
+#if ((defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)) && (defined(__MD97__) || defined(__MD97P__)))
+ ESL_TEST_ZI$$Base = .;
+#if defined(__CPUEVAL__)
+ *spv_drv.obj* (.bss*)
+ *esl_profile.obj* (.bss*)
+
+ . = ALIGN(64);
+ *stack_init.obj* (CACHED_EXTSRAM_ZI)
+
+ . = ALIGN(64);
+ *libcpueval.a* (.bss*)
+#endif
+
+#if defined(__ESL_BENCHMARK_COREMARK_L2CACHE_LOCK__)
+ . = ALIGN(64);
+ *stack_init.obj* (CACHED_EXTSRAM_ZI)
+ . = ALIGN(64);
+ *core_list_join.obj* (.bss*)
+ *core_main.obj* (.bss*)
+ *core_matrix.obj* (.bss*)
+ *core_state.obj* (.bss*)
+ *core_util.obj* (.bss*)
+ *core_portme.obj* (.bss*)
+#endif
+
+#if defined(__ESL_BENCHMARK_DHRYSTONE_L2CACHE_LOCK__)
+ . = ALIGN(64);
+ *stack_init.obj* (CACHED_EXTSRAM_ZI)
+ . = ALIGN(64);
+ *dhry_1.obj* (.bss*)
+ *dhry_2.obj* (.bss*)
+#endif
+
+ ESL_TEST_ZI$$Limit = .;
+ ESL_TEST_ZI$$Length = ABSOLUTE( ESL_TEST_ZI$$Limit - ESL_TEST_ZI$$Base);
+
+ . = ALIGN(64);
+ SECTION_L2CACHE_LOCK_ESL_ZI$$Base = .;
+ * (SECTION_L2CACHE_LOCK_ESL_ZI*)
+ . = ALIGN(64);
+ SECTION_L2CACHE_LOCK_ESL_ZI$$Limit = .;
+ SECTION_L2CACHE_LOCK_ESL_ZI$$Length = ABSOLUTE( SECTION_L2CACHE_LOCK_ESL_ZI$$Limit - SECTION_L2CACHE_LOCK_ESL_ZI$$Base);
+
+
+#endif
+
+ * (CACHED_EXTSRAM_ZI)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_ZI_VOLTE_CORE3/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_ZI_VOLTE_CORE3/Common.txt
new file mode 100644
index 0000000..14e3ec9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/CACHED_EXTSRAM_ZI_VOLTE_CORE3/Common.txt
@@ -0,0 +1 @@
+ KEEP (* (VOLTE_CORE_MCURW_HWRW_CACHEDZI)) /* extern size to 32 MB (use 216 MB ~ 248 MB) */
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DSPRAM0/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DSPRAM0/Common.txt
new file mode 100644
index 0000000..c3731d8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DSPRAM0/Common.txt
@@ -0,0 +1,12 @@
+ _gp_0 = ABSOLUTE(ORIGIN(DSPRAM0) + 0x8000);
+ SDATA0$$Base = . ;
+ * (.sdata_0)
+ * (.sdata_0.*)
+ SDATA0$$Limit = . ;
+ SDATA0$$ZI$$Base = . ;
+ * (.sbss_0)
+ * (.sbss_0.*)
+ SDATA0$$ZI$$Limit = . ;
+ * (DSPRAM_RODATA_CORE0*)
+ * (DSPRAM_RW_CORE0*)
+ . = ALIGN(8);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DSPRAM0_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DSPRAM0_ZI/Common.txt
new file mode 100644
index 0000000..608d143
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DSPRAM0_ZI/Common.txt
@@ -0,0 +1,2 @@
+ * (DSPRAM_ZI_CORE0*)
+ . = ALIGN(8);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DSPRAM1/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DSPRAM1/Common.txt
new file mode 100644
index 0000000..c6c354e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DSPRAM1/Common.txt
@@ -0,0 +1,12 @@
+ _gp_1 = ABSOLUTE(ORIGIN(DSPRAM1) + 0x8000);
+ SDATA1$$Base = . ;
+ * (.sdata_1)
+ * (.sdata_1.*)
+ SDATA1$$Limit = . ;
+ SDATA1$$ZI$$Base = . ;
+ * (.sbss_1)
+ * (.sbss_1.*)
+ SDATA1$$ZI$$Limit = . ;
+ * (DSPRAM_RODATA_CORE1*)
+ * (DSPRAM_RW_CORE1*)
+ . = ALIGN(8);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DSPRAM1_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DSPRAM1_ZI/Common.txt
new file mode 100644
index 0000000..199aae8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DSPRAM1_ZI/Common.txt
@@ -0,0 +1,2 @@
+ * (DSPRAM_ZI_CORE1*)
+ . = ALIGN(8);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DSPRAM2/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DSPRAM2/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DSPRAM2/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DSPRAM2_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DSPRAM2_ZI/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DSPRAM2_ZI/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_RW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_RW/Common.txt
new file mode 100644
index 0000000..176e6e8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_RW/Common.txt
@@ -0,0 +1,7 @@
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_RW$$Base = .;
+ * (DYNAMICCACHEABLERW_C_CORE0) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_RW$$Limit = .;
+
+
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_RW$$Length = ABSOLUTE(DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_RW$$Limit - DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_RW$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_ZI/Common.txt
new file mode 100644
index 0000000..c0b25e9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_ZI/Common.txt
@@ -0,0 +1,5 @@
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_ZI$$ZI$$Base = .;
+ * (DYNAMICCACHEABLEZI_C_CORE0) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_ZI$$ZI$$Limit = .;
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_ZI$$ZI$$Length = ABSOLUTE(DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_ZI$$ZI$$Limit - DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_ZI$$ZI$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_RW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_RW/Common.txt
new file mode 100644
index 0000000..a2f92c4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_RW/Common.txt
@@ -0,0 +1,7 @@
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_RW$$Base = .;
+ * (DYNAMICCACHEABLERW_C_CORE1) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_RW$$Limit = .;
+
+
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_RW$$Length = ABSOLUTE(DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_RW$$Limit - DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_RW$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_ZI/Common.txt
new file mode 100644
index 0000000..7925681
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_ZI/Common.txt
@@ -0,0 +1,5 @@
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_ZI$$ZI$$Base = .;
+ * (DYNAMICCACHEABLEZI_C_CORE1) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_ZI$$ZI$$Limit = .;
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_ZI$$ZI$$Length = ABSOLUTE(DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_ZI$$ZI$$Limit - DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_ZI$$ZI$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_RW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_RW/Common.txt
new file mode 100644
index 0000000..fb9f547
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_RW/Common.txt
@@ -0,0 +1,7 @@
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_RW$$Base = .;
+ * (DYNAMICCACHEABLERW_C_CORE2) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_RW$$Limit = .;
+
+
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_RW$$Length = ABSOLUTE(DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_RW$$Limit - DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_RW$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_ZI/Common.txt
new file mode 100644
index 0000000..b80ab17
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_ZI/Common.txt
@@ -0,0 +1,5 @@
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_ZI$$ZI$$Base = .;
+ * (DYNAMICCACHEABLEZI_C_CORE2) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_ZI$$ZI$$Limit = .;
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_ZI$$ZI$$Length = ABSOLUTE(DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_ZI$$ZI$$Limit - DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE2_ZI$$ZI$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW_ZI/Common.txt
new file mode 100644
index 0000000..6247a7d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW_ZI/Common.txt
@@ -0,0 +1 @@
+ * (MCURO_HWRW_DC_NOINIT)
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW/Common.txt
new file mode 100644
index 0000000..bab8202
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW/Common.txt
@@ -0,0 +1 @@
+ * (MCURW_HWRW_DC_RW)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW_ZI/Common.txt
new file mode 100644
index 0000000..531225c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW_ZI/Common.txt
@@ -0,0 +1 @@
+ * (MCURW_HWRW_DC_ZI)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_RW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_RW/Common.txt
new file mode 100644
index 0000000..976acbb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_RW/Common.txt
@@ -0,0 +1,9 @@
+ * (DYNAMICCACHEABLERW_C)
+
+
+ /********************** A. need to be confirmed in 93 **********************/
+ /********************** B. need to be moved to right section in 93 **********************/
+ /********************** C. will be removed in 93 **********************/
+ . = ALIGN(CACHELINESIZE);
+ * (DYNAMICCACHEABLERW_NC_CORE2) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_ZI/Common.txt
new file mode 100644
index 0000000..90fe4f5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_ZI/Common.txt
@@ -0,0 +1,9 @@
+ /********************** A. need to be confirmed in 93 **********************/
+ /********************** B. need to be moved to right section in 93 **********************/
+ /********************** C. will be removed in 93 **********************/
+ . = ALIGN(CACHELINESIZE);
+ * (DYNAMICCACHEABLEZI_C_CORE2) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+
+
+ * (DYNAMICCACHEABLEZI_C*)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_RW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_RW/Common.txt
new file mode 100644
index 0000000..76d0ccc
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_RW/Common.txt
@@ -0,0 +1,5 @@
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_RW$$Base = .;
+ * (DYNAMICCACHEABLERW_NC_CORE0) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_RW$$Limit = .;
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_RW$$Length = ABSOLUTE(DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_RW$$Limit - DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_RW$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_ZI/Common.txt
new file mode 100644
index 0000000..26d4367
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_ZI/Common.txt
@@ -0,0 +1,5 @@
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_ZI$$ZI$$Base = .;
+ * (DYNAMICCACHEABLEZI_NC_CORE0) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_ZI$$ZI$$Limit = .;
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_ZI$$ZI$$Length = ABSOLUTE(DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_ZI$$ZI$$Limit - DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_ZI$$ZI$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_RW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_RW/Common.txt
new file mode 100644
index 0000000..bf7de6c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_RW/Common.txt
@@ -0,0 +1,5 @@
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_RW$$Base = .;
+ * (DYNAMICCACHEABLERW_NC_CORE1) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_RW$$Limit = .;
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_RW$$Length = ABSOLUTE(DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_RW$$Limit - DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_RW$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_ZI/Common.txt
new file mode 100644
index 0000000..23e0682
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_ZI/Common.txt
@@ -0,0 +1,5 @@
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_ZI$$ZI$$Base = .;
+ * (DYNAMICCACHEABLEZI_NC_CORE1) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_ZI$$ZI$$Limit = .;
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_ZI$$ZI$$Length = ABSOLUTE(DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_ZI$$ZI$$Limit - DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_ZI$$ZI$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_RW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_RW/Common.txt
new file mode 100644
index 0000000..9ba8fa3
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_RW/Common.txt
@@ -0,0 +1,5 @@
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_RW$$Base = .;
+ * (DYNAMICCACHEABLERW_NC_CORE2) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_RW$$Limit = .;
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_RW$$Length = ABSOLUTE(DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_RW$$Limit - DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_RW$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_ZI/Common.txt
new file mode 100644
index 0000000..2ab176a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_ZI/Common.txt
@@ -0,0 +1,5 @@
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_ZI$$ZI$$Base = .;
+ * (DYNAMICCACHEABLEZI_NC_CORE2) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_ZI$$ZI$$Limit = .;
+ DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_ZI$$ZI$$Length = ABSOLUTE(DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_ZI$$ZI$$Limit - DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE2_ZI$$ZI$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CSIF_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CSIF_ZI/Common.txt
new file mode 100644
index 0000000..e6a7fe6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CSIF_ZI/Common.txt
@@ -0,0 +1,12 @@
+#if (defined(MT6885) || defined(MT6873)) && !defined(MT6893)
+ /*Ensure that SS_EXT_CSIF start is allways over 4MB*/
+ . = . <= 0x400000 ? 0x400000 - Image$$DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW$$ZI$$Base : . ;
+ . = ALIGN(64);
+ Image$$MCURW_HWRW_DNC_SS_EXT_CSIF$$Base = . ;
+ * (MCURW_HWRW_DNC_SS_EXT_CSIF)
+ Image$$MCURW_HWRW_DNC_SS_EXT_CSIF$$Limit = . ;
+ . = ALIGN(64);
+ Image$$MCURW_HWRW_DNC_NL1_EXT_CSIF$$Base = . ;
+ * (MCURW_HWRW_DNC_NL1_EXT_CSIF)
+ Image$$MCURW_HWRW_DNC_NL1_EXT_CSIF$$Limit = . ;
+#endif
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW_ZI/Common.txt
new file mode 100644
index 0000000..c6a2f1b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW_ZI/Common.txt
@@ -0,0 +1 @@
+ * (MCURO_HWRW_DNC_NOINIT)
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW/Common.txt
new file mode 100644
index 0000000..f233380
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW/Common.txt
@@ -0,0 +1 @@
+ * (MCURW_HWRW_DNC_RW)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW_ZI/Common.txt
new file mode 100644
index 0000000..1130051
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW_ZI/Common.txt
@@ -0,0 +1,13 @@
+ * (MCURW_HWRW_DNC_ZI)
+#if (defined(__MD97__) && !defined(MT6885) && !defined(MT6873)) || defined(MT6893)
+ /*Ensure that SS_EXT_CSIF start is allways over 4MB*/
+ . = . <= 0x400000 ? 0x400000 - Image$$DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW$$ZI$$Base : . ;
+ . = ALIGN(64);
+ Image$$MCURW_HWRW_DNC_SS_EXT_CSIF$$Base = . ;
+ * (MCURW_HWRW_DNC_SS_EXT_CSIF)
+ Image$$MCURW_HWRW_DNC_SS_EXT_CSIF$$Limit = . ;
+ . = ALIGN(64);
+ Image$$MCURW_HWRW_DNC_NL1_EXT_CSIF$$Base = . ;
+ * (MCURW_HWRW_DNC_NL1_EXT_CSIF)
+ Image$$MCURW_HWRW_DNC_NL1_EXT_CSIF$$Limit = . ;
+#endif
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_RW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_RW/Common.txt
new file mode 100644
index 0000000..6ff6028
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_RW/Common.txt
@@ -0,0 +1,9 @@
+ * (DYNAMICCACHEABLERW_NC)
+
+
+ /********************** A. need to be confirmed in 93 **********************/
+ /********************** B. need to be moved to right section in 93 **********************/
+ /********************** C. will be removed in 93 **********************/
+ . = ALIGN(CACHELINESIZE);
+ * (DYNAMICCACHEABLERW_C_CORE2) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_ZI/Common.txt
new file mode 100644
index 0000000..e3d3617
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_ZI/Common.txt
@@ -0,0 +1,14 @@
+ . = ALIGN(CACHELINESIZE);
+ MCURW_HWRO_DNC_NOINIT$$Base = . ;
+ * (MCURW_HWRO_DNC_NOINIT)
+ . = ALIGN(CACHELINESIZE);
+ MCURW_HWRO_DNC_NOINIT$$Limit = . ;
+ MCURW_HWRO_DNC_NOINIT$$Length = ABSOLUTE(MCURW_HWRO_DNC_NOINIT$$Limit - MCURW_HWRO_DNC_NOINIT$$Base);
+ /********************** A. need to be confirmed in 93 **********************/
+ /********************** B. need to be moved to right section in 93 **********************/
+ /********************** C. will be removed in 93 **********************/
+ . = ALIGN(CACHELINESIZE);
+ * (DYNAMICCACHEABLEZI_NC_CORE2) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+
+ * (DYNAMICCACHEABLEZI_NC*)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_ADT_L_CODE/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_ADT_L_CODE/Common.txt
new file mode 100644
index 0000000..dfaba31
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_ADT_L_CODE/Common.txt
@@ -0,0 +1,3 @@
+ * (DYNAMIC_SECTION_ISPRAM0_ADT_L_ROCODE)
+ LONG(0);
+ . = ALIGN(8);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_ADT_T_CODE/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_ADT_T_CODE/Common.txt
new file mode 100644
index 0000000..09cfd59
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_ADT_T_CODE/Common.txt
@@ -0,0 +1,3 @@
+ * (DYNAMIC_SECTION_ISPRAM0_ADT_T_ROCODE)
+ LONG(0);
+ . = ALIGN(8);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_ADT_W2_CODE/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_ADT_W2_CODE/Common.txt
new file mode 100644
index 0000000..76d75b9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_ADT_W2_CODE/Common.txt
@@ -0,0 +1,3 @@
+ * (DYNAMIC_SECTION_ISPRAM0_ADT_W2_ROCODE)
+ LONG(0);
+ . = ALIGN(8);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_ADT_W_CODE/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_ADT_W_CODE/Common.txt
new file mode 100644
index 0000000..0f97ede
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_ADT_W_CODE/Common.txt
@@ -0,0 +1,4 @@
+ * (DYNAMIC_SECTION_ISPRAM0_ADT_W_ROCODE)
+ LONG(0);
+ . = ALIGN(8);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_UBIN_T_CODE/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_UBIN_T_CODE/Common.txt
new file mode 100644
index 0000000..d434569
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_UBIN_T_CODE/Common.txt
@@ -0,0 +1,4 @@
+ * (DYNAMIC_SECTION_ISPRAM0_UBIN_T_ROCODE)
+ LONG(0);
+ . = ALIGN(8);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_UBIN_W_CODE/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_UBIN_W_CODE/Common.txt
new file mode 100644
index 0000000..bf30118
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/DYNAMIC_SECTION_ISPRAM0_UBIN_W_CODE/Common.txt
@@ -0,0 +1,4 @@
+ * (DYNAMIC_SECTION_ISPRAM0_UBIN_W_ROCODE)
+ LONG(0);
+ . = ALIGN(8);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EMIINIT_CODE/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EMIINIT_CODE/Common.txt
new file mode 100644
index 0000000..288619c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EMIINIT_CODE/Common.txt
@@ -0,0 +1 @@
+ * (EMIINITCODE EMIINITCONST EMIINITRW)
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EMIINIT_CODE/Common_ZI.txt b/mcu/custom/system/Template/lds_config/InputSections/EMIINIT_CODE/Common_ZI.txt
new file mode 100644
index 0000000..665f8d8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EMIINIT_CODE/Common_ZI.txt
@@ -0,0 +1 @@
+ * (EMIINITZI)
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM/Common.txt
new file mode 100644
index 0000000..2e658c0
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM/Common.txt
@@ -0,0 +1,19 @@
+ * (NONCACHEDRW)
+
+
+ /********************** A. need to be confirmed in 93 **********************/
+ /********************** B. need to be moved to right section in 93 **********************/
+ /********************** C. will be removed in 93 **********************/
+ * (NONCACHEDRW_CORE2)
+
+
+ /* continuous physical region - should be continuous with PHY_EXTSRAM_ZI! */
+ /* Caution: PHY_EXTSRAM_RW should be in the bottom of this region and kept 64 bytes aligned */
+ . = ALIGN(64);
+ PHY_EXTSRAM_RW$$Base = .;
+ * (PHY_EXTSRAM_RW)
+ . = ALIGN(4);
+ PHY_EXTSRAM_RW$$Limit = .;
+ PHY_EXTSRAM_RW$$Length = ABSOLUTE(PHY_EXTSRAM_RW$$Limit - PHY_EXTSRAM_RW$$Base);
+
+
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE0/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE0/Common.txt
new file mode 100644
index 0000000..6b31af8
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE0/Common.txt
@@ -0,0 +1,5 @@
+ EXTSRAM_CORE0$$Base = .;
+ * (NONCACHEDRW_CORE0) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ EXTSRAM_CORE0$$Limit = .;
+ EXTSRAM_CORE0$$Length = ABSOLUTE(EXTSRAM_CORE0$$Limit - EXTSRAM_CORE0$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE0_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE0_ZI/Common.txt
new file mode 100644
index 0000000..b93e8a6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE0_ZI/Common.txt
@@ -0,0 +1,5 @@
+ EXTSRAM_CORE0$$ZI$$Base = .;
+ * (NONCACHEDZI_CORE0) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ EXTSRAM_CORE0$$ZI$$Limit = .;
+ EXTSRAM_CORE0$$ZI$$Length = ABSOLUTE(EXTSRAM_CORE0$$ZI$$Limit - EXTSRAM_CORE0$$ZI$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE1/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE1/Common.txt
new file mode 100644
index 0000000..56e4ea7
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE1/Common.txt
@@ -0,0 +1,5 @@
+ EXTSRAM_CORE1$$Base = .;
+ * (NONCACHEDRW_CORE1) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ EXTSRAM_CORE1$$Limit = .;
+ EXTSRAM_CORE1$$Length = ABSOLUTE(EXTSRAM_CORE1$$Limit - EXTSRAM_CORE1$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE1_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE1_ZI/Common.txt
new file mode 100644
index 0000000..ac68920
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE1_ZI/Common.txt
@@ -0,0 +1,5 @@
+ EXTSRAM_CORE1$$ZI$$Base = .;
+ * (NONCACHEDZI_CORE1) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ EXTSRAM_CORE1$$ZI$$Limit = .;
+ EXTSRAM_CORE1$$ZI$$Length = ABSOLUTE(EXTSRAM_CORE1$$ZI$$Limit - EXTSRAM_CORE1$$ZI$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE2/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE2/Common.txt
new file mode 100644
index 0000000..fd7b33d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE2/Common.txt
@@ -0,0 +1,5 @@
+ EXTSRAM_CORE2$$Base = .;
+ * (NONCACHEDRW_CORE2) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ EXTSRAM_CORE2$$Limit = .;
+ EXTSRAM_CORE2$$Length = ABSOLUTE(EXTSRAM_CORE2$$Limit - EXTSRAM_CORE2$$Base);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE2_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE2_ZI/Common.txt
new file mode 100644
index 0000000..0dcac84
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_CORE2_ZI/Common.txt
@@ -0,0 +1,6 @@
+ EXTSRAM_CORE2$$ZI$$Base = .;
+ * (NONCACHEDZI_CORE2) /* base and end align to cache line size */
+ . = ALIGN(CACHELINESIZE);
+ EXTSRAM_CORE2$$ZI$$Limit = .;
+ EXTSRAM_CORE2$$ZI$$Length = ABSOLUTE(EXTSRAM_CORE2$$ZI$$Limit - EXTSRAM_CORE2$$ZI$$Base);
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_DSP_RX/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_DSP_RX/Common.txt
new file mode 100644
index 0000000..ad4d395
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_DSP_RX/Common.txt
@@ -0,0 +1,2 @@
+ * (EXTRAM_RXDATA)
+ LONG(0); /* add this to avoid the last section to be empty section */
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_DSP_RX_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_DSP_RX_ZI/Common.txt
new file mode 100755
index 0000000..ad4d395
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_DSP_RX_ZI/Common.txt
@@ -0,0 +1,2 @@
+ * (EXTRAM_RXDATA)
+ LONG(0); /* add this to avoid the last section to be empty section */
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_DSP_TX/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_DSP_TX/Common.txt
new file mode 100644
index 0000000..9c7387b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_DSP_TX/Common.txt
@@ -0,0 +1,2 @@
+ * (EXTRAM_TXDATA)
+ LONG(0); /* add this to avoid this fix length section to be empty section */
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_DSP_TX_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_DSP_TX_ZI/Common.txt
new file mode 100755
index 0000000..9c7387b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_DSP_TX_ZI/Common.txt
@@ -0,0 +1,2 @@
+ * (EXTRAM_TXDATA)
+ LONG(0); /* add this to avoid this fix length section to be empty section */
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_FS_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_FS_ZI/Common.txt
new file mode 100644
index 0000000..b116bc1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_FS_ZI/Common.txt
@@ -0,0 +1 @@
+ KEEP(*flash_mtd.ramdisk.obj* (STATICZI))
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSPBIN_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSPBIN_ZI/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSPBIN_ZI/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6295M.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6295M.txt
new file mode 100644
index 0000000..866d24e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6295M.txt
@@ -0,0 +1,5 @@
+ DSP_TEMP_ROM_SPACE$$Base = .;
+ * (DSP_BIN_ZI)
+ DSP_TEMP_ROM_SPACE$$Limit = .;
+ DSP_TEMP_ROM_SPACE$$Length = ABSOLUTE(DSP_TEMP_ROM_SPACE$$Limit - DSP_TEMP_ROM_SPACE$$Base);
+ . = DSP_TEMP_ROM_SPACE$$Base + 0x2000000;
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6297.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6297.txt
new file mode 100644
index 0000000..5d4c792
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6297.txt
@@ -0,0 +1,43 @@
+#ifdef MT6297
+ . += 0x01280000;
+ DSP_TEMP_ROM_SPACE$$Base = .;
+ * (DSP_BIN_ZI)
+ DSP_TEMP_ROM_SPACE$$Limit = .;
+ DSP_TEMP_ROM_SPACE$$Length = ABSOLUTE(DSP_TEMP_ROM_SPACE$$Limit - DSP_TEMP_ROM_SPACE$$Base);
+ . = DSP_TEMP_ROM_SPACE$$Base + 0x2B00000;
+#elif defined(MT6885) || defined(MT6893)
+ . += 0x01FA4000;
+ DSP_TEMP_ROM_SPACE$$Base = .;
+ * (DSP_BIN_ZI)
+ . = DSP_TEMP_ROM_SPACE$$Base + 0x1800000;
+ DSP_TEMP_ROM_SPACE$$Limit = .;
+ DSP_TEMP_ROM_SPACE$$Length = ABSOLUTE(DSP_TEMP_ROM_SPACE$$Limit - DSP_TEMP_ROM_SPACE$$Base);
+#elif defined(MT6873)
+ . += 0x01D40000;
+ DSP_TEMP_ROM_SPACE$$Base = .;
+ * (DSP_BIN_ZI)
+ . = DSP_TEMP_ROM_SPACE$$Base + 0x1800000;
+ DSP_TEMP_ROM_SPACE$$Limit = .;
+ DSP_TEMP_ROM_SPACE$$Length = ABSOLUTE(DSP_TEMP_ROM_SPACE$$Limit - DSP_TEMP_ROM_SPACE$$Base);
+#elif defined(MT6853) || defined(MT6833)
+ . += 0x01D40000;
+ DSP_TEMP_ROM_SPACE$$Base = .;
+ * (DSP_BIN_ZI)
+ . = DSP_TEMP_ROM_SPACE$$Base + 0xB00000;
+ DSP_TEMP_ROM_SPACE$$Limit = .;
+ DSP_TEMP_ROM_SPACE$$Length = ABSOLUTE(DSP_TEMP_ROM_SPACE$$Limit - DSP_TEMP_ROM_SPACE$$Base);
+#elif defined(CHIP10992)
+ . += 0x01FA4000;
+ DSP_TEMP_ROM_SPACE$$Base = .;
+ * (DSP_BIN_ZI)
+ . = DSP_TEMP_ROM_SPACE$$Base + 0xB00000;
+ DSP_TEMP_ROM_SPACE$$Limit = .;
+ DSP_TEMP_ROM_SPACE$$Length = ABSOLUTE(DSP_TEMP_ROM_SPACE$$Limit - DSP_TEMP_ROM_SPACE$$Base);
+#else
+ . += 0x01D40000;
+ DSP_TEMP_ROM_SPACE$$Base = .;
+ * (DSP_BIN_ZI)
+ . = DSP_TEMP_ROM_SPACE$$Base + 0xB00000;
+ DSP_TEMP_ROM_SPACE$$Limit = .;
+ DSP_TEMP_ROM_SPACE$$Length = ABSOLUTE(DSP_TEMP_ROM_SPACE$$Limit - DSP_TEMP_ROM_SPACE$$Base);
+#endif
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6297_FPGA.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6297_FPGA.txt
new file mode 100644
index 0000000..57c9459
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6297_FPGA.txt
@@ -0,0 +1,6 @@
+ . += 0x00A00000;
+ DSP_TEMP_ROM_SPACE$$Base = .;
+ * (DSP_BIN_ZI)
+ DSP_TEMP_ROM_SPACE$$Limit = .;
+ DSP_TEMP_ROM_SPACE$$Length = ABSOLUTE(DSP_TEMP_ROM_SPACE$$Limit - DSP_TEMP_ROM_SPACE$$Base);
+ . = DSP_TEMP_ROM_SPACE$$Base + 0x2B00000;
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6739.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6739.txt
new file mode 100755
index 0000000..fde7efc
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6739.txt
@@ -0,0 +1,6 @@
+ /* owner: Yuni */
+ DSP_TEMP_ROM_SPACE$$Base = .;
+ * (DSP_BIN_ZI)
+ DSP_TEMP_ROM_SPACE$$Limit = .;
+ DSP_TEMP_ROM_SPACE$$Length = ABSOLUTE(DSP_TEMP_ROM_SPACE$$Limit - DSP_TEMP_ROM_SPACE$$Base);
+ . = DSP_TEMP_ROM_SPACE$$Base + 0x0E00000; /* 14MB */
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6763.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6763.txt
new file mode 100755
index 0000000..def29cc
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6763.txt
@@ -0,0 +1,6 @@
+ /* owner: Yuni */
+ DSP_TEMP_ROM_SPACE$$Base = .;
+ * (DSP_BIN_ZI)
+ DSP_TEMP_ROM_SPACE$$Limit = .;
+ DSP_TEMP_ROM_SPACE$$Length = ABSOLUTE(DSP_TEMP_ROM_SPACE$$Limit - DSP_TEMP_ROM_SPACE$$Base);
+ . = DSP_TEMP_ROM_SPACE$$Base + 0x1000000; /* 16MB */
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6771.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6771.txt
new file mode 100755
index 0000000..def29cc
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_L1DSP_ZI/MT6771.txt
@@ -0,0 +1,6 @@
+ /* owner: Yuni */
+ DSP_TEMP_ROM_SPACE$$Base = .;
+ * (DSP_BIN_ZI)
+ DSP_TEMP_ROM_SPACE$$Limit = .;
+ DSP_TEMP_ROM_SPACE$$Length = ABSOLUTE(DSP_TEMP_ROM_SPACE$$Limit - DSP_TEMP_ROM_SPACE$$Base);
+ . = DSP_TEMP_ROM_SPACE$$Base + 0x1000000; /* 16MB */
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_MCURO_HWRW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_MCURO_HWRW/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_MCURO_HWRW/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_MCURO_HWRW_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_MCURO_HWRW_ZI/Common.txt
new file mode 100644
index 0000000..2bc5c69
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_MCURO_HWRW_ZI/Common.txt
@@ -0,0 +1 @@
+ * (MCURO_HWRW_NC_NOINIT)
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_MCURW_HWRW/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_MCURW_HWRW/Common.txt
new file mode 100644
index 0000000..1f026e4
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_MCURW_HWRW/Common.txt
@@ -0,0 +1 @@
+ * (MCURW_HWRW_NC_RW)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_MCURW_HWRW_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_MCURW_HWRW_ZI/Common.txt
new file mode 100644
index 0000000..4e7a100
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_MCURW_HWRW_ZI/Common.txt
@@ -0,0 +1 @@
+ * (MCURW_HWRW_NC_ZI)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_ULTRA_DATA/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_ULTRA_DATA/Common.txt
new file mode 100644
index 0000000..0fea38e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_ULTRA_DATA/Common.txt
@@ -0,0 +1,3 @@
+ . = ALIGN(64);
+ *(EXTSRAM_ULTRA_DATA_RO)
+ *(EXTSRAM_ULTRA_DATA_RW)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_ULTRA_DATA_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_ULTRA_DATA_ZI/Common.txt
new file mode 100644
index 0000000..7ac3b0d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_ULTRA_DATA_ZI/Common.txt
@@ -0,0 +1 @@
+ *(EXTSRAM_ULTRA_DATA_ZI)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_ZI/Common.txt
new file mode 100644
index 0000000..ac2045b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_ZI/Common.txt
@@ -0,0 +1,6 @@
+ * (NONCACHEDZI)
+
+ /********************** A. need to be confirmed in 93 **********************/
+ /********************** B. need to be moved to right section in 93 **********************/
+ /********************** C. will be removed in 93 **********************/
+ * (NONCACHEDZI_CORE2)
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_ZI/Head.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_ZI/Head.txt
new file mode 100644
index 0000000..3cee06f
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_ZI/Head.txt
@@ -0,0 +1,6 @@
+ . = ALIGN(4);
+ PHY_EXTSRAM_ZI$$Base = .;
+ * (PHY_EXTSRAM_ZI)
+ . = ALIGN(4);
+ PHY_EXTSRAM_ZI$$Limit = .;
+ PHY_EXTSRAM_ZI$$Length = ABSOLUTE(PHY_EXTSRAM_ZI$$Limit - PHY_EXTSRAM_ZI$$Base);
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_ZI_VOLTE_CORE3/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_ZI_VOLTE_CORE3/Common.txt
new file mode 100755
index 0000000..8b13789
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/EXTSRAM_ZI_VOLTE_CORE3/Common.txt
@@ -0,0 +1 @@
+
diff --git a/mcu/custom/system/Template/lds_config/InputSections/ISPRAM0/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/ISPRAM0/Common.txt
new file mode 100644
index 0000000..29267b9
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/ISPRAM0/Common.txt
@@ -0,0 +1,2 @@
+ * (ISPRAM_ROCODE_CORE0*)
+ . = ALIGN(8);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/ISPRAM0A/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/ISPRAM0A/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/ISPRAM0A/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/ISPRAM0B/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/ISPRAM0B/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/ISPRAM0B/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/ISPRAM0C/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/ISPRAM0C/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/ISPRAM0C/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/ISPRAM1/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/ISPRAM1/Common.txt
new file mode 100644
index 0000000..ec95858
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/ISPRAM1/Common.txt
@@ -0,0 +1,2 @@
+ * (ISPRAM_ROCODE_CORE1*)
+ . = ALIGN(8);
diff --git a/mcu/custom/system/Template/lds_config/InputSections/ISPRAM2/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/ISPRAM2/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/ISPRAM2/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2C_CODE/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2C_CODE/Common.txt
new file mode 100644
index 0000000..77dd22a
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2C_CODE/Common.txt
@@ -0,0 +1,3 @@
+ /* Image$$L2SRAM_L2C_CODE$$Base must align 0x1000 */
+ KEEP(* (L2SRAM_L2C_ROCODE_GUARD))
+ * (L2SRAM_L2C_ROCODE)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2C_DATA/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2C_DATA/Common.txt
new file mode 100644
index 0000000..ea21463
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2C_DATA/Common.txt
@@ -0,0 +1,2 @@
+ * (L2SRAM_L2C_RODATA)
+ * (L2SRAM_L2C_RW)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2C_DATA_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2C_DATA_ZI/Common.txt
new file mode 100644
index 0000000..eee6945
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2C_DATA_ZI/Common.txt
@@ -0,0 +1 @@
+ * (L2SRAM_L2C_ZI)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2NC_CODE/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2NC_CODE/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2NC_CODE/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2NC_DATA/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2NC_DATA/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2NC_DATA/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2NC_DATA_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2NC_DATA_ZI/Common.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/L2SRAM_L2NC_DATA_ZI/Common.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/ROM/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/ROM/Common.txt
new file mode 100644
index 0000000..3018cb6
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/ROM/Common.txt
@@ -0,0 +1,584 @@
+ TLBREFILL_EXCEPTION$$Base = . ;
+ KEEP(* (TLBREFILL_EXCEPTION))
+ TLBREFILL_EXCEPTION$$End = . ;
+
+ . = Image$$ROM$$Base + 0x100;
+ CACHEERR_EXCEPTION$$Base = . ;
+ KEEP(* (CACHEERR_EXCEPTION))
+ CACHEERR_EXCEPTION$$End = . ;
+
+ . = Image$$ROM$$Base + 0x180;
+ GENERAL_EXCEPTION$$Base = . ;
+ /*KEEP(* (VECTOR_ROUTINE))*/
+ KEEP(* (GENERAL_EXCEPTION))
+ GENERAL_EXCEPTION$$End = . ;
+
+ . = Image$$ROM$$Base + 0x200;
+ INTERRUPT_VECTOR$$Base = . ;
+ KEEP(* (INTERRUPT_VECTOR))
+ INTERRUPT_VECTOR$$End = . ;
+
+
+ /* FILL(0x7000003f); */ /* force fill sdbbp to reserve LMA space */ /* Do we need it ? */
+
+#if ((defined(__ESL_HRT__) || defined(__SPV_UFPS_LOAD__)) && (defined(__MD97__) || defined(__MD97P__)))
+ . = ALIGN(64);
+ ESL_TEST_RO$$Base = .;
+ *kal_hrt_api.obj* (.text*)
+ *esl_profile.obj* (.text*)
+ *cache.obj* (EXCLUDE_FILE (*simmngr_cache.obj* *cse_racache.obj* *l2cache.obj*).text*)
+ *atomic_operations.obj* (.text*)
+ *drv_csif_main.obj* (.text*)
+
+ . = ALIGN(64);
+#if defined(__CPUEVAL__)
+ *libcpueval.a* (.text*)
+ *libcpueval.a* (.rodata*)
+#endif
+
+#if defined(__ESL_BENCHMARK_COREMARK_L2CACHE_LOCK__)
+ *core_list_join.obj* (.text*)
+ *core_main.obj* (.text*)
+ *core_matrix.obj* (.text*)
+ *core_state.obj* (.text*)
+ *core_util.obj* (.text*)
+ *core_portme.obj* (.text*)
+#endif
+
+#if defined(__ESL_BENCHMARK_DHRYSTONE_L2CACHE_LOCK__)
+ *dhry_1.obj* (.text*)
+ *dhry_2.obj* (.text*)
+#endif
+
+ ESL_TEST_RO$$Limit = .;
+ ESL_TEST_RO$$Length = ABSOLUTE( ESL_TEST_RO$$Limit - ESL_TEST_RO$$Base);
+
+ . = ALIGN(64);
+ SECTION_L2CACHE_LOCK_ESL_ROCODE$$Base = .;
+ * (SECTION_L2CACHE_LOCK_ESL_ROCODE*)
+ . = ALIGN(64);
+ SECTION_L2CACHE_LOCK_ESL_ROCODE$$Limit = .;
+ SECTION_L2CACHE_LOCK_ESL_ROCODE$$Length = ABSOLUTE( SECTION_L2CACHE_LOCK_ESL_ROCODE$$Limit - SECTION_L2CACHE_LOCK_ESL_ROCODE$$Base);
+
+#endif
+
+ * (DRAM_EX_ROCODE) /*CODE_PROTECT*/
+ * (SNORCODE*)
+ * (SECOND_PART*)
+#if (defined( __MD97__) || defined(__MD97P__))
+ * (.text*)
+ L2CACHE_LOCK_ITC_ROCODE$$Base = .;
+ *kal_hw_itc.obj* (L2CACHE_LOCK_ROCODE)
+ L2CACHE_LOCK_ITC_ROCODE$$Limit = .;
+ * (L2CACHE_LOCK_ROCODE*)
+ * (L2CACHE_LOCK_RODATA)
+#elif defined( __MD95__)
+ * (.text*)
+#else
+ * (EXCLUDE_FILE (*lib_a-memcpy.o *lib_a-memset.o) .text*)
+#endif
+ * (EMIINITCODE)
+ * (i.*)
+ * (.ARM.extab)
+ * (CRYPTO_ASM)
+ KEEP(* (Keep_CODE))
+
+ /***** remap to EMI in 92 *****/
+ *libkal.a: (INTSRAM_ROCODE*)
+ * (INTSRAM_ROCODE*)
+ * (L2SRAM_ROCODE)
+ /***** remap to EMI in 92 *****/
+
+ ROM_RODATA$$Base = .; /* RODATA should be put in the end of ROM section. CGA will not parsing symbols after this linker symbol */
+ * (.rodata*)
+#if !defined(__AMMS_DRDI__)
+ /* DRDI 2G */
+ * (DRDIRODATA.2G.SET0.*)
+ * (DRDIRODATA.2G.SET1.*)
+ * (DRDIRODATA.2G.SET2.*)
+ * (DRDIRODATA.2G.SET3.*)
+ * (DRDIRODATA.2G.SET4.*)
+ * (DRDIRODATA.2G.SET5.*)
+ * (DRDIRODATA.2G.SET6.*)
+ * (DRDIRODATA.2G.SET7.*)
+ * (DRDIRODATA.2G.SET8.*)
+ * (DRDIRODATA.2G.SET9.*)
+ * (DRDIRODATA.2G.SET10.*)
+ * (DRDIRODATA.2G.SET11.*)
+ * (DRDIRODATA.2G.SET12.*)
+ * (DRDIRODATA.2G.SET13.*)
+ * (DRDIRODATA.2G.SET14.*)
+ * (DRDIRODATA.2G.SET15.*)
+ * (DRDIRODATA.2G.SET16.*)
+ * (DRDIRODATA.2G.SET17.*)
+ * (DRDIRODATA.2G.SET18.*)
+ * (DRDIRODATA.2G.SET19.*)
+ * (DRDIRODATA.2G.SET20.*)
+ * (DRDIRODATA.2G.SET21.*)
+ * (DRDIRODATA.2G.SET22.*)
+ * (DRDIRODATA.2G.SET23.*)
+ * (DRDIRODATA.2G.SET24.*)
+ * (DRDIRODATA.2G.SET25.*)
+ * (DRDIRODATA.2G.SET26.*)
+ * (DRDIRODATA.2G.SET27.*)
+ * (DRDIRODATA.2G.SET28.*)
+ * (DRDIRODATA.2G.SET29.*)
+ * (DRDIRODATA.2G.SET30.*)
+ * (DRDIRODATA.2G.SET31.*)
+ * (DRDIRODATA.2G.SET32.*)
+ * (DRDIRODATA.2G.SET33.*)
+ * (DRDIRODATA.2G.SET34.*)
+ * (DRDIRODATA.2G.SET35.*)
+ * (DRDIRODATA.2G.SET36.*)
+ * (DRDIRODATA.2G.SET37.*)
+ * (DRDIRODATA.2G.SET38.*)
+ * (DRDIRODATA.2G.SET39.*)
+ * (DRDIRODATA.2G.SET40.*)
+ * (DRDIRODATA.2G.SET41.*)
+ * (DRDIRODATA.2G.SET42.*)
+ * (DRDIRODATA.2G.SET43.*)
+ * (DRDIRODATA.2G.SET44.*)
+ * (DRDIRODATA.2G.SET45.*)
+ * (DRDIRODATA.2G.SET46.*)
+ * (DRDIRODATA.2G.SET47.*)
+ * (DRDIRODATA.2G.SET48.*)
+ * (DRDIRODATA.2G.SET49.*)
+ * (DRDIRODATA.2G.SET50.*)
+ * (DRDIRODATA.2G.SET51.*)
+ * (DRDIRODATA.2G.SET52.*)
+ * (DRDIRODATA.2G.SET53.*)
+ * (DRDIRODATA.2G.SET54.*)
+ * (DRDIRODATA.2G.SET55.*)
+ * (DRDIRODATA.2G.SET56.*)
+ * (DRDIRODATA.2G.SET57.*)
+ * (DRDIRODATA.2G.SET58.*)
+ * (DRDIRODATA.2G.SET59.*)
+ * (DRDIRODATA.2G.SET60.*)
+ * (DRDIRODATA.2G.SET61.*)
+ * (DRDIRODATA.2G.SET62.*)
+ * (DRDIRODATA.2G.SET63.*)
+ /* DRDI 3G FDD */
+ * (DRDIRODATA.3GFDD.SET0.*)
+ * (DRDIRODATA.3GFDD.SET1.*)
+ * (DRDIRODATA.3GFDD.SET2.*)
+ * (DRDIRODATA.3GFDD.SET3.*)
+ * (DRDIRODATA.3GFDD.SET4.*)
+ * (DRDIRODATA.3GFDD.SET5.*)
+ * (DRDIRODATA.3GFDD.SET6.*)
+ * (DRDIRODATA.3GFDD.SET7.*)
+ * (DRDIRODATA.3GFDD.SET8.*)
+ * (DRDIRODATA.3GFDD.SET9.*)
+ * (DRDIRODATA.3GFDD.SET10.*)
+ * (DRDIRODATA.3GFDD.SET11.*)
+ * (DRDIRODATA.3GFDD.SET12.*)
+ * (DRDIRODATA.3GFDD.SET13.*)
+ * (DRDIRODATA.3GFDD.SET14.*)
+ * (DRDIRODATA.3GFDD.SET15.*)
+ * (DRDIRODATA.3GFDD.SET16.*)
+ * (DRDIRODATA.3GFDD.SET17.*)
+ * (DRDIRODATA.3GFDD.SET18.*)
+ * (DRDIRODATA.3GFDD.SET19.*)
+ * (DRDIRODATA.3GFDD.SET20.*)
+ * (DRDIRODATA.3GFDD.SET21.*)
+ * (DRDIRODATA.3GFDD.SET22.*)
+ * (DRDIRODATA.3GFDD.SET23.*)
+ * (DRDIRODATA.3GFDD.SET24.*)
+ * (DRDIRODATA.3GFDD.SET25.*)
+ * (DRDIRODATA.3GFDD.SET26.*)
+ * (DRDIRODATA.3GFDD.SET27.*)
+ * (DRDIRODATA.3GFDD.SET28.*)
+ * (DRDIRODATA.3GFDD.SET29.*)
+ * (DRDIRODATA.3GFDD.SET30.*)
+ * (DRDIRODATA.3GFDD.SET31.*)
+ * (DRDIRODATA.3GFDD.SET32.*)
+ * (DRDIRODATA.3GFDD.SET33.*)
+ * (DRDIRODATA.3GFDD.SET34.*)
+ * (DRDIRODATA.3GFDD.SET35.*)
+ * (DRDIRODATA.3GFDD.SET36.*)
+ * (DRDIRODATA.3GFDD.SET37.*)
+ * (DRDIRODATA.3GFDD.SET38.*)
+ * (DRDIRODATA.3GFDD.SET39.*)
+ * (DRDIRODATA.3GFDD.SET40.*)
+ * (DRDIRODATA.3GFDD.SET41.*)
+ * (DRDIRODATA.3GFDD.SET42.*)
+ * (DRDIRODATA.3GFDD.SET43.*)
+ * (DRDIRODATA.3GFDD.SET44.*)
+ * (DRDIRODATA.3GFDD.SET45.*)
+ * (DRDIRODATA.3GFDD.SET46.*)
+ * (DRDIRODATA.3GFDD.SET47.*)
+ * (DRDIRODATA.3GFDD.SET48.*)
+ * (DRDIRODATA.3GFDD.SET49.*)
+ * (DRDIRODATA.3GFDD.SET50.*)
+ * (DRDIRODATA.3GFDD.SET51.*)
+ * (DRDIRODATA.3GFDD.SET52.*)
+ * (DRDIRODATA.3GFDD.SET53.*)
+ * (DRDIRODATA.3GFDD.SET54.*)
+ * (DRDIRODATA.3GFDD.SET55.*)
+ * (DRDIRODATA.3GFDD.SET56.*)
+ * (DRDIRODATA.3GFDD.SET57.*)
+ * (DRDIRODATA.3GFDD.SET58.*)
+ * (DRDIRODATA.3GFDD.SET59.*)
+ * (DRDIRODATA.3GFDD.SET60.*)
+ * (DRDIRODATA.3GFDD.SET61.*)
+ * (DRDIRODATA.3GFDD.SET62.*)
+ * (DRDIRODATA.3GFDD.SET63.*)
+ /* DRDI 3G TDD */
+ * (DRDIRODATA.3GTDD.SET0.*)
+ * (DRDIRODATA.3GTDD.SET1.*)
+ * (DRDIRODATA.3GTDD.SET2.*)
+ * (DRDIRODATA.3GTDD.SET3.*)
+ * (DRDIRODATA.3GTDD.SET4.*)
+ * (DRDIRODATA.3GTDD.SET5.*)
+ * (DRDIRODATA.3GTDD.SET6.*)
+ * (DRDIRODATA.3GTDD.SET7.*)
+ * (DRDIRODATA.3GTDD.SET8.*)
+ * (DRDIRODATA.3GTDD.SET9.*)
+ * (DRDIRODATA.3GTDD.SET10.*)
+ * (DRDIRODATA.3GTDD.SET11.*)
+ * (DRDIRODATA.3GTDD.SET12.*)
+ * (DRDIRODATA.3GTDD.SET13.*)
+ * (DRDIRODATA.3GTDD.SET14.*)
+ * (DRDIRODATA.3GTDD.SET15.*)
+ * (DRDIRODATA.3GTDD.SET16.*)
+ * (DRDIRODATA.3GTDD.SET17.*)
+ * (DRDIRODATA.3GTDD.SET18.*)
+ * (DRDIRODATA.3GTDD.SET19.*)
+ * (DRDIRODATA.3GTDD.SET20.*)
+ * (DRDIRODATA.3GTDD.SET21.*)
+ * (DRDIRODATA.3GTDD.SET22.*)
+ * (DRDIRODATA.3GTDD.SET23.*)
+ * (DRDIRODATA.3GTDD.SET24.*)
+ * (DRDIRODATA.3GTDD.SET25.*)
+ * (DRDIRODATA.3GTDD.SET26.*)
+ * (DRDIRODATA.3GTDD.SET27.*)
+ * (DRDIRODATA.3GTDD.SET28.*)
+ * (DRDIRODATA.3GTDD.SET29.*)
+ * (DRDIRODATA.3GTDD.SET30.*)
+ * (DRDIRODATA.3GTDD.SET31.*)
+ * (DRDIRODATA.3GTDD.SET32.*)
+ * (DRDIRODATA.3GTDD.SET33.*)
+ * (DRDIRODATA.3GTDD.SET34.*)
+ * (DRDIRODATA.3GTDD.SET35.*)
+ * (DRDIRODATA.3GTDD.SET36.*)
+ * (DRDIRODATA.3GTDD.SET37.*)
+ * (DRDIRODATA.3GTDD.SET38.*)
+ * (DRDIRODATA.3GTDD.SET39.*)
+ * (DRDIRODATA.3GTDD.SET40.*)
+ * (DRDIRODATA.3GTDD.SET41.*)
+ * (DRDIRODATA.3GTDD.SET42.*)
+ * (DRDIRODATA.3GTDD.SET43.*)
+ * (DRDIRODATA.3GTDD.SET44.*)
+ * (DRDIRODATA.3GTDD.SET45.*)
+ * (DRDIRODATA.3GTDD.SET46.*)
+ * (DRDIRODATA.3GTDD.SET47.*)
+ * (DRDIRODATA.3GTDD.SET48.*)
+ * (DRDIRODATA.3GTDD.SET49.*)
+ * (DRDIRODATA.3GTDD.SET50.*)
+ * (DRDIRODATA.3GTDD.SET51.*)
+ * (DRDIRODATA.3GTDD.SET52.*)
+ * (DRDIRODATA.3GTDD.SET53.*)
+ * (DRDIRODATA.3GTDD.SET54.*)
+ * (DRDIRODATA.3GTDD.SET55.*)
+ * (DRDIRODATA.3GTDD.SET56.*)
+ * (DRDIRODATA.3GTDD.SET57.*)
+ * (DRDIRODATA.3GTDD.SET58.*)
+ * (DRDIRODATA.3GTDD.SET59.*)
+ * (DRDIRODATA.3GTDD.SET60.*)
+ * (DRDIRODATA.3GTDD.SET61.*)
+ * (DRDIRODATA.3GTDD.SET62.*)
+ * (DRDIRODATA.3GTDD.SET63.*)
+ /* DRDI MMRF */
+ * (DRDIRODATA.MMRF.SET0.*)
+ * (DRDIRODATA.MMRF.SET1.*)
+ * (DRDIRODATA.MMRF.SET2.*)
+ * (DRDIRODATA.MMRF.SET3.*)
+ * (DRDIRODATA.MMRF.SET4.*)
+ * (DRDIRODATA.MMRF.SET5.*)
+ * (DRDIRODATA.MMRF.SET6.*)
+ * (DRDIRODATA.MMRF.SET7.*)
+ * (DRDIRODATA.MMRF.SET8.*)
+ * (DRDIRODATA.MMRF.SET9.*)
+ * (DRDIRODATA.MMRF.SET10.*)
+ * (DRDIRODATA.MMRF.SET11.*)
+ * (DRDIRODATA.MMRF.SET12.*)
+ * (DRDIRODATA.MMRF.SET13.*)
+ * (DRDIRODATA.MMRF.SET14.*)
+ * (DRDIRODATA.MMRF.SET15.*)
+ * (DRDIRODATA.MMRF.SET16.*)
+ * (DRDIRODATA.MMRF.SET17.*)
+ * (DRDIRODATA.MMRF.SET18.*)
+ * (DRDIRODATA.MMRF.SET19.*)
+ * (DRDIRODATA.MMRF.SET20.*)
+ * (DRDIRODATA.MMRF.SET21.*)
+ * (DRDIRODATA.MMRF.SET22.*)
+ * (DRDIRODATA.MMRF.SET23.*)
+ * (DRDIRODATA.MMRF.SET24.*)
+ * (DRDIRODATA.MMRF.SET25.*)
+ * (DRDIRODATA.MMRF.SET26.*)
+ * (DRDIRODATA.MMRF.SET27.*)
+ * (DRDIRODATA.MMRF.SET28.*)
+ * (DRDIRODATA.MMRF.SET29.*)
+ * (DRDIRODATA.MMRF.SET30.*)
+ * (DRDIRODATA.MMRF.SET31.*)
+ * (DRDIRODATA.MMRF.SET32.*)
+ * (DRDIRODATA.MMRF.SET33.*)
+ * (DRDIRODATA.MMRF.SET34.*)
+ * (DRDIRODATA.MMRF.SET35.*)
+ * (DRDIRODATA.MMRF.SET36.*)
+ * (DRDIRODATA.MMRF.SET37.*)
+ * (DRDIRODATA.MMRF.SET38.*)
+ * (DRDIRODATA.MMRF.SET39.*)
+ * (DRDIRODATA.MMRF.SET40.*)
+ * (DRDIRODATA.MMRF.SET41.*)
+ * (DRDIRODATA.MMRF.SET42.*)
+ * (DRDIRODATA.MMRF.SET43.*)
+ * (DRDIRODATA.MMRF.SET44.*)
+ * (DRDIRODATA.MMRF.SET45.*)
+ * (DRDIRODATA.MMRF.SET46.*)
+ * (DRDIRODATA.MMRF.SET47.*)
+ * (DRDIRODATA.MMRF.SET48.*)
+ * (DRDIRODATA.MMRF.SET49.*)
+ * (DRDIRODATA.MMRF.SET50.*)
+ * (DRDIRODATA.MMRF.SET51.*)
+ * (DRDIRODATA.MMRF.SET52.*)
+ * (DRDIRODATA.MMRF.SET53.*)
+ * (DRDIRODATA.MMRF.SET54.*)
+ * (DRDIRODATA.MMRF.SET55.*)
+ * (DRDIRODATA.MMRF.SET56.*)
+ * (DRDIRODATA.MMRF.SET57.*)
+ * (DRDIRODATA.MMRF.SET58.*)
+ * (DRDIRODATA.MMRF.SET59.*)
+ * (DRDIRODATA.MMRF.SET60.*)
+ * (DRDIRODATA.MMRF.SET61.*)
+ * (DRDIRODATA.MMRF.SET62.*)
+ * (DRDIRODATA.MMRF.SET63.*)
+ /* C2K */
+ * (DRDIRODATA.C2K.SET0.*)
+ * (DRDIRODATA.C2K.SET1.*)
+ * (DRDIRODATA.C2K.SET2.*)
+ * (DRDIRODATA.C2K.SET3.*)
+ * (DRDIRODATA.C2K.SET4.*)
+ * (DRDIRODATA.C2K.SET5.*)
+ * (DRDIRODATA.C2K.SET6.*)
+ * (DRDIRODATA.C2K.SET7.*)
+ * (DRDIRODATA.C2K.SET8.*)
+ * (DRDIRODATA.C2K.SET9.*)
+ * (DRDIRODATA.C2K.SET10.*)
+ * (DRDIRODATA.C2K.SET11.*)
+ * (DRDIRODATA.C2K.SET12.*)
+ * (DRDIRODATA.C2K.SET13.*)
+ * (DRDIRODATA.C2K.SET14.*)
+ * (DRDIRODATA.C2K.SET15.*)
+ * (DRDIRODATA.C2K.SET16.*)
+ * (DRDIRODATA.C2K.SET17.*)
+ * (DRDIRODATA.C2K.SET18.*)
+ * (DRDIRODATA.C2K.SET19.*)
+ * (DRDIRODATA.C2K.SET20.*)
+ * (DRDIRODATA.C2K.SET21.*)
+ * (DRDIRODATA.C2K.SET22.*)
+ * (DRDIRODATA.C2K.SET23.*)
+ * (DRDIRODATA.C2K.SET24.*)
+ * (DRDIRODATA.C2K.SET25.*)
+ * (DRDIRODATA.C2K.SET26.*)
+ * (DRDIRODATA.C2K.SET27.*)
+ * (DRDIRODATA.C2K.SET28.*)
+ * (DRDIRODATA.C2K.SET29.*)
+ * (DRDIRODATA.C2K.SET30.*)
+ * (DRDIRODATA.C2K.SET31.*)
+ * (DRDIRODATA.C2K.SET32.*)
+ * (DRDIRODATA.C2K.SET33.*)
+ * (DRDIRODATA.C2K.SET34.*)
+ * (DRDIRODATA.C2K.SET35.*)
+ * (DRDIRODATA.C2K.SET36.*)
+ * (DRDIRODATA.C2K.SET37.*)
+ * (DRDIRODATA.C2K.SET38.*)
+ * (DRDIRODATA.C2K.SET39.*)
+ * (DRDIRODATA.C2K.SET40.*)
+ * (DRDIRODATA.C2K.SET41.*)
+ * (DRDIRODATA.C2K.SET42.*)
+ * (DRDIRODATA.C2K.SET43.*)
+ * (DRDIRODATA.C2K.SET44.*)
+ * (DRDIRODATA.C2K.SET45.*)
+ * (DRDIRODATA.C2K.SET46.*)
+ * (DRDIRODATA.C2K.SET47.*)
+ * (DRDIRODATA.C2K.SET48.*)
+ * (DRDIRODATA.C2K.SET49.*)
+ * (DRDIRODATA.C2K.SET50.*)
+ * (DRDIRODATA.C2K.SET51.*)
+ * (DRDIRODATA.C2K.SET52.*)
+ * (DRDIRODATA.C2K.SET53.*)
+ * (DRDIRODATA.C2K.SET54.*)
+ * (DRDIRODATA.C2K.SET55.*)
+ * (DRDIRODATA.C2K.SET56.*)
+ * (DRDIRODATA.C2K.SET57.*)
+ * (DRDIRODATA.C2K.SET58.*)
+ * (DRDIRODATA.C2K.SET59.*)
+ * (DRDIRODATA.C2K.SET60.*)
+ * (DRDIRODATA.C2K.SET61.*)
+ * (DRDIRODATA.C2K.SET62.*)
+ * (DRDIRODATA.C2K.SET63.*)
+ /* LTE */
+ * (DRDIRODATA.LTE.SET0.*)
+ * (DRDIRODATA.LTE.SET1.*)
+ * (DRDIRODATA.LTE.SET2.*)
+ * (DRDIRODATA.LTE.SET3.*)
+ * (DRDIRODATA.LTE.SET4.*)
+ * (DRDIRODATA.LTE.SET5.*)
+ * (DRDIRODATA.LTE.SET6.*)
+ * (DRDIRODATA.LTE.SET7.*)
+ * (DRDIRODATA.LTE.SET8.*)
+ * (DRDIRODATA.LTE.SET9.*)
+ * (DRDIRODATA.LTE.SET10.*)
+ * (DRDIRODATA.LTE.SET11.*)
+ * (DRDIRODATA.LTE.SET12.*)
+ * (DRDIRODATA.LTE.SET13.*)
+ * (DRDIRODATA.LTE.SET14.*)
+ * (DRDIRODATA.LTE.SET15.*)
+ * (DRDIRODATA.LTE.SET16.*)
+ * (DRDIRODATA.LTE.SET17.*)
+ * (DRDIRODATA.LTE.SET18.*)
+ * (DRDIRODATA.LTE.SET19.*)
+ * (DRDIRODATA.LTE.SET20.*)
+ * (DRDIRODATA.LTE.SET21.*)
+ * (DRDIRODATA.LTE.SET22.*)
+ * (DRDIRODATA.LTE.SET23.*)
+ * (DRDIRODATA.LTE.SET24.*)
+ * (DRDIRODATA.LTE.SET25.*)
+ * (DRDIRODATA.LTE.SET26.*)
+ * (DRDIRODATA.LTE.SET27.*)
+ * (DRDIRODATA.LTE.SET28.*)
+ * (DRDIRODATA.LTE.SET29.*)
+ * (DRDIRODATA.LTE.SET30.*)
+ * (DRDIRODATA.LTE.SET31.*)
+ * (DRDIRODATA.LTE.SET32.*)
+ * (DRDIRODATA.LTE.SET33.*)
+ * (DRDIRODATA.LTE.SET34.*)
+ * (DRDIRODATA.LTE.SET35.*)
+ * (DRDIRODATA.LTE.SET36.*)
+ * (DRDIRODATA.LTE.SET37.*)
+ * (DRDIRODATA.LTE.SET38.*)
+ * (DRDIRODATA.LTE.SET39.*)
+ * (DRDIRODATA.LTE.SET40.*)
+ * (DRDIRODATA.LTE.SET41.*)
+ * (DRDIRODATA.LTE.SET42.*)
+ * (DRDIRODATA.LTE.SET43.*)
+ * (DRDIRODATA.LTE.SET44.*)
+ * (DRDIRODATA.LTE.SET45.*)
+ * (DRDIRODATA.LTE.SET46.*)
+ * (DRDIRODATA.LTE.SET47.*)
+ * (DRDIRODATA.LTE.SET48.*)
+ * (DRDIRODATA.LTE.SET49.*)
+ * (DRDIRODATA.LTE.SET50.*)
+ * (DRDIRODATA.LTE.SET51.*)
+ * (DRDIRODATA.LTE.SET52.*)
+ * (DRDIRODATA.LTE.SET53.*)
+ * (DRDIRODATA.LTE.SET54.*)
+ * (DRDIRODATA.LTE.SET55.*)
+ * (DRDIRODATA.LTE.SET56.*)
+ * (DRDIRODATA.LTE.SET57.*)
+ * (DRDIRODATA.LTE.SET58.*)
+ * (DRDIRODATA.LTE.SET59.*)
+ * (DRDIRODATA.LTE.SET60.*)
+ * (DRDIRODATA.LTE.SET61.*)
+ * (DRDIRODATA.LTE.SET62.*)
+ * (DRDIRODATA.LTE.SET63.*)
+ /* DRDI NR */
+ * (DRDIRODATA.NR.SET0.*)
+ * (DRDIRODATA.NR.SET1.*)
+ * (DRDIRODATA.NR.SET2.*)
+ * (DRDIRODATA.NR.SET3.*)
+ * (DRDIRODATA.NR.SET4.*)
+ * (DRDIRODATA.NR.SET5.*)
+ * (DRDIRODATA.NR.SET6.*)
+ * (DRDIRODATA.NR.SET7.*)
+ * (DRDIRODATA.NR.SET8.*)
+ * (DRDIRODATA.NR.SET9.*)
+ * (DRDIRODATA.NR.SET10.*)
+ * (DRDIRODATA.NR.SET11.*)
+ * (DRDIRODATA.NR.SET12.*)
+ * (DRDIRODATA.NR.SET13.*)
+ * (DRDIRODATA.NR.SET14.*)
+ * (DRDIRODATA.NR.SET15.*)
+ * (DRDIRODATA.NR.SET16.*)
+ * (DRDIRODATA.NR.SET17.*)
+ * (DRDIRODATA.NR.SET18.*)
+ * (DRDIRODATA.NR.SET19.*)
+ * (DRDIRODATA.NR.SET20.*)
+ * (DRDIRODATA.NR.SET21.*)
+ * (DRDIRODATA.NR.SET22.*)
+ * (DRDIRODATA.NR.SET23.*)
+ * (DRDIRODATA.NR.SET24.*)
+ * (DRDIRODATA.NR.SET25.*)
+ * (DRDIRODATA.NR.SET26.*)
+ * (DRDIRODATA.NR.SET27.*)
+ * (DRDIRODATA.NR.SET28.*)
+ * (DRDIRODATA.NR.SET29.*)
+ * (DRDIRODATA.NR.SET30.*)
+ * (DRDIRODATA.NR.SET31.*)
+ * (DRDIRODATA.NR.SET32.*)
+ * (DRDIRODATA.NR.SET33.*)
+ * (DRDIRODATA.NR.SET34.*)
+ * (DRDIRODATA.NR.SET35.*)
+ * (DRDIRODATA.NR.SET36.*)
+ * (DRDIRODATA.NR.SET37.*)
+ * (DRDIRODATA.NR.SET38.*)
+ * (DRDIRODATA.NR.SET39.*)
+ * (DRDIRODATA.NR.SET40.*)
+ * (DRDIRODATA.NR.SET41.*)
+ * (DRDIRODATA.NR.SET42.*)
+ * (DRDIRODATA.NR.SET43.*)
+ * (DRDIRODATA.NR.SET44.*)
+ * (DRDIRODATA.NR.SET45.*)
+ * (DRDIRODATA.NR.SET46.*)
+ * (DRDIRODATA.NR.SET47.*)
+ * (DRDIRODATA.NR.SET48.*)
+ * (DRDIRODATA.NR.SET49.*)
+ * (DRDIRODATA.NR.SET50.*)
+ * (DRDIRODATA.NR.SET51.*)
+ * (DRDIRODATA.NR.SET52.*)
+ * (DRDIRODATA.NR.SET53.*)
+ * (DRDIRODATA.NR.SET54.*)
+ * (DRDIRODATA.NR.SET55.*)
+ * (DRDIRODATA.NR.SET56.*)
+ * (DRDIRODATA.NR.SET57.*)
+ * (DRDIRODATA.NR.SET58.*)
+ * (DRDIRODATA.NR.SET59.*)
+ * (DRDIRODATA.NR.SET60.*)
+ * (DRDIRODATA.NR.SET61.*)
+ * (DRDIRODATA.NR.SET62.*)
+ * (DRDIRODATA.NR.SET63.*)
+#endif /* end of !defined(__AMMS_DRDI__) */
+ /***** remap to EMI in 92 *****/
+ * (EMIINITCONST)
+ * (INTERNBLOCK2_RO)
+ * (L2SRAM_RODATA)
+ /***** remap to EMI in 92 *****/
+ . = ALIGN(CACHELINESIZE); /* the end of RO should be 32 byte alignment */
+ ROM_RODATA$$Limit = .;
+ ROM_RODATA$$Length = ABSOLUTE(ROM_RODATA$$Limit - ROM_RODATA$$Base);
+
+
+ /********************** A. need to be confirmed in 93 **********************/
+ * (.MIPS.abiflags*)
+ * (.gnu.attributes)
+ * (.mdebug.abi32)
+ * (.pdr)
+ * (.reginfo)
+ * (.rel.dyn)
+ * (esal_code)
+
+ /********************** B. need to be moved to right section in 93 **********************/
+ /********************** C. will be removed in 93 **********************/
+#if !(defined( __MD97__) || defined(__MD97P__))
+ * (L2SRAM_L2C_ROCODE)
+ * (L2SRAM_L2C_RODATA)
+ * (L2SRAM_L2NC_ROCODE)
+ * (L2SRAM_L2NC_RODATA)
+ * (ISPRAM_ROCODE_CORE2*)
+ * (DSPRAM_RODATA_CORE2*)
+#endif
+
+ /********************** end **********************/
+#if defined(__RF_SCAN_FOR_DESENSE_TEST__)
+ * (BANK9_INPUTSECTION)
+#endif
diff --git a/mcu/custom/system/Template/lds_config/InputSections/ROM/Head.txt b/mcu/custom/system/Template/lds_config/InputSections/ROM/Head.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/ROM/Head.txt
diff --git a/mcu/custom/system/Template/lds_config/InputSections/ROM_GFH/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/ROM_GFH/Common.txt
new file mode 100644
index 0000000..17f0462
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/ROM_GFH/Common.txt
@@ -0,0 +1,6 @@
+ ROM_IV_REGION$$Base = . ;
+ KEEP(*(MAUI_IV_REGION))
+ ROM_IV_REGION$$Limit = . ;
+ ROM_IV_REGION$$Length = ABSOLUTE(ROM_IV_REGION$$Limit - ROM_IV_REGION$$Base);
+ KEEP(*(MAUI_GFH))
+ KEEP(*(MAUI_GFH_EXT))
diff --git a/mcu/custom/system/Template/lds_config/InputSections/ROM_SIGNATURE_SECTION/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/ROM_SIGNATURE_SECTION/Common.txt
new file mode 100644
index 0000000..438f9bb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/ROM_SIGNATURE_SECTION/Common.txt
@@ -0,0 +1 @@
+ KEEP(* (MAUI_SIGNATURE_SECTION))
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/SECURE_RO_ME/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/SECURE_RO_ME/Common.txt
new file mode 100755
index 0000000..693dd4f
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/SECURE_RO_ME/Common.txt
@@ -0,0 +1 @@
+ KEEP(* (SECURE_RO))
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/SECURE_RO_ME_GFH/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/SECURE_RO_ME_GFH/Common.txt
new file mode 100755
index 0000000..8690d28
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/SECURE_RO_ME_GFH/Common.txt
@@ -0,0 +1,2 @@
+ * (SECURE_RO_ME_GFH)
+ * (SECURE_RO_ME_GFH_EXT)
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/SECURE_RO_ME_SIGNATURE_SECTION/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/SECURE_RO_ME_SIGNATURE_SECTION/Common.txt
new file mode 100755
index 0000000..364a4fb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/SECURE_RO_ME_SIGNATURE_SECTION/Common.txt
@@ -0,0 +1 @@
+ * (SECURE_RO_ME_SIGNATURE_SECTION)
\ No newline at end of file
diff --git a/mcu/custom/system/Template/lds_config/InputSections/UROM/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/UROM/Common.txt
new file mode 100644
index 0000000..4861260
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/UROM/Common.txt
@@ -0,0 +1,7 @@
+ * (NONCACHED_ROCODE)
+ * (NONCACHED_RODATA)
+ . = ALIGN(0x1000);
+ BOOT_EX_VECTORS$$Base = . ;
+ KEEP(* (BOOT_EX_VECTORS))
+ BOOT_EX_VECTORS$$End = . ;
+ /*. = ALIGN(4);*/
diff --git a/mcu/custom/system/Template/lds_config/InputSections/USPRAM_CODE/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/USPRAM_CODE/Common.txt
new file mode 100644
index 0000000..afd8b8c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/USPRAM_CODE/Common.txt
@@ -0,0 +1 @@
+ * (USPRAM_ROCODE)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/USPRAM_DATA/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/USPRAM_DATA/Common.txt
new file mode 100644
index 0000000..be2f4e5
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/USPRAM_DATA/Common.txt
@@ -0,0 +1,2 @@
+ * (USSRAM_ROCODE)
+ * (USPRAM_DATA_RW*)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/USPRAM_DATA_ZI/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/USPRAM_DATA_ZI/Common.txt
new file mode 100644
index 0000000..264d8ae
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/USPRAM_DATA_ZI/Common.txt
@@ -0,0 +1 @@
+ * (USPRAM_DATA_ZI*)
diff --git a/mcu/custom/system/Template/lds_config/InputSections/bss/Common.txt b/mcu/custom/system/Template/lds_config/InputSections/bss/Common.txt
new file mode 100644
index 0000000..a497eef
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/InputSections/bss/Common.txt
@@ -0,0 +1,28 @@
+ * (.bss*)
+ * (.sbss*)
+ KEEP(* (Keep_ZI))
+ * (COMMON)
+ *(.scommon)
+#if defined(__MD97__) || defined(__MD97P__)
+ * (L2CACHE_LOCK_ZI)
+#endif
+ /***** remap to EMI in 92 *****/
+ * (INTSRAM_ZI*)
+ * (INTERNBLOCK2_ZI)
+ * (EMIINITZI)
+ * (L2SRAM_ZI)
+ /***** remap to EMI in 92 *****/
+
+
+ /********************** A. need to be confirmed in 93 **********************/
+ /********************** B. need to be moved to right section in 93 **********************/
+ /********************** C. will be removed in 93 **********************/
+ * (DYNAMIC_SECTION_L2SRAM_UBIN_W_ZI)
+ * (DYNAMIC_SECTION_L2SRAM_UBIN_T_ZI)
+ * (BSS_CORE2) /* base and end align to cache line size */
+#if !(defined(__MD97__) || defined(__MD97P__))
+ * (L2SRAM_L2C_ZI)
+ * (L2SRAM_L2NC_ZI)
+ * (DSPRAM_ZI_CORE2*)
+#endif
+ . = ALIGN(8);
diff --git a/mcu/custom/system/Template/lds_config/RegionConfig/Default.csv b/mcu/custom/system/Template/lds_config/RegionConfig/Default.csv
new file mode 100644
index 0000000..301f42b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/RegionConfig/Default.csv
@@ -0,0 +1,257 @@
+Type,Name,VMA,LMA,ALIGN,MaxSize,Attribute,BaseRegion,ExecutionView,LoadView,Condition,CompileOption
+ACTION,. = ORIGIN(UROM);,,,,,,,,,,
+ACTION,_zap1 = . ;,,,,,,,,,,
+ACTION,_ftext_ram = . ;,,,,,,,,,,
+ACTION, _edata_ram = . ;,,,,,,,,,,
+ACTION, _fbss = . ;,,,,,,,,,,
+ACTION, _end = . ;,,,,,,,,,,
+SectionFrame,ROM_GFH,.,,,,RO,,UROM,UROM,,
+SectionFrame,AUROM,.,,,,RO,,UROM,UROM,,
+SectionFrame,ISPRAM0A,ORIGIN(ISPRAM0A),,,,RO,,ISPRAM0A,UROM,,
+SectionFrame,ISPRAM0B,ORIGIN(ISPRAM0B),,,,RO,,ISPRAM0B,UROM,,
+SectionFrame,ISPRAM0C,ORIGIN(ISPRAM0C),,,,RO,,ISPRAM0C,UROM,,
+SectionFrame,ISPRAM0,ORIGIN(ISPRAM0),,,,RO,,ISPRAM0,UROM,,
+SectionFrame,DYNAMIC_SECTION_ISPRAM0_ADT_W2_CODE,.,,ALIGN(64),,RO,,ISPRAM0,UROM,,
+ACTION,. = Image$$DYNAMIC_SECTION_ISPRAM0_ADT_W2_CODE$$Base ;,,,,,,,,,,
+ACTION,. &= 0x0003FFFF;,,,,,,,,
+ACTION,. += ORIGIN(ISPRAM0A);,,,,,,,,,,
+SectionFrame,DYNAMIC_SECTION_ISPRAM0_ADT_L_CODE,.,,ALIGN(64),,RO,,ISPRAM0A,UROM,,
+ACTION,. = Image$$DYNAMIC_SECTION_ISPRAM0_ADT_W2_CODE$$Base ;,,,,,,,,,,
+ACTION,. &= 0x0003FFFF;,,,,,,,,
+ACTION,. += ORIGIN(ISPRAM0B);,,,,,,,,,,
+SectionFrame,DYNAMIC_SECTION_ISPRAM0_ADT_T_CODE,.,,ALIGN(64),,RO,,ISPRAM0B,UROM,,
+ACTION,. = Image$$DYNAMIC_SECTION_ISPRAM0_ADT_W2_CODE$$Base ;,,,,,,,,,,
+ACTION,. &= 0x0003FFFF;,,,,,,,,
+ACTION,. += ORIGIN(ISPRAM0C);,,,,,,,,,,
+SectionFrame,DYNAMIC_SECTION_ISPRAM0_ADT_W_CODE,.,,ALIGN(64),,RO,,ISPRAM0C,UROM,,
+ACTION,. = Image$$DYNAMIC_SECTION_ISPRAM0_ADT_W2_CODE$$Base ;,,,,,,,,,,
+ACTION,. &= 0x0003FFFF;,,,,,,,,
+ACTION, LinkerTemp1 = MAX(SIZEOF(DYNAMIC_SECTION_ISPRAM0_ADT_L_CODE),SIZEOF(DYNAMIC_SECTION_ISPRAM0_ADT_T_CODE));,,,,,,,,,,
+ACTION, LinkerTemp2 = MAX(SIZEOF(DYNAMIC_SECTION_ISPRAM0_ADT_W_CODE),SIZEOF(DYNAMIC_SECTION_ISPRAM0_ADT_W2_CODE));,,,,,,,,,,
+ACTION,. += ORIGIN(ISPRAM0B)+MAX(LinkerTemp1,LinkerTemp2);,,,,,,,,,,
+SectionFrame,DYNAMIC_SECTION_ISPRAM0_UBIN_T_CODE,.,,ALIGN(64),,RO,,ISPRAM0B,UROM,,
+ACTION,. = Image$$DYNAMIC_SECTION_ISPRAM0_UBIN_T_CODE$$Base ;,,,,,,,,,,
+ACTION,. &= 0x0003FFFF;,,,,,,,,
+ACTION,. += ORIGIN(ISPRAM0C);,,,,,,,,,,
+SectionFrame,DYNAMIC_SECTION_ISPRAM0_UBIN_W_CODE,.,,ALIGN(64),,RO,,ISPRAM0C,UROM,,
+SectionFrame,DSPRAM0,ORIGIN(DSPRAM0),,,,RW,DSPRAM0,DSPRAM0,UROM
+SectionFrame,DSPRAM0_ZI,.,,,,ZI,DSPRAM0,DSPRAM0,UROM
+SectionFrame,ISPRAM1,ORIGIN(ISPRAM1),,,,RO,,ISPRAM1,UROM
+SectionFrame,DSPRAM1,ORIGIN(DSPRAM1),,,,RW,DSPRAM1,DSPRAM1,UROM
+SectionFrame,DSPRAM1_ZI,.,,,,ZI,DSPRAM1,DSPRAM1,UROM
+LinkerSymbol,ISPRAM0_PHYSICAL_BOUNDARY,[ISPRAM0_BASE],,,,EV::Base,,,
+LinkerSymbol,ISPRAM0_PHYSICAL_BOUNDARY,[ISPRAM0_SIZE],,,,EV::Length,,,
+LinkerSymbol,ISPRAM0A_PHYSICAL_BOUNDARY,ORIGIN(ISPRAM0A),,,,EV::Base,,,
+LinkerSymbol,ISPRAM0A_PHYSICAL_BOUNDARY,[ISPRAM0_SIZE],,,,EV::Length,,,
+LinkerSymbol,ISPRAM0B_PHYSICAL_BOUNDARY,ORIGIN(ISPRAM0B),,,,EV::Base,,,
+LinkerSymbol,ISPRAM0B_PHYSICAL_BOUNDARY,[ISPRAM0_SIZE],,,,EV::Length,,,
+LinkerSymbol,ISPRAM0C_PHYSICAL_BOUNDARY,ORIGIN(ISPRAM0C),,,,EV::Base,,,
+LinkerSymbol,ISPRAM0C_PHYSICAL_BOUNDARY,[ISPRAM0_SIZE],,,,EV::Length,,,
+LinkerSymbol,DSPRAM0_PHYSICAL_BOUNDARY,[DSPRAM0_BASE],,,,EV::Base,,,
+LinkerSymbol,DSPRAM0_PHYSICAL_BOUNDARY,[DSPRAM0_SIZE],,,,EV::Length,,,
+LinkerSymbol,ISPRAM1_PHYSICAL_BOUNDARY,[ISPRAM1_BASE],,,,EV::Base,,,
+LinkerSymbol,ISPRAM1_PHYSICAL_BOUNDARY,[ISPRAM1_SIZE],,,,EV::Length,,,
+LinkerSymbol,DSPRAM1_PHYSICAL_BOUNDARY,[DSPRAM1_BASE],,,,EV::Base,,,
+LinkerSymbol,DSPRAM1_PHYSICAL_BOUNDARY,[DSPRAM1_SIZE],,,,EV::Length,,,
+ACTION,. = LOADADDR(DSPRAM1_ZI);,,,,,,,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(ROM); /* 0x00000000 */,,,,,,,,
+SectionFrame,ROM,.,,ALIGN(0x4000),,RO,,ROM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(UROM);,,,,,,,,
+SectionFrame,UROM,.,,ALIGN(32),,RO,,UROM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. = ORIGIN(MCURO_HWRW);,,,,,,,,,,
+LinkerSymbol,MCURO_HWRW,.,,,,EV::Base,,,,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(UROM);,,,,,,,,
+SectionFrame,EXTSRAM_MCURO_HWRW,.,,,,RW,EXTSRAM_MCURO_HWRW,MCURO_HWRW,UROM
+SectionFrame,EXTSRAM_MCURO_HWRW_ZI,.,,,,ZI,EXTSRAM_MCURO_HWRW,MCURO_HWRW,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW,MCURO_HWRW,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW,MCURO_HWRW,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURO_HWRW,.,,ALIGN(32),,RW,CACHED_EXTSRAM_MCURO_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURO_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_MCURO_HWRW,VRAM,UROM
+SectionFrame,EXTSRAM,ORIGIN(RAM),,,,RW,EXTSRAM,RAM,UROM
+SectionFrame,EXTSRAM_ZI,.,,,,ZI,EXTSRAM,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_RW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_RW,RAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_RW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_RW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM,.,,ALIGN(32),,RW,CACHED_EXTSRAM,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_ZI,.,,,,ZI,CACHED_EXTSRAM,VRAM,UROM
+SectionFrame,#.bss,.,,,,ZI,CACHED_EXTSRAM,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_NVRAM_LTABLE,.,,,,RW,,VRAM,UROM
+SectionFrame,EXTSRAM_MCURW_HWRW,ORIGIN(MCURW_HWRW),,,,RW,EXTSRAM_MCURW_HWRW,MCURW_HWRW,UROM
+SectionFrame,EXTSRAM_MCURW_HWRW_ZI,.,,,,ZI,EXTSRAM_MCURW_HWRW,MCURW_HWRW,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW,MCURW_HWRW,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW,MCURW_HWRW,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURW_HWRW,.,,ALIGN(32),,RW,CACHED_EXTSRAM_MCURW_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURW_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_MCURW_HWRW,VRAM,UROM
+SectionFrame,EXTSRAM_DSP_TX,ORIGIN(DSP_TXRX),,,[TX_SIZE],ZI,,DSP_TXRX,UROM,
+SectionFrame,EXTSRAM_DSP_RX,ORIGIN(DSP_TXRX)+[TX_SIZE],,ALIGN([RX_SIZE]),[RX_SIZE],ZI,,DSP_TXRX,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW,ORIGIN(IOCU2),,,,RW,CACHED_EXTSRAM_IOCU2_MCURW_HWRW,IOCU2,UROM
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_IOCU2_MCURW_HWRW,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_READ_ALLOC_MCURW_HWRW,ORIGIN(IOCU3),,,,RW,CACHED_EXTSRAM_IOCU3_READ_ALLOC_MCURW_HWRW,IOCU3,UROM
+SectionFrame,CACHED_EXTSRAM_IOCU3_READ_ALLOC_MCURW_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_IOCU3_READ_ALLOC_MCURW_HWRW,IOCU3,UROM,
+LinkerSymbol,L2CACHE_LOCK,ORIGIN(L2C_LOCK),,,,EV::Base,,,,,
+SectionFrame,CACHED_EXTSRAM_L2CACHE_LOCK_DATA,ORIGIN(L2C_LOCK),,ALIGN(0x8000),,RW,CACHED_EXTSRAM_L2CACHE_LOCK_DATA,L2C_LOCK,UROM
+SectionFrame,CACHED_EXTSRAM_L2CACHE_LOCK_DATA_ZI,.,,,,ZI,CACHED_EXTSRAM_L2CACHE_LOCK_DATA,L2C_LOCK,UROM
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_0,.,,,,RW,DYNAMIC_SECTION_L2CACHE_LOCK_0,L2C_LOCK,UROM
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_0_ZI,.,,,,ZI,DYNAMIC_SECTION_L2CACHE_LOCK_0,L2C_LOCK,UROM
+LinkerSymbol,L2CACHE_LOCK,.,,,,EV::ZILimit,,,,,
+LinkerSymbol,L2CACHE_LOCK,ABSOLUTE(Image$$L2CACHE_LOCK$$ZI$$Limit - Image$$L2CACHE_LOCK$$Base),,,,EV::Length,,,,,
+SectionFrame,EXTSRAM_CORE0,ORIGIN(CORE0),,,,RW,EXTSRAM_CORE0,CORE0,UROM
+SectionFrame,EXTSRAM_CORE0_ZI,.,,,,ZI,EXTSRAM_CORE0,CORE0,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_RW,CORE0,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_RW,CORE0,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_RW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_RW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_CORE0,.,,ALIGN(32),,RW,CACHED_EXTSRAM_CORE0,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_CORE0_ZI,.,,,,ZI,CACHED_EXTSRAM_CORE0,VRAM,UROM
+SectionFrame,EXTSRAM_CORE1,ORIGIN(CORE1),,,,RW,EXTSRAM_CORE1,CORE1,UROM
+SectionFrame,EXTSRAM_CORE1_ZI,.,,,,ZI,EXTSRAM_CORE1,CORE1,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_RW,CORE1,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_RW,CORE1,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_RW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_RW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_CORE1,.,,ALIGN(32),,RW,CACHED_EXTSRAM_CORE1,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_CORE1_ZI,.,,,,ZI,CACHED_EXTSRAM_CORE1,VRAM,UROM
+ACTION,. = LOADADDR(CACHED_EXTSRAM_CORE1_ZI);,,,,,,,,,,(__AMMS_DRDI__)
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,,,(__AMMS_DRDI__)
+ACTION,. += ORIGIN(SECURE_RO);,,,,,,,,,,(__AMMS_DRDI__)
+SectionFrame,ROM_SIGNATURE_SECTION,.,,,,RW,,SECURE_RO,UROM,,(__AMMS_DRDI__)
+ACTION,. = ORIGIN(DRDI);,,,,,,,,,,(__AMMS_DRDI__)
+LinkerSymbol,DRDI,.,,,,EV::Base,,,,,
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,ORIGIN(DRDI),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,DRDI,UROM,,(__AMMS_DRDI__)
+LinkerSymbol,DRDI,.,,,,EV::Limit,,,,,
+LinkerSymbol,DRDI,(Image$$DRDI$$Limit - Image$$DRDI$$Base),,,,EV::Length,,,,
+SectionFrame,EXTSRAM_FS_ZI,ORIGIN(EXTSRAM_FS),,,,ZI,,EXTSRAM_FS,UROM,
+SectionFrame,EXTSRAM_L1DSP_ZI,ORIGIN(L1DSP),,,,ZI,,L1DSP,UROM,
+ACTION,. = LOADADDR(EXTSRAM_L1DSP_ZI);,,,,,,,,,,!__AMMS_DRDI__
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,,,!__AMMS_DRDI__
+ACTION,. += ORIGIN(SECURE_RO);,,,,,,,,,,!__AMMS_DRDI__
+SectionFrame,ROM_SIGNATURE_SECTION,.,,,,RW,,SECURE_RO,UROM,,!__AMMS_DRDI__
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,,,
+LinkerSymbol,EXECUTION_VIEW_END,.,,,,EV::ZILimit,,,,
+ACTION,. = LOADADDR(EXTSRAM_L1DSP_ZI);,,,,,,,,,,__AMMS_DRDI__
+ACTION,. = LOADADDR(ROM_SIGNATURE_SECTION);,,,,,,,,,,!(__AMMS_DRDI__)
+LinkerSymbol,LOAD_VIEW_END,.,,,,EV::ZILimit,,,,
+LinkerSymbol,ISPRAM,LENGTH(ISPRAM0),,,,EV::Length,,,,
+LinkerSymbol,DSPRAM,LENGTH(DSPRAM0),,,,EV::Length,,,,
+LinkerSymbol,KTEST,ORIGIN(RAM)+LENGTH(RAM)-12,,,,EV::Base,,,,
+LinkerSymbol,DUMMY_END,[EXTSRAM_END],,,,EV::Base,,,,
+ACTION,"ASSERT( INTERRUPT_VECTOR$$Base >= GENERAL_EXCEPTION$$End, please reduce the size of input section GENERAL_EXCEPTION(VECTOR_ROUTINE))",,,,,,,,,
+ACTION,"ASSERT( (SDATA0$$ZI$$Limit - SDATA0$$ZI$$Base + SDATA0$$Limit - SDATA0$$Base) <= 0x10000, small data of core0 exceed 64 KB)",,,,,,,,,
+ACTION,"ASSERT( (SDATA1$$ZI$$Limit - SDATA1$$ZI$$Base + SDATA1$$Limit - SDATA1$$Base) <= 0x10000, small data of core1 exceed 64 KB)",,,,,,,,,
+ACTION,"ASSERT( L2CACHE_LOCK$$Length <= 0x8000, ""only 32 KB for L2CACHE_LOCK"")",,,,,,,,,
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_0$$Length <= 0x18000, ""only 96 KB for DYNAMIC_SECTION_L2CACHE_LOCK_3GW"")",,,,,,,,,
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_X$$Length <= 0x18000, ""only 96 KB for DYNAMIC_SECTION_L2CACHE_LOCK_3GW_IDLE"")",,,,,,,,,
diff --git a/mcu/custom/system/Template/lds_config/RegionConfig/MT6295M.csv b/mcu/custom/system/Template/lds_config/RegionConfig/MT6295M.csv
new file mode 100644
index 0000000..4cf077c
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/RegionConfig/MT6295M.csv
@@ -0,0 +1,252 @@
+Type,Name,VMA,LMA,ALIGN,MaxSize,Attribute,BaseRegion,ExecutionView,LoadView,Condition,CompileOption
+ACTION,. = ORIGIN(UROM);,,,,,,,,,,
+ACTION,_zap1 = . ;,,,,,,,,,,
+ACTION,_ftext_ram = . ;,,,,,,,,,,
+ACTION, _edata_ram = . ;,,,,,,,,,,
+ACTION, _fbss = . ;,,,,,,,,,,
+ACTION, _end = . ;,,,,,,,,,,
+SectionFrame,ROM_GFH,.,,,,RO,,UROM,UROM,,
+SectionFrame,AUROM,.,,,,RO,,UROM,UROM,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(ROM); /* 0x90000000 */,,,,,,,,
+SectionFrame,ROM,.,,ALIGN(0x4000),,RO,,ROM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(UROM);,,,,,,,,
+SectionFrame,UROM,.,,ALIGN(32),,RO,,UROM,UROM
+ACTION,. = ORIGIN(RAM);,,,,,,,,
+LinkerSymbol,MCURO_HWRW,.,,,,EV::Base,,,,
+SectionFrame,EXTSRAM_MCURO_HWRW,.,,,,RW,EXTSRAM_MCURO_HWRW,RAM,UROM
+SectionFrame,EXTSRAM_MCURO_HWRW_ZI,.,,,,ZI,EXTSRAM_MCURO_HWRW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW,RAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURO_HWRW,.,,ALIGN(32),,RW,CACHED_EXTSRAM_MCURO_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURO_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_MCURO_HWRW,VRAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+SectionFrame,EXTSRAM,ALIGN(0x1000000),,,,RW,EXTSRAM,RAM,UROM
+SectionFrame,EXTSRAM_ZI,.,,,,ZI,EXTSRAM,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_RW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_RW,RAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_RW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_RW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_WT,.,,ALIGN(32),,RW,CACHED_EXTSRAM_WT,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_WT_ZI,.,,,,ZI,CACHED_EXTSRAM_WT,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_NVRAM_LTABLE,.,,,,RW,,VRAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(IOCU2);,,,,,,,,
+SectionFrame,CACHED_EXTSRAM,.,,ALIGN(32),,RW,CACHED_EXTSRAM,IOCU2,UROM
+SectionFrame,CACHED_EXTSRAM_ZI,.,,,,ZI,CACHED_EXTSRAM,IOCU2,UROM
+SectionFrame,#.bss,.,,,,ZI,CACHED_EXTSRAM,IOCU2,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+SectionFrame,EXTSRAM_MCURW_HWRW,ALIGN(0x10000),,,,RW,EXTSRAM_MCURW_HWRW,RAM,UROM
+SectionFrame,EXTSRAM_MCURW_HWRW_ZI,.,,,,ZI,EXTSRAM_MCURW_HWRW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW,RAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURW_HWRW,.,,ALIGN(32),,RW,CACHED_EXTSRAM_MCURW_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURW_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_MCURW_HWRW,VRAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+SectionFrame,EXTSRAM_DSP_TX,ALIGN([TX_SIZE]),,,[TX_SIZE],ZI,,RAM,UROM
+SectionFrame,EXTSRAM_DSP_RX,ADDR(EXTSRAM_DSP_TX) + [TX_SIZE],,ALIGN([RX_SIZE]),[RX_SIZE],ZI,,RAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(IOCU2);,,,,,,,,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW,ALIGN(0x10000),,,,RW,CACHED_EXTSRAM_IOCU2_MCURW_HWRW,IOCU2,UROM
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_IOCU2_MCURW_HWRW,IOCU2,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(IOCU3);,,,,,,,,
+SectionFrame,CACHED_EXTSRAM_IOCU3_READ_ALLOC_MCURW_HWRW,ALIGN(0x100000),,,,RW,CACHED_EXTSRAM_IOCU3_READ_ALLOC_MCURW_HWRW,IOCU3,UROM
+SectionFrame,CACHED_EXTSRAM_IOCU3_READ_ALLOC_MCURW_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_IOCU3_READ_ALLOC_MCURW_HWRW,IOCU3,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,. = ALIGN(0x100000);,,,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,. += ORIGIN(ROM);,,,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+LinkerSymbol,L2CACHE_LOCK,.,,,,EV::Base,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_L_IDLE,.,,ALIGN(0x20000),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_W_COMMON,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_W_PAGING,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_T_IDLE,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_C_RTT_IDLE,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_C_DO_IDLE,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_MML1_IDLE,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_SS_IDLE,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,. = Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_IDLE$$Base + 0x20000;,,,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_L_CONN0,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_L_CONN1,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,. = Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_CONN1$$Base + 0x20000;,,,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_L_CONN2,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,. = Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_CONN0$$Base + 0x40000;,,,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_W_CONN0,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_W_CONN1,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,. = Image$$DYNAMIC_SECTION_L2CACHE_LOCK_W_CONN1$$Base + 0x20000;,,,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_W_CONN2,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,. = Image$$DYNAMIC_SECTION_L2CACHE_LOCK_W_CONN0$$Base + 0x40000;,,,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_T_CONN0,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_T_CONN1,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,. = Image$$DYNAMIC_SECTION_L2CACHE_LOCK_T_CONN1$$Base + 0x20000;,,,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_T_CONN2,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,. = Image$$DYNAMIC_SECTION_L2CACHE_LOCK_T_CONN0$$Base + 0x40000;,,,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_C_RTT_TALKING,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,. = Image$$DYNAMIC_SECTION_L2CACHE_LOCK_C_RTT_TALKING$$Base + 0x20000;,,,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_C_DO_DATALINK,.,,ALIGN(0x40),,RW,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+LinkerSymbol,L2CACHE_LOCK,.,,,,EV::ZILimit,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+LinkerSymbol,L2CACHE_LOCK,ABSOLUTE(Image$$L2CACHE_LOCK$$ZI$$Limit - Image$$L2CACHE_LOCK$$Base),,,,EV::Length,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+SectionFrame,EXTSRAM_CORE0,ALIGN(0x100000),,,,RW,EXTSRAM_CORE0,RAM,UROM
+SectionFrame,EXTSRAM_CORE0_ZI,.,,,,ZI,EXTSRAM_CORE0,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_RW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE0_RW,RAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_RW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE0_RW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_CORE0,.,,ALIGN(32),,RW,CACHED_EXTSRAM_CORE0,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_CORE0_ZI,.,,,,ZI,CACHED_EXTSRAM_CORE0,VRAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+SectionFrame,EXTSRAM_CORE1,ALIGN(0x100000),,,,RW,EXTSRAM_CORE1,RAM,UROM
+SectionFrame,EXTSRAM_CORE1_ZI,.,,,,ZI,EXTSRAM_CORE1,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_RW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CORE1_RW,RAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_RW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_CORE1_RW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_CORE1,.,,ALIGN(32),,RW,CACHED_EXTSRAM_CORE1,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_CORE1_ZI,.,,,,ZI,CACHED_EXTSRAM_CORE1,VRAM,UROM
+ACTION,. = LOADADDR(CACHED_EXTSRAM_CORE1_ZI);,,,,,,,,,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,,,
+ACTION,. += ORIGIN(SECURE_RO);,,,,,,,,,,
+SectionFrame,ROM_SIGNATURE_SECTION,.,,,,RW,,SECURE_RO,UROM,,
+ACTION,. = Image$$CACHED_EXTSRAM_CORE1$$ZI$$Limit;,,,,,,,,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,,,(__AMMS_DRDI__)
+ACTION,. = ALIGN(0x200000);,,,,,,,,,,(__AMMS_DRDI__)
+ACTION,. += ORIGIN(VRAM);,,,,,,,,,,(__AMMS_DRDI__)
+LinkerSymbol,DRDI,.,,,,EV::Base,,,,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+LinkerSymbol,DRDI,.,,,,EV::Limit,,,,,(__AMMS_DRDI__)
+LinkerSymbol,DRDI,(Image$$DRDI$$Limit - Image$$DRDI$$Base),,,,EV::Length,,,,,(__AMMS_DRDI__)
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,,
+LinkerSymbol,EXECUTION_VIEW_END,.,,,,EV::ZILimit,,,,
+SectionFrame,EXTSRAM_FS_ZI,ORIGIN(EXTSRAM_FS),,,,ZI,,EXTSRAM_FS,UROM,FS_RAMDISK=TRUE
+SectionFrame,EXTSRAM_L1DSP_ZI,ORIGIN(L1DSP),,,,ZI,,L1DSP,UROM,
+ACTION,. = LOADADDR(EXTSRAM_L1DSP_ZI);,,,,,,,,,
+LinkerSymbol,LOAD_VIEW_END,.,,,,EV::ZILimit,,,,
+LinkerSymbol,KTEST,ADDR(EXTSRAM_MCURW_HWRW)-12,,,,EV::Base,,,,
+LinkerSymbol,DUMMY_END,[EXTSRAM_END],,,,EV::Base,,,,
+ACTION,"ASSERT( Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_CONN0$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_IDLE$$Base + 0x40000), L_CONN0 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_CONN1$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_IDLE$$Base + 0x40000), L_CONN1 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_CONN2$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_IDLE$$Base + 0x60000), L_CONN2 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( Image$$DYNAMIC_SECTION_L2CACHE_LOCK_W_CONN0$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_IDLE$$Base + 0x80000), W_CONN0 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( Image$$DYNAMIC_SECTION_L2CACHE_LOCK_W_CONN1$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_IDLE$$Base + 0x80000), W_CONN1 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( Image$$DYNAMIC_SECTION_L2CACHE_LOCK_W_CONN2$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_IDLE$$Base + 0xA0000), W_CONN2 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( Image$$DYNAMIC_SECTION_L2CACHE_LOCK_T_CONN0$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_IDLE$$Base + 0xC0000), T_CONN0 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( Image$$DYNAMIC_SECTION_L2CACHE_LOCK_T_CONN1$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_IDLE$$Base + 0xC0000), T_CONN1 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( Image$$DYNAMIC_SECTION_L2CACHE_LOCK_T_CONN2$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_IDLE$$Base + 0xE0000), T_CONN2 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( Image$$DYNAMIC_SECTION_L2CACHE_LOCK_C_RTT_TALKING$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_IDLE$$Base + 0x100000), C_RTT_TALKING end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( Image$$DYNAMIC_SECTION_L2CACHE_LOCK_C_DO_DATALINK$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_L_IDLE$$Base + 0x120000), C_DO_DATALIK end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( INTERRUPT_VECTOR$$Base >= GENERAL_EXCEPTION$$End, please reduce the size of input section GENERAL_EXCEPTION(VECTOR_ROUTINE))",,,,,,,,,
+ACTION,"ASSERT( (SDATA0$$ZI$$Limit - SDATA0$$ZI$$Base + SDATA0$$Limit - SDATA0$$Base) <= 0x10000, small data of core0 exceed 64 KB)",,,,,,,,,
+ACTION,"ASSERT( (SDATA1$$ZI$$Limit - SDATA1$$ZI$$Base + SDATA1$$Limit - SDATA1$$Base) <= 0x10000, small data of core1 exceed 64 KB)",,,,,,,,,
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_0$$Length <= 0x18000, ""only 96 KB for DYNAMIC_SECTION_L2CACHE_LOCK_0"")",,,,,,,,,
+ACTION,"ASSERT( (Image$$EXECUTION_VIEW_END$$ZI$$Limit& 0x0fffffff) <= 0x0C800000, ""only 200 MB for general MCU memory (no ramdisk & DSP space)"")",,,,,,,,
diff --git a/mcu/custom/system/Template/lds_config/RegionConfig/MT6297.csv b/mcu/custom/system/Template/lds_config/RegionConfig/MT6297.csv
new file mode 100644
index 0000000..230e6fb
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/RegionConfig/MT6297.csv
@@ -0,0 +1,619 @@
+Type,Name,VMA,LMA,ALIGN,MaxSize,Attribute,BaseRegion,ExecutionView,LoadView,Condition,CompileOption
+ACTION,. = ORIGIN(UROM);,,,,,,,,,,
+ACTION,_zap1 = . ;,,,,,,,,,,
+ACTION,_ftext_ram = . ;,,,,,,,,,,
+ACTION, _edata_ram = . ;,,,,,,,,,,
+ACTION, _fbss = . ;,,,,,,,,,,
+ACTION, _end = . ;,,,,,,,,,,
+SectionFrame,ROM_GFH,.,,,,RO,,UROM,UROM,,
+SectionFrame,AUROM,.,,,,RO,,UROM,UROM,,
+SectionFrame,L2SRAM_L2C_CODE,ORIGIN(L2SRAM),,,,RO,,L2SRAM,UROM
+SectionFrame,L2SRAM_L2C_DATA,.,,,,RW,L2SRAM_L2C_DATA,L2SRAM,UROM
+SectionFrame,L2SRAM_L2C_DATA_ZI,.,,,,ZI,L2SRAM_L2C_DATA,L2SRAM,UROM
+ACTION,. = LOADADDR(L2SRAM_L2C_DATA_ZI);,,,,,,,,,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(ROM); /* 0x90000000 */,,,,,,,,
+SectionFrame,ROM,.,,ALIGN(0x4000),,RO,,ROM,UROM
+SectionFrame,CACHED_EXTSRAM_ULTRA_CODE,.,,ALIGN(64),,RO,,ROM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(UROM);,,,,,,,,
+SectionFrame,UROM,.,,ALIGN(64),,RO,,UROM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(ROM);,,,,,,,,
+SectionFrame,CACHED_EXTSRAM_L2CACHE_LOCK_RO,.,,ALIGN(0x10000),,RO,,ROM,UROM
+ACTION,. = ORIGIN(RAM);,,,,,,,,
+LinkerSymbol,MCURO_HWRW,.,,,,EV::Base,,,,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+SectionFrame,EXTSRAM_MCURO_HWRW,.,,,,RW,EXTSRAM_MCURO_HWRW,RAM,UROM
+SectionFrame,EXTSRAM_MCURO_HWRW_ZI,.,,,,ZI,EXTSRAM_MCURO_HWRW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW,RAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURO_HWRW,.,,ALIGN(32),,RW,CACHED_EXTSRAM_MCURO_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURO_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_MCURO_HWRW,VRAM,UROM
+ACTION,. = ALIGN(0x100000);,,,,,,,,,,(MT6297)
+ACTION,. = ALIGN(0x1000000);,,,,,,,,,,(!MT6297 && !CHIP10992)
+ACTION,. = ALIGN(0x800000);,,,,,,,,,,(CHIP10992)
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+SectionFrame,EXTSRAM,.,,,,RW,EXTSRAM,RAM,UROM
+SectionFrame,EXTSRAM_ZI,.,,,,ZI,EXTSRAM,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_RW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_RW,RAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_RW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_RW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_WT,.,,ALIGN(32),,RW,CACHED_EXTSRAM_WT,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_WT_ZI,.,,,,ZI,CACHED_EXTSRAM_WT,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_NVRAM_LTABLE,.,,,,RW,,VRAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(IOCU2);,,,,,,,,
+SectionFrame,CACHED_EXTSRAM,.,,ALIGN(32),,RW,CACHED_EXTSRAM,IOCU2,UROM
+SectionFrame,CACHED_EXTSRAM_ZI,.,,,,ZI,CACHED_EXTSRAM,IOCU2,UROM
+SectionFrame,bss,.,,,,ZI,CACHED_EXTSRAM,IOCU2,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. = ALIGN(0x10000);,,,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW,RAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. = ALIGN(0x10000);,,,,,,,,,,
+ACTION,. += ORIGIN(IOCU2);,,,,,,,,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW,.,,,,RW,CACHED_EXTSRAM_IOCU2_MCURW_HWRW,IOCU2,UROM
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_IOCU2_MCURW_HWRW,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_00,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_01,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_02,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_03,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_04,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_05,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_06,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_07,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_08,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_09,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_10,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_11,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_12,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_13,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_14,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI_15,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+ACTION,. = ALIGN(0x100000);,,,,,,,,,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+LinkerSymbol,ULTRA_DATA,.,,,,EV::Base,,,,,
+SectionFrame,EXTSRAM_ULTRA_DATA,.,,,,RW,EXTSRAM_ULTRA_DATA,RAM,UROM
+SectionFrame,EXTSRAM_ULTRA_DATA_ZI,.,,,,ZI,EXTSRAM_ULTRA_DATA,RAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(IOCU2);,,,,,,,,
+SectionFrame,CACHED_EXTSRAM_IOCU2_ULTRA_DATA,.,,,,RW,CACHED_EXTSRAM_IOCU2_ULTRA_DATA,IOCU2,UROM
+SectionFrame,CACHED_EXTSRAM_IOCU2_ULTRA_DATA_ZI,.,,,,ZI,CACHED_EXTSRAM_IOCU2_ULTRA_DATA,IOCU2,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,CACHED_EXTSRAM_ULTRA_DATA,.,,,,RW,CACHED_EXTSRAM_ULTRA_DATA,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_ULTRA_DATA_ZI,.,,,,ZI,CACHED_EXTSRAM_ULTRA_DATA,VRAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(IOCU3);,,,,,,,,
+SectionFrame,CACHED_EXTSRAM_IOCU3_ULTRA_DATA,.,,,,RW,CACHED_EXTSRAM_IOCU3_ULTRA_DATA,IOCU3,UROM
+SectionFrame,CACHED_EXTSRAM_IOCU3_ULTRA_DATA_ZI,.,,,,ZI,CACHED_EXTSRAM_IOCU3_ULTRA_DATA,IOCU3,UROM
+LinkerSymbol,ULTRA_DATA,.,,,,EV::ZILimit,,,,,
+ACTION,. = ALIGN(0x10000);,,,,,,,,,,
+SectionFrame,CACHED_EXTSRAM_IOCU3_READ_WRITE_ALLOC_MCURW_HWRW,.,,,,RW,CACHED_EXTSRAM_IOCU3_READ_WRITE_ALLOC_MCURW_HWRW,IOCU3,UROM
+SectionFrame,CACHED_EXTSRAM_IOCU3_READ_WRITE_ALLOC_MCURW_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_IOCU3_READ_WRITE_ALLOC_MCURW_HWRW,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_00,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_01,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_02,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_03,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_04,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_05,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_06,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_07,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_08,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_09,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_10,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_11,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_12,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_13,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_14,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_15,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+ACTION,. = ALIGN(0x10000);,,,,,,,,,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. = ALIGN([TX_SIZE]);,,,,,,,,,,
+SectionFrame,EXTSRAM_DSP_TX_ZI,.,,,[TX_SIZE],ZI,,RAM,UROM,
+ACTION,. = ALIGN([TX_SIZE]);,,,,,,,,,,
+SectionFrame,EXTSRAM_DSP_RX_ZI,.,,ALIGN([RX_SIZE]),[RX_SIZE],ZI,,RAM,UROM,
+ACTION,. = 0x10000000;,,,,,,,,,,(MT6297)
+SectionFrame,EXTSRAM_MCURW_HWRW,.,,,,RW,EXTSRAM_MCURW_HWRW,RAM,UROM,,(MT6297)
+SectionFrame,EXTSRAM_MCURW_HWRW,ALIGN(0x10000),,,,RW,EXTSRAM_MCURW_HWRW,RAM,UROM,,(!MT6297)
+SectionFrame,EXTSRAM_MCURW_HWRW_ZI,.,,,,ZI,EXTSRAM_MCURW_HWRW,RAM,UROM
+ACTION,. &= 0x1FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURW_HWRW,.,,ALIGN(32),,RW,CACHED_EXTSRAM_MCURW_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURW_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_MCURW_HWRW,VRAM,UROM
+ACTION,. = LOADADDR(CACHED_EXTSRAM_MCURW_HWRW_ZI);,,,,,,,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(SECURE_RO);,,,,,,,,
+SectionFrame,ROM_SIGNATURE_SECTION,.,,,,RW,,SECURE_RO,UROM,
+ACTION,. = Image$$CACHED_EXTSRAM_MCURW_HWRW$$ZI$$Limit;,,,,,,,,,
+ACTION,. &= 0x1FFFFFFF;,,,,,,,,,,(__AMMS_DRDI__)
+ACTION,. += ORIGIN(VRAM);,,,,,,,,,,(__AMMS_DRDI__)
+ACTION,. = ALIGN(0x10000);,,,,,,,,,,(__AMMS_DRDI__)
+LinkerSymbol,DRDI,.,,,,EV::Base,,,,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_16,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_17,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_18,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_19,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_20,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_21,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_22,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_23,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_24,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_25,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_26,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_27,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_28,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_29,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_30,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_31,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_32,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_33,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_34,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_35,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_36,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_37,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_38,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_39,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_40,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_41,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_42,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_43,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_44,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_45,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_46,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_47,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_48,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_49,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_50,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_51,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_52,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_53,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_54,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_55,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_56,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_57,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_58,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_59,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_60,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_61,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_62,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_63,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_16,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_17,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_18,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_19,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_20,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_21,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_22,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_23,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_24,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_25,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_26,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_27,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_28,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_29,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_30,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_31,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_32,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_33,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_34,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_35,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_36,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_37,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_38,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_39,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_40,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_41,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_42,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_43,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_44,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_45,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_46,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_47,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_48,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_49,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_50,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_51,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_52,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_53,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_54,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_55,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_56,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_57,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_58,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_59,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_60,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_61,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_62,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_63,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_16,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_17,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_18,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_19,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_20,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_21,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_22,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_23,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_24,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_25,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_26,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_27,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_28,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_29,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_30,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_31,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_32,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_33,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_34,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_35,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_36,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_37,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_38,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_39,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_40,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_41,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_42,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_43,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_44,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_45,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_46,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_47,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_48,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_49,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_50,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_51,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_52,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_53,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_54,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_55,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_56,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_57,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_58,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_59,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_60,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_61,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_62,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_63,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_16,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_17,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_18,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_19,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_20,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_21,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_22,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_23,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_24,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_25,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_26,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_27,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_28,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_29,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_30,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_31,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_32,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_33,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_34,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_35,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_36,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_37,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_38,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_39,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_40,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_41,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_42,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_43,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_44,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_45,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_46,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_47,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_48,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_49,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_50,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_51,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_52,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_53,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_54,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_55,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_56,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_57,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_58,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_59,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_60,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_61,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_62,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_63,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_16,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_17,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_18,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_19,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_20,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_21,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_22,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_23,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_24,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_25,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_26,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_27,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_28,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_29,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_30,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_31,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_32,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_33,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_34,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_35,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_36,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_37,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_38,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_39,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_40,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_41,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_42,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_43,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_44,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_45,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_46,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_47,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_48,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_49,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_50,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_51,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_52,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_53,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_54,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_55,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_56,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_57,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_58,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_59,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_60,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_61,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_62,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_63,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_16,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_17,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_18,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_19,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_20,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_21,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_22,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_23,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_24,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_25,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_26,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_27,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_28,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_29,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_30,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_31,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_32,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_33,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_34,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_35,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_36,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_37,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_38,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_39,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_40,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_41,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_42,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_43,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_44,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_45,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_46,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_47,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_48,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_49,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_50,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_51,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_52,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_53,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_54,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_55,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_56,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_57,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_58,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_59,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_60,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_61,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_62,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_63,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_16,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_17,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_18,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_19,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_20,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_21,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_22,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_23,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_24,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_25,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_26,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_27,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_28,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_29,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_30,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_31,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_32,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_33,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_34,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_35,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_36,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_37,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_38,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_39,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_40,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_41,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_42,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_43,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_44,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_45,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_46,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_47,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_48,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_49,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_50,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_51,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_52,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_53,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_54,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_55,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_56,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_57,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_58,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_59,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_60,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_61,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_62,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_63,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_NR_00,VRAM,UROM,,(__AMMS_DRDI__)
+LinkerSymbol,DRDI,.,,,,EV::Limit,,,,,(__AMMS_DRDI__)
+LinkerSymbol,DRDI,(Image$$DRDI$$Limit - Image$$DRDI$$Base),,,,EV::Length,,,,,(__AMMS_DRDI__)
+ACTION,. &= 0x1FFFFFFF;,,,,,,,,
+LinkerSymbol,EXECUTION_VIEW_END,.,,,,EV::ZILimit,,,,
+LinkerSymbol,SIB_AREA,.,,,,EV::Base,,,,,
+SectionFrame,EXTSRAM_FS_ZI,ORIGIN(EXTSRAM_FS),,,,ZI,,EXTSRAM_FS,UROM,FS_RAMDISK=TRUE
+ACTION,. = ORIGIN(L1DSP);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_CSIF_ZI,.,,,,ZI,,L1DSP,UROM,,((MT6885 || MT6873) && !MT6893)
+ACTION,. = ORIGIN(L1DSP) + 0x680000;,,,,,,,,,,((MT6885 || MT6873) && !MT6893)
+SectionFrame,EXTSRAM_L1DSP_ZI,.,,,,ZI,,L1DSP,UROM,
+LinkerSymbol,SIB_AREA,ORIGIN(EXTSRAM_FS),,,,EV::ZILimit,,,,
+LinkerSymbol,SIB_AREA,ABSOLUTE(Image$$SIB_AREA$$ZI$$Limit - Image$$SIB_AREA$$Base),,,,EV::Length,,,,,
+LinkerSymbol,KTEST,ORIGIN(RAM)+LENGTH(RAM)-12,,,,EV::Base,,,,
+LinkerSymbol,DUMMY_END,[EXTSRAM_END],,,,EV::Base,,,,
+ACTION,"ASSERT( (ESL_TEST_RO$$Length + ESL_TEST_RW$$Length + ESL_TEST_ZI$$Length + SECTION_L2CACHE_LOCK_ESL_ROCODE$$Length + SECTION_L2CACHE_LOCK_ESL_RWDATA$$Length + SECTION_L2CACHE_LOCK_ESL_ZI$$Length) < 0x100000, ESL lock size should be smaller than 1MB)",,,,,,,,,((__ESL_HRT__ || __SPV_UFPS_LOAD__) && (__MD97__ || __MD97P__))
+ACTION,"ASSERT( INTERRUPT_VECTOR$$Base >= GENERAL_EXCEPTION$$End, please reduce the size of input section GENERAL_EXCEPTION(VECTOR_ROUTINE))",,,,,,,,,
+ACTION,"ASSERT( (Image$$L2SRAM_L2C_DATA$$ZI$$Limit - Image$$L2SRAM_L2C_CODE$$Base) <= 0x30000, L2SRAM size exceeds 192 KB)",,,,,,,,,
+ACTION,"ASSERT( (SDATA0$$ZI$$Limit - SDATA0$$ZI$$Base + SDATA0$$Limit - SDATA0$$Base) <= 0x10000, small data of core0 exceed 64 KB)",,,,,,,,,
+ACTION,"ASSERT( (SDATA1$$ZI$$Limit - SDATA1$$ZI$$Base + SDATA1$$Limit - SDATA1$$Base) <= 0x10000, small data of core1 exceed 64 KB)",,,,,,,,,
+ACTION,"ASSERT( (Image$$EXECUTION_VIEW_END$$ZI$$Limit& 0x1fffffff) <= 0x1C000000, ""only 448 MB for general MCU memory (no ramdisk & DSP space)"")",,,,,,,,FS_RAMDISK=TRUE,(MT6297)
+ACTION,"ASSERT( (Image$$EXECUTION_VIEW_END$$ZI$$Limit& 0x1fffffff) <= 0x17C00000, ""only 380 MB for general MCU memory (no ramdisk & DSP space)"")",,,,,,,,(FS_RAMDISK=TRUE),(!MT6297)
+ACTION,"ASSERT( (Image$$EXECUTION_VIEW_END$$ZI$$Limit& 0x1fffffff) <= 0x19C00000, ""only 412 MB for general MCU memory (no ramdisk & DSP space)"")",,,,,,,,!(FS_RAMDISK=TRUE),(!MT6297)
+ACTION,"ASSERT( (Image$$EXECUTION_VIEW_END$$ZI$$Limit& 0x0fffffff) <= 0x0CD00000, ""only 205 MB for general MCU memory (no ramdisk & DSP space)"")",,,,,,,,!(FS_RAMDISK=TRUE),(CHIP10992 && !__CDMA2000_RAT__)
+ACTION,"ASSERT( (Image$$EXECUTION_VIEW_END$$ZI$$Limit& 0x1fffffff) <= 0x10D00000, ""only 269 MB for general MCU memory (no ramdisk & DSP space)"")",,,,,,,,!(FS_RAMDISK=TRUE),(CHIP10992 && __CDMA2000_RAT__)
+ACTION,"ASSERT( (Image$$CACHED_EXTSRAM_MCURW_HWRW$$ZI$$Limit& 0x0fffffff) < 0x10F00000, ""CACHED_EXTSRAM_MCURW_HWRW_ZI section cannot access 0x10F00000 (ram_disk range)"")",,,,,,,,,(CHIP10992 && __FS_RAMDISK__)
+ACTION,"ASSERT( (Image$$EXTSRAM_DSP_TX_ZI$$Base& 0xF8000000) < 0x10000000, ""Image$$EXTSRAM_DSP_TX_ZI$$Base should be smaller than 0x1000_0000"")",,,,,,,,,
+ACTION,"ASSERT( (Image$$MCURW_HWRW_DNC_NL1_EXT_CSIF$$Limit - Image$$MCURW_HWRW_DNC_SS_EXT_CSIF$$Base) <= 0x680000, ""only 6.5 MB for MCU & DSP share memory"")",,,,,,,,,((MT6885 || MT6873) && !MT6893)
+ACTION,"ASSERT( Image$$CACHED_EXTSRAM_IOCU3_MCURW_HWRW_ZI_15$$ZI$$Limit < 0x3F000000, ""IOCU3 section is out of 0x3F000000"")",,,,,,,,,
diff --git a/mcu/custom/system/Template/lds_config/RegionConfig/MT6297_FPGA.csv b/mcu/custom/system/Template/lds_config/RegionConfig/MT6297_FPGA.csv
new file mode 100644
index 0000000..ad17378
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/RegionConfig/MT6297_FPGA.csv
@@ -0,0 +1,294 @@
+Type,Name,VMA,LMA,ALIGN,MaxSize,Attribute,BaseRegion,ExecutionView,LoadView,Condition,CompileOption
+ACTION,. = ORIGIN(UROM);,,,,,,,,,,
+ACTION,_zap1 = . ;,,,,,,,,,,
+ACTION,_ftext_ram = . ;,,,,,,,,,,
+ACTION, _edata_ram = . ;,,,,,,,,,,
+ACTION, _fbss = . ;,,,,,,,,,,
+ACTION, _end = . ;,,,,,,,,,,
+SectionFrame,ROM_GFH,.,,,,RO,,UROM,UROM,,
+SectionFrame,AUROM,.,,,,RO,,UROM,UROM,,
+SectionFrame,L2SRAM_L2C_CODE,ORIGIN(L2SRAM),,,,RO,,L2SRAM,UROM
+SectionFrame,L2SRAM_L2C_DATA,.,,,,RW,L2SRAM_L2C_DATA,L2SRAM,UROM
+SectionFrame,L2SRAM_L2C_DATA_ZI,.,,,,ZI,L2SRAM_L2C_DATA,L2SRAM,UROM
+ACTION,. = LOADADDR(L2SRAM_L2C_DATA_ZI);,,,,,,,,,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(ROM); /* 0x90000000 */,,,,,,,,
+SectionFrame,ROM,.,,ALIGN(0x4000),,RO,,ROM,UROM
+SectionFrame,CACHED_EXTSRAM_ULTRA_CODE,.,,ALIGN(64),,RO,,ROM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(UROM);,,,,,,,,
+SectionFrame,UROM,.,,ALIGN(64),,RO,,UROM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(ROM);,,,,,,,,
+SectionFrame,DUMMY_L2CACHE_LOCK,.,,,,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+LinkerSymbol,L2CACHE_LOCK,.,,,,EV::Base,,,,,
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE,.,,ALIGN(0x40000),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_L_IDLE,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_W_COMMON,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_W_PAGING,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_T_IDLE,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_C_RTT_IDLE,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_C_DO_IDLE,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_MML1_IDLE,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_SS_IDLE,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_N_CONN0,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_N_CONN1,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_N_CONN3,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_L_CONN0,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_L_CONN1,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_N_CONN2,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_L_CONN2,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_W_CONN0,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_W_CONN1,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_W_CONN2,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_T_CONN0,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_T_CONN1,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_T_CONN2,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_C_RTT_TALKING,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+SectionFrame,DYNAMIC_SECTION_L2CACHE_LOCK_C_DO_DATALINK,.,,ALIGN(0x40),,RO,,ROM,UROM,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+LinkerSymbol,L2CACHE_LOCK,.,,,,EV::ZILimit,,,,,
+LinkerSymbol,L2CACHE_LOCK,ABSOLUTE(Image$$L2CACHE_LOCK$$ZI$$Limit - Image$$L2CACHE_LOCK$$Base),,,,EV::Length,,,,,
+ACTION,. = ORIGIN(RAM);,,,,,,,,
+LinkerSymbol,MCURO_HWRW,.,,,,EV::Base,,,,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,,,(__AMMS_DRDI__)
+ACTION,. += ORIGIN(VRAM);,,,,,,,,,,(__AMMS_DRDI__)
+LinkerSymbol,DRDI,.,,,,EV::Base,,,,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_2G_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GFDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_3GTDD_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_MMRF_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_C2K_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,ALIGN(CACHELINESIZE),,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_01,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_02,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_03,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_04,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_05,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_06,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_07,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_08,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_09,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_10,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_11,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_12,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_13,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_14,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+OVERLAY,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_15,.,,,,RW,CACHED_EXTSRAM_MCURO_HWRW_DRDI_LTE_00,VRAM,UROM,,(__AMMS_DRDI__)
+LinkerSymbol,DRDI,.,,,,EV::Limit,,,,,(__AMMS_DRDI__)
+LinkerSymbol,DRDI,(Image$$DRDI$$Limit - Image$$DRDI$$Base),,,,EV::Length,,,,,(__AMMS_DRDI__)
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+SectionFrame,EXTSRAM_MCURO_HWRW,.,,,,RW,EXTSRAM_MCURO_HWRW,RAM,UROM
+SectionFrame,EXTSRAM_MCURO_HWRW_ZI,.,,,,ZI,EXTSRAM_MCURO_HWRW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURO_HWRW,RAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURO_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURO_HWRW,.,,ALIGN(32),,RW,CACHED_EXTSRAM_MCURO_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURO_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_MCURO_HWRW,VRAM,UROM
+ACTION,. = ALIGN(0x100000);,,,,,,,,,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+SectionFrame,EXTSRAM,.,,,,RW,EXTSRAM,RAM,UROM
+SectionFrame,EXTSRAM_ZI,.,,,,ZI,EXTSRAM,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_RW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_RW,RAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_RW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_RW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_RW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_WT,.,,ALIGN(32),,RW,CACHED_EXTSRAM_WT,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_WT_ZI,.,,,,ZI,CACHED_EXTSRAM_WT,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_NVRAM_LTABLE,.,,,,RW,,VRAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(IOCU2);,,,,,,,,
+SectionFrame,CACHED_EXTSRAM,.,,ALIGN(32),,RW,CACHED_EXTSRAM,IOCU2,UROM
+SectionFrame,CACHED_EXTSRAM_ZI,.,,,,ZI,CACHED_EXTSRAM,IOCU2,UROM
+SectionFrame,bss,.,,,,ZI,CACHED_EXTSRAM,IOCU2,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. = ALIGN(0x10000);,,,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW,RAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_NONCACHEABLE_MCURW_HWRW,RAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. = ALIGN(0x10000);,,,,,,,,,,
+ACTION,. += ORIGIN(IOCU2);,,,,,,,,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW,.,,,,RW,CACHED_EXTSRAM_IOCU2_MCURW_HWRW,IOCU2,UROM
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_IOCU2_MCURW_HWRW,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_00,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_01,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_02,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_03,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_04,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_05,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_06,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_07,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_08,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_09,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_10,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_11,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_12,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_13,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_14,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU2_MCURW_HWRW_15,.,,ALIGN(0x10000),,ZI,,IOCU2,UROM,
+ACTION,. = ALIGN(0x100000);,,,,,,,,,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+LinkerSymbol,ULTRA_DATA,.,,,,EV::Base,,,,,
+SectionFrame,EXTSRAM_ULTRA_DATA,.,,,,RW,EXTSRAM_ULTRA_DATA,RAM,UROM
+SectionFrame,EXTSRAM_ULTRA_DATA_ZI,.,,,,ZI,EXTSRAM_ULTRA_DATA,RAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(IOCU2);,,,,,,,,
+SectionFrame,CACHED_EXTSRAM_IOCU2_ULTRA_DATA,.,,,,RW,CACHED_EXTSRAM_IOCU2_ULTRA_DATA,IOCU2,UROM
+SectionFrame,CACHED_EXTSRAM_IOCU2_ULTRA_DATA_ZI,.,,,,ZI,CACHED_EXTSRAM_IOCU2_ULTRA_DATA,IOCU2,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,CACHED_EXTSRAM_ULTRA_DATA,.,,,,RW,CACHED_EXTSRAM_ULTRA_DATA,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_ULTRA_DATA_ZI,.,,,,ZI,CACHED_EXTSRAM_ULTRA_DATA,VRAM,UROM
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(IOCU3);,,,,,,,,
+SectionFrame,CACHED_EXTSRAM_IOCU3_ULTRA_DATA,.,,,,RW,CACHED_EXTSRAM_IOCU3_ULTRA_DATA,IOCU3,UROM
+SectionFrame,CACHED_EXTSRAM_IOCU3_ULTRA_DATA_ZI,.,,,,ZI,CACHED_EXTSRAM_IOCU3_ULTRA_DATA,IOCU3,UROM
+LinkerSymbol,ULTRA_DATA,.,,,,EV::ZILimit,,,,,
+ACTION,. = ALIGN(0x10000);,,,,,,,,,,
+SectionFrame,CACHED_EXTSRAM_IOCU3_READ_WRITE_ALLOC_MCURW_HWRW,.,,,,RW,CACHED_EXTSRAM_IOCU3_READ_WRITE_ALLOC_MCURW_HWRW,IOCU3,UROM
+SectionFrame,CACHED_EXTSRAM_IOCU3_READ_WRITE_ALLOC_MCURW_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_IOCU3_READ_WRITE_ALLOC_MCURW_HWRW,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_00,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_01,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_02,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_03,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_04,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_05,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_06,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_07,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_08,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_09,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_10,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_11,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_12,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_13,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_14,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+SectionFrame,CACHED_EXTSRAM_IOCU3_MCURW_HWRW_15,.,,ALIGN(0x10000),,ZI,,IOCU3,UROM,
+ACTION,. = ALIGN(0x10000);,,,,,,,,,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. = ALIGN([TX_SIZE]);,,,,,,,,,,
+SectionFrame,EXTSRAM_DSP_TX,.,,,[TX_SIZE],ZI,,RAM,UROM,
+ACTION,. = ALIGN([TX_SIZE]);,,,,,,,,,,
+SectionFrame,EXTSRAM_DSP_RX,.,,ALIGN([RX_SIZE]),[RX_SIZE],ZI,,RAM,UROM,
+ACTION,. = ALIGN(0x10000);,,,,,,,,,,
+SectionFrame,EXTSRAM_MCURW_HWRW,.,,,,RW,EXTSRAM_MCURW_HWRW,RAM,UROM
+SectionFrame,EXTSRAM_MCURW_HWRW_ZI,.,,,,ZI,EXTSRAM_MCURW_HWRW,RAM,UROM
+ACTION,. += ORIGIN(VRAM);,,,,,,,,
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW,.,,ALIGN(32),,RW,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW,VRAM,UROM
+SectionFrame,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW_ZI,.,,,,ZI,DYNAMIC_CACHEABLE_EXTSRAM_DEFAULT_CACHEABLE_MCURW_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURW_HWRW,.,,ALIGN(32),,RW,CACHED_EXTSRAM_MCURW_HWRW,VRAM,UROM
+SectionFrame,CACHED_EXTSRAM_MCURW_HWRW_ZI,.,,,,ZI,CACHED_EXTSRAM_MCURW_HWRW,VRAM,UROM
+LinkerSymbol,SIB_AREA,.,,,,EV::Base,,,,,
+LinkerSymbol,EXECUTION_VIEW_END,.,,,,EV::ZILimit,,,,
+SectionFrame,EXTSRAM_FS_ZI,ORIGIN(EXTSRAM_FS),,,,ZI,,EXTSRAM_FS,UROM,FS_RAMDISK=TRUE
+SectionFrame,EXTSRAM_L1DSP_ZI,ORIGIN(L1DSP),,,,ZI,,L1DSP,UROM,
+LinkerSymbol,SIB_AREA,ORIGIN(EXTSRAM_FS),,,,EV::ZILimit,,,,FS_RAMDISK=TRUE
+LinkerSymbol,SIB_AREA,ORIGIN(L1DSP),,,,EV::ZILimit,,,,!(FS_RAMDISK=TRUE)
+LinkerSymbol,SIB_AREA,ABSOLUTE(Image$$SIB_AREA$$ZI$$Limit - Image$$SIB_AREA$$Base),,,,EV::Length,,,,,
+ACTION,. = LOADADDR(EXTSRAM_L1DSP_ZI);,,,,,,,,
+ACTION,. &= 0x0FFFFFFF;,,,,,,,,
+ACTION,. += ORIGIN(SECURE_RO);,,,,,,,,
+SectionFrame,ROM_SIGNATURE_SECTION,.,,,,RW,,SECURE_RO,UROM,
+LinkerSymbol,KTEST,ORIGIN(RAM)+LENGTH(RAM)-12,,,,EV::Base,,,,
+LinkerSymbol,DUMMY_END,[EXTSRAM_END],,,,EV::Base,,,,
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0x40000), N_IDLE end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_N_CONN0$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0xE5000), N_CONN0 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_N_CONN1$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0xE5000), N_CONN1 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_N_CONN2$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0x125000), N_CONN2 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_N_CONN3$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0xE5000), N_CONN3 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_L_CONN0$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0x100000), L_CONN0 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_L_CONN1$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0x100000), L_CONN1 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_L_CONN2$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0x140000), L_CONN2 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_W_CONN0$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0x165800), W_CONN0 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_W_CONN1$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0x180000), W_CONN1 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_W_CONN2$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0x1B2000), W_CONN2 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_T_CONN0$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0x1B5800), T_CONN0 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_T_CONN1$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0x1B7C00), T_CONN1 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_T_CONN2$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0x1B9000), T_CONN2 end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_C_RTT_TALKING$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0x1B9000), C_RTT_TALKING end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_C_DO_DATALINK$$Limit <= (Image$$DYNAMIC_SECTION_L2CACHE_LOCK_N_IDLE$$Base + 0x1B9400), C_DO_DATALIK end exceeds allocated l2 cache way)",,,,,,,,,(__DYNAMIC_CACHE_LOCK_CENTRAL_CONTROL_SUPPORT__)
+ACTION,"ASSERT( INTERRUPT_VECTOR$$Base >= GENERAL_EXCEPTION$$End, please reduce the size of input section GENERAL_EXCEPTION(VECTOR_ROUTINE))",,,,,,,,,
+ACTION,"ASSERT( (Image$$L2SRAM_L2C_DATA$$ZI$$Limit - Image$$L2SRAM_L2C_CODE$$Base) <= 0x30000, L2SRAM size exceeds 192 KB)",,,,,,,,,
+ACTION,"ASSERT( (SDATA0$$ZI$$Limit - SDATA0$$ZI$$Base + SDATA0$$Limit - SDATA0$$Base) <= 0x10000, small data of core0 exceed 64 KB)",,,,,,,,,
+ACTION,"ASSERT( (SDATA1$$ZI$$Limit - SDATA1$$ZI$$Base + SDATA1$$Limit - SDATA1$$Base) <= 0x10000, small data of core1 exceed 64 KB)",,,,,,,,,
+ACTION,"ASSERT( DYNAMIC_SECTION_L2CACHE_LOCK_0$$Length <= 0x18000, ""only 96 KB for DYNAMIC_SECTION_L2CACHE_LOCK_0"")",,,,,,,,,
+ACTION,"ASSERT( (Image$$EXECUTION_VIEW_END$$ZI$$Limit& 0x0fffffff) <= 0xBB00000, ""only 187 MB for general MCU memory (no ramdisk & DSP space)"")",,,,,,,,FS_RAMDISK=TRUE
+ACTION,"ASSERT( (Image$$EXECUTION_VIEW_END$$ZI$$Limit& 0x0fffffff) <= 0xCB00000, ""only 203 MB for general MCU memory (no ramdisk & DSP space)"")",,,,,,,,!(FS_RAMDISK=TRUE)
diff --git a/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/ELBRUS.txt b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/ELBRUS.txt
new file mode 100755
index 0000000..d27128d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/ELBRUS.txt
@@ -0,0 +1,30 @@
+AUROM : ORIGIN = [AUROM_BASE], LENGTH = [AUROM_LEN]
+UROM : ORIGIN = [UROM_BASE], LENGTH = [UROM_LEN]
+ROM : ORIGIN = [ROM_BASE], LENGTH = [ROM_LEN]
+MCURO_HWRW : ORIGIN = [MCURO_HWRW_BASE], LENGTH = [MCURO_HWRW_LEN]
+RAM : ORIGIN = [RAM_BASE], LENGTH = [RAM_LEN]
+VRAM : ORIGIN = [VRAM_BASE], LENGTH = [VRAM_LEN]
+VRAM_CORE0 : ORIGIN = [VRAM_CORE0_BASE], LENGTH = [VRAM_CORE0_LEN]
+RAM_CORE0 : ORIGIN = [RAM_CORE0_BASE], LENGTH = [RAM_CORE0_LEN]
+VRAM_CORE1 : ORIGIN = [VRAM_CORE1_BASE], LENGTH = [VRAM_CORE1_LEN]
+RAM_CORE1 : ORIGIN = [RAM_CORE1_BASE], LENGTH = [RAM_CORE1_LEN]
+VRAM_CORE2 : ORIGIN = [VRAM_CORE2_BASE], LENGTH = [VRAM_CORE2_LEN]
+RAM_CORE2 : ORIGIN = [RAM_CORE2_BASE], LENGTH = [RAM_CORE2_LEN]
+MCURW_HWRW : ORIGIN = [MCURW_HWRW_BASE], LENGTH = [MCURW_HWRW_LEN]
+L2C_LOCK : ORIGIN = [L2C_LOCK_BASE], LENGTH = [L2C_LOCK_LEN]
+IOCU2 : ORIGIN = [IOCU2_BASE], LENGTH = [IOCU2_LEN]
+DSP_TXRX : ORIGIN = [DSP_TXRX_BASE], LENGTH = [DSP_TXRX_LEN]
+EXTSRAM_FS : ORIGIN = [EXTSRAM_FS_BASE], LENGTH = [EXTSRAM_FS_LEN]
+VOLTE : ORIGIN = [VOLTE_BASE], LENGTH = [VOLTE_LEN]
+ISPRAM0 : ORIGIN = 0x9F800000, LENGTH = 0x00060000
+DSPRAM0 : ORIGIN = 0x9F880000, LENGTH = 0x00020000
+ISPRAM1 : ORIGIN = 0x9F900000, LENGTH = 0x00060000
+DSPRAM1 : ORIGIN = 0x9F980000, LENGTH = 0x00020000
+ISPRAM2 : ORIGIN = 0x9FA00000, LENGTH = 0x00060000
+DSPRAM2 : ORIGIN = 0x9FA80000, LENGTH = 0x00020000
+L2SRAM : ORIGIN = 0x9FC00000, LENGTH = 0x00040000
+BROM : ORIGIN = 0x9FE00000, LENGTH = 0x00100000
+BS1 : ORIGIN = 0x9FF00000, LENGTH = 0x00040000
+BS2 : ORIGIN = 0x9FF40000, LENGTH = 0x00040000
+BS3 : ORIGIN = 0x9FF80000, LENGTH = 0x00040000
+BS4 : ORIGIN = 0x9FFC0000, LENGTH = 0x00040000
diff --git a/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/GEN93M17.txt b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/GEN93M17.txt
new file mode 100755
index 0000000..45c4e86
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/GEN93M17.txt
@@ -0,0 +1,29 @@
+UROM : ORIGIN = [UROM_BASE], LENGTH = [UROM_LEN]
+ROM : ORIGIN = [ROM_BASE], LENGTH = [ROM_LEN]
+MCURO_HWRW : ORIGIN = [MCURO_HWRW_BASE], LENGTH = [MCURO_HWRW_LEN]
+RAM : ORIGIN = [RAM_BASE], LENGTH = [RAM_LEN]
+VRAM : ORIGIN = [VRAM_BASE], LENGTH = [VRAM_LEN]
+VRAM_CORE0 : ORIGIN = [VRAM_CORE0_BASE], LENGTH = [VRAM_CORE0_LEN]
+RAM_CORE0 : ORIGIN = [RAM_CORE0_BASE], LENGTH = [RAM_CORE0_LEN]
+VRAM_CORE1 : ORIGIN = [VRAM_CORE1_BASE], LENGTH = [VRAM_CORE1_LEN]
+RAM_CORE1 : ORIGIN = [RAM_CORE1_BASE], LENGTH = [RAM_CORE1_LEN]
+VRAM_CORE2 : ORIGIN = [VRAM_CORE2_BASE], LENGTH = [VRAM_CORE2_LEN]
+RAM_CORE2 : ORIGIN = [RAM_CORE2_BASE], LENGTH = [RAM_CORE2_LEN]
+MCURW_HWRW : ORIGIN = [MCURW_HWRW_BASE], LENGTH = [MCURW_HWRW_LEN]
+L2C_LOCK : ORIGIN = [L2C_LOCK_BASE], LENGTH = [L2C_LOCK_LEN]
+IOCU2 : ORIGIN = [IOCU2_BASE], LENGTH = [IOCU2_LEN]
+DSP_TXRX : ORIGIN = [DSP_TXRX_BASE], LENGTH = [DSP_TXRX_LEN]
+EXTSRAM_FS : ORIGIN = [EXTSRAM_FS_BASE], LENGTH = [EXTSRAM_FS_LEN]
+VOLTE : ORIGIN = [VOLTE_BASE], LENGTH = [VOLTE_LEN]
+ISPRAM0 : ORIGIN = 0x9F000000, LENGTH = 0x00100000
+DSPRAM0 : ORIGIN = 0x9F100000, LENGTH = 0x000A0000
+ISPRAM1 : ORIGIN = 0x9F200000, LENGTH = 0x00100000
+DSPRAM1 : ORIGIN = 0x9F300000, LENGTH = 0x000A0000
+ISPRAM2 : ORIGIN = 0x9FA00000, LENGTH = 0x0
+DSPRAM2 : ORIGIN = 0x9FA80000, LENGTH = 0x0
+L2SRAM : ORIGIN = 0x9FC00000, LENGTH = 0x0
+BROM : ORIGIN = 0x9FE00000, LENGTH = 0x00100000
+BS1 : ORIGIN = 0x9FF00000, LENGTH = 0x00040000
+BS2 : ORIGIN = 0x9FF40000, LENGTH = 0x00040000
+BS3 : ORIGIN = 0x9FF80000, LENGTH = 0x00040000
+BS4 : ORIGIN = 0x9FFC0000, LENGTH = 0x00040000
diff --git a/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6295M.txt b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6295M.txt
new file mode 100755
index 0000000..aff3987
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6295M.txt
@@ -0,0 +1,14 @@
+UROM : ORIGIN = [UROM_BASE], LENGTH = [UROM_LEN]
+ROM : ORIGIN = [ROM_BASE], LENGTH = [ROM_LEN]
+RAM : ORIGIN = [RAM_BASE], LENGTH = [RAM_LEN]
+VRAM : ORIGIN = [VRAM_BASE], LENGTH = [VRAM_LEN]
+IOCU2 : ORIGIN = [IOCU2_BASE], LENGTH = [IOCU2_LEN]
+IOCU3 : ORIGIN = [IOCU3_BASE], LENGTH = [IOCU3_LEN]
+EXTSRAM_FS : ORIGIN = [EXTSRAM_FS_BASE], LENGTH = [EXTSRAM_FS_LEN]
+L1DSP : ORIGIN = [L1DSP_BASE], LENGTH = [L1DSP_LEN]
+SECURE_RO : ORIGIN = [UROM_BASE], LENGTH = 0xffffffff - [UROM_BASE]
+BROM : ORIGIN = 0x9FE00000, LENGTH = 0x00100000
+BS1 : ORIGIN = 0x9FF00000, LENGTH = 0x00040000
+BS2 : ORIGIN = 0x9FF40000, LENGTH = 0x00040000
+BS3 : ORIGIN = 0x9FF80000, LENGTH = 0x00040000
+BS4 : ORIGIN = 0x9FFC0000, LENGTH = 0x00040000
diff --git a/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6297.txt b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6297.txt
new file mode 100755
index 0000000..85b7020
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6297.txt
@@ -0,0 +1,24 @@
+UROM : ORIGIN = [UROM_BASE], LENGTH = [UROM_LEN]
+ROM : ORIGIN = [ROM_BASE], LENGTH = [ROM_LEN]
+RAM : ORIGIN = [RAM_BASE], LENGTH = [RAM_LEN]
+VRAM : ORIGIN = [VRAM_BASE], LENGTH = [VRAM_LEN]
+IOCU2 : ORIGIN = [IOCU2_BASE], LENGTH = [IOCU2_LEN]
+IOCU3 : ORIGIN = [IOCU3_BASE], LENGTH = [IOCU3_LEN]
+EXTSRAM_FS : ORIGIN = [EXTSRAM_FS_BASE], LENGTH = [EXTSRAM_FS_LEN]
+L1DSP : ORIGIN = [L1DSP_BASE], LENGTH = [L1DSP_LEN]
+SECURE_RO : ORIGIN = [UROM_BASE], LENGTH = 0xffffffff - [UROM_BASE]
+USPRAM : ORIGIN = 0x9F000000, LENGTH = 0x00040000
+ISPRAM0 : ORIGIN = 0x9F100000, LENGTH = 0x00010000
+DSPRAM0 : ORIGIN = 0x9F200000, LENGTH = 0x00010000
+ISPRAM1 : ORIGIN = 0x9F300000, LENGTH = 0x00010000
+DSPRAM1 : ORIGIN = 0x9F400000, LENGTH = 0x00010000
+ISPRAM2 : ORIGIN = 0x9F500000, LENGTH = 0x00010000
+DSPRAM2 : ORIGIN = 0x9F600000, LENGTH = 0x00010000
+ISPRAM3 : ORIGIN = 0x9F700000, LENGTH = 0x00010000
+DSPRAM3 : ORIGIN = 0x9F800000, LENGTH = 0x00010000
+L2SRAM : ORIGIN = 0x9FC00000, LENGTH = [L2SRAM_LEN]
+BROM : ORIGIN = 0x9FE00000, LENGTH = 0x00100000
+BS1 : ORIGIN = 0x9FF00000, LENGTH = 0x00040000
+BS2 : ORIGIN = 0x9FF40000, LENGTH = 0x00040000
+BS3 : ORIGIN = 0x9FF80000, LENGTH = 0x00040000
+BS4 : ORIGIN = 0x9FFC0000, LENGTH = 0x00040000
diff --git a/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6297_FPGA.txt b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6297_FPGA.txt
new file mode 100755
index 0000000..9235a6e
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6297_FPGA.txt
@@ -0,0 +1,24 @@
+UROM : ORIGIN = [UROM_BASE], LENGTH = [UROM_LEN]
+ROM : ORIGIN = [ROM_BASE], LENGTH = [ROM_LEN]
+RAM : ORIGIN = [RAM_BASE], LENGTH = [RAM_LEN]
+VRAM : ORIGIN = [VRAM_BASE], LENGTH = [VRAM_LEN]
+IOCU2 : ORIGIN = [IOCU2_BASE], LENGTH = [IOCU2_LEN]
+IOCU3 : ORIGIN = [IOCU3_BASE], LENGTH = [IOCU3_LEN]
+EXTSRAM_FS : ORIGIN = [EXTSRAM_FS_BASE], LENGTH = [EXTSRAM_FS_LEN]
+L1DSP : ORIGIN = [L1DSP_BASE], LENGTH = [L1DSP_LEN]
+SECURE_RO : ORIGIN = [UROM_BASE], LENGTH = 0xffffffff - [UROM_BASE]
+USPRAM : ORIGIN = 0x9F000000, LENGTH = 0x00040000
+ISPRAM0 : ORIGIN = 0x9F100000, LENGTH = 0x00010000
+DSPRAM0 : ORIGIN = 0x9F200000, LENGTH = 0x00010000
+ISPRAM1 : ORIGIN = 0x9F300000, LENGTH = 0x00010000
+DSPRAM1 : ORIGIN = 0x9F400000, LENGTH = 0x00010000
+ISPRAM2 : ORIGIN = 0x9F500000, LENGTH = 0x00010000
+DSPRAM2 : ORIGIN = 0x9F600000, LENGTH = 0x00010000
+ISPRAM3 : ORIGIN = 0x9F700000, LENGTH = 0x00010000
+DSPRAM3 : ORIGIN = 0x9F800000, LENGTH = 0x00010000
+L2SRAM : ORIGIN = 0x9FC00000, LENGTH = 0x00030000
+BROM : ORIGIN = 0x9FE00000, LENGTH = 0x00100000
+BS1 : ORIGIN = 0x9FF00000, LENGTH = 0x00040000
+BS2 : ORIGIN = 0x9FF40000, LENGTH = 0x00040000
+BS3 : ORIGIN = 0x9FF80000, LENGTH = 0x00040000
+BS4 : ORIGIN = 0x9FFC0000, LENGTH = 0x00040000
diff --git a/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6739.txt b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6739.txt
new file mode 100755
index 0000000..7ba7f07
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6739.txt
@@ -0,0 +1,31 @@
+UROM : ORIGIN = [UROM_BASE], LENGTH = [UROM_LEN]
+ROM : ORIGIN = [ROM_BASE], LENGTH = [ROM_LEN]
+MCURO_HWRW : ORIGIN = [MCURO_HWRW_BASE], LENGTH = [MCURO_HWRW_LEN]
+RAM : ORIGIN = [RAM_BASE], LENGTH = [RAM_LEN]
+VRAM : ORIGIN = [VRAM_BASE], LENGTH = [VRAM_LEN]
+MCURW_HWRW : ORIGIN = [MCURW_HWRW_BASE], LENGTH = [MCURW_HWRW_LEN]
+DSP_TXRX : ORIGIN = [DSP_TXRX_BASE], LENGTH = [DSP_TXRX_LEN]
+IOCU2 : ORIGIN = [IOCU2_BASE], LENGTH = [IOCU2_LEN]
+IOCU3 : ORIGIN = [IOCU3_BASE], LENGTH = [IOCU3_LEN]
+L2C_LOCK : ORIGIN = [L2C_LOCK_BASE], LENGTH = [L2C_LOCK_LEN]
+CORE0 : ORIGIN = [CORE0_BASE], LENGTH = [CORE0_LEN]
+CORE1 : ORIGIN = [CORE1_BASE], LENGTH = [CORE1_LEN]
+DRDI : ORIGIN = [DRDI_BASE], LENGTH = [DRDI_LEN]
+EXTSRAM_FS : ORIGIN = [EXTSRAM_FS_BASE], LENGTH = [EXTSRAM_FS_LEN]
+L1DSP : ORIGIN = [L1DSP_BASE], LENGTH = [L1DSP_LEN]
+SECURE_RO : ORIGIN = [UROM_BASE], LENGTH = 0xffffffff - [UROM_BASE]
+ISPRAM0 : ORIGIN = 0x9F000000, LENGTH = 0x0002D000
+ISPRAM0A : ORIGIN = 0x9F040000, LENGTH = 0x0002D000
+ISPRAM0B : ORIGIN = 0x9F080000, LENGTH = 0x0002D000
+ISPRAM0C : ORIGIN = 0x9F0C0000, LENGTH = 0x0002D000
+DSPRAM0 : ORIGIN = 0x9F100000, LENGTH = 0x00009000
+ISPRAM1 : ORIGIN = 0x9F200000, LENGTH = 0x00024000
+ISPRAM1A : ORIGIN = 0x9F240000, LENGTH = 0x00040000
+ISPRAM1B : ORIGIN = 0x9F280000, LENGTH = 0x00040000
+ISPRAM1C : ORIGIN = 0x9F2C0000, LENGTH = 0x00040000
+DSPRAM1 : ORIGIN = 0x9F300000, LENGTH = 0x00006000
+BROM : ORIGIN = 0x9FE00000, LENGTH = 0x00100000
+BS1 : ORIGIN = 0x9FF00000, LENGTH = 0x00040000
+BS2 : ORIGIN = 0x9FF40000, LENGTH = 0x00040000
+BS3 : ORIGIN = 0x9FF80000, LENGTH = 0x00040000
+BS4 : ORIGIN = 0x9FFC0000, LENGTH = 0x00040000
diff --git a/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6755.txt b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6755.txt
new file mode 100755
index 0000000..2ee33b1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6755.txt
@@ -0,0 +1,10 @@
+ROM : ORIGIN = [ROM_BASE], LENGTH = [ROM_LEN]
+L1CORE_LV : ORIGIN = [L1CORE_LV_BASE], LENGTH = [L1CORE_LV_LEN]
+L1CORE_RWZI : ORIGIN = [L1CORE_RWZI_BASE], LENGTH = [L1CORE_RWZI_LEN]
+RAM : ORIGIN = [RAM_BASE], LENGTH = [RAM_LEN]
+VRAM : ORIGIN = [CACHEABLE_PREFIX] | [RAM_BASE], LENGTH = [RAM_LEN]
+TCM : ORIGIN = 0x70000000, LENGTH = 0x80000
+DTCM : ORIGIN = 0x70040000, LENGTH = 0x40000
+L1CORE_TCM_BASE : ORIGIN = 0x72000000, LENGTH = 0x0
+L1CORE_ITCM : ORIGIN = 0x00000000, LENGTH = 0x80000
+L1CORE_L2SRAM : ORIGIN = 0x75000000, LENGTH = 0x80000
diff --git a/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6763.txt b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6763.txt
new file mode 100755
index 0000000..035130d
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6763.txt
@@ -0,0 +1,30 @@
+UROM : ORIGIN = [UROM_BASE], LENGTH = [UROM_LEN]
+ROM : ORIGIN = [ROM_BASE], LENGTH = [ROM_LEN]
+MCURO_HWRW : ORIGIN = [MCURO_HWRW_BASE], LENGTH = [MCURO_HWRW_LEN]
+RAM : ORIGIN = [RAM_BASE], LENGTH = [RAM_LEN]
+VRAM : ORIGIN = [VRAM_BASE], LENGTH = [VRAM_LEN]
+MCURW_HWRW : ORIGIN = [MCURW_HWRW_BASE], LENGTH = [MCURW_HWRW_LEN]
+DSP_TXRX : ORIGIN = [DSP_TXRX_BASE], LENGTH = [DSP_TXRX_LEN]
+IOCU2 : ORIGIN = [IOCU2_BASE], LENGTH = [IOCU2_LEN]
+IOCU3 : ORIGIN = [IOCU3_BASE], LENGTH = [IOCU3_LEN]
+L2C_LOCK : ORIGIN = [L2C_LOCK_BASE], LENGTH = [L2C_LOCK_LEN]
+CORE0 : ORIGIN = [CORE0_BASE], LENGTH = [CORE0_LEN]
+CORE1 : ORIGIN = [CORE1_BASE], LENGTH = [CORE1_LEN]
+EXTSRAM_FS : ORIGIN = [EXTSRAM_FS_BASE], LENGTH = [EXTSRAM_FS_LEN]
+L1DSP : ORIGIN = [L1DSP_BASE], LENGTH = [L1DSP_LEN]
+SECURE_RO : ORIGIN = [UROM_BASE], LENGTH = 0xffffffff - [UROM_BASE]
+ISPRAM0 : ORIGIN = 0x9F000000, LENGTH = 0x0002D000
+ISPRAM0A : ORIGIN = 0x9F040000, LENGTH = 0x0002D000
+ISPRAM0B : ORIGIN = 0x9F080000, LENGTH = 0x0002D000
+ISPRAM0C : ORIGIN = 0x9F0C0000, LENGTH = 0x0002D000
+DSPRAM0 : ORIGIN = 0x9F100000, LENGTH = 0x00009000
+ISPRAM1 : ORIGIN = 0x9F200000, LENGTH = 0x00024000
+ISPRAM1A : ORIGIN = 0x9F240000, LENGTH = 0x00040000
+ISPRAM1B : ORIGIN = 0x9F280000, LENGTH = 0x00040000
+ISPRAM1C : ORIGIN = 0x9F2C0000, LENGTH = 0x00040000
+DSPRAM1 : ORIGIN = 0x9F300000, LENGTH = 0x00006000
+BROM : ORIGIN = 0x9FE00000, LENGTH = 0x00100000
+BS1 : ORIGIN = 0x9FF00000, LENGTH = 0x00040000
+BS2 : ORIGIN = 0x9FF40000, LENGTH = 0x00040000
+BS3 : ORIGIN = 0x9FF80000, LENGTH = 0x00040000
+BS4 : ORIGIN = 0x9FFC0000, LENGTH = 0x00040000
diff --git a/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6771.txt b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6771.txt
new file mode 100755
index 0000000..7ba7f07
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6771.txt
@@ -0,0 +1,31 @@
+UROM : ORIGIN = [UROM_BASE], LENGTH = [UROM_LEN]
+ROM : ORIGIN = [ROM_BASE], LENGTH = [ROM_LEN]
+MCURO_HWRW : ORIGIN = [MCURO_HWRW_BASE], LENGTH = [MCURO_HWRW_LEN]
+RAM : ORIGIN = [RAM_BASE], LENGTH = [RAM_LEN]
+VRAM : ORIGIN = [VRAM_BASE], LENGTH = [VRAM_LEN]
+MCURW_HWRW : ORIGIN = [MCURW_HWRW_BASE], LENGTH = [MCURW_HWRW_LEN]
+DSP_TXRX : ORIGIN = [DSP_TXRX_BASE], LENGTH = [DSP_TXRX_LEN]
+IOCU2 : ORIGIN = [IOCU2_BASE], LENGTH = [IOCU2_LEN]
+IOCU3 : ORIGIN = [IOCU3_BASE], LENGTH = [IOCU3_LEN]
+L2C_LOCK : ORIGIN = [L2C_LOCK_BASE], LENGTH = [L2C_LOCK_LEN]
+CORE0 : ORIGIN = [CORE0_BASE], LENGTH = [CORE0_LEN]
+CORE1 : ORIGIN = [CORE1_BASE], LENGTH = [CORE1_LEN]
+DRDI : ORIGIN = [DRDI_BASE], LENGTH = [DRDI_LEN]
+EXTSRAM_FS : ORIGIN = [EXTSRAM_FS_BASE], LENGTH = [EXTSRAM_FS_LEN]
+L1DSP : ORIGIN = [L1DSP_BASE], LENGTH = [L1DSP_LEN]
+SECURE_RO : ORIGIN = [UROM_BASE], LENGTH = 0xffffffff - [UROM_BASE]
+ISPRAM0 : ORIGIN = 0x9F000000, LENGTH = 0x0002D000
+ISPRAM0A : ORIGIN = 0x9F040000, LENGTH = 0x0002D000
+ISPRAM0B : ORIGIN = 0x9F080000, LENGTH = 0x0002D000
+ISPRAM0C : ORIGIN = 0x9F0C0000, LENGTH = 0x0002D000
+DSPRAM0 : ORIGIN = 0x9F100000, LENGTH = 0x00009000
+ISPRAM1 : ORIGIN = 0x9F200000, LENGTH = 0x00024000
+ISPRAM1A : ORIGIN = 0x9F240000, LENGTH = 0x00040000
+ISPRAM1B : ORIGIN = 0x9F280000, LENGTH = 0x00040000
+ISPRAM1C : ORIGIN = 0x9F2C0000, LENGTH = 0x00040000
+DSPRAM1 : ORIGIN = 0x9F300000, LENGTH = 0x00006000
+BROM : ORIGIN = 0x9FE00000, LENGTH = 0x00100000
+BS1 : ORIGIN = 0x9FF00000, LENGTH = 0x00040000
+BS2 : ORIGIN = 0x9FF40000, LENGTH = 0x00040000
+BS3 : ORIGIN = 0x9FF80000, LENGTH = 0x00040000
+BS4 : ORIGIN = 0x9FFC0000, LENGTH = 0x00040000
diff --git a/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6797.txt b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6797.txt
new file mode 100755
index 0000000..2ee33b1
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/MT6797.txt
@@ -0,0 +1,10 @@
+ROM : ORIGIN = [ROM_BASE], LENGTH = [ROM_LEN]
+L1CORE_LV : ORIGIN = [L1CORE_LV_BASE], LENGTH = [L1CORE_LV_LEN]
+L1CORE_RWZI : ORIGIN = [L1CORE_RWZI_BASE], LENGTH = [L1CORE_RWZI_LEN]
+RAM : ORIGIN = [RAM_BASE], LENGTH = [RAM_LEN]
+VRAM : ORIGIN = [CACHEABLE_PREFIX] | [RAM_BASE], LENGTH = [RAM_LEN]
+TCM : ORIGIN = 0x70000000, LENGTH = 0x80000
+DTCM : ORIGIN = 0x70040000, LENGTH = 0x40000
+L1CORE_TCM_BASE : ORIGIN = 0x72000000, LENGTH = 0x0
+L1CORE_ITCM : ORIGIN = 0x00000000, LENGTH = 0x80000
+L1CORE_L2SRAM : ORIGIN = 0x75000000, LENGTH = 0x80000
diff --git a/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/TK6291.txt b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/TK6291.txt
new file mode 100644
index 0000000..fd6536b
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/ldsTemplate/MEMORY/TK6291.txt
@@ -0,0 +1,10 @@
+ROM : ORIGIN = [ROM_BASE], LENGTH = [ROM_LEN]
+L1CORE_LV : ORIGIN = [L1CORE_LV_BASE], LENGTH = [L1CORE_LV_LEN]
+L1CORE_RWZI : ORIGIN = [L1CORE_RWZI_BASE], LENGTH = [L1CORE_RWZI_LEN]
+RAM : ORIGIN = [RAM_BASE], LENGTH = [RAM_LEN]
+VRAM : ORIGIN = [CACHEABLE_PREFIX] | [RAM_BASE], LENGTH = [RAM_LEN]
+TCM : ORIGIN = 0x70000000, LENGTH = 0x80000
+DTCM : ORIGIN = 0x70040000, LENGTH = 0x40000
+L1CORE_TCM_BASE : ORIGIN = 0x72000000, LENGTH = 0x0
+L1CORE_ITCM : ORIGIN = 0x00000000, LENGTH = 0x80000
+L1CORE_L2SRAM : ORIGIN = 0x75000000, LENGTH = 0x100000
diff --git a/mcu/custom/system/Template/lds_config/ldsTemplate/ldsMainFrame.txt b/mcu/custom/system/Template/lds_config/ldsTemplate/ldsMainFrame.txt
new file mode 100644
index 0000000..ba9bdbc
--- /dev/null
+++ b/mcu/custom/system/Template/lds_config/ldsTemplate/ldsMainFrame.txt
@@ -0,0 +1,39 @@
+OUTPUT_ARCH(mips)
+ENTRY(INT_Vectors)
+MEMORY
+{
+[ldsGen_GenMEMORY]
+}
+
+CACHELINESIZE = 32;
+
+SECTIONS
+{
+[ldsGen_GenSECTIONS]
+[ldsGen_AvoidOrphanSECTIONS]
+ /DISCARD/ :
+ {
+ * (SHOULD_NOT_USED_RODATA)
+ * (SHOULD_NOT_USED_FUNCTION)
+
+ /* SPRAM3 */
+ * (.sdata_3)
+ * (.sdata_3.*)
+ * (.sbss_3)
+ * (.sbss_3.*)
+ * (ISPRAM_ROCODE_CORE3*)
+ * (DSPRAM_RODATA_CORE3*)
+ * (DSPRAM_RW_CORE3*)
+ * (DSPRAM_ZI_CORE3*)
+ * (IOCU_READ_ALLOC_MCURW_HWRW_C*)
+ * (.nanoMIPS.abiflags*)
+ * (.note.gnu.gold-version*)
+ * (.init)
+ * (.jcr*)
+ * (.eh_frame*)
+ * (.gcc_except_table*)
+ }
+ PROVIDE (end = .);
+}
+
+EXTERN(DummyReference)