[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/driver/devdrv/csif/inc/dummy.txt b/mcu/driver/devdrv/csif/inc/dummy.txt
new file mode 100644
index 0000000..285ea6c
--- /dev/null
+++ b/mcu/driver/devdrv/csif/inc/dummy.txt
@@ -0,0 +1 @@
+Please DO NOT use this path. (INC_PATH, #include, ... )
diff --git a/mcu/driver/devdrv/csif/mt6297/inc/csif_SSDVT.h b/mcu/driver/devdrv/csif/mt6297/inc/csif_SSDVT.h
new file mode 100644
index 0000000..0be6551
--- /dev/null
+++ b/mcu/driver/devdrv/csif/mt6297/inc/csif_SSDVT.h
@@ -0,0 +1,408 @@
+//***********************
+// Instance number
+//***********************
+#define S2C_IRQ_NUM (6)
+#define C2S_IRQ_NUM (4)
+#define S2C_IDLE_IRQ_NUM (2)
+#define DSP_MPU_NUM (2)
+#define L1_MPU_NUM (2)
+#define ERROR_SOURCE_NUM (2)
+#define DSM_SRAM_SIZE (8192)
+#define CSIF_DSR_SIZE_TEMP (CSIF_DSR_SIZE) // 1KB
+#define DSP_CORE_TH_NUM (4)
+#define CSIF_MAILBOX_NUM (6)
+#define CSIF_64_MAILBOX_NUM (5)
+#define CSIF_256_MAILBOX_NUM (1)
+#define CSIF_MAX_MAILBOX_ENTRY_NUM (256)
+#define OLPDET_MUM_BIT_NUM (CSIF_DSM_SIZE/CSIF_OLPDET_UNIT)
+
+//***********************
+// Error bit
+//***********************
+#define S2C_IRQ_OVFL_ERROR_BIT_OFFSET (0)
+#define S2C_IRQ0_OVFL_ERROR_BIT (0)
+#define S2C_IRQ1_OVFL_ERROR_BIT (1)
+#define S2C_IRQ2_OVFL_ERROR_BIT (2)
+#define S2C_IRQ3_OVFL_ERROR_BIT (3)
+#define S2C_IRQ4_OVFL_ERROR_BIT (4)
+#define S2C_IRQ5_OVFL_ERROR_BIT (5)
+#define DSP_MPU_ERROR_BIT_OFFSET (10)
+#define DSP_MPU0_ERROR_BIT (10)
+#define DSP_MPU1_ERROR_BIT (11)
+#define DSP_UNDEF_REGION_BIT_OFFSET (12)
+#define DSP_UNDEF_DSM_WRITE (12)
+#define DSP_UNDEF_DSM_READ (13)
+#define DSP_UNDEF_DSR_WRITE (14)
+#define DSP_UNDEF_DSR_READ (15)
+#define MPU_CFG_ERROR_BIT_OFFSET (16)
+#define DSP_MPU0_CFG_ERROR_BIT (16)
+#define DSP_MPU1_CFG_ERROR_BIT (17)
+#define L1_MPU0_CFG_ERROR_BIT (18)
+#define L1_MPU1_CFG_ERROR_BIT (19)
+#define MAILBOX_ERR_BIT_OFFSET (20)
+#define MAILBOX0_ERR_BIT (20)
+#define MAILBOX1_ERR_BIT (21)
+#define MAILBOX2_ERR_BIT (22)
+#define MAILBOX3_ERR_BIT (23)
+#define MAILBOX4_ERR_BIT (24)
+#define MAILBOX5_ERR_BIT (25)
+#define OLPDET_ERR_BIT (26)
+
+
+
+//***********************
+// Error Source bit
+//***********************
+#define S2C_IRQ_OVFL_ERROR_SOURCE0_OFFSET (0)
+#define S2C_IRQ_OVFL_ERROR_SOURCE_BIT_WIDTH (8)
+#define S2C_IRQ_OVFL_ERROR_SOURCE_BIT_MASK (0xFF)
+#define S2C_IRQ_OVFL_ERROR_SOURCE1_OFFSET (0)
+//#if !defined(__JSP__)
+#define ERROR_SOURCE_ID_MCORE0_TH0 (0)
+#define ERROR_SOURCE_ID_MCORE0_TH1 (1)
+#define ERROR_SOURCE_ID_MCORE0_TH2 (2)
+#define ERROR_SOURCE_ID_MCORE0_TH3 (3)
+#define ERROR_SOURCE_ID_MCORE1_TH0 (8)
+#define ERROR_SOURCE_ID_MCORE1_TH1 (9)
+#define ERROR_SOURCE_ID_MCORE1_TH2 (10)
+#define ERROR_SOURCE_ID_MCORE1_TH3 (11)
+/*
+#else
+#define ERROR_SOURCE_ID_MCORE0_TH0 (0)
+#define ERROR_SOURCE_ID_MCORE0_TH1 (1)
+#define ERROR_SOURCE_ID_MCORE0_TH2 (2)
+#define ERROR_SOURCE_ID_MCORE0_TH3 (3)
+#define ERROR_SOURCE_ID_MCORE1_TH0 (4)
+#define ERROR_SOURCE_ID_MCORE1_TH1 (5)
+#define ERROR_SOURCE_ID_MCORE1_TH2 (6)
+#define ERROR_SOURCE_ID_MCORE1_TH3 (7)
+#endif
+*/
+#define ERROR_SOURCE_ID_DEFAULT_VALUE (0xFF)
+
+#define DSP_MPU_ERROR_SOURCE1_OFFSET (16)
+#define DSP_MPU_ERROR_SOURCE_BIT_MASK (0xFF)
+#define DSP_MPU_ERROR_SOURCE_BIT_WIDTH (8)
+
+#define DSP_UNDEFINED_ERROR_SOURCE2_OFFSET (0)
+#define DSP_UNDEFINED_ERROR_SOURCE_BIT_MASK (0xFF)
+#define DSP_UNDEFINED_ERROR_SOURCE_BIT_WIDTH (8)
+
+#define MAILBOX_ERROR_SOURCE3_OFFSET (0)
+#define MAILBOX_ERROR_SOURCE4_OFFSET (0)
+#define MAILBOX_ERROR_SOURCE_BIT_MASK (0xFF)
+#define MAILBOX_ERROR_SOURCE_BIT_WIDTH (8)
+
+#define OLPDET_ERROR_SOURCE4_OFFSET (16)
+#define OLPDET_ERROR_SOURCE_BIT_MASK (0xFF)
+#define OLPDET_ERROR_SOURCE_BIT_WIDTH (8)
+
+
+//***********************
+// MPU bit
+//***********************
+#define MPU_TYPE_READ (0)
+#define MPU_TYPE_WRITE (1)
+#define MPU_TYPE_NUM (2)
+#define DSP_MPU_OFFSET (0)
+#define L1_MPU_OFFSET (2)
+#define MPU_TYPE_BIT_OFFSET (16)
+#define MPU_START_MASK (0xFFFF)
+#define MPU_RANGE_MASK (0xFFFF)
+#define MPU_TYPE_BIT_MASK (0x10000)
+
+
+
+//***********************
+// CR default value
+//***********************
+#define S2C_IRQ_STATUS_DEFAULT_VAL (0x0)
+#define S2C_IRQ_MASKED_STATUS_DEFAULT_VAL (0x0)
+#define S2C_IRQ_EN_DEFAULT_VAL (0x0)
+
+#define DSP_CORE_IDLE_DEFAULT_VAL (0x0)
+#define S2C_IRQ_IDLE_EN_DEFAULT_VAL (0x0)
+
+#define C2S_IRQ_STATUS_DEFAULT_VAL (0x0)
+#define C2S_IRQ_MASKED_STATUS_DEFAULT_VAL (0x0)
+#define C2S_IRQ_EN_DEFAULT_VAL (0x0)
+
+#define MPU_START_ADDR_DEFAULT_VAL (0x0)
+#define MPU_RANGE_DEFAULT_VAL (0x0)
+#define MPU_ERR_ADDR_DEFAULT_VAL (0xA4CF0000)
+
+#define DSM_UNDEFINED_REGION_STATUS_DEFAULT_VAL (0x0)
+#define DSR_UNDEFINED_REGION_STATUS_DEFAULT_VAL (0xA4CF0000)
+
+#define DSP_ERROR_FLAG_DEFAULT_VAL (0x0)
+#define DSP_ERROR_SNAPSHOT_DEFAULT_VAL (0x0)
+#define DSP_ERROR_EN_DEFAULT_VAL (0x07FFFFFF)
+#define DSP_ERROR_SOURCE0_DEFAULT_VAL (0xFFFFFFFF)
+#define DSP_ERROR_SOURCE1_DEFAULT_VAL (0xFFFFFFFF)
+#define DSP_ERROR_SOURCE2_DEFAULT_VAL (0xFFFFFFFF)
+#define DSP_ERROR_SOURCE3_DEFAULT_VAL (0xFFFFFFFF)
+#define DSP_ERROR_SOURCE4_DEFAULT_VAL (0x00FFFFFF)
+
+#define L1_ERROR_FLAG_DEFAULT_VAL (0x0)
+#define L1_ERROR_SNAPSHOT_DEFAULT_VAL (0x0)
+#define L1_ERROR_EN_DEFAULT_VAL (0x07FFFFFF)
+
+#define S2C_IRQ_OVFL_STATUS_DEFAULT_VAL (0x0)
+#define C2S_IRQ_OVFL_STATUS_DEFAULT_VAL (0x0)
+
+#define MAILBOX_SEND_DEFAULT_VAL (0x0)
+#define MAILBOX_RECV_DEFAULT_VAL (CSIF_MAILBOX_EMPTY_VALUE)
+#define MAILBOX_STATS_DEFAULT_VAL (0x0)
+#define MAILBOX_MAX_FIFO_USAGE_DEFAULT_VAL (0x0)
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define MAILBOX_ERROR_SUB_ENABLE_DEFAULT_VAL (0x3)
+#elif defined(MT6297)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+#define MAILBOX_ERROR_STATUS_DEFAULT_VAL (0x0)
+#define MAILBOX_ERROR_RECORD_DEFAULT_VAL (0x0)
+#define MAILBOX_DEBUG_ENABLE_DEFAULT_VAL (0x0)
+#define MAILBOX_DEBUG_READ_CONTENT_DEFAULT_VAL (MAILBOX_RECV_DEFAULT_VAL)
+#define MAILBOX_DEBUG_READ_IDX_DEFAULT_VAL (0x0)
+
+#define OLPDET_SET_DEFAULT_VAL (0x0)
+#define OLPDET_CLR_DEFAULT_VAL (0x0)
+#define OLPDET_INUSE_MAIL_SIZE_DEFAULT_VAL (0x0)
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define OLPDET_MAX_MAIL_SIZE_DEFAULT_VAL (0x0)
+#define OLPDET_ERROR_SUB_ENABLE_DEFAULT_VAL (0xF)
+#elif defined(MT6297)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+#define OLPDET_ERROR_STATUS_DEFAULT_VAL (0x0)
+#define OLPDET_SET_CANDIDATE_RECORD_DEFAULT_VAL (0x0)
+#define OLPDET_CLR_CANDIDATE_RECORD_DEFAULT_VAL (0x0)
+#define OLPDET_DEBUG_READ_MUM_DEFAULT_VAL (0x0)
+#define OLPDET_DEBUG_READ_MUM_IDX_DEFAULT_VAL (0x0)
+#define OLPDET_DEBUG_CLR_MUM_ENABLE_DEFAULT_VAL (0x0)
+
+//***********************
+// CR bit width
+//***********************
+#define S2C_IRQ_EN_WIDTH (32)
+#define C2S_IRQ_EN_WIDTH (32)
+#define MPU_START_WIDTH (16)
+#define MPU_RANGE_WIDTH (17)
+#define DSP_ERROR_EN_WIDTH (27)
+#define L1_ERROR_EN_WIDTH (27)
+#define MAILBOX_SEND_WIDTH (32)
+#define MAILBOX_ERROR_SUB_ENABLE_WIDTH (2)
+#define MAILBOX_DEBUG_ENABLE_WIDTH (1)
+#define OLPDET_SET_CLR_OFFSET_WIDTH (11)
+#define OLPDET_SET_CLR_LENGTH_WIDTH (8)
+#define OLPDET_ERROR_SUB_ENABLE_WIDTH (4)
+#define OLPDET_DEBUG_CLR_MUM_ENABLE_WIDTH (1)
+
+
+//***********************
+// RSVD CR for cross core sync
+//***********************
+#if !defined(__CSIF_SHAOLIN_64b_WORKAROUND__)
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_RSVD_0 (CSIF_DSR_BASE + 0x1D8)
+#define CSIF_RSVD_1 (CSIF_DSR_BASE + 0x1DC)
+#elif defined(MT6297)
+#define CSIF_RSVD_0 (CSIF_DSR_BASE + 0x174)
+#define CSIF_RSVD_1 (CSIF_DSR_BASE + 0x178)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+#else
+#define CSIF_RSVD_0 (CSIF_DSM_BASE + 0x2960)
+#define CSIF_RSVD_1 (CSIF_DSM_BASE + 0x2964)
+#endif
+//***********************
+// Cross core sync pattern
+//***********************
+#define CSIF_CROSS_START1_MCU (0xFF97B001)
+#define CSIF_CROSS_START1_DSP (0xFF97A001)
+
+#define CSIF_CROSS_START2_MCU (0xFF97B002)
+#define CSIF_CROSS_START2_DSP (0xFF97A002)
+
+#define CSIF_CROSS_IRQ_S2C_WAIT (0xFF97CC0A)
+#define CSIF_CROSS_IRQ_S2C_PASS (0xFF97CC0B)
+#define CSIF_CROSS_IRQ_C2S_WAIT (0xFF97DD0A)
+#define CSIF_CROSS_IRQ_C2S_PASS (0xFF97DD0B)
+
+#define CSIF_CROSS_IDLE_IRQ_TH0_SYNC (0xAF97000A)
+#define CSIF_CROSS_IDLE_IRQ_TH0_SYNC_DONE (0xAF97001A)
+#define CSIF_CROSS_IDLE_IRQ_TH1_SYNC (0xAF97000B)
+#define CSIF_CROSS_IDLE_IRQ_TH1_SYNC_DONE (0xAF97001B)
+#define CSIF_CROSS_IDLE_IRQ_TH2_SYNC (0xAF97000C)
+#define CSIF_CROSS_IDLE_IRQ_TH2_SYNC_DONE (0xAF97001C)
+#define CSIF_CROSS_IDLE_IRQ_TH3_SYNC (0xAF97000D)
+#define CSIF_CROSS_IDLE_IRQ_TH3_SYNC_DONE (0xAF97001D)
+#define CSIF_CROSS_IDLE_IRQ_CORE_SYNC (0xAF9700FF)
+
+#define CSIF_CROSS_MAILBOX_SYNC1_MCU (0xBF97B001)
+#define CSIF_CROSS_MAILBOX_SYNC1_DSP (0xBF97A001)
+#define CSIF_CROSS_MAILBOX_SYNC2_MCU (0xBF97B002)
+#define CSIF_CROSS_MAILBOX_SYNC2_DSP (0xBF97A002)
+
+//***********************
+// IRQ_Handler type
+//***********************
+#define CSIF_IRQ_HANDLER_IRQ_TEST (0x62970000)
+#define CSIF_IRQ_HANDLER_IDLE_IRQ_TEST (0x62970001)
+#define CSIF_IRQ_HANDLER_MAILBOX_TEST (0x62970002)
+
+//***********************
+// IDLE IRQ
+//***********************
+#define CSIF_IDLE_IRQ_BIT_MASK (0x3FF)
+
+//***********************
+// Memory test pattern
+//***********************
+#define MEM_TEST_PATTERN0 (0x0)
+#define MEM_TEST_PATTERN1 (0xFFFFFFFF)
+#define MEM_TEST_PATTERN2 (0xA5A5A5A5)
+#define MEM_TEST_PATTERN3 (0x5A5A5A5A)
+
+#define MEM_TEST_PATTERN1_64 (0xFFFFFFFFFFFFFFFF)
+#define MEM_TEST_PATTERN2_64 (0xA5A5A5A5A5A5A5A5)
+#define MEM_TEST_PATTERN3_64 (0x5A5A5A5A5A5A5A5A)
+
+#define MEM_TEST_PATTERN1_128 (0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
+#define MEM_TEST_PATTERN2_128 (0xA5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5)
+#define MEM_TEST_PATTERN3_128 (0x5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A)
+
+
+//***********************
+// multithread sync pattern
+//***********************
+#define TEST_THREAD_SYNC_T0 (0xFEDC0000)
+#define TEST_THREAD_SYNC_T1 (0xFEDC0001)
+#define TEST_THREAD_SYNC_T2 (0xFEDC0002)
+#define TEST_THREAD_SYNC_T3 (0xFEDC0003)
+#define TEST_THREAD_SYNC_ALL_PASS (0xFEDCABCD)
+
+
+//***********************
+// Mailbox test pattern
+//***********************
+#define MAILBOX_TEST_PATTERN0 (0xABCD0000)
+
+//***********************
+// Mailbox
+//***********************
+
+#define MAILBOX_FULL_ERROR_BIT (0)
+#define MAILBOX_CONTENT_ERROR_BIT (1)
+
+//***********************
+// OLPDET
+//***********************
+
+#define OLPDET_SET_CONTENT_ERROR_BIT (0)
+#define OLPDET_CLR_CONTENT_ERROR_BIT (1)
+#define OLPDET_OLP_HIT_ERROR_BIT (2)
+#define OLPDET_CLR_NOHIT_ERROR_BIT (3)
+
+//***********************
+// DBGC CR
+//***********************
+// csif config is at
+// /proj/d_01055/MDSYS_PLATFORM/alex01055/proj/MT6297MP/pwa/MT6297MP_000/dig/MDSYS_PLATFORM/mml1_mcoresys_irq_map/src_rtl/mml1_mcoresys_irq_map.v
+// bit[10] now
+#if !defined(__JSP__)
+#define DBGC_PRIO0_IF DR_MML1_DSPDBGC_TOP_PRIO0_IF
+#define DBGC_PRIO0_INSEN DR_MML1_DSPDBGC_TOP_PRIO0_INSEN
+#define CSIF_DBGC_BIT (7)
+#else
+#define DBGC_PRIO0_IF DR_MML1_DSPDBGC_TOP_PRIO0_IF
+#define DBGC_PRIO0_INSEN DR_MML1_DSPDBGC_TOP_PRIO0_INSEN
+#define CSIF_DBGC_BIT (15)
+#endif
+
+
+#define EXC_TEST_WAITING_CYCLE (0x6297) // delay time must long enough to wait LISR triggered and handled
+#define EXPECT_EXC_FLAG_TRUE (0xFAAAAAAA)
+#define EXPECT_EXC_FLAG_FALSE (0xFAAADDDD)
+
+#define EXPECT_ERROR_FLAG_TRUE (0xEAAAAAAA)
+#define EXPECT_ERROR_FLAG_FALSE (0xEAAADDDD)
+
+//***********************
+// Testing
+//***********************
+#define ACCESS_TYPE_READ (0x0)
+#define ACCESS_TYPE_WRITE (0x1)
+#define ACCESS_TYPE_NUM (2)
+
+#define ACCESS_REGION_DSM (0)
+#define ACCESS_REGION_DSR (1)
+
+#define LAST_CSIF_CR (DR_MML1_DSPCSIF_TOP_C2S_IRQ3_OVFL_CLR)
+
+#if defined(MT6833) || defined(MT6877)
+#define CORE_IDLE_COMPARE_MASK (0x7)
+#else
+#define CORE_IDLE_COMPARE_MASK (0xF)
+#endif
+
+#define IDLE_IRQ_ENABLE_TYPE_OR (0)
+#define IDLE_IRQ_ENABLE_TYPE_AND (1)
+
+#define EXPECT_IRQ_SET_FLAG_TRUE (0xDABCAAAA)
+#define EXPECT_IRQ_SET_FLAG_FALSE (0xDABCDDDD)
+
+#define IRQ_TEST_WAITING_CYCLE (100)
+
+#if !defined(__MIPS_I7200__)
+#define SSDVT_FAIL_MSG(a, b, c) ssdvt_test_fail_info_notification(a, b, c)
+#define SSDVT_PASS() ssdvt_test_pass_one_thread_notification()
+#define SSDVT_LOG(a, b, c)
+#else
+//#define SSDVT_FAIL_MSG(a, b, c) printf("!!<-[TEST FAIL]->!! code0:%x, code1:%x, code2:%x\n",a,b,c)
+//#define SSDVT_FAIL_MSG(a, b, c) printf("!!<-[TEST FAIL]->!! code0:%x, code1:%x, code2:%x\n",a,b,c);while(1)
+//#define SSDVT_PASS() printf("!!<-[TEST PASS!]->!!");while(1)
+//#define SSDVT_LOG(a, b, c) printf("[Log]: code0:%x, code1:%x, code2:%x\n",a,b,c)
+#define SSDVT_FAIL_MSG(a, b, c) FAIL_MSG[0]=a;FAIL_MSG[1]=b;FAIL_MSG[2]=c;while(1)
+#define SSDVT_PASS() while(1)
+#define SSDVT_LOG(a, b, c)
+#endif
+
+
+#define OLPDET_TEST_REGION_A (0)
+#define OLPDET_TEST_REGION_B (1)
+#define OLPDET_TEST_REGION_C (2)
+#define OLPDET_TEST_REGION_TOTAL (3)
+
+#define OLPDET_TEST_REGION_A_START_ADDR (0)
+#define OLPDET_TEST_REGION_B_START_ADDR (1024)
+#define OLPDET_TEST_REGION_C_START_ADDR (1920)
+#define OLPDET_TEST_REGION_LENGTH (128)
+
+
+kal_bool TEST_REGION_POINT_ARRAY[OLPDET_TEST_REGION_TOTAL][7] = {
+ {KAL_FALSE, KAL_FALSE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE},
+ {KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE},
+ {KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_FALSE}
+};
+
+#define OLPDET_TEST_POINT_LENGTH (2)
+#define MAILBOX_TEST_PREFIX_PATTERN (0x62970000)
+
+#define MCORE_ID_MCORE0 (0)
+#define MCORE_ID_MCORE1 (1)
+
+#define CSIF_REG_WRITE_DELAY(addr, data) DRV_WriteReg32_Device(addr, data); \
+ DRV_Memory_Barrier_Write();
+
+#define MULTIPLE_REG_TEST_NUM 5
+#define MULTIPLE_REG_TEST_NUM_SUB_1 2
+#define MULTIPLE_REG_TEST_NUM_SUB_2 (MULTIPLE_REG_TEST_NUM - MULTIPLE_REG_TEST_NUM_SUB_1)
+kal_uint32 MULTIPLE_REG_TEST_OFFSET[MULTIPLE_REG_TEST_NUM] = {0, 0x800, 0x1000, 0x2000, 0x3FE0};
+kal_uint32 MULTIPLE_REG_TEST_SIZE[MULTIPLE_REG_TEST_NUM] = {0x400, 0x100, 0x8, 0x200, 0x20};
+
+#define MULTIPLE_MAIL_TEST_NUM 8
+#define MULTIPLE_IRQ_TEST_NUM 16
diff --git a/mcu/driver/devdrv/csif/mt6297/inc/drv_csif.h b/mcu/driver/devdrv/csif/mt6297/inc/drv_csif.h
new file mode 100644
index 0000000..d18a769
--- /dev/null
+++ b/mcu/driver/devdrv/csif/mt6297/inc/drv_csif.h
@@ -0,0 +1,534 @@
+#ifndef __DRV_CSIF_H__
+#define __DRV_CSIF_H__
+
+#include "csif_l1core_public_api.h"
+
+#include "intrCtrl.h"
+#include "kal_public_api.h"
+#include "kal_general_types.h"
+
+#include "sync_data.h"
+#include "drv_comm.h"
+#include "reg_base.h"
+
+#define __CSIF_DEBUG__
+
+/*******************************************************************************
+ * CSIF CR Definition
+ *******************************************************************************/
+
+// temp define for compiling test
+
+#define CSIF_BANK_A_BASE (BASE_MADDR_MCOREPERI_INFRA_CSIF)
+#define CSIF_BANK_B_BASE (BASE_NADDR_MCOREPERI_INFRA_CSIF)
+
+#define CSIF_DSR_BASE (CSIF_BANK_A_BASE)
+#define CSIF_DSM_BASE (CSIF_BANK_A_BASE + 0x2000)
+#define CSIF_DSR_SIZE (0x400) //1KB
+#define CSIF_DSM_SIZE (16384) //16KB
+
+
+/* Control Register Addr and Offset */
+#define CSIF_S2C_IRQ_CR_BASE (CSIF_DSR_BASE + 0x0)
+#define CSIF_S2C_IRQ_CLR_OFFSET (0x0)
+#define CSIF_S2C_IRQ_STATUS_OFFSET (0x4)
+#define CSIF_S2C_IRQ_MASKED_STATUS_OFFSET (0x8)
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_S2C_IRQ_ENABLE_SET_OFFSET (0xC)
+#define CSIF_S2C_IRQ_ENABLE_CLR_OFFSET (0x10)
+#define CSIF_S2C_IRQ_ENABLE_OFFSET (0x14)
+#elif defined(MT6297)
+#define CSIF_S2C_IRQ_ENABLE_OFFSET (0xC)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_CORE_IDLE (CSIF_DSR_BASE + 0xC0)
+#define CSIF_S2C_IDLE_IRQ_CR_BASE (CSIF_DSR_BASE + 0xC4)
+#elif defined(MT6297)
+#define CSIF_CORE_IDLE (CSIF_DSR_BASE + 0x60)
+#define CSIF_S2C_IDLE_IRQ_CR_BASE (CSIF_DSR_BASE + 0x64)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+#define CSIF_S2C_IDLE_IRQ_ENABLE_OFFSET (0x0)
+#define CSIF_S2C_IDLE_IRQ_ENABLE_SET_OFFSET (0x4)
+#define CSIF_S2C_IDLE_IRQ_ENABLE_CLR_OFFSET (0x8)
+
+#define CSIF_S2C_IDLE_ENABLE_MCORE0_BIT (0U)
+#define CSIF_S2C_IDLE_ENABLE_MCORE1_BIT (4U)
+#define CSIF_S2C_IDLE_ENABLE_MCORE0_AND_OR_BIT (8U)
+#define CSIF_S2C_IDLE_ENABLE_MCORE1_AND_OR_BIT (9U)
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_C2S_IRQ_CR_BASE (CSIF_DSR_BASE + 0xE0)
+#elif defined(MT6297)
+#define CSIF_C2S_IRQ_CR_BASE (CSIF_DSR_BASE + 0x80)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+#define CSIF_C2S_IRQ_SET_OFFSET (0x0)
+#define CSIF_C2S_IRQ_STATUS_OFFSET (0x4)
+#define CSIF_C2S_IRQ_MASKED_STATUS_OFFSET (0x8)
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_MPU_CR_BASE (CSIF_DSR_BASE + 0x160)
+#elif defined(MT6297)
+#define CSIF_MPU_CR_BASE (CSIF_DSR_BASE + 0xC0)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+#define CSIF_MPU_START_ADDR_OFFSET (0x0)
+#define CSIF_MPU_RANGE_OFFSET (0x4)
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_MPU_ERR_CR_BASE (CSIF_DSR_BASE + 0x180)
+#elif defined(MT6297)
+#define CSIF_MPU_ERR_CR_BASE (CSIF_DSR_BASE + 0xE0)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+#define CSIF_MPU_ERR_ADDR_OFFSET (0x0)
+#define CSIF_MPU_ERR_CLR_OFFSET (0x4)
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_MPU_CFG_ERR_CLR_DSP_CR_BASE (CSIF_DSR_BASE + 0x190)
+#define CSIF_MPU_CFG_ERR_CLR_L1_CR_BASE (CSIF_DSR_BASE + 0x198)
+#elif defined(MT6297)
+#define CSIF_MPU_CFG_ERR_CLR_DSP_CR_BASE (CSIF_DSR_BASE + 0xF0)
+#define CSIF_MPU_CFG_ERR_CLR_L1_CR_BASE (CSIF_DSR_BASE + 0xF8)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+#define CSIF_MPU_CFG_ERR_CLR_OFFSET (0x0)
+
+#define CSIF_MPU_CHANNEL_NUM_DSP (2)
+#define CSIF_MPU_CHANNEL_NUM_L1 (2)
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_DSM_WRITE_UNDEFINED_ERR_STATUS_CR (CSIF_DSR_BASE + 0x1A0)
+#define CSIF_DSM_WRITE_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x1A4)
+#define CSIF_DSM_READ_UNDEFINED_ERR_STATUS_CR (CSIF_DSR_BASE + 0x1A8)
+#define CSIF_DSM_READ_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x1AC)
+#define CSIF_DSR_WRITE_UNDEFINED_ERR_ADDR_CR (CSIF_DSR_BASE + 0x1B0)
+#define CSIF_DSR_WRITE_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x1B4)
+#define CSIF_DSR_READ_UNDEFINED_ERR_ADDR_CR (CSIF_DSR_BASE + 0x1B8)
+#define CSIF_DSR_READ_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x1BC)
+
+#define CSIF_L1_ERROR_FLAG_CR (CSIF_DSR_BASE + 0x1C0)
+#define CSIF_L1_ERROR_SNAPSHOT_CR (CSIF_DSR_BASE + 0x1C4)
+#define CSIF_L1_ERROR_ENABLE_CR (CSIF_DSR_BASE + 0x1CC)
+#elif defined(MT6297)
+#define CSIF_DSM_WRITE_UNDEFINED_ERR_STATUS_CR (CSIF_DSR_BASE + 0x100)
+#define CSIF_DSM_WRITE_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x104)
+#define CSIF_DSM_READ_UNDEFINED_ERR_STATUS_CR (CSIF_DSR_BASE + 0x108)
+#define CSIF_DSM_READ_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x10C)
+#define CSIF_DSR_WRITE_UNDEFINED_ERR_ADDR_CR (CSIF_DSR_BASE + 0x110)
+#define CSIF_DSR_WRITE_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x114)
+#define CSIF_DSR_READ_UNDEFINED_ERR_ADDR_CR (CSIF_DSR_BASE + 0x118)
+#define CSIF_DSR_READ_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x11C)
+
+#define CSIF_L1_ERROR_FLAG_CR (CSIF_DSR_BASE + 0x140)
+#define CSIF_L1_ERROR_SNAPSHOT_CR (CSIF_DSR_BASE + 0x144)
+#define CSIF_L1_ERROR_ENABLE_CR (CSIF_DSR_BASE + 0x160)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+
+// Disable s2c/c2s irq ovfl error to use SW to control
+#define CSIF_L1_ERROR_MASK (0x7FFFC00)
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_L1_MPU_CFG_ENABLE_CR (CSIF_DSR_BASE + 0x1D0)
+#define CSIF_L1_OVFL_CLR_CFG_ENABLE_CR (CSIF_DSR_BASE + 0x1D4)
+#elif defined(MT6297)
+#define CSIF_L1_MPU_CFG_ENABLE_CR (CSIF_DSR_BASE + 0x164)
+#define CSIF_L1_OVFL_CLR_CFG_ENABLE_CR (CSIF_DSR_BASE + 0x168)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_S2C_IRQ_OVFL_CR_BASE (CSIF_DSR_BASE + 0x210)
+#elif defined(MT6297)
+#define CSIF_S2C_IRQ_OVFL_CR_BASE (CSIF_DSR_BASE + 0x180)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+#define CSIF_S2C_IRQ_OVFL_STATUS_OFFSET (0x0)
+#define CSIF_S2C_IRQ_OVFL_CLR_OFFSET (0x4)
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_C2S_IRQ_OVFL_CR_BASE (CSIF_DSR_BASE + 0x240)
+#elif defined(MT6297)
+#define CSIF_C2S_IRQ_OVFL_CR_BASE (CSIF_DSR_BASE + 0x1C0)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+#define CSIF_C2S_IRQ_OVFL_STATUS_OFFSET (0x0)
+#define CSIF_C2S_IRQ_OVFL_CLR_OFFSET (0x4)
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_MAILBOX_CR_BASE (CSIF_DSR_BASE + 0x260)
+#define CSIF_MAILBOX_SEND_OFFSET (0x0)
+#define CSIF_MAILBOX_RECV_OFFSET (0x4)
+#define CSIF_MAILBOX_STATUS_OFFSET (0x8)
+#define CSIF_MAILBOX_MAX_FIFO_USAGE_OFFSET (0xC)
+#define CSIF_MAILBOX_ERROR_SUB_ENABLE_OFFSET (0x10)
+#define CSIF_MAILBOX_ERROR_STATUS_OFFSET (0x14)
+#define CSIF_MAILBOX_ERROR_RECORD_OFFSET (0x18)
+#define CSIF_MAILBOX_CLR_ERROR_OFFSET (0x1C)
+#define CSIF_MAILBOX_DEBUG_ENABLE_OFFSET (0x20)
+#define CSIF_MAILBOX_DEBUG_READ_CONTENT_OFFSET (0x24)
+#define CSIF_MAILBOX_DEBUG_READ_IDX_OFFSET (0x28)
+#elif defined(MT6297)
+#define CSIF_MAILBOX_CR_BASE (CSIF_DSR_BASE + 0x200)
+#define CSIF_MAILBOX_SEND_OFFSET (0x0)
+#define CSIF_MAILBOX_RECV_OFFSET (0x4)
+#define CSIF_MAILBOX_STATUS_OFFSET (0x8)
+#define CSIF_MAILBOX_MAX_FIFO_USAGE_OFFSET (0xC)
+#define CSIF_MAILBOX_ERROR_STATUS_OFFSET (0x10)
+#define CSIF_MAILBOX_ERROR_RECORD_OFFSET (0x14)
+#define CSIF_MAILBOX_CLR_ERROR_OFFSET (0x18)
+#define CSIF_MAILBOX_DEBUG_ENABLE_OFFSET (0x1C)
+#define CSIF_MAILBOX_DEBUG_READ_CONTENT_OFFSET (0x20)
+#define CSIF_MAILBOX_DEBUG_READ_IDX_OFFSET (0x24)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_OLPDET_CR_BASE (CSIF_DSR_BASE + 0x380)
+#define CSIF_OLPDET_SET_OFFSET (0x0)
+#define CSIF_OLPDET_CLR_OFFSET (0x4)
+#define CSIF_OLPDET_INUSE_MAIL_SIZE_OFFSET (0x8)
+#define CSIF_OLPDET_MAX_MAIL_SIZE_OFFSET (0xC)
+#define CSIF_OLPDET_MAX_MAIL_SIZE_CLR_OFFSET (0x10)
+#define CSIF_OLPDET_ERROR_SUB_ENABLE_OFFSET (0x14)
+#define CSIF_OLPDET_ERROR_STATUS_OFFSET (0x18)
+#define CSIF_OLPDET_SET_CANDIDATE_RECORD_OFFSET (0x1C)
+#define CSIF_OLPDET_CLR_CANDIDATE_RECORD_OFFSET (0x20)
+#define CSIF_OLPDET_CLR_ERROR_OFFSET (0x24)
+#define CSIF_OLPDET_DEBUG_READ_MUM_OFFSET (0x28)
+#define CSIF_OLPDET_DEBUG_READ_MUM_IDX_OFFSET (0x2C)
+#define CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE_OFFSET (0x30)
+#elif defined(MT6297)
+#define CSIF_OLPDET_CR_BASE (CSIF_DSR_BASE + 0x380)
+#define CSIF_OLPDET_SET_OFFSET (0x0)
+#define CSIF_OLPDET_CLR_OFFSET (0x4)
+#define CSIF_OLPDET_INUSE_MAIL_SIZE_OFFSET (0x8)
+#define CSIF_OLPDET_ERROR_STATUS_OFFSET (0xC)
+#define CSIF_OLPDET_SET_CANDIDATE_RECORD_OFFSET (0x10)
+#define CSIF_OLPDET_CLR_CANDIDATE_RECORD_OFFSET (0x14)
+#define CSIF_OLPDET_CLR_ERROR_OFFSET (0x18)
+#define CSIF_OLPDET_DEBUG_READ_MUM_OFFSET (0x1C)
+#define CSIF_OLPDET_DEBUG_READ_MUM_IDX_OFFSET (0x20)
+#define CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE_OFFSET (0x24)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+
+// ************************
+// For using CR
+// ************************
+#define CSIF_S2C_IRQ_CLR (CSIF_S2C_IRQ_CR_BASE + CSIF_S2C_IRQ_CLR_OFFSET)
+#define CSIF_S2C_IRQ_STATUS (CSIF_S2C_IRQ_CR_BASE + CSIF_S2C_IRQ_STATUS_OFFSET)
+#define CSIF_S2C_IRQ_MASKED_STATUS (CSIF_S2C_IRQ_CR_BASE + CSIF_S2C_IRQ_MASKED_STATUS_OFFSET)
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_S2C_IRQ_ENABLE_SET (CSIF_S2C_IRQ_CR_BASE + CSIF_S2C_IRQ_ENABLE_SET_OFFSET)
+#define CSIF_S2C_IRQ_ENABLE_CLR (CSIF_S2C_IRQ_CR_BASE + CSIF_S2C_IRQ_ENABLE_CLR_OFFSET)
+#elif defined(MT6297)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+#define CSIF_S2C_IRQ_ENABLE (CSIF_S2C_IRQ_CR_BASE + CSIF_S2C_IRQ_ENABLE_OFFSET)
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_S2C_IRQ_SIZE (0x20)
+#elif defined(MT6297)
+#define CSIF_S2C_IRQ_SIZE (CSIF_S2C_IRQ_ENABLE_OFFSET - CSIF_S2C_IRQ_CLR_OFFSET + 4)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+
+#define CSIF_S2C_IDLE_IRQ_ENABLE (CSIF_S2C_IDLE_IRQ_CR_BASE + CSIF_S2C_IDLE_IRQ_ENABLE_OFFSET)
+#define CSIF_S2C_IDLE_IRQ_ENABLE_SET (CSIF_S2C_IDLE_IRQ_CR_BASE + CSIF_S2C_IDLE_IRQ_ENABLE_SET_OFFSET)
+#define CSIF_S2C_IDLE_IRQ_ENABLE_CLR (CSIF_S2C_IDLE_IRQ_CR_BASE + CSIF_S2C_IDLE_IRQ_ENABLE_CLR_OFFSET)
+#define CSIF_S2C_IDLE_IRQ_ENABLE_SIZE (CSIF_S2C_IDLE_IRQ_ENABLE_CLR_OFFSET - CSIF_S2C_IDLE_IRQ_ENABLE_OFFSET + 4)
+
+#define CSIF_S2C_IDLE_IRQ_NUM (2)
+
+#define CSIF_C2S_IRQ_SET (CSIF_C2S_IRQ_CR_BASE + CSIF_C2S_IRQ_SET_OFFSET)
+#define CSIF_C2S_IRQ_STATUS (CSIF_C2S_IRQ_CR_BASE + CSIF_C2S_IRQ_STATUS_OFFSET)
+#define CSIF_C2S_IRQ_MASKED_STATUS (CSIF_C2S_IRQ_CR_BASE + CSIF_C2S_IRQ_MASKED_STATUS_OFFSET)
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_C2S_IRQ_SIZE (0x20)
+#elif defined(MT6297)
+#define CSIF_C2S_IRQ_SIZE (CSIF_C2S_IRQ_MASKED_STATUS_OFFSET - CSIF_C2S_IRQ_SET_OFFSET + 4)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+
+#define CSIF_MPU_START_ADDR (CSIF_MPU_CR_BASE + CSIF_MPU_START_ADDR_OFFSET)
+#define CSIF_MPU_RANGE (CSIF_MPU_CR_BASE + CSIF_MPU_RANGE_OFFSET)
+#define CSIF_MPU_SIZE (CSIF_MPU_RANGE_OFFSET - CSIF_MPU_START_ADDR_OFFSET + 4)
+
+#define CSIF_MPU_TYPE_M (0x10000)
+#define CSIF_MPU_TYPE_P (16U)
+
+#define CSIF_MPU_START_M (0xFFFF)
+#define CSIF_MPU_START_P (0U)
+
+#define CSIF_MPU_RANGE_M (0xFFFF)
+#define CSIF_MPU_RANGE_P (0U)
+
+#define CSIF_MPU_ERR_ADDR (CSIF_MPU_ERR_CR_BASE + CSIF_MPU_ERR_ADDR_OFFSET)
+#define CSIF_MPU_ERR_CLR (CSIF_MPU_ERR_CR_BASE + CSIF_MPU_ERR_CLR_OFFSET)
+#define CSIF_MPU_ERR_SIZE (CSIF_MPU_ERR_CLR_OFFSET - CSIF_MPU_ERR_ADDR_OFFSET + 4)
+
+#define CSIF_MPU_CFG_ERR_CLR_DSP (CSIF_MPU_CFG_ERR_CLR_DSP_CR_BASE + CSIF_MPU_CFG_ERR_CLR_OFFSET)
+#define CSIF_MPU_CFG_ERR_CLR_L1 (CSIF_MPU_CFG_ERR_CLR_L1_CR_BASE + CSIF_MPU_CFG_ERR_CLR_OFFSET)
+#define CSIF_MPU_CFG_ERR_CLR_SIZE (CSIF_MPU_CFG_ERR_CLR_OFFSET - CSIF_MPU_CFG_ERR_CLR_OFFSET + 4)
+
+#define CSIF_S2C_IRQ_OVFL_STATUS (CSIF_S2C_IRQ_OVFL_CR_BASE + CSIF_S2C_IRQ_OVFL_STATUS_OFFSET)
+#define CSIF_S2C_IRQ_OVFL_CLR (CSIF_S2C_IRQ_OVFL_CR_BASE + CSIF_S2C_IRQ_OVFL_CLR_OFFSET)
+#define CSIF_S2C_IRQ_OVFL_SIZE (CSIF_S2C_IRQ_OVFL_CLR_OFFSET - CSIF_S2C_IRQ_OVFL_STATUS_OFFSET + 4)
+
+#define CSIF_C2S_IRQ_OVFL_STATUS (CSIF_C2S_IRQ_OVFL_CR_BASE + CSIF_C2S_IRQ_OVFL_STATUS_OFFSET)
+#define CSIF_C2S_IRQ_OVFL_CLR (CSIF_C2S_IRQ_OVFL_CR_BASE + CSIF_C2S_IRQ_OVFL_CLR_OFFSET)
+#define CSIF_C2S_IRQ_OVFL_SIZE (CSIF_C2S_IRQ_OVFL_CLR_OFFSET - CSIF_C2S_IRQ_OVFL_STATUS_OFFSET + 4)
+
+#define CSIF_MAILBOX_SEND (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_SEND_OFFSET)
+#define CSIF_MAILBOX_RECV (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_RECV_OFFSET)
+#define CSIF_MAILBOX_STATUS (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_STATUS_OFFSET)
+#define CSIF_MAILBOX_MAX_FIFO_USAGE (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_MAX_FIFO_USAGE_OFFSET)
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_MAILBOX_ERROR_SUB_ENABLE (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_ERROR_SUB_ENABLE_OFFSET)
+#elif defined(MT6297)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+#define CSIF_MAILBOX_ERROR_STATUS (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_ERROR_STATUS_OFFSET)
+#define CSIF_MAILBOX_ERROR_RECORD (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_ERROR_RECORD_OFFSET)
+#define CSIF_MAILBOX_CLR_ERROR (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_CLR_ERROR_OFFSET)
+#define CSIF_MAILBOX_DEBUG_ENABLE (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_DEBUG_ENABLE_OFFSET)
+#define CSIF_MAILBOX_DEBUG_READ_CONTENT (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_DEBUG_READ_CONTENT_OFFSET)
+#define CSIF_MAILBOX_DEBUG_READ_IDX (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_DEBUG_READ_IDX_OFFSET)
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_MAILBOX_SIZE (0x30)
+#elif defined(MT6297)
+#define CSIF_MAILBOX_SIZE (0x40)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+
+#define CSIF_MAILBOX_256_STATUS_R_IDX_M (0x1FF)
+#define CSIF_MAILBOX_256_STATUS_R_IDX_P (0U)
+#define CSIF_MAILBOX_256_STATUS_W_IDX_M (0x3FE00)
+#define CSIF_MAILBOX_256_STATUS_W_IDX_P (9U)
+#define CSIF_MAILBOX_256_STATUS_MAIL_NUM_M (0x7FC0000)
+#define CSIF_MAILBOX_256_STATUS_MAIL_NUM_P (18U)
+
+#define CSIF_MAILBOX_64_STATUS_R_IDX_M (0xFF)
+#define CSIF_MAILBOX_64_STATUS_R_IDX_P (0U)
+#define CSIF_MAILBOX_64_STATUS_W_IDX_M (0xFF00)
+#define CSIF_MAILBOX_64_STATUS_W_IDX_P (8U)
+#define CSIF_MAILBOX_64_STATUS_MAIL_NUM_M (0xFF0000)
+#define CSIF_MAILBOX_64_STATUS_MAIL_NUM_P (16U)
+
+#define MAILBOX_256_WRAP_MASK (0xFF)
+#define MAILBOX_64_WRAP_MASK (0x3F)
+
+#define CSIF_OLPDET_SET (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_SET_OFFSET )
+#define CSIF_OLPDET_CLR (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_CLR_OFFSET )
+#define CSIF_OLPDET_INUSE_MAIL_SIZE (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_INUSE_MAIL_SIZE_OFFSET )
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_OLPDET_MAX_MAIL_SIZE (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_MAX_MAIL_SIZE_OFFSET )
+#define CSIF_OLPDET_MAX_MAIL_SIZE_CLR (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_MAX_MAIL_SIZE_CLR_OFFSET )
+#define CSIF_OLPDET_ERROR_SUB_ENABLE (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_ERROR_SUB_ENABLE_OFFSET )
+#elif defined(MT6297)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+#define CSIF_OLPDET_ERROR_STATUS (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_ERROR_STATUS_OFFSET )
+#define CSIF_OLPDET_SET_CANDIDATE_RECORD (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_SET_CANDIDATE_RECORD_OFFSET)
+#define CSIF_OLPDET_CLR_CANDIDATE_RECORD (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_CLR_CANDIDATE_RECORD_OFFSET)
+#define CSIF_OLPDET_CLR_ERROR (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_CLR_ERROR_OFFSET )
+#define CSIF_OLPDET_DEBUG_READ_MUM (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_DEBUG_READ_MUM_OFFSET )
+#define CSIF_OLPDET_DEBUG_READ_MUM_IDX (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_DEBUG_READ_MUM_IDX_OFFSET )
+#define CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE_OFFSET)
+#define CSIF_OLPDET_SIZE (CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE_OFFSET - CSIF_OLPDET_SET_OFFSET + 4)
+
+#define CSIF_OLPDET_SET_OFFSET_M (0x7FF)
+#define CSIF_OLPDET_SET_OFFSET_P (0U)
+#define CSIF_OLPDET_SET_LENGTH_M (0xFF0000)
+#define CSIF_OLPDET_SET_LENGTH_P (16U)
+
+#define CSIF_OLPDET_CLR_OFFSET_M (0x7FF)
+#define CSIF_OLPDET_CLR_OFFSET_P (0U)
+#define CSIF_OLPDET_CLR_LENGTH_M (0xFF0000)
+#define CSIF_OLPDET_CLR_LENGTH_P (16U)
+
+#define CSIF_OLPDET_SET_CONTENT_ERROR_M (0x1)
+#define CSIF_OLPDET_SET_CONTENT_ERROR_P (0)
+#define CSIF_OLPDET_CLR_CONTENT_ERROR_M (0x2)
+#define CSIF_OLPDET_CLR_CONTENT_ERROR_P (1)
+#define CSIF_OLPDET_OLP_HIT_ERROR_M (0x4)
+#define CSIF_OLPDET_OLP_HIT_ERROR_P (2)
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#define CSIF_OLPDET_CLR_NOHIT_ERROR_M (0x8)
+#define CSIF_OLPDET_CLR_NOHIT_ERROR_P (3)
+#elif defined(MT6297)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+
+#define CSIF_S2C_IRQ0_OVFL_ERR_P (0)
+#define CSIF_S2C_IRQ1_OVFL_ERR_P (1)
+#define CSIF_S2C_IRQ2_OVFL_ERR_P (2)
+#define CSIF_S2C_IRQ3_OVFL_ERR_P (3)
+#define CSIF_S2C_IRQ4_OVFL_ERR_P (4)
+#define CSIF_S2C_IRQ5_OVFL_ERR_P (5)
+#define CSIF_C2S_IRQ0_OVFL_ERR_P (6)
+#define CSIF_C2S_IRQ1_OVFL_ERR_P (7)
+#define CSIF_C2S_IRQ2_OVFL_ERR_P (8)
+#define CSIF_C2S_IRQ3_OVFL_ERR_P (9)
+#define CSIF_L1_MPU0_ERR_P (10)
+#define CSIF_L1_MPU1_ERR_P (11)
+#define CSIF_L1_DSM_W_UNDEF_REG_ERR_P (12)
+#define CSIF_L1_DSM_R_UNDEF_REG_ERR_P (13)
+#define CSIF_L1_DSR_W_UNDEF_REG_ERR_P (14)
+#define CSIF_L1_DSR_R_UNDEF_REG_ERR_P (15)
+#define CSIF_DSP_MPU0_CFG_ERR_P (16)
+#define CSIF_DSP_MPU1_CFG_ERR_P (17)
+#define CSIF_L1_MPU0_CFG_ERR_P (18)
+#define CSIF_L1_MPU1_CFG_ERR_P (19)
+#define CSIF_MAILBOX0_ERR_P (20)
+#define CSIF_MAILBOX1_ERR_P (21)
+#define CSIF_MAILBOX2_ERR_P (22)
+#define CSIF_MAILBOX3_ERR_P (23)
+#define CSIF_MAILBOX4_ERR_P (24)
+#define CSIF_MAILBOX5_ERR_P (25)
+#define CSIF_OLPDET_ERR_P (26)
+
+/******************************************************************************
+ * Macros
+ *******************************************************************************/
+
+/* C2S */
+#define CSIF_C2S_IRQ_CR_BASE_PTR ((volatile csif_uint32*)(CSIF_C2S_IRQ_CR_BASE))
+#define CSIF_C2S_IRQ_CLR_PTR ((volatile csif_uint32*)(CSIF_C2S_IRQ_CLR))
+#define CSIF_C2S_IRQ_STATUS_PTR ((volatile csif_uint32*)(CSIF_C2S_IRQ_STATUS))
+#define CSIF_C2S_IRQ_MASKED_STATUS_PTR ((volatile csif_uint32*)(CSIF_C2S_IRQ_MASKED_STATUS))
+#define CSIF_C2S_IRQ_ENABLE_PTR ((volatile csif_uint32*)(CSIF_C2S_IRQ_ENABLE))
+
+
+#define CSIF_TRUE KAL_TRUE
+#define CSIF_FALSE KAL_FALSE
+
+/* Read/Write macros */
+#define BANK_MASK (0x0FFFFFFF)
+#define BANK_B_PREFIX (0xB0000000)
+#define CSIF_REG_READ(addr, data) data=(*(volatile kal_uint32 *)(addr))
+#define CSIF_REG_WRITE(addr, data) do{DRV_WriteReg32(addr, data); MO_Sync();}while(0);
+#define CSIF_REG_WRITE_BANKB(addr, data) DRV_WriteReg32(((addr & BANK_MASK) | BANK_B_PREFIX), data);
+#define CSIF_NULL NULL
+#if defined(__CSIF_DRV_TEST__)
+ #include <stdio.h>
+ #define CSIF_ASSERT(expr, e1, e2, e3) if((expr) == 0){ASSERT_MSG[0]=e1;ASSERT_MSG[1]=e2;ASSERT_MSG[2]=e3;}
+#else
+ #define CSIF_ASSERT(expr, e1, e2, e3) EXT_ASSERT(expr, e1, e2, e3)
+#endif
+#define CSIF_GET_RETURN_ADDRESS(data) GET_RETURN_ADDRESS(data)
+#define CSIF_HANDLER(nID) \
+csif_InterruptHandlerInternal( \
+ (volatile csif_uint32*)(CSIF_S2C_IRQ_CLR + CSIF_S2C_IRQ_SIZE*nID), \
+ (volatile csif_uint32*)(CSIF_S2C_IRQ_STATUS + CSIF_S2C_IRQ_SIZE*nID), \
+ (volatile csif_uint32*)(CSIF_S2C_IRQ_MASKED_STATUS + CSIF_S2C_IRQ_SIZE*nID), \
+ (volatile csif_uint32*)(CSIF_S2C_IRQ_ENABLE + CSIF_S2C_IRQ_SIZE*nID), \
+ nID, \
+ csif_s2c_isr_handler[nID])
+
+#define CSIF_MAILBOX_EMPTY_VALUE (0xFFFFFFFF)
+#define CSIF_MAILBOX_ERROR_VALUE (0xEFFFFFFF)
+
+#define CSIF_OLPDET_UNIT (8) // 1 bit in OLPDET is 8 Bytes(2 words)
+#define CSIF_OLPDET_UNIT_MASK (0x7) // 1 bit in OLPDET is 8 Bytes(2 words)
+
+#define CSIF_DSM_MASK (0x00003FFF)//16KB
+/*******************************************************************************
+ * Debug feature
+ *******************************************************************************/
+#if defined(__CSIF_DEBUG__)
+
+#define CSIF_DEBUG_API_RECORD_SIZE (64)
+#define CSIF_DEBUG_MULTI_API_RECORD_SIZE (32)
+#define CSIF_DEBUG_ISR_HANDLE_CODE_SIZE (16)
+
+#define SHAOLIN_CORE_NUM (4)
+#define SHAOLIN_VPE_NUM (3)
+
+#if defined(MT6833) || defined(MT6877)
+#define MCORE_TH_NUM (3)
+#else
+#define MCORE_TH_NUM (4)
+#endif
+#define MCORE_CORE_NUM (2)
+
+#if defined(MT6297) // for Apollo OLPDET workaround
+#define D2D_DEBUG_RECORD_PREFIX (0xD0000000)
+#endif
+
+typedef struct {
+ csif_uint32 time;
+ csif_uint32 code;
+} CSIF_DebugISRRecord;
+
+/** The Ring Buffer */
+typedef struct {
+ CSIF_DebugISRRecord records[CSIF_DEBUG_ISR_HANDLE_CODE_SIZE];
+ csif_uint32 top_index;
+} CSIF_DebugISRCodeList;
+
+typedef struct {
+ csif_uint32 time;
+ csif_uint32 status;
+ csif_uint32 set_addr; /**< The control register address */
+ csif_uint32 set_value; /**< The writing value for the control regsiters */
+ csif_uint32 caller; /**< The caller address */
+} CSIF_DebugRecord;
+
+typedef struct {
+ csif_uint32 time;
+ csif_uint32 set_addr; /**< The control register address */
+ csif_uint32 set_value; /**< The writing value for the control regsiters */
+ csif_uint32 caller; /**< The caller address */
+ csif_uint32 multiIdx; /**< the index that multiple API called */
+} CSIF_MultiOperation_DebugRecord;
+
+/** The Ring Buffer */
+typedef struct {
+ CSIF_DebugRecord records[CSIF_DEBUG_API_RECORD_SIZE];
+ kal_atomic_uint32 top_index;
+} CSIF_DebugRecordList;
+
+typedef struct {
+ CSIF_MultiOperation_DebugRecord records[CSIF_DEBUG_MULTI_API_RECORD_SIZE];
+ kal_atomic_uint32 top_index;
+} CSIF_MultiOperationDebugRecordList;
+
+void csif_DebugAddRecord(csif_uint32 status,
+ volatile csif_uint32* set_addr,
+ csif_uint32 set_value,
+ csif_uint32 caller);
+
+void csif_MultiDebugAddRecord(csif_uint32 multiIdx,
+ volatile csif_uint32* set_addr,
+ csif_uint32 set_value,
+ csif_uint32 caller);
+
+void csif_DebugAddISRHandlerCode(CSIF_S2C_INDEX nID, csif_uint32 code);
+
+#endif /* __CSIF_DEBUG__ */
+
+#endif /* __DRV_CSIF_H__ */
diff --git a/mcu/driver/devdrv/csif/mt6297/src/csif_dvt_main.c b/mcu/driver/devdrv/csif/mt6297/src/csif_dvt_main.c
new file mode 100644
index 0000000..94f5ac0
--- /dev/null
+++ b/mcu/driver/devdrv/csif/mt6297/src/csif_dvt_main.c
@@ -0,0 +1,2833 @@
+#include "drv_csif.h"
+#include "kal_hrt_api.h"
+#include "csif_l1core_public_api.h"
+#include "csif_SSDVT.h"
+
+volatile csif_uint32 test_case_index = 0;
+volatile csif_uint32 IRQ_HANDLER_TYPE = 0;
+volatile csif_uint32 _mcore_testing_thread = 0;
+csif_uint32 THIS_MCORE_ID = 0;
+
+volatile csif_uint32 _mcuInternalSyncPattern = 0;
+
+volatile csif_uint32 FAIL_MSG[3];
+#if defined(__CSIF_DRV_TEST__)
+volatile csif_uint32 _errCount = 0;
+volatile CSIF_ID_STATUS_t errStatusStruct[26];
+#endif
+
+/*******************************************************************************
+ * Macros
+ *******************************************************************************/
+/* e.g. GET_S2C_IRQ_LIMIT_NUMBER(0) => CSIF_S2C_N0_TOTAL_NUMBER */
+#define POSTFIX(nID, pos) nID##pos
+#define PREFIX(nID, pre) POSTFIX(pre##nID, _TOTAL_NUMBER)
+#define GET_S2C_IRQ_LIMIT_NUMBER(nID) PREFIX(nID, CSIF_S2C_N)
+
+#define GET_C2S_IRQ_LIMIT_NUMBER(nID) PREFIX(nID, CSIF_C2S_N)
+
+/*******************************************************************************
+ * Variable Declaration
+ *******************************************************************************/
+// thread shared variable
+volatile kal_uint32 _csif_exception_sync = 0;
+volatile kal_uint32 _csif_exception_sync_th[4] = {0};
+volatile kal_uint32 _csif_c2s_irq_test_flag[CSIF_ENUM_ALL_C2S_INT_NUM] = {0};
+
+
+
+static const kal_uint32 CSIF_S2C_Interrupt_Num[CSIF_ENUM_ALL_S2C_INT_NUM] = {
+ GET_S2C_IRQ_LIMIT_NUMBER(0),
+ GET_S2C_IRQ_LIMIT_NUMBER(1),
+ GET_S2C_IRQ_LIMIT_NUMBER(2),
+ GET_S2C_IRQ_LIMIT_NUMBER(3),
+ GET_S2C_IRQ_LIMIT_NUMBER(4),
+ GET_S2C_IRQ_LIMIT_NUMBER(5)
+};
+static const kal_uint32 CSIF_C2S_Interrupt_Num[CSIF_ENUM_ALL_C2S_INT_NUM] = {
+ GET_C2S_IRQ_LIMIT_NUMBER(0),
+ GET_C2S_IRQ_LIMIT_NUMBER(1),
+ GET_C2S_IRQ_LIMIT_NUMBER(2),
+ GET_C2S_IRQ_LIMIT_NUMBER(3)
+};
+
+extern csif_uint32 csif_mailbox_entry_num_table[CSIF_MAILBOX_TOTAL_NUM];
+
+
+// OLPDET TEST
+volatile kal_uint32 set_api_value = 0;
+volatile kal_uint32 clr_api_value = 0;
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+volatile kal_uint32 expect_max_mail_size;
+#endif
+volatile kal_uint32 expect_inuse_mail_size;
+volatile kal_uint32 expect_error_status;
+volatile kal_uint32 expect_set_candidate_record;
+volatile kal_uint32 expect_clr_candidate_record;
+
+volatile kal_uint32 set_candidate_record;
+volatile kal_uint32 clr_candidate_record;
+
+volatile kal_uint32 log_pattern = 0;;
+
+kal_uint32 expect_mum_arr[OLPDET_MUM_BIT_NUM/32] = {0};
+kal_uint32 dump_mum_arr[OLPDET_MUM_BIT_NUM/32] = {0};
+
+volatile kal_uint32 olpdet_record_set_err[32]={0};
+volatile kal_uint32 olpdet_err_count = 0;
+
+volatile kal_bool olpdet_error_polling_flag = KAL_FALSE;
+
+/*******************************************************************************
+ * Functions - Test
+ *******************************************************************************/
+
+volatile csif_uint32 expect_s2c_nID = 0;
+volatile csif_uint32 expect_s2c_bit = 2;
+
+#if defined(__CSIF_DRV_TEST__)
+void CSIF_drv_test_err(CSIF_ID_STATUS_t* status_id){
+ errStatusStruct[_errCount].id = status_id->id;
+ errStatusStruct[_errCount].code = status_id->code;
+ errStatusStruct[_errCount].masked_status = status_id->masked_status;
+ _errCount++;
+ return;
+}
+
+void CSIF_drv_test_olpdet_err(CSIF_ID_STATUS_t* status_id)
+{
+ volatile kal_uint32 read_error_flag;
+ volatile kal_uint32 read_error_snapshot;
+ volatile kal_uint32 inuse_mail_size;
+ volatile kal_uint32 error_status;
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ volatile kal_uint32 max_mail_size;
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE, max_mail_size);
+#endif
+
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE, inuse_mail_size);
+ CSIF_REG_READ(CSIF_OLPDET_ERROR_STATUS, error_status);
+ CSIF_REG_READ(CSIF_L1_ERROR_FLAG_CR, read_error_flag);
+ CSIF_REG_READ(CSIF_L1_ERROR_SNAPSHOT_CR, read_error_snapshot);
+
+ CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, set_candidate_record);
+ CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, clr_candidate_record);
+
+ olpdet_record_set_err[olpdet_err_count%8] = set_candidate_record;
+ olpdet_err_count++;
+
+ if(expect_error_status != 0){
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ if(max_mail_size != expect_max_mail_size )
+ {
+ SSDVT_FAIL_MSG(max_mail_size, (log_pattern | 0xA40000)| (expect_max_mail_size & 0xFFFF) , test_case_index);
+ }
+#endif
+ if(inuse_mail_size != expect_inuse_mail_size )
+ {
+ SSDVT_FAIL_MSG(inuse_mail_size, (log_pattern | 0xA00000)| (expect_inuse_mail_size & 0xFFFF) , test_case_index);
+ }
+
+ if(error_status != expect_error_status)
+ {
+ SSDVT_FAIL_MSG(error_status, (log_pattern | 0xA10000)| (expect_error_status & 0xFFFF), test_case_index);
+ }
+ if(set_candidate_record != expect_set_candidate_record)
+ {
+ SSDVT_FAIL_MSG(set_candidate_record, (log_pattern | 0xA20000)| (expect_set_candidate_record & 0xFFFF), test_case_index);
+ }
+ if(clr_candidate_record != expect_clr_candidate_record)
+ {
+ SSDVT_FAIL_MSG(clr_candidate_record, (log_pattern | 0xA30000)| (expect_clr_candidate_record & 0xFFFF), test_case_index);
+ }
+
+ if((read_error_flag & (0x1 << (OLPDET_ERR_BIT ))) == 0 ){
+ SSDVT_FAIL_MSG(read_error_flag, (log_pattern | 0xAA0000), test_case_index);
+ }
+ if((read_error_snapshot & (0x1 << (OLPDET_ERR_BIT ))) == 0 ){
+ SSDVT_FAIL_MSG(read_error_snapshot, (log_pattern | 0xAB0000), test_case_index);
+ }
+
+ // clear error
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+ CSIF_REG_READ(CSIF_OLPDET_ERROR_STATUS, error_status);
+ if(error_status != 0)
+ {
+ SSDVT_FAIL_MSG(error_status, (log_pattern | 0xC10000)| (expect_error_status & 0xFFFF), test_case_index);
+ }
+ olpdet_error_polling_flag = KAL_TRUE;
+ }
+ else{
+ SSDVT_FAIL_MSG(read_error_snapshot, (log_pattern | 0xEB0000)| (error_status & 0xFFFF) , test_case_index);
+ }
+}
+#endif
+
+#if defined(__CSIF_CROSS_CORE_TEST__)
+void CSIF_CROSSCORE_TEST(CSIF_ID_STATUS_t* status_id){
+ switch(IRQ_HANDLER_TYPE)
+ {
+ case CSIF_IRQ_HANDLER_IRQ_TEST:
+ {
+ test_case_index = test_case_index | (expect_s2c_nID << 8) | (expect_s2c_bit << 0);
+ if(status_id->id == expect_s2c_nID && status_id->code == expect_s2c_bit)
+ {
+ expect_s2c_bit++;
+ if(expect_s2c_bit > 31)
+ {
+ if(expect_s2c_nID == 0){
+ expect_s2c_bit = 2;
+ }else{
+ expect_s2c_bit = 0;
+ }
+ expect_s2c_nID++;
+ }
+ CSIF_REG_WRITE(CSIF_RSVD_1, CSIF_CROSS_IRQ_S2C_PASS);
+ }
+ else{
+ SSDVT_FAIL_MSG(status_id->id, status_id->code, test_case_index);
+ }
+ break;
+ }
+ case CSIF_IRQ_HANDLER_IDLE_IRQ_TEST:
+ {
+ _mcuInternalSyncPattern = EXPECT_IRQ_SET_FLAG_TRUE;
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + 0*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + 1*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+ break;
+ }
+ case CSIF_IRQ_HANDLER_MAILBOX_TEST:
+ {
+ break;
+ }
+ default:
+ {
+ SSDVT_FAIL_MSG(IRQ_HANDLER_TYPE, 0, test_case_index);
+ }
+ }
+ return;
+}
+#endif
+
+void cross_interrupt_test(void)
+{
+ volatile kal_uint32 read_value=0;
+ // **************************
+ // Disable S2C_IRQ_ENABLE
+ // **************************
+ for(kal_uint32 csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + csif_num_index*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, 0x0);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, read_value);
+ if(read_value != 0x0){
+ SSDVT_FAIL_MSG(read_value, csif_num_index, test_case_index);
+ }
+ }
+ // Disable DSP error
+ //CSIF_REG_WRITE(CSIF_DSP_ERROR_ENABLE_CR, 0x0);
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0);
+
+
+ volatile csif_uint32 dspSyncPattern = 0;
+
+ test_case_index = 0x10000000; // CSIF cross core interrupt TEST (s2c part)
+
+ // Sync barrier before test
+ while(1){
+ CSIF_REG_READ(CSIF_RSVD_0, dspSyncPattern);
+ if(dspSyncPattern == CSIF_CROSS_START1_DSP){
+ break;
+ }
+ }
+
+ // clear s2c irq
+ for(int i = CSIF_ENUM_S2C_N0; i< CSIF_ENUM_ALL_S2C_INT_NUM; i++)
+ {
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_CLR + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+ }
+ // enable s2c irq
+ for(int i = CSIF_ENUM_S2C_N0; i< CSIF_ENUM_ALL_S2C_INT_NUM; i++)
+ {
+ if(i == 0 || i == 1){
+#if defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFC);
+#elif defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_SET + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFC);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ }else{
+#if defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_SET + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ }
+ }
+
+ // sync barrier befor S2C IRQ test
+ CSIF_REG_WRITE(CSIF_RSVD_0, CSIF_CROSS_START1_MCU);
+
+ //***************
+ //** S2C irq in here
+ //***************
+
+ // Sync barrier before C2S IRQ test
+ while(1){
+ CSIF_REG_READ(CSIF_RSVD_0, dspSyncPattern);
+ if(dspSyncPattern == CSIF_CROSS_START2_DSP){
+ break;
+ }
+ }
+
+ test_case_index = 0x1b000000; // CSIF cross core interrupt TEST (c2s part)
+ // MCU trigger C2S irq to DSP
+ for(int i = CSIF_ENUM_C2S_N0; i < CSIF_ENUM_ALL_C2S_INT_NUM; i++)
+ {
+#if defined(__CSIF_SHAOLIN_64b_WORKAROUND__)
+ if((i & 0x1) != 0){
+ continue;
+ }
+#endif
+ for(int bit_i = 0; bit_i < C2S_IRQ_EN_WIDTH; bit_i++)
+ {
+ test_case_index = test_case_index | (i << 8) | (bit_i << 0);
+
+ CSIF_REG_WRITE(CSIF_C2S_IRQ_SET + i*CSIF_C2S_IRQ_SIZE, (0x1 << bit_i));
+
+ // Sync barrier during MCU set IRQ
+ CSIF_REG_WRITE(CSIF_RSVD_1, CSIF_CROSS_IRQ_C2S_WAIT);
+ while(1){
+ CSIF_REG_READ(CSIF_RSVD_1, dspSyncPattern);
+ if(dspSyncPattern == CSIF_CROSS_IRQ_C2S_PASS){
+ break;
+ }
+ }
+ }
+ }
+
+ // sync barrier after C2S IRQ test
+ CSIF_REG_WRITE(CSIF_RSVD_0, CSIF_CROSS_START2_MCU);
+
+
+ return;
+
+}
+
+// irq_idx = 0/1, enable_mask must be 4-bit mask; type=0/1 (IDLE_IRQ_ENABLE_TYPE_OR/IDLE_IRQ_ENABLE_TYPE_AND);
+// expect_irq_set_flag=EXPECT_IRQ_SET_FLAG_TRUE/FALSE
+void set_idle_irq_mask(csif_uint32 irq_idx, csif_uint32 enable_mask, csif_uint32 type, csif_uint32 expect_irq_set_flag)
+{
+ volatile csif_uint32 set_enable_reg_value;
+ //volatile csif_uint32 read_enable_reg_value;
+ volatile csif_uint32 read_S2C_status_value;
+
+
+ volatile csif_uint32 IRQ_waiting_counter = 0;
+
+
+
+ if(THIS_MCORE_ID == MCORE_ID_MCORE0){
+ set_enable_reg_value = (enable_mask << CSIF_S2C_IDLE_ENABLE_MCORE0_BIT) | (type << CSIF_S2C_IDLE_ENABLE_MCORE0_AND_OR_BIT);
+ }
+ else if(THIS_MCORE_ID == MCORE_ID_MCORE1){
+ set_enable_reg_value = (enable_mask << CSIF_S2C_IDLE_ENABLE_MCORE1_BIT) | (type << CSIF_S2C_IDLE_ENABLE_MCORE1_AND_OR_BIT);
+ }
+ else
+ {
+ //unsupported core
+ SSDVT_FAIL_MSG(THIS_MCORE_ID, 0x9ADDFFFF, test_case_index | (irq_idx << 16));
+ }
+
+ _mcuInternalSyncPattern = EXPECT_IRQ_SET_FLAG_FALSE;
+
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_SET + irq_idx*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, set_enable_reg_value);
+ /*
+ CSIF_REG_READ(CSIF_S2C_IDLE_IRQ_ENABLE + irq_idx*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, read_enable_reg_value);
+ if(read_enable_reg_value != set_enable_reg_value){
+ SSDVT_FAIL_MSG(read_enable_reg_value, (0x9B000000 | set_enable_reg_value), test_case_index | (irq_idx << 16));
+ }
+ */
+
+ while(IRQ_waiting_counter < EXC_TEST_WAITING_CYCLE){
+ IRQ_waiting_counter++;
+ }
+
+ if(expect_irq_set_flag == EXPECT_IRQ_SET_FLAG_TRUE)
+ {
+ if(_mcuInternalSyncPattern != EXPECT_IRQ_SET_FLAG_TRUE){
+ CSIF_REG_READ(CSIF_S2C_IRQ_STATUS + irq_idx*CSIF_S2C_IRQ_SIZE, read_S2C_status_value);
+ SSDVT_FAIL_MSG(read_S2C_status_value, (0x9C000000), test_case_index | (irq_idx << 16));
+ }
+ }
+ else if(expect_irq_set_flag == EXPECT_IRQ_SET_FLAG_FALSE)
+ {
+ if(_mcuInternalSyncPattern != EXPECT_IRQ_SET_FLAG_FALSE){
+ CSIF_REG_READ(CSIF_S2C_IRQ_STATUS + irq_idx*CSIF_S2C_IRQ_SIZE, read_S2C_status_value);
+ SSDVT_FAIL_MSG(read_S2C_status_value, (0x9D000000), test_case_index | (irq_idx << 16));
+ }
+ }
+
+ // clear enable register
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + irq_idx*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, CSIF_IDLE_IRQ_BIT_MASK);
+ /*
+ CSIF_REG_READ(CSIF_S2C_IDLE_IRQ_ENABLE + irq_idx*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, read_enable_reg_value);
+ if(read_enable_reg_value != 0){
+ SSDVT_FAIL_MSG(read_enable_reg_value, (0x9E000000 | irq_idx), (irq_idx << 16)|(test_case_index << 8)|_testing_main_thread);
+ }
+ */
+}
+
+void cross_idle_irq_test(void)
+{
+ volatile kal_uint32 read_value=0;
+ volatile kal_uint32 dsp_sync_pattern=0;
+ volatile kal_uint32 expect_polling_pattern=0;
+ volatile kal_uint32 dspSyncPattern=0;
+ test_case_index = 0x2000FFFF;
+ // **************************
+ // Disable S2C_IRQ_ENABLE
+ // **************************
+ for(kal_uint32 csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + csif_num_index*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, 0x0);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, read_value);
+ if(read_value != 0x0){
+ SSDVT_FAIL_MSG(read_value, csif_num_index, test_case_index);
+ }
+ }
+ // Disable L1 error
+ //CSIF_REG_WRITE(CSIF_DSP_ERROR_ENABLE_CR, 0x0);
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0);
+
+ // clear s2c irq
+ for(int i = CSIF_ENUM_S2C_N0; i< CSIF_ENUM_ALL_S2C_INT_NUM; i++)
+ {
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_CLR + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+ }
+ // clear s2c idle_irq enable
+ for(int i = 0; i < S2C_IDLE_IRQ_NUM; i++){
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + i*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, CSIF_IDLE_IRQ_BIT_MASK);
+ }
+ // enable s2c irq
+ for(int i = CSIF_ENUM_S2C_N0; i< S2C_IDLE_IRQ_NUM; i++)
+ {
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_SET + i*CSIF_S2C_IRQ_SIZE, 0x3);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + i*CSIF_S2C_IRQ_SIZE, 0x3);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ }
+
+ for(_mcore_testing_thread = 0; _mcore_testing_thread < MCORE_TH_NUM; _mcore_testing_thread++)
+ {
+ test_case_index = 0x2EEE0000 | _mcore_testing_thread;
+ switch(_mcore_testing_thread){
+ case 0:
+ dsp_sync_pattern = CSIF_CROSS_IDLE_IRQ_TH0_SYNC;
+ expect_polling_pattern = CSIF_CROSS_IDLE_IRQ_TH0_SYNC_DONE;
+ break;
+ case 1:
+ dsp_sync_pattern = CSIF_CROSS_IDLE_IRQ_TH1_SYNC;
+ expect_polling_pattern = CSIF_CROSS_IDLE_IRQ_TH1_SYNC_DONE;
+ break;
+ case 2:
+ dsp_sync_pattern = CSIF_CROSS_IDLE_IRQ_TH2_SYNC;
+ expect_polling_pattern = CSIF_CROSS_IDLE_IRQ_TH2_SYNC_DONE;
+ break;
+ case 3:
+ dsp_sync_pattern = CSIF_CROSS_IDLE_IRQ_TH3_SYNC;
+ expect_polling_pattern = CSIF_CROSS_IDLE_IRQ_TH3_SYNC_DONE;
+ break;
+ }
+ CSIF_REG_WRITE(CSIF_RSVD_0, dsp_sync_pattern);
+ while(1){
+ CSIF_REG_READ(CSIF_RSVD_0, dspSyncPattern);
+ if(dspSyncPattern == expect_polling_pattern){
+ break;
+ }
+ }
+
+ // 0x21()(irq_num)(thread)(testcase)
+ test_case_index = 0x21000000 | (_mcore_testing_thread << 8);
+ for(kal_uint32 irq_idx = 0; irq_idx < S2C_IDLE_IRQ_NUM; irq_idx++)
+ {
+ test_case_index = test_case_index | (0x1 << 0);
+ // case 1: or with 1111
+ set_idle_irq_mask(irq_idx, CORE_IDLE_COMPARE_MASK, IDLE_IRQ_ENABLE_TYPE_OR, EXPECT_IRQ_SET_FLAG_TRUE);
+
+ test_case_index = test_case_index | (0x1 << 1);
+ // case 2: or with main thread only
+ set_idle_irq_mask(irq_idx, (0x1 << _mcore_testing_thread), IDLE_IRQ_ENABLE_TYPE_OR, EXPECT_IRQ_SET_FLAG_FALSE);
+
+ test_case_index = test_case_index | (0x1 << 2);
+ // case 3: or with main thread except
+ set_idle_irq_mask(irq_idx, (CORE_IDLE_COMPARE_MASK ^ (0x1 << _mcore_testing_thread)), IDLE_IRQ_ENABLE_TYPE_OR, EXPECT_IRQ_SET_FLAG_TRUE);
+
+ test_case_index = test_case_index | (0x1 << 3);
+ // case 4: and with 1111
+ set_idle_irq_mask(irq_idx, CORE_IDLE_COMPARE_MASK, IDLE_IRQ_ENABLE_TYPE_AND, EXPECT_IRQ_SET_FLAG_FALSE);
+
+ test_case_index = test_case_index | (0x1 << 4);
+ // case 5: and with main thread only
+ set_idle_irq_mask(irq_idx, (0x1 << _mcore_testing_thread), IDLE_IRQ_ENABLE_TYPE_AND, EXPECT_IRQ_SET_FLAG_FALSE);
+
+ test_case_index = test_case_index | (0x1 << 5);
+ // case 6: or with main thread except
+ set_idle_irq_mask(irq_idx, (CORE_IDLE_COMPARE_MASK ^ (0x1 << _mcore_testing_thread)), IDLE_IRQ_ENABLE_TYPE_AND, EXPECT_IRQ_SET_FLAG_TRUE);
+ }
+ }
+ CSIF_REG_WRITE(CSIF_RSVD_0, CSIF_CROSS_IDLE_IRQ_CORE_SYNC);
+ return;
+}
+
+void cross_mailbox_test(void)
+{
+
+ volatile kal_uint32 read_value=0;
+ volatile kal_uint32 read_mail=0;
+ volatile kal_uint32 dspSyncPattern=0;
+ kal_uint32 maxMailNum = 0;
+ test_case_index = 0x3000FFFF;
+ // **************************
+ // Disable S2C_IRQ_ENABLE
+ // **************************
+ for(kal_uint32 csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + csif_num_index*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, 0x0);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, read_value);
+ if(read_value != 0x0){
+ SSDVT_FAIL_MSG(read_value, csif_num_index, test_case_index);
+ }
+ }
+ // Disable DSP error
+ //CSIF_REG_WRITE(CSIF_DSP_ERROR_ENABLE_CR, 0x0);
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0);
+
+ // Sync barrier before test
+ while(1){
+ CSIF_REG_READ(CSIF_RSVD_0, dspSyncPattern);
+ if(dspSyncPattern == CSIF_CROSS_MAILBOX_SYNC1_DSP){
+ break;
+ }
+ }
+ CSIF_REG_WRITE(CSIF_RSVD_0, CSIF_CROSS_MAILBOX_SYNC1_MCU);
+
+ // 0x30(m_idx)(i 16bit)
+ test_case_index = 0x30000000; // CSIF cross core Mailbox test (s2c part)
+
+ for(kal_uint32 m_idx = 0; m_idx < CSIF_MAILBOX_NUM; m_idx++)
+ {
+ test_case_index = 0x30000000; // CSIF cross core Mailbox test (s2c part)
+ test_case_index = test_case_index | (m_idx << 16);
+
+ if(m_idx == 0){
+ maxMailNum = 256;
+ }
+ else{
+ maxMailNum = 64;
+ }
+ // DSP send mail here
+ while(1){
+ CSIF_REG_READ(CSIF_RSVD_0, dspSyncPattern);
+ if(dspSyncPattern == CSIF_CROSS_MAILBOX_SYNC2_DSP){
+ break;
+ }
+ }
+ // receive mail
+ for(int i = 0; i < maxMailNum + 1; i++){
+ test_case_index = test_case_index | (i);
+ CSIF_REG_READ(CSIF_MAILBOX_RECV + m_idx*CSIF_MAILBOX_SIZE, read_mail);
+ if(read_mail != (MAILBOX_TEST_PREFIX_PATTERN | i)){
+ SSDVT_FAIL_MSG(read_mail, 0xAAAA0001, test_case_index);
+ }
+ }
+
+ CSIF_REG_READ(CSIF_MAILBOX_RECV + m_idx*CSIF_MAILBOX_SIZE, read_mail);
+ if(read_mail != CSIF_MAILBOX_EMPTY_VALUE){
+ SSDVT_FAIL_MSG(read_mail, 0xAAAA00EE, test_case_index);
+ }
+ test_case_index = 0x3b000000; // CSIF cross core Mailbox test (c2s part)
+ test_case_index = test_case_index | (m_idx << 16);
+
+ // send mail
+ for(int i = 0; i < maxMailNum + 1; i++){
+ test_case_index = test_case_index | (i);
+ CSIF_REG_WRITE(CSIF_MAILBOX_SEND + m_idx*CSIF_MAILBOX_SIZE, (MAILBOX_TEST_PREFIX_PATTERN | i));
+ }
+ CSIF_REG_WRITE(CSIF_RSVD_0, CSIF_CROSS_MAILBOX_SYNC2_MCU);
+ // DSP receive mail here until next iteration sync2
+
+ }
+
+}
+
+void csif_reg_default_value_test(void)
+{
+ test_case_index = 0xDC970000;
+
+ volatile kal_uint32 csif_num_index=0;
+
+ //case0: S2C_IRQ
+ //status ,masked status and enable
+ volatile kal_uint32 reg_read_value = 0;
+ for(csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+ //read status
+ CSIF_REG_READ(CSIF_S2C_IRQ_STATUS + csif_num_index*CSIF_S2C_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != S2C_IRQ_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ //read masked status
+ CSIF_REG_READ(CSIF_S2C_IRQ_MASKED_STATUS + csif_num_index*CSIF_S2C_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != S2C_IRQ_MASKED_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ //read enable
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != S2C_IRQ_EN_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+
+ }
+ test_case_index = 0xDC970001;
+
+ //case1: idle
+ //DSP core idle
+ /* mask because not sure DSP state */
+ /*
+ //read status
+ CSIF_REG_READ(CSIF_CORE_IDLE, reg_read_value);
+ if(reg_read_value != DSP_CORE_IDLE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0, test_case_index);
+ }
+ */
+ test_case_index = 0xDC970002;
+
+ //case2: idle_enable irq0 and irq1
+ //status ,masked status and enable
+ for(csif_num_index=0; csif_num_index<S2C_IDLE_IRQ_NUM; csif_num_index++)
+ {
+ //read enable
+ CSIF_REG_READ(CSIF_S2C_IDLE_IRQ_ENABLE + csif_num_index*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, reg_read_value);
+ if(reg_read_value != S2C_IRQ_IDLE_EN_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC970003;
+
+ //case3: c2s irq
+ //status ,masked status
+ for(csif_num_index=0; csif_num_index<C2S_IRQ_NUM; csif_num_index++)
+ {
+ //read status
+ CSIF_REG_READ(CSIF_C2S_IRQ_STATUS + csif_num_index*CSIF_C2S_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != C2S_IRQ_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ //read masked status
+ CSIF_REG_READ(CSIF_C2S_IRQ_MASKED_STATUS + csif_num_index*CSIF_C2S_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != C2S_IRQ_MASKED_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC970004;
+
+ //case4: mpu
+ //start, range
+ for(csif_num_index=0; csif_num_index<(DSP_MPU_NUM+L1_MPU_NUM); csif_num_index++)
+ {
+ //read start addr
+ CSIF_REG_READ(CSIF_MPU_START_ADDR + csif_num_index*CSIF_MPU_SIZE, reg_read_value);
+ if(reg_read_value != MPU_START_ADDR_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ //read range
+ CSIF_REG_READ(CSIF_MPU_RANGE + csif_num_index*CSIF_MPU_SIZE, reg_read_value);
+ if(reg_read_value != MPU_RANGE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC970005;
+
+ //case5: mpu err
+ //addr
+ for(csif_num_index=0; csif_num_index<DSP_MPU_NUM; csif_num_index++)
+ {
+ //read start addr
+ CSIF_REG_READ(CSIF_MPU_ERR_ADDR + csif_num_index*CSIF_MPU_ERR_SIZE, reg_read_value);
+ if(reg_read_value != MPU_ERR_ADDR_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC970006;
+
+ //case6: undefined region record
+ //error_status
+ //read DSM write
+ CSIF_REG_READ(CSIF_DSM_WRITE_UNDEFINED_ERR_STATUS_CR, reg_read_value);
+ if(reg_read_value != DSM_UNDEFINED_REGION_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0, test_case_index);
+ }
+ CSIF_REG_READ(CSIF_DSM_READ_UNDEFINED_ERR_STATUS_CR, reg_read_value);
+ if(reg_read_value != DSM_UNDEFINED_REGION_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 1, test_case_index);
+ }
+ CSIF_REG_READ(CSIF_DSR_WRITE_UNDEFINED_ERR_ADDR_CR, reg_read_value);
+ if(reg_read_value != DSR_UNDEFINED_REGION_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 2, test_case_index);
+ }
+ CSIF_REG_READ(CSIF_DSR_READ_UNDEFINED_ERR_ADDR_CR, reg_read_value);
+ if(reg_read_value != DSR_UNDEFINED_REGION_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 3, test_case_index);
+ }
+ test_case_index = 0xDC970007;
+
+ //case7: error flag
+ //error flag, shapshot, enable
+ //read error flag
+ CSIF_REG_READ(CSIF_L1_ERROR_FLAG_CR, reg_read_value);
+ if(reg_read_value != L1_ERROR_FLAG_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0, test_case_index);
+ }
+ //read error snapshot
+ CSIF_REG_READ(CSIF_L1_ERROR_SNAPSHOT_CR, reg_read_value);
+ if(reg_read_value != L1_ERROR_SNAPSHOT_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 1, test_case_index);
+ }
+ //read error enable
+ CSIF_REG_READ(CSIF_L1_ERROR_ENABLE_CR, reg_read_value);
+ if(reg_read_value != L1_ERROR_EN_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 2, test_case_index);
+ }
+
+ test_case_index = 0xDC970009;
+
+ //case9: S2C irq ovfl
+ //read ovfl error status
+ for(csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+ //read ovfl status
+ CSIF_REG_READ(CSIF_S2C_IRQ_OVFL_STATUS + csif_num_index*CSIF_S2C_IRQ_OVFL_SIZE, reg_read_value);
+ if(reg_read_value != S2C_IRQ_OVFL_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC97000A;
+
+ //case10: C2S irq ovfl
+ //read ovfl error status
+ for(csif_num_index=0; csif_num_index<C2S_IRQ_NUM; csif_num_index++)
+ {
+ //read ovfl status
+ CSIF_REG_READ(CSIF_C2S_IRQ_OVFL_STATUS + csif_num_index*CSIF_C2S_IRQ_OVFL_SIZE, reg_read_value);
+ if(reg_read_value != C2S_IRQ_OVFL_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC97000B;
+
+ // case11: MAILBOX
+ for(csif_num_index=0; csif_num_index<CSIF_MAILBOX_NUM; csif_num_index++)
+ {
+ //read send
+ CSIF_REG_READ(CSIF_MAILBOX_SEND + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_SEND_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC00000 | csif_num_index, test_case_index);
+ }
+ //read recv
+ CSIF_REG_READ(CSIF_MAILBOX_RECV + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_RECV_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC10000 | csif_num_index, test_case_index);
+ }
+ //read status
+ CSIF_REG_READ(CSIF_MAILBOX_STATUS + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_STATS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC20000 | csif_num_index, test_case_index);
+ }
+ //read max_fifo_usage
+ CSIF_REG_READ(CSIF_MAILBOX_MAX_FIFO_USAGE + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_MAX_FIFO_USAGE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC30000 | csif_num_index, test_case_index);
+ }
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ //read error _sub_enable
+ CSIF_REG_READ(CSIF_MAILBOX_ERROR_SUB_ENABLE + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_ERROR_SUB_ENABLE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC90000 | csif_num_index, test_case_index);
+ }
+#endif
+ //read error_status
+ CSIF_REG_READ(CSIF_MAILBOX_ERROR_STATUS + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_ERROR_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC40000 | csif_num_index, test_case_index);
+ }
+ //read error_record
+ CSIF_REG_READ(CSIF_MAILBOX_ERROR_RECORD + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_ERROR_RECORD_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC50000 | csif_num_index, test_case_index);
+ }
+ //read debug_enable
+ CSIF_REG_READ(CSIF_MAILBOX_DEBUG_ENABLE + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_DEBUG_ENABLE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC60000 | csif_num_index, test_case_index);
+ }
+ //read debug_read_content
+ CSIF_REG_READ(CSIF_MAILBOX_DEBUG_READ_CONTENT + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_DEBUG_READ_CONTENT_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC70000 | csif_num_index, test_case_index);
+ }
+ //read debug_read_idx
+ CSIF_REG_READ(CSIF_MAILBOX_DEBUG_READ_IDX + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_DEBUG_READ_IDX_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC80000 | csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC97000C;
+
+ // case12: OLPDET
+ for(csif_num_index=0; csif_num_index<1; csif_num_index++)
+ {
+ //read set
+ CSIF_REG_READ(CSIF_OLPDET_SET + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_SET_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD00000 | csif_num_index, test_case_index);
+ }
+ //read clr
+ CSIF_REG_READ(CSIF_OLPDET_CLR + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_CLR_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD10000 | csif_num_index, test_case_index);
+ }
+ //read inuse_mail_size
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_INUSE_MAIL_SIZE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD20000 | csif_num_index, test_case_index);
+ }
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ //read max_mail_size
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_MAX_MAIL_SIZE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD90000 | csif_num_index, test_case_index);
+ }
+ //read error sub enable
+ CSIF_REG_READ(CSIF_OLPDET_ERROR_SUB_ENABLE + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_ERROR_SUB_ENABLE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABDA0000 | csif_num_index, test_case_index);
+ }
+#endif
+ //read error_status
+ CSIF_REG_READ(CSIF_OLPDET_ERROR_STATUS + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_ERROR_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD30000 | csif_num_index, test_case_index);
+ }
+ //read set_candidate
+ CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_SET_CANDIDATE_RECORD_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD40000 | csif_num_index, test_case_index);
+ }
+ //read clr_candidate
+ CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_CLR_CANDIDATE_RECORD_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD50000 | csif_num_index, test_case_index);
+ }
+ //read debug_read_mum_idx
+ // Note: this debug_mum_idx must be read earlier that debug_read_mum
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_DEBUG_READ_MUM_IDX_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD70000 | csif_num_index, test_case_index);
+ }
+ //read debug_read_mum
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_DEBUG_READ_MUM_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD60000 | csif_num_index, test_case_index);
+ }
+ //read debug_clr_mum_enable
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_DEBUG_CLR_MUM_ENABLE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD80000 | csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC97000D;
+}
+
+void csif_reg_rw_test(void)
+{
+ volatile kal_uint32 csif_num_index=0;
+ volatile kal_uint32 reg_read_value = 0;
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ kal_uint32 expect_read_value = 0;
+#endif
+ test_case_index = 0xDC971000;
+
+ // Disable C2S IRQ
+ for(csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + csif_num_index*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, 0x0);
+#else
+ #error "unsupport project, may need porting"
+#endif // project option
+ }
+
+ // Disable DSP&L1 error
+ //CSIF_REG_WRITE(CSIF_DSP_ERROR_ENABLE_CR, 0x0);
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0);
+
+ //case0: S2C_IRQ enable
+ for(csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ expect_read_value = 0;
+ for(kal_uint32 bit_idx = 0; bit_idx < S2C_IRQ_EN_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_SET + csif_num_index*CSIF_S2C_IRQ_SIZE, (0x1 << bit_idx));
+ expect_read_value = expect_read_value | (0x1 << bit_idx);
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != expect_read_value){
+ SSDVT_FAIL_MSG(reg_read_value, (0x000A0000| csif_num_index), test_case_index);
+ }
+ }
+ for(kal_uint32 bit_idx = 0; bit_idx < S2C_IRQ_EN_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + csif_num_index*CSIF_S2C_IRQ_SIZE, (0x1 << bit_idx));
+ expect_read_value = expect_read_value & ~(0x1 << bit_idx);
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != expect_read_value){
+ SSDVT_FAIL_MSG(reg_read_value, (0x000B0000| csif_num_index), test_case_index);
+ }
+ }
+#elif defined(MT6297)
+ //write and read reg bit sequentially
+ for(kal_uint32 bit_idx = 0; bit_idx < S2C_IRQ_EN_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+#else
+ #error "unsupport project, may need porting"
+#endif // project option
+ }
+ // Disable S2C IRQ
+ for(csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + csif_num_index*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, 0x0);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ }
+
+ test_case_index = 0xDC971002;
+
+ //case2: MPU start/range
+ for(csif_num_index=0; csif_num_index<DSP_MPU_NUM+L1_MPU_NUM; csif_num_index++)
+ {
+ //write and read reg bit sequentially
+ // MPU start
+ for(kal_uint32 bit_idx = 0; bit_idx < MPU_START_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_MPU_START_ADDR + csif_num_index*CSIF_MPU_SIZE, (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_MPU_START_ADDR + csif_num_index*CSIF_MPU_SIZE, reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ // MPU range
+ for(kal_uint32 bit_idx = 0; bit_idx < MPU_RANGE_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_MPU_RANGE + csif_num_index*CSIF_MPU_SIZE, (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_MPU_RANGE + csif_num_index*CSIF_MPU_SIZE, reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ }
+ // Clear MPU start/range
+ for(csif_num_index=0; csif_num_index<DSP_MPU_NUM+L1_MPU_NUM; csif_num_index++)
+ {
+ CSIF_REG_WRITE(CSIF_MPU_START_ADDR + csif_num_index*CSIF_MPU_SIZE, 0x0);
+ CSIF_REG_WRITE(CSIF_MPU_RANGE + csif_num_index*CSIF_MPU_SIZE, 0x0);
+ }
+ test_case_index = 0xDC971003;
+
+ //case3: Error enable
+ //write and read reg bit sequentially
+ // L1 error enable
+ for(kal_uint32 bit_idx = 0; bit_idx < L1_ERROR_EN_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_L1_ERROR_ENABLE_CR, reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, bit_idx, test_case_index);
+ }
+ }
+ // Clear DSP & L1 error enable
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0);
+ test_case_index = 0xDC971004;
+
+ //case4: MAILBOX
+ for(csif_num_index=0; csif_num_index<CSIF_MAILBOX_NUM; csif_num_index++)
+ {
+ //mailbox_send RW
+ for(kal_uint32 bit_idx = 0; bit_idx < MAILBOX_SEND_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_MAILBOX_SEND + csif_num_index*CSIF_MAILBOX_SIZE, (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_MAILBOX_SEND + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC00000 | csif_num_index << 8 | bit_idx, test_case_index);
+ }
+ }
+ //mailbox_debug_enable RW
+ for(kal_uint32 bit_idx = 0; bit_idx < MAILBOX_DEBUG_ENABLE_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_MAILBOX_DEBUG_ENABLE + csif_num_index*CSIF_MAILBOX_SIZE, (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_MAILBOX_DEBUG_ENABLE + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC10000 | csif_num_index << 8 | bit_idx, test_case_index);
+ }
+ }
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ //mailbox_error_sub_enable
+ for(kal_uint32 bit_idx = 0; bit_idx < MAILBOX_ERROR_SUB_ENABLE_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_MAILBOX_ERROR_SUB_ENABLE + csif_num_index*CSIF_MAILBOX_SIZE, (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_MAILBOX_ERROR_SUB_ENABLE + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC20000 | csif_num_index << 8 | bit_idx, test_case_index);
+ }
+ }
+#endif
+ }
+ test_case_index = 0xDC971005;
+ //case5: olpdet
+ //olpdet set/clr RW
+ for(kal_uint32 bit_idx = CSIF_OLPDET_SET_OFFSET_P; bit_idx < CSIF_OLPDET_SET_OFFSET_P+OLPDET_SET_CLR_OFFSET_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_OLPDET_SET , (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_OLPDET_SET , reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD00000 | bit_idx, test_case_index);
+ }
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR , (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_OLPDET_CLR , reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD10000 | bit_idx, test_case_index);
+ }
+ }
+ for(kal_uint32 bit_idx = CSIF_OLPDET_SET_LENGTH_P; bit_idx < CSIF_OLPDET_SET_LENGTH_P+OLPDET_SET_CLR_LENGTH_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_OLPDET_SET , (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_OLPDET_SET , reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD20000 | bit_idx, test_case_index);
+ }
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR , (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_OLPDET_CLR , reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD30000 | bit_idx, test_case_index);
+ }
+ }
+ //olpdet debug_clr_mum_enable RW
+ for(kal_uint32 bit_idx = 0; bit_idx < OLPDET_DEBUG_CLR_MUM_ENABLE_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE , (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE , reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD40000 | bit_idx, test_case_index);
+ }
+ }
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ //olpdet error_sub_enable
+ for(kal_uint32 bit_idx = 0; bit_idx < OLPDET_ERROR_SUB_ENABLE_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_OLPDET_ERROR_SUB_ENABLE , (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_OLPDET_ERROR_SUB_ENABLE , reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD50000 | bit_idx, test_case_index);
+ }
+ }
+#endif // project option
+ test_case_index = 0xDC971006;
+}
+
+
+
+
+void OLPDET_Set(csif_uint32 two_word_addr, csif_uint32 two_word_size)
+{
+ set_api_value = (two_word_addr << CSIF_OLPDET_SET_OFFSET_P) | (two_word_size << CSIF_OLPDET_SET_LENGTH_P);
+ if(expect_error_status != 0){
+ expect_set_candidate_record = set_api_value;
+ }
+ CSIF_REG_WRITE(CSIF_OLPDET_SET, set_api_value);
+}
+
+void OLPDET_Clr(csif_uint32 two_word_addr, csif_uint32 two_word_size)
+{
+ clr_api_value = (two_word_addr << CSIF_OLPDET_SET_OFFSET_P) | (two_word_size << CSIF_OLPDET_SET_LENGTH_P);
+ if(expect_error_status != 0){
+ expect_clr_candidate_record = clr_api_value;
+ }
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR, clr_api_value);
+}
+
+void olpdet_check_status(void)
+{
+ volatile kal_uint32 read_error_flag;
+ volatile kal_uint32 read_error_snapshot;
+ volatile kal_uint32 inuse_mail_size;
+ volatile kal_uint32 error_status;
+
+
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ volatile kal_uint32 max_mail_size;
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE, max_mail_size);
+#endif
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE, inuse_mail_size);
+ CSIF_REG_READ(CSIF_OLPDET_ERROR_STATUS, error_status);
+ CSIF_REG_READ(CSIF_L1_ERROR_FLAG_CR, read_error_flag);
+ CSIF_REG_READ(CSIF_L1_ERROR_SNAPSHOT_CR, read_error_snapshot);
+
+ if(expect_error_status != 0){
+ SSDVT_FAIL_MSG(read_error_snapshot, (log_pattern | 0xFB0000)| (error_status & 0xFFFF) , test_case_index);
+ }
+ else{
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ if(max_mail_size != expect_max_mail_size )
+ {
+ SSDVT_FAIL_MSG(max_mail_size, (log_pattern | 0xB40000)| (expect_max_mail_size & 0xFFFF) , test_case_index);
+ }
+#endif
+ if(inuse_mail_size != expect_inuse_mail_size )
+ {
+ SSDVT_FAIL_MSG(inuse_mail_size, (log_pattern | 0xB00000)| (expect_inuse_mail_size & 0xFFFF) , test_case_index);
+ }
+
+ if(error_status != expect_error_status)
+ {
+ SSDVT_FAIL_MSG(error_status, (log_pattern | 0xB10000)| (expect_error_status & 0xFFFF), test_case_index);
+ }
+ if(set_candidate_record != expect_set_candidate_record)
+ {
+ SSDVT_FAIL_MSG(set_candidate_record, (log_pattern | 0xB20000)| (expect_set_candidate_record & 0xFFFFF), test_case_index);
+ }
+ if(clr_candidate_record != expect_clr_candidate_record)
+ {
+ SSDVT_FAIL_MSG(clr_candidate_record, (log_pattern | 0xB30000)| (expect_clr_candidate_record & 0xFFFFF), test_case_index);
+ }
+ if((read_error_flag & (0x1 << (OLPDET_ERR_BIT ))) != 0 ){
+ SSDVT_FAIL_MSG(read_error_flag, (log_pattern | 0xBA0000) , test_case_index);
+ }
+ if((read_error_snapshot & (0x1 << (OLPDET_ERR_BIT ))) != 0 ){
+ SSDVT_FAIL_MSG(read_error_snapshot, (log_pattern | 0xBB0000), test_case_index);
+ }
+ }
+}
+
+void csif_olpdet_dvt_test(void)
+{
+
+ // Disable DSP&L1 error
+ //CSIF_REG_WRITE(CSIF_DSP_ERROR_ENABLE_CR, 0x0);
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, CSIF_L1_ERROR_MASK);
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ volatile kal_uint32 read_max_mail_size;
+#endif
+
+
+
+
+
+ volatile kal_uint32 read_debug_read_mum;
+ volatile kal_uint32 read_debug_read_mum_idx;
+
+ kal_uint32 region_start_addr = 0;
+
+ kal_uint32 olpdet_error_flag = 0;
+
+ volatile kal_uint32 dummy_olpdet_counter = 0;
+
+
+ //******* local variable init!! **************//
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ expect_max_mail_size = 0;
+#endif
+ expect_inuse_mail_size = 0;
+ expect_error_status = 0;
+ expect_set_candidate_record = 0;
+ expect_clr_candidate_record = 0;
+ //*****************************************//
+
+ // case1: check initial status
+ test_case_index = 0xDC972001;
+ // check OLPDET status
+ log_pattern = 0xAA000000;
+ set_candidate_record = expect_set_candidate_record;
+ clr_candidate_record = expect_clr_candidate_record;
+ olpdet_check_status();
+
+ // case2 set default olpdet region
+ test_case_index = 0xDC972A00;
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR, OLPDET_TEST_REGION_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_B_START_ADDR, OLPDET_TEST_REGION_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_C_START_ADDR, OLPDET_TEST_REGION_LENGTH);
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = OLPDET_TEST_REGION_LENGTH*3;
+ expect_error_status = 0;
+ expect_set_candidate_record = 0;
+ expect_clr_candidate_record = 0;
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+#endif
+ //*****************************************//
+
+ for(kal_uint32 test_region = OLPDET_TEST_REGION_A; test_region < OLPDET_TEST_REGION_TOTAL; test_region++)
+ {
+ switch(test_region){
+ case OLPDET_TEST_REGION_A:
+ region_start_addr = OLPDET_TEST_REGION_A_START_ADDR;
+ break;
+ case OLPDET_TEST_REGION_B:
+ region_start_addr = OLPDET_TEST_REGION_B_START_ADDR;
+ break;
+ case OLPDET_TEST_REGION_C:
+ region_start_addr = OLPDET_TEST_REGION_C_START_ADDR;
+ break;
+ }
+ for(kal_uint32 test_point = 0; test_point < 7; test_point++)
+ {
+ test_case_index = test_case_index | (test_region << 8) | test_point;
+
+ if(TEST_REGION_POINT_ARRAY[test_region][test_point] == KAL_FALSE){
+ continue;
+ }
+
+ if(test_point == 0 || test_point == 6 )
+ {
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size + OLPDET_TEST_POINT_LENGTH;
+ expect_error_status = 0;
+ expect_set_candidate_record = 0;
+ expect_clr_candidate_record = 0;
+ #if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+ #endif
+ //*****************************************//
+ log_pattern = 0xBA000000;
+ set_candidate_record = expect_set_candidate_record;
+ clr_candidate_record = expect_clr_candidate_record;
+ olpdet_error_flag = 1;
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ }
+ else
+ {
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size;
+ if(test_region == OLPDET_TEST_REGION_C && (test_point == 5) )
+ {
+
+ expect_error_status = (0x1 << OLPDET_OLP_HIT_ERROR_BIT) | (0x1 << OLPDET_SET_CONTENT_ERROR_BIT);
+ //expect_error_status = (0x1 << OLPDET_OLP_HIT_ERROR_BIT) ;
+ }
+ else{
+ expect_error_status = 0x1 << OLPDET_OLP_HIT_ERROR_BIT;
+ }
+ #if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+ #endif
+ //expect_set_candidate_record = set_api_value;
+ CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+ // modify flag to false that must be set to true in exception callback
+ olpdet_error_polling_flag = KAL_FALSE;
+ //*****************************************//
+ log_pattern = 0xBB000000;
+ }
+ switch(test_point)
+ {
+ case 0:
+ OLPDET_Set(region_start_addr - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 1:
+ OLPDET_Set(region_start_addr - OLPDET_TEST_POINT_LENGTH + 1, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 2:
+ OLPDET_Set(region_start_addr, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 3:
+ OLPDET_Set(region_start_addr + 64, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 4:
+ OLPDET_Set(region_start_addr + OLPDET_TEST_REGION_LENGTH - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 5:
+ OLPDET_Set(region_start_addr + OLPDET_TEST_REGION_LENGTH - OLPDET_TEST_POINT_LENGTH + 1, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 6:
+ OLPDET_Set(region_start_addr + OLPDET_TEST_REGION_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ break;
+ }
+ while(olpdet_error_polling_flag != KAL_TRUE){
+ dummy_olpdet_counter++;
+ }
+ if(olpdet_error_flag != 0){
+ olpdet_check_status();
+ olpdet_error_flag = 0;
+ }
+ }
+ }
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ // case2a clr default olpdet region
+ test_case_index = 0xDC972B00;
+ // reset region to default
+ OLPDET_Clr(OLPDET_TEST_REGION_A_START_ADDR + OLPDET_TEST_REGION_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Clr(OLPDET_TEST_REGION_B_START_ADDR - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Clr(OLPDET_TEST_REGION_B_START_ADDR + OLPDET_TEST_REGION_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Clr(OLPDET_TEST_REGION_C_START_ADDR - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size - 4*OLPDET_TEST_POINT_LENGTH;
+ expect_error_status = 0;
+ expect_set_candidate_record = 0;
+ expect_clr_candidate_record = 0;
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+#endif
+ //*****************************************//
+ for(kal_uint32 test_region = OLPDET_TEST_REGION_A; test_region < OLPDET_TEST_REGION_TOTAL; test_region++)
+ {
+ switch(test_region){
+ case OLPDET_TEST_REGION_A:
+ region_start_addr = OLPDET_TEST_REGION_A_START_ADDR;
+ break;
+ case OLPDET_TEST_REGION_B:
+ region_start_addr = OLPDET_TEST_REGION_B_START_ADDR;
+ break;
+ case OLPDET_TEST_REGION_C:
+ region_start_addr = OLPDET_TEST_REGION_C_START_ADDR;
+ break;
+ }
+ for(kal_uint32 test_point = 0; test_point < 7; test_point++)
+ {
+ test_case_index = test_case_index | (test_region << 8) | test_point;
+
+ if(TEST_REGION_POINT_ARRAY[test_region][test_point] == KAL_FALSE){
+ continue;
+ }
+
+ if(test_point == 2 || test_point == 3 || test_point == 4 )
+ {
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size - OLPDET_TEST_POINT_LENGTH;
+ expect_error_status = 0;
+ expect_set_candidate_record = 0;
+ expect_clr_candidate_record = 0;
+ #if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+ #endif
+ //*****************************************//
+ log_pattern = 0xBA000000;
+ set_candidate_record = expect_set_candidate_record;
+ clr_candidate_record = expect_clr_candidate_record;
+ olpdet_error_flag = 1;
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ }
+ else
+ {
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size;
+ if(test_region == OLPDET_TEST_REGION_C && (test_point == 5) )
+ {
+
+ expect_error_status = (0x1 << OLPDET_CLR_NOHIT_ERROR_BIT) | (0x1 << OLPDET_CLR_CONTENT_ERROR_BIT);
+ }
+ else{
+ expect_error_status = 0x1 << OLPDET_CLR_NOHIT_ERROR_BIT;
+ }
+ #if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+ #endif
+ //expect_set_candidate_record = set_api_value;
+ CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, expect_set_candidate_record);
+ // modify flag to false that must be set to true in exception callback
+ olpdet_error_polling_flag = KAL_FALSE;
+ //*****************************************//
+ log_pattern = 0xBB000000;
+ }
+ switch(test_point)
+ {
+ case 0:
+ OLPDET_Clr(region_start_addr - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 1:
+ OLPDET_Clr(region_start_addr - OLPDET_TEST_POINT_LENGTH + 1, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 2:
+ OLPDET_Clr(region_start_addr, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 3:
+ OLPDET_Clr(region_start_addr + 64, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 4:
+ OLPDET_Clr(region_start_addr + OLPDET_TEST_REGION_LENGTH - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 5:
+ OLPDET_Clr(region_start_addr + OLPDET_TEST_REGION_LENGTH - OLPDET_TEST_POINT_LENGTH + 1, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 6:
+ OLPDET_Clr(region_start_addr + OLPDET_TEST_REGION_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ break;
+ }
+ while(olpdet_error_polling_flag != KAL_TRUE){
+ dummy_olpdet_counter++;
+ }
+ if(olpdet_error_flag != 0){
+ olpdet_check_status();
+ olpdet_error_flag = 0;
+ }
+ }
+ }
+
+ test_case_index = 0xDC972C00;
+ //reset region to default (restore testing point 2, 3, 4)
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR + 64, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR + OLPDET_TEST_REGION_LENGTH - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_B_START_ADDR, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_B_START_ADDR + 64, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_B_START_ADDR + OLPDET_TEST_REGION_LENGTH - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_C_START_ADDR, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_C_START_ADDR + 64, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_C_START_ADDR + OLPDET_TEST_REGION_LENGTH - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ // restore region state to after set test
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR + OLPDET_TEST_REGION_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_B_START_ADDR - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_B_START_ADDR + OLPDET_TEST_REGION_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_C_START_ADDR - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ //clear max mail size
+ CSIF_REG_WRITE(CSIF_OLPDET_MAX_MAIL_SIZE_CLR, 0x1);
+ expect_max_mail_size = 0;
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size + 13*OLPDET_TEST_POINT_LENGTH;
+ expect_error_status = 0;
+ expect_set_candidate_record = set_candidate_record;
+ expect_clr_candidate_record = clr_candidate_record;
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+#endif
+ olpdet_error_flag = 1;
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ olpdet_check_status();
+ //*****************************************//
+
+#endif // Petrus project
+
+ // case3 set content error
+ test_case_index = 0xDC973000;
+
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size;
+ expect_error_status = (0x1 << OLPDET_SET_CONTENT_ERROR_BIT);
+ expect_set_candidate_record = set_api_value;
+ CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+#endif
+ olpdet_error_polling_flag = KAL_FALSE;
+ //*****************************************//
+ log_pattern = 0xCA000000;
+ // set length overflow
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 129);
+ while(olpdet_error_polling_flag != KAL_TRUE){
+ dummy_olpdet_counter++;
+ }
+ // case4 clr length overflow
+ test_case_index = 0xDC974000;
+
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size;
+ expect_error_status = (0x1 << OLPDET_CLR_CONTENT_ERROR_BIT);
+ CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, expect_set_candidate_record);
+ expect_clr_candidate_record = clr_api_value;
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+#endif
+ olpdet_error_polling_flag = KAL_FALSE;
+ //*****************************************//
+ log_pattern = 0xCB000000;
+ // clr length overflow
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ OLPDET_Clr(OLPDET_TEST_REGION_A_START_ADDR, 129);
+#elif defined(MT6297)
+ OLPDET_Clr(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 129);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ while(olpdet_error_polling_flag != KAL_TRUE){
+ dummy_olpdet_counter++;
+ }
+ // case5 Dump MUM
+ test_case_index = 0xDC975000;
+
+ // create set MUM array
+ //first 128 + tail 2 bit
+ expect_mum_arr[0] = 0xFFFFFFFF; //0 ~ 31
+ expect_mum_arr[1] = 0xFFFFFFFF; //32 ~ 63
+ expect_mum_arr[2] = 0xFFFFFFFF; //64 ~ 95
+ expect_mum_arr[3] = 0xFFFFFFFF; //96 ~ 127
+ expect_mum_arr[4] = 0x00000003; //128 ~ 129
+
+ // head 2 bit + 1024~1151 + tail 2 bit
+ expect_mum_arr[31] = 0xC0000000; //1022 ~ 1023
+ expect_mum_arr[32] = 0xFFFFFFFF; //1024 ~ 1055
+ expect_mum_arr[33] = 0xFFFFFFFF; //1056 ~ 1087
+ expect_mum_arr[34] = 0xFFFFFFFF; //1088 ~ 1119
+ expect_mum_arr[35] = 0xFFFFFFFF; //1120 ~ 1151
+ expect_mum_arr[36] = 0x00000003; //1152 ~ 1153
+
+ // head 2 bit + 1920 ~ 2048
+ expect_mum_arr[59] = 0xC0000000; //1022 ~ 1023
+ expect_mum_arr[60] = 0xFFFFFFFF; //1920 ~ 1951
+ expect_mum_arr[61] = 0xFFFFFFFF; //1954 ~ 1983
+ expect_mum_arr[62] = 0xFFFFFFFF; //1984 ~ 2015
+ expect_mum_arr[63] = 0xFFFFFFFF; //2016 ~ 2047
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX, read_debug_read_mum_idx);
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM, read_debug_read_mum);
+ dump_mum_arr[read_debug_read_mum_idx] = read_debug_read_mum;
+ }
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ test_case_index = test_case_index | dump_i;
+ if(dump_mum_arr[dump_i] != expect_mum_arr[dump_i]){
+ SSDVT_FAIL_MSG(dump_mum_arr[dump_i], expect_mum_arr[dump_i], test_case_index);
+ }
+ }
+
+ //case:6 clear error and redump MUM
+ test_case_index = 0xDC976000;
+ // clear error
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX, read_debug_read_mum_idx);
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM, read_debug_read_mum);
+ dump_mum_arr[read_debug_read_mum_idx] = read_debug_read_mum;
+ }
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ test_case_index = test_case_index | dump_i;
+ if(dump_mum_arr[dump_i] != expect_mum_arr[dump_i]){
+ SSDVT_FAIL_MSG(dump_mum_arr[dump_i], expect_mum_arr[dump_i], test_case_index);
+ }
+ }
+#if defined(MT6297)
+ //case:7 trigger error and enable debug_clr_mum, then dump(should be empty)
+ test_case_index = 0xDC977000;
+
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size;
+ expect_error_status = (0x1 << OLPDET_SET_CONTENT_ERROR_BIT);
+ expect_set_candidate_record = set_api_value;
+ CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+ olpdet_error_polling_flag = KAL_FALSE;
+ //*****************************************//
+ log_pattern = 0xDA000000;
+
+ // enable debug_clr_mum
+ CSIF_REG_WRITE(CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE, 0x1);
+
+ // set length overflow
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 129);
+ while(olpdet_error_polling_flag != KAL_TRUE){
+ dummy_olpdet_counter++;
+ }
+ /*
+ for(int i = 0; i < 100; i++){
+ dummy_olpdet_counter++;
+ }
+ */
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX, read_debug_read_mum_idx);
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM, read_debug_read_mum);
+ dump_mum_arr[read_debug_read_mum_idx] = read_debug_read_mum;
+ }
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ test_case_index = test_case_index | dump_i;
+ if(dump_mum_arr[dump_i] != 0){
+ SSDVT_FAIL_MSG(dump_mum_arr[dump_i], 0xDAFFBEEF, test_case_index);
+ }
+ }
+
+
+ test_case_index = 0xDC972008;
+ return;
+#elif defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ //case:7 enable debug_clr_mum, then clear error (without error happened) and dump(should be empty)
+ test_case_index = 0xDC977000;
+ // enable debug_clr_mum
+ CSIF_REG_WRITE(CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE, 0x1);
+ // Clear error
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+ // Clear max mail size
+ CSIF_REG_WRITE(CSIF_OLPDET_MAX_MAIL_SIZE_CLR, 0x1);
+ //******* local variable init!! **************//
+ expect_max_mail_size = 0;
+ expect_inuse_mail_size = 0;
+ expect_error_status = 0;
+ expect_set_candidate_record = set_candidate_record;
+ expect_clr_candidate_record = clr_candidate_record;
+ //CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, expect_set_candidate_record);
+ //CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+ olpdet_error_flag = 1;
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ //*****************************************//
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX, read_debug_read_mum_idx);
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM, read_debug_read_mum);
+ dump_mum_arr[read_debug_read_mum_idx] = read_debug_read_mum;
+ }
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ test_case_index = test_case_index | dump_i;
+ if(dump_mum_arr[dump_i] != 0){
+ SSDVT_FAIL_MSG(dump_mum_arr[dump_i], 0xDAFFBEEF, test_case_index);
+ }
+ }
+ log_pattern = 0xDB000000;
+ olpdet_check_status();
+
+ //case:8 Disable sub enable and trigger error, check error status
+ test_case_index = 0xDC978000;
+ log_pattern = 0xDC000000;
+ CSIF_REG_WRITE(CSIF_OLPDET_ERROR_SUB_ENABLE, ~(CSIF_OLPDET_SET_CONTENT_ERROR_M | CSIF_OLPDET_CLR_CONTENT_ERROR_M | CSIF_OLPDET_OLP_HIT_ERROR_M | CSIF_OLPDET_CLR_NOHIT_ERROR_M));
+
+ //******* local variable init!! **************//
+ expect_error_status = 0;
+ expect_set_candidate_record = set_candidate_record;
+ expect_clr_candidate_record = clr_candidate_record;
+ //CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, expect_set_candidate_record);
+ //CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 129);
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE, expect_inuse_mail_size);
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE, expect_max_mail_size);
+ olpdet_error_flag = 1;
+
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ //*****************************************//
+
+ olpdet_check_status();
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+
+ // olpdet_clr_content error
+ log_pattern = 0xDD000000;
+
+ //******* local variable init!! **************//
+ expect_error_status = 0;
+ expect_set_candidate_record = set_candidate_record;
+ expect_clr_candidate_record = clr_candidate_record;
+ //CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, expect_set_candidate_record);
+ //CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+ olpdet_error_flag = 1;
+ OLPDET_Clr(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 129);
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE, expect_inuse_mail_size);
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE, expect_max_mail_size);
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ //*****************************************//
+
+ olpdet_check_status();
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+
+ // olpdet_olphit error
+ log_pattern = 0xDE000000;
+
+ //******* local variable init!! **************//
+ expect_error_status = 0;
+ expect_set_candidate_record = set_candidate_record;
+ expect_clr_candidate_record = clr_candidate_record;
+ //CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, expect_set_candidate_record);
+ //CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+ olpdet_error_flag = 1;
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 128);
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 128);
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE, expect_inuse_mail_size);
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE, expect_max_mail_size);
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ //*****************************************//
+ olpdet_check_status();
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+
+ // olpdet_clr nohit error
+ log_pattern = 0xDF000000;
+
+ //******* local variable init!! **************//
+ expect_error_status = 0;
+ expect_set_candidate_record = set_candidate_record;
+ expect_clr_candidate_record = clr_candidate_record;
+ //CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, expect_set_candidate_record);
+ //CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+ olpdet_error_flag = 1;
+ OLPDET_Clr(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 128);
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE, expect_inuse_mail_size);
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE, expect_max_mail_size);
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ //*****************************************//
+ olpdet_check_status();
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+#else
+ #error "unsupport project, may need porting"
+#endif
+}
+
+void csif_mem_test(void)
+{
+
+
+ volatile kal_uint32 write_idx = 0;
+ volatile kal_uint32 mem_read_value = 0;
+ volatile kal_uint64 mem_read_value_64 = 0;
+
+
+ volatile kal_uint32 memory_base_addr = CSIF_DSM_BASE;
+ volatile kal_uint32 memory_size = CSIF_DSM_SIZE;
+
+ //case0: write 0 (1x/1x)
+ for(write_idx = 0; write_idx < memory_size/4; write_idx++)
+ {
+ *((volatile kal_uint32*)(memory_base_addr+write_idx*4)) = MEM_TEST_PATTERN0;
+ mem_read_value = *((volatile kal_uint32*)(memory_base_addr+write_idx*4));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*4),test_case_index);
+ if(mem_read_value != MEM_TEST_PATTERN0){
+ SSDVT_FAIL_MSG(mem_read_value, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 1;
+
+ //case1: write 0xFFFFFFFF (1x/1x)
+ for(write_idx = 0; write_idx < memory_size/4; write_idx++)
+ {
+ *((volatile kal_uint32*)(memory_base_addr+write_idx*4)) = MEM_TEST_PATTERN1;
+ mem_read_value = *((volatile kal_uint32*)(memory_base_addr+write_idx*4));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*4),test_case_index);
+ if(mem_read_value != MEM_TEST_PATTERN1){
+ SSDVT_FAIL_MSG(mem_read_value, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 2;
+
+ //case2: write 0xA5A5A5A5 (1x/1x)
+ for(write_idx = 0; write_idx < memory_size/4; write_idx++)
+ {
+ *((volatile kal_uint32*)(memory_base_addr+write_idx*4)) = MEM_TEST_PATTERN2;
+ mem_read_value = *((volatile kal_uint32*)(memory_base_addr+write_idx*4));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*4),test_case_index);
+ if(mem_read_value != MEM_TEST_PATTERN2){
+ SSDVT_FAIL_MSG(mem_read_value, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 3;
+
+ //case3: write 0x5A5A5A5A (1x/1x)
+ for(write_idx = 0; write_idx < memory_size/4; write_idx++)
+ {
+ *((volatile kal_uint32*)(memory_base_addr+write_idx*4)) = MEM_TEST_PATTERN3;
+ mem_read_value = *((volatile kal_uint32*)(memory_base_addr+write_idx*4));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*4),test_case_index);
+ if(mem_read_value != MEM_TEST_PATTERN3){
+ SSDVT_FAIL_MSG(mem_read_value, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 4;
+
+ //case4: write incremental pattern (1x/1x)
+ volatile kal_uint32 INC_PATTERN = 1;
+ for(write_idx = 0; write_idx < memory_size/4; write_idx++)
+ {
+ *((volatile kal_uint32*)(memory_base_addr+write_idx*4)) = INC_PATTERN;
+ mem_read_value = *((volatile kal_uint32*)(memory_base_addr+write_idx*4));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*4),test_case_index);
+ if(mem_read_value != INC_PATTERN){
+ SSDVT_FAIL_MSG(mem_read_value, write_idx, test_case_index);
+ }
+ INC_PATTERN++;
+ }
+
+ test_case_index = 5;
+
+ //case5: write 0 (2x/2x)
+ for(write_idx = 0; write_idx < memory_size/8; write_idx++)
+ {
+ *((volatile kal_uint64*)(memory_base_addr+write_idx*8)) = MEM_TEST_PATTERN0;
+ mem_read_value_64 = *((volatile kal_uint64*)(memory_base_addr+write_idx*8));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*8),test_case_index);
+ if(mem_read_value_64 != MEM_TEST_PATTERN0){
+ SSDVT_FAIL_MSG((kal_uint32)mem_read_value_64, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 6;
+
+ //case6: write 0xFFFFFFFFFFFFFFFF (2x/2x)
+ for(write_idx = 0; write_idx < memory_size/8; write_idx++)
+ {
+ *((volatile kal_uint64*)(memory_base_addr+write_idx*8)) = MEM_TEST_PATTERN1_64;
+ mem_read_value_64 = *((volatile kal_uint64*)(memory_base_addr+write_idx*8));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*8),test_case_index);
+ if(mem_read_value_64 != MEM_TEST_PATTERN1_64){
+ SSDVT_FAIL_MSG((kal_uint32)mem_read_value_64, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 7;
+
+ //case7: write 0xA5A5A5A5A5A5A5A5 (2x/2x)
+ for(write_idx = 0; write_idx < memory_size/8; write_idx++)
+ {
+ *((volatile kal_uint64*)(memory_base_addr+write_idx*8)) = MEM_TEST_PATTERN2_64;
+ mem_read_value_64 = *((volatile kal_uint64*)(memory_base_addr+write_idx*8));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*8),test_case_index);
+ if(mem_read_value_64 != MEM_TEST_PATTERN2_64){
+ SSDVT_FAIL_MSG((kal_uint32)mem_read_value_64, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 8;
+
+ //case8: write 0x5A5A5A5A5A5A5A5A (2x/2x)
+ for(write_idx = 0; write_idx < memory_size/8; write_idx++)
+ {
+ *((volatile kal_uint64*)(memory_base_addr+write_idx*8)) = MEM_TEST_PATTERN3_64;
+ mem_read_value_64 = *((volatile kal_uint64*)(memory_base_addr+write_idx*8));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*8),test_case_index);
+ if(mem_read_value_64 != MEM_TEST_PATTERN3_64){
+ SSDVT_FAIL_MSG((kal_uint32)mem_read_value_64, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 9;
+
+ //case9: write incremental pattern (2x/2x)
+ volatile kal_uint64 INC_PATTERN_64 = 1;
+ for(write_idx = 0; write_idx < memory_size/8; write_idx++)
+ {
+ *((volatile kal_uint64*)(memory_base_addr+write_idx*8)) = INC_PATTERN_64;
+ mem_read_value_64 = *((volatile kal_uint64*)(memory_base_addr+write_idx*8));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*8),test_case_index);
+ if(mem_read_value_64 != INC_PATTERN_64){
+ SSDVT_FAIL_MSG((kal_uint32)mem_read_value_64, write_idx, test_case_index);
+ }
+ INC_PATTERN++;
+ }
+
+ test_case_index = 10;
+}
+
+#if defined(__CSIF_DRV_TEST__)
+void CSIF_C2S_IRQ_SET_test(void)
+{
+ // enable all c2s_IRQ
+ /*
+ for (int i=CSIF_ENUM_C2S_N0; i<CSIF_ENUM_ALL_C2S_INT_NUM; i++){
+ CSIF_REG_WRITE(CSIF_C2S_IRQ_ENABLE + i*CSIF_C2S_IRQ_SIZE, 0xFFFFFFFF);
+ }
+ */
+
+ csif_uint32 expect_c2s_status[CSIF_ENUM_ALL_C2S_INT_NUM] = {0};
+ csif_uint32 expect_c2s_masked_status[CSIF_ENUM_ALL_C2S_INT_NUM] = {0};
+ volatile csif_uint32 c2s_status_read = 0;
+ volatile csif_uint32 c2s_masked_status_read = 0;
+ for(int i = CSIF_ENUM_C2S_N0; i< CSIF_ENUM_ALL_C2S_INT_NUM; i++)
+ {
+ for(int bit_i = 0; bit_i < CSIF_C2S_Interrupt_Num[i]; bit_i++)
+ {
+ expect_c2s_status[i] = expect_c2s_status[i] | (0x1 << bit_i);
+ expect_c2s_masked_status[i] = expect_c2s_masked_status[i] | (0x1 << bit_i);
+ CSIF_C2S_SWI_Set(i, bit_i);
+ c2s_status_read = CSIF_C2S_SWI_Read(i);
+ c2s_masked_status_read = CSIF_C2S_SWI_MASKED_Read(i);
+ if(c2s_status_read != expect_c2s_status[i]){
+ SSDVT_FAIL_MSG(c2s_status_read, 0xAAA00000 | (i << 8) | bit_i, test_case_index);
+ }
+ // NOTE!! not sure mcore state here!
+ /*
+ if(c2s_masked_status_read != expect_c2s_masked_status[i])
+ {
+ SSDVT_FAIL_MSG(c2s_masked_status_read, 0xAAA20000 | (i << 8) | bit_i, test_case_index);
+ }
+ */
+ }
+ }
+
+ // disable all c2s_IRQ
+ /*
+ for (int i=CSIF_ENUM_C2S_N0; i<CSIF_ENUM_ALL_C2S_INT_NUM; i++){
+ CSIF_REG_WRITE(CSIF_C2S_IRQ_ENABLE + i*CSIF_C2S_IRQ_SIZE, 0x0);
+ }
+ */
+}
+
+void CSIF_S2C_IRQ_ENABLE_test(void)
+{
+ csif_uint32 expect_s2c_enable_status[CSIF_ENUM_ALL_S2C_INT_NUM] = {0};
+ volatile csif_uint32 s2c_enable_status_read = 0;
+ for(int i = CSIF_ENUM_S2C_N0; i< CSIF_ENUM_ALL_S2C_INT_NUM; i++)
+ {
+ for(int bit_i = 0; bit_i < CSIF_S2C_Interrupt_Num[i]; bit_i++)
+ {
+ expect_s2c_enable_status[i] = expect_s2c_enable_status[i] | (0x1 << bit_i);
+ CSIF_S2C_SWI_Enable(i, bit_i);
+ s2c_enable_status_read = CSIF_S2C_SWI_Enable_Read(i);
+ if(s2c_enable_status_read != expect_s2c_enable_status[i])
+ {
+ SSDVT_FAIL_MSG(s2c_enable_status_read, 0xAAB00000 | (i << 8) | bit_i, test_case_index);
+ }
+ }
+ }
+ for(int i = CSIF_ENUM_S2C_N0; i< CSIF_ENUM_ALL_S2C_INT_NUM; i++)
+ {
+ for(int bit_i = 0; bit_i < CSIF_S2C_Interrupt_Num[i]; bit_i++)
+ {
+ expect_s2c_enable_status[i] = expect_s2c_enable_status[i] & ~(0x1 << bit_i);
+ CSIF_S2C_SWI_Disable(i, bit_i);
+ s2c_enable_status_read = CSIF_S2C_SWI_Enable_Read(i);
+ if(s2c_enable_status_read != expect_s2c_enable_status[i])
+ {
+ SSDVT_FAIL_MSG(s2c_enable_status_read, 0xAAB10000 | (i << 8) | bit_i, test_case_index);
+ }
+ }
+ }
+ return;
+}
+
+void CSIF_C2S_IRQ_OVFL_test(void)
+{
+ volatile csif_uint32 irq_ovfl_read = 0;
+ //disable L1 error type (27 error, 2018/3/21)
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0);
+
+ for(int i = CSIF_ENUM_C2S_N0; i< CSIF_ENUM_ALL_C2S_INT_NUM; i++)
+ {
+ for(int bit_i = 0; bit_i < CSIF_C2S_Interrupt_Num[i]; bit_i++)
+ {
+ //CSIF_C2S_SWI_Set(i, bit_i);// c2s_irq may be set due to S2C_Set test, but still set twice first
+ CSIF_C2S_SWI_Set(i, bit_i);
+ irq_ovfl_read = CSIF_C2S_Overflow_Read(i);
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ if(bit_i < 16) // bit 0~15 irq_ovfl_allowed is False
+#else
+ if(bit_i < 32) // bit 0~31 irq_ovfl_allowed is False
+#endif
+ {
+ if((irq_ovfl_read & (0x1 << bit_i)) != 0)
+ {
+ SSDVT_FAIL_MSG(irq_ovfl_read, 0xAADF0000 | (i << 8) | bit_i, test_case_index);
+ }
+ }
+ else
+ {
+ if((irq_ovfl_read & (0x1 << bit_i)) == 0)
+ {
+ SSDVT_FAIL_MSG(irq_ovfl_read, 0xAAD00000 | (i << 8) | bit_i, test_case_index);
+ }
+ }
+ CSIF_C2S_Overflow_Clear(i, bit_i);
+ irq_ovfl_read = CSIF_C2S_Overflow_Read(i);
+ if((irq_ovfl_read & (0x1 << bit_i)) != 0)
+ {
+ SSDVT_FAIL_MSG(irq_ovfl_read, 0xAAD10000 | (i << 8) | bit_i, test_case_index);
+ }
+ }
+ }
+
+ //enable L1 error type (27 error, 2018/3/21)
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, CSIF_L1_ERROR_MASK);
+
+ return;
+}
+
+void CSIF_MPU_SET_test(void)
+{
+ volatile csif_uint32 read_mpu_start = 0;
+ volatile csif_uint32 read_mpu_range = 0;
+ volatile csif_uint32 read_mpu_type = 0;
+
+ csif_uint32 set_start_value = 0;
+ csif_uint32 set_range_value = 0;
+
+ for(int i = CSIF_DSP_MPU0; i < CSIF_MPU_TOTAL_NUM; i++)
+ {
+ for(int t = CSIF_MPU_READ; t < CSIF_MPU_TOTAL_TYPE; t++)
+ {
+ set_start_value = CSIF_DSM_BASE + 0x8;
+ set_range_value = 0x4000-0x8;
+
+ CSIF_MPU_Set(i, set_start_value, set_range_value, t);
+
+ CSIF_REG_READ(CSIF_MPU_START_ADDR + i*CSIF_MPU_SIZE, read_mpu_start);
+ CSIF_REG_READ(CSIF_MPU_RANGE + i*CSIF_MPU_SIZE, read_mpu_range);
+
+ read_mpu_type = (read_mpu_range & CSIF_MPU_TYPE_M) >> CSIF_MPU_TYPE_P;
+ read_mpu_range = (read_mpu_range & CSIF_MPU_RANGE_M) >> CSIF_MPU_RANGE_P;
+ if(read_mpu_start != (set_start_value & CSIF_MPU_START_M) )
+ {
+ SSDVT_FAIL_MSG(read_mpu_start, 0xAAE00000 | (i << 8) | t, test_case_index);
+ }
+ if(read_mpu_range != set_range_value)
+ {
+ SSDVT_FAIL_MSG(read_mpu_range, 0xAAE10000 | (i << 8) | t, test_case_index);
+ }
+ if(read_mpu_type != t)
+ {
+ SSDVT_FAIL_MSG(read_mpu_type, 0xAAE20000 | (i << 8) | t, test_case_index);
+ }
+
+ set_start_value = 0x0;
+ set_range_value = 0x0;
+
+ CSIF_MPU_Set(i, set_start_value, set_range_value, t);
+
+ CSIF_REG_READ(CSIF_MPU_START_ADDR + i*CSIF_MPU_SIZE, read_mpu_start);
+ CSIF_REG_READ(CSIF_MPU_RANGE + i*CSIF_MPU_SIZE, read_mpu_range);
+
+ read_mpu_type = (read_mpu_range & CSIF_MPU_TYPE_M) >> CSIF_MPU_TYPE_P;
+ read_mpu_range = (read_mpu_range & CSIF_MPU_RANGE_M) >> CSIF_MPU_RANGE_P;
+ if(read_mpu_start != (set_start_value & CSIF_MPU_START_M) )
+ {
+ SSDVT_FAIL_MSG(read_mpu_start, 0xAAEA0000 | (i << 8) | t, test_case_index);
+ }
+ if(read_mpu_range != set_range_value)
+ {
+ SSDVT_FAIL_MSG(read_mpu_range, 0xAAEB0000 | (i << 8) | t, test_case_index);
+ }
+ if(read_mpu_type != t)
+ {
+ SSDVT_FAIL_MSG(read_mpu_type, 0xAAEC0000 | (i << 8) | t, test_case_index);
+ }
+ }
+ }
+ return;
+}
+
+void CSIF_MAILBOX_C2S_SEND_RECV_test(void)
+{
+ volatile CSIF_MAILBOX_STATUS_t mailbox_status_read;
+ volatile csif_uint32 mailbox_max_usage_read;
+
+ volatile csif_uint32 previous_mailbox_r_idx_read;
+ volatile csif_uint32 previous_mailbox_w_idx_read;
+ volatile csif_uint32 previous_mailbox_mail_num_read;
+ volatile csif_uint32 previous_mailbox_max_usage_read;
+
+ volatile csif_uint32 read_mail = 0;
+
+ csif_uint32 mailboxMask = 0;
+
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ for(int i = CSIF_MAILBOX_C2S_SS_TEST_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#else
+ for(int i = CSIF_MAILBOX_C2S_C2S_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#endif
+ {
+ mailbox_status_read = CSIF_MAILBOX_C2S_Status_Read(i);
+ mailbox_max_usage_read = CSIF_MAILBOX_C2S_Max_FIFO_Usage_Read(i);
+ if(mailbox_status_read.r_idx != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.r_idx, 0xAAF00000 | (i << 8) | 0xFF , test_case_index);
+ }
+ if(mailbox_status_read.w_idx != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.w_idx, 0xAAF10000 | (i << 8) | 0xFF, test_case_index);
+ }
+ if(mailbox_status_read.mail_num != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.mail_num, 0xAAF20000 | (i << 8) | 0xFF, test_case_index);
+ }
+ if(mailbox_max_usage_read != 0){
+ SSDVT_FAIL_MSG(mailbox_max_usage_read, 0xAAF30000 | (i << 8) | 0xFF, test_case_index);
+ }
+ previous_mailbox_r_idx_read = mailbox_status_read.r_idx;
+ previous_mailbox_w_idx_read = mailbox_status_read.w_idx;
+ previous_mailbox_mail_num_read = mailbox_status_read.mail_num;
+ previous_mailbox_max_usage_read = mailbox_max_usage_read;
+
+ if(csif_mailbox_entry_num_table[i] == 256){
+ mailboxMask = MAILBOX_256_WRAP_MASK;
+ }else if(csif_mailbox_entry_num_table[i] == 64){
+ mailboxMask = MAILBOX_64_WRAP_MASK;
+ }
+ // C2S mailbox send test
+ for(int m = 0; m < csif_mailbox_entry_num_table[i]; m++)
+ {
+ CSIF_MAILBOX_C2S_Send(i, m);
+ mailbox_status_read = CSIF_MAILBOX_C2S_Status_Read(i);
+ mailbox_max_usage_read = CSIF_MAILBOX_C2S_Max_FIFO_Usage_Read(i);
+
+ if(mailbox_status_read.r_idx != previous_mailbox_r_idx_read){
+ SSDVT_FAIL_MSG(mailbox_status_read.r_idx, 0xAAFA0000 | (i << 8) | m, test_case_index);
+ }
+
+ if(mailbox_status_read.w_idx != ((previous_mailbox_w_idx_read + 1) & mailboxMask)){
+ SSDVT_FAIL_MSG(mailbox_status_read.w_idx, 0xAAFB0000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_status_read.mail_num != previous_mailbox_mail_num_read + 1){
+ SSDVT_FAIL_MSG(mailbox_status_read.mail_num, 0xAAFC0000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_max_usage_read != previous_mailbox_max_usage_read + 1){
+ SSDVT_FAIL_MSG(mailbox_max_usage_read, 0xAAF40000 | (i << 8) | m, test_case_index);
+ }
+
+ previous_mailbox_r_idx_read = mailbox_status_read.r_idx;
+ previous_mailbox_w_idx_read = mailbox_status_read.w_idx;
+ previous_mailbox_mail_num_read = mailbox_status_read.mail_num;
+ previous_mailbox_max_usage_read = mailbox_max_usage_read;
+ }
+
+
+ // C2S mailbox recv test
+ for(int m = 0; m < csif_mailbox_entry_num_table[i]; m++)
+ {
+ read_mail = CSIF_MAILBOX_C2S_Read(i);
+ mailbox_status_read = CSIF_MAILBOX_C2S_Status_Read(i);
+ mailbox_max_usage_read = CSIF_MAILBOX_C2S_Max_FIFO_Usage_Read(i);
+
+ if(read_mail != m ){
+ SSDVT_FAIL_MSG(read_mail, 0xAAF60000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_status_read.r_idx != ((previous_mailbox_r_idx_read + 1) & mailboxMask )){
+ SSDVT_FAIL_MSG(mailbox_status_read.r_idx, 0xAAF0000 | (i << 8) | m, test_case_index);
+ }
+
+ if(mailbox_status_read.w_idx != ((previous_mailbox_w_idx_read) & mailboxMask)){
+ SSDVT_FAIL_MSG(mailbox_status_read.w_idx, 0xAAFE0000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_status_read.mail_num != previous_mailbox_mail_num_read - 1){
+ SSDVT_FAIL_MSG(mailbox_status_read.mail_num, 0xAAFF0000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_max_usage_read != previous_mailbox_max_usage_read ){
+ SSDVT_FAIL_MSG(mailbox_max_usage_read, 0xAAF50000 | (i << 8) | m, test_case_index);
+ }
+
+ previous_mailbox_r_idx_read = mailbox_status_read.r_idx;
+ previous_mailbox_w_idx_read = mailbox_status_read.w_idx;
+ previous_mailbox_mail_num_read = mailbox_status_read.mail_num;
+ previous_mailbox_max_usage_read = mailbox_max_usage_read;
+ }
+ }
+ return;
+}
+
+void CSIF_MAILBOX_S2C_RECV_test(void)
+{
+ volatile CSIF_MAILBOX_STATUS_t mailbox_status_read;
+ volatile csif_uint32 mailbox_max_usage_read;
+
+ volatile csif_uint32 read_mail = 0;
+
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ for(int i = CSIF_MAILBOX_S2C_SS_TEST_ID3; i < CSIF_MAILBOX_S2C_LAST_ID; i++)
+#else
+ for(int i = CSIF_MAILBOX_S2C_S2C_ID0; i < CSIF_MAILBOX_S2C_LAST_ID; i++)
+#endif
+ {
+ mailbox_status_read = CSIF_MAILBOX_S2C_Status_Read(i);
+ mailbox_max_usage_read = CSIF_MAILBOX_S2C_Max_FIFO_Usage_Read(i);
+ if(mailbox_status_read.r_idx != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.r_idx, 0xAB000000 | (i << 8) | 0xFF , test_case_index);
+ }
+ if(mailbox_status_read.w_idx != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.w_idx, 0xAB010000 | (i << 8) | 0xFF, test_case_index);
+ }
+ if(mailbox_status_read.mail_num != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.mail_num, 0xAB020000 | (i << 8) | 0xFF, test_case_index);
+ }
+ if(mailbox_max_usage_read != 0){
+ SSDVT_FAIL_MSG(mailbox_max_usage_read, 0xAB030000 | (i << 8) | 0xFF, test_case_index);
+ }
+
+ for(int m = 0; m < 5; m++)
+ {
+ read_mail = CSIF_MAILBOX_S2C_Read(i);
+ mailbox_status_read = CSIF_MAILBOX_S2C_Status_Read(i);
+ mailbox_max_usage_read = CSIF_MAILBOX_S2C_Max_FIFO_Usage_Read(i);
+ /*
+ printf("i = %d, m = %d; w_idx = %d, r_idx = %d, mailnum = %d, max = %d, read_mail = %d\n", i, m,
+ mailbox_status_read.w_idx, mailbox_status_read.r_idx, mailbox_status_read.mail_num,
+ mailbox_max_usage_read, read_mail );
+ ` */
+ if(read_mail != CSIF_MAILBOX_EMPTY_VALUE){
+ SSDVT_FAIL_MSG(read_mail, 0xAB120000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_status_read.r_idx != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.r_idx, 0xAB130000 | (i << 8) | m , test_case_index);
+ }
+ if(mailbox_status_read.w_idx != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.w_idx, 0xAB140000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_status_read.mail_num != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.mail_num, 0xAB150000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_max_usage_read != 0){
+ SSDVT_FAIL_MSG(mailbox_max_usage_read, 0xAB160000 | (i << 8) | m, test_case_index);
+ }
+ }
+ }
+ return;
+}
+
+void CSIF_OLPDET_test(void)
+{
+ csif_uint32 set_size = 0;
+ csif_uint32 clr_size = 0;
+ volatile csif_uint32 read_inuse_mem_size = 0;
+ csif_uint32 expect_mem_size = 0;
+
+ // set size = 8
+ set_size = 8;
+ for(int i = 0; i < CSIF_DSM_SIZE/set_size; i++)
+ {
+ CSIF_OLPDET_Set(CSIF_DSM_BASE + set_size*i, set_size);
+ expect_mem_size = expect_mem_size + set_size;
+ read_inuse_mem_size = CSIF_Total_Inuse_Mem_Size();
+ if(read_inuse_mem_size != expect_mem_size)
+ {
+ SSDVT_FAIL_MSG(read_inuse_mem_size, 0xAC000000 | (i << 8) | set_size, expect_mem_size);
+ }
+ }
+ // clr by size = 1024
+ clr_size = 1024;
+ for(int i = 0; i < CSIF_DSM_SIZE/clr_size; i++)
+ {
+ CSIF_OLPDET_Clr(CSIF_DSM_BASE + clr_size*i, clr_size);
+ expect_mem_size = expect_mem_size - clr_size;
+ read_inuse_mem_size = CSIF_Total_Inuse_Mem_Size();
+ if(read_inuse_mem_size != expect_mem_size)
+ {
+ SSDVT_FAIL_MSG(read_inuse_mem_size, 0xAC010000 | (i << 8) | clr_size, expect_mem_size);
+ }
+ }
+ // set size = 1024
+ set_size = 1024;
+ for(int i = 0; i < CSIF_DSM_SIZE/set_size; i++)
+ {
+ CSIF_OLPDET_Set(CSIF_DSM_BASE + set_size*i, set_size);
+ expect_mem_size = expect_mem_size + set_size;
+ read_inuse_mem_size = CSIF_Total_Inuse_Mem_Size();
+ if(read_inuse_mem_size != expect_mem_size)
+ {
+ SSDVT_FAIL_MSG(read_inuse_mem_size, 0xAC020000 | (i << 8) | set_size, expect_mem_size);
+ }
+ }
+ // clr by size = 8
+ clr_size = 8;
+ for(int i = 0; i < CSIF_DSM_SIZE/clr_size; i++)
+ {
+ CSIF_OLPDET_Clr(CSIF_DSM_BASE + clr_size*i, clr_size);
+ expect_mem_size = expect_mem_size - clr_size;
+ read_inuse_mem_size = CSIF_Total_Inuse_Mem_Size();
+ if(read_inuse_mem_size != expect_mem_size)
+ {
+ SSDVT_FAIL_MSG(read_inuse_mem_size, 0xAC030000 | (i << 8) | clr_size, expect_mem_size);
+ }
+ }
+ return;
+}
+
+void CSIF_IDLE_IRQ_ENABLE_test(void)
+{
+ //volatile csif_uint32 idle_read;
+ volatile csif_uint32 idle_enable_read = 0;
+ volatile csif_uint32 previous_idle_enable = 0;
+
+ // disable S2C_IRQ ENABLE
+ for (int i=CSIF_ENUM_S2C_N0; i<CSIF_ENUM_ALL_S2C_INT_NUM; i++){
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + i*CSIF_S2C_IRQ_SIZE, 0x0);
+ }
+ //disable CSIF s2c_WFI_enable mask (write 10 bits on each enable mask, 4 th per core and 1 AND/OR bit per core)
+ for (int i=0; i<CSIF_S2C_IDLE_IRQ_NUM; i++){
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + i*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+ }
+
+ //idle_read = CSIF_CORE_IDLE_Read();
+ // NOTE!!! not sure what's mcore state here!
+ /*
+ if((idle_read & (0xF << (4*THIS_MCORE_ID))) != 0x0){
+ SSDVT_FAIL_MSG(idle_read, 0xAE000000 | THIS_MCORE_ID , test_case_index);
+ }
+ */
+
+ for(int i = 0; i < CSIF_S2C_IDLE_IRQ_NUM; i++)
+ {
+ idle_enable_read = CSIF_IDLE_ENABLE_Read(i);
+ previous_idle_enable = idle_enable_read;
+ if(idle_enable_read != 0x0){
+ SSDVT_FAIL_MSG(idle_enable_read, 0xAE010000 | i<<8 , test_case_index);
+ }
+ for(int bit_i = 0; bit_i < 10; bit_i++)
+ {
+ CSIF_IDLE_ENABLE_Set(i, 0x1 << bit_i);
+ idle_enable_read = CSIF_IDLE_ENABLE_Read(i);
+ if(idle_enable_read != (previous_idle_enable | (0x1 << bit_i)))
+ {
+ SSDVT_FAIL_MSG(idle_enable_read, 0xAE020000 | i<<8 | bit_i , test_case_index);
+ }
+ previous_idle_enable = idle_enable_read;
+ }
+ }
+
+ for(int i = 0; i < CSIF_S2C_IDLE_IRQ_NUM; i++)
+ {
+ idle_enable_read = CSIF_IDLE_ENABLE_Read(i);
+ previous_idle_enable = idle_enable_read;
+ if(idle_enable_read != 0x3FF){
+ SSDVT_FAIL_MSG(idle_enable_read, 0xAE030000 | i<<8 , test_case_index);
+ }
+ for(int bit_i = 0; bit_i < 10; bit_i++)
+ {
+ CSIF_IDLE_ENABLE_Clr(i, 0x1 << bit_i);
+ idle_enable_read = CSIF_IDLE_ENABLE_Read(i);
+ if(idle_enable_read != (0x3FF & (previous_idle_enable & ~(0x1 << bit_i))))
+ {
+ SSDVT_FAIL_MSG(idle_enable_read, 0xAE040000 | i<<8 | bit_i , test_case_index);
+ }
+ previous_idle_enable = idle_enable_read;
+ }
+ }
+
+ //open mask of CSIF s2c_WFI_enable mask (write 10 bits on each enable mask, 4 th per core and 1 AND/OR bit per core)
+ //WFI_irq0
+ //CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_SET + 0*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+ //WFI_irq1
+ //CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_SET + 1*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+
+ return;
+}
+
+kal_uint32 olpdet_driver_expect_mum_arr[OLPDET_MUM_BIT_NUM/32] = {0};
+kal_uint32 olpdet_driver_dump_mum_arr[OLPDET_MUM_BIT_NUM/32] = {0};
+
+void CSIF_OLPDET_MULTIPLE_TEST(){
+ CSIF_OLPDET_CONFIG_t olpdet_set_array[MULTIPLE_REG_TEST_NUM];
+ CSIF_OLPDET_CONFIG_t* olpdet_set_array_ptr;
+ kal_uint32 mum_idx = 0;
+ kal_uint32 mum_content = 0;
+
+ // OLPDET_Set
+ for(int i = 0; i<MULTIPLE_REG_TEST_NUM; i++ ){
+ // prepare API argument
+ olpdet_set_array[i].addr = CSIF_DSM_BASE + MULTIPLE_REG_TEST_OFFSET[i];
+ olpdet_set_array[i].size = MULTIPLE_REG_TEST_SIZE[i];
+ }
+ olpdet_set_array_ptr = &olpdet_set_array[0];
+ CSIF_OLPDET_Multiple_Set(MULTIPLE_REG_TEST_NUM, olpdet_set_array_ptr);
+
+ /* dump OLPDET to check */
+ //1: offset 0, + size: 0x400(1024)
+ olpdet_driver_expect_mum_arr[0] = 0xFFFFFFFF; //0 ~ 31
+ olpdet_driver_expect_mum_arr[1] = 0xFFFFFFFF; //32 ~ 63
+ olpdet_driver_expect_mum_arr[2] = 0xFFFFFFFF; //64 ~ 95
+ olpdet_driver_expect_mum_arr[3] = 0xFFFFFFFF; //96 ~ 127
+ //2: offset 0x800, + size: 0x100
+ olpdet_driver_expect_mum_arr[8] = 0xFFFFFFFF;
+ //3: offset 0x1000, + size: 0x8
+ olpdet_driver_expect_mum_arr[16] = 0x00000001;
+ //4: offset 0x2000, + size: 0x200
+ olpdet_driver_expect_mum_arr[32] = 0xFFFFFFFF;
+ olpdet_driver_expect_mum_arr[33] = 0xFFFFFFFF;
+ //5: offset 0x3FE0, + size: 0x20
+ olpdet_driver_expect_mum_arr[63] = 0xF0000000;
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX, mum_idx);
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM, mum_content);
+ olpdet_driver_dump_mum_arr[mum_idx] = mum_content;
+ }
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ test_case_index = test_case_index | (dump_i<<4);
+ if(olpdet_driver_dump_mum_arr[dump_i] != olpdet_driver_expect_mum_arr[dump_i]){
+ SSDVT_FAIL_MSG(olpdet_driver_dump_mum_arr[dump_i], olpdet_driver_expect_mum_arr[dump_i], dump_i);
+ }
+ }
+ // clear error and reset debug mum idx
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+ /* end of dump OLPDET to check */
+
+ // OLPDET_Clr 1
+ CSIF_OLPDET_CONFIG_t olpdet_clr_array1[MULTIPLE_REG_TEST_NUM_SUB_1];
+ CSIF_OLPDET_CONFIG_t* olpdet_clr_array_ptr1;
+ for(int i = 0; i<MULTIPLE_REG_TEST_NUM_SUB_1; i++ ){
+ // prepare API argument
+ olpdet_clr_array1[i].addr = CSIF_DSM_BASE + MULTIPLE_REG_TEST_OFFSET[i];
+ olpdet_clr_array1[i].size = MULTIPLE_REG_TEST_SIZE[i];
+ }
+ olpdet_clr_array_ptr1 = &olpdet_clr_array1[0];
+ CSIF_OLPDET_Multiple_Clr(MULTIPLE_REG_TEST_NUM_SUB_1, olpdet_clr_array_ptr1);
+
+ /* dump OLPDET to check */
+ //1: offset 0, + size: 0x400(1024)
+ olpdet_driver_expect_mum_arr[0] = 0x0; //0 ~ 31
+ olpdet_driver_expect_mum_arr[1] = 0x0; //32 ~ 63
+ olpdet_driver_expect_mum_arr[2] = 0x0; //64 ~ 95
+ olpdet_driver_expect_mum_arr[3] = 0x0; //96 ~ 127
+ //2: offset 0x800, + size: 0x100
+ olpdet_driver_expect_mum_arr[8] = 0x0;
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX, mum_idx);
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM, mum_content);
+ olpdet_driver_dump_mum_arr[mum_idx] = mum_content;
+ }
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ test_case_index = test_case_index | (dump_i<<4);
+ if(olpdet_driver_dump_mum_arr[dump_i] != olpdet_driver_expect_mum_arr[dump_i]){
+ SSDVT_FAIL_MSG(olpdet_driver_dump_mum_arr[dump_i], olpdet_driver_expect_mum_arr[dump_i], dump_i);
+ }
+ }
+ // clear error and reset debug mum idx
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+ /* end of dump OLPDET to check */
+
+ // OLPDET_Clr 2
+ CSIF_OLPDET_CONFIG_t olpdet_clr_array2[MULTIPLE_REG_TEST_NUM_SUB_2];
+ CSIF_OLPDET_CONFIG_t* olpdet_clr_array_ptr2;
+ for(int i = 0; i<MULTIPLE_REG_TEST_NUM_SUB_2; i++ ){
+ // prepare API argument
+ olpdet_clr_array2[i].addr = CSIF_DSM_BASE + MULTIPLE_REG_TEST_OFFSET[i+MULTIPLE_REG_TEST_NUM_SUB_1];
+ olpdet_clr_array2[i].size = MULTIPLE_REG_TEST_SIZE[i+MULTIPLE_REG_TEST_NUM_SUB_1];
+ }
+ olpdet_clr_array_ptr2 = &olpdet_clr_array2[0];
+ CSIF_OLPDET_Multiple_Clr(MULTIPLE_REG_TEST_NUM_SUB_2, olpdet_clr_array_ptr2);
+
+ /* dump OLPDET to check */
+ //3: offset 0x1000, + size: 0x8
+ olpdet_driver_expect_mum_arr[16] = 0x0;
+ //4: offset 0x2000, + size: 0x200
+ olpdet_driver_expect_mum_arr[32] = 0x0;
+ olpdet_driver_expect_mum_arr[33] = 0x0;
+ //5: offset 0x3FE0, + size: 0x20
+ olpdet_driver_expect_mum_arr[63] = 0x0;
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX, mum_idx);
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM, mum_content);
+ olpdet_driver_dump_mum_arr[mum_idx] = mum_content;
+ }
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ test_case_index = test_case_index | (dump_i<<4);
+ if(olpdet_driver_dump_mum_arr[dump_i] != olpdet_driver_expect_mum_arr[dump_i]){
+ SSDVT_FAIL_MSG(olpdet_driver_dump_mum_arr[dump_i], olpdet_driver_expect_mum_arr[dump_i], dump_i);
+ }
+ }
+ // clear error and reset debug mum idx
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+ /* end of dump OLPDET to check */
+}
+
+csif_uint32 mail_golden_array[CSIF_MAILBOX_C2S_LAST_ID][MULTIPLE_MAIL_TEST_NUM] = {{0}};
+void CSIF_MAILBOX_MULTIPLE_TEST()
+{
+ csif_uint32 shift_i = 0;
+ csif_uint32 base_i = 0;
+ csif_uint32 total_mail_length = 0;
+ csif_uint32 mail_read_idx = 0;
+ volatile csif_uint32 read_mail = 0;
+ volatile CSIF_MAILBOX_STATUS_t mailbox_status_read;
+
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ CSIF_MAIL_INFO_t mail_info_array[(CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_SS_TEST_ID0)*MULTIPLE_MAIL_TEST_NUM]= {0};
+ total_mail_length = (CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_SS_TEST_ID0)*MULTIPLE_MAIL_TEST_NUM;
+ for(int i = CSIF_MAILBOX_C2S_SS_TEST_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#else
+ CSIF_MAIL_INFO_t mail_info_array[(CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_C2S_ID0)*MULTIPLE_MAIL_TEST_NUM]= {0};
+ total_mail_length = (CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_C2S_ID0)*MULTIPLE_MAIL_TEST_NUM;
+ for(int i = CSIF_MAILBOX_C2S_C2S_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#endif
+ {
+ for(int mail_idx = 0; mail_idx < MULTIPLE_MAIL_TEST_NUM; mail_idx++)
+ {
+ mail_info_array[(shift_i*MULTIPLE_MAIL_TEST_NUM + mail_idx)].mail = MAILBOX_TEST_PREFIX_PATTERN | (i << 12) | (mail_idx);
+ mail_info_array[(shift_i*MULTIPLE_MAIL_TEST_NUM + mail_idx)].mID = i;
+ mail_golden_array[i][mail_idx] = MAILBOX_TEST_PREFIX_PATTERN | (i << 12) | (mail_idx);
+ }
+ shift_i++;
+ }
+ CSIF_MAILBOX_C2S_Multiple_Send(total_mail_length, &mail_info_array[0]);
+
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ for(int i = CSIF_MAILBOX_C2S_SS_TEST_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#else
+ for(int i = CSIF_MAILBOX_C2S_C2S_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#endif
+ {
+ mailbox_status_read = CSIF_MAILBOX_C2S_Status_Read(i);
+ if(mailbox_status_read.mail_num != MULTIPLE_MAIL_TEST_NUM){
+ SSDVT_FAIL_MSG(mailbox_status_read.mail_num, MULTIPLE_MAIL_TEST_NUM, i);
+ }
+ mail_read_idx = 0;
+ read_mail = CSIF_MAILBOX_C2S_Read(i);
+ while(read_mail != CSIF_MAILBOX_EMPTY_VALUE)
+ {
+ if(read_mail != mail_golden_array[i][mail_read_idx]){
+ SSDVT_FAIL_MSG(read_mail, mail_read_idx, i);
+ }
+ read_mail = CSIF_MAILBOX_C2S_Read(i);
+ mail_read_idx++;
+ }
+ }
+}
+
+csif_uint32 irq_golden_array[CSIF_ENUM_ALL_C2S_INT_NUM] = {0};
+void CSIF_MAILBOX_MULTIPLE_IRQ_MULTIPLE_TEST()
+{
+ csif_uint32 shift_i = 0;
+ csif_uint32 base_i = 0;
+ csif_uint32 total_mail_length = 0;
+ csif_uint32 mail_read_idx = 0;
+ volatile csif_uint32 read_mail = 0;
+ volatile CSIF_MAILBOX_STATUS_t mailbox_status_read;
+
+// Mailbox multiple setting
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ CSIF_MAIL_INFO_t mail_info_array[(CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_SS_TEST_ID0)*MULTIPLE_MAIL_TEST_NUM]= {0};
+ total_mail_length = (CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_SS_TEST_ID0)*MULTIPLE_MAIL_TEST_NUM;
+ for(int i = CSIF_MAILBOX_C2S_SS_TEST_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#else
+ CSIF_MAIL_INFO_t mail_info_array[(CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_C2S_ID0)*MULTIPLE_MAIL_TEST_NUM]= {0};
+ total_mail_length = (CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_C2S_ID0)*MULTIPLE_MAIL_TEST_NUM;
+ for(int i = CSIF_MAILBOX_C2S_C2S_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#endif
+ {
+ for(int mail_idx = 0; mail_idx < MULTIPLE_MAIL_TEST_NUM; mail_idx++)
+ {
+ mail_info_array[(shift_i*MULTIPLE_MAIL_TEST_NUM + mail_idx)].mail = MAILBOX_TEST_PREFIX_PATTERN | (i << 12) | (mail_idx*2);
+ mail_info_array[(shift_i*MULTIPLE_MAIL_TEST_NUM + mail_idx)].mID = i;
+ mail_golden_array[i][mail_idx] = MAILBOX_TEST_PREFIX_PATTERN | (i << 12) | (mail_idx*2);
+ }
+ shift_i++;
+ }
+
+// IRQ multiple setting
+ csif_uint32 total_irq_length = 0;
+ csif_uint32 irq_ovfl_read = 0;
+ shift_i = 0;
+
+ //disable L1 error type (27 error, 2018/3/21)
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0); // For IRQ ovfl
+
+ CSIF_IRQ_INFO_t irq_info_array[(CSIF_ENUM_ALL_C2S_INT_NUM - CSIF_ENUM_C2S_N0)*MULTIPLE_IRQ_TEST_NUM]= {0};
+ total_irq_length = (CSIF_ENUM_ALL_C2S_INT_NUM - CSIF_ENUM_C2S_N0)*MULTIPLE_IRQ_TEST_NUM;
+
+ for(int i = CSIF_ENUM_C2S_N0; i< CSIF_ENUM_ALL_C2S_INT_NUM; i++)
+ {
+ for(int bit_i = 0; bit_i < MULTIPLE_IRQ_TEST_NUM; bit_i++)
+ {
+ irq_golden_array[i] = irq_golden_array[i] | (0x1 << (i + bit_i));
+ irq_info_array[(shift_i*MULTIPLE_IRQ_TEST_NUM+bit_i)].nID = i;
+ irq_info_array[(shift_i*MULTIPLE_IRQ_TEST_NUM+bit_i)].code = i + bit_i;
+ }
+ shift_i++;
+ }
+// Trigger API
+ CSIF_MAILBOX_C2S_Multiple_Send_C2S_SWI_Multiple_Set(total_mail_length, &mail_info_array[0], total_irq_length, &irq_info_array[0]);
+
+ // Check mail box multiple set
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ for(int i = CSIF_MAILBOX_C2S_SS_TEST_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#else
+ for(int i = CSIF_MAILBOX_C2S_C2S_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#endif
+ {
+ mailbox_status_read = CSIF_MAILBOX_C2S_Status_Read(i);
+ if(mailbox_status_read.mail_num != MULTIPLE_MAIL_TEST_NUM){
+ SSDVT_FAIL_MSG(mailbox_status_read.mail_num, MULTIPLE_MAIL_TEST_NUM, i);
+ }
+ mail_read_idx = 0;
+ read_mail = CSIF_MAILBOX_C2S_Read(i);
+ while(read_mail != CSIF_MAILBOX_EMPTY_VALUE)
+ {
+ if(read_mail != mail_golden_array[i][mail_read_idx]){
+ SSDVT_FAIL_MSG(read_mail, mail_read_idx, i);
+ }
+ read_mail = CSIF_MAILBOX_C2S_Read(i);
+ mail_read_idx++;
+ }
+ }
+
+// Check IRQ multiple set
+ // ALL C2S bit had been set by CSIF_C2S_IRQ_SET_test();
+ // so the bit we trigger in this test should be overflow case (based on irq_ovfl_allowed attribute in config file)
+ for(int i = CSIF_ENUM_C2S_N0; i< CSIF_ENUM_ALL_C2S_INT_NUM; i++)
+ {
+ for(int bit_i = 0; bit_i < MULTIPLE_IRQ_TEST_NUM; bit_i++)
+ {
+ irq_ovfl_read = CSIF_C2S_Overflow_Read(i);
+
+ if((irq_golden_array[i] & (0x1 << bit_i)) == 0) // this bit didn't been triggered
+ {
+ if(irq_ovfl_read & (0x1 << bit_i)){
+ SSDVT_FAIL_MSG(irq_ovfl_read, i, bit_i);
+ }
+
+ }else // this bit had been triggered
+ {
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ if(bit_i < 16) // bit 0~15 irq_ovfl_allowed is False
+#else
+ if(bit_i < 32) // bit 0~31 irq_ovfl_allowed is False
+#endif
+ {
+ if((irq_ovfl_read & (0x1 << bit_i)) != 0)
+ {
+ SSDVT_FAIL_MSG(irq_ovfl_read, i, bit_i);
+ }
+ }else
+ {
+ if((irq_ovfl_read & (0x1 << bit_i)) == 0)
+ {
+ SSDVT_FAIL_MSG(irq_ovfl_read, i, bit_i);
+ }
+ }
+ }
+ CSIF_C2S_Overflow_Clear(i, bit_i);
+ irq_ovfl_read = CSIF_C2S_Overflow_Read(i);
+ if((irq_ovfl_read & (0x1 << bit_i)) != 0)
+ {
+ SSDVT_FAIL_MSG(irq_ovfl_read, i, bit_i);
+ }
+ }
+ }
+
+ //enable L1 error type (27 error, 2018/3/21)
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, CSIF_L1_ERROR_MASK);
+}
+#endif // __CSIF_DRV_TEST__
+
+#if defined(__CSIF_DRV_TEST__)
+void csif_driver_test()
+{
+ test_case_index = 0xDD970001;
+ CSIF_C2S_IRQ_SET_test();
+ test_case_index = 0xDD970002;
+ //CSIF_S2C_IRQ_ENABLE_test();
+ test_case_index = 0xDD970003;
+ CSIF_C2S_IRQ_OVFL_test();
+ test_case_index = 0xDD970004;
+ //CSIF_MPU_SET_test();
+ test_case_index = 0xDD970005;
+ CSIF_MAILBOX_C2S_SEND_RECV_test();
+ test_case_index = 0xDD970006;
+ CSIF_MAILBOX_S2C_RECV_test();
+ test_case_index = 0xDD970007;
+ CSIF_OLPDET_test();
+ test_case_index = 0xDD970008;
+ CSIF_IDLE_IRQ_ENABLE_test();
+ test_case_index = 0xDD970009;
+ CSIF_OLPDET_MULTIPLE_TEST();
+ test_case_index = 0xDD97000A;
+ CSIF_MAILBOX_MULTIPLE_TEST();
+ test_case_index = 0xDD97000B;
+ CSIF_MAILBOX_MULTIPLE_IRQ_MULTIPLE_TEST();
+ test_case_index = 0xDD97000C;
+}
+#endif
+
+#if defined(__SSDVT_CSIF_TEST__)
+void CSIF_SSDVT()
+{
+#if defined(__CSIF_DRV_TEST__)
+
+#if defined(__CSIF_DVT_OLPDET__)
+ csif_olpdet_dvt_test();
+#endif
+ csif_mem_test();
+ //csif_irq_ovfl_test();
+#if !defined(__CSIF_DVT_OLPDET__) && !defined(__CSIF_DVT_REG_RW__)
+ csif_driver_test();
+#endif
+
+#endif
+#if defined(__CSIF_CROSS_CORE_TEST__)
+#if defined(__CSIF_SW_IRQ_TEST__)
+ IRQ_HANDLER_TYPE = CSIF_IRQ_HANDLER_IRQ_TEST;
+ cross_interrupt_test();
+#endif
+#if defined(__CSIF_IDLE_IRQ_TEST__)
+ #if defined(__CSIF_CROSS_CORE_MCORE1_ONLY__)
+ THIS_MCORE_ID = 1;
+ #else
+ THIS_MCORE_ID = 0;
+ #endif
+ IRQ_HANDLER_TYPE = CSIF_IRQ_HANDLER_IDLE_IRQ_TEST;
+ cross_idle_irq_test();
+#endif
+#if defined(__CSIF_MAILBOX_TEST__)
+ IRQ_HANDLER_TYPE = CSIF_IRQ_HANDLER_MAILBOX_TEST;
+ cross_mailbox_test();
+#endif
+#endif
+
+ return;
+}
+#endif
diff --git a/mcu/driver/devdrv/csif/mt6297/src/csif_profiling_main.c b/mcu/driver/devdrv/csif/mt6297/src/csif_profiling_main.c
new file mode 100644
index 0000000..c1931d7
--- /dev/null
+++ b/mcu/driver/devdrv/csif/mt6297/src/csif_profiling_main.c
@@ -0,0 +1,366 @@
+#include "csif_l1core_public_api.h"
+#include "drv_csif.h"
+#include "mips_ia_utils_public.h"
+
+#define OLPDET_START_ADDR CSIF_DSM_BASE
+#define OLPDET_SIZE 32
+#define MAILBOX_ID 0
+#define MAIL_CONTENT 0xFA970000
+
+#define RUN_ITERATION 4
+
+#define TESTING_MULTIPLE_MAIL_NUM 4
+#define MAX_TESTING_MULTIPLE_MAIL_NUM 8 // mapping to max aggregated mail num array below
+const kal_uint32 aggregate_mail_num_array[TESTING_MULTIPLE_MAIL_NUM] = {1, 2, 4, 8};
+
+typedef struct{
+ kal_uint32 start_time;
+ kal_uint32 end_time;
+ kal_uint32 latency;
+}CSIF_PROFILING_INFO;
+
+CSIF_PROFILING_INFO Profile_Multiple_Mail_Send_No_IRQ_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_Multiple_Mail_Send_One_IRQ_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_Multiple_Mail_Send_Multiple_IRQ_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_Multiple_Mail_Deallocate_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+
+kal_uint32 csif_c2s_IRQ_code[RUN_ITERATION] = {0}; // IRQ cannot be cleared by MCU side, need to use unique code for each case
+kal_uint32 Global_iteration_counter = 0;
+kal_uint32 IRQ_ID = 0;
+
+// ** for profile single API latency ** //
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+#if !defined(__CSIF_MULTIPLE_API__) // single API
+CSIF_PROFILING_INFO Profile_OLPDET_SET_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_OLPDET_CLR_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_MAILBOX_SEND_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_MAILBOX_RECV_array[RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_IRQ_SET_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+#else // multiple API
+CSIF_PROFILING_INFO Profile_OLPDET_MULTIPLE_SET_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_OLPDET_MULTIPLE_CLR_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_MAILBOX_MULTIPLE_SEND_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_MAILBOX_MULTIPLE_SEND_IRQ_SET_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+#endif // single/multiple API
+#endif // single api individual profile
+//////////////////////////////////////////
+
+
+void Multiple_Mail_Send_no_IRQ(){
+ kal_uint32 read_mail = 0;
+#if defined(__CSIF_MULTIPLE_API__)
+ kal_uint32 mail_length = 0;
+ kal_uint32 olpdet_length = 0;
+ CSIF_OLPDET_CONFIG_t olpdet_config_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+ CSIF_MAIL_INFO_t mail_info_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+#endif
+
+ for(kal_uint32 mail_num_idx = 0; mail_num_idx < TESTING_MULTIPLE_MAIL_NUM; mail_num_idx++){
+ /* start measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Send_No_IRQ_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+ //}
+#if !defined(__CSIF_MULTIPLE_API__)
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_SET_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_OLPDET_Set(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_SET_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_OLPDET_SET_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_OLPDET_SET_array[mail_num_idx][Global_iteration_counter].end_time - Profile_OLPDET_SET_array[mail_num_idx][Global_iteration_counter].start_time;
+ Profile_MAILBOX_SEND_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_MAILBOX_C2S_Send(MAILBOX_ID, (MAIL_CONTENT | mail_idx));
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_MAILBOX_SEND_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_MAILBOX_SEND_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_MAILBOX_SEND_array[mail_num_idx][Global_iteration_counter].end_time - Profile_MAILBOX_SEND_array[mail_num_idx][Global_iteration_counter].start_time;
+#endif
+ }
+#else // Multiple API
+ olpdet_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ olpdet_config_array[mail_idx].addr = CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx);
+ olpdet_config_array[mail_idx].size = OLPDET_SIZE;
+ }
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_MULTIPLE_SET_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_OLPDET_Multiple_Set(olpdet_length, &olpdet_config_array[0]);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_MULTIPLE_SET_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_OLPDET_MULTIPLE_SET_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_OLPDET_MULTIPLE_SET_array[mail_num_idx][Global_iteration_counter].end_time - Profile_OLPDET_MULTIPLE_SET_array[mail_num_idx][Global_iteration_counter].start_time;
+#endif
+ mail_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ mail_info_array[mail_idx].mID = MAILBOX_ID;
+ mail_info_array[mail_idx].mail = (MAIL_CONTENT | mail_idx);
+ }
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_MAILBOX_MULTIPLE_SEND_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_MAILBOX_C2S_Multiple_Send(mail_length, &mail_info_array[0]);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_MAILBOX_MULTIPLE_SEND_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_MAILBOX_MULTIPLE_SEND_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_MAILBOX_MULTIPLE_SEND_array[mail_num_idx][Global_iteration_counter].end_time - Profile_MAILBOX_MULTIPLE_SEND_array[mail_num_idx][Global_iteration_counter].start_time;
+#endif
+#endif // end of multiple API
+ /* end measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Send_No_IRQ_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_Multiple_Mail_Send_No_IRQ_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_Multiple_Mail_Send_No_IRQ_array[mail_num_idx][Global_iteration_counter].end_time - Profile_Multiple_Mail_Send_No_IRQ_array[mail_num_idx][Global_iteration_counter].start_time;
+ //}
+ /* Recover OLPDET and Mailbox */
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ CSIF_OLPDET_Clr(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+ }
+ do{
+ read_mail = CSIF_MAILBOX_C2S_Read(MAILBOX_ID);
+ }while(read_mail != CSIF_MAILBOX_EMPTY_VALUE);
+ /* Recover OLPDET and Mailbox */
+ }
+}
+
+void Multiple_Mail_Send_with_Single_IRQ(){
+ kal_uint32 read_mail = 0;
+#if defined(__CSIF_MULTIPLE_API__)
+ kal_uint32 mail_length = 0;
+ kal_uint32 olpdet_length = 0;
+ kal_uint32 irq_length = 0;
+ CSIF_OLPDET_CONFIG_t olpdet_config_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+ CSIF_MAIL_INFO_t mail_info_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+ CSIF_IRQ_INFO_t irq_info_array[1] = {0};
+#endif
+ for(kal_uint32 mail_num_idx = 0; mail_num_idx < TESTING_MULTIPLE_MAIL_NUM; mail_num_idx++){
+ /* start measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Send_One_IRQ_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+ //}
+#if !defined(__CSIF_MULTIPLE_API__)
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ CSIF_OLPDET_Set(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+ CSIF_MAILBOX_C2S_Send(MAILBOX_ID, (MAIL_CONTENT | mail_idx));
+
+ }
+
+ CSIF_C2S_SWI_Set(IRQ_ID, csif_c2s_IRQ_code[IRQ_ID]);
+
+#else // Multiple API
+ olpdet_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ olpdet_config_array[mail_idx].addr = CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx);
+ olpdet_config_array[mail_idx].size = OLPDET_SIZE;
+ }
+ CSIF_OLPDET_Multiple_Set(olpdet_length, &olpdet_config_array[0]);
+
+ mail_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ mail_info_array[mail_idx].mID = MAILBOX_ID;
+ mail_info_array[mail_idx].mail = (MAIL_CONTENT | mail_idx);
+ }
+ irq_length = 1;
+ irq_info_array[0].nID = IRQ_ID;
+ irq_info_array[0].code = csif_c2s_IRQ_code[IRQ_ID];
+ CSIF_MAILBOX_C2S_Multiple_Send_C2S_SWI_Multiple_Set(mail_length, &mail_info_array[0], irq_length, &irq_info_array[0]);
+#endif // end of multiple API
+ /* end measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Send_One_IRQ_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_Multiple_Mail_Send_One_IRQ_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_Multiple_Mail_Send_One_IRQ_array[mail_num_idx][Global_iteration_counter].end_time - Profile_Multiple_Mail_Send_One_IRQ_array[mail_num_idx][Global_iteration_counter].start_time;
+ //}
+ csif_c2s_IRQ_code[IRQ_ID]++;
+ /* Recover OLPDET and Mailbox */
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ CSIF_OLPDET_Clr(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+ }
+ do{
+ read_mail = CSIF_MAILBOX_C2S_Read(MAILBOX_ID);
+ }while(read_mail != CSIF_MAILBOX_EMPTY_VALUE);
+ /* Recover OLPDET and Mailbox */
+ }
+}
+
+void Multiple_Mail_Send_with_Multiple_IRQ(){
+ kal_uint32 read_mail = 0;
+#if defined(__CSIF_MULTIPLE_API__)
+ kal_uint32 mail_length = 0;
+ kal_uint32 olpdet_length = 0;
+ kal_uint32 irq_length = 0;
+ CSIF_OLPDET_CONFIG_t olpdet_config_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+ CSIF_MAIL_INFO_t mail_info_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+ CSIF_IRQ_INFO_t irq_info_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+#endif
+ for(kal_uint32 mail_num_idx = 0; mail_num_idx < TESTING_MULTIPLE_MAIL_NUM; mail_num_idx++){
+ /* start measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Send_Multiple_IRQ_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+ //}
+#if !defined(__CSIF_MULTIPLE_API__)
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ CSIF_OLPDET_Set(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+ CSIF_MAILBOX_C2S_Send(MAILBOX_ID, (MAIL_CONTENT | mail_idx));
+
+ }
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_IRQ_SET_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_C2S_SWI_Set(IRQ_ID, csif_c2s_IRQ_code[IRQ_ID]);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_IRQ_SET_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_IRQ_SET_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_IRQ_SET_array[mail_num_idx][Global_iteration_counter].end_time - Profile_IRQ_SET_array[mail_num_idx][Global_iteration_counter].start_time;
+#endif
+ csif_c2s_IRQ_code[IRQ_ID]++;
+ }
+#else // Multiple API
+ olpdet_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ olpdet_config_array[mail_idx].addr = CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx);
+ olpdet_config_array[mail_idx].size = OLPDET_SIZE;
+ }
+ CSIF_OLPDET_Multiple_Set(olpdet_length, &olpdet_config_array[0]);
+
+ mail_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ mail_info_array[mail_idx].mID = MAILBOX_ID;
+ mail_info_array[mail_idx].mail = (MAIL_CONTENT | mail_idx);
+ }
+ irq_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ irq_info_array[mail_idx].nID = IRQ_ID;
+ irq_info_array[mail_idx].code = csif_c2s_IRQ_code[IRQ_ID];
+ csif_c2s_IRQ_code[IRQ_ID]++;
+ }
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_MAILBOX_MULTIPLE_SEND_IRQ_SET_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_MAILBOX_C2S_Multiple_Send_C2S_SWI_Multiple_Set(mail_length, &mail_info_array[0], irq_length, &irq_info_array[0]);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_MAILBOX_MULTIPLE_SEND_IRQ_SET_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_MAILBOX_MULTIPLE_SEND_IRQ_SET_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_MAILBOX_MULTIPLE_SEND_IRQ_SET_array[mail_num_idx][Global_iteration_counter].end_time - Profile_MAILBOX_MULTIPLE_SEND_IRQ_SET_array[mail_num_idx][Global_iteration_counter].start_time;
+#endif
+#endif // end of multiple API
+ /* end measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Send_Multiple_IRQ_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_Multiple_Mail_Send_Multiple_IRQ_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_Multiple_Mail_Send_Multiple_IRQ_array[mail_num_idx][Global_iteration_counter].end_time - Profile_Multiple_Mail_Send_Multiple_IRQ_array[mail_num_idx][Global_iteration_counter].start_time;
+ // }
+ /* Recover OLPDET and Mailbox */
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ CSIF_OLPDET_Clr(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+ }
+ do{
+ read_mail = CSIF_MAILBOX_C2S_Read(MAILBOX_ID);
+ }while(read_mail != CSIF_MAILBOX_EMPTY_VALUE);
+ /* Recover OLPDET and Mailbox */
+ }
+}
+
+void Multiple_Mail_Deallocate(){
+#if defined(__CSIF_MULTIPLE_API__)
+ kal_uint32 olpdet_length = 0;
+ CSIF_OLPDET_CONFIG_t olpdet_config_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+#endif
+ for(kal_uint32 mail_num_idx = 0; mail_num_idx < TESTING_MULTIPLE_MAIL_NUM; mail_num_idx++){
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ CSIF_OLPDET_Set(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+ }
+ /* start measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Deallocate_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+ //}
+#if !defined(__CSIF_MULTIPLE_API__)
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_CLR_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_OLPDET_Clr(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_CLR_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_OLPDET_CLR_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_OLPDET_CLR_array[mail_num_idx][Global_iteration_counter].end_time - Profile_OLPDET_CLR_array[mail_num_idx][Global_iteration_counter].start_time;
+#endif
+ }
+#else // Multiple API
+ olpdet_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ olpdet_config_array[mail_idx].addr = CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx);
+ olpdet_config_array[mail_idx].size = OLPDET_SIZE;
+ }
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_MULTIPLE_CLR_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_OLPDET_Multiple_Clr(olpdet_length, &olpdet_config_array[0]);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_MULTIPLE_CLR_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_OLPDET_MULTIPLE_CLR_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_OLPDET_MULTIPLE_CLR_array[mail_num_idx][Global_iteration_counter].end_time - Profile_OLPDET_MULTIPLE_CLR_array[mail_num_idx][Global_iteration_counter].start_time;
+#endif
+#endif // end of multiple API
+ /* end measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Deallocate_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_Multiple_Mail_Deallocate_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_Multiple_Mail_Deallocate_array[mail_num_idx][Global_iteration_counter].end_time - Profile_Multiple_Mail_Deallocate_array[mail_num_idx][Global_iteration_counter].start_time;
+ //}
+ }
+}
+
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__) && !defined(__CSIF_MULTIPLE_API__)
+void Recv_single_mail_profile()
+{
+ csif_uint32 read_mail;
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_MAILBOX_RECV_array[Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ read_mail = CSIF_MAILBOX_C2S_Read(MAILBOX_ID);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_MAILBOX_RECV_array[Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_MAILBOX_RECV_array[Global_iteration_counter].latency =
+ Profile_MAILBOX_RECV_array[Global_iteration_counter].end_time - Profile_MAILBOX_RECV_array[Global_iteration_counter].start_time;
+#endif
+}
+#endif
+
+void CSIF_PROFILING_ENTRY(){
+
+ for(int i = 0; i<RUN_ITERATION; i++ ){
+ Multiple_Mail_Send_no_IRQ();
+ Global_iteration_counter++;
+ }
+ IRQ_ID = 0;
+ Global_iteration_counter = 0;
+ for(int i = 0; i<RUN_ITERATION; i++ ){
+ Multiple_Mail_Send_with_Single_IRQ();
+ IRQ_ID++;
+ Global_iteration_counter++;
+ }
+ IRQ_ID = 0;
+ Global_iteration_counter = 0;
+ for(int i = 0; i<RUN_ITERATION; i++ ){
+ Multiple_Mail_Send_with_Multiple_IRQ();
+ IRQ_ID++;
+ Global_iteration_counter++;
+ }
+ Global_iteration_counter = 0;
+ for(int i = 0; i<RUN_ITERATION; i++ ){
+ Multiple_Mail_Deallocate();
+ Global_iteration_counter++;
+ }
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__) && !defined(__CSIF_MULTIPLE_API__)
+ Global_iteration_counter = 0;
+ for(int i = 0; i<RUN_ITERATION; i++ ){
+ Recv_single_mail_profile();
+ Global_iteration_counter++;
+ }
+#endif
+}
diff --git a/mcu/driver/devdrv/csif/mt6297/src/drv_csif_init.c b/mcu/driver/devdrv/csif/mt6297/src/drv_csif_init.c
new file mode 100644
index 0000000..da3e403
--- /dev/null
+++ b/mcu/driver/devdrv/csif/mt6297/src/drv_csif_init.c
@@ -0,0 +1,349 @@
+#include "drv_csif.h"
+#include "kal_internal_api.h"
+#include "init_comm.h"
+#include "kal_hrt_api.h"
+
+/*******************************************************************************
+ * Global CSIF structure declare here
+ *******************************************************************************/
+csif_uint32 FPGA_version = 0;
+
+/*******************************************************************************
+ * Data Structure
+ *******************************************************************************/
+/* extern entry functions */
+#undef M_CSIF_S2C_INFO
+#undef M_CSIF_L1_ERR_INFO
+#define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) extern void CSIFHandler(CSIF_ID_STATUS_t *);
+#define M_CSIF_L1_ERR_INFO(CSIFErrHandler, Code, Value) extern void CSIFErrHandler(CSIF_ID_STATUS_t *);
+
+#include "csif_s2c_isr_config_n0_pre.h"
+#include "csif_s2c_isr_config_n1_pre.h"
+#include "csif_s2c_isr_config_n2_pre.h"
+#include "csif_s2c_isr_config_n3_pre.h"
+#include "csif_s2c_isr_config_n4_pre.h"
+#include "csif_s2c_isr_config_n5_pre.h"
+#include "csif_l1_err_isr_config_pre.h"
+
+#undef M_CSIF_S2C_INFO
+#undef M_CSIF_L1_ERR_INFO
+
+/* CSIF handler function pointer array */
+
+CSIF_InterruptEntryFun csif_s2c_isr_handler_n0[CSIF_S2C_N0_TOTAL_NUMBER] = {
+ #undef M_CSIF_S2C_INFO
+ #define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIFHandler,
+
+ #include "csif_s2c_isr_config_n0_pre.h"
+
+ #undef M_CSIF_S2C_INFO
+};
+
+CSIF_InterruptEntryFun csif_s2c_isr_handler_n1[CSIF_S2C_N1_TOTAL_NUMBER] = {
+ #undef M_CSIF_S2C_INFO
+ #define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIFHandler,
+
+ #include "csif_s2c_isr_config_n1_pre.h"
+
+ #undef M_CSIF_S2C_INFO
+};
+
+CSIF_InterruptEntryFun csif_s2c_isr_handler_n2[CSIF_S2C_N2_TOTAL_NUMBER] = {
+ #undef M_CSIF_S2C_INFO
+ #define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIFHandler,
+
+ #include "csif_s2c_isr_config_n2_pre.h"
+
+ #undef M_CSIF_S2C_INFO
+};
+
+CSIF_InterruptEntryFun csif_s2c_isr_handler_n3[CSIF_S2C_N3_TOTAL_NUMBER] = {
+ #undef M_CSIF_S2C_INFO
+ #define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIFHandler,
+
+ #include "csif_s2c_isr_config_n3_pre.h"
+
+ #undef M_CSIF_S2C_INFO
+};
+
+CSIF_InterruptEntryFun csif_s2c_isr_handler_n4[CSIF_S2C_N4_TOTAL_NUMBER] = {
+ #undef M_CSIF_S2C_INFO
+ #define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIFHandler,
+
+ #include "csif_s2c_isr_config_n4_pre.h"
+
+ #undef M_CSIF_S2C_INFO
+};
+
+CSIF_InterruptEntryFun csif_s2c_isr_handler_n5[CSIF_S2C_N5_TOTAL_NUMBER] = {
+ #undef M_CSIF_S2C_INFO
+ #define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIFHandler,
+
+ #include "csif_s2c_isr_config_n5_pre.h"
+
+ #undef M_CSIF_S2C_INFO
+};
+
+CSIF_InterruptEntryFun* csif_s2c_isr_handler[CSIF_ENUM_ALL_S2C_INT_NUM] = {
+ csif_s2c_isr_handler_n0,
+ csif_s2c_isr_handler_n1,
+ csif_s2c_isr_handler_n2,
+ csif_s2c_isr_handler_n3,
+ csif_s2c_isr_handler_n4,
+ csif_s2c_isr_handler_n5
+};
+
+
+/* CSIF Error handler function pointer array */
+CSIF_InterruptEntryFun csif_l1_err_isr_handler[CSIF_L1_ERR_TOTAL_NUMBER] = {
+ #undef M_CSIF_L1_ERR_INFO
+ #define M_CSIF_L1_ERR_INFO(CSIFErrHandler, Code, Value) CSIFErrHandler,
+
+ #include "csif_l1_err_isr_config_pre.h"
+
+ #undef M_CSIF_L1_ERR_INFO
+};
+
+/* CSIF irq ovfl allowed bool array */
+
+csif_bool csif_c2s_irq_ovfl_allow_n0[CSIF_C2S_N0_TOTAL_NUMBER] = {
+ #undef M_CSIF_C2S_INFO
+ #define M_CSIF_C2S_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) IRQ_ovfl_allow,
+
+ #include "csif_c2s_isr_config_n0_pre.h"
+
+ #undef M_CSIF_C2S_INFO
+};
+
+csif_bool csif_c2s_irq_ovfl_allow_n1[CSIF_C2S_N1_TOTAL_NUMBER] = {
+ #undef M_CSIF_C2S_INFO
+ #define M_CSIF_C2S_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) IRQ_ovfl_allow,
+
+ #include "csif_c2s_isr_config_n1_pre.h"
+
+ #undef M_CSIF_C2S_INFO
+};
+
+csif_bool csif_c2s_irq_ovfl_allow_n2[CSIF_C2S_N2_TOTAL_NUMBER] = {
+ #undef M_CSIF_C2S_INFO
+ #define M_CSIF_C2S_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) IRQ_ovfl_allow,
+
+ #include "csif_c2s_isr_config_n2_pre.h"
+
+ #undef M_CSIF_C2S_INFO
+};
+
+csif_bool csif_c2s_irq_ovfl_allow_n3[CSIF_C2S_N3_TOTAL_NUMBER] = {
+ #undef M_CSIF_C2S_INFO
+ #define M_CSIF_C2S_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) IRQ_ovfl_allow,
+
+ #include "csif_c2s_isr_config_n3_pre.h"
+
+ #undef M_CSIF_C2S_INFO
+};
+
+
+csif_bool* csif_c2s_irq_ovfl_allow[CSIF_ENUM_ALL_C2S_INT_NUM] = {
+ csif_c2s_irq_ovfl_allow_n0,
+ csif_c2s_irq_ovfl_allow_n1,
+ csif_c2s_irq_ovfl_allow_n2,
+ csif_c2s_irq_ovfl_allow_n3
+};
+
+/* CSIF HW entry num array */
+
+csif_uint32 csif_mailbox_entry_num_table[CSIF_MAILBOX_TOTAL_NUM] = {
+ #undef M_CSIF_MAILBOX_HW_INFO
+ #undef M_CSIF_MAILBOX_C2S_INFO
+ #undef M_CSIF_MAILBOX_S2C_INFO
+
+ #define M_CSIF_MAILBOX_HW_INFO(entrySize, HW_ID) entrySize,
+ #define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID)
+ #define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID)
+
+ #include "csif_mailbox_config_pre.h"
+
+ #undef M_CSIF_MAILBOX_HW_INFO
+ #undef M_CSIF_MAILBOX_C2S_INFO
+ #undef M_CSIF_MAILBOX_S2C_INFO
+};
+
+
+/*
+****************************************************************************************************************************
+* CSIF_Init.
+*
+* This function is for initiate the CSIF HW/SW
+*
+* Input: None
+*
+* Output: None
+*
+****************************************************************************************************************************
+*/
+
+void csif_init(void)
+{
+#if defined (__FPGA__)
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ if(INT_FPGA_PURPOSE() == FPGA_H5)
+ {
+#elif defined(MT6297)
+ if((INT_FPGA_PURPOSE() != FPGA_H1) && (INT_FPGA_PURPOSE() != FPGA_H3) && (INT_FPGA_PURPOSE() != FPGA_H4))
+ {
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+#endif
+ //[step0.] zero init
+
+ //[step1.] disable CSIF interrupt source & error type
+ //disable S2C CSIF interrupt source
+ for (int i=0; i<CSIF_ENUM_ALL_S2C_INT_NUM; i++){
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + i*CSIF_S2C_IRQ_SIZE, 0x0);
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+ }
+ //disable CSIF s2c_WFI_enable mask (write 10 bits on each enable mask, 4 th per core and 1 AND/OR bit per core)
+ /*
+ for (int i=0; i<CSIF_S2C_IDLE_IRQ_NUM; i++){
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + i*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+ }
+ */
+ //disable L1 error type (27 error, 2018/3/21)
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0);
+
+ //disable mailbox debug enable
+ for (int i=0; i<CSIF_MAILBOX_HW_TOTAL_NUMBER; i++){
+ CSIF_REG_WRITE(CSIF_MAILBOX_DEBUG_ENABLE + i*CSIF_MAILBOX_SIZE, 0x0);
+ }
+
+ //[step2.] clear error interrupt (MPU violation, MPU cfg error, undefined region, OVFL) & CSIF C2S interrupt status
+ //clear MPU violation status
+ for (int i=0; i<CSIF_MPU_CHANNEL_NUM_DSP; i++){
+ CSIF_REG_WRITE(CSIF_MPU_ERR_CLR + i*CSIF_MPU_ERR_SIZE, 0x1);
+ }
+ //clear DSP MPU cfg err status
+ for (int i=0; i<CSIF_MPU_CHANNEL_NUM_DSP; i++){
+ CSIF_REG_WRITE(CSIF_MPU_CFG_ERR_CLR_DSP + i*CSIF_MPU_CFG_ERR_CLR_SIZE, 0x1);
+ }
+ //clear L1 MPU cfg err status
+ for (int i=0; i<CSIF_MPU_CHANNEL_NUM_L1; i++){
+ CSIF_REG_WRITE(CSIF_MPU_CFG_ERR_CLR_L1 + i*CSIF_MPU_CFG_ERR_CLR_SIZE, 0x1);
+ }
+ //clear undefined region error status
+ CSIF_REG_WRITE(CSIF_DSM_WRITE_UNDEFINED_ERR_CLR_CR, 0x1);
+ CSIF_REG_WRITE(CSIF_DSM_READ_UNDEFINED_ERR_CLR_CR, 0x1);
+ CSIF_REG_WRITE(CSIF_DSR_WRITE_UNDEFINED_ERR_CLR_CR, 0x1);
+ CSIF_REG_WRITE(CSIF_DSR_READ_UNDEFINED_ERR_CLR_CR, 0x1);
+
+ //clear C2S overflow status
+ //(!!make rule: TBD! Which side to clear irq ovfl!)
+ /*
+ for (int i=0; i<CSIF_ENUM_ALL_C2S_INT_NUM; i++){
+ CSIF_REG_WRITE(CSIF_C2S_IRQ_OVFL_CLR + i*CSIF_C2S_IRQ_OVFL_SIZE, 0xFFFFFFFF);
+ }
+
+ //clear S2C overflow status
+ for (int i=0; i<CSIF_ENUM_ALL_S2C_INT_NUM; i++){
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_OVFL_CLR + i*CSIF_S2C_IRQ_OVFL_SIZE, 0xFFFFFFFF);
+ }
+ */
+ //clear s2c irq status
+ // s2c0/1 bit0/1 no effect (HW IRQ)
+ // unclear s2c irq because it must not pending s2c irq when 1st boot up
+ // unclear s2c irq because maybe there is user trigger s2c irq before activate done
+ /*
+ for (int i=0; i<CSIF_ENUM_ALL_S2C_INT_NUM; i++){
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_CLR + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+ }
+ */
+ //clear mailbox error
+ for (int i=0; i<CSIF_MAILBOX_HW_TOTAL_NUMBER; i++){
+ CSIF_REG_WRITE(CSIF_MAILBOX_CLR_ERROR + i*CSIF_MAILBOX_SIZE, 0x1);
+ }
+
+ //clear OLPDET error
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+
+ //[step3.] enable CSIF setting
+#if !defined(__CSIF_DRV_TEST__)
+ //enable L1 error type (27 error, 2018/3/21)
+ // s2c/c2s irq ovfl error to use SW to control
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, CSIF_L1_ERROR_MASK);
+ //enable S2C CSIF interrupt source
+ for (int i=0; i<CSIF_ENUM_ALL_S2C_INT_NUM; i++){
+ if(i == 0 || i == 1){
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_SET + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+ }else{
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_SET + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+ }
+ }
+#endif
+ //open mask of CSIF s2c_WFI_enable mask (write 10 bits on each enable mask, 4 th per core and 1 AND/OR bit per core)
+ //WFI_irq0
+ //CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_SET + 0*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+ //WFI_irq1
+ //CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_SET + 1*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+
+ // set SS region on DSM into OLPDET
+ //CSIF_OLPDET_Set(0, 2048);
+
+ //[step4.] Register CIRQ
+ //IRQ_Register_LISR(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE, CSIF_S2C_N0_Handler, "csif_s2c_n0");
+ //IRQSensitivity(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE, LEVEL_SENSITIVE);
+ IRQUnmask(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE);
+
+ //IRQ_Register_LISR(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE, CSIF_S2C_N1_Handler, "csif_s2c_n1");
+ //IRQSensitivity(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE, LEVEL_SENSITIVE);
+ IRQUnmask(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE);
+
+ //IRQ_Register_LISR(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE, CSIF_S2C_N2_Handler, "csif_s2c_n2");
+ //IRQSensitivity(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE, LEVEL_SENSITIVE);
+ IRQUnmask(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE);
+
+ //IRQ_Register_LISR(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE, CSIF_S2C_N3_Handler, "csif_s2c_n3");
+ //IRQSensitivity(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE, LEVEL_SENSITIVE);
+ IRQUnmask(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE);
+
+ //IRQ_Register_LISR(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE, CSIF_S2C_N4_Handler, "csif_s2c_n4");
+ //IRQSensitivity(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE, LEVEL_SENSITIVE);
+ IRQUnmask(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE);
+
+ //IRQ_Register_LISR(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE, CSIF_S2C_N5_Handler, "csif_s2c_n5");
+ //IRQSensitivity(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE, LEVEL_SENSITIVE);
+ IRQUnmask(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE);
+
+ //IRQ_Register_LISR(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE, CSIF_L1_ERR_Handler, "csif_error_irq");
+ //IRQSensitivity(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE, LEVEL_SENSITIVE);
+ IRQUnmask(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE);
+
+ //[step5.] pass ext_csif base addr to DSP
+ extern void EXT_CSIF_Init(void);
+ EXT_CSIF_Init();
+
+#if defined (__FPGA__)
+ }
+ else
+ {
+ return;
+ }
+#endif
+}
+
diff --git a/mcu/driver/devdrv/csif/mt6297/src/drv_csif_main.c b/mcu/driver/devdrv/csif/mt6297/src/drv_csif_main.c
new file mode 100644
index 0000000..569428b
--- /dev/null
+++ b/mcu/driver/devdrv/csif/mt6297/src/drv_csif_main.c
@@ -0,0 +1,1130 @@
+#include "drv_csif.h"
+#include "kal_hrt_api.h"
+#include "kal_public_defs.h"
+#include "kal_public_api.h"
+#if defined(__CSIF_DEBUG__)
+#include "us_timer.h"
+#endif
+
+#if defined(MT6297)
+#include "d2d_public.h" // For Apollo OLPDET workaround
+#include "kal_itc.h"
+#endif
+
+#if defined(__CSIF_DEBUG__)
+// #include frc_api.h
+#endif /* __CSIF_DEBUG__ */
+
+#if defined(__CSIF_DRV_TEST__)
+volatile csif_uint32 ASSERT_MSG[3];
+#endif
+
+
+/*******************************************************************************
+ * Macros
+ *******************************************************************************/
+/* e.g. GET_S2C_IRQ_LIMIT_NUMBER(0) => CSIF_S2C_N0_TOTAL_NUMBER */
+#define POSTFIX(nID, pos) nID##pos
+#define PREFIX(nID, pre) POSTFIX(pre##nID, _TOTAL_NUMBER)
+#define GET_S2C_IRQ_LIMIT_NUMBER(nID) PREFIX(nID, CSIF_S2C_N)
+
+#define GET_C2S_IRQ_LIMIT_NUMBER(nID) PREFIX(nID, CSIF_C2S_N)
+
+/*******************************************************************************
+ * Variable Declaration
+ *******************************************************************************/
+extern CSIF_InterruptEntryFun* csif_s2c_isr_handler[CSIF_ENUM_ALL_S2C_INT_NUM];
+extern csif_bool* csif_c2s_irq_ovfl_allow[CSIF_ENUM_ALL_C2S_INT_NUM];
+extern CSIF_InterruptEntryFun csif_l1_err_isr_handler[CSIF_L1_ERR_TOTAL_NUMBER];
+extern csif_uint32 csif_mailbox_entry_num_table[CSIF_MAILBOX_TOTAL_NUM];
+
+#if defined(MT6297)
+kal_uint32 olpdet_lock = 0; // For Apollo OLPDET workaround
+#endif
+
+static const kal_uint32 CSIF_S2C_Interrupt_Num[CSIF_ENUM_ALL_S2C_INT_NUM] = {
+ GET_S2C_IRQ_LIMIT_NUMBER(0),
+ GET_S2C_IRQ_LIMIT_NUMBER(1),
+ GET_S2C_IRQ_LIMIT_NUMBER(2),
+ GET_S2C_IRQ_LIMIT_NUMBER(3),
+ GET_S2C_IRQ_LIMIT_NUMBER(4),
+ GET_S2C_IRQ_LIMIT_NUMBER(5)
+};
+static const kal_uint32 CSIF_C2S_Interrupt_Num[CSIF_ENUM_ALL_C2S_INT_NUM] = {
+ GET_C2S_IRQ_LIMIT_NUMBER(0),
+ GET_C2S_IRQ_LIMIT_NUMBER(1),
+ GET_C2S_IRQ_LIMIT_NUMBER(2),
+ GET_C2S_IRQ_LIMIT_NUMBER(3)
+};
+/*******************************************************************************
+ * Debug
+ *******************************************************************************/
+#if defined(__CSIF_DEBUG__)
+
+CSIF_DebugISRCodeList csif_debug_s2c_isr_handler_n0;
+CSIF_DebugISRCodeList csif_debug_s2c_isr_handler_n1;
+CSIF_DebugISRCodeList csif_debug_s2c_isr_handler_n2;
+CSIF_DebugISRCodeList csif_debug_s2c_isr_handler_n3;
+CSIF_DebugISRCodeList csif_debug_s2c_isr_handler_n4;
+CSIF_DebugISRCodeList csif_debug_s2c_isr_handler_n5;
+
+CSIF_DebugRecordList csif_debug_records;
+CSIF_MultiOperationDebugRecordList csif_multioperation_debug_records;
+
+kal_atomic_uint32 MultiOperation_debug_idx = 0;
+#endif /* __CSIF_DEBUG__ */
+
+
+/*******************************************************************************
+ * Function prototypes
+ *******************************************************************************/
+void csif_InterruptHandlerInternal(volatile csif_uint32* clr_reg,
+ volatile csif_uint32* status_reg,
+ volatile csif_uint32* m_status_reg,
+ volatile csif_uint32* enable_reg,
+ volatile csif_uint32 isr_n_num,
+ CSIF_InterruptEntryFun* handler);
+
+
+/*******************************************************************************
+ * Functions - Debug information
+ *******************************************************************************/
+#if defined(__CSIF_DEBUG__)
+void csif_DebugAddISRHandlerCode(CSIF_S2C_INDEX nID, csif_uint32 code){
+ CSIF_DebugISRCodeList* code_list = CSIF_NULL;
+
+ switch(nID){
+ case CSIF_ENUM_S2C_N0:
+ code_list = &csif_debug_s2c_isr_handler_n0;
+ break;
+ case CSIF_ENUM_S2C_N1:
+ code_list = &csif_debug_s2c_isr_handler_n1;
+ break;
+ case CSIF_ENUM_S2C_N2:
+ code_list = &csif_debug_s2c_isr_handler_n2;
+ break;
+ case CSIF_ENUM_S2C_N3:
+ code_list = &csif_debug_s2c_isr_handler_n3;
+ break;
+ case CSIF_ENUM_S2C_N4:
+ code_list = &csif_debug_s2c_isr_handler_n4;
+ break;
+ case CSIF_ENUM_S2C_N5:
+ code_list = &csif_debug_s2c_isr_handler_n5;
+ break;
+ default:
+ CSIF_ASSERT(0, nID, code, CSIF_ENUM_ALL_S2C_INT_NUM);
+ }
+
+ csif_uint32 record_index = 0;
+
+ if(code_list != CSIF_NULL){
+ record_index = code_list -> top_index;
+ //record_index = kal_atomic_inc_circular_index(&(code_list -> top_index), CSIF_DEBUG_ISR_HANDLE_CODE_SIZE);
+ code_list -> records[record_index].time = ust_get_current_time();
+ code_list -> records[record_index].code = code;
+ (code_list -> top_index)++;
+
+ if (code_list -> top_index == CSIF_DEBUG_ISR_HANDLE_CODE_SIZE){
+ code_list -> top_index = 0;
+ }
+ }
+ return;
+}
+
+void csif_DebugAddRecord(csif_uint32 status,
+ volatile csif_uint32* set_addr,
+ csif_uint32 set_value,
+ csif_uint32 caller){
+ csif_uint32 record_index = 0;
+ CSIF_DebugRecordList* record_list = CSIF_NULL;
+
+ record_list = &csif_debug_records;
+
+ //csif_uint32 mask;
+ //mask = kal_hrt_SaveAndSetIRQMask();
+
+ //record_index = record_list -> top_index;
+ record_index = kal_atomic_inc_circular_index(&(record_list -> top_index), CSIF_DEBUG_API_RECORD_SIZE);
+ //(record_list -> top_index)++;
+ //if (record_list -> top_index == CSIF_DEBUG_API_RECORD_SIZE){
+ // record_list -> top_index = 0;
+ //}
+ //kal_hrt_RestoreIRQMask(mask);
+
+ record_list -> records[record_index].time = ust_get_current_time();
+ record_list -> records[record_index].status = status;
+ record_list -> records[record_index].set_addr = (csif_uint32)set_addr;
+ record_list -> records[record_index].set_value = set_value;
+ record_list -> records[record_index].caller = caller;
+ return;
+}
+
+void csif_MultiDebugAddRecord(csif_uint32 multiIdx,
+ volatile csif_uint32* set_addr,
+ csif_uint32 set_value,
+ csif_uint32 caller){
+ csif_uint32 record_index = 0;
+ CSIF_MultiOperationDebugRecordList* record_list = CSIF_NULL;
+
+ record_list = &csif_multioperation_debug_records;
+
+ //csif_uint32 mask;
+ //mask = kal_hrt_SaveAndSetIRQMask();
+
+ //record_index = record_list -> top_index;
+ record_index = kal_atomic_inc_circular_index(&(record_list -> top_index), CSIF_DEBUG_MULTI_API_RECORD_SIZE);
+ //(record_list -> top_index)++;
+ //if (record_list -> top_index == CSIF_DEBUG_API_RECORD_SIZE){
+ // record_list -> top_index = 0;
+ //}
+ //kal_hrt_RestoreIRQMask(mask);
+
+ record_list -> records[record_index].time = ust_get_current_time();
+ record_list -> records[record_index].set_addr = (csif_uint32)set_addr;
+ record_list -> records[record_index].set_value = set_value;
+ record_list -> records[record_index].caller = caller;
+ record_list -> records[record_index].multiIdx = multiIdx;
+ return;
+}
+
+#endif /* __CSIF_DEBUG__ */
+
+
+/*******************************************************************************
+ * Functions - Common Part
+ *******************************************************************************/
+void CSIF_Invalid(CSIF_ID_STATUS_t* status_id){
+#if !defined(__CSIF_DRV_TEST__)
+ // code 1: csif_id(irq_id 0-5), code 2: csif_bit, code 3: masked_status
+ CSIF_ASSERT(0, status_id->id, status_id->code, status_id->masked_status);
+#else
+#endif
+}
+
+void __attribute__ ((used)) csif_InterruptHandlerInternal(volatile csif_uint32* clr_reg,
+ volatile csif_uint32* status_reg,
+ volatile csif_uint32* m_status_reg,
+ volatile csif_uint32* enable_reg,
+ volatile csif_uint32 isr_n_num,
+ CSIF_InterruptEntryFun* handler)
+{
+ CSIF_ID_STATUS_t status_id;
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+
+
+ csif_uint32 index = 0;
+ // status_id:
+ // id: c2s irq num (0~3)
+ // code: local_c2s bit code (0~31)
+ // masked_status: c2s_masked status (corresponding irq 0 or irq 1)
+ // *reg_addr: c2s status reg addr
+ status_id.reg_addr = (csif_uint32*)status_reg;
+ CSIF_REG_READ(m_status_reg, status_id.masked_status);
+
+ csif_uint32 csif_interrupt_num = CSIF_S2C_Interrupt_Num[isr_n_num];
+ while(index < csif_interrupt_num)
+ {
+ if((status_id.masked_status & (0x1<<index))!= 0)
+ {
+ status_id.id = isr_n_num;
+ status_id.code = index;
+ // clear irq bit before entering user callback
+ CSIF_REG_WRITE(clr_reg, 1<<index);
+ status_id.masked_status = status_id.masked_status & (~(0x1<<index));
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(status_id.masked_status, clr_reg, 0x1<<index, caller);
+#endif /* __CSIF_DEBUG__ */
+
+ (handler[index])((CSIF_ID_STATUS_t *)(&status_id));
+
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddISRHandlerCode(isr_n_num, index);
+#endif /* __CSIF_DEBUG__ */
+
+ }
+ index++;
+ }
+}
+
+
+void CSIF_S2C_N0_Handler(kal_uint32 irq_id){
+ CSIF_HANDLER(CSIF_ENUM_S2C_N0);
+}
+
+void CSIF_S2C_N1_Handler(kal_uint32 irq_id){
+ CSIF_HANDLER(CSIF_ENUM_S2C_N1);
+}
+
+void CSIF_S2C_N2_Handler(kal_uint32 irq_id){
+ CSIF_HANDLER(CSIF_ENUM_S2C_N2);
+}
+
+void CSIF_S2C_N3_Handler(kal_uint32 irq_id){
+ CSIF_HANDLER(CSIF_ENUM_S2C_N3);
+}
+
+void CSIF_S2C_N4_Handler(kal_uint32 irq_id){
+ CSIF_HANDLER(CSIF_ENUM_S2C_N4);
+}
+
+void CSIF_S2C_N5_Handler(kal_uint32 irq_id){
+ CSIF_HANDLER(CSIF_ENUM_S2C_N5);
+}
+
+// CSIF error user return caller function
+#if !defined(__MAUI_BASIC__)
+extern kal_uint32 NL1_FWK_CSIF_Mailbox_Public_Dispatch_Olpdet_Error(CSIF_OLPDET_ERROR_TYPE_ENUM_T error_type, kal_uint32 addr, kal_uint32 size);
+extern kal_uint32 NL1_FWK_CSIF_Mailbox_Public_Dispatch_Mailbox_Error(kal_uint32 mailbox_idx, kal_uint32 error_content);
+#endif
+
+void CSIF_L1_ERR_Handler(kal_uint32 irq_id){
+ CSIF_ID_STATUS_t err_status_id;
+ csif_uint32 index = 0;
+#if !defined(__MAUI_BASIC__)
+ csif_uint32 error_dispatch_addr = 0;
+ csif_uint32 error_mailbox_id = 0;
+ csif_uint32 error_mailbox_status = 0;
+ csif_uint32 error_mailbox_record = 0;
+ csif_uint32 error_olpdet_status = 0;
+ csif_uint32 error_olpdet_candidate_record = 0;
+ CSIF_OLPDET_ERROR_TYPE_ENUM_T error_olpdet_type = CSIF_OLPDET_ERROR_TOTAL_NUM;
+ csif_uint32 error_olpdet_addr = 0;
+ csif_uint32 error_olpdet_size = 0;
+#endif
+
+
+ //***** err_status_id: ***********
+ // id: error snapshot
+ // code: error bit
+ // masked_status: error_enable
+ // *reg_addr: addr of error status base addr (MCU doesn't have error source)
+ //*********************************
+ err_status_id.reg_addr = (csif_uint32*)CSIF_L1_ERROR_FLAG_CR;
+ CSIF_REG_READ(CSIF_L1_ERROR_SNAPSHOT_CR, err_status_id.id);
+ CSIF_REG_READ(CSIF_L1_ERROR_ENABLE_CR, err_status_id.masked_status);
+
+ while (index < CSIF_L1_ERR_TOTAL_NUMBER) {
+ if ((err_status_id.masked_status & (1 << index)) && (err_status_id.id & (1 << index))) {
+ err_status_id.code = index;
+#if !defined(__MAUI_BASIC__)
+ if ((err_status_id.code == CSIF_MAILBOX0_ERR_P) || (err_status_id.code == CSIF_MAILBOX1_ERR_P) ||
+ (err_status_id.code == CSIF_MAILBOX2_ERR_P) || (err_status_id.code == CSIF_MAILBOX3_ERR_P) ||
+ (err_status_id.code == CSIF_MAILBOX4_ERR_P) || (err_status_id.code == CSIF_MAILBOX5_ERR_P) ) {
+ // Handle mailbox error
+ error_mailbox_id = err_status_id.code - CSIF_MAILBOX0_ERR_P;
+ CSIF_REG_READ(CSIF_MAILBOX_ERROR_STATUS + error_mailbox_id*CSIF_MAILBOX_SIZE, error_mailbox_status);
+ CSIF_REG_READ(CSIF_MAILBOX_ERROR_RECORD + error_mailbox_id*CSIF_MAILBOX_SIZE, error_mailbox_record);
+/*
+ * <TODO> To be removed
+ * This is temporary workaround to solve flavors for which does not build NL1 module
+ */
+#if defined(__NR_RAT__)
+ error_dispatch_addr = NL1_FWK_CSIF_Mailbox_Public_Dispatch_Mailbox_Error(error_mailbox_id, error_mailbox_record); // para 1 should be replace to SLM/NL1FWK Mailbox error function
+#endif
+ CUSTOM_ASSERT_ADDR_EXT3(0, error_dispatch_addr, error_mailbox_id, error_mailbox_record, error_mailbox_status);
+ } else if (err_status_id.code == CSIF_OLPDET_ERR_P) {
+ // Handle OLPDET error
+ CSIF_REG_READ(CSIF_OLPDET_ERROR_STATUS, error_olpdet_status);
+ if ((error_olpdet_status & CSIF_OLPDET_OLP_HIT_ERROR_M) != 0) {
+ CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, error_olpdet_candidate_record);
+ error_olpdet_type = CSIF_OLP_HIT_ERROR;
+ }
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+ else if ((error_olpdet_status & CSIF_OLPDET_CLR_NOHIT_ERROR_M) != 0) {
+ CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, error_olpdet_candidate_record);
+ error_olpdet_type = CSIF_CLR_NOHIT_ERROR;
+ }
+#elif defined(MT6297)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+ error_olpdet_addr = ((error_olpdet_candidate_record & CSIF_OLPDET_SET_OFFSET_M) >> CSIF_OLPDET_SET_OFFSET_P) * CSIF_OLPDET_UNIT;
+ error_olpdet_size = ((error_olpdet_candidate_record & CSIF_OLPDET_SET_LENGTH_M) >> CSIF_OLPDET_SET_LENGTH_P) * CSIF_OLPDET_UNIT;
+/*
+ * <TODO> To be removed
+ * This is temporary workaround to solve flavors for which does not build NL1 module
+ */
+#if defined(__NR_RAT__)
+ error_dispatch_addr = NL1_FWK_CSIF_Mailbox_Public_Dispatch_Olpdet_Error(error_olpdet_type, error_olpdet_addr, error_olpdet_size); // para 1 should be replace to SLM/NL1FWK Mailbox error function
+#endif
+ CUSTOM_ASSERT_ADDR_EXT3(0, error_dispatch_addr, error_olpdet_addr, error_olpdet_size, error_olpdet_status);
+ }
+#endif
+ (csif_l1_err_isr_handler[index])((CSIF_ID_STATUS_t *)(&err_status_id));
+ }
+ index++;
+ }
+
+ // code 1: error snapshot, code 2: error_bit, code 3: error_enable
+ CSIF_ASSERT(0, err_status_id.id, err_status_id.code, err_status_id.masked_status);
+}
+
+
+/*******************************************************************************
+ * Functions - MCU CSIF PART API
+ *******************************************************************************/
+
+void CSIF_C2S_SWI_Set(CSIF_C2S_INDEX nID, csif_uint32 code){
+ csif_uint32 before_status = 0xFFFFFFFF;
+ csif_uint32 idx = (csif_uint32) nID;
+ // get caller here
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ // assertion of user setting code out of code limit
+ csif_uint32 code_limit = CSIF_C2S_Interrupt_Num[idx];
+ CSIF_ASSERT(code < code_limit, nID, code, code_limit);
+
+ if(csif_c2s_irq_ovfl_allow[idx][code] == CSIF_TRUE){
+ CSIF_REG_WRITE(CSIF_C2S_IRQ_SET + idx*CSIF_C2S_IRQ_SIZE, 1 << code);
+ }else{
+ // Use HWITC to create critical section
+ kal_hrt_take_itc_lock(KAL_ITC_CSIF_LOCK, KAL_INFINITE_WAIT);
+ /* end of HWITC take */
+ CSIF_REG_READ(CSIF_C2S_IRQ_STATUS + idx*CSIF_C2S_IRQ_SIZE, before_status);
+ if((before_status & (1 << code)) == 0){
+ CSIF_REG_WRITE(CSIF_C2S_IRQ_SET + idx*CSIF_C2S_IRQ_SIZE, 1 << code);
+ /* Release HWITC */
+ kal_hrt_give_itc_lock(KAL_ITC_CSIF_LOCK);
+ }
+ else{
+ /* Release HWITC */
+ kal_hrt_give_itc_lock(KAL_ITC_CSIF_LOCK);
+#if defined(__CSIF_DEBUG__)
+ CSIF_ASSERT((before_status & (1 << code)) == 0, nID, code, caller);
+#else
+ CSIF_ASSERT((before_status & (1 << code)) == 0, nID, code, 0);
+#endif
+ //CSIF_REG_WRITE(CSIF_C2S_IRQ_SET + idx*CSIF_C2S_IRQ_SIZE, 1 << code);
+ }
+ }
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(before_status, (csif_uint32*)(CSIF_C2S_IRQ_SET + idx*CSIF_C2S_IRQ_SIZE), 1 << code, caller);
+#endif /* __CSIF_DEBUG__ */
+}
+
+csif_uint32 CSIF_C2S_SWI_Read(CSIF_C2S_INDEX nID){
+ csif_uint32 c2s_swi_read = 0;
+ CSIF_REG_READ(CSIF_C2S_IRQ_STATUS + nID*CSIF_C2S_IRQ_SIZE, c2s_swi_read);
+ return c2s_swi_read;
+}
+
+csif_uint32 CSIF_C2S_SWI_MASKED_Read(CSIF_C2S_INDEX nID){
+ csif_uint32 c2s_swi_masked_read = 0;
+ CSIF_REG_READ(CSIF_C2S_IRQ_MASKED_STATUS + nID*CSIF_C2S_IRQ_SIZE, c2s_swi_masked_read);
+ return c2s_swi_masked_read;
+}
+
+
+
+csif_uint32 CSIF_S2C_SWI_Read(CSIF_S2C_INDEX nID){
+ csif_uint32 s2c_swi_read = 0;
+ CSIF_REG_READ(CSIF_S2C_IRQ_STATUS + nID*CSIF_S2C_IRQ_SIZE, s2c_swi_read);
+ return s2c_swi_read;
+}
+
+csif_uint32 CSIF_S2C_SWI_MASKED_Read(CSIF_S2C_INDEX nID){
+ csif_uint32 s2c_swi_masked_read = 0;
+ CSIF_REG_READ(CSIF_S2C_IRQ_MASKED_STATUS + nID*CSIF_S2C_IRQ_SIZE, s2c_swi_masked_read);
+ return s2c_swi_masked_read;
+}
+
+csif_uint32 CSIF_S2C_SWI_Enable_Read(CSIF_S2C_INDEX nID){
+ csif_uint32 enable_read = 0;
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + nID*CSIF_S2C_IRQ_SIZE, enable_read);
+ return enable_read;
+}
+
+void CSIF_S2C_SWI_Enable(CSIF_S2C_INDEX nID, csif_uint32 code){
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ // assertion of user setting code out of code limit
+ csif_uint32 code_limit = CSIF_S2C_Interrupt_Num[nID];
+ CSIF_ASSERT(code < code_limit, nID, code, code_limit);
+
+ // use atomic to protect setting S2C enable CR part
+ /*TODO use Shaolin atomic */
+ //cc_spinlock_hw_take_lock(CC_SPINLOCK_CSIF_DRIVER);
+
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_SET + nID*CSIF_S2C_IRQ_SIZE, (1<<code));
+
+ // release atomic
+ /*TODO use Shaolin atomic */
+ //cc_spinlock_hw_give_lock(CC_SPINLOCK_CSIF_DRIVER);
+
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(nID, (csif_uint32*)(CSIF_S2C_IRQ_ENABLE_SET + nID*CSIF_S2C_IRQ_SIZE), (1<<code), caller);
+#endif /* __CSIF_DEBUG__ */
+#elif defined(MT6297)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif // project option
+}
+
+void CSIF_S2C_SWI_Disable(CSIF_S2C_INDEX nID, csif_uint32 code){
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ // assertion of user setting code out of code limit
+ csif_uint32 code_limit = CSIF_S2C_Interrupt_Num[nID];
+ CSIF_ASSERT(code < code_limit, nID, code, code_limit);
+
+ // use atomic to protect setting S2C enable CR part
+ /*TODO use Shaolin atomic */
+ //cc_spinlock_hw_take_lock(CC_SPINLOCK_CSIF_DRIVER);
+
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + nID*CSIF_S2C_IRQ_SIZE, (1 << code));
+
+
+ // release atomic
+ /*TODO use Shaolin atomic */
+ //cc_spinlock_hw_give_lock(CC_SPINLOCK_CSIF_DRIVER);
+
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(nID, (csif_uint32*)(CSIF_S2C_IRQ_ENABLE_CLR + nID*CSIF_S2C_IRQ_SIZE), (1 << code), caller);
+#endif /* __CSIF_DEBUG__ */
+#elif defined(MT6297)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif // project option
+}
+
+// this enable bitmask api shouldn't let user use, SS use only
+void CSIF_S2C_SWI_Enable_bitmask(CSIF_S2C_INDEX nID, csif_uint32 bitmap){
+#if defined(MT6297)
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ /*Todo*/ /*maybe no need, because we won't use enable bitmask without backup/restore flow*/
+ /*need to atomic of backup/restore flow api*/
+ // use atomic to protect setting S2C enable CR part
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + nID*CSIF_S2C_IRQ_SIZE, bitmap);
+
+ // release atomic
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(nID, (csif_uint32*)(CSIF_S2C_IRQ_ENABLE + nID*CSIF_S2C_IRQ_SIZE), bitmap, caller);
+#endif /* __CSIF_DEBUG__ */
+#elif defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif // project option
+}
+
+csif_uint32 CSIF_S2C_Overflow_Read(CSIF_S2C_INDEX nID){
+ csif_uint32 s2c_ovfl_status = 0;
+ CSIF_REG_READ(CSIF_S2C_IRQ_OVFL_STATUS + nID*CSIF_S2C_IRQ_OVFL_SIZE, s2c_ovfl_status);
+ return s2c_ovfl_status;
+}
+
+void CSIF_S2C_Overflow_Clear(CSIF_S2C_INDEX nID, csif_uint32 code){
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ // assertion of user setting code out of code limit
+ csif_uint32 code_limit = CSIF_S2C_Interrupt_Num[nID];
+ CSIF_ASSERT(code < code_limit, nID, code, code_limit);
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_OVFL_CLR + nID*CSIF_S2C_IRQ_OVFL_SIZE, 1 << code);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(nID, (csif_uint32*)(CSIF_S2C_IRQ_OVFL_CLR + nID*CSIF_S2C_IRQ_OVFL_SIZE), 1 << code, caller);
+#endif /* __CSIF_DEBUG__ */
+}
+
+csif_uint32 CSIF_C2S_Overflow_Read(CSIF_C2S_INDEX nID){
+ csif_uint32 c2s_ovfl_status = 0;
+ CSIF_REG_READ(CSIF_C2S_IRQ_OVFL_STATUS + nID*CSIF_C2S_IRQ_OVFL_SIZE, c2s_ovfl_status);
+ return c2s_ovfl_status;
+}
+
+void CSIF_C2S_Overflow_Clear(CSIF_C2S_INDEX nID, csif_uint32 code){
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ // assertion of user setting code out of code limit
+ csif_uint32 code_limit = CSIF_C2S_Interrupt_Num[nID];
+ CSIF_ASSERT(code < code_limit, nID, code, code_limit);
+ CSIF_REG_WRITE(CSIF_C2S_IRQ_OVFL_CLR + nID*CSIF_C2S_IRQ_OVFL_SIZE, 1 << code);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(nID, (csif_uint32*)(CSIF_C2S_IRQ_OVFL_CLR + nID*CSIF_C2S_IRQ_OVFL_SIZE), 1 << code, caller);
+#endif /* __CSIF_DEBUG__ */
+}
+
+void CSIF_MPU_Set(CSIF_MPU_ENUM_T mpuID, csif_uint32 start, csif_uint32 range, CSIF_MPU_TYPE_ENUM_T type){
+#if 0
+/* under construction !*/
+#if defined(__CSIF_DEBUG__)
+/* under construction !*/
+/* under construction !*/
+#endif /* __CSIF_DEBUG__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__CSIF_DEBUG__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* __CSIF_DEBUG__ */
+#endif
+}
+
+csif_uint32 CSIF_CORE_IDLE_Read(void){
+ csif_uint32 core_idle = 0;
+ CSIF_REG_READ(CSIF_CORE_IDLE, core_idle);
+ return core_idle;
+}
+
+csif_uint32 CSIF_IDLE_ENABLE_Read(CSIF_S2C_INDEX nID){
+ csif_uint32 idle_enable = 0;
+ CSIF_REG_READ(CSIF_S2C_IDLE_IRQ_ENABLE + nID*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, idle_enable);
+ return idle_enable;
+}
+
+void CSIF_IDLE_ENABLE_Set(CSIF_S2C_INDEX nID, csif_uint32 enable_map){
+ CSIF_ASSERT(nID < CSIF_S2C_IDLE_IRQ_NUM, nID, enable_map, 0);
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_SET + nID*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, enable_map);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(nID, (csif_uint32*)(CSIF_S2C_IDLE_IRQ_ENABLE_SET + nID*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE), enable_map, caller);
+#endif /* __CSIF_DEBUG__ */
+}
+
+void CSIF_IDLE_ENABLE_Clr(CSIF_S2C_INDEX nID, csif_uint32 clr_bit_map){
+ CSIF_ASSERT(nID < CSIF_S2C_IDLE_IRQ_NUM, nID, clr_bit_map, 0);
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + nID*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, clr_bit_map);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(nID, (csif_uint32*)(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + nID*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE), clr_bit_map, caller);
+#endif /* __CSIF_DEBUG__ */
+}
+
+//************ mailbox related feature *************//
+void CSIF_MAILBOX_C2S_Send(CSIF_MAILBOX_C2S_INDEX mID, csif_uint32 mail)
+{
+ if(mail == CSIF_MAILBOX_EMPTY_VALUE || mail == CSIF_MAILBOX_ERROR_VALUE){
+ CSIF_ASSERT(0, mID, mail, 0);
+ return;
+ }
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ CSIF_REG_WRITE(CSIF_MAILBOX_SEND + mID*CSIF_MAILBOX_SIZE, mail);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(mID, (csif_uint32*)(CSIF_MAILBOX_SEND + mID*CSIF_MAILBOX_SIZE), mail, caller);
+#endif /* __CSIF_DEBUG__ */
+}
+
+
+
+CSIF_MAILBOX_STATUS_t CSIF_MAILBOX_C2S_Status_Read(CSIF_MAILBOX_C2S_INDEX mID)
+{
+ CSIF_MAILBOX_STATUS_t read_status_struct;
+ csif_uint32 read_status = 0;
+ CSIF_REG_READ(CSIF_MAILBOX_STATUS + mID*CSIF_MAILBOX_SIZE, read_status);
+ //printf("read mailbox %d status: %x\n", mID, read_status);
+ if(csif_mailbox_entry_num_table[mID] == 256)
+ {
+ read_status_struct.r_idx = (read_status & CSIF_MAILBOX_256_STATUS_R_IDX_M) >> CSIF_MAILBOX_256_STATUS_R_IDX_P;
+ read_status_struct.w_idx = (read_status & CSIF_MAILBOX_256_STATUS_W_IDX_M) >> CSIF_MAILBOX_256_STATUS_W_IDX_P;
+ read_status_struct.mail_num = (read_status & CSIF_MAILBOX_256_STATUS_MAIL_NUM_M) >> CSIF_MAILBOX_256_STATUS_MAIL_NUM_P;
+ }
+ else if(csif_mailbox_entry_num_table[mID] == 64)
+ {
+ read_status_struct.r_idx = (read_status & CSIF_MAILBOX_64_STATUS_R_IDX_M) >> CSIF_MAILBOX_64_STATUS_R_IDX_P;
+ read_status_struct.w_idx = (read_status & CSIF_MAILBOX_64_STATUS_W_IDX_M) >> CSIF_MAILBOX_64_STATUS_W_IDX_P;
+ read_status_struct.mail_num = (read_status & CSIF_MAILBOX_64_STATUS_MAIL_NUM_M) >> CSIF_MAILBOX_64_STATUS_MAIL_NUM_P;
+ }
+ else
+ {
+ // undefined CSIF mailbox entry num
+ CSIF_ASSERT(0, mID, csif_mailbox_entry_num_table[mID], 0);
+ }
+ if(csif_mailbox_entry_num_table[mID] == 256)
+ {
+ read_status_struct.r_idx = read_status_struct.r_idx & MAILBOX_256_WRAP_MASK;
+ read_status_struct.w_idx = read_status_struct.w_idx & MAILBOX_256_WRAP_MASK;
+ }
+ else if(csif_mailbox_entry_num_table[mID] == 64)
+ {
+ read_status_struct.r_idx = read_status_struct.r_idx & MAILBOX_64_WRAP_MASK;
+ read_status_struct.w_idx = read_status_struct.w_idx & MAILBOX_64_WRAP_MASK;
+ }
+ return read_status_struct;
+}
+
+csif_uint32 CSIF_MAILBOX_C2S_Max_FIFO_Usage_Read(CSIF_MAILBOX_C2S_INDEX mID)
+{
+ csif_uint32 max_record = 0;
+ CSIF_REG_READ(CSIF_MAILBOX_MAX_FIFO_USAGE + mID*CSIF_MAILBOX_SIZE, max_record);
+ return max_record;
+}
+
+// for MCU L1 LPWR debug feature, not normal case
+csif_uint32 CSIF_MAILBOX_C2S_Read(CSIF_MAILBOX_C2S_INDEX mID)
+{
+ csif_uint32 read_mail = 0;
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ CSIF_REG_READ(CSIF_MAILBOX_RECV + mID*CSIF_MAILBOX_SIZE, read_mail);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(mID, (csif_uint32*)(CSIF_MAILBOX_RECV + mID*CSIF_MAILBOX_SIZE), read_mail, caller);
+#endif /* __CSIF_DEBUG__ */
+ return read_mail;
+}
+// ----------------------------------------------- //
+
+csif_uint32 CSIF_MAILBOX_S2C_Read(CSIF_MAILBOX_S2C_INDEX mID)
+{
+ csif_uint32 read_mail = 0;
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ CSIF_REG_READ(CSIF_MAILBOX_RECV + mID*CSIF_MAILBOX_SIZE, read_mail);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(mID, (csif_uint32*)(CSIF_MAILBOX_RECV + mID*CSIF_MAILBOX_SIZE), read_mail, caller);
+#endif /* __CSIF_DEBUG__ */
+ return read_mail;
+}
+
+CSIF_MAILBOX_STATUS_t CSIF_MAILBOX_S2C_Status_Read(CSIF_MAILBOX_S2C_INDEX mID)
+{
+ CSIF_MAILBOX_STATUS_t read_status_struct;
+ csif_uint32 read_status = 0;
+ CSIF_REG_READ(CSIF_MAILBOX_STATUS + mID*CSIF_MAILBOX_SIZE, read_status);
+ if(csif_mailbox_entry_num_table[mID] == 256)
+ {
+ read_status_struct.r_idx = (read_status & CSIF_MAILBOX_256_STATUS_R_IDX_M) >> CSIF_MAILBOX_256_STATUS_R_IDX_P;
+ read_status_struct.w_idx = (read_status & CSIF_MAILBOX_256_STATUS_W_IDX_M) >> CSIF_MAILBOX_256_STATUS_W_IDX_P;
+ read_status_struct.mail_num = (read_status & CSIF_MAILBOX_256_STATUS_MAIL_NUM_M) >> CSIF_MAILBOX_256_STATUS_MAIL_NUM_P;
+ }
+ else if(csif_mailbox_entry_num_table[mID] == 64)
+ {
+ read_status_struct.r_idx = (read_status & CSIF_MAILBOX_64_STATUS_R_IDX_M) >> CSIF_MAILBOX_64_STATUS_R_IDX_P;
+ read_status_struct.w_idx = (read_status & CSIF_MAILBOX_64_STATUS_W_IDX_M) >> CSIF_MAILBOX_64_STATUS_W_IDX_P;
+ read_status_struct.mail_num = (read_status & CSIF_MAILBOX_64_STATUS_MAIL_NUM_M) >> CSIF_MAILBOX_64_STATUS_MAIL_NUM_P;
+ }
+ else
+ {
+ // undefined CSIF mailbox entry num
+ CSIF_ASSERT(0, mID, csif_mailbox_entry_num_table[mID], 0);
+ }
+ if(csif_mailbox_entry_num_table[mID] == 256)
+ {
+ read_status_struct.r_idx = read_status_struct.r_idx & MAILBOX_256_WRAP_MASK;
+ read_status_struct.w_idx = read_status_struct.w_idx & MAILBOX_256_WRAP_MASK;
+ }
+ else if(csif_mailbox_entry_num_table[mID] == 64)
+ {
+ read_status_struct.r_idx = read_status_struct.r_idx & MAILBOX_64_WRAP_MASK;
+ read_status_struct.w_idx = read_status_struct.w_idx & MAILBOX_64_WRAP_MASK;
+ }
+ return read_status_struct;
+}
+
+csif_uint32 CSIF_MAILBOX_S2C_Max_FIFO_Usage_Read(CSIF_MAILBOX_S2C_INDEX mID)
+{
+ csif_uint32 max_record = 0;
+ CSIF_REG_READ(CSIF_MAILBOX_MAX_FIFO_USAGE + mID*CSIF_MAILBOX_SIZE, max_record);
+ return max_record;
+}
+
+void CSIF_OLPDET_Set(csif_uint32 addr, csif_uint32 size)
+{
+ addr = addr & CSIF_DSM_MASK;
+ CSIF_ASSERT(((addr & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size >= 0) && (size <= 1024 )), addr, size, 0);
+ CSIF_ASSERT(((addr >= 0) && (addr <= CSIF_DSM_SIZE)), addr, size, 0);
+ CSIF_ASSERT((addr+size <= CSIF_DSM_SIZE), addr, size, 0);
+
+ csif_uint32 two_word_addr = 0;
+ csif_uint32 two_word_size = 0;
+ csif_uint32 set_value = 0;
+
+ // covert to 2 word unit
+ two_word_addr = addr/CSIF_OLPDET_UNIT;
+ two_word_size = size/CSIF_OLPDET_UNIT;
+ set_value = (two_word_addr << CSIF_OLPDET_SET_OFFSET_P) | (two_word_size << CSIF_OLPDET_SET_LENGTH_P);
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+
+#if !defined(MT6297) || defined(__CSIF_PROFILING__) || defined(__NL1_ESL__)// not Apollo, use normal OLPDET set/clr flow
+//#if !defined(MT6297) // not Apollo, use normal OLPDET set/clr flow
+ CSIF_REG_WRITE(CSIF_OLPDET_SET, set_value);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord((size << 16 | addr), (csif_uint32*)(CSIF_OLPDET_SET), set_value, caller);
+#endif /* __CSIF_DEBUG__ */
+#else // Apollo, for Apollo OLPDET HW bug
+ /* Use HWITC to create critical section.
+ Note that we use a special light-weight ITC Macro here to avoid
+ CHRT domain cannot DI fatal error.
+ It is a SS internal API, and does not do timing violation check.
+ Need SS's approval before using it */
+ kal_uint32 irq_mask=0, mt_mask=0, ori_prio=0;
+ KAL_ITC_LOCK_TAKE_DI_DMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+ d2d_wreg32(CSIF_OLPDET_SET, set_value);
+ /* Release HWITC */
+ KAL_ITC_LOCK_GIVE_EI_EMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord((D2D_DEBUG_RECORD_PREFIX | size << 16 | addr), (csif_uint32*)(CSIF_OLPDET_SET), set_value, caller);
+#endif /* __CSIF_DEBUG__ */
+#endif // end of proj option
+}
+
+void CSIF_OLPDET_Clr(csif_uint32 addr, csif_uint32 size)
+{
+ addr = addr & CSIF_DSM_MASK;
+ CSIF_ASSERT(((addr & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size >= 0) && (size <= 1024 )), addr, size, 0);
+ CSIF_ASSERT(((addr >= 0) && (addr <= CSIF_DSM_SIZE)), addr, size, 0);
+ CSIF_ASSERT((addr+size <= CSIF_DSM_SIZE), addr, size, 0);
+
+ csif_uint32 two_word_addr = 0;
+ csif_uint32 two_word_size = 0;
+ csif_uint32 set_value = 0;
+
+ // covert to 2 word unit
+ two_word_addr = addr/CSIF_OLPDET_UNIT;
+ two_word_size = size/CSIF_OLPDET_UNIT;
+ set_value = (two_word_addr << CSIF_OLPDET_CLR_OFFSET_P) | (two_word_size << CSIF_OLPDET_CLR_LENGTH_P);
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+#if !defined(MT6297) || defined(__CSIF_PROFILING__) || defined(__NL1_ESL__)// not Apollo, use normal OLPDET set/clr flow
+//#if !defined(MT6297) // not Apollo, use normal OLPDET set/clr flow
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR, set_value);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord((size << 16 | addr), (csif_uint32*)(CSIF_OLPDET_CLR), set_value, caller);
+#endif /* __CSIF_DEBUG__ */
+#else // Apollo, for Apollo OLPDET HW bug
+ /* Use HWITC to create critical section.
+ Note that we use a special light-weight ITC Macro here to avoid
+ CHRT domain cannot DI fatal error.
+ It is a SS internal API, and does not do timing violation check.
+ Need SS's approval before using it */
+ kal_uint32 irq_mask=0, mt_mask=0, ori_prio=0;
+ KAL_ITC_LOCK_TAKE_DI_DMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+ d2d_wreg32(CSIF_OLPDET_CLR, set_value);
+ /* Release HWITC */
+ KAL_ITC_LOCK_GIVE_EI_EMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord((D2D_DEBUG_RECORD_PREFIX | size << 16 | addr), (csif_uint32*)(CSIF_OLPDET_CLR), set_value, caller);
+#endif /* __CSIF_DEBUG__ */
+#endif // end of proj option
+}
+
+csif_uint32 CSIF_Total_Inuse_Mem_Size()
+{
+ csif_uint32 read_size;
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE, read_size);
+ return (read_size * CSIF_OLPDET_UNIT);
+}
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)
+csif_uint32 CSIF_Total_Max_Mem_Size()
+{
+ csif_uint32 read_size;
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE, read_size);
+ return (read_size * CSIF_OLPDET_UNIT);
+}
+
+void CSIF_Total_Max_Mem_Size_Clear()
+{
+ CSIF_REG_WRITE(CSIF_OLPDET_MAX_MAIL_SIZE_CLR, 0x1);
+}
+#elif defined(MT6297)
+#else
+ #error "Unsupport project, need to do platform option porting!!"
+#endif
+
+void CSIF_OLPDET_Multiple_Set(csif_uint32 length, CSIF_OLPDET_CONFIG_t* olpdet_config_array)
+{
+ csif_uint32 idx = 0;
+ csif_uint32 two_word_addr = 0;
+ csif_uint32 two_word_size = 0;
+ csif_uint32 set_value = 0;
+ csif_uint32 addr = 0;
+ csif_uint32 size = 0;
+
+#if defined(MT6297) && !defined(__CSIF_PROFILING__) && !defined(__NL1_ESL__)// Apollo, for Apollo OLPDET HW bug
+ kal_uint32 irq_mask=0, mt_mask=0, ori_prio=0;
+#endif
+
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 multiIdx = kal_atomic_inc_return(&MultiOperation_debug_idx);
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+
+ CSIF_ASSERT((length >= 1 ), length, (csif_uint32)&olpdet_config_array, 0);
+
+ for(idx = 0; idx < length; idx++){
+ addr = (olpdet_config_array[idx].addr) & CSIF_DSM_MASK;
+ size = (olpdet_config_array[idx].size);
+ CSIF_ASSERT(((addr & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size >= 0) && (size <= 1024 )), addr, size, 0);
+ CSIF_ASSERT(((addr >= 0) && (addr <= CSIF_DSM_SIZE)), addr, size, 0);
+ CSIF_ASSERT((addr+size <= CSIF_DSM_SIZE), addr, size, 0);
+ // covert to 2 word unit
+ two_word_addr = addr/CSIF_OLPDET_UNIT;
+ two_word_size = size/CSIF_OLPDET_UNIT;
+ set_value = (two_word_addr << CSIF_OLPDET_SET_OFFSET_P) | (two_word_size << CSIF_OLPDET_SET_LENGTH_P);
+#if !defined(MT6297) || defined(__CSIF_PROFILING__) || defined(__NL1_ESL__)// not Apollo, use normal OLPDET set/clr flow
+//#if !defined(MT6297) // not Apollo, use normal OLPDET set/clr flow
+ if(idx == length - 1){
+ CSIF_REG_WRITE(CSIF_OLPDET_SET, set_value); // last operation, use bank A and MO_sync()
+ }else{
+ CSIF_REG_WRITE_BANKB(CSIF_OLPDET_SET, set_value); // continous operation, use bank B without MO_sync()
+ }
+#if defined(__CSIF_DEBUG__)
+ csif_MultiDebugAddRecord(multiIdx, (csif_uint32*)(CSIF_OLPDET_SET), set_value, caller);
+#endif /* __CSIF_DEBUG__ */
+#else // Apollo, for Apollo OLPDET HW bug
+ /* Use HWITC to create critical section.
+ Note that we use a special light-weight ITC Macro here to avoid
+ CHRT domain cannot DI fatal error.
+ It is a SS internal API, and does not do timing violation check.
+ Need SS's approval before using it */
+ KAL_ITC_LOCK_TAKE_DI_DMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+ d2d_wreg32(CSIF_OLPDET_SET, set_value);
+ /* Release HWITC */
+ KAL_ITC_LOCK_GIVE_EI_EMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+#if defined(__CSIF_DEBUG__)
+ csif_MultiDebugAddRecord((D2D_DEBUG_RECORD_PREFIX | multiIdx), (csif_uint32*)(CSIF_OLPDET_SET), set_value, caller);
+#endif /* __CSIF_DEBUG__ */
+#endif // end of proj option
+ }
+}
+
+void CSIF_OLPDET_Multiple_Clr(csif_uint32 length, CSIF_OLPDET_CONFIG_t* olpdet_config_array)
+{
+ csif_uint32 idx = 0;
+ csif_uint32 two_word_addr = 0;
+ csif_uint32 two_word_size = 0;
+ csif_uint32 set_value = 0;
+ csif_uint32 addr = 0;
+ csif_uint32 size = 0;
+
+#if defined(MT6297) && !defined(__CSIF_PROFILING__) && !defined(__NL1_ESL__)// Apollo, for Apollo OLPDET HW bug
+ kal_uint32 irq_mask=0, mt_mask=0, ori_prio=0;
+#endif
+
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 multiIdx = kal_atomic_inc_return(&MultiOperation_debug_idx);
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+
+ CSIF_ASSERT((length >= 1 ), length, (csif_uint32)&olpdet_config_array, 0);
+
+ for(idx = 0; idx < length; idx++){
+ addr = (olpdet_config_array[idx].addr) & CSIF_DSM_MASK;
+ size = (olpdet_config_array[idx].size);
+ CSIF_ASSERT(((addr & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size >= 0) && (size <= 1024 )), addr, size, 0);
+ CSIF_ASSERT(((addr >= 0) && (addr <= CSIF_DSM_SIZE)), addr, size, 0);
+ CSIF_ASSERT((addr+size <= CSIF_DSM_SIZE), addr, size, 0);
+ // covert to 2 word unit
+ two_word_addr = addr/CSIF_OLPDET_UNIT;
+ two_word_size = size/CSIF_OLPDET_UNIT;
+ set_value = (two_word_addr << CSIF_OLPDET_CLR_OFFSET_P) | (two_word_size << CSIF_OLPDET_CLR_LENGTH_P);
+#if !defined(MT6297) || defined(__CSIF_PROFILING__) || defined(__NL1_ESL__)// not Apollo, use normal OLPDET set/clr flow
+//#if !defined(MT6297) // not Apollo, use normal OLPDET set/clr flow
+ if(idx == length - 1){
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR, set_value); // last operation, use bank A and MO_sync()
+ }else{
+ CSIF_REG_WRITE_BANKB(CSIF_OLPDET_CLR, set_value); // continous operation, use bank B without MO_sync()
+ }
+#if defined(__CSIF_DEBUG__)
+ csif_MultiDebugAddRecord(multiIdx, (csif_uint32*)(CSIF_OLPDET_CLR), set_value, caller);
+#endif /* __CSIF_DEBUG__ */
+#else // Apollo, for Apollo OLPDET HW bug
+ /* Use HWITC to create critical section.
+ Note that we use a special light-weight ITC Macro here to avoid
+ CHRT domain cannot DI fatal error.
+ It is a SS internal API, and does not do timing violation check.
+ Need SS's approval before using it */
+ KAL_ITC_LOCK_TAKE_DI_DMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+ d2d_wreg32(CSIF_OLPDET_CLR, set_value);
+ /* Release HWITC */
+ KAL_ITC_LOCK_GIVE_EI_EMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+#if defined(__CSIF_DEBUG__)
+ csif_MultiDebugAddRecord((D2D_DEBUG_RECORD_PREFIX | multiIdx), (csif_uint32*)(CSIF_OLPDET_CLR), set_value, caller);
+#endif /* __CSIF_DEBUG__ */
+#endif // end of proj option
+ }
+}
+
+void CSIF_MAILBOX_C2S_Multiple_Send(csif_uint32 length, CSIF_MAIL_INFO_t* mail_info_array)
+{
+ csif_uint32 idx = 0;
+ csif_uint32 mID = 0;
+ csif_uint32 mail = 0;
+
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 multiIdx = kal_atomic_inc_return(&MultiOperation_debug_idx);
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+
+ CSIF_ASSERT((length >= 1 ), length, (csif_uint32)&mail_info_array, 0);
+ for(idx = 0; idx < length; idx++){
+ mID = mail_info_array[idx].mID;
+ mail = mail_info_array[idx].mail;
+ if(mail == CSIF_MAILBOX_EMPTY_VALUE || mail == CSIF_MAILBOX_ERROR_VALUE){
+ CSIF_ASSERT(0, mID, mail, 0);
+ return;
+ }
+ if(idx == length - 1){
+ CSIF_REG_WRITE((CSIF_MAILBOX_SEND + (mID*CSIF_MAILBOX_SIZE)), mail); // last operation, use bank A and MO_sync()
+ }else{
+ CSIF_REG_WRITE_BANKB((CSIF_MAILBOX_SEND + (mID*CSIF_MAILBOX_SIZE)), mail); // continous operation, use bank B without MO_sync()
+ }
+#if defined(__CSIF_DEBUG__)
+ csif_MultiDebugAddRecord(multiIdx, (csif_uint32*)(CSIF_MAILBOX_SEND + (mID*CSIF_MAILBOX_SIZE)), mail, caller);
+#endif /* __CSIF_DEBUG__ */
+ }
+}
+
+void CSIF_MAILBOX_C2S_Multiple_Send_C2S_SWI_Multiple_Set(csif_uint32 mailbox_length, CSIF_MAIL_INFO_t* mail_info_array, \
+ csif_uint32 irq_length, CSIF_IRQ_INFO_t* irq_info_array)
+{
+ csif_uint32 idx = 0;
+ csif_uint32 mID = 0;
+ csif_uint32 mail = 0;
+
+ csif_uint32 before_status = 0xFFFFFFFF;
+ csif_uint32 nID = 0;
+ csif_uint32 code = 0;
+ csif_uint32 code_limit = 0;
+
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 multiIdx = kal_atomic_inc_return(&MultiOperation_debug_idx);
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+
+ CSIF_ASSERT((mailbox_length >= 1 ), mailbox_length, (csif_uint32)&mail_info_array, 0);
+ CSIF_ASSERT((irq_length >= 1 ), irq_length, (csif_uint32)&irq_info_array, 0);
+ // Mailbox multiple send
+ for(idx = 0; idx < mailbox_length; idx++)
+ {
+ mID = mail_info_array[idx].mID;
+ mail = mail_info_array[idx].mail;
+ if(mail == CSIF_MAILBOX_EMPTY_VALUE || mail == CSIF_MAILBOX_ERROR_VALUE){
+ CSIF_ASSERT(0, mID, mail, 0);
+ return;
+ }
+ CSIF_REG_WRITE_BANKB((CSIF_MAILBOX_SEND + (mID*CSIF_MAILBOX_SIZE)), mail); // continous operation, use bank B without MO_sync()
+#if defined(__CSIF_DEBUG__)
+ csif_MultiDebugAddRecord(multiIdx, (csif_uint32*)(CSIF_MAILBOX_SEND + (mID*CSIF_MAILBOX_SIZE)), mail, caller);
+#endif /* __CSIF_DEBUG__ */
+ }
+ // IRQ multiple set
+ for(idx = 0; idx < irq_length; idx++)
+ {
+ nID = irq_info_array[idx].nID;
+ code = irq_info_array[idx].code;
+
+ // assertion of user setting code out of code limit
+ code_limit = CSIF_C2S_Interrupt_Num[nID];
+ CSIF_ASSERT(code < code_limit, nID, code, code_limit);
+
+ // no need this special handle in Mercury if HW support IRQ ovfl enable switch
+ if(csif_c2s_irq_ovfl_allow[nID][code] == CSIF_TRUE)
+ {
+ if(idx == irq_length - 1)
+ {
+ CSIF_REG_WRITE((CSIF_C2S_IRQ_SET + (nID*CSIF_C2S_IRQ_SIZE)), 1 << code); // last operation, use bank A and MO_sync()
+ }else
+ {
+ CSIF_REG_WRITE_BANKB((CSIF_C2S_IRQ_SET + (nID*CSIF_C2S_IRQ_SIZE)), 1 << code); // continous operation, use bank B without MO_sync()
+ }
+
+ }else
+ {
+ // Use HWITC to create critical section
+ kal_hrt_take_itc_lock(KAL_ITC_CSIF_LOCK, KAL_INFINITE_WAIT);
+ /* end of HWITC take */
+ CSIF_REG_READ(CSIF_C2S_IRQ_STATUS + nID*CSIF_C2S_IRQ_SIZE, before_status);
+ if((before_status & (1 << code)) == 0){
+ if(idx == irq_length - 1)
+ {
+ CSIF_REG_WRITE((CSIF_C2S_IRQ_SET + (nID*CSIF_C2S_IRQ_SIZE)), 1 << code); // last operation, use bank A and MO_sync()
+ }else
+ {
+ CSIF_REG_WRITE_BANKB((CSIF_C2S_IRQ_SET + (nID*CSIF_C2S_IRQ_SIZE)), 1 << code); // continous operation, use bank B without MO_sync()
+ }
+ /* Release HWITC */
+ kal_hrt_give_itc_lock(KAL_ITC_CSIF_LOCK);
+ }
+ else{
+ /* Release HWITC */
+ kal_hrt_give_itc_lock(KAL_ITC_CSIF_LOCK);
+ CSIF_ASSERT((before_status & (1 << code)) == 0, nID, code, 0);
+ //CSIF_REG_WRITE(CSIF_C2S_IRQ_SET + nID*CSIF_C2S_IRQ_SIZE, 1 << code);
+ }
+ }
+#if defined(__CSIF_DEBUG__)
+ csif_MultiDebugAddRecord(multiIdx, (csif_uint32*)(CSIF_C2S_IRQ_SET + (nID*CSIF_C2S_IRQ_SIZE)), 1 << code, caller);
+#endif /* __CSIF_DEBUG__ */
+ }
+}
+//**** mailbox debug usage ****//
+
+
+//**** CSIF test ****//
+#if defined(__CSIF_DRV_TEST__)
+void CSIF_Test(CSIF_ID_STATUS_t* status_id){
+
+}
+#endif
diff --git a/mcu/driver/devdrv/csif/mt6297p/inc/csif_SSDVT.h b/mcu/driver/devdrv/csif/mt6297p/inc/csif_SSDVT.h
new file mode 100644
index 0000000..550979f
--- /dev/null
+++ b/mcu/driver/devdrv/csif/mt6297p/inc/csif_SSDVT.h
@@ -0,0 +1,398 @@
+//***********************
+// Instance number
+//***********************
+#define S2C_IRQ_NUM (6)
+#define C2S_IRQ_NUM (4)
+#define S2C_IDLE_IRQ_NUM (2)
+#define DSP_MPU_NUM (2)
+#define L1_MPU_NUM (2)
+#define ERROR_SOURCE_NUM (2)
+#define DSM_SRAM_SIZE (8192)
+#define CSIF_DSR_SIZE_TEMP (CSIF_DSR_SIZE) // 1KB
+#define DSP_CORE_TH_NUM (4)
+#define CSIF_MAILBOX_NUM (6)
+#define CSIF_64_MAILBOX_NUM (5)
+#define CSIF_256_MAILBOX_NUM (1)
+#define CSIF_MAX_MAILBOX_ENTRY_NUM (256)
+#define OLPDET_MUM_BIT_NUM (CSIF_DSM_SIZE/CSIF_OLPDET_UNIT)
+
+//***********************
+// Error bit
+//***********************
+#define S2C_IRQ_OVFL_ERROR_BIT_OFFSET (0)
+#define S2C_IRQ0_OVFL_ERROR_BIT (0)
+#define S2C_IRQ1_OVFL_ERROR_BIT (1)
+#define S2C_IRQ2_OVFL_ERROR_BIT (2)
+#define S2C_IRQ3_OVFL_ERROR_BIT (3)
+#define S2C_IRQ4_OVFL_ERROR_BIT (4)
+#define S2C_IRQ5_OVFL_ERROR_BIT (5)
+#define DSP_MPU_ERROR_BIT_OFFSET (10)
+#define DSP_MPU0_ERROR_BIT (10)
+#define DSP_MPU1_ERROR_BIT (11)
+#define DSP_UNDEF_REGION_BIT_OFFSET (12)
+#define DSP_UNDEF_DSM_WRITE (12)
+#define DSP_UNDEF_DSM_READ (13)
+#define DSP_UNDEF_DSR_WRITE (14)
+#define DSP_UNDEF_DSR_READ (15)
+#define MPU_CFG_ERROR_BIT_OFFSET (16)
+#define DSP_MPU0_CFG_ERROR_BIT (16)
+#define DSP_MPU1_CFG_ERROR_BIT (17)
+#define L1_MPU0_CFG_ERROR_BIT (18)
+#define L1_MPU1_CFG_ERROR_BIT (19)
+#define MAILBOX_ERR_BIT_OFFSET (20)
+#define MAILBOX0_ERR_BIT (20)
+#define MAILBOX1_ERR_BIT (21)
+#define MAILBOX2_ERR_BIT (22)
+#define MAILBOX3_ERR_BIT (23)
+#define MAILBOX4_ERR_BIT (24)
+#define MAILBOX5_ERR_BIT (25)
+#define OLPDET_ERR_BIT (26)
+
+
+
+//***********************
+// Error Source bit
+//***********************
+#define S2C_IRQ_OVFL_ERROR_SOURCE0_OFFSET (0)
+#define S2C_IRQ_OVFL_ERROR_SOURCE_BIT_WIDTH (8)
+#define S2C_IRQ_OVFL_ERROR_SOURCE_BIT_MASK (0xFF)
+#define S2C_IRQ_OVFL_ERROR_SOURCE1_OFFSET (0)
+//#if !defined(__JSP__)
+#define ERROR_SOURCE_ID_MCORE0_TH0 (0)
+#define ERROR_SOURCE_ID_MCORE0_TH1 (1)
+#define ERROR_SOURCE_ID_MCORE0_TH2 (2)
+#define ERROR_SOURCE_ID_MCORE0_TH3 (3)
+#define ERROR_SOURCE_ID_MCORE1_TH0 (8)
+#define ERROR_SOURCE_ID_MCORE1_TH1 (9)
+#define ERROR_SOURCE_ID_MCORE1_TH2 (10)
+#define ERROR_SOURCE_ID_MCORE1_TH3 (11)
+/*
+#else
+#define ERROR_SOURCE_ID_MCORE0_TH0 (0)
+#define ERROR_SOURCE_ID_MCORE0_TH1 (1)
+#define ERROR_SOURCE_ID_MCORE0_TH2 (2)
+#define ERROR_SOURCE_ID_MCORE0_TH3 (3)
+#define ERROR_SOURCE_ID_MCORE1_TH0 (4)
+#define ERROR_SOURCE_ID_MCORE1_TH1 (5)
+#define ERROR_SOURCE_ID_MCORE1_TH2 (6)
+#define ERROR_SOURCE_ID_MCORE1_TH3 (7)
+#endif
+*/
+#define ERROR_SOURCE_ID_DEFAULT_VALUE (0xFF)
+
+#define DSP_MPU_ERROR_SOURCE1_OFFSET (16)
+#define DSP_MPU_ERROR_SOURCE_BIT_MASK (0xFF)
+#define DSP_MPU_ERROR_SOURCE_BIT_WIDTH (8)
+
+#define DSP_UNDEFINED_ERROR_SOURCE2_OFFSET (0)
+#define DSP_UNDEFINED_ERROR_SOURCE_BIT_MASK (0xFF)
+#define DSP_UNDEFINED_ERROR_SOURCE_BIT_WIDTH (8)
+
+#define MAILBOX_ERROR_SOURCE3_OFFSET (0)
+#define MAILBOX_ERROR_SOURCE4_OFFSET (0)
+#define MAILBOX_ERROR_SOURCE_BIT_MASK (0xFF)
+#define MAILBOX_ERROR_SOURCE_BIT_WIDTH (8)
+
+#define OLPDET_ERROR_SOURCE4_OFFSET (16)
+#define OLPDET_ERROR_SOURCE_BIT_MASK (0xFF)
+#define OLPDET_ERROR_SOURCE_BIT_WIDTH (8)
+
+
+//***********************
+// MPU bit
+//***********************
+#define MPU_TYPE_READ (0)
+#define MPU_TYPE_WRITE (1)
+#define MPU_TYPE_NUM (2)
+#define DSP_MPU_OFFSET (0)
+#define L1_MPU_OFFSET (2)
+#define MPU_TYPE_BIT_OFFSET (16)
+#define MPU_START_MASK (0xFFFF)
+#define MPU_RANGE_MASK (0xFFFF)
+#define MPU_TYPE_BIT_MASK (0x10000)
+
+
+
+//***********************
+// CR default value
+//***********************
+#define S2C_IRQ_STATUS_DEFAULT_VAL (0x0)
+#define S2C_IRQ_MASKED_STATUS_DEFAULT_VAL (0x0)
+#define S2C_IRQ_EN_DEFAULT_VAL (0x0)
+
+#define DSP_CORE_IDLE_DEFAULT_VAL (0x0)
+#define S2C_IRQ_IDLE_EN_DEFAULT_VAL (0x0)
+
+#define C2S_IRQ_STATUS_DEFAULT_VAL (0x0)
+#define C2S_IRQ_MASKED_STATUS_DEFAULT_VAL (0x0)
+#define C2S_IRQ_EN_DEFAULT_VAL (0x0)
+
+#define MPU_START_ADDR_DEFAULT_VAL (0x0)
+#define MPU_RANGE_DEFAULT_VAL (0x0)
+#define MPU_ERR_ADDR_DEFAULT_VAL (0xA4CF0000)
+
+#define DSM_UNDEFINED_REGION_STATUS_DEFAULT_VAL (0x0)
+#define DSR_UNDEFINED_REGION_STATUS_DEFAULT_VAL (0xA4CF0000)
+
+#define DSP_ERROR_FLAG_DEFAULT_VAL (0x0)
+#define DSP_ERROR_SNAPSHOT_DEFAULT_VAL (0x0)
+#define DSP_ERROR_EN_DEFAULT_VAL (0x07FFFFFF)
+#define DSP_ERROR_SOURCE0_DEFAULT_VAL (0xFFFFFFFF)
+#define DSP_ERROR_SOURCE1_DEFAULT_VAL (0xFFFFFFFF)
+#define DSP_ERROR_SOURCE2_DEFAULT_VAL (0xFFFFFFFF)
+#define DSP_ERROR_SOURCE3_DEFAULT_VAL (0xFFFFFFFF)
+#define DSP_ERROR_SOURCE4_DEFAULT_VAL (0x00FFFFFF)
+
+#define L1_ERROR_FLAG_DEFAULT_VAL (0x0)
+#define L1_ERROR_SNAPSHOT_DEFAULT_VAL (0x0)
+#define L1_ERROR_EN_DEFAULT_VAL (0x07FFFFFF)
+
+#define S2C_IRQ_OVFL_STATUS_DEFAULT_VAL (0x0)
+#define C2S_IRQ_OVFL_STATUS_DEFAULT_VAL (0x0)
+
+#define MAILBOX_SEND_DEFAULT_VAL (0x0)
+#define MAILBOX_RECV_DEFAULT_VAL (CSIF_MAILBOX_EMPTY_VALUE)
+#define MAILBOX_STATS_DEFAULT_VAL (0x0)
+#define MAILBOX_MAX_FIFO_USAGE_DEFAULT_VAL (0x0)
+#if defined(MT6885) || defined(MT6873)
+#define MAILBOX_ERROR_SUB_ENABLE_DEFAULT_VAL (0x3)
+#endif
+#define MAILBOX_ERROR_STATUS_DEFAULT_VAL (0x0)
+#define MAILBOX_ERROR_RECORD_DEFAULT_VAL (0x0)
+#define MAILBOX_DEBUG_ENABLE_DEFAULT_VAL (0x0)
+#define MAILBOX_DEBUG_READ_CONTENT_DEFAULT_VAL (MAILBOX_RECV_DEFAULT_VAL)
+#define MAILBOX_DEBUG_READ_IDX_DEFAULT_VAL (0x0)
+
+#define OLPDET_SET_DEFAULT_VAL (0x0)
+#define OLPDET_CLR_DEFAULT_VAL (0x0)
+#define OLPDET_INUSE_MAIL_SIZE_DEFAULT_VAL (0x0)
+#if defined(MT6885) || defined(MT6873)
+#define OLPDET_MAX_MAIL_SIZE_DEFAULT_VAL (0x0)
+#define OLPDET_ERROR_SUB_ENABLE_DEFAULT_VAL (0xF)
+#endif
+#define OLPDET_ERROR_STATUS_DEFAULT_VAL (0x0)
+#define OLPDET_SET_CANDIDATE_RECORD_DEFAULT_VAL (0x0)
+#define OLPDET_CLR_CANDIDATE_RECORD_DEFAULT_VAL (0x0)
+#define OLPDET_DEBUG_READ_MUM_DEFAULT_VAL (0x0)
+#define OLPDET_DEBUG_READ_MUM_IDX_DEFAULT_VAL (0x0)
+#define OLPDET_DEBUG_CLR_MUM_ENABLE_DEFAULT_VAL (0x0)
+
+//***********************
+// CR bit width
+//***********************
+#define S2C_IRQ_EN_WIDTH (32)
+#define C2S_IRQ_EN_WIDTH (32)
+#define MPU_START_WIDTH (16)
+#define MPU_RANGE_WIDTH (17)
+#define DSP_ERROR_EN_WIDTH (27)
+#define L1_ERROR_EN_WIDTH (27)
+#define MAILBOX_SEND_WIDTH (32)
+#define MAILBOX_ERROR_SUB_ENABLE_WIDTH (2)
+#define MAILBOX_DEBUG_ENABLE_WIDTH (1)
+#define OLPDET_SET_CLR_OFFSET_WIDTH (11)
+#define OLPDET_SET_CLR_LENGTH_WIDTH (8)
+#define OLPDET_ERROR_SUB_ENABLE_WIDTH (4)
+#define OLPDET_DEBUG_CLR_MUM_ENABLE_WIDTH (1)
+
+
+//***********************
+// RSVD CR for cross core sync
+//***********************
+#if !defined(__CSIF_SHAOLIN_64b_WORKAROUND__)
+#if defined(MT6297)
+#define CSIF_RSVD_0 (CSIF_DSR_BASE + 0x174)
+#define CSIF_RSVD_1 (CSIF_DSR_BASE + 0x178)
+#elif defined(MT6885) || defined(MT6873)
+#define CSIF_RSVD_0 (CSIF_DSR_BASE + 0x1D8)
+#define CSIF_RSVD_1 (CSIF_DSR_BASE + 0x1DC)
+#else
+ #error "unsupport project, may need porting"
+#endif // project
+#else
+#define CSIF_RSVD_0 (CSIF_DSM_BASE + 0x2960)
+#define CSIF_RSVD_1 (CSIF_DSM_BASE + 0x2964)
+#endif
+//***********************
+// Cross core sync pattern
+//***********************
+#define CSIF_CROSS_START1_MCU (0xFF97B001)
+#define CSIF_CROSS_START1_DSP (0xFF97A001)
+
+#define CSIF_CROSS_START2_MCU (0xFF97B002)
+#define CSIF_CROSS_START2_DSP (0xFF97A002)
+
+#define CSIF_CROSS_IRQ_S2C_WAIT (0xFF97CC0A)
+#define CSIF_CROSS_IRQ_S2C_PASS (0xFF97CC0B)
+#define CSIF_CROSS_IRQ_C2S_WAIT (0xFF97DD0A)
+#define CSIF_CROSS_IRQ_C2S_PASS (0xFF97DD0B)
+
+#define CSIF_CROSS_IDLE_IRQ_TH0_SYNC (0xAF97000A)
+#define CSIF_CROSS_IDLE_IRQ_TH0_SYNC_DONE (0xAF97001A)
+#define CSIF_CROSS_IDLE_IRQ_TH1_SYNC (0xAF97000B)
+#define CSIF_CROSS_IDLE_IRQ_TH1_SYNC_DONE (0xAF97001B)
+#define CSIF_CROSS_IDLE_IRQ_TH2_SYNC (0xAF97000C)
+#define CSIF_CROSS_IDLE_IRQ_TH2_SYNC_DONE (0xAF97001C)
+#define CSIF_CROSS_IDLE_IRQ_TH3_SYNC (0xAF97000D)
+#define CSIF_CROSS_IDLE_IRQ_TH3_SYNC_DONE (0xAF97001D)
+#define CSIF_CROSS_IDLE_IRQ_CORE_SYNC (0xAF9700FF)
+
+#define CSIF_CROSS_MAILBOX_SYNC1_MCU (0xBF97B001)
+#define CSIF_CROSS_MAILBOX_SYNC1_DSP (0xBF97A001)
+#define CSIF_CROSS_MAILBOX_SYNC2_MCU (0xBF97B002)
+#define CSIF_CROSS_MAILBOX_SYNC2_DSP (0xBF97A002)
+
+//***********************
+// IRQ_Handler type
+//***********************
+#define CSIF_IRQ_HANDLER_IRQ_TEST (0x62970000)
+#define CSIF_IRQ_HANDLER_IDLE_IRQ_TEST (0x62970001)
+#define CSIF_IRQ_HANDLER_MAILBOX_TEST (0x62970002)
+
+//***********************
+// IDLE IRQ
+//***********************
+#define CSIF_IDLE_IRQ_BIT_MASK (0x3FF)
+
+//***********************
+// Memory test pattern
+//***********************
+#define MEM_TEST_PATTERN0 (0x0)
+#define MEM_TEST_PATTERN1 (0xFFFFFFFF)
+#define MEM_TEST_PATTERN2 (0xA5A5A5A5)
+#define MEM_TEST_PATTERN3 (0x5A5A5A5A)
+
+#define MEM_TEST_PATTERN1_64 (0xFFFFFFFFFFFFFFFF)
+#define MEM_TEST_PATTERN2_64 (0xA5A5A5A5A5A5A5A5)
+#define MEM_TEST_PATTERN3_64 (0x5A5A5A5A5A5A5A5A)
+
+#define MEM_TEST_PATTERN1_128 (0xFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF)
+#define MEM_TEST_PATTERN2_128 (0xA5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5)
+#define MEM_TEST_PATTERN3_128 (0x5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A5A)
+
+
+//***********************
+// multithread sync pattern
+//***********************
+#define TEST_THREAD_SYNC_T0 (0xFEDC0000)
+#define TEST_THREAD_SYNC_T1 (0xFEDC0001)
+#define TEST_THREAD_SYNC_T2 (0xFEDC0002)
+#define TEST_THREAD_SYNC_T3 (0xFEDC0003)
+#define TEST_THREAD_SYNC_ALL_PASS (0xFEDCABCD)
+
+
+//***********************
+// Mailbox test pattern
+//***********************
+#define MAILBOX_TEST_PATTERN0 (0xABCD0000)
+
+//***********************
+// Mailbox
+//***********************
+
+#define MAILBOX_FULL_ERROR_BIT (0)
+#define MAILBOX_CONTENT_ERROR_BIT (1)
+
+//***********************
+// OLPDET
+//***********************
+
+#define OLPDET_SET_CONTENT_ERROR_BIT (0)
+#define OLPDET_CLR_CONTENT_ERROR_BIT (1)
+#define OLPDET_OLP_HIT_ERROR_BIT (2)
+#define OLPDET_CLR_NOHIT_ERROR_BIT (3)
+
+//***********************
+// DBGC CR
+//***********************
+// csif config is at
+// /proj/d_01055/MDSYS_PLATFORM/alex01055/proj/MT6297MP/pwa/MT6297MP_000/dig/MDSYS_PLATFORM/mml1_mcoresys_irq_map/src_rtl/mml1_mcoresys_irq_map.v
+// bit[10] now
+#if !defined(__JSP__)
+#define DBGC_PRIO0_IF DR_MML1_DSPDBGC_TOP_PRIO0_IF
+#define DBGC_PRIO0_INSEN DR_MML1_DSPDBGC_TOP_PRIO0_INSEN
+#define CSIF_DBGC_BIT (7)
+#else
+#define DBGC_PRIO0_IF DR_MML1_DSPDBGC_TOP_PRIO0_IF
+#define DBGC_PRIO0_INSEN DR_MML1_DSPDBGC_TOP_PRIO0_INSEN
+#define CSIF_DBGC_BIT (15)
+#endif
+
+
+#define EXC_TEST_WAITING_CYCLE (0x6297) // delay time must long enough to wait LISR triggered and handled
+#define EXPECT_EXC_FLAG_TRUE (0xFAAAAAAA)
+#define EXPECT_EXC_FLAG_FALSE (0xFAAADDDD)
+
+#define EXPECT_ERROR_FLAG_TRUE (0xEAAAAAAA)
+#define EXPECT_ERROR_FLAG_FALSE (0xEAAADDDD)
+
+//***********************
+// Testing
+//***********************
+#define ACCESS_TYPE_READ (0x0)
+#define ACCESS_TYPE_WRITE (0x1)
+#define ACCESS_TYPE_NUM (2)
+
+#define ACCESS_REGION_DSM (0)
+#define ACCESS_REGION_DSR (1)
+
+#define LAST_CSIF_CR (DR_MML1_DSPCSIF_TOP_C2S_IRQ3_OVFL_CLR)
+
+#define CORE_IDLE_COMPARE_MASK (0xF)
+
+#define IDLE_IRQ_ENABLE_TYPE_OR (0)
+#define IDLE_IRQ_ENABLE_TYPE_AND (1)
+
+#define EXPECT_IRQ_SET_FLAG_TRUE (0xDABCAAAA)
+#define EXPECT_IRQ_SET_FLAG_FALSE (0xDABCDDDD)
+
+#define IRQ_TEST_WAITING_CYCLE (100)
+
+#if !defined(__MIPS_I7200__)
+#define SSDVT_FAIL_MSG(a, b, c) ssdvt_test_fail_info_notification(a, b, c)
+#define SSDVT_PASS() ssdvt_test_pass_one_thread_notification()
+#define SSDVT_LOG(a, b, c)
+#else
+//#define SSDVT_FAIL_MSG(a, b, c) printf("!!<-[TEST FAIL]->!! code0:%x, code1:%x, code2:%x\n",a,b,c)
+//#define SSDVT_FAIL_MSG(a, b, c) printf("!!<-[TEST FAIL]->!! code0:%x, code1:%x, code2:%x\n",a,b,c);while(1)
+//#define SSDVT_PASS() printf("!!<-[TEST PASS!]->!!");while(1)
+//#define SSDVT_LOG(a, b, c) printf("[Log]: code0:%x, code1:%x, code2:%x\n",a,b,c)
+#define SSDVT_FAIL_MSG(a, b, c) FAIL_MSG[0]=a;FAIL_MSG[1]=b;FAIL_MSG[2]=c;while(1)
+#define SSDVT_PASS() while(1)
+#define SSDVT_LOG(a, b, c)
+#endif
+
+
+#define OLPDET_TEST_REGION_A (0)
+#define OLPDET_TEST_REGION_B (1)
+#define OLPDET_TEST_REGION_C (2)
+#define OLPDET_TEST_REGION_TOTAL (3)
+
+#define OLPDET_TEST_REGION_A_START_ADDR (0)
+#define OLPDET_TEST_REGION_B_START_ADDR (1024)
+#define OLPDET_TEST_REGION_C_START_ADDR (1920)
+#define OLPDET_TEST_REGION_LENGTH (128)
+
+
+kal_bool TEST_REGION_POINT_ARRAY[OLPDET_TEST_REGION_TOTAL][7] = {
+ {KAL_FALSE, KAL_FALSE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE},
+ {KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE},
+ {KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_TRUE, KAL_FALSE}
+};
+
+#define OLPDET_TEST_POINT_LENGTH (2)
+#define MAILBOX_TEST_PREFIX_PATTERN (0x62970000)
+
+#define MCORE_ID_MCORE0 (0)
+#define MCORE_ID_MCORE1 (1)
+
+#define CSIF_REG_WRITE_DELAY(addr, data) DRV_WriteReg32_Device(addr, data); \
+ DRV_Memory_Barrier_Write();
+
+#define MULTIPLE_REG_TEST_NUM 5
+#define MULTIPLE_REG_TEST_NUM_SUB_1 2
+#define MULTIPLE_REG_TEST_NUM_SUB_2 (MULTIPLE_REG_TEST_NUM - MULTIPLE_REG_TEST_NUM_SUB_1)
+kal_uint32 MULTIPLE_REG_TEST_OFFSET[MULTIPLE_REG_TEST_NUM] = {0, 0x800, 0x1000, 0x2000, 0x3FE0};
+kal_uint32 MULTIPLE_REG_TEST_SIZE[MULTIPLE_REG_TEST_NUM] = {0x400, 0x100, 0x8, 0x200, 0x20};
+
+#define MULTIPLE_MAIL_TEST_NUM 8
+#define MULTIPLE_IRQ_TEST_NUM 16
diff --git a/mcu/driver/devdrv/csif/mt6297p/inc/drv_csif.h b/mcu/driver/devdrv/csif/mt6297p/inc/drv_csif.h
new file mode 100644
index 0000000..3fd9a19
--- /dev/null
+++ b/mcu/driver/devdrv/csif/mt6297p/inc/drv_csif.h
@@ -0,0 +1,491 @@
+#ifndef __DRV_CSIF_H__
+#define __DRV_CSIF_H__
+
+#include "csif_l1core_public_api.h"
+
+#include "intrCtrl.h"
+#include "kal_public_api.h"
+#include "kal_general_types.h"
+
+#include "sync_data.h"
+#include "drv_comm.h"
+#include "reg_base.h"
+
+#define __CSIF_DEBUG__
+
+/*******************************************************************************
+ * CSIF CR Definition
+ *******************************************************************************/
+
+// temp define for compiling test
+
+#define CSIF_BANK_A_BASE (BASE_MADDR_MCORE_MSYS_DSPCSIF)
+#define CSIF_BANK_B_BASE (BASE_NADDR_MCORE_MSYS_DSPCSIF)
+
+#define CSIF_DSR_BASE (CSIF_BANK_A_BASE)
+#define CSIF_DSM_BASE (CSIF_BANK_A_BASE + 0x2000)
+#define CSIF_DSR_SIZE (0x400) //1KB
+#define CSIF_DSM_SIZE (16384) //16KB
+
+
+/* Control Register Addr and Offset */
+#define CSIF_S2C_IRQ_CR_BASE (CSIF_DSR_BASE + 0x0)
+#define CSIF_S2C_IRQ_CLR_OFFSET (0x0)
+#define CSIF_S2C_IRQ_STATUS_OFFSET (0x4)
+#define CSIF_S2C_IRQ_MASKED_STATUS_OFFSET (0x8)
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_S2C_IRQ_ENABLE_SET_OFFSET (0xC)
+#define CSIF_S2C_IRQ_ENABLE_CLR_OFFSET (0x10)
+#define CSIF_S2C_IRQ_ENABLE_OFFSET (0x14)
+#elif defined(MT6297)
+#define CSIF_S2C_IRQ_ENABLE_OFFSET (0xC)
+#else
+ #error "unsupport project, may need porting"
+#endif
+
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_CORE_IDLE (CSIF_DSR_BASE + 0xC0)
+#define CSIF_S2C_IDLE_IRQ_CR_BASE (CSIF_DSR_BASE + 0xC4)
+#elif defined(MT6297)
+#define CSIF_CORE_IDLE (CSIF_DSR_BASE + 0x60)
+#define CSIF_S2C_IDLE_IRQ_CR_BASE (CSIF_DSR_BASE + 0x64)
+#else
+ #error "unsupport project, may need porting"
+#endif
+#define CSIF_S2C_IDLE_IRQ_ENABLE_OFFSET (0x0)
+#define CSIF_S2C_IDLE_IRQ_ENABLE_SET_OFFSET (0x4)
+#define CSIF_S2C_IDLE_IRQ_ENABLE_CLR_OFFSET (0x8)
+
+#define CSIF_S2C_IDLE_ENABLE_MCORE0_BIT (0U)
+#define CSIF_S2C_IDLE_ENABLE_MCORE1_BIT (4U)
+#define CSIF_S2C_IDLE_ENABLE_MCORE0_AND_OR_BIT (8U)
+#define CSIF_S2C_IDLE_ENABLE_MCORE1_AND_OR_BIT (9U)
+
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_C2S_IRQ_CR_BASE (CSIF_DSR_BASE + 0xE0)
+#elif defined(MT6297)
+#define CSIF_C2S_IRQ_CR_BASE (CSIF_DSR_BASE + 0x80)
+#else
+ #error "unsupport project, may need porting"
+#endif
+#define CSIF_C2S_IRQ_SET_OFFSET (0x0)
+#define CSIF_C2S_IRQ_STATUS_OFFSET (0x4)
+#define CSIF_C2S_IRQ_MASKED_STATUS_OFFSET (0x8)
+
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_MPU_CR_BASE (CSIF_DSR_BASE + 0x160)
+#elif defined(MT6297)
+#define CSIF_MPU_CR_BASE (CSIF_DSR_BASE + 0xC0)
+#else
+ #error "unsupport project, may need porting"
+#endif
+#define CSIF_MPU_START_ADDR_OFFSET (0x0)
+#define CSIF_MPU_RANGE_OFFSET (0x4)
+
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_MPU_ERR_CR_BASE (CSIF_DSR_BASE + 0x180)
+#elif defined(MT6297)
+#define CSIF_MPU_ERR_CR_BASE (CSIF_DSR_BASE + 0xE0)
+#else
+ #error "unsupport project, may need porting"
+#endif
+#define CSIF_MPU_ERR_ADDR_OFFSET (0x0)
+#define CSIF_MPU_ERR_CLR_OFFSET (0x4)
+
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_MPU_CFG_ERR_CLR_DSP_CR_BASE (CSIF_DSR_BASE + 0x190)
+#define CSIF_MPU_CFG_ERR_CLR_L1_CR_BASE (CSIF_DSR_BASE + 0x198)
+#elif defined(MT6297)
+#define CSIF_MPU_CFG_ERR_CLR_DSP_CR_BASE (CSIF_DSR_BASE + 0xF0)
+#define CSIF_MPU_CFG_ERR_CLR_L1_CR_BASE (CSIF_DSR_BASE + 0xF8)
+#else
+ #error "unsupport project, may need porting"
+#endif
+#define CSIF_MPU_CFG_ERR_CLR_OFFSET (0x0)
+
+#define CSIF_MPU_CHANNEL_NUM_DSP (2)
+#define CSIF_MPU_CHANNEL_NUM_L1 (2)
+
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_DSM_WRITE_UNDEFINED_ERR_STATUS_CR (CSIF_DSR_BASE + 0x1A0)
+#define CSIF_DSM_WRITE_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x1A4)
+#define CSIF_DSM_READ_UNDEFINED_ERR_STATUS_CR (CSIF_DSR_BASE + 0x1A8)
+#define CSIF_DSM_READ_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x1AC)
+#define CSIF_DSR_WRITE_UNDEFINED_ERR_ADDR_CR (CSIF_DSR_BASE + 0x1B0)
+#define CSIF_DSR_WRITE_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x1B4)
+#define CSIF_DSR_READ_UNDEFINED_ERR_ADDR_CR (CSIF_DSR_BASE + 0x1B8)
+#define CSIF_DSR_READ_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x1BC)
+
+#define CSIF_L1_ERROR_FLAG_CR (CSIF_DSR_BASE + 0x1C0)
+#define CSIF_L1_ERROR_SNAPSHOT_CR (CSIF_DSR_BASE + 0x1C4)
+#define CSIF_L1_ERROR_ENABLE_CR (CSIF_DSR_BASE + 0x1CC)
+#elif defined(MT6297)
+#define CSIF_DSM_WRITE_UNDEFINED_ERR_STATUS_CR (CSIF_DSR_BASE + 0x100)
+#define CSIF_DSM_WRITE_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x104)
+#define CSIF_DSM_READ_UNDEFINED_ERR_STATUS_CR (CSIF_DSR_BASE + 0x108)
+#define CSIF_DSM_READ_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x10C)
+#define CSIF_DSR_WRITE_UNDEFINED_ERR_ADDR_CR (CSIF_DSR_BASE + 0x110)
+#define CSIF_DSR_WRITE_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x114)
+#define CSIF_DSR_READ_UNDEFINED_ERR_ADDR_CR (CSIF_DSR_BASE + 0x118)
+#define CSIF_DSR_READ_UNDEFINED_ERR_CLR_CR (CSIF_DSR_BASE + 0x11C)
+
+#define CSIF_L1_ERROR_FLAG_CR (CSIF_DSR_BASE + 0x140)
+#define CSIF_L1_ERROR_SNAPSHOT_CR (CSIF_DSR_BASE + 0x144)
+#define CSIF_L1_ERROR_ENABLE_CR (CSIF_DSR_BASE + 0x160)
+#else
+ #error "unsupport project, may need porting"
+#endif
+
+#define CSIF_L1_ERROR_MASK (0x7FFFC00) // disable s2c/c2s irq ovfl error to use SW to control
+
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_L1_MPU_CFG_ENABLE_CR (CSIF_DSR_BASE + 0x1D0)
+#define CSIF_L1_OVFL_CLR_CFG_ENABLE_CR (CSIF_DSR_BASE + 0x1D4)
+#elif defined(MT6297)
+#define CSIF_L1_MPU_CFG_ENABLE_CR (CSIF_DSR_BASE + 0x164)
+#define CSIF_L1_OVFL_CLR_CFG_ENABLE_CR (CSIF_DSR_BASE + 0x168)
+#else
+ #error "unsupport project, may need porting"
+#endif
+
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_S2C_IRQ_OVFL_CR_BASE (CSIF_DSR_BASE + 0x210)
+#elif defined(MT6297)
+#define CSIF_S2C_IRQ_OVFL_CR_BASE (CSIF_DSR_BASE + 0x180)
+#else
+ #error "unsupport project, may need porting"
+#endif
+#define CSIF_S2C_IRQ_OVFL_STATUS_OFFSET (0x0)
+#define CSIF_S2C_IRQ_OVFL_CLR_OFFSET (0x4)
+
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_C2S_IRQ_OVFL_CR_BASE (CSIF_DSR_BASE + 0x240)
+#elif defined(MT6297)
+#define CSIF_C2S_IRQ_OVFL_CR_BASE (CSIF_DSR_BASE + 0x1C0)
+#else
+ #error "unsupport project, may need porting"
+#endif
+#define CSIF_C2S_IRQ_OVFL_STATUS_OFFSET (0x0)
+#define CSIF_C2S_IRQ_OVFL_CLR_OFFSET (0x4)
+
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_MAILBOX_CR_BASE (CSIF_DSR_BASE + 0x260)
+#define CSIF_MAILBOX_SEND_OFFSET (0x0)
+#define CSIF_MAILBOX_RECV_OFFSET (0x4)
+#define CSIF_MAILBOX_STATUS_OFFSET (0x8)
+#define CSIF_MAILBOX_MAX_FIFO_USAGE_OFFSET (0xC)
+#define CSIF_MAILBOX_ERROR_SUB_ENABLE_OFFSET (0x10)
+#define CSIF_MAILBOX_ERROR_STATUS_OFFSET (0x14)
+#define CSIF_MAILBOX_ERROR_RECORD_OFFSET (0x18)
+#define CSIF_MAILBOX_CLR_ERROR_OFFSET (0x1C)
+#define CSIF_MAILBOX_DEBUG_ENABLE_OFFSET (0x20)
+#define CSIF_MAILBOX_DEBUG_READ_CONTENT_OFFSET (0x24)
+#define CSIF_MAILBOX_DEBUG_READ_IDX_OFFSET (0x28)
+#elif defined(MT6297)
+#define CSIF_MAILBOX_CR_BASE (CSIF_DSR_BASE + 0x200)
+#define CSIF_MAILBOX_SEND_OFFSET (0x0)
+#define CSIF_MAILBOX_RECV_OFFSET (0x4)
+#define CSIF_MAILBOX_STATUS_OFFSET (0x8)
+#define CSIF_MAILBOX_MAX_FIFO_USAGE_OFFSET (0xC)
+#define CSIF_MAILBOX_ERROR_STATUS_OFFSET (0x10)
+#define CSIF_MAILBOX_ERROR_RECORD_OFFSET (0x14)
+#define CSIF_MAILBOX_CLR_ERROR_OFFSET (0x18)
+#define CSIF_MAILBOX_DEBUG_ENABLE_OFFSET (0x1C)
+#define CSIF_MAILBOX_DEBUG_READ_CONTENT_OFFSET (0x20)
+#define CSIF_MAILBOX_DEBUG_READ_IDX_OFFSET (0x24)
+#else
+ #error "unsupport project, may need porting"
+#endif
+
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_OLPDET_CR_BASE (CSIF_DSR_BASE + 0x380)
+#define CSIF_OLPDET_SET_OFFSET (0x0)
+#define CSIF_OLPDET_CLR_OFFSET (0x4)
+#define CSIF_OLPDET_INUSE_MAIL_SIZE_OFFSET (0x8)
+#define CSIF_OLPDET_MAX_MAIL_SIZE_OFFSET (0xC)
+#define CSIF_OLPDET_MAX_MAIL_SIZE_CLR_OFFSET (0x10)
+#define CSIF_OLPDET_ERROR_SUB_ENABLE_OFFSET (0x14)
+#define CSIF_OLPDET_ERROR_STATUS_OFFSET (0x18)
+#define CSIF_OLPDET_SET_CANDIDATE_RECORD_OFFSET (0x1C)
+#define CSIF_OLPDET_CLR_CANDIDATE_RECORD_OFFSET (0x20)
+#define CSIF_OLPDET_CLR_ERROR_OFFSET (0x24)
+#define CSIF_OLPDET_DEBUG_READ_MUM_OFFSET (0x28)
+#define CSIF_OLPDET_DEBUG_READ_MUM_IDX_OFFSET (0x2C)
+#define CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE_OFFSET (0x30)
+#elif defined(MT6297)
+#define CSIF_OLPDET_CR_BASE (CSIF_DSR_BASE + 0x380)
+#define CSIF_OLPDET_SET_OFFSET (0x0)
+#define CSIF_OLPDET_CLR_OFFSET (0x4)
+#define CSIF_OLPDET_INUSE_MAIL_SIZE_OFFSET (0x8)
+#define CSIF_OLPDET_ERROR_STATUS_OFFSET (0xC)
+#define CSIF_OLPDET_SET_CANDIDATE_RECORD_OFFSET (0x10)
+#define CSIF_OLPDET_CLR_CANDIDATE_RECORD_OFFSET (0x14)
+#define CSIF_OLPDET_CLR_ERROR_OFFSET (0x18)
+#define CSIF_OLPDET_DEBUG_READ_MUM_OFFSET (0x1C)
+#define CSIF_OLPDET_DEBUG_READ_MUM_IDX_OFFSET (0x20)
+#define CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE_OFFSET (0x24)
+#else
+ #error "unsupport project, may need porting"
+#endif
+
+// ************************
+// For using CR
+// ************************
+#define CSIF_S2C_IRQ_CLR (CSIF_S2C_IRQ_CR_BASE + CSIF_S2C_IRQ_CLR_OFFSET)
+#define CSIF_S2C_IRQ_STATUS (CSIF_S2C_IRQ_CR_BASE + CSIF_S2C_IRQ_STATUS_OFFSET)
+#define CSIF_S2C_IRQ_MASKED_STATUS (CSIF_S2C_IRQ_CR_BASE + CSIF_S2C_IRQ_MASKED_STATUS_OFFSET)
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_S2C_IRQ_ENABLE_SET (CSIF_S2C_IRQ_CR_BASE + CSIF_S2C_IRQ_ENABLE_SET_OFFSET)
+#define CSIF_S2C_IRQ_ENABLE_CLR (CSIF_S2C_IRQ_CR_BASE + CSIF_S2C_IRQ_ENABLE_CLR_OFFSET)
+#endif
+#define CSIF_S2C_IRQ_ENABLE (CSIF_S2C_IRQ_CR_BASE + CSIF_S2C_IRQ_ENABLE_OFFSET)
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_S2C_IRQ_SIZE (0x20)
+#elif defined(MT6297)
+#define CSIF_S2C_IRQ_SIZE (CSIF_S2C_IRQ_ENABLE_OFFSET - CSIF_S2C_IRQ_CLR_OFFSET + 4)
+#else
+ #error "unsupport project, may need porting"
+#endif
+
+#define CSIF_S2C_IDLE_IRQ_ENABLE (CSIF_S2C_IDLE_IRQ_CR_BASE + CSIF_S2C_IDLE_IRQ_ENABLE_OFFSET)
+#define CSIF_S2C_IDLE_IRQ_ENABLE_SET (CSIF_S2C_IDLE_IRQ_CR_BASE + CSIF_S2C_IDLE_IRQ_ENABLE_SET_OFFSET)
+#define CSIF_S2C_IDLE_IRQ_ENABLE_CLR (CSIF_S2C_IDLE_IRQ_CR_BASE + CSIF_S2C_IDLE_IRQ_ENABLE_CLR_OFFSET)
+#define CSIF_S2C_IDLE_IRQ_ENABLE_SIZE (CSIF_S2C_IDLE_IRQ_ENABLE_CLR_OFFSET - CSIF_S2C_IDLE_IRQ_ENABLE_OFFSET + 4)
+
+#define CSIF_S2C_IDLE_IRQ_NUM (2)
+
+#define CSIF_C2S_IRQ_SET (CSIF_C2S_IRQ_CR_BASE + CSIF_C2S_IRQ_SET_OFFSET)
+#define CSIF_C2S_IRQ_STATUS (CSIF_C2S_IRQ_CR_BASE + CSIF_C2S_IRQ_STATUS_OFFSET)
+#define CSIF_C2S_IRQ_MASKED_STATUS (CSIF_C2S_IRQ_CR_BASE + CSIF_C2S_IRQ_MASKED_STATUS_OFFSET)
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_C2S_IRQ_SIZE (0x20)
+#elif defined(MT6297)
+#define CSIF_C2S_IRQ_SIZE (CSIF_C2S_IRQ_MASKED_STATUS_OFFSET - CSIF_C2S_IRQ_SET_OFFSET + 4)
+#else
+ #error "unsupport project, may need porting"
+#endif
+
+#define CSIF_MPU_START_ADDR (CSIF_MPU_CR_BASE + CSIF_MPU_START_ADDR_OFFSET)
+#define CSIF_MPU_RANGE (CSIF_MPU_CR_BASE + CSIF_MPU_RANGE_OFFSET)
+#define CSIF_MPU_SIZE (CSIF_MPU_RANGE_OFFSET - CSIF_MPU_START_ADDR_OFFSET + 4)
+
+#define CSIF_MPU_TYPE_M (0x10000)
+#define CSIF_MPU_TYPE_P (16U)
+
+#define CSIF_MPU_START_M (0xFFFF)
+#define CSIF_MPU_START_P (0U)
+
+#define CSIF_MPU_RANGE_M (0xFFFF)
+#define CSIF_MPU_RANGE_P (0U)
+
+#define CSIF_MPU_ERR_ADDR (CSIF_MPU_ERR_CR_BASE + CSIF_MPU_ERR_ADDR_OFFSET)
+#define CSIF_MPU_ERR_CLR (CSIF_MPU_ERR_CR_BASE + CSIF_MPU_ERR_CLR_OFFSET)
+#define CSIF_MPU_ERR_SIZE (CSIF_MPU_ERR_CLR_OFFSET - CSIF_MPU_ERR_ADDR_OFFSET + 4)
+
+#define CSIF_MPU_CFG_ERR_CLR_DSP (CSIF_MPU_CFG_ERR_CLR_DSP_CR_BASE + CSIF_MPU_CFG_ERR_CLR_OFFSET)
+#define CSIF_MPU_CFG_ERR_CLR_L1 (CSIF_MPU_CFG_ERR_CLR_L1_CR_BASE + CSIF_MPU_CFG_ERR_CLR_OFFSET)
+#define CSIF_MPU_CFG_ERR_CLR_SIZE (CSIF_MPU_CFG_ERR_CLR_OFFSET - CSIF_MPU_CFG_ERR_CLR_OFFSET + 4)
+
+#define CSIF_S2C_IRQ_OVFL_STATUS (CSIF_S2C_IRQ_OVFL_CR_BASE + CSIF_S2C_IRQ_OVFL_STATUS_OFFSET)
+#define CSIF_S2C_IRQ_OVFL_CLR (CSIF_S2C_IRQ_OVFL_CR_BASE + CSIF_S2C_IRQ_OVFL_CLR_OFFSET)
+#define CSIF_S2C_IRQ_OVFL_SIZE (CSIF_S2C_IRQ_OVFL_CLR_OFFSET - CSIF_S2C_IRQ_OVFL_STATUS_OFFSET + 4)
+
+#define CSIF_C2S_IRQ_OVFL_STATUS (CSIF_C2S_IRQ_OVFL_CR_BASE + CSIF_C2S_IRQ_OVFL_STATUS_OFFSET)
+#define CSIF_C2S_IRQ_OVFL_CLR (CSIF_C2S_IRQ_OVFL_CR_BASE + CSIF_C2S_IRQ_OVFL_CLR_OFFSET)
+#define CSIF_C2S_IRQ_OVFL_SIZE (CSIF_C2S_IRQ_OVFL_CLR_OFFSET - CSIF_C2S_IRQ_OVFL_STATUS_OFFSET + 4)
+
+#define CSIF_MAILBOX_SEND (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_SEND_OFFSET)
+#define CSIF_MAILBOX_RECV (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_RECV_OFFSET)
+#define CSIF_MAILBOX_STATUS (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_STATUS_OFFSET)
+#define CSIF_MAILBOX_MAX_FIFO_USAGE (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_MAX_FIFO_USAGE_OFFSET)
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_MAILBOX_ERROR_SUB_ENABLE (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_ERROR_SUB_ENABLE_OFFSET)
+#endif
+#define CSIF_MAILBOX_ERROR_STATUS (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_ERROR_STATUS_OFFSET)
+#define CSIF_MAILBOX_ERROR_RECORD (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_ERROR_RECORD_OFFSET)
+#define CSIF_MAILBOX_CLR_ERROR (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_CLR_ERROR_OFFSET)
+#define CSIF_MAILBOX_DEBUG_ENABLE (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_DEBUG_ENABLE_OFFSET)
+#define CSIF_MAILBOX_DEBUG_READ_CONTENT (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_DEBUG_READ_CONTENT_OFFSET)
+#define CSIF_MAILBOX_DEBUG_READ_IDX (CSIF_MAILBOX_CR_BASE + CSIF_MAILBOX_DEBUG_READ_IDX_OFFSET)
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_MAILBOX_SIZE (0x30)
+#elif defined(MT6297)
+#define CSIF_MAILBOX_SIZE (0x40)
+#else
+ #error "unsupport project, may need porting"
+#endif
+
+#define CSIF_MAILBOX_256_STATUS_R_IDX_M (0x1FF)
+#define CSIF_MAILBOX_256_STATUS_R_IDX_P (0U)
+#define CSIF_MAILBOX_256_STATUS_W_IDX_M (0x3FE00)
+#define CSIF_MAILBOX_256_STATUS_W_IDX_P (9U)
+#define CSIF_MAILBOX_256_STATUS_MAIL_NUM_M (0x7FC0000)
+#define CSIF_MAILBOX_256_STATUS_MAIL_NUM_P (18U)
+
+#define CSIF_MAILBOX_64_STATUS_R_IDX_M (0xFF)
+#define CSIF_MAILBOX_64_STATUS_R_IDX_P (0U)
+#define CSIF_MAILBOX_64_STATUS_W_IDX_M (0xFF00)
+#define CSIF_MAILBOX_64_STATUS_W_IDX_P (8U)
+#define CSIF_MAILBOX_64_STATUS_MAIL_NUM_M (0xFF0000)
+#define CSIF_MAILBOX_64_STATUS_MAIL_NUM_P (16U)
+
+#define MAILBOX_256_WRAP_MASK (0xFF)
+#define MAILBOX_64_WRAP_MASK (0x3F)
+
+#define CSIF_OLPDET_SET (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_SET_OFFSET )
+#define CSIF_OLPDET_CLR (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_CLR_OFFSET )
+#define CSIF_OLPDET_INUSE_MAIL_SIZE (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_INUSE_MAIL_SIZE_OFFSET )
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_OLPDET_MAX_MAIL_SIZE (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_MAX_MAIL_SIZE_OFFSET )
+#define CSIF_OLPDET_MAX_MAIL_SIZE_CLR (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_MAX_MAIL_SIZE_CLR_OFFSET )
+#define CSIF_OLPDET_ERROR_SUB_ENABLE (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_ERROR_SUB_ENABLE_OFFSET )
+#endif
+#define CSIF_OLPDET_ERROR_STATUS (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_ERROR_STATUS_OFFSET )
+#define CSIF_OLPDET_SET_CANDIDATE_RECORD (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_SET_CANDIDATE_RECORD_OFFSET)
+#define CSIF_OLPDET_CLR_CANDIDATE_RECORD (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_CLR_CANDIDATE_RECORD_OFFSET)
+#define CSIF_OLPDET_CLR_ERROR (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_CLR_ERROR_OFFSET )
+#define CSIF_OLPDET_DEBUG_READ_MUM (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_DEBUG_READ_MUM_OFFSET )
+#define CSIF_OLPDET_DEBUG_READ_MUM_IDX (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_DEBUG_READ_MUM_IDX_OFFSET )
+#define CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE (CSIF_OLPDET_CR_BASE + CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE_OFFSET)
+#define CSIF_OLPDET_SIZE (CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE_OFFSET - CSIF_OLPDET_SET_OFFSET + 4)
+
+#define CSIF_OLPDET_SET_OFFSET_M (0x7FF)
+#define CSIF_OLPDET_SET_OFFSET_P (0U)
+#define CSIF_OLPDET_SET_LENGTH_M (0xFF0000)
+#define CSIF_OLPDET_SET_LENGTH_P (16U)
+
+#define CSIF_OLPDET_CLR_OFFSET_M (0x7FF)
+#define CSIF_OLPDET_CLR_OFFSET_P (0U)
+#define CSIF_OLPDET_CLR_LENGTH_M (0xFF0000)
+#define CSIF_OLPDET_CLR_LENGTH_P (16U)
+
+#define CSIF_OLPDET_SET_CONTENT_ERROR_M (0x1)
+#define CSIF_OLPDET_SET_CONTENT_ERROR_P (0)
+#define CSIF_OLPDET_CLR_CONTENT_ERROR_M (0x2)
+#define CSIF_OLPDET_CLR_CONTENT_ERROR_P (1)
+#define CSIF_OLPDET_OLP_HIT_ERROR_M (0x4)
+#define CSIF_OLPDET_OLP_HIT_ERROR_P (2)
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#define CSIF_OLPDET_CLR_NOHIT_ERROR_M (0x8)
+#define CSIF_OLPDET_CLR_NOHIT_ERROR_P (3)
+#endif
+
+/*******************************************************************************
+ * Macros
+ *******************************************************************************/
+
+/* C2S */
+#define CSIF_C2S_IRQ_CR_BASE_PTR ((volatile csif_uint32*)(CSIF_C2S_IRQ_CR_BASE))
+#define CSIF_C2S_IRQ_CLR_PTR ((volatile csif_uint32*)(CSIF_C2S_IRQ_CLR))
+#define CSIF_C2S_IRQ_STATUS_PTR ((volatile csif_uint32*)(CSIF_C2S_IRQ_STATUS))
+#define CSIF_C2S_IRQ_MASKED_STATUS_PTR ((volatile csif_uint32*)(CSIF_C2S_IRQ_MASKED_STATUS))
+#define CSIF_C2S_IRQ_ENABLE_PTR ((volatile csif_uint32*)(CSIF_C2S_IRQ_ENABLE))
+
+
+#define CSIF_TRUE KAL_TRUE
+#define CSIF_FALSE KAL_FALSE
+
+/* Read/Write macros */
+#define BANK_MASK 0x0FFFFFFF
+#define BANK_B_PREFIX 0xB0000000
+#define CSIF_REG_READ(addr, data) data=(*(volatile kal_uint32 *)(addr))
+#define CSIF_REG_WRITE(addr, data) do{DRV_WriteReg32(addr, data); MO_Sync();}while(0);
+#define CSIF_REG_WRITE_BANKB(addr, data) DRV_WriteReg32(((addr & BANK_MASK) | BANK_B_PREFIX), data);
+#define CSIF_NULL NULL
+#if defined(__CSIF_DRV_TEST__)
+ #include <stdio.h>
+ #define CSIF_ASSERT(expr, e1, e2, e3) if((expr) == 0){ASSERT_MSG[0]=e1;ASSERT_MSG[1]=e2;ASSERT_MSG[2]=e3;}
+#else
+ #define CSIF_ASSERT(expr, e1, e2, e3) EXT_ASSERT(expr, e1, e2, e3)
+#endif
+/* TODO */
+// change read LR by CR_LR to SR_LR
+#define CSIF_GET_RETURN_ADDRESS(data) GET_RETURN_ADDRESS(data)
+#define CSIF_HANDLER(nID) \
+csif_InterruptHandlerInternal( \
+ (volatile csif_uint32*)(CSIF_S2C_IRQ_CLR + CSIF_S2C_IRQ_SIZE*nID), \
+ (volatile csif_uint32*)(CSIF_S2C_IRQ_STATUS + CSIF_S2C_IRQ_SIZE*nID), \
+ (volatile csif_uint32*)(CSIF_S2C_IRQ_MASKED_STATUS + CSIF_S2C_IRQ_SIZE*nID), \
+ (volatile csif_uint32*)(CSIF_S2C_IRQ_ENABLE + CSIF_S2C_IRQ_SIZE*nID), \
+ nID, \
+ csif_s2c_isr_handler[nID])
+
+#define CSIF_MAILBOX_EMPTY_VALUE (0xFFFFFFFF)
+#define CSIF_MAILBOX_ERROR_VALUE (0xEFFFFFFF)
+
+#define CSIF_OLPDET_UNIT (8) // 1 bit in OLPDET is 8 Bytes(2 words)
+#define CSIF_OLPDET_UNIT_MASK (0x7) // 1 bit in OLPDET is 8 Bytes(2 words)
+
+#define CSIF_DSM_MASK (0x00003FFF) //16KB
+/*******************************************************************************
+ * Debug feature
+ *******************************************************************************/
+#if defined(__CSIF_DEBUG__)
+
+#define CSIF_DEBUG_API_RECORD_SIZE 64
+#define CSIF_DEBUG_MULTI_API_RECORD_SIZE 32
+#define CSIF_DEBUG_ISR_HANDLE_CODE_SIZE 16
+
+#define SHAOLIN_CORE_NUM 4
+#define SHAOLIN_VPE_NUM 3
+
+#define MCORE_TH_NUM 4
+#define MCORE_CORE_NUM 2
+
+#if defined(MT6297) // for Apollo OLPDET workaround
+#define D2D_DEBUG_RECORD_PREFIX (0xD0000000)
+#endif
+
+typedef struct{
+ csif_uint32 time;
+ csif_uint32 code;
+}CSIF_DebugISRRecord;
+
+/** The Ring Buffer */
+typedef struct{
+ CSIF_DebugISRRecord records[CSIF_DEBUG_ISR_HANDLE_CODE_SIZE];
+ csif_uint32 top_index;
+}CSIF_DebugISRCodeList;
+
+typedef struct{
+ csif_uint32 time;
+ csif_uint32 status;
+ csif_uint32 set_addr; /**< The control register address */
+ csif_uint32 set_value; /**< The writing value for the control regsiters */
+ csif_uint32 caller; /**< The caller address */
+}CSIF_DebugRecord;
+
+typedef struct{
+ csif_uint32 time;
+ csif_uint32 set_addr; /**< The control register address */
+ csif_uint32 set_value; /**< The writing value for the control regsiters */
+ csif_uint32 caller; /**< The caller address */
+ csif_uint32 multiIdx; /**< the index that multiple API called */
+}CSIF_MultiOperation_DebugRecord;
+
+/** The Ring Buffer */
+typedef struct{
+ CSIF_DebugRecord records[CSIF_DEBUG_API_RECORD_SIZE];
+ kal_atomic_uint32 top_index;
+}CSIF_DebugRecordList;
+
+typedef struct{
+ CSIF_MultiOperation_DebugRecord records[CSIF_DEBUG_MULTI_API_RECORD_SIZE];
+ kal_atomic_uint32 top_index;
+}CSIF_MultiOperationDebugRecordList;
+
+void csif_DebugAddRecord(csif_uint32 status,
+ volatile csif_uint32* set_addr,
+ csif_uint32 set_value,
+ csif_uint32 caller);
+
+void csif_MultiDebugAddRecord(csif_uint32 multiIdx,
+ volatile csif_uint32* set_addr,
+ csif_uint32 set_value,
+ csif_uint32 caller);
+
+void csif_DebugAddISRHandlerCode(CSIF_S2C_INDEX nID, csif_uint32 code);
+
+#endif /* __CSIF_DEBUG__ */
+
+#endif /* __DRV_CSIF_H__ */
diff --git a/mcu/driver/devdrv/csif/mt6297p/src/csif_dvt_main.c b/mcu/driver/devdrv/csif/mt6297p/src/csif_dvt_main.c
new file mode 100644
index 0000000..64d89af
--- /dev/null
+++ b/mcu/driver/devdrv/csif/mt6297p/src/csif_dvt_main.c
@@ -0,0 +1,2833 @@
+#include "drv_csif.h"
+#include "kal_hrt_api.h"
+#include "csif_l1core_public_api.h"
+#include "csif_SSDVT.h"
+
+volatile csif_uint32 test_case_index = 0;
+volatile csif_uint32 IRQ_HANDLER_TYPE = 0;
+volatile csif_uint32 _mcore_testing_thread = 0;
+csif_uint32 THIS_MCORE_ID = 0;
+
+volatile csif_uint32 _mcuInternalSyncPattern = 0;
+
+volatile csif_uint32 FAIL_MSG[3];
+#if defined(__CSIF_DRV_TEST__)
+volatile csif_uint32 _errCount = 0;
+volatile CSIF_ID_STATUS_t errStatusStruct[26];
+#endif
+
+/*******************************************************************************
+ * Macros
+ *******************************************************************************/
+/* e.g. GET_S2C_IRQ_LIMIT_NUMBER(0) => CSIF_S2C_N0_TOTAL_NUMBER */
+#define POSTFIX(nID, pos) nID##pos
+#define PREFIX(nID, pre) POSTFIX(pre##nID, _TOTAL_NUMBER)
+#define GET_S2C_IRQ_LIMIT_NUMBER(nID) PREFIX(nID, CSIF_S2C_N)
+
+#define GET_C2S_IRQ_LIMIT_NUMBER(nID) PREFIX(nID, CSIF_C2S_N)
+
+/*******************************************************************************
+ * Variable Declaration
+ *******************************************************************************/
+// thread shared variable
+volatile kal_uint32 _csif_exception_sync = 0;
+volatile kal_uint32 _csif_exception_sync_th[4] = {0};
+volatile kal_uint32 _csif_c2s_irq_test_flag[CSIF_ENUM_ALL_C2S_INT_NUM] = {0};
+
+
+
+static const kal_uint32 CSIF_S2C_Interrupt_Num[CSIF_ENUM_ALL_S2C_INT_NUM] = {
+ GET_S2C_IRQ_LIMIT_NUMBER(0),
+ GET_S2C_IRQ_LIMIT_NUMBER(1),
+ GET_S2C_IRQ_LIMIT_NUMBER(2),
+ GET_S2C_IRQ_LIMIT_NUMBER(3),
+ GET_S2C_IRQ_LIMIT_NUMBER(4),
+ GET_S2C_IRQ_LIMIT_NUMBER(5)
+};
+static const kal_uint32 CSIF_C2S_Interrupt_Num[CSIF_ENUM_ALL_C2S_INT_NUM] = {
+ GET_C2S_IRQ_LIMIT_NUMBER(0),
+ GET_C2S_IRQ_LIMIT_NUMBER(1),
+ GET_C2S_IRQ_LIMIT_NUMBER(2),
+ GET_C2S_IRQ_LIMIT_NUMBER(3)
+};
+
+extern csif_uint32 csif_mailbox_entry_num_table[CSIF_MAILBOX_TOTAL_NUM];
+
+
+// OLPDET TEST
+volatile kal_uint32 set_api_value = 0;
+volatile kal_uint32 clr_api_value = 0;
+
+#if defined(MT6885) || defined(MT6873)
+volatile kal_uint32 expect_max_mail_size;
+#endif
+volatile kal_uint32 expect_inuse_mail_size;
+volatile kal_uint32 expect_error_status;
+volatile kal_uint32 expect_set_candidate_record;
+volatile kal_uint32 expect_clr_candidate_record;
+
+volatile kal_uint32 set_candidate_record;
+volatile kal_uint32 clr_candidate_record;
+
+volatile kal_uint32 log_pattern = 0;;
+
+kal_uint32 expect_mum_arr[OLPDET_MUM_BIT_NUM/32] = {0};
+kal_uint32 dump_mum_arr[OLPDET_MUM_BIT_NUM/32] = {0};
+
+volatile kal_uint32 olpdet_record_set_err[32]={0};
+volatile kal_uint32 olpdet_err_count = 0;
+
+volatile kal_bool olpdet_error_polling_flag = KAL_FALSE;
+
+/*******************************************************************************
+ * Functions - Test
+ *******************************************************************************/
+
+volatile csif_uint32 expect_s2c_nID = 0;
+volatile csif_uint32 expect_s2c_bit = 2;
+
+#if defined(__CSIF_DRV_TEST__)
+void CSIF_drv_test_err(CSIF_ID_STATUS_t* status_id){
+ errStatusStruct[_errCount].id = status_id->id;
+ errStatusStruct[_errCount].code = status_id->code;
+ errStatusStruct[_errCount].masked_status = status_id->masked_status;
+ _errCount++;
+ return;
+}
+
+void CSIF_drv_test_olpdet_err(CSIF_ID_STATUS_t* status_id)
+{
+ volatile kal_uint32 read_error_flag;
+ volatile kal_uint32 read_error_snapshot;
+ volatile kal_uint32 inuse_mail_size;
+ volatile kal_uint32 error_status;
+
+#if defined(MT6885) || defined(MT6873)
+ volatile kal_uint32 max_mail_size;
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE, max_mail_size);
+#endif
+
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE, inuse_mail_size);
+ CSIF_REG_READ(CSIF_OLPDET_ERROR_STATUS, error_status);
+ CSIF_REG_READ(CSIF_L1_ERROR_FLAG_CR, read_error_flag);
+ CSIF_REG_READ(CSIF_L1_ERROR_SNAPSHOT_CR, read_error_snapshot);
+
+ CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, set_candidate_record);
+ CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, clr_candidate_record);
+
+ olpdet_record_set_err[olpdet_err_count%8] = set_candidate_record;
+ olpdet_err_count++;
+
+ if(expect_error_status != 0){
+#if defined(MT6885) || defined(MT6873)
+ if(max_mail_size != expect_max_mail_size )
+ {
+ SSDVT_FAIL_MSG(max_mail_size, (log_pattern | 0xA40000)| (expect_max_mail_size & 0xFFFF) , test_case_index);
+ }
+#endif
+ if(inuse_mail_size != expect_inuse_mail_size )
+ {
+ SSDVT_FAIL_MSG(inuse_mail_size, (log_pattern | 0xA00000)| (expect_inuse_mail_size & 0xFFFF) , test_case_index);
+ }
+
+ if(error_status != expect_error_status)
+ {
+ SSDVT_FAIL_MSG(error_status, (log_pattern | 0xA10000)| (expect_error_status & 0xFFFF), test_case_index);
+ }
+ if(set_candidate_record != expect_set_candidate_record)
+ {
+ SSDVT_FAIL_MSG(set_candidate_record, (log_pattern | 0xA20000)| (expect_set_candidate_record & 0xFFFF), test_case_index);
+ }
+ if(clr_candidate_record != expect_clr_candidate_record)
+ {
+ SSDVT_FAIL_MSG(clr_candidate_record, (log_pattern | 0xA30000)| (expect_clr_candidate_record & 0xFFFF), test_case_index);
+ }
+
+ if((read_error_flag & (0x1 << (OLPDET_ERR_BIT ))) == 0 ){
+ SSDVT_FAIL_MSG(read_error_flag, (log_pattern | 0xAA0000), test_case_index);
+ }
+ if((read_error_snapshot & (0x1 << (OLPDET_ERR_BIT ))) == 0 ){
+ SSDVT_FAIL_MSG(read_error_snapshot, (log_pattern | 0xAB0000), test_case_index);
+ }
+
+ // clear error
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+ CSIF_REG_READ(CSIF_OLPDET_ERROR_STATUS, error_status);
+ if(error_status != 0)
+ {
+ SSDVT_FAIL_MSG(error_status, (log_pattern | 0xC10000)| (expect_error_status & 0xFFFF), test_case_index);
+ }
+ olpdet_error_polling_flag = KAL_TRUE;
+ }
+ else{
+ SSDVT_FAIL_MSG(read_error_snapshot, (log_pattern | 0xEB0000)| (error_status & 0xFFFF) , test_case_index);
+ }
+}
+#endif
+
+#if defined(__CSIF_CROSS_CORE_TEST__)
+void CSIF_CROSSCORE_TEST(CSIF_ID_STATUS_t* status_id){
+ switch(IRQ_HANDLER_TYPE)
+ {
+ case CSIF_IRQ_HANDLER_IRQ_TEST:
+ {
+ test_case_index = test_case_index | (expect_s2c_nID << 8) | (expect_s2c_bit << 0);
+ if(status_id->id == expect_s2c_nID && status_id->code == expect_s2c_bit)
+ {
+ expect_s2c_bit++;
+ if(expect_s2c_bit > 31)
+ {
+ if(expect_s2c_nID == 0){
+ expect_s2c_bit = 2;
+ }else{
+ expect_s2c_bit = 0;
+ }
+ expect_s2c_nID++;
+ }
+ CSIF_REG_WRITE(CSIF_RSVD_1, CSIF_CROSS_IRQ_S2C_PASS);
+ }
+ else{
+ SSDVT_FAIL_MSG(status_id->id, status_id->code, test_case_index);
+ }
+ break;
+ }
+ case CSIF_IRQ_HANDLER_IDLE_IRQ_TEST:
+ {
+ _mcuInternalSyncPattern = EXPECT_IRQ_SET_FLAG_TRUE;
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + 0*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + 1*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+ break;
+ }
+ case CSIF_IRQ_HANDLER_MAILBOX_TEST:
+ {
+ break;
+ }
+ default:
+ {
+ SSDVT_FAIL_MSG(IRQ_HANDLER_TYPE, 0, test_case_index);
+ }
+ }
+ return;
+}
+#endif
+
+void cross_interrupt_test(void)
+{
+ volatile kal_uint32 read_value=0;
+ // **************************
+ // Disable S2C_IRQ_ENABLE
+ // **************************
+ for(kal_uint32 csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+#if defined(MT6885) || defined(MT6873)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + csif_num_index*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, 0x0);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, read_value);
+ if(read_value != 0x0){
+ SSDVT_FAIL_MSG(read_value, csif_num_index, test_case_index);
+ }
+ }
+ // Disable DSP error
+ //CSIF_REG_WRITE(CSIF_DSP_ERROR_ENABLE_CR, 0x0);
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0);
+
+
+ volatile csif_uint32 dspSyncPattern = 0;
+
+ test_case_index = 0x10000000; // CSIF cross core interrupt TEST (s2c part)
+
+ // Sync barrier before test
+ while(1){
+ CSIF_REG_READ(CSIF_RSVD_0, dspSyncPattern);
+ if(dspSyncPattern == CSIF_CROSS_START1_DSP){
+ break;
+ }
+ }
+
+ // clear s2c irq
+ for(int i = CSIF_ENUM_S2C_N0; i< CSIF_ENUM_ALL_S2C_INT_NUM; i++)
+ {
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_CLR + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+ }
+ // enable s2c irq
+ for(int i = CSIF_ENUM_S2C_N0; i< CSIF_ENUM_ALL_S2C_INT_NUM; i++)
+ {
+ if(i == 0 || i == 1){
+#if defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFC);
+#elif defined(MT6885) || defined(MT6873)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_SET + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFC);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ }else{
+#if defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6885) || defined(MT6873)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_SET + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ }
+ }
+
+ // sync barrier befor S2C IRQ test
+ CSIF_REG_WRITE(CSIF_RSVD_0, CSIF_CROSS_START1_MCU);
+
+ //***************
+ //** S2C irq in here
+ //***************
+
+ // Sync barrier before C2S IRQ test
+ while(1){
+ CSIF_REG_READ(CSIF_RSVD_0, dspSyncPattern);
+ if(dspSyncPattern == CSIF_CROSS_START2_DSP){
+ break;
+ }
+ }
+
+ test_case_index = 0x1b000000; // CSIF cross core interrupt TEST (c2s part)
+ // MCU trigger C2S irq to DSP
+ for(int i = CSIF_ENUM_C2S_N0; i < CSIF_ENUM_ALL_C2S_INT_NUM; i++)
+ {
+#if defined(__CSIF_SHAOLIN_64b_WORKAROUND__)
+ if((i & 0x1) != 0){
+ continue;
+ }
+#endif
+ for(int bit_i = 0; bit_i < C2S_IRQ_EN_WIDTH; bit_i++)
+ {
+ test_case_index = test_case_index | (i << 8) | (bit_i << 0);
+
+ CSIF_REG_WRITE(CSIF_C2S_IRQ_SET + i*CSIF_C2S_IRQ_SIZE, (0x1 << bit_i));
+
+ // Sync barrier during MCU set IRQ
+ CSIF_REG_WRITE(CSIF_RSVD_1, CSIF_CROSS_IRQ_C2S_WAIT);
+ while(1){
+ CSIF_REG_READ(CSIF_RSVD_1, dspSyncPattern);
+ if(dspSyncPattern == CSIF_CROSS_IRQ_C2S_PASS){
+ break;
+ }
+ }
+ }
+ }
+
+ // sync barrier after C2S IRQ test
+ CSIF_REG_WRITE(CSIF_RSVD_0, CSIF_CROSS_START2_MCU);
+
+
+ return;
+
+}
+
+// irq_idx = 0/1, enable_mask must be 4-bit mask; type=0/1 (IDLE_IRQ_ENABLE_TYPE_OR/IDLE_IRQ_ENABLE_TYPE_AND);
+// expect_irq_set_flag=EXPECT_IRQ_SET_FLAG_TRUE/FALSE
+void set_idle_irq_mask(csif_uint32 irq_idx, csif_uint32 enable_mask, csif_uint32 type, csif_uint32 expect_irq_set_flag)
+{
+ volatile csif_uint32 set_enable_reg_value;
+ //volatile csif_uint32 read_enable_reg_value;
+ volatile csif_uint32 read_S2C_status_value;
+
+
+ volatile csif_uint32 IRQ_waiting_counter = 0;
+
+
+
+ if(THIS_MCORE_ID == MCORE_ID_MCORE0){
+ set_enable_reg_value = (enable_mask << CSIF_S2C_IDLE_ENABLE_MCORE0_BIT) | (type << CSIF_S2C_IDLE_ENABLE_MCORE0_AND_OR_BIT);
+ }
+ else if(THIS_MCORE_ID == MCORE_ID_MCORE1){
+ set_enable_reg_value = (enable_mask << CSIF_S2C_IDLE_ENABLE_MCORE1_BIT) | (type << CSIF_S2C_IDLE_ENABLE_MCORE1_AND_OR_BIT);
+ }
+ else
+ {
+ //unsupported core
+ SSDVT_FAIL_MSG(THIS_MCORE_ID, 0x9ADDFFFF, test_case_index | (irq_idx << 16));
+ }
+
+ _mcuInternalSyncPattern = EXPECT_IRQ_SET_FLAG_FALSE;
+
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_SET + irq_idx*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, set_enable_reg_value);
+ /*
+ CSIF_REG_READ(CSIF_S2C_IDLE_IRQ_ENABLE + irq_idx*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, read_enable_reg_value);
+ if(read_enable_reg_value != set_enable_reg_value){
+ SSDVT_FAIL_MSG(read_enable_reg_value, (0x9B000000 | set_enable_reg_value), test_case_index | (irq_idx << 16));
+ }
+ */
+
+ while(IRQ_waiting_counter < EXC_TEST_WAITING_CYCLE){
+ IRQ_waiting_counter++;
+ }
+
+ if(expect_irq_set_flag == EXPECT_IRQ_SET_FLAG_TRUE)
+ {
+ if(_mcuInternalSyncPattern != EXPECT_IRQ_SET_FLAG_TRUE){
+ CSIF_REG_READ(CSIF_S2C_IRQ_STATUS + irq_idx*CSIF_S2C_IRQ_SIZE, read_S2C_status_value);
+ SSDVT_FAIL_MSG(read_S2C_status_value, (0x9C000000), test_case_index | (irq_idx << 16));
+ }
+ }
+ else if(expect_irq_set_flag == EXPECT_IRQ_SET_FLAG_FALSE)
+ {
+ if(_mcuInternalSyncPattern != EXPECT_IRQ_SET_FLAG_FALSE){
+ CSIF_REG_READ(CSIF_S2C_IRQ_STATUS + irq_idx*CSIF_S2C_IRQ_SIZE, read_S2C_status_value);
+ SSDVT_FAIL_MSG(read_S2C_status_value, (0x9D000000), test_case_index | (irq_idx << 16));
+ }
+ }
+
+ // clear enable register
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + irq_idx*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, CSIF_IDLE_IRQ_BIT_MASK);
+ /*
+ CSIF_REG_READ(CSIF_S2C_IDLE_IRQ_ENABLE + irq_idx*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, read_enable_reg_value);
+ if(read_enable_reg_value != 0){
+ SSDVT_FAIL_MSG(read_enable_reg_value, (0x9E000000 | irq_idx), (irq_idx << 16)|(test_case_index << 8)|_testing_main_thread);
+ }
+ */
+}
+
+void cross_idle_irq_test(void)
+{
+ volatile kal_uint32 read_value=0;
+ volatile kal_uint32 dsp_sync_pattern=0;
+ volatile kal_uint32 expect_polling_pattern=0;
+ volatile kal_uint32 dspSyncPattern=0;
+ test_case_index = 0x2000FFFF;
+ // **************************
+ // Disable S2C_IRQ_ENABLE
+ // **************************
+ for(kal_uint32 csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+#if defined(MT6885) || defined(MT6873)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + csif_num_index*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, 0x0);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, read_value);
+ if(read_value != 0x0){
+ SSDVT_FAIL_MSG(read_value, csif_num_index, test_case_index);
+ }
+ }
+ // Disable L1 error
+ //CSIF_REG_WRITE(CSIF_DSP_ERROR_ENABLE_CR, 0x0);
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0);
+
+ // clear s2c irq
+ for(int i = CSIF_ENUM_S2C_N0; i< CSIF_ENUM_ALL_S2C_INT_NUM; i++)
+ {
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_CLR + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+ }
+ // clear s2c idle_irq enable
+ for(int i = 0; i < S2C_IDLE_IRQ_NUM; i++){
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + i*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, CSIF_IDLE_IRQ_BIT_MASK);
+ }
+ // enable s2c irq
+ for(int i = CSIF_ENUM_S2C_N0; i< S2C_IDLE_IRQ_NUM; i++)
+ {
+#if defined(MT6885) || defined(MT6873)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_SET + i*CSIF_S2C_IRQ_SIZE, 0x3);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + i*CSIF_S2C_IRQ_SIZE, 0x3);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ }
+
+ for(_mcore_testing_thread = 0; _mcore_testing_thread < MCORE_TH_NUM; _mcore_testing_thread++)
+ {
+ test_case_index = 0x2EEE0000 | _mcore_testing_thread;
+ switch(_mcore_testing_thread){
+ case 0:
+ dsp_sync_pattern = CSIF_CROSS_IDLE_IRQ_TH0_SYNC;
+ expect_polling_pattern = CSIF_CROSS_IDLE_IRQ_TH0_SYNC_DONE;
+ break;
+ case 1:
+ dsp_sync_pattern = CSIF_CROSS_IDLE_IRQ_TH1_SYNC;
+ expect_polling_pattern = CSIF_CROSS_IDLE_IRQ_TH1_SYNC_DONE;
+ break;
+ case 2:
+ dsp_sync_pattern = CSIF_CROSS_IDLE_IRQ_TH2_SYNC;
+ expect_polling_pattern = CSIF_CROSS_IDLE_IRQ_TH2_SYNC_DONE;
+ break;
+ case 3:
+ dsp_sync_pattern = CSIF_CROSS_IDLE_IRQ_TH3_SYNC;
+ expect_polling_pattern = CSIF_CROSS_IDLE_IRQ_TH3_SYNC_DONE;
+ break;
+ }
+ CSIF_REG_WRITE(CSIF_RSVD_0, dsp_sync_pattern);
+ while(1){
+ CSIF_REG_READ(CSIF_RSVD_0, dspSyncPattern);
+ if(dspSyncPattern == expect_polling_pattern){
+ break;
+ }
+ }
+
+ // 0x21()(irq_num)(thread)(testcase)
+ test_case_index = 0x21000000 | (_mcore_testing_thread << 8);
+ for(kal_uint32 irq_idx = 0; irq_idx < S2C_IDLE_IRQ_NUM; irq_idx++)
+ {
+ test_case_index = test_case_index | 1;
+ // case 1: or with 1111
+ set_idle_irq_mask(irq_idx, 0xF, IDLE_IRQ_ENABLE_TYPE_OR, EXPECT_IRQ_SET_FLAG_TRUE);
+
+ test_case_index = test_case_index | 2;
+ // case 2: or with main thread only
+ set_idle_irq_mask(irq_idx, (0x1 << _mcore_testing_thread), IDLE_IRQ_ENABLE_TYPE_OR, EXPECT_IRQ_SET_FLAG_FALSE);
+
+ test_case_index = test_case_index | 3;
+ // case 3: or with main thread except
+ set_idle_irq_mask(irq_idx, (0xF ^ (0x1 << _mcore_testing_thread)), IDLE_IRQ_ENABLE_TYPE_OR, EXPECT_IRQ_SET_FLAG_TRUE);
+
+ test_case_index = test_case_index | 4;
+ // case 4: and with 1111
+ set_idle_irq_mask(irq_idx, 0xF, IDLE_IRQ_ENABLE_TYPE_AND, EXPECT_IRQ_SET_FLAG_FALSE);
+
+ test_case_index = test_case_index | 5;
+ // case 5: and with main thread only
+ set_idle_irq_mask(irq_idx, (0x1 << _mcore_testing_thread), IDLE_IRQ_ENABLE_TYPE_AND, EXPECT_IRQ_SET_FLAG_FALSE);
+
+ test_case_index = test_case_index | 6;
+ // case 6: or with main thread except
+ set_idle_irq_mask(irq_idx, (0xF ^ (0x1 << _mcore_testing_thread)), IDLE_IRQ_ENABLE_TYPE_AND, EXPECT_IRQ_SET_FLAG_TRUE);
+ }
+ }
+ CSIF_REG_WRITE(CSIF_RSVD_0, CSIF_CROSS_IDLE_IRQ_CORE_SYNC);
+ return;
+}
+
+void cross_mailbox_test(void)
+{
+
+ volatile kal_uint32 read_value=0;
+ volatile kal_uint32 read_mail=0;
+ volatile kal_uint32 dspSyncPattern=0;
+ kal_uint32 maxMailNum = 0;
+ test_case_index = 0x3000FFFF;
+ // **************************
+ // Disable S2C_IRQ_ENABLE
+ // **************************
+ for(kal_uint32 csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+#if defined(MT6885) || defined(MT6873)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + csif_num_index*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, 0x0);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, read_value);
+ if(read_value != 0x0){
+ SSDVT_FAIL_MSG(read_value, csif_num_index, test_case_index);
+ }
+ }
+ // Disable DSP error
+ //CSIF_REG_WRITE(CSIF_DSP_ERROR_ENABLE_CR, 0x0);
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0);
+
+ // Sync barrier before test
+ while(1){
+ CSIF_REG_READ(CSIF_RSVD_0, dspSyncPattern);
+ if(dspSyncPattern == CSIF_CROSS_MAILBOX_SYNC1_DSP){
+ break;
+ }
+ }
+ CSIF_REG_WRITE(CSIF_RSVD_0, CSIF_CROSS_MAILBOX_SYNC1_MCU);
+
+ // 0x30(m_idx)(i 16bit)
+ test_case_index = 0x30000000; // CSIF cross core Mailbox test (s2c part)
+
+ for(kal_uint32 m_idx = 0; m_idx < CSIF_MAILBOX_NUM; m_idx++)
+ {
+ test_case_index = 0x30000000; // CSIF cross core Mailbox test (s2c part)
+ test_case_index = test_case_index | (m_idx << 16);
+
+ if(m_idx == 0){
+ maxMailNum = 256;
+ }
+ else{
+ maxMailNum = 64;
+ }
+ // DSP send mail here
+ while(1){
+ CSIF_REG_READ(CSIF_RSVD_0, dspSyncPattern);
+ if(dspSyncPattern == CSIF_CROSS_MAILBOX_SYNC2_DSP){
+ break;
+ }
+ }
+ // receive mail
+ for(int i = 0; i < maxMailNum + 1; i++){
+ test_case_index = test_case_index | (i);
+ CSIF_REG_READ(CSIF_MAILBOX_RECV + m_idx*CSIF_MAILBOX_SIZE, read_mail);
+ if(read_mail != (MAILBOX_TEST_PREFIX_PATTERN | i)){
+ SSDVT_FAIL_MSG(read_mail, 0xAAAA0001, test_case_index);
+ }
+ }
+
+ CSIF_REG_READ(CSIF_MAILBOX_RECV + m_idx*CSIF_MAILBOX_SIZE, read_mail);
+ if(read_mail != CSIF_MAILBOX_EMPTY_VALUE){
+ SSDVT_FAIL_MSG(read_mail, 0xAAAA00EE, test_case_index);
+ }
+ test_case_index = 0x3b000000; // CSIF cross core Mailbox test (c2s part)
+ test_case_index = test_case_index | (m_idx << 16);
+
+ // send mail
+ for(int i = 0; i < maxMailNum + 1; i++){
+ test_case_index = test_case_index | (i);
+ CSIF_REG_WRITE(CSIF_MAILBOX_SEND + m_idx*CSIF_MAILBOX_SIZE, (MAILBOX_TEST_PREFIX_PATTERN | i));
+ }
+ CSIF_REG_WRITE(CSIF_RSVD_0, CSIF_CROSS_MAILBOX_SYNC2_MCU);
+ // DSP receive mail here until next iteration sync2
+
+ }
+
+}
+
+void csif_reg_default_value_test(void)
+{
+ test_case_index = 0xDC970000;
+
+ volatile kal_uint32 csif_num_index=0;
+
+ //case0: S2C_IRQ
+ //status ,masked status and enable
+ volatile kal_uint32 reg_read_value = 0;
+ for(csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+ //read status
+ CSIF_REG_READ(CSIF_S2C_IRQ_STATUS + csif_num_index*CSIF_S2C_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != S2C_IRQ_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ //read masked status
+ CSIF_REG_READ(CSIF_S2C_IRQ_MASKED_STATUS + csif_num_index*CSIF_S2C_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != S2C_IRQ_MASKED_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ //read enable
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != S2C_IRQ_EN_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+
+ }
+ test_case_index = 0xDC970001;
+
+ //case1: idle
+ //DSP core idle
+ /* mask because not sure DSP state */
+ /*
+ //read status
+ CSIF_REG_READ(CSIF_CORE_IDLE, reg_read_value);
+ if(reg_read_value != DSP_CORE_IDLE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0, test_case_index);
+ }
+ */
+ test_case_index = 0xDC970002;
+
+ //case2: idle_enable irq0 and irq1
+ //status ,masked status and enable
+ for(csif_num_index=0; csif_num_index<S2C_IDLE_IRQ_NUM; csif_num_index++)
+ {
+ //read enable
+ CSIF_REG_READ(CSIF_S2C_IDLE_IRQ_ENABLE + csif_num_index*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, reg_read_value);
+ if(reg_read_value != S2C_IRQ_IDLE_EN_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC970003;
+
+ //case3: c2s irq
+ //status ,masked status
+ for(csif_num_index=0; csif_num_index<C2S_IRQ_NUM; csif_num_index++)
+ {
+ //read status
+ CSIF_REG_READ(CSIF_C2S_IRQ_STATUS + csif_num_index*CSIF_C2S_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != C2S_IRQ_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ //read masked status
+ CSIF_REG_READ(CSIF_C2S_IRQ_MASKED_STATUS + csif_num_index*CSIF_C2S_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != C2S_IRQ_MASKED_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC970004;
+
+ //case4: mpu
+ //start, range
+ for(csif_num_index=0; csif_num_index<(DSP_MPU_NUM+L1_MPU_NUM); csif_num_index++)
+ {
+ //read start addr
+ CSIF_REG_READ(CSIF_MPU_START_ADDR + csif_num_index*CSIF_MPU_SIZE, reg_read_value);
+ if(reg_read_value != MPU_START_ADDR_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ //read range
+ CSIF_REG_READ(CSIF_MPU_RANGE + csif_num_index*CSIF_MPU_SIZE, reg_read_value);
+ if(reg_read_value != MPU_RANGE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC970005;
+
+ //case5: mpu err
+ //addr
+ for(csif_num_index=0; csif_num_index<DSP_MPU_NUM; csif_num_index++)
+ {
+ //read start addr
+ CSIF_REG_READ(CSIF_MPU_ERR_ADDR + csif_num_index*CSIF_MPU_ERR_SIZE, reg_read_value);
+ if(reg_read_value != MPU_ERR_ADDR_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC970006;
+
+ //case6: undefined region record
+ //error_status
+ //read DSM write
+ CSIF_REG_READ(CSIF_DSM_WRITE_UNDEFINED_ERR_STATUS_CR, reg_read_value);
+ if(reg_read_value != DSM_UNDEFINED_REGION_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0, test_case_index);
+ }
+ CSIF_REG_READ(CSIF_DSM_READ_UNDEFINED_ERR_STATUS_CR, reg_read_value);
+ if(reg_read_value != DSM_UNDEFINED_REGION_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 1, test_case_index);
+ }
+ CSIF_REG_READ(CSIF_DSR_WRITE_UNDEFINED_ERR_ADDR_CR, reg_read_value);
+ if(reg_read_value != DSR_UNDEFINED_REGION_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 2, test_case_index);
+ }
+ CSIF_REG_READ(CSIF_DSR_READ_UNDEFINED_ERR_ADDR_CR, reg_read_value);
+ if(reg_read_value != DSR_UNDEFINED_REGION_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 3, test_case_index);
+ }
+ test_case_index = 0xDC970007;
+
+ //case7: error flag
+ //error flag, shapshot, enable
+ //read error flag
+ CSIF_REG_READ(CSIF_L1_ERROR_FLAG_CR, reg_read_value);
+ if(reg_read_value != L1_ERROR_FLAG_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0, test_case_index);
+ }
+ //read error snapshot
+ CSIF_REG_READ(CSIF_L1_ERROR_SNAPSHOT_CR, reg_read_value);
+ if(reg_read_value != L1_ERROR_SNAPSHOT_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 1, test_case_index);
+ }
+ //read error enable
+ CSIF_REG_READ(CSIF_L1_ERROR_ENABLE_CR, reg_read_value);
+ if(reg_read_value != L1_ERROR_EN_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 2, test_case_index);
+ }
+
+ test_case_index = 0xDC970009;
+
+ //case9: S2C irq ovfl
+ //read ovfl error status
+ for(csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+ //read ovfl status
+ CSIF_REG_READ(CSIF_S2C_IRQ_OVFL_STATUS + csif_num_index*CSIF_S2C_IRQ_OVFL_SIZE, reg_read_value);
+ if(reg_read_value != S2C_IRQ_OVFL_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC97000A;
+
+ //case10: C2S irq ovfl
+ //read ovfl error status
+ for(csif_num_index=0; csif_num_index<C2S_IRQ_NUM; csif_num_index++)
+ {
+ //read ovfl status
+ CSIF_REG_READ(CSIF_C2S_IRQ_OVFL_STATUS + csif_num_index*CSIF_C2S_IRQ_OVFL_SIZE, reg_read_value);
+ if(reg_read_value != C2S_IRQ_OVFL_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC97000B;
+
+ // case11: MAILBOX
+ for(csif_num_index=0; csif_num_index<CSIF_MAILBOX_NUM; csif_num_index++)
+ {
+ //read send
+ CSIF_REG_READ(CSIF_MAILBOX_SEND + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_SEND_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC00000 | csif_num_index, test_case_index);
+ }
+ //read recv
+ CSIF_REG_READ(CSIF_MAILBOX_RECV + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_RECV_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC10000 | csif_num_index, test_case_index);
+ }
+ //read status
+ CSIF_REG_READ(CSIF_MAILBOX_STATUS + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_STATS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC20000 | csif_num_index, test_case_index);
+ }
+ //read max_fifo_usage
+ CSIF_REG_READ(CSIF_MAILBOX_MAX_FIFO_USAGE + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_MAX_FIFO_USAGE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC30000 | csif_num_index, test_case_index);
+ }
+#if defined(MT6885) || defined(MT6873)
+ //read error _sub_enable
+ CSIF_REG_READ(CSIF_MAILBOX_ERROR_SUB_ENABLE + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_ERROR_SUB_ENABLE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC90000 | csif_num_index, test_case_index);
+ }
+#endif
+ //read error_status
+ CSIF_REG_READ(CSIF_MAILBOX_ERROR_STATUS + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_ERROR_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC40000 | csif_num_index, test_case_index);
+ }
+ //read error_record
+ CSIF_REG_READ(CSIF_MAILBOX_ERROR_RECORD + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_ERROR_RECORD_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC50000 | csif_num_index, test_case_index);
+ }
+ //read debug_enable
+ CSIF_REG_READ(CSIF_MAILBOX_DEBUG_ENABLE + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_DEBUG_ENABLE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC60000 | csif_num_index, test_case_index);
+ }
+ //read debug_read_content
+ CSIF_REG_READ(CSIF_MAILBOX_DEBUG_READ_CONTENT + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_DEBUG_READ_CONTENT_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC70000 | csif_num_index, test_case_index);
+ }
+ //read debug_read_idx
+ CSIF_REG_READ(CSIF_MAILBOX_DEBUG_READ_IDX + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != MAILBOX_DEBUG_READ_IDX_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC80000 | csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC97000C;
+
+ // case12: OLPDET
+ for(csif_num_index=0; csif_num_index<1; csif_num_index++)
+ {
+ //read set
+ CSIF_REG_READ(CSIF_OLPDET_SET + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_SET_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD00000 | csif_num_index, test_case_index);
+ }
+ //read clr
+ CSIF_REG_READ(CSIF_OLPDET_CLR + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_CLR_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD10000 | csif_num_index, test_case_index);
+ }
+ //read inuse_mail_size
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_INUSE_MAIL_SIZE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD20000 | csif_num_index, test_case_index);
+ }
+#if defined(MT6885) || defined(MT6873)
+ //read max_mail_size
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_MAX_MAIL_SIZE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD90000 | csif_num_index, test_case_index);
+ }
+ //read error sub enable
+ CSIF_REG_READ(CSIF_OLPDET_ERROR_SUB_ENABLE + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_ERROR_SUB_ENABLE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABDA0000 | csif_num_index, test_case_index);
+ }
+#endif
+ //read error_status
+ CSIF_REG_READ(CSIF_OLPDET_ERROR_STATUS + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_ERROR_STATUS_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD30000 | csif_num_index, test_case_index);
+ }
+ //read set_candidate
+ CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_SET_CANDIDATE_RECORD_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD40000 | csif_num_index, test_case_index);
+ }
+ //read clr_candidate
+ CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_CLR_CANDIDATE_RECORD_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD50000 | csif_num_index, test_case_index);
+ }
+ //read debug_read_mum_idx
+ // Note: this debug_mum_idx must be read earlier that debug_read_mum
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_DEBUG_READ_MUM_IDX_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD70000 | csif_num_index, test_case_index);
+ }
+ //read debug_read_mum
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_DEBUG_READ_MUM_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD60000 | csif_num_index, test_case_index);
+ }
+ //read debug_clr_mum_enable
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE + csif_num_index*CSIF_OLPDET_SIZE, reg_read_value);
+ if(reg_read_value != OLPDET_DEBUG_CLR_MUM_ENABLE_DEFAULT_VAL)
+ {
+ // sim fail
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD80000 | csif_num_index, test_case_index);
+ }
+ }
+ test_case_index = 0xDC97000D;
+}
+
+void csif_reg_rw_test(void)
+{
+ volatile kal_uint32 csif_num_index=0;
+ volatile kal_uint32 reg_read_value = 0;
+#if defined(MT6885) || defined(MT6873)
+ kal_uint32 expect_read_value = 0;
+#endif
+ test_case_index = 0xDC971000;
+
+ // Disable C2S IRQ
+ for(csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+#if defined(MT6885) || defined(MT6873)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + csif_num_index*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, 0x0);
+#else
+ #error "unsupport project, may need porting"
+#endif // project option
+ }
+
+ // Disable DSP&L1 error
+ //CSIF_REG_WRITE(CSIF_DSP_ERROR_ENABLE_CR, 0x0);
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0);
+
+ //case0: S2C_IRQ enable
+ for(csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+#if defined(MT6885) || defined(MT6873)
+ expect_read_value = 0;
+ for(kal_uint32 bit_idx = 0; bit_idx < S2C_IRQ_EN_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_SET + csif_num_index*CSIF_S2C_IRQ_SIZE, (0x1 << bit_idx));
+ expect_read_value = expect_read_value | (0x1 << bit_idx);
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != expect_read_value){
+ SSDVT_FAIL_MSG(reg_read_value, (0x000A0000| csif_num_index), test_case_index);
+ }
+ }
+ for(kal_uint32 bit_idx = 0; bit_idx < S2C_IRQ_EN_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + csif_num_index*CSIF_S2C_IRQ_SIZE, (0x1 << bit_idx));
+ expect_read_value = expect_read_value & ~(0x1 << bit_idx);
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != expect_read_value){
+ SSDVT_FAIL_MSG(reg_read_value, (0x000B0000| csif_num_index), test_case_index);
+ }
+ }
+#elif defined(MT6297)
+ //write and read reg bit sequentially
+ for(kal_uint32 bit_idx = 0; bit_idx < S2C_IRQ_EN_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+#else
+ #error "unsupport project, may need porting"
+#endif // project option
+ }
+ // Disable S2C IRQ
+ for(csif_num_index=0; csif_num_index<S2C_IRQ_NUM; csif_num_index++)
+ {
+#if defined(MT6885) || defined(MT6873)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + csif_num_index*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + csif_num_index*CSIF_S2C_IRQ_SIZE, 0x0);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ }
+
+ test_case_index = 0xDC971002;
+
+ //case2: MPU start/range
+ for(csif_num_index=0; csif_num_index<DSP_MPU_NUM+L1_MPU_NUM; csif_num_index++)
+ {
+ //write and read reg bit sequentially
+ // MPU start
+ for(kal_uint32 bit_idx = 0; bit_idx < MPU_START_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_MPU_START_ADDR + csif_num_index*CSIF_MPU_SIZE, (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_MPU_START_ADDR + csif_num_index*CSIF_MPU_SIZE, reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ // MPU range
+ for(kal_uint32 bit_idx = 0; bit_idx < MPU_RANGE_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_MPU_RANGE + csif_num_index*CSIF_MPU_SIZE, (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_MPU_RANGE + csif_num_index*CSIF_MPU_SIZE, reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, csif_num_index, test_case_index);
+ }
+ }
+ }
+ // Clear MPU start/range
+ for(csif_num_index=0; csif_num_index<DSP_MPU_NUM+L1_MPU_NUM; csif_num_index++)
+ {
+ CSIF_REG_WRITE(CSIF_MPU_START_ADDR + csif_num_index*CSIF_MPU_SIZE, 0x0);
+ CSIF_REG_WRITE(CSIF_MPU_RANGE + csif_num_index*CSIF_MPU_SIZE, 0x0);
+ }
+ test_case_index = 0xDC971003;
+
+ //case3: Error enable
+ //write and read reg bit sequentially
+ // L1 error enable
+ for(kal_uint32 bit_idx = 0; bit_idx < L1_ERROR_EN_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_L1_ERROR_ENABLE_CR, reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, bit_idx, test_case_index);
+ }
+ }
+ // Clear DSP & L1 error enable
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0);
+ test_case_index = 0xDC971004;
+
+ //case4: MAILBOX
+ for(csif_num_index=0; csif_num_index<CSIF_MAILBOX_NUM; csif_num_index++)
+ {
+ //mailbox_send RW
+ for(kal_uint32 bit_idx = 0; bit_idx < MAILBOX_SEND_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_MAILBOX_SEND + csif_num_index*CSIF_MAILBOX_SIZE, (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_MAILBOX_SEND + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC00000 | csif_num_index << 8 | bit_idx, test_case_index);
+ }
+ }
+ //mailbox_debug_enable RW
+ for(kal_uint32 bit_idx = 0; bit_idx < MAILBOX_DEBUG_ENABLE_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_MAILBOX_DEBUG_ENABLE + csif_num_index*CSIF_MAILBOX_SIZE, (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_MAILBOX_DEBUG_ENABLE + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC10000 | csif_num_index << 8 | bit_idx, test_case_index);
+ }
+ }
+#if defined(MT6885) || defined(MT6873)
+ //mailbox_error_sub_enable
+ for(kal_uint32 bit_idx = 0; bit_idx < MAILBOX_ERROR_SUB_ENABLE_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_MAILBOX_ERROR_SUB_ENABLE + csif_num_index*CSIF_MAILBOX_SIZE, (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_MAILBOX_ERROR_SUB_ENABLE + csif_num_index*CSIF_MAILBOX_SIZE, reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABC20000 | csif_num_index << 8 | bit_idx, test_case_index);
+ }
+ }
+#endif
+ }
+ test_case_index = 0xDC971005;
+ //case5: olpdet
+ //olpdet set/clr RW
+ for(kal_uint32 bit_idx = CSIF_OLPDET_SET_OFFSET_P; bit_idx < CSIF_OLPDET_SET_OFFSET_P+OLPDET_SET_CLR_OFFSET_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_OLPDET_SET , (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_OLPDET_SET , reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD00000 | bit_idx, test_case_index);
+ }
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR , (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_OLPDET_CLR , reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD10000 | bit_idx, test_case_index);
+ }
+ }
+ for(kal_uint32 bit_idx = CSIF_OLPDET_SET_LENGTH_P; bit_idx < CSIF_OLPDET_SET_LENGTH_P+OLPDET_SET_CLR_LENGTH_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_OLPDET_SET , (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_OLPDET_SET , reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD20000 | bit_idx, test_case_index);
+ }
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR , (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_OLPDET_CLR , reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD30000 | bit_idx, test_case_index);
+ }
+ }
+ //olpdet debug_clr_mum_enable RW
+ for(kal_uint32 bit_idx = 0; bit_idx < OLPDET_DEBUG_CLR_MUM_ENABLE_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE , (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE , reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD40000 | bit_idx, test_case_index);
+ }
+ }
+#if defined(MT6885) || defined(MT6873)
+ //olpdet error_sub_enable
+ for(kal_uint32 bit_idx = 0; bit_idx < OLPDET_ERROR_SUB_ENABLE_WIDTH; bit_idx++){
+ CSIF_REG_WRITE(CSIF_OLPDET_ERROR_SUB_ENABLE , (0x1 << bit_idx));
+ CSIF_REG_READ(CSIF_OLPDET_ERROR_SUB_ENABLE , reg_read_value);
+ if(reg_read_value != (0x1 << bit_idx)){
+ SSDVT_FAIL_MSG(reg_read_value, 0xABD50000 | bit_idx, test_case_index);
+ }
+ }
+#endif // project option
+ test_case_index = 0xDC971006;
+}
+
+
+
+
+void OLPDET_Set(csif_uint32 two_word_addr, csif_uint32 two_word_size)
+{
+ set_api_value = (two_word_addr << CSIF_OLPDET_SET_OFFSET_P) | (two_word_size << CSIF_OLPDET_SET_LENGTH_P);
+ if(expect_error_status != 0){
+ expect_set_candidate_record = set_api_value;
+ }
+ CSIF_REG_WRITE(CSIF_OLPDET_SET, set_api_value);
+}
+
+void OLPDET_Clr(csif_uint32 two_word_addr, csif_uint32 two_word_size)
+{
+ clr_api_value = (two_word_addr << CSIF_OLPDET_SET_OFFSET_P) | (two_word_size << CSIF_OLPDET_SET_LENGTH_P);
+ if(expect_error_status != 0){
+ expect_clr_candidate_record = clr_api_value;
+ }
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR, clr_api_value);
+}
+
+void olpdet_check_status(void)
+{
+ volatile kal_uint32 read_error_flag;
+ volatile kal_uint32 read_error_snapshot;
+ volatile kal_uint32 inuse_mail_size;
+ volatile kal_uint32 error_status;
+
+
+
+#if defined(MT6885) || defined(MT6873)
+ volatile kal_uint32 max_mail_size;
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE, max_mail_size);
+#endif
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE, inuse_mail_size);
+ CSIF_REG_READ(CSIF_OLPDET_ERROR_STATUS, error_status);
+ CSIF_REG_READ(CSIF_L1_ERROR_FLAG_CR, read_error_flag);
+ CSIF_REG_READ(CSIF_L1_ERROR_SNAPSHOT_CR, read_error_snapshot);
+
+ if(expect_error_status != 0){
+ SSDVT_FAIL_MSG(read_error_snapshot, (log_pattern | 0xFB0000)| (error_status & 0xFFFF) , test_case_index);
+ }
+ else{
+#if defined(MT6885) || defined(MT6873)
+ if(max_mail_size != expect_max_mail_size )
+ {
+ SSDVT_FAIL_MSG(max_mail_size, (log_pattern | 0xB40000)| (expect_max_mail_size & 0xFFFF) , test_case_index);
+ }
+#endif
+ if(inuse_mail_size != expect_inuse_mail_size )
+ {
+ SSDVT_FAIL_MSG(inuse_mail_size, (log_pattern | 0xB00000)| (expect_inuse_mail_size & 0xFFFF) , test_case_index);
+ }
+
+ if(error_status != expect_error_status)
+ {
+ SSDVT_FAIL_MSG(error_status, (log_pattern | 0xB10000)| (expect_error_status & 0xFFFF), test_case_index);
+ }
+ if(set_candidate_record != expect_set_candidate_record)
+ {
+ SSDVT_FAIL_MSG(set_candidate_record, (log_pattern | 0xB20000)| (expect_set_candidate_record & 0xFFFFF), test_case_index);
+ }
+ if(clr_candidate_record != expect_clr_candidate_record)
+ {
+ SSDVT_FAIL_MSG(clr_candidate_record, (log_pattern | 0xB30000)| (expect_clr_candidate_record & 0xFFFFF), test_case_index);
+ }
+ if((read_error_flag & (0x1 << (OLPDET_ERR_BIT ))) != 0 ){
+ SSDVT_FAIL_MSG(read_error_flag, (log_pattern | 0xBA0000) , test_case_index);
+ }
+ if((read_error_snapshot & (0x1 << (OLPDET_ERR_BIT ))) != 0 ){
+ SSDVT_FAIL_MSG(read_error_snapshot, (log_pattern | 0xBB0000), test_case_index);
+ }
+ }
+}
+
+void csif_olpdet_dvt_test(void)
+{
+
+ // Disable DSP&L1 error
+ //CSIF_REG_WRITE(CSIF_DSP_ERROR_ENABLE_CR, 0x0);
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, CSIF_L1_ERROR_MASK);
+
+#if defined(MT6885) || defined(MT6873)
+ volatile kal_uint32 read_max_mail_size;
+#endif
+
+
+
+
+
+ volatile kal_uint32 read_debug_read_mum;
+ volatile kal_uint32 read_debug_read_mum_idx;
+
+ kal_uint32 region_start_addr = 0;
+
+ kal_uint32 olpdet_error_flag = 0;
+
+ volatile kal_uint32 dummy_olpdet_counter = 0;
+
+
+ //******* local variable init!! **************//
+#if defined(MT6885) || defined(MT6873)
+ expect_max_mail_size = 0;
+#endif
+ expect_inuse_mail_size = 0;
+ expect_error_status = 0;
+ expect_set_candidate_record = 0;
+ expect_clr_candidate_record = 0;
+ //*****************************************//
+
+ // case1: check initial status
+ test_case_index = 0xDC972001;
+ // check OLPDET status
+ log_pattern = 0xAA000000;
+ set_candidate_record = expect_set_candidate_record;
+ clr_candidate_record = expect_clr_candidate_record;
+ olpdet_check_status();
+
+ // case2 set default olpdet region
+ test_case_index = 0xDC972A00;
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR, OLPDET_TEST_REGION_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_B_START_ADDR, OLPDET_TEST_REGION_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_C_START_ADDR, OLPDET_TEST_REGION_LENGTH);
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = OLPDET_TEST_REGION_LENGTH*3;
+ expect_error_status = 0;
+ expect_set_candidate_record = 0;
+ expect_clr_candidate_record = 0;
+#if defined(MT6885) || defined(MT6873)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+#endif
+ //*****************************************//
+
+ for(kal_uint32 test_region = OLPDET_TEST_REGION_A; test_region < OLPDET_TEST_REGION_TOTAL; test_region++)
+ {
+ switch(test_region){
+ case OLPDET_TEST_REGION_A:
+ region_start_addr = OLPDET_TEST_REGION_A_START_ADDR;
+ break;
+ case OLPDET_TEST_REGION_B:
+ region_start_addr = OLPDET_TEST_REGION_B_START_ADDR;
+ break;
+ case OLPDET_TEST_REGION_C:
+ region_start_addr = OLPDET_TEST_REGION_C_START_ADDR;
+ break;
+ }
+ for(kal_uint32 test_point = 0; test_point < 7; test_point++)
+ {
+ test_case_index = test_case_index | (test_region << 8) | test_point;
+
+ if(TEST_REGION_POINT_ARRAY[test_region][test_point] == KAL_FALSE){
+ continue;
+ }
+
+ if(test_point == 0 || test_point == 6 )
+ {
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size + OLPDET_TEST_POINT_LENGTH;
+ expect_error_status = 0;
+ expect_set_candidate_record = 0;
+ expect_clr_candidate_record = 0;
+ #if defined(MT6885) || defined(MT6873)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+ #endif
+ //*****************************************//
+ log_pattern = 0xBA000000;
+ set_candidate_record = expect_set_candidate_record;
+ clr_candidate_record = expect_clr_candidate_record;
+ olpdet_error_flag = 1;
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ }
+ else
+ {
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size;
+ if(test_region == OLPDET_TEST_REGION_C && (test_point == 5) )
+ {
+
+ expect_error_status = (0x1 << OLPDET_OLP_HIT_ERROR_BIT) | (0x1 << OLPDET_SET_CONTENT_ERROR_BIT);
+ //expect_error_status = (0x1 << OLPDET_OLP_HIT_ERROR_BIT) ;
+ }
+ else{
+ expect_error_status = 0x1 << OLPDET_OLP_HIT_ERROR_BIT;
+ }
+ #if defined(MT6885) || defined(MT6873)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+ #endif
+ //expect_set_candidate_record = set_api_value;
+ CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+ // modify flag to false that must be set to true in exception callback
+ olpdet_error_polling_flag = KAL_FALSE;
+ //*****************************************//
+ log_pattern = 0xBB000000;
+ }
+ switch(test_point)
+ {
+ case 0:
+ OLPDET_Set(region_start_addr - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 1:
+ OLPDET_Set(region_start_addr - OLPDET_TEST_POINT_LENGTH + 1, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 2:
+ OLPDET_Set(region_start_addr, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 3:
+ OLPDET_Set(region_start_addr + 64, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 4:
+ OLPDET_Set(region_start_addr + OLPDET_TEST_REGION_LENGTH - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 5:
+ OLPDET_Set(region_start_addr + OLPDET_TEST_REGION_LENGTH - OLPDET_TEST_POINT_LENGTH + 1, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 6:
+ OLPDET_Set(region_start_addr + OLPDET_TEST_REGION_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ break;
+ }
+ while(olpdet_error_polling_flag != KAL_TRUE){
+ dummy_olpdet_counter++;
+ }
+ if(olpdet_error_flag != 0){
+ olpdet_check_status();
+ olpdet_error_flag = 0;
+ }
+ }
+ }
+#if defined(MT6885) || defined(MT6873)
+ // case2a clr default olpdet region
+ test_case_index = 0xDC972B00;
+ // reset region to default
+ OLPDET_Clr(OLPDET_TEST_REGION_A_START_ADDR + OLPDET_TEST_REGION_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Clr(OLPDET_TEST_REGION_B_START_ADDR - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Clr(OLPDET_TEST_REGION_B_START_ADDR + OLPDET_TEST_REGION_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Clr(OLPDET_TEST_REGION_C_START_ADDR - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size - 4*OLPDET_TEST_POINT_LENGTH;
+ expect_error_status = 0;
+ expect_set_candidate_record = 0;
+ expect_clr_candidate_record = 0;
+#if defined(MT6885) || defined(MT6873)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+#endif
+ //*****************************************//
+ for(kal_uint32 test_region = OLPDET_TEST_REGION_A; test_region < OLPDET_TEST_REGION_TOTAL; test_region++)
+ {
+ switch(test_region){
+ case OLPDET_TEST_REGION_A:
+ region_start_addr = OLPDET_TEST_REGION_A_START_ADDR;
+ break;
+ case OLPDET_TEST_REGION_B:
+ region_start_addr = OLPDET_TEST_REGION_B_START_ADDR;
+ break;
+ case OLPDET_TEST_REGION_C:
+ region_start_addr = OLPDET_TEST_REGION_C_START_ADDR;
+ break;
+ }
+ for(kal_uint32 test_point = 0; test_point < 7; test_point++)
+ {
+ test_case_index = test_case_index | (test_region << 8) | test_point;
+
+ if(TEST_REGION_POINT_ARRAY[test_region][test_point] == KAL_FALSE){
+ continue;
+ }
+
+ if(test_point == 2 || test_point == 3 || test_point == 4 )
+ {
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size - OLPDET_TEST_POINT_LENGTH;
+ expect_error_status = 0;
+ expect_set_candidate_record = 0;
+ expect_clr_candidate_record = 0;
+ #if defined(MT6885) || defined(MT6873)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+ #endif
+ //*****************************************//
+ log_pattern = 0xBA000000;
+ set_candidate_record = expect_set_candidate_record;
+ clr_candidate_record = expect_clr_candidate_record;
+ olpdet_error_flag = 1;
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ }
+ else
+ {
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size;
+ if(test_region == OLPDET_TEST_REGION_C && (test_point == 5) )
+ {
+
+ expect_error_status = (0x1 << OLPDET_CLR_NOHIT_ERROR_BIT) | (0x1 << OLPDET_CLR_CONTENT_ERROR_BIT);
+ }
+ else{
+ expect_error_status = 0x1 << OLPDET_CLR_NOHIT_ERROR_BIT;
+ }
+ #if defined(MT6885) || defined(MT6873)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+ #endif
+ //expect_set_candidate_record = set_api_value;
+ CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, expect_set_candidate_record);
+ // modify flag to false that must be set to true in exception callback
+ olpdet_error_polling_flag = KAL_FALSE;
+ //*****************************************//
+ log_pattern = 0xBB000000;
+ }
+ switch(test_point)
+ {
+ case 0:
+ OLPDET_Clr(region_start_addr - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 1:
+ OLPDET_Clr(region_start_addr - OLPDET_TEST_POINT_LENGTH + 1, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 2:
+ OLPDET_Clr(region_start_addr, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 3:
+ OLPDET_Clr(region_start_addr + 64, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 4:
+ OLPDET_Clr(region_start_addr + OLPDET_TEST_REGION_LENGTH - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 5:
+ OLPDET_Clr(region_start_addr + OLPDET_TEST_REGION_LENGTH - OLPDET_TEST_POINT_LENGTH + 1, OLPDET_TEST_POINT_LENGTH);
+ break;
+ case 6:
+ OLPDET_Clr(region_start_addr + OLPDET_TEST_REGION_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ break;
+ }
+ while(olpdet_error_polling_flag != KAL_TRUE){
+ dummy_olpdet_counter++;
+ }
+ if(olpdet_error_flag != 0){
+ olpdet_check_status();
+ olpdet_error_flag = 0;
+ }
+ }
+ }
+
+ test_case_index = 0xDC972C00;
+ //reset region to default (restore testing point 2, 3, 4)
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR + 64, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR + OLPDET_TEST_REGION_LENGTH - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_B_START_ADDR, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_B_START_ADDR + 64, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_B_START_ADDR + OLPDET_TEST_REGION_LENGTH - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_C_START_ADDR, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_C_START_ADDR + 64, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_C_START_ADDR + OLPDET_TEST_REGION_LENGTH - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ // restore region state to after set test
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR + OLPDET_TEST_REGION_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_B_START_ADDR - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_B_START_ADDR + OLPDET_TEST_REGION_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ OLPDET_Set(OLPDET_TEST_REGION_C_START_ADDR - OLPDET_TEST_POINT_LENGTH, OLPDET_TEST_POINT_LENGTH);
+ //clear max mail size
+ CSIF_REG_WRITE(CSIF_OLPDET_MAX_MAIL_SIZE_CLR, 0x1);
+ expect_max_mail_size = 0;
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size + 13*OLPDET_TEST_POINT_LENGTH;
+ expect_error_status = 0;
+ expect_set_candidate_record = set_candidate_record;
+ expect_clr_candidate_record = clr_candidate_record;
+#if defined(MT6885) || defined(MT6873)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+#endif
+ olpdet_error_flag = 1;
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ olpdet_check_status();
+ //*****************************************//
+
+#endif // Petrus project
+
+ // case3 set content error
+ test_case_index = 0xDC973000;
+
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size;
+ expect_error_status = (0x1 << OLPDET_SET_CONTENT_ERROR_BIT);
+ expect_set_candidate_record = set_api_value;
+ CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+#if defined(MT6885) || defined(MT6873)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+#endif
+ olpdet_error_polling_flag = KAL_FALSE;
+ //*****************************************//
+ log_pattern = 0xCA000000;
+ // set length overflow
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 129);
+ while(olpdet_error_polling_flag != KAL_TRUE){
+ dummy_olpdet_counter++;
+ }
+ // case4 clr length overflow
+ test_case_index = 0xDC974000;
+
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size;
+ expect_error_status = (0x1 << OLPDET_CLR_CONTENT_ERROR_BIT);
+ CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, expect_set_candidate_record);
+ expect_clr_candidate_record = clr_api_value;
+#if defined(MT6885) || defined(MT6873)
+ if(expect_inuse_mail_size > expect_max_mail_size){
+ expect_max_mail_size = expect_inuse_mail_size;
+ }else{
+ expect_max_mail_size = expect_max_mail_size;
+ }
+#endif
+ olpdet_error_polling_flag = KAL_FALSE;
+ //*****************************************//
+ log_pattern = 0xCB000000;
+ // clr length overflow
+#if defined(MT6885) || defined(MT6873)
+ OLPDET_Clr(OLPDET_TEST_REGION_A_START_ADDR, 129);
+#elif defined(MT6297)
+ OLPDET_Clr(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 129);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ while(olpdet_error_polling_flag != KAL_TRUE){
+ dummy_olpdet_counter++;
+ }
+ // case5 Dump MUM
+ test_case_index = 0xDC975000;
+
+ // create set MUM array
+ //first 128 + tail 2 bit
+ expect_mum_arr[0] = 0xFFFFFFFF; //0 ~ 31
+ expect_mum_arr[1] = 0xFFFFFFFF; //32 ~ 63
+ expect_mum_arr[2] = 0xFFFFFFFF; //64 ~ 95
+ expect_mum_arr[3] = 0xFFFFFFFF; //96 ~ 127
+ expect_mum_arr[4] = 0x00000003; //128 ~ 129
+
+ // head 2 bit + 1024~1151 + tail 2 bit
+ expect_mum_arr[31] = 0xC0000000; //1022 ~ 1023
+ expect_mum_arr[32] = 0xFFFFFFFF; //1024 ~ 1055
+ expect_mum_arr[33] = 0xFFFFFFFF; //1056 ~ 1087
+ expect_mum_arr[34] = 0xFFFFFFFF; //1088 ~ 1119
+ expect_mum_arr[35] = 0xFFFFFFFF; //1120 ~ 1151
+ expect_mum_arr[36] = 0x00000003; //1152 ~ 1153
+
+ // head 2 bit + 1920 ~ 2048
+ expect_mum_arr[59] = 0xC0000000; //1022 ~ 1023
+ expect_mum_arr[60] = 0xFFFFFFFF; //1920 ~ 1951
+ expect_mum_arr[61] = 0xFFFFFFFF; //1954 ~ 1983
+ expect_mum_arr[62] = 0xFFFFFFFF; //1984 ~ 2015
+ expect_mum_arr[63] = 0xFFFFFFFF; //2016 ~ 2047
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX, read_debug_read_mum_idx);
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM, read_debug_read_mum);
+ dump_mum_arr[read_debug_read_mum_idx] = read_debug_read_mum;
+ }
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ test_case_index = test_case_index | dump_i;
+ if(dump_mum_arr[dump_i] != expect_mum_arr[dump_i]){
+ SSDVT_FAIL_MSG(dump_mum_arr[dump_i], expect_mum_arr[dump_i], test_case_index);
+ }
+ }
+
+ //case:6 clear error and redump MUM
+ test_case_index = 0xDC976000;
+ // clear error
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX, read_debug_read_mum_idx);
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM, read_debug_read_mum);
+ dump_mum_arr[read_debug_read_mum_idx] = read_debug_read_mum;
+ }
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ test_case_index = test_case_index | dump_i;
+ if(dump_mum_arr[dump_i] != expect_mum_arr[dump_i]){
+ SSDVT_FAIL_MSG(dump_mum_arr[dump_i], expect_mum_arr[dump_i], test_case_index);
+ }
+ }
+#if defined(MT6297)
+ //case:7 trigger error and enable debug_clr_mum, then dump(should be empty)
+ test_case_index = 0xDC977000;
+
+ //******* local variable init!! **************//
+ expect_inuse_mail_size = expect_inuse_mail_size;
+ expect_error_status = (0x1 << OLPDET_SET_CONTENT_ERROR_BIT);
+ expect_set_candidate_record = set_api_value;
+ CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+ olpdet_error_polling_flag = KAL_FALSE;
+ //*****************************************//
+ log_pattern = 0xDA000000;
+
+ // enable debug_clr_mum
+ CSIF_REG_WRITE(CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE, 0x1);
+
+ // set length overflow
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 129);
+ while(olpdet_error_polling_flag != KAL_TRUE){
+ dummy_olpdet_counter++;
+ }
+ /*
+ for(int i = 0; i < 100; i++){
+ dummy_olpdet_counter++;
+ }
+ */
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX, read_debug_read_mum_idx);
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM, read_debug_read_mum);
+ dump_mum_arr[read_debug_read_mum_idx] = read_debug_read_mum;
+ }
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ test_case_index = test_case_index | dump_i;
+ if(dump_mum_arr[dump_i] != 0){
+ SSDVT_FAIL_MSG(dump_mum_arr[dump_i], 0xDAFFBEEF, test_case_index);
+ }
+ }
+
+
+ test_case_index = 0xDC972008;
+ return;
+#elif defined(MT6885) || defined(MT6873)
+ //case:7 enable debug_clr_mum, then clear error (without error happened) and dump(should be empty)
+ test_case_index = 0xDC977000;
+ // enable debug_clr_mum
+ CSIF_REG_WRITE(CSIF_OLPDET_DEBUG_CLR_MUM_ENABLE, 0x1);
+ // Clear error
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+ // Clear max mail size
+ CSIF_REG_WRITE(CSIF_OLPDET_MAX_MAIL_SIZE_CLR, 0x1);
+ //******* local variable init!! **************//
+ expect_max_mail_size = 0;
+ expect_inuse_mail_size = 0;
+ expect_error_status = 0;
+ expect_set_candidate_record = set_candidate_record;
+ expect_clr_candidate_record = clr_candidate_record;
+ //CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, expect_set_candidate_record);
+ //CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+ olpdet_error_flag = 1;
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ //*****************************************//
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX, read_debug_read_mum_idx);
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM, read_debug_read_mum);
+ dump_mum_arr[read_debug_read_mum_idx] = read_debug_read_mum;
+ }
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ test_case_index = test_case_index | dump_i;
+ if(dump_mum_arr[dump_i] != 0){
+ SSDVT_FAIL_MSG(dump_mum_arr[dump_i], 0xDAFFBEEF, test_case_index);
+ }
+ }
+ log_pattern = 0xDB000000;
+ olpdet_check_status();
+
+ //case:8 Disable sub enable and trigger error, check error status
+ test_case_index = 0xDC978000;
+ log_pattern = 0xDC000000;
+ CSIF_REG_WRITE(CSIF_OLPDET_ERROR_SUB_ENABLE, ~(CSIF_OLPDET_SET_CONTENT_ERROR_M | CSIF_OLPDET_CLR_CONTENT_ERROR_M | CSIF_OLPDET_OLP_HIT_ERROR_M | CSIF_OLPDET_CLR_NOHIT_ERROR_M));
+
+ //******* local variable init!! **************//
+ expect_error_status = 0;
+ expect_set_candidate_record = set_candidate_record;
+ expect_clr_candidate_record = clr_candidate_record;
+ //CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, expect_set_candidate_record);
+ //CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 129);
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE, expect_inuse_mail_size);
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE, expect_max_mail_size);
+ olpdet_error_flag = 1;
+
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ //*****************************************//
+
+ olpdet_check_status();
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+
+ // olpdet_clr_content error
+ log_pattern = 0xDD000000;
+
+ //******* local variable init!! **************//
+ expect_error_status = 0;
+ expect_set_candidate_record = set_candidate_record;
+ expect_clr_candidate_record = clr_candidate_record;
+ //CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, expect_set_candidate_record);
+ //CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+ olpdet_error_flag = 1;
+ OLPDET_Clr(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 129);
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE, expect_inuse_mail_size);
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE, expect_max_mail_size);
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ //*****************************************//
+
+ olpdet_check_status();
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+
+ // olpdet_olphit error
+ log_pattern = 0xDE000000;
+
+ //******* local variable init!! **************//
+ expect_error_status = 0;
+ expect_set_candidate_record = set_candidate_record;
+ expect_clr_candidate_record = clr_candidate_record;
+ //CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, expect_set_candidate_record);
+ //CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+ olpdet_error_flag = 1;
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 128);
+ OLPDET_Set(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 128);
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE, expect_inuse_mail_size);
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE, expect_max_mail_size);
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ //*****************************************//
+ olpdet_check_status();
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+
+ // olpdet_clr nohit error
+ log_pattern = 0xDF000000;
+
+ //******* local variable init!! **************//
+ expect_error_status = 0;
+ expect_set_candidate_record = set_candidate_record;
+ expect_clr_candidate_record = clr_candidate_record;
+ //CSIF_REG_READ(CSIF_OLPDET_SET_CANDIDATE_RECORD, expect_set_candidate_record);
+ //CSIF_REG_READ(CSIF_OLPDET_CLR_CANDIDATE_RECORD, expect_clr_candidate_record);
+ olpdet_error_flag = 1;
+ OLPDET_Clr(OLPDET_TEST_REGION_A_START_ADDR+OLPDET_TEST_REGION_LENGTH+128, 128);
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE, expect_inuse_mail_size);
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE, expect_max_mail_size);
+ // modify flag to true that test can directly go through
+ olpdet_error_polling_flag = KAL_TRUE;
+ //*****************************************//
+ olpdet_check_status();
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+#else
+ #error "unsupport project, may need porting"
+#endif
+}
+
+void csif_mem_test(void)
+{
+
+
+ volatile kal_uint32 write_idx = 0;
+ volatile kal_uint32 mem_read_value = 0;
+ volatile kal_uint64 mem_read_value_64 = 0;
+
+
+ volatile kal_uint32 memory_base_addr = CSIF_DSM_BASE;
+ volatile kal_uint32 memory_size = CSIF_DSM_SIZE;
+
+ //case0: write 0 (1x/1x)
+ for(write_idx = 0; write_idx < memory_size/4; write_idx++)
+ {
+ *((volatile kal_uint32*)(memory_base_addr+write_idx*4)) = MEM_TEST_PATTERN0;
+ mem_read_value = *((volatile kal_uint32*)(memory_base_addr+write_idx*4));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*4),test_case_index);
+ if(mem_read_value != MEM_TEST_PATTERN0){
+ SSDVT_FAIL_MSG(mem_read_value, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 1;
+
+ //case1: write 0xFFFFFFFF (1x/1x)
+ for(write_idx = 0; write_idx < memory_size/4; write_idx++)
+ {
+ *((volatile kal_uint32*)(memory_base_addr+write_idx*4)) = MEM_TEST_PATTERN1;
+ mem_read_value = *((volatile kal_uint32*)(memory_base_addr+write_idx*4));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*4),test_case_index);
+ if(mem_read_value != MEM_TEST_PATTERN1){
+ SSDVT_FAIL_MSG(mem_read_value, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 2;
+
+ //case2: write 0xA5A5A5A5 (1x/1x)
+ for(write_idx = 0; write_idx < memory_size/4; write_idx++)
+ {
+ *((volatile kal_uint32*)(memory_base_addr+write_idx*4)) = MEM_TEST_PATTERN2;
+ mem_read_value = *((volatile kal_uint32*)(memory_base_addr+write_idx*4));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*4),test_case_index);
+ if(mem_read_value != MEM_TEST_PATTERN2){
+ SSDVT_FAIL_MSG(mem_read_value, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 3;
+
+ //case3: write 0x5A5A5A5A (1x/1x)
+ for(write_idx = 0; write_idx < memory_size/4; write_idx++)
+ {
+ *((volatile kal_uint32*)(memory_base_addr+write_idx*4)) = MEM_TEST_PATTERN3;
+ mem_read_value = *((volatile kal_uint32*)(memory_base_addr+write_idx*4));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*4),test_case_index);
+ if(mem_read_value != MEM_TEST_PATTERN3){
+ SSDVT_FAIL_MSG(mem_read_value, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 4;
+
+ //case4: write incremental pattern (1x/1x)
+ volatile kal_uint32 INC_PATTERN = 1;
+ for(write_idx = 0; write_idx < memory_size/4; write_idx++)
+ {
+ *((volatile kal_uint32*)(memory_base_addr+write_idx*4)) = INC_PATTERN;
+ mem_read_value = *((volatile kal_uint32*)(memory_base_addr+write_idx*4));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*4),test_case_index);
+ if(mem_read_value != INC_PATTERN){
+ SSDVT_FAIL_MSG(mem_read_value, write_idx, test_case_index);
+ }
+ INC_PATTERN++;
+ }
+
+ test_case_index = 5;
+
+ //case5: write 0 (2x/2x)
+ for(write_idx = 0; write_idx < memory_size/8; write_idx++)
+ {
+ *((volatile kal_uint64*)(memory_base_addr+write_idx*8)) = MEM_TEST_PATTERN0;
+ mem_read_value_64 = *((volatile kal_uint64*)(memory_base_addr+write_idx*8));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*8),test_case_index);
+ if(mem_read_value_64 != MEM_TEST_PATTERN0){
+ SSDVT_FAIL_MSG((kal_uint32)mem_read_value_64, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 6;
+
+ //case6: write 0xFFFFFFFFFFFFFFFF (2x/2x)
+ for(write_idx = 0; write_idx < memory_size/8; write_idx++)
+ {
+ *((volatile kal_uint64*)(memory_base_addr+write_idx*8)) = MEM_TEST_PATTERN1_64;
+ mem_read_value_64 = *((volatile kal_uint64*)(memory_base_addr+write_idx*8));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*8),test_case_index);
+ if(mem_read_value_64 != MEM_TEST_PATTERN1_64){
+ SSDVT_FAIL_MSG((kal_uint32)mem_read_value_64, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 7;
+
+ //case7: write 0xA5A5A5A5A5A5A5A5 (2x/2x)
+ for(write_idx = 0; write_idx < memory_size/8; write_idx++)
+ {
+ *((volatile kal_uint64*)(memory_base_addr+write_idx*8)) = MEM_TEST_PATTERN2_64;
+ mem_read_value_64 = *((volatile kal_uint64*)(memory_base_addr+write_idx*8));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*8),test_case_index);
+ if(mem_read_value_64 != MEM_TEST_PATTERN2_64){
+ SSDVT_FAIL_MSG((kal_uint32)mem_read_value_64, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 8;
+
+ //case8: write 0x5A5A5A5A5A5A5A5A (2x/2x)
+ for(write_idx = 0; write_idx < memory_size/8; write_idx++)
+ {
+ *((volatile kal_uint64*)(memory_base_addr+write_idx*8)) = MEM_TEST_PATTERN3_64;
+ mem_read_value_64 = *((volatile kal_uint64*)(memory_base_addr+write_idx*8));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*8),test_case_index);
+ if(mem_read_value_64 != MEM_TEST_PATTERN3_64){
+ SSDVT_FAIL_MSG((kal_uint32)mem_read_value_64, write_idx, test_case_index);
+ }
+ }
+
+ test_case_index = 9;
+
+ //case9: write incremental pattern (2x/2x)
+ volatile kal_uint64 INC_PATTERN_64 = 1;
+ for(write_idx = 0; write_idx < memory_size/8; write_idx++)
+ {
+ *((volatile kal_uint64*)(memory_base_addr+write_idx*8)) = INC_PATTERN_64;
+ mem_read_value_64 = *((volatile kal_uint64*)(memory_base_addr+write_idx*8));
+ SSDVT_LOG(write_idx,(memory_base_addr+write_idx*8),test_case_index);
+ if(mem_read_value_64 != INC_PATTERN_64){
+ SSDVT_FAIL_MSG((kal_uint32)mem_read_value_64, write_idx, test_case_index);
+ }
+ INC_PATTERN++;
+ }
+
+ test_case_index = 10;
+}
+
+#if defined(__CSIF_DRV_TEST__)
+void CSIF_C2S_IRQ_SET_test(void)
+{
+ // enable all c2s_IRQ
+ /*
+ for (int i=CSIF_ENUM_C2S_N0; i<CSIF_ENUM_ALL_C2S_INT_NUM; i++){
+ CSIF_REG_WRITE(CSIF_C2S_IRQ_ENABLE + i*CSIF_C2S_IRQ_SIZE, 0xFFFFFFFF);
+ }
+ */
+
+ csif_uint32 expect_c2s_status[CSIF_ENUM_ALL_C2S_INT_NUM] = {0};
+ csif_uint32 expect_c2s_masked_status[CSIF_ENUM_ALL_C2S_INT_NUM] = {0};
+ volatile csif_uint32 c2s_status_read = 0;
+ volatile csif_uint32 c2s_masked_status_read = 0;
+ for(int i = CSIF_ENUM_C2S_N0; i< CSIF_ENUM_ALL_C2S_INT_NUM; i++)
+ {
+ for(int bit_i = 0; bit_i < CSIF_C2S_Interrupt_Num[i]; bit_i++)
+ {
+ expect_c2s_status[i] = expect_c2s_status[i] | (0x1 << bit_i);
+ expect_c2s_masked_status[i] = expect_c2s_masked_status[i] | (0x1 << bit_i);
+ CSIF_C2S_SWI_Set(i, bit_i);
+ c2s_status_read = CSIF_C2S_SWI_Read(i);
+ c2s_masked_status_read = CSIF_C2S_SWI_MASKED_Read(i);
+ if(c2s_status_read != expect_c2s_status[i]){
+ SSDVT_FAIL_MSG(c2s_status_read, 0xAAA00000 | (i << 8) | bit_i, test_case_index);
+ }
+ // NOTE!! not sure mcore state here!
+ /*
+ if(c2s_masked_status_read != expect_c2s_masked_status[i])
+ {
+ SSDVT_FAIL_MSG(c2s_masked_status_read, 0xAAA20000 | (i << 8) | bit_i, test_case_index);
+ }
+ */
+ }
+ }
+
+ // disable all c2s_IRQ
+ /*
+ for (int i=CSIF_ENUM_C2S_N0; i<CSIF_ENUM_ALL_C2S_INT_NUM; i++){
+ CSIF_REG_WRITE(CSIF_C2S_IRQ_ENABLE + i*CSIF_C2S_IRQ_SIZE, 0x0);
+ }
+ */
+}
+
+void CSIF_S2C_IRQ_ENABLE_test(void)
+{
+ csif_uint32 expect_s2c_enable_status[CSIF_ENUM_ALL_S2C_INT_NUM] = {0};
+ volatile csif_uint32 s2c_enable_status_read = 0;
+ for(int i = CSIF_ENUM_S2C_N0; i< CSIF_ENUM_ALL_S2C_INT_NUM; i++)
+ {
+ for(int bit_i = 0; bit_i < CSIF_S2C_Interrupt_Num[i]; bit_i++)
+ {
+ expect_s2c_enable_status[i] = expect_s2c_enable_status[i] | (0x1 << bit_i);
+ CSIF_S2C_SWI_Enable(i, bit_i);
+ s2c_enable_status_read = CSIF_S2C_SWI_Enable_Read(i);
+ if(s2c_enable_status_read != expect_s2c_enable_status[i])
+ {
+ SSDVT_FAIL_MSG(s2c_enable_status_read, 0xAAB00000 | (i << 8) | bit_i, test_case_index);
+ }
+ }
+ }
+ for(int i = CSIF_ENUM_S2C_N0; i< CSIF_ENUM_ALL_S2C_INT_NUM; i++)
+ {
+ for(int bit_i = 0; bit_i < CSIF_S2C_Interrupt_Num[i]; bit_i++)
+ {
+ expect_s2c_enable_status[i] = expect_s2c_enable_status[i] & ~(0x1 << bit_i);
+ CSIF_S2C_SWI_Disable(i, bit_i);
+ s2c_enable_status_read = CSIF_S2C_SWI_Enable_Read(i);
+ if(s2c_enable_status_read != expect_s2c_enable_status[i])
+ {
+ SSDVT_FAIL_MSG(s2c_enable_status_read, 0xAAB10000 | (i << 8) | bit_i, test_case_index);
+ }
+ }
+ }
+ return;
+}
+
+void CSIF_C2S_IRQ_OVFL_test(void)
+{
+ volatile csif_uint32 irq_ovfl_read = 0;
+ //disable L1 error type (27 error, 2018/3/21)
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0);
+
+ for(int i = CSIF_ENUM_C2S_N0; i< CSIF_ENUM_ALL_C2S_INT_NUM; i++)
+ {
+ for(int bit_i = 0; bit_i < CSIF_C2S_Interrupt_Num[i]; bit_i++)
+ {
+ //CSIF_C2S_SWI_Set(i, bit_i);// c2s_irq may be set due to S2C_Set test, but still set twice first
+ CSIF_C2S_SWI_Set(i, bit_i);
+ irq_ovfl_read = CSIF_C2S_Overflow_Read(i);
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ if(bit_i < 16) // bit 0~15 irq_ovfl_allowed is False
+#else
+ if(bit_i < 32) // bit 0~31 irq_ovfl_allowed is False
+#endif
+ {
+ if((irq_ovfl_read & (0x1 << bit_i)) != 0)
+ {
+ SSDVT_FAIL_MSG(irq_ovfl_read, 0xAADF0000 | (i << 8) | bit_i, test_case_index);
+ }
+ }
+ else
+ {
+ if((irq_ovfl_read & (0x1 << bit_i)) == 0)
+ {
+ SSDVT_FAIL_MSG(irq_ovfl_read, 0xAAD00000 | (i << 8) | bit_i, test_case_index);
+ }
+ }
+ CSIF_C2S_Overflow_Clear(i, bit_i);
+ irq_ovfl_read = CSIF_C2S_Overflow_Read(i);
+ if((irq_ovfl_read & (0x1 << bit_i)) != 0)
+ {
+ SSDVT_FAIL_MSG(irq_ovfl_read, 0xAAD10000 | (i << 8) | bit_i, test_case_index);
+ }
+ }
+ }
+
+ //enable L1 error type (27 error, 2018/3/21)
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, CSIF_L1_ERROR_MASK);
+
+ return;
+}
+
+void CSIF_MPU_SET_test(void)
+{
+ volatile csif_uint32 read_mpu_start = 0;
+ volatile csif_uint32 read_mpu_range = 0;
+ volatile csif_uint32 read_mpu_type = 0;
+
+ csif_uint32 set_start_value = 0;
+ csif_uint32 set_range_value = 0;
+
+ for(int i = CSIF_DSP_MPU0; i < CSIF_MPU_TOTAL_NUM; i++)
+ {
+ for(int t = CSIF_MPU_READ; t < CSIF_MPU_TOTAL_TYPE; t++)
+ {
+ set_start_value = CSIF_DSM_BASE + 0x8;
+ set_range_value = 0x4000-0x8;
+
+ CSIF_MPU_Set(i, set_start_value, set_range_value, t);
+
+ CSIF_REG_READ(CSIF_MPU_START_ADDR + i*CSIF_MPU_SIZE, read_mpu_start);
+ CSIF_REG_READ(CSIF_MPU_RANGE + i*CSIF_MPU_SIZE, read_mpu_range);
+
+ read_mpu_type = (read_mpu_range & CSIF_MPU_TYPE_M) >> CSIF_MPU_TYPE_P;
+ read_mpu_range = (read_mpu_range & CSIF_MPU_RANGE_M) >> CSIF_MPU_RANGE_P;
+ if(read_mpu_start != (set_start_value & CSIF_MPU_START_M) )
+ {
+ SSDVT_FAIL_MSG(read_mpu_start, 0xAAE00000 | (i << 8) | t, test_case_index);
+ }
+ if(read_mpu_range != set_range_value)
+ {
+ SSDVT_FAIL_MSG(read_mpu_range, 0xAAE10000 | (i << 8) | t, test_case_index);
+ }
+ if(read_mpu_type != t)
+ {
+ SSDVT_FAIL_MSG(read_mpu_type, 0xAAE20000 | (i << 8) | t, test_case_index);
+ }
+
+ set_start_value = 0x0;
+ set_range_value = 0x0;
+
+ CSIF_MPU_Set(i, set_start_value, set_range_value, t);
+
+ CSIF_REG_READ(CSIF_MPU_START_ADDR + i*CSIF_MPU_SIZE, read_mpu_start);
+ CSIF_REG_READ(CSIF_MPU_RANGE + i*CSIF_MPU_SIZE, read_mpu_range);
+
+ read_mpu_type = (read_mpu_range & CSIF_MPU_TYPE_M) >> CSIF_MPU_TYPE_P;
+ read_mpu_range = (read_mpu_range & CSIF_MPU_RANGE_M) >> CSIF_MPU_RANGE_P;
+ if(read_mpu_start != (set_start_value & CSIF_MPU_START_M) )
+ {
+ SSDVT_FAIL_MSG(read_mpu_start, 0xAAEA0000 | (i << 8) | t, test_case_index);
+ }
+ if(read_mpu_range != set_range_value)
+ {
+ SSDVT_FAIL_MSG(read_mpu_range, 0xAAEB0000 | (i << 8) | t, test_case_index);
+ }
+ if(read_mpu_type != t)
+ {
+ SSDVT_FAIL_MSG(read_mpu_type, 0xAAEC0000 | (i << 8) | t, test_case_index);
+ }
+ }
+ }
+ return;
+}
+
+void CSIF_MAILBOX_C2S_SEND_RECV_test(void)
+{
+ volatile CSIF_MAILBOX_STATUS_t mailbox_status_read;
+ volatile csif_uint32 mailbox_max_usage_read;
+
+ volatile csif_uint32 previous_mailbox_r_idx_read;
+ volatile csif_uint32 previous_mailbox_w_idx_read;
+ volatile csif_uint32 previous_mailbox_mail_num_read;
+ volatile csif_uint32 previous_mailbox_max_usage_read;
+
+ volatile csif_uint32 read_mail = 0;
+
+ csif_uint32 mailboxMask = 0;
+
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ for(int i = CSIF_MAILBOX_C2S_SS_TEST_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#else
+ for(int i = CSIF_MAILBOX_C2S_C2S_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#endif
+ {
+ mailbox_status_read = CSIF_MAILBOX_C2S_Status_Read(i);
+ mailbox_max_usage_read = CSIF_MAILBOX_C2S_Max_FIFO_Usage_Read(i);
+ if(mailbox_status_read.r_idx != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.r_idx, 0xAAF00000 | (i << 8) | 0xFF , test_case_index);
+ }
+ if(mailbox_status_read.w_idx != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.w_idx, 0xAAF10000 | (i << 8) | 0xFF, test_case_index);
+ }
+ if(mailbox_status_read.mail_num != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.mail_num, 0xAAF20000 | (i << 8) | 0xFF, test_case_index);
+ }
+ if(mailbox_max_usage_read != 0){
+ SSDVT_FAIL_MSG(mailbox_max_usage_read, 0xAAF30000 | (i << 8) | 0xFF, test_case_index);
+ }
+ previous_mailbox_r_idx_read = mailbox_status_read.r_idx;
+ previous_mailbox_w_idx_read = mailbox_status_read.w_idx;
+ previous_mailbox_mail_num_read = mailbox_status_read.mail_num;
+ previous_mailbox_max_usage_read = mailbox_max_usage_read;
+
+ if(csif_mailbox_entry_num_table[i] == 256){
+ mailboxMask = MAILBOX_256_WRAP_MASK;
+ }else if(csif_mailbox_entry_num_table[i] == 64){
+ mailboxMask = MAILBOX_64_WRAP_MASK;
+ }
+ // C2S mailbox send test
+ for(int m = 0; m < csif_mailbox_entry_num_table[i]; m++)
+ {
+ CSIF_MAILBOX_C2S_Send(i, m);
+ mailbox_status_read = CSIF_MAILBOX_C2S_Status_Read(i);
+ mailbox_max_usage_read = CSIF_MAILBOX_C2S_Max_FIFO_Usage_Read(i);
+
+ if(mailbox_status_read.r_idx != previous_mailbox_r_idx_read){
+ SSDVT_FAIL_MSG(mailbox_status_read.r_idx, 0xAAFA0000 | (i << 8) | m, test_case_index);
+ }
+
+ if(mailbox_status_read.w_idx != ((previous_mailbox_w_idx_read + 1) & mailboxMask)){
+ SSDVT_FAIL_MSG(mailbox_status_read.w_idx, 0xAAFB0000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_status_read.mail_num != previous_mailbox_mail_num_read + 1){
+ SSDVT_FAIL_MSG(mailbox_status_read.mail_num, 0xAAFC0000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_max_usage_read != previous_mailbox_max_usage_read + 1){
+ SSDVT_FAIL_MSG(mailbox_max_usage_read, 0xAAF40000 | (i << 8) | m, test_case_index);
+ }
+
+ previous_mailbox_r_idx_read = mailbox_status_read.r_idx;
+ previous_mailbox_w_idx_read = mailbox_status_read.w_idx;
+ previous_mailbox_mail_num_read = mailbox_status_read.mail_num;
+ previous_mailbox_max_usage_read = mailbox_max_usage_read;
+ }
+
+
+ // C2S mailbox recv test
+ for(int m = 0; m < csif_mailbox_entry_num_table[i]; m++)
+ {
+ read_mail = CSIF_MAILBOX_C2S_Read(i);
+ mailbox_status_read = CSIF_MAILBOX_C2S_Status_Read(i);
+ mailbox_max_usage_read = CSIF_MAILBOX_C2S_Max_FIFO_Usage_Read(i);
+
+ if(read_mail != m ){
+ SSDVT_FAIL_MSG(read_mail, 0xAAF60000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_status_read.r_idx != ((previous_mailbox_r_idx_read + 1) & mailboxMask )){
+ SSDVT_FAIL_MSG(mailbox_status_read.r_idx, 0xAAF0000 | (i << 8) | m, test_case_index);
+ }
+
+ if(mailbox_status_read.w_idx != ((previous_mailbox_w_idx_read) & mailboxMask)){
+ SSDVT_FAIL_MSG(mailbox_status_read.w_idx, 0xAAFE0000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_status_read.mail_num != previous_mailbox_mail_num_read - 1){
+ SSDVT_FAIL_MSG(mailbox_status_read.mail_num, 0xAAFF0000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_max_usage_read != previous_mailbox_max_usage_read ){
+ SSDVT_FAIL_MSG(mailbox_max_usage_read, 0xAAF50000 | (i << 8) | m, test_case_index);
+ }
+
+ previous_mailbox_r_idx_read = mailbox_status_read.r_idx;
+ previous_mailbox_w_idx_read = mailbox_status_read.w_idx;
+ previous_mailbox_mail_num_read = mailbox_status_read.mail_num;
+ previous_mailbox_max_usage_read = mailbox_max_usage_read;
+ }
+ }
+ return;
+}
+
+void CSIF_MAILBOX_S2C_RECV_test(void)
+{
+ volatile CSIF_MAILBOX_STATUS_t mailbox_status_read;
+ volatile csif_uint32 mailbox_max_usage_read;
+
+ volatile csif_uint32 read_mail = 0;
+
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ for(int i = CSIF_MAILBOX_S2C_SS_TEST_ID3; i < CSIF_MAILBOX_S2C_LAST_ID; i++)
+#else
+ for(int i = CSIF_MAILBOX_S2C_S2C_ID0; i < CSIF_MAILBOX_S2C_LAST_ID; i++)
+#endif
+ {
+ mailbox_status_read = CSIF_MAILBOX_S2C_Status_Read(i);
+ mailbox_max_usage_read = CSIF_MAILBOX_S2C_Max_FIFO_Usage_Read(i);
+ if(mailbox_status_read.r_idx != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.r_idx, 0xAB000000 | (i << 8) | 0xFF , test_case_index);
+ }
+ if(mailbox_status_read.w_idx != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.w_idx, 0xAB010000 | (i << 8) | 0xFF, test_case_index);
+ }
+ if(mailbox_status_read.mail_num != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.mail_num, 0xAB020000 | (i << 8) | 0xFF, test_case_index);
+ }
+ if(mailbox_max_usage_read != 0){
+ SSDVT_FAIL_MSG(mailbox_max_usage_read, 0xAB030000 | (i << 8) | 0xFF, test_case_index);
+ }
+
+ for(int m = 0; m < 5; m++)
+ {
+ read_mail = CSIF_MAILBOX_S2C_Read(i);
+ mailbox_status_read = CSIF_MAILBOX_S2C_Status_Read(i);
+ mailbox_max_usage_read = CSIF_MAILBOX_S2C_Max_FIFO_Usage_Read(i);
+ /*
+ printf("i = %d, m = %d; w_idx = %d, r_idx = %d, mailnum = %d, max = %d, read_mail = %d\n", i, m,
+ mailbox_status_read.w_idx, mailbox_status_read.r_idx, mailbox_status_read.mail_num,
+ mailbox_max_usage_read, read_mail );
+ ` */
+ if(read_mail != CSIF_MAILBOX_EMPTY_VALUE){
+ SSDVT_FAIL_MSG(read_mail, 0xAB120000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_status_read.r_idx != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.r_idx, 0xAB130000 | (i << 8) | m , test_case_index);
+ }
+ if(mailbox_status_read.w_idx != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.w_idx, 0xAB140000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_status_read.mail_num != 0){
+ SSDVT_FAIL_MSG(mailbox_status_read.mail_num, 0xAB150000 | (i << 8) | m, test_case_index);
+ }
+ if(mailbox_max_usage_read != 0){
+ SSDVT_FAIL_MSG(mailbox_max_usage_read, 0xAB160000 | (i << 8) | m, test_case_index);
+ }
+ }
+ }
+ return;
+}
+
+void CSIF_OLPDET_test(void)
+{
+ csif_uint32 set_size = 0;
+ csif_uint32 clr_size = 0;
+ volatile csif_uint32 read_inuse_mem_size = 0;
+ csif_uint32 expect_mem_size = 0;
+
+ // set size = 8
+ set_size = 8;
+ for(int i = 0; i < CSIF_DSM_SIZE/set_size; i++)
+ {
+ CSIF_OLPDET_Set(CSIF_DSM_BASE + set_size*i, set_size);
+ expect_mem_size = expect_mem_size + set_size;
+ read_inuse_mem_size = CSIF_Total_Inuse_Mem_Size();
+ if(read_inuse_mem_size != expect_mem_size)
+ {
+ SSDVT_FAIL_MSG(read_inuse_mem_size, 0xAC000000 | (i << 8) | set_size, expect_mem_size);
+ }
+ }
+ // clr by size = 1024
+ clr_size = 1024;
+ for(int i = 0; i < CSIF_DSM_SIZE/clr_size; i++)
+ {
+ CSIF_OLPDET_Clr(CSIF_DSM_BASE + clr_size*i, clr_size);
+ expect_mem_size = expect_mem_size - clr_size;
+ read_inuse_mem_size = CSIF_Total_Inuse_Mem_Size();
+ if(read_inuse_mem_size != expect_mem_size)
+ {
+ SSDVT_FAIL_MSG(read_inuse_mem_size, 0xAC010000 | (i << 8) | clr_size, expect_mem_size);
+ }
+ }
+ // set size = 1024
+ set_size = 1024;
+ for(int i = 0; i < CSIF_DSM_SIZE/set_size; i++)
+ {
+ CSIF_OLPDET_Set(CSIF_DSM_BASE + set_size*i, set_size);
+ expect_mem_size = expect_mem_size + set_size;
+ read_inuse_mem_size = CSIF_Total_Inuse_Mem_Size();
+ if(read_inuse_mem_size != expect_mem_size)
+ {
+ SSDVT_FAIL_MSG(read_inuse_mem_size, 0xAC020000 | (i << 8) | set_size, expect_mem_size);
+ }
+ }
+ // clr by size = 8
+ clr_size = 8;
+ for(int i = 0; i < CSIF_DSM_SIZE/clr_size; i++)
+ {
+ CSIF_OLPDET_Clr(CSIF_DSM_BASE + clr_size*i, clr_size);
+ expect_mem_size = expect_mem_size - clr_size;
+ read_inuse_mem_size = CSIF_Total_Inuse_Mem_Size();
+ if(read_inuse_mem_size != expect_mem_size)
+ {
+ SSDVT_FAIL_MSG(read_inuse_mem_size, 0xAC030000 | (i << 8) | clr_size, expect_mem_size);
+ }
+ }
+ return;
+}
+
+void CSIF_IDLE_IRQ_ENABLE_test(void)
+{
+ //volatile csif_uint32 idle_read;
+ volatile csif_uint32 idle_enable_read = 0;
+ volatile csif_uint32 previous_idle_enable = 0;
+
+ // disable S2C_IRQ ENABLE
+ for (int i=CSIF_ENUM_S2C_N0; i<CSIF_ENUM_ALL_S2C_INT_NUM; i++){
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + i*CSIF_S2C_IRQ_SIZE, 0x0);
+ }
+ //disable CSIF s2c_WFI_enable mask (write 10 bits on each enable mask, 4 th per core and 1 AND/OR bit per core)
+ for (int i=0; i<CSIF_S2C_IDLE_IRQ_NUM; i++){
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + i*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+ }
+
+ //idle_read = CSIF_CORE_IDLE_Read();
+ // NOTE!!! not sure what's mcore state here!
+ /*
+ if((idle_read & (0xF << (4*THIS_MCORE_ID))) != 0x0){
+ SSDVT_FAIL_MSG(idle_read, 0xAE000000 | THIS_MCORE_ID , test_case_index);
+ }
+ */
+
+ for(int i = 0; i < CSIF_S2C_IDLE_IRQ_NUM; i++)
+ {
+ idle_enable_read = CSIF_IDLE_ENABLE_Read(i);
+ previous_idle_enable = idle_enable_read;
+ if(idle_enable_read != 0x0){
+ SSDVT_FAIL_MSG(idle_enable_read, 0xAE010000 | i<<8 , test_case_index);
+ }
+ for(int bit_i = 0; bit_i < 10; bit_i++)
+ {
+ CSIF_IDLE_ENABLE_Set(i, 0x1 << bit_i);
+ idle_enable_read = CSIF_IDLE_ENABLE_Read(i);
+ if(idle_enable_read != (previous_idle_enable | (0x1 << bit_i)))
+ {
+ SSDVT_FAIL_MSG(idle_enable_read, 0xAE020000 | i<<8 | bit_i , test_case_index);
+ }
+ previous_idle_enable = idle_enable_read;
+ }
+ }
+
+ for(int i = 0; i < CSIF_S2C_IDLE_IRQ_NUM; i++)
+ {
+ idle_enable_read = CSIF_IDLE_ENABLE_Read(i);
+ previous_idle_enable = idle_enable_read;
+ if(idle_enable_read != 0x3FF){
+ SSDVT_FAIL_MSG(idle_enable_read, 0xAE030000 | i<<8 , test_case_index);
+ }
+ for(int bit_i = 0; bit_i < 10; bit_i++)
+ {
+ CSIF_IDLE_ENABLE_Clr(i, 0x1 << bit_i);
+ idle_enable_read = CSIF_IDLE_ENABLE_Read(i);
+ if(idle_enable_read != (0x3FF & (previous_idle_enable & ~(0x1 << bit_i))))
+ {
+ SSDVT_FAIL_MSG(idle_enable_read, 0xAE040000 | i<<8 | bit_i , test_case_index);
+ }
+ previous_idle_enable = idle_enable_read;
+ }
+ }
+
+ //open mask of CSIF s2c_WFI_enable mask (write 10 bits on each enable mask, 4 th per core and 1 AND/OR bit per core)
+ //WFI_irq0
+ //CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_SET + 0*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+ //WFI_irq1
+ //CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_SET + 1*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+
+ return;
+}
+
+kal_uint32 olpdet_driver_expect_mum_arr[OLPDET_MUM_BIT_NUM/32] = {0};
+kal_uint32 olpdet_driver_dump_mum_arr[OLPDET_MUM_BIT_NUM/32] = {0};
+
+void CSIF_OLPDET_MULTIPLE_TEST(){
+ CSIF_OLPDET_CONFIG_t olpdet_set_array[MULTIPLE_REG_TEST_NUM];
+ CSIF_OLPDET_CONFIG_t* olpdet_set_array_ptr;
+ kal_uint32 mum_idx = 0;
+ kal_uint32 mum_content = 0;
+
+ // OLPDET_Set
+ for(int i = 0; i<MULTIPLE_REG_TEST_NUM; i++ ){
+ // prepare API argument
+ olpdet_set_array[i].addr = CSIF_DSM_BASE + MULTIPLE_REG_TEST_OFFSET[i];
+ olpdet_set_array[i].size = MULTIPLE_REG_TEST_SIZE[i];
+ }
+ olpdet_set_array_ptr = &olpdet_set_array[0];
+ CSIF_OLPDET_Multiple_Set(MULTIPLE_REG_TEST_NUM, olpdet_set_array_ptr);
+
+ /* dump OLPDET to check */
+ //1: offset 0, + size: 0x400(1024)
+ olpdet_driver_expect_mum_arr[0] = 0xFFFFFFFF; //0 ~ 31
+ olpdet_driver_expect_mum_arr[1] = 0xFFFFFFFF; //32 ~ 63
+ olpdet_driver_expect_mum_arr[2] = 0xFFFFFFFF; //64 ~ 95
+ olpdet_driver_expect_mum_arr[3] = 0xFFFFFFFF; //96 ~ 127
+ //2: offset 0x800, + size: 0x100
+ olpdet_driver_expect_mum_arr[8] = 0xFFFFFFFF;
+ //3: offset 0x1000, + size: 0x8
+ olpdet_driver_expect_mum_arr[16] = 0x00000001;
+ //4: offset 0x2000, + size: 0x200
+ olpdet_driver_expect_mum_arr[32] = 0xFFFFFFFF;
+ olpdet_driver_expect_mum_arr[33] = 0xFFFFFFFF;
+ //5: offset 0x3FE0, + size: 0x20
+ olpdet_driver_expect_mum_arr[63] = 0xF0000000;
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX, mum_idx);
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM, mum_content);
+ olpdet_driver_dump_mum_arr[mum_idx] = mum_content;
+ }
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ test_case_index = test_case_index | (dump_i<<4);
+ if(olpdet_driver_dump_mum_arr[dump_i] != olpdet_driver_expect_mum_arr[dump_i]){
+ SSDVT_FAIL_MSG(olpdet_driver_dump_mum_arr[dump_i], olpdet_driver_expect_mum_arr[dump_i], dump_i);
+ }
+ }
+ // clear error and reset debug mum idx
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+ /* end of dump OLPDET to check */
+
+ // OLPDET_Clr 1
+ CSIF_OLPDET_CONFIG_t olpdet_clr_array1[MULTIPLE_REG_TEST_NUM_SUB_1];
+ CSIF_OLPDET_CONFIG_t* olpdet_clr_array_ptr1;
+ for(int i = 0; i<MULTIPLE_REG_TEST_NUM_SUB_1; i++ ){
+ // prepare API argument
+ olpdet_clr_array1[i].addr = CSIF_DSM_BASE + MULTIPLE_REG_TEST_OFFSET[i];
+ olpdet_clr_array1[i].size = MULTIPLE_REG_TEST_SIZE[i];
+ }
+ olpdet_clr_array_ptr1 = &olpdet_clr_array1[0];
+ CSIF_OLPDET_Multiple_Clr(MULTIPLE_REG_TEST_NUM_SUB_1, olpdet_clr_array_ptr1);
+
+ /* dump OLPDET to check */
+ //1: offset 0, + size: 0x400(1024)
+ olpdet_driver_expect_mum_arr[0] = 0x0; //0 ~ 31
+ olpdet_driver_expect_mum_arr[1] = 0x0; //32 ~ 63
+ olpdet_driver_expect_mum_arr[2] = 0x0; //64 ~ 95
+ olpdet_driver_expect_mum_arr[3] = 0x0; //96 ~ 127
+ //2: offset 0x800, + size: 0x100
+ olpdet_driver_expect_mum_arr[8] = 0x0;
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX, mum_idx);
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM, mum_content);
+ olpdet_driver_dump_mum_arr[mum_idx] = mum_content;
+ }
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ test_case_index = test_case_index | (dump_i<<4);
+ if(olpdet_driver_dump_mum_arr[dump_i] != olpdet_driver_expect_mum_arr[dump_i]){
+ SSDVT_FAIL_MSG(olpdet_driver_dump_mum_arr[dump_i], olpdet_driver_expect_mum_arr[dump_i], dump_i);
+ }
+ }
+ // clear error and reset debug mum idx
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+ /* end of dump OLPDET to check */
+
+ // OLPDET_Clr 2
+ CSIF_OLPDET_CONFIG_t olpdet_clr_array2[MULTIPLE_REG_TEST_NUM_SUB_2];
+ CSIF_OLPDET_CONFIG_t* olpdet_clr_array_ptr2;
+ for(int i = 0; i<MULTIPLE_REG_TEST_NUM_SUB_2; i++ ){
+ // prepare API argument
+ olpdet_clr_array2[i].addr = CSIF_DSM_BASE + MULTIPLE_REG_TEST_OFFSET[i+MULTIPLE_REG_TEST_NUM_SUB_1];
+ olpdet_clr_array2[i].size = MULTIPLE_REG_TEST_SIZE[i+MULTIPLE_REG_TEST_NUM_SUB_1];
+ }
+ olpdet_clr_array_ptr2 = &olpdet_clr_array2[0];
+ CSIF_OLPDET_Multiple_Clr(MULTIPLE_REG_TEST_NUM_SUB_2, olpdet_clr_array_ptr2);
+
+ /* dump OLPDET to check */
+ //3: offset 0x1000, + size: 0x8
+ olpdet_driver_expect_mum_arr[16] = 0x0;
+ //4: offset 0x2000, + size: 0x200
+ olpdet_driver_expect_mum_arr[32] = 0x0;
+ olpdet_driver_expect_mum_arr[33] = 0x0;
+ //5: offset 0x3FE0, + size: 0x20
+ olpdet_driver_expect_mum_arr[63] = 0x0;
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM_IDX, mum_idx);
+ CSIF_REG_READ(CSIF_OLPDET_DEBUG_READ_MUM, mum_content);
+ olpdet_driver_dump_mum_arr[mum_idx] = mum_content;
+ }
+
+ for(kal_uint32 dump_i = 0; dump_i < OLPDET_MUM_BIT_NUM/32; dump_i++)
+ {
+ test_case_index = test_case_index | (dump_i<<4);
+ if(olpdet_driver_dump_mum_arr[dump_i] != olpdet_driver_expect_mum_arr[dump_i]){
+ SSDVT_FAIL_MSG(olpdet_driver_dump_mum_arr[dump_i], olpdet_driver_expect_mum_arr[dump_i], dump_i);
+ }
+ }
+ // clear error and reset debug mum idx
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+ /* end of dump OLPDET to check */
+}
+
+csif_uint32 mail_golden_array[CSIF_MAILBOX_C2S_LAST_ID][MULTIPLE_MAIL_TEST_NUM] = {{0}};
+void CSIF_MAILBOX_MULTIPLE_TEST()
+{
+ csif_uint32 shift_i = 0;
+ csif_uint32 base_i = 0;
+ csif_uint32 total_mail_length = 0;
+ csif_uint32 mail_read_idx = 0;
+ volatile csif_uint32 read_mail = 0;
+ volatile CSIF_MAILBOX_STATUS_t mailbox_status_read;
+
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ CSIF_MAIL_INFO_t mail_info_array[(CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_SS_TEST_ID0)*MULTIPLE_MAIL_TEST_NUM]= {0};
+ total_mail_length = (CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_SS_TEST_ID0)*MULTIPLE_MAIL_TEST_NUM;
+ for(int i = CSIF_MAILBOX_C2S_SS_TEST_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#else
+ CSIF_MAIL_INFO_t mail_info_array[(CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_C2S_ID0)*MULTIPLE_MAIL_TEST_NUM]= {0};
+ total_mail_length = (CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_C2S_ID0)*MULTIPLE_MAIL_TEST_NUM;
+ for(int i = CSIF_MAILBOX_C2S_C2S_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#endif
+ {
+ for(int mail_idx = 0; mail_idx < MULTIPLE_MAIL_TEST_NUM; mail_idx++)
+ {
+ mail_info_array[(shift_i*MULTIPLE_MAIL_TEST_NUM + mail_idx)].mail = MAILBOX_TEST_PREFIX_PATTERN | (i << 12) | (mail_idx);
+ mail_info_array[(shift_i*MULTIPLE_MAIL_TEST_NUM + mail_idx)].mID = i;
+ mail_golden_array[i][mail_idx] = MAILBOX_TEST_PREFIX_PATTERN | (i << 12) | (mail_idx);
+ }
+ shift_i++;
+ }
+ CSIF_MAILBOX_C2S_Multiple_Send(total_mail_length, &mail_info_array[0]);
+
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ for(int i = CSIF_MAILBOX_C2S_SS_TEST_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#else
+ for(int i = CSIF_MAILBOX_C2S_C2S_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#endif
+ {
+ mailbox_status_read = CSIF_MAILBOX_C2S_Status_Read(i);
+ if(mailbox_status_read.mail_num != MULTIPLE_MAIL_TEST_NUM){
+ SSDVT_FAIL_MSG(mailbox_status_read.mail_num, MULTIPLE_MAIL_TEST_NUM, i);
+ }
+ mail_read_idx = 0;
+ read_mail = CSIF_MAILBOX_C2S_Read(i);
+ while(read_mail != CSIF_MAILBOX_EMPTY_VALUE)
+ {
+ if(read_mail != mail_golden_array[i][mail_read_idx]){
+ SSDVT_FAIL_MSG(read_mail, mail_read_idx, i);
+ }
+ read_mail = CSIF_MAILBOX_C2S_Read(i);
+ mail_read_idx++;
+ }
+ }
+}
+
+csif_uint32 irq_golden_array[CSIF_ENUM_ALL_C2S_INT_NUM] = {0};
+void CSIF_MAILBOX_MULTIPLE_IRQ_MULTIPLE_TEST()
+{
+ csif_uint32 shift_i = 0;
+ csif_uint32 base_i = 0;
+ csif_uint32 total_mail_length = 0;
+ csif_uint32 mail_read_idx = 0;
+ volatile csif_uint32 read_mail = 0;
+ volatile CSIF_MAILBOX_STATUS_t mailbox_status_read;
+
+// Mailbox multiple setting
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ CSIF_MAIL_INFO_t mail_info_array[(CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_SS_TEST_ID0)*MULTIPLE_MAIL_TEST_NUM]= {0};
+ total_mail_length = (CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_SS_TEST_ID0)*MULTIPLE_MAIL_TEST_NUM;
+ for(int i = CSIF_MAILBOX_C2S_SS_TEST_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#else
+ CSIF_MAIL_INFO_t mail_info_array[(CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_C2S_ID0)*MULTIPLE_MAIL_TEST_NUM]= {0};
+ total_mail_length = (CSIF_MAILBOX_C2S_LAST_ID - CSIF_MAILBOX_C2S_C2S_ID0)*MULTIPLE_MAIL_TEST_NUM;
+ for(int i = CSIF_MAILBOX_C2S_C2S_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#endif
+ {
+ for(int mail_idx = 0; mail_idx < MULTIPLE_MAIL_TEST_NUM; mail_idx++)
+ {
+ mail_info_array[(shift_i*MULTIPLE_MAIL_TEST_NUM + mail_idx)].mail = MAILBOX_TEST_PREFIX_PATTERN | (i << 12) | (mail_idx*2);
+ mail_info_array[(shift_i*MULTIPLE_MAIL_TEST_NUM + mail_idx)].mID = i;
+ mail_golden_array[i][mail_idx] = MAILBOX_TEST_PREFIX_PATTERN | (i << 12) | (mail_idx*2);
+ }
+ shift_i++;
+ }
+
+// IRQ multiple setting
+ csif_uint32 total_irq_length = 0;
+ csif_uint32 irq_ovfl_read = 0;
+ shift_i = 0;
+
+ //disable L1 error type (27 error, 2018/3/21)
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0); // For IRQ ovfl
+
+ CSIF_IRQ_INFO_t irq_info_array[(CSIF_ENUM_ALL_C2S_INT_NUM - CSIF_ENUM_C2S_N0)*MULTIPLE_IRQ_TEST_NUM]= {0};
+ total_irq_length = (CSIF_ENUM_ALL_C2S_INT_NUM - CSIF_ENUM_C2S_N0)*MULTIPLE_IRQ_TEST_NUM;
+
+ for(int i = CSIF_ENUM_C2S_N0; i< CSIF_ENUM_ALL_C2S_INT_NUM; i++)
+ {
+ for(int bit_i = 0; bit_i < MULTIPLE_IRQ_TEST_NUM; bit_i++)
+ {
+ irq_golden_array[i] = irq_golden_array[i] | (0x1 << (i + bit_i));
+ irq_info_array[(shift_i*MULTIPLE_IRQ_TEST_NUM+bit_i)].nID = i;
+ irq_info_array[(shift_i*MULTIPLE_IRQ_TEST_NUM+bit_i)].code = i + bit_i;
+ }
+ shift_i++;
+ }
+// Trigger API
+ CSIF_MAILBOX_C2S_Multiple_Send_C2S_SWI_Multiple_Set(total_mail_length, &mail_info_array[0], total_irq_length, &irq_info_array[0]);
+
+ // Check mail box multiple set
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ for(int i = CSIF_MAILBOX_C2S_SS_TEST_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#else
+ for(int i = CSIF_MAILBOX_C2S_C2S_ID0; i < CSIF_MAILBOX_C2S_LAST_ID; i++)
+#endif
+ {
+ mailbox_status_read = CSIF_MAILBOX_C2S_Status_Read(i);
+ if(mailbox_status_read.mail_num != MULTIPLE_MAIL_TEST_NUM){
+ SSDVT_FAIL_MSG(mailbox_status_read.mail_num, MULTIPLE_MAIL_TEST_NUM, i);
+ }
+ mail_read_idx = 0;
+ read_mail = CSIF_MAILBOX_C2S_Read(i);
+ while(read_mail != CSIF_MAILBOX_EMPTY_VALUE)
+ {
+ if(read_mail != mail_golden_array[i][mail_read_idx]){
+ SSDVT_FAIL_MSG(read_mail, mail_read_idx, i);
+ }
+ read_mail = CSIF_MAILBOX_C2S_Read(i);
+ mail_read_idx++;
+ }
+ }
+
+// Check IRQ multiple set
+ // ALL C2S bit had been set by CSIF_C2S_IRQ_SET_test();
+ // so the bit we trigger in this test should be overflow case (based on irq_ovfl_allowed attribute in config file)
+ for(int i = CSIF_ENUM_C2S_N0; i< CSIF_ENUM_ALL_C2S_INT_NUM; i++)
+ {
+ for(int bit_i = 0; bit_i < MULTIPLE_IRQ_TEST_NUM; bit_i++)
+ {
+ irq_ovfl_read = CSIF_C2S_Overflow_Read(i);
+
+ if((irq_golden_array[i] & (0x1 << bit_i)) == 0) // this bit didn't been triggered
+ {
+ if(irq_ovfl_read & (0x1 << bit_i)){
+ SSDVT_FAIL_MSG(irq_ovfl_read, i, bit_i);
+ }
+
+ }else // this bit had been triggered
+ {
+#if defined(__CSIF_DRV_TEST__) && defined(__MAUI_BASIC__)
+ if(bit_i < 16) // bit 0~15 irq_ovfl_allowed is False
+#else
+ if(bit_i < 32) // bit 0~31 irq_ovfl_allowed is False
+#endif
+ {
+ if((irq_ovfl_read & (0x1 << bit_i)) != 0)
+ {
+ SSDVT_FAIL_MSG(irq_ovfl_read, i, bit_i);
+ }
+ }else
+ {
+ if((irq_ovfl_read & (0x1 << bit_i)) == 0)
+ {
+ SSDVT_FAIL_MSG(irq_ovfl_read, i, bit_i);
+ }
+ }
+ }
+ CSIF_C2S_Overflow_Clear(i, bit_i);
+ irq_ovfl_read = CSIF_C2S_Overflow_Read(i);
+ if((irq_ovfl_read & (0x1 << bit_i)) != 0)
+ {
+ SSDVT_FAIL_MSG(irq_ovfl_read, i, bit_i);
+ }
+ }
+ }
+
+ //enable L1 error type (27 error, 2018/3/21)
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, CSIF_L1_ERROR_MASK);
+}
+#endif // __CSIF_DRV_TEST__
+
+#if defined(__CSIF_DRV_TEST__)
+void csif_driver_test()
+{
+ test_case_index = 0xDD970001;
+ CSIF_C2S_IRQ_SET_test();
+ test_case_index = 0xDD970002;
+ //CSIF_S2C_IRQ_ENABLE_test();
+ test_case_index = 0xDD970003;
+ CSIF_C2S_IRQ_OVFL_test();
+ test_case_index = 0xDD970004;
+ //CSIF_MPU_SET_test();
+ test_case_index = 0xDD970005;
+ CSIF_MAILBOX_C2S_SEND_RECV_test();
+ test_case_index = 0xDD970006;
+ CSIF_MAILBOX_S2C_RECV_test();
+ test_case_index = 0xDD970007;
+ CSIF_OLPDET_test();
+ test_case_index = 0xDD970008;
+ CSIF_IDLE_IRQ_ENABLE_test();
+ test_case_index = 0xDD970009;
+ CSIF_OLPDET_MULTIPLE_TEST();
+ test_case_index = 0xDD97000A;
+ CSIF_MAILBOX_MULTIPLE_TEST();
+ test_case_index = 0xDD97000B;
+ CSIF_MAILBOX_MULTIPLE_IRQ_MULTIPLE_TEST();
+ test_case_index = 0xDD97000C;
+}
+#endif
+
+#if defined(__SSDVT_CSIF_TEST__)
+void CSIF_SSDVT()
+{
+#if defined(__CSIF_DRV_TEST__)
+
+#if defined(__CSIF_DVT_OLPDET__)
+ csif_olpdet_dvt_test();
+#endif
+ csif_mem_test();
+ //csif_irq_ovfl_test();
+#if !defined(__CSIF_DVT_OLPDET__) && !defined(__CSIF_DVT_REG_RW__)
+ csif_driver_test();
+#endif
+
+#endif
+#if defined(__CSIF_CROSS_CORE_TEST__)
+#if defined(__CSIF_SW_IRQ_TEST__)
+ IRQ_HANDLER_TYPE = CSIF_IRQ_HANDLER_IRQ_TEST;
+ cross_interrupt_test();
+#endif
+#if defined(__CSIF_IDLE_IRQ_TEST__)
+ #if defined(__CSIF_CROSS_CORE_MCORE1_ONLY__)
+ THIS_MCORE_ID = 1;
+ #else
+ THIS_MCORE_ID = 0;
+ #endif
+ IRQ_HANDLER_TYPE = CSIF_IRQ_HANDLER_IDLE_IRQ_TEST;
+ cross_idle_irq_test();
+#endif
+#if defined(__CSIF_MAILBOX_TEST__)
+ IRQ_HANDLER_TYPE = CSIF_IRQ_HANDLER_MAILBOX_TEST;
+ cross_mailbox_test();
+#endif
+#endif
+
+ return;
+}
+#endif
diff --git a/mcu/driver/devdrv/csif/mt6297p/src/csif_profiling_main.c b/mcu/driver/devdrv/csif/mt6297p/src/csif_profiling_main.c
new file mode 100644
index 0000000..c1931d7
--- /dev/null
+++ b/mcu/driver/devdrv/csif/mt6297p/src/csif_profiling_main.c
@@ -0,0 +1,366 @@
+#include "csif_l1core_public_api.h"
+#include "drv_csif.h"
+#include "mips_ia_utils_public.h"
+
+#define OLPDET_START_ADDR CSIF_DSM_BASE
+#define OLPDET_SIZE 32
+#define MAILBOX_ID 0
+#define MAIL_CONTENT 0xFA970000
+
+#define RUN_ITERATION 4
+
+#define TESTING_MULTIPLE_MAIL_NUM 4
+#define MAX_TESTING_MULTIPLE_MAIL_NUM 8 // mapping to max aggregated mail num array below
+const kal_uint32 aggregate_mail_num_array[TESTING_MULTIPLE_MAIL_NUM] = {1, 2, 4, 8};
+
+typedef struct{
+ kal_uint32 start_time;
+ kal_uint32 end_time;
+ kal_uint32 latency;
+}CSIF_PROFILING_INFO;
+
+CSIF_PROFILING_INFO Profile_Multiple_Mail_Send_No_IRQ_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_Multiple_Mail_Send_One_IRQ_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_Multiple_Mail_Send_Multiple_IRQ_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_Multiple_Mail_Deallocate_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+
+kal_uint32 csif_c2s_IRQ_code[RUN_ITERATION] = {0}; // IRQ cannot be cleared by MCU side, need to use unique code for each case
+kal_uint32 Global_iteration_counter = 0;
+kal_uint32 IRQ_ID = 0;
+
+// ** for profile single API latency ** //
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+#if !defined(__CSIF_MULTIPLE_API__) // single API
+CSIF_PROFILING_INFO Profile_OLPDET_SET_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_OLPDET_CLR_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_MAILBOX_SEND_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_MAILBOX_RECV_array[RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_IRQ_SET_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+#else // multiple API
+CSIF_PROFILING_INFO Profile_OLPDET_MULTIPLE_SET_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_OLPDET_MULTIPLE_CLR_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_MAILBOX_MULTIPLE_SEND_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+CSIF_PROFILING_INFO Profile_MAILBOX_MULTIPLE_SEND_IRQ_SET_array[TESTING_MULTIPLE_MAIL_NUM][RUN_ITERATION];
+#endif // single/multiple API
+#endif // single api individual profile
+//////////////////////////////////////////
+
+
+void Multiple_Mail_Send_no_IRQ(){
+ kal_uint32 read_mail = 0;
+#if defined(__CSIF_MULTIPLE_API__)
+ kal_uint32 mail_length = 0;
+ kal_uint32 olpdet_length = 0;
+ CSIF_OLPDET_CONFIG_t olpdet_config_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+ CSIF_MAIL_INFO_t mail_info_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+#endif
+
+ for(kal_uint32 mail_num_idx = 0; mail_num_idx < TESTING_MULTIPLE_MAIL_NUM; mail_num_idx++){
+ /* start measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Send_No_IRQ_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+ //}
+#if !defined(__CSIF_MULTIPLE_API__)
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_SET_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_OLPDET_Set(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_SET_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_OLPDET_SET_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_OLPDET_SET_array[mail_num_idx][Global_iteration_counter].end_time - Profile_OLPDET_SET_array[mail_num_idx][Global_iteration_counter].start_time;
+ Profile_MAILBOX_SEND_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_MAILBOX_C2S_Send(MAILBOX_ID, (MAIL_CONTENT | mail_idx));
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_MAILBOX_SEND_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_MAILBOX_SEND_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_MAILBOX_SEND_array[mail_num_idx][Global_iteration_counter].end_time - Profile_MAILBOX_SEND_array[mail_num_idx][Global_iteration_counter].start_time;
+#endif
+ }
+#else // Multiple API
+ olpdet_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ olpdet_config_array[mail_idx].addr = CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx);
+ olpdet_config_array[mail_idx].size = OLPDET_SIZE;
+ }
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_MULTIPLE_SET_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_OLPDET_Multiple_Set(olpdet_length, &olpdet_config_array[0]);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_MULTIPLE_SET_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_OLPDET_MULTIPLE_SET_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_OLPDET_MULTIPLE_SET_array[mail_num_idx][Global_iteration_counter].end_time - Profile_OLPDET_MULTIPLE_SET_array[mail_num_idx][Global_iteration_counter].start_time;
+#endif
+ mail_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ mail_info_array[mail_idx].mID = MAILBOX_ID;
+ mail_info_array[mail_idx].mail = (MAIL_CONTENT | mail_idx);
+ }
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_MAILBOX_MULTIPLE_SEND_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_MAILBOX_C2S_Multiple_Send(mail_length, &mail_info_array[0]);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_MAILBOX_MULTIPLE_SEND_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_MAILBOX_MULTIPLE_SEND_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_MAILBOX_MULTIPLE_SEND_array[mail_num_idx][Global_iteration_counter].end_time - Profile_MAILBOX_MULTIPLE_SEND_array[mail_num_idx][Global_iteration_counter].start_time;
+#endif
+#endif // end of multiple API
+ /* end measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Send_No_IRQ_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_Multiple_Mail_Send_No_IRQ_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_Multiple_Mail_Send_No_IRQ_array[mail_num_idx][Global_iteration_counter].end_time - Profile_Multiple_Mail_Send_No_IRQ_array[mail_num_idx][Global_iteration_counter].start_time;
+ //}
+ /* Recover OLPDET and Mailbox */
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ CSIF_OLPDET_Clr(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+ }
+ do{
+ read_mail = CSIF_MAILBOX_C2S_Read(MAILBOX_ID);
+ }while(read_mail != CSIF_MAILBOX_EMPTY_VALUE);
+ /* Recover OLPDET and Mailbox */
+ }
+}
+
+void Multiple_Mail_Send_with_Single_IRQ(){
+ kal_uint32 read_mail = 0;
+#if defined(__CSIF_MULTIPLE_API__)
+ kal_uint32 mail_length = 0;
+ kal_uint32 olpdet_length = 0;
+ kal_uint32 irq_length = 0;
+ CSIF_OLPDET_CONFIG_t olpdet_config_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+ CSIF_MAIL_INFO_t mail_info_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+ CSIF_IRQ_INFO_t irq_info_array[1] = {0};
+#endif
+ for(kal_uint32 mail_num_idx = 0; mail_num_idx < TESTING_MULTIPLE_MAIL_NUM; mail_num_idx++){
+ /* start measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Send_One_IRQ_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+ //}
+#if !defined(__CSIF_MULTIPLE_API__)
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ CSIF_OLPDET_Set(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+ CSIF_MAILBOX_C2S_Send(MAILBOX_ID, (MAIL_CONTENT | mail_idx));
+
+ }
+
+ CSIF_C2S_SWI_Set(IRQ_ID, csif_c2s_IRQ_code[IRQ_ID]);
+
+#else // Multiple API
+ olpdet_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ olpdet_config_array[mail_idx].addr = CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx);
+ olpdet_config_array[mail_idx].size = OLPDET_SIZE;
+ }
+ CSIF_OLPDET_Multiple_Set(olpdet_length, &olpdet_config_array[0]);
+
+ mail_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ mail_info_array[mail_idx].mID = MAILBOX_ID;
+ mail_info_array[mail_idx].mail = (MAIL_CONTENT | mail_idx);
+ }
+ irq_length = 1;
+ irq_info_array[0].nID = IRQ_ID;
+ irq_info_array[0].code = csif_c2s_IRQ_code[IRQ_ID];
+ CSIF_MAILBOX_C2S_Multiple_Send_C2S_SWI_Multiple_Set(mail_length, &mail_info_array[0], irq_length, &irq_info_array[0]);
+#endif // end of multiple API
+ /* end measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Send_One_IRQ_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_Multiple_Mail_Send_One_IRQ_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_Multiple_Mail_Send_One_IRQ_array[mail_num_idx][Global_iteration_counter].end_time - Profile_Multiple_Mail_Send_One_IRQ_array[mail_num_idx][Global_iteration_counter].start_time;
+ //}
+ csif_c2s_IRQ_code[IRQ_ID]++;
+ /* Recover OLPDET and Mailbox */
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ CSIF_OLPDET_Clr(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+ }
+ do{
+ read_mail = CSIF_MAILBOX_C2S_Read(MAILBOX_ID);
+ }while(read_mail != CSIF_MAILBOX_EMPTY_VALUE);
+ /* Recover OLPDET and Mailbox */
+ }
+}
+
+void Multiple_Mail_Send_with_Multiple_IRQ(){
+ kal_uint32 read_mail = 0;
+#if defined(__CSIF_MULTIPLE_API__)
+ kal_uint32 mail_length = 0;
+ kal_uint32 olpdet_length = 0;
+ kal_uint32 irq_length = 0;
+ CSIF_OLPDET_CONFIG_t olpdet_config_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+ CSIF_MAIL_INFO_t mail_info_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+ CSIF_IRQ_INFO_t irq_info_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+#endif
+ for(kal_uint32 mail_num_idx = 0; mail_num_idx < TESTING_MULTIPLE_MAIL_NUM; mail_num_idx++){
+ /* start measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Send_Multiple_IRQ_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+ //}
+#if !defined(__CSIF_MULTIPLE_API__)
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ CSIF_OLPDET_Set(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+ CSIF_MAILBOX_C2S_Send(MAILBOX_ID, (MAIL_CONTENT | mail_idx));
+
+ }
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_IRQ_SET_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_C2S_SWI_Set(IRQ_ID, csif_c2s_IRQ_code[IRQ_ID]);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_IRQ_SET_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_IRQ_SET_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_IRQ_SET_array[mail_num_idx][Global_iteration_counter].end_time - Profile_IRQ_SET_array[mail_num_idx][Global_iteration_counter].start_time;
+#endif
+ csif_c2s_IRQ_code[IRQ_ID]++;
+ }
+#else // Multiple API
+ olpdet_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ olpdet_config_array[mail_idx].addr = CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx);
+ olpdet_config_array[mail_idx].size = OLPDET_SIZE;
+ }
+ CSIF_OLPDET_Multiple_Set(olpdet_length, &olpdet_config_array[0]);
+
+ mail_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ mail_info_array[mail_idx].mID = MAILBOX_ID;
+ mail_info_array[mail_idx].mail = (MAIL_CONTENT | mail_idx);
+ }
+ irq_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ irq_info_array[mail_idx].nID = IRQ_ID;
+ irq_info_array[mail_idx].code = csif_c2s_IRQ_code[IRQ_ID];
+ csif_c2s_IRQ_code[IRQ_ID]++;
+ }
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_MAILBOX_MULTIPLE_SEND_IRQ_SET_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_MAILBOX_C2S_Multiple_Send_C2S_SWI_Multiple_Set(mail_length, &mail_info_array[0], irq_length, &irq_info_array[0]);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_MAILBOX_MULTIPLE_SEND_IRQ_SET_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_MAILBOX_MULTIPLE_SEND_IRQ_SET_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_MAILBOX_MULTIPLE_SEND_IRQ_SET_array[mail_num_idx][Global_iteration_counter].end_time - Profile_MAILBOX_MULTIPLE_SEND_IRQ_SET_array[mail_num_idx][Global_iteration_counter].start_time;
+#endif
+#endif // end of multiple API
+ /* end measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Send_Multiple_IRQ_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_Multiple_Mail_Send_Multiple_IRQ_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_Multiple_Mail_Send_Multiple_IRQ_array[mail_num_idx][Global_iteration_counter].end_time - Profile_Multiple_Mail_Send_Multiple_IRQ_array[mail_num_idx][Global_iteration_counter].start_time;
+ // }
+ /* Recover OLPDET and Mailbox */
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ CSIF_OLPDET_Clr(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+ }
+ do{
+ read_mail = CSIF_MAILBOX_C2S_Read(MAILBOX_ID);
+ }while(read_mail != CSIF_MAILBOX_EMPTY_VALUE);
+ /* Recover OLPDET and Mailbox */
+ }
+}
+
+void Multiple_Mail_Deallocate(){
+#if defined(__CSIF_MULTIPLE_API__)
+ kal_uint32 olpdet_length = 0;
+ CSIF_OLPDET_CONFIG_t olpdet_config_array[MAX_TESTING_MULTIPLE_MAIL_NUM] = {0};
+#endif
+ for(kal_uint32 mail_num_idx = 0; mail_num_idx < TESTING_MULTIPLE_MAIL_NUM; mail_num_idx++){
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ CSIF_OLPDET_Set(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+ }
+ /* start measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Deallocate_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+ //}
+#if !defined(__CSIF_MULTIPLE_API__)
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_CLR_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_OLPDET_Clr(CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx), OLPDET_SIZE);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_CLR_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_OLPDET_CLR_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_OLPDET_CLR_array[mail_num_idx][Global_iteration_counter].end_time - Profile_OLPDET_CLR_array[mail_num_idx][Global_iteration_counter].start_time;
+#endif
+ }
+#else // Multiple API
+ olpdet_length = aggregate_mail_num_array[mail_num_idx];
+ for(kal_uint32 mail_idx = 0; mail_idx<aggregate_mail_num_array[mail_num_idx];mail_idx++){
+ olpdet_config_array[mail_idx].addr = CSIF_DSM_BASE+(OLPDET_SIZE*mail_idx);
+ olpdet_config_array[mail_idx].size = OLPDET_SIZE;
+ }
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_MULTIPLE_CLR_array[mail_num_idx][Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ CSIF_OLPDET_Multiple_Clr(olpdet_length, &olpdet_config_array[0]);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_OLPDET_MULTIPLE_CLR_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_OLPDET_MULTIPLE_CLR_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_OLPDET_MULTIPLE_CLR_array[mail_num_idx][Global_iteration_counter].end_time - Profile_OLPDET_MULTIPLE_CLR_array[mail_num_idx][Global_iteration_counter].start_time;
+#endif
+#endif // end of multiple API
+ /* end measuring time */
+ //if(Global_iteration_counter == RUN_ITERATION - 1){
+ Profile_Multiple_Mail_Deallocate_array[mail_num_idx][Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_Multiple_Mail_Deallocate_array[mail_num_idx][Global_iteration_counter].latency =
+ Profile_Multiple_Mail_Deallocate_array[mail_num_idx][Global_iteration_counter].end_time - Profile_Multiple_Mail_Deallocate_array[mail_num_idx][Global_iteration_counter].start_time;
+ //}
+ }
+}
+
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__) && !defined(__CSIF_MULTIPLE_API__)
+void Recv_single_mail_profile()
+{
+ csif_uint32 read_mail;
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_MAILBOX_RECV_array[Global_iteration_counter].start_time = miu_cycle_counter_read();
+#endif
+ read_mail = CSIF_MAILBOX_C2S_Read(MAILBOX_ID);
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__)
+ Profile_MAILBOX_RECV_array[Global_iteration_counter].end_time = miu_cycle_counter_read();
+ Profile_MAILBOX_RECV_array[Global_iteration_counter].latency =
+ Profile_MAILBOX_RECV_array[Global_iteration_counter].end_time - Profile_MAILBOX_RECV_array[Global_iteration_counter].start_time;
+#endif
+}
+#endif
+
+void CSIF_PROFILING_ENTRY(){
+
+ for(int i = 0; i<RUN_ITERATION; i++ ){
+ Multiple_Mail_Send_no_IRQ();
+ Global_iteration_counter++;
+ }
+ IRQ_ID = 0;
+ Global_iteration_counter = 0;
+ for(int i = 0; i<RUN_ITERATION; i++ ){
+ Multiple_Mail_Send_with_Single_IRQ();
+ IRQ_ID++;
+ Global_iteration_counter++;
+ }
+ IRQ_ID = 0;
+ Global_iteration_counter = 0;
+ for(int i = 0; i<RUN_ITERATION; i++ ){
+ Multiple_Mail_Send_with_Multiple_IRQ();
+ IRQ_ID++;
+ Global_iteration_counter++;
+ }
+ Global_iteration_counter = 0;
+ for(int i = 0; i<RUN_ITERATION; i++ ){
+ Multiple_Mail_Deallocate();
+ Global_iteration_counter++;
+ }
+#if defined(__CSIF_SINGLE_API_INDIVIDUAL_PROFILE__) && !defined(__CSIF_MULTIPLE_API__)
+ Global_iteration_counter = 0;
+ for(int i = 0; i<RUN_ITERATION; i++ ){
+ Recv_single_mail_profile();
+ Global_iteration_counter++;
+ }
+#endif
+}
diff --git a/mcu/driver/devdrv/csif/mt6297p/src/drv_csif_init.c b/mcu/driver/devdrv/csif/mt6297p/src/drv_csif_init.c
new file mode 100644
index 0000000..f1eb577
--- /dev/null
+++ b/mcu/driver/devdrv/csif/mt6297p/src/drv_csif_init.c
@@ -0,0 +1,349 @@
+#include "drv_csif.h"
+#include "kal_internal_api.h"
+#include "init_comm.h"
+#include "kal_hrt_api.h"
+
+/*******************************************************************************
+ * Global CSIF structure declare here
+ *******************************************************************************/
+csif_uint32 FPGA_version = 0;
+
+/*******************************************************************************
+ * Data Structure
+ *******************************************************************************/
+/* extern entry functions */
+#undef M_CSIF_S2C_INFO
+#undef M_CSIF_L1_ERR_INFO
+#define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) extern void CSIFHandler(CSIF_ID_STATUS_t *);
+#define M_CSIF_L1_ERR_INFO(CSIFErrHandler, Code, Value) extern void CSIFErrHandler(CSIF_ID_STATUS_t *);
+
+#include "csif_s2c_isr_config_n0_pre.h"
+#include "csif_s2c_isr_config_n1_pre.h"
+#include "csif_s2c_isr_config_n2_pre.h"
+#include "csif_s2c_isr_config_n3_pre.h"
+#include "csif_s2c_isr_config_n4_pre.h"
+#include "csif_s2c_isr_config_n5_pre.h"
+#include "csif_l1_err_isr_config_pre.h"
+
+#undef M_CSIF_S2C_INFO
+#undef M_CSIF_L1_ERR_INFO
+
+/* CSIF handler function pointer array */
+
+CSIF_InterruptEntryFun csif_s2c_isr_handler_n0[CSIF_S2C_N0_TOTAL_NUMBER] = {
+ #undef M_CSIF_S2C_INFO
+ #define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIFHandler,
+
+ #include "csif_s2c_isr_config_n0_pre.h"
+
+ #undef M_CSIF_S2C_INFO
+};
+
+CSIF_InterruptEntryFun csif_s2c_isr_handler_n1[CSIF_S2C_N1_TOTAL_NUMBER] = {
+ #undef M_CSIF_S2C_INFO
+ #define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIFHandler,
+
+ #include "csif_s2c_isr_config_n1_pre.h"
+
+ #undef M_CSIF_S2C_INFO
+};
+
+CSIF_InterruptEntryFun csif_s2c_isr_handler_n2[CSIF_S2C_N2_TOTAL_NUMBER] = {
+ #undef M_CSIF_S2C_INFO
+ #define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIFHandler,
+
+ #include "csif_s2c_isr_config_n2_pre.h"
+
+ #undef M_CSIF_S2C_INFO
+};
+
+CSIF_InterruptEntryFun csif_s2c_isr_handler_n3[CSIF_S2C_N3_TOTAL_NUMBER] = {
+ #undef M_CSIF_S2C_INFO
+ #define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIFHandler,
+
+ #include "csif_s2c_isr_config_n3_pre.h"
+
+ #undef M_CSIF_S2C_INFO
+};
+
+CSIF_InterruptEntryFun csif_s2c_isr_handler_n4[CSIF_S2C_N4_TOTAL_NUMBER] = {
+ #undef M_CSIF_S2C_INFO
+ #define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIFHandler,
+
+ #include "csif_s2c_isr_config_n4_pre.h"
+
+ #undef M_CSIF_S2C_INFO
+};
+
+CSIF_InterruptEntryFun csif_s2c_isr_handler_n5[CSIF_S2C_N5_TOTAL_NUMBER] = {
+ #undef M_CSIF_S2C_INFO
+ #define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIFHandler,
+
+ #include "csif_s2c_isr_config_n5_pre.h"
+
+ #undef M_CSIF_S2C_INFO
+};
+
+CSIF_InterruptEntryFun* csif_s2c_isr_handler[CSIF_ENUM_ALL_S2C_INT_NUM] = {
+ csif_s2c_isr_handler_n0,
+ csif_s2c_isr_handler_n1,
+ csif_s2c_isr_handler_n2,
+ csif_s2c_isr_handler_n3,
+ csif_s2c_isr_handler_n4,
+ csif_s2c_isr_handler_n5
+};
+
+
+/* CSIF Error handler function pointer array */
+CSIF_InterruptEntryFun csif_l1_err_isr_handler[CSIF_L1_ERR_TOTAL_NUMBER] = {
+ #undef M_CSIF_L1_ERR_INFO
+ #define M_CSIF_L1_ERR_INFO(CSIFErrHandler, Code, Value) CSIFErrHandler,
+
+ #include "csif_l1_err_isr_config_pre.h"
+
+ #undef M_CSIF_L1_ERR_INFO
+};
+
+/* CSIF irq ovfl allowed bool array */
+
+csif_bool csif_c2s_irq_ovfl_allow_n0[CSIF_C2S_N0_TOTAL_NUMBER] = {
+ #undef M_CSIF_C2S_INFO
+ #define M_CSIF_C2S_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) IRQ_ovfl_allow,
+
+ #include "csif_c2s_isr_config_n0_pre.h"
+
+ #undef M_CSIF_C2S_INFO
+};
+
+csif_bool csif_c2s_irq_ovfl_allow_n1[CSIF_C2S_N1_TOTAL_NUMBER] = {
+ #undef M_CSIF_C2S_INFO
+ #define M_CSIF_C2S_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) IRQ_ovfl_allow,
+
+ #include "csif_c2s_isr_config_n1_pre.h"
+
+ #undef M_CSIF_C2S_INFO
+};
+
+csif_bool csif_c2s_irq_ovfl_allow_n2[CSIF_C2S_N2_TOTAL_NUMBER] = {
+ #undef M_CSIF_C2S_INFO
+ #define M_CSIF_C2S_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) IRQ_ovfl_allow,
+
+ #include "csif_c2s_isr_config_n2_pre.h"
+
+ #undef M_CSIF_C2S_INFO
+};
+
+csif_bool csif_c2s_irq_ovfl_allow_n3[CSIF_C2S_N3_TOTAL_NUMBER] = {
+ #undef M_CSIF_C2S_INFO
+ #define M_CSIF_C2S_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) IRQ_ovfl_allow,
+
+ #include "csif_c2s_isr_config_n3_pre.h"
+
+ #undef M_CSIF_C2S_INFO
+};
+
+
+csif_bool* csif_c2s_irq_ovfl_allow[CSIF_ENUM_ALL_C2S_INT_NUM] = {
+ csif_c2s_irq_ovfl_allow_n0,
+ csif_c2s_irq_ovfl_allow_n1,
+ csif_c2s_irq_ovfl_allow_n2,
+ csif_c2s_irq_ovfl_allow_n3
+};
+
+/* CSIF HW entry num array */
+
+csif_uint32 csif_mailbox_entry_num_table[CSIF_MAILBOX_TOTAL_NUM] = {
+ #undef M_CSIF_MAILBOX_HW_INFO
+ #undef M_CSIF_MAILBOX_C2S_INFO
+ #undef M_CSIF_MAILBOX_S2C_INFO
+
+ #define M_CSIF_MAILBOX_HW_INFO(entrySize, HW_ID) entrySize,
+ #define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID)
+ #define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID)
+
+ #include "csif_mailbox_config_pre.h"
+
+ #undef M_CSIF_MAILBOX_HW_INFO
+ #undef M_CSIF_MAILBOX_C2S_INFO
+ #undef M_CSIF_MAILBOX_S2C_INFO
+};
+
+
+/*
+****************************************************************************************************************************
+* CSIF_Init.
+*
+* This function is for initiate the CSIF HW/SW
+*
+* Input: None
+*
+* Output: None
+*
+****************************************************************************************************************************
+*/
+
+void csif_init(void)
+{
+#if defined (__FPGA__)
+ #if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+ if(INT_FPGA_PURPOSE() == FPGA_H5)
+ {
+ #elif defined(MT6297)
+ if((INT_FPGA_PURPOSE() != FPGA_H1) && (INT_FPGA_PURPOSE() != FPGA_H3) && (INT_FPGA_PURPOSE() != FPGA_H4))
+ {
+ #else
+ #error "unsupport project, may need porting"
+ #endif
+#endif
+ //[step0.] zero init
+
+ //[step1.] disable CSIF interrupt source & error type
+ //disable S2C CSIF interrupt source
+ for (int i=0; i<CSIF_ENUM_ALL_S2C_INT_NUM; i++){
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + i*CSIF_S2C_IRQ_SIZE, 0x0);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ }
+ //disable CSIF s2c_WFI_enable mask (write 10 bits on each enable mask, 4 th per core and 1 AND/OR bit per core)
+ /*
+ for (int i=0; i<CSIF_S2C_IDLE_IRQ_NUM; i++){
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + i*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+ }
+ */
+ //disable L1 error type (27 error, 2018/3/21)
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, 0x0);
+
+ //disable mailbox debug enable
+ for (int i=0; i<CSIF_MAILBOX_HW_TOTAL_NUMBER; i++){
+ CSIF_REG_WRITE(CSIF_MAILBOX_DEBUG_ENABLE + i*CSIF_MAILBOX_SIZE, 0x0);
+ }
+
+ //[step2.] clear error interrupt (MPU violation, MPU cfg error, undefined region, OVFL) & CSIF C2S interrupt status
+ //clear MPU violation status
+ for (int i=0; i<CSIF_MPU_CHANNEL_NUM_DSP; i++){
+ CSIF_REG_WRITE(CSIF_MPU_ERR_CLR + i*CSIF_MPU_ERR_SIZE, 0x1);
+ }
+ //clear DSP MPU cfg err status
+ for (int i=0; i<CSIF_MPU_CHANNEL_NUM_DSP; i++){
+ CSIF_REG_WRITE(CSIF_MPU_CFG_ERR_CLR_DSP + i*CSIF_MPU_CFG_ERR_CLR_SIZE, 0x1);
+ }
+ //clear L1 MPU cfg err status
+ for (int i=0; i<CSIF_MPU_CHANNEL_NUM_L1; i++){
+ CSIF_REG_WRITE(CSIF_MPU_CFG_ERR_CLR_L1 + i*CSIF_MPU_CFG_ERR_CLR_SIZE, 0x1);
+ }
+ //clear undefined region error status
+ CSIF_REG_WRITE(CSIF_DSM_WRITE_UNDEFINED_ERR_CLR_CR, 0x1);
+ CSIF_REG_WRITE(CSIF_DSM_READ_UNDEFINED_ERR_CLR_CR, 0x1);
+ CSIF_REG_WRITE(CSIF_DSR_WRITE_UNDEFINED_ERR_CLR_CR, 0x1);
+ CSIF_REG_WRITE(CSIF_DSR_READ_UNDEFINED_ERR_CLR_CR, 0x1);
+
+ //clear C2S overflow status
+ //(!!make rule: TBD! Which side to clear irq ovfl!)
+ /*
+ for (int i=0; i<CSIF_ENUM_ALL_C2S_INT_NUM; i++){
+ CSIF_REG_WRITE(CSIF_C2S_IRQ_OVFL_CLR + i*CSIF_C2S_IRQ_OVFL_SIZE, 0xFFFFFFFF);
+ }
+
+ //clear S2C overflow status
+ for (int i=0; i<CSIF_ENUM_ALL_S2C_INT_NUM; i++){
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_OVFL_CLR + i*CSIF_S2C_IRQ_OVFL_SIZE, 0xFFFFFFFF);
+ }
+ */
+ //clear s2c irq status
+ // s2c0/1 bit0/1 no effect (HW IRQ)
+ // unclear s2c irq because it must not pending s2c irq when 1st boot up
+ // unclear s2c irq because maybe there is user trigger s2c irq before activate done
+ /*
+ for (int i=0; i<CSIF_ENUM_ALL_S2C_INT_NUM; i++){
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_CLR + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+ }
+ */
+ //clear mailbox error
+ for (int i=0; i<CSIF_MAILBOX_HW_TOTAL_NUMBER; i++){
+ CSIF_REG_WRITE(CSIF_MAILBOX_CLR_ERROR + i*CSIF_MAILBOX_SIZE, 0x1);
+ }
+
+ //clear OLPDET error
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR_ERROR, 0x1);
+
+ //[step3.] enable CSIF setting
+ #if !defined(__CSIF_DRV_TEST__)
+ //enable L1 error type (27 error, 2018/3/21)
+ // s2c/c2s irq ovfl error to use SW to control
+ CSIF_REG_WRITE(CSIF_L1_ERROR_ENABLE_CR, CSIF_L1_ERROR_MASK);
+ //enable S2C CSIF interrupt source
+ for (int i=0; i<CSIF_ENUM_ALL_S2C_INT_NUM; i++){
+ if(i == 0 || i == 1){
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_SET + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ }else{
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_SET + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#elif defined(MT6297)
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + i*CSIF_S2C_IRQ_SIZE, 0xFFFFFFFF);
+#else
+ #error "unsupport project, may need porting"
+#endif
+ }
+ }
+ #endif
+ //open mask of CSIF s2c_WFI_enable mask (write 10 bits on each enable mask, 4 th per core and 1 AND/OR bit per core)
+ //WFI_irq0
+ //CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_SET + 0*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+ //WFI_irq1
+ //CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_SET + 1*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, 0x3FF);
+
+ // set SS region on DSM into OLPDET
+ //CSIF_OLPDET_Set(0, 2048);
+
+ //[step4.] Register CIRQ
+ //IRQ_Register_LISR(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE, CSIF_S2C_N0_Handler, "csif_s2c_n0");
+ //IRQSensitivity(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE, LEVEL_SENSITIVE);
+ IRQUnmask(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE);
+
+ //IRQ_Register_LISR(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE, CSIF_S2C_N1_Handler, "csif_s2c_n1");
+ //IRQSensitivity(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE, LEVEL_SENSITIVE);
+ IRQUnmask(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE);
+
+ //IRQ_Register_LISR(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE, CSIF_S2C_N2_Handler, "csif_s2c_n2");
+ //IRQSensitivity(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE, LEVEL_SENSITIVE);
+ IRQUnmask(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE);
+
+ //IRQ_Register_LISR(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE, CSIF_S2C_N3_Handler, "csif_s2c_n3");
+ //IRQSensitivity(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE, LEVEL_SENSITIVE);
+ IRQUnmask(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE);
+
+ //IRQ_Register_LISR(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE, CSIF_S2C_N4_Handler, "csif_s2c_n4");
+ //IRQSensitivity(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE, LEVEL_SENSITIVE);
+ IRQUnmask(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE);
+
+ //IRQ_Register_LISR(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE, CSIF_S2C_N5_Handler, "csif_s2c_n5");
+ //IRQSensitivity(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE, LEVEL_SENSITIVE);
+ IRQUnmask(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE);
+
+ //IRQ_Register_LISR(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE, CSIF_L1_ERR_Handler, "csif_error_irq");
+ //IRQSensitivity(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE, LEVEL_SENSITIVE);
+ IRQUnmask(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE);
+
+ //[step5.] pass ext_csif base addr to DSP
+ extern void EXT_CSIF_Init(void);
+ EXT_CSIF_Init();
+
+#if defined (__FPGA__)
+ }
+ else
+ {
+ return;
+ }
+#endif
+}
+
diff --git a/mcu/driver/devdrv/csif/mt6297p/src/drv_csif_main.c b/mcu/driver/devdrv/csif/mt6297p/src/drv_csif_main.c
new file mode 100644
index 0000000..f61a609
--- /dev/null
+++ b/mcu/driver/devdrv/csif/mt6297p/src/drv_csif_main.c
@@ -0,0 +1,1067 @@
+#include "drv_csif.h"
+#include "kal_hrt_api.h"
+#include "kal_public_defs.h"
+#if defined(__CSIF_DEBUG__)
+#include "us_timer.h"
+#endif
+
+#if defined(MT6297)
+#include "d2d_public.h" // For Apollo OLPDET workaround
+#include "kal_itc.h"
+#endif
+
+#if defined(__CSIF_DEBUG__)
+// #include frc_api.h
+#endif /* __CSIF_DEBUG__ */
+
+#if defined(__CSIF_DRV_TEST__)
+volatile csif_uint32 ASSERT_MSG[3];
+#endif
+
+
+/*******************************************************************************
+ * Macros
+ *******************************************************************************/
+/* e.g. GET_S2C_IRQ_LIMIT_NUMBER(0) => CSIF_S2C_N0_TOTAL_NUMBER */
+#define POSTFIX(nID, pos) nID##pos
+#define PREFIX(nID, pre) POSTFIX(pre##nID, _TOTAL_NUMBER)
+#define GET_S2C_IRQ_LIMIT_NUMBER(nID) PREFIX(nID, CSIF_S2C_N)
+
+#define GET_C2S_IRQ_LIMIT_NUMBER(nID) PREFIX(nID, CSIF_C2S_N)
+
+/*******************************************************************************
+ * Variable Declaration
+ *******************************************************************************/
+extern CSIF_InterruptEntryFun* csif_s2c_isr_handler[CSIF_ENUM_ALL_S2C_INT_NUM];
+extern csif_bool* csif_c2s_irq_ovfl_allow[CSIF_ENUM_ALL_C2S_INT_NUM];
+extern CSIF_InterruptEntryFun csif_l1_err_isr_handler[CSIF_L1_ERR_TOTAL_NUMBER];
+extern csif_uint32 csif_mailbox_entry_num_table[CSIF_MAILBOX_TOTAL_NUM];
+
+#if defined(MT6297)
+kal_uint32 olpdet_lock = 0; // For Apollo OLPDET workaround
+#endif
+
+static const kal_uint32 CSIF_S2C_Interrupt_Num[CSIF_ENUM_ALL_S2C_INT_NUM] = {
+ GET_S2C_IRQ_LIMIT_NUMBER(0),
+ GET_S2C_IRQ_LIMIT_NUMBER(1),
+ GET_S2C_IRQ_LIMIT_NUMBER(2),
+ GET_S2C_IRQ_LIMIT_NUMBER(3),
+ GET_S2C_IRQ_LIMIT_NUMBER(4),
+ GET_S2C_IRQ_LIMIT_NUMBER(5)
+};
+static const kal_uint32 CSIF_C2S_Interrupt_Num[CSIF_ENUM_ALL_C2S_INT_NUM] = {
+ GET_C2S_IRQ_LIMIT_NUMBER(0),
+ GET_C2S_IRQ_LIMIT_NUMBER(1),
+ GET_C2S_IRQ_LIMIT_NUMBER(2),
+ GET_C2S_IRQ_LIMIT_NUMBER(3)
+};
+/*******************************************************************************
+ * Debug
+ *******************************************************************************/
+#if defined(__CSIF_DEBUG__)
+
+CSIF_DebugISRCodeList csif_debug_s2c_isr_handler_n0;
+CSIF_DebugISRCodeList csif_debug_s2c_isr_handler_n1;
+CSIF_DebugISRCodeList csif_debug_s2c_isr_handler_n2;
+CSIF_DebugISRCodeList csif_debug_s2c_isr_handler_n3;
+CSIF_DebugISRCodeList csif_debug_s2c_isr_handler_n4;
+CSIF_DebugISRCodeList csif_debug_s2c_isr_handler_n5;
+
+CSIF_DebugRecordList csif_debug_records;
+CSIF_MultiOperationDebugRecordList csif_multioperation_debug_records;
+
+kal_atomic_uint32 MultiOperation_debug_idx = 0;
+#endif /* __CSIF_DEBUG__ */
+
+
+/*******************************************************************************
+ * Function prototypes
+ *******************************************************************************/
+void csif_InterruptHandlerInternal(volatile csif_uint32* clr_reg,
+ volatile csif_uint32* status_reg,
+ volatile csif_uint32* m_status_reg,
+ volatile csif_uint32* enable_reg,
+ volatile csif_uint32 isr_n_num,
+ CSIF_InterruptEntryFun* handler);
+
+
+/*******************************************************************************
+ * Functions - Debug information
+ *******************************************************************************/
+#if defined(__CSIF_DEBUG__)
+void csif_DebugAddISRHandlerCode(CSIF_S2C_INDEX nID, csif_uint32 code){
+ CSIF_DebugISRCodeList* code_list = CSIF_NULL;
+
+ switch(nID){
+ case CSIF_ENUM_S2C_N0:
+ code_list = &csif_debug_s2c_isr_handler_n0;
+ break;
+ case CSIF_ENUM_S2C_N1:
+ code_list = &csif_debug_s2c_isr_handler_n1;
+ break;
+ case CSIF_ENUM_S2C_N2:
+ code_list = &csif_debug_s2c_isr_handler_n2;
+ break;
+ case CSIF_ENUM_S2C_N3:
+ code_list = &csif_debug_s2c_isr_handler_n3;
+ break;
+ case CSIF_ENUM_S2C_N4:
+ code_list = &csif_debug_s2c_isr_handler_n4;
+ break;
+ case CSIF_ENUM_S2C_N5:
+ code_list = &csif_debug_s2c_isr_handler_n5;
+ break;
+ default:
+ CSIF_ASSERT(0, nID, code, CSIF_ENUM_ALL_S2C_INT_NUM);
+ }
+
+ csif_uint32 record_index = 0;
+
+ if(code_list != CSIF_NULL){
+ record_index = code_list -> top_index;
+ //record_index = kal_atomic_inc_circular_index(&(code_list -> top_index), CSIF_DEBUG_ISR_HANDLE_CODE_SIZE);
+ code_list -> records[record_index].time = ust_get_current_time();
+ code_list -> records[record_index].code = code;
+ (code_list -> top_index)++;
+
+ if (code_list -> top_index == CSIF_DEBUG_ISR_HANDLE_CODE_SIZE){
+ code_list -> top_index = 0;
+ }
+ }
+ return;
+}
+
+void csif_DebugAddRecord(csif_uint32 status,
+ volatile csif_uint32* set_addr,
+ csif_uint32 set_value,
+ csif_uint32 caller){
+ csif_uint32 record_index = 0;
+ CSIF_DebugRecordList* record_list = CSIF_NULL;
+
+ record_list = &csif_debug_records;
+
+ //csif_uint32 mask;
+ //mask = kal_hrt_SaveAndSetIRQMask();
+
+ //record_index = record_list -> top_index;
+ record_index = kal_atomic_inc_circular_index(&(record_list -> top_index), CSIF_DEBUG_API_RECORD_SIZE);
+ //(record_list -> top_index)++;
+ //if (record_list -> top_index == CSIF_DEBUG_API_RECORD_SIZE){
+ // record_list -> top_index = 0;
+ //}
+ //kal_hrt_RestoreIRQMask(mask);
+
+ record_list -> records[record_index].time = ust_get_current_time();
+ record_list -> records[record_index].status = status;
+ record_list -> records[record_index].set_addr = (csif_uint32)set_addr;
+ record_list -> records[record_index].set_value = set_value;
+ record_list -> records[record_index].caller = caller;
+ return;
+}
+
+void csif_MultiDebugAddRecord(csif_uint32 multiIdx,
+ volatile csif_uint32* set_addr,
+ csif_uint32 set_value,
+ csif_uint32 caller){
+ csif_uint32 record_index = 0;
+ CSIF_MultiOperationDebugRecordList* record_list = CSIF_NULL;
+
+ record_list = &csif_multioperation_debug_records;
+
+ //csif_uint32 mask;
+ //mask = kal_hrt_SaveAndSetIRQMask();
+
+ //record_index = record_list -> top_index;
+ record_index = kal_atomic_inc_circular_index(&(record_list -> top_index), CSIF_DEBUG_MULTI_API_RECORD_SIZE);
+ //(record_list -> top_index)++;
+ //if (record_list -> top_index == CSIF_DEBUG_API_RECORD_SIZE){
+ // record_list -> top_index = 0;
+ //}
+ //kal_hrt_RestoreIRQMask(mask);
+
+ record_list -> records[record_index].time = ust_get_current_time();
+ record_list -> records[record_index].set_addr = (csif_uint32)set_addr;
+ record_list -> records[record_index].set_value = set_value;
+ record_list -> records[record_index].caller = caller;
+ record_list -> records[record_index].multiIdx = multiIdx;
+ return;
+}
+
+#endif /* __CSIF_DEBUG__ */
+
+
+/*******************************************************************************
+ * Functions - Common Part
+ *******************************************************************************/
+void CSIF_Invalid(CSIF_ID_STATUS_t* status_id){
+#if !defined(__CSIF_DRV_TEST__)
+ // code 1: csif_id(irq_id 0-5), code 2: csif_bit, code 3: masked_status
+ CSIF_ASSERT(0, status_id->id, status_id->code, status_id->masked_status);
+#else
+#endif
+}
+
+void __attribute__ ((used)) csif_InterruptHandlerInternal(volatile csif_uint32* clr_reg,
+ volatile csif_uint32* status_reg,
+ volatile csif_uint32* m_status_reg,
+ volatile csif_uint32* enable_reg,
+ volatile csif_uint32 isr_n_num,
+ CSIF_InterruptEntryFun* handler)
+{
+ CSIF_ID_STATUS_t status_id;
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+
+
+ csif_uint32 index = 0;
+ // status_id:
+ // id: c2s irq num (0~3)
+ // code: local_c2s bit code (0~31)
+ // masked_status: c2s_masked status (corresponding irq 0 or irq 1)
+ // *reg_addr: c2s status reg addr
+ status_id.reg_addr = (csif_uint32*)status_reg;
+ CSIF_REG_READ(m_status_reg, status_id.masked_status);
+
+ csif_uint32 csif_interrupt_num = CSIF_S2C_Interrupt_Num[isr_n_num];
+ while(index < csif_interrupt_num)
+ {
+ if((status_id.masked_status & (0x1<<index))!= 0)
+ {
+ status_id.id = isr_n_num;
+ status_id.code = index;
+ // clear irq bit before entering user callback
+ CSIF_REG_WRITE(clr_reg, 1<<index);
+ status_id.masked_status = status_id.masked_status & (~(0x1<<index));
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(status_id.masked_status, clr_reg, 0x1<<index, caller);
+#endif /* __CSIF_DEBUG__ */
+
+ (handler[index])((CSIF_ID_STATUS_t *)(&status_id));
+
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddISRHandlerCode(isr_n_num, index);
+#endif /* __CSIF_DEBUG__ */
+
+ }
+ index++;
+ }
+}
+
+
+void CSIF_S2C_N0_Handler(kal_uint32 irq_id){
+ CSIF_HANDLER(CSIF_ENUM_S2C_N0);
+}
+
+void CSIF_S2C_N1_Handler(kal_uint32 irq_id){
+ CSIF_HANDLER(CSIF_ENUM_S2C_N1);
+}
+
+void CSIF_S2C_N2_Handler(kal_uint32 irq_id){
+ CSIF_HANDLER(CSIF_ENUM_S2C_N2);
+}
+
+void CSIF_S2C_N3_Handler(kal_uint32 irq_id){
+ CSIF_HANDLER(CSIF_ENUM_S2C_N3);
+}
+
+void CSIF_S2C_N4_Handler(kal_uint32 irq_id){
+ CSIF_HANDLER(CSIF_ENUM_S2C_N4);
+}
+
+void CSIF_S2C_N5_Handler(kal_uint32 irq_id){
+ CSIF_HANDLER(CSIF_ENUM_S2C_N5);
+}
+
+
+void CSIF_L1_ERR_Handler(kal_uint32 irq_id){
+ CSIF_ID_STATUS_t err_status_id;
+ csif_uint32 index = 0;
+
+ //***** err_status_id: ***********
+ // id: error snapshot
+ // code: error bit
+ // masked_status: error_enable
+ // *reg_addr: addr of error status base addr (MCU doesn't have error source)
+ //*********************************
+ err_status_id.reg_addr = (csif_uint32*)CSIF_L1_ERROR_FLAG_CR;
+ CSIF_REG_READ(CSIF_L1_ERROR_SNAPSHOT_CR, err_status_id.id);
+ CSIF_REG_READ(CSIF_L1_ERROR_ENABLE_CR, err_status_id.masked_status);
+
+ while(index < CSIF_L1_ERR_TOTAL_NUMBER){
+ if((err_status_id.masked_status & (1 << index)) && (err_status_id.id & (1 << index))){
+ err_status_id.code = index;
+ (csif_l1_err_isr_handler[index])((CSIF_ID_STATUS_t *)(&err_status_id));
+ }
+ index++;
+ }
+
+ // code 1: error snapshot, code 2: error_bit, code 3: error_enable
+ CSIF_ASSERT(0, err_status_id.id, err_status_id.code, err_status_id.masked_status);
+}
+
+
+/*******************************************************************************
+ * Functions - MCU CSIF PART API
+ *******************************************************************************/
+
+void CSIF_C2S_SWI_Set(CSIF_C2S_INDEX nID, csif_uint32 code){
+ csif_uint32 before_status = 0xFFFFFFFF;
+ // get caller here
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ // assertion of user setting code out of code limit
+ csif_uint32 code_limit = CSIF_C2S_Interrupt_Num[nID];
+ CSIF_ASSERT(code < code_limit, nID, code, code_limit);
+
+ if(csif_c2s_irq_ovfl_allow[nID][code] == CSIF_TRUE){
+ CSIF_REG_WRITE(CSIF_C2S_IRQ_SET + nID*CSIF_C2S_IRQ_SIZE, 1 << code);
+ }else{
+ // Use HWITC to create critical section
+ kal_hrt_take_itc_lock(KAL_ITC_CSIF_LOCK, KAL_INFINITE_WAIT);
+ /* end of HWITC take */
+ CSIF_REG_READ(CSIF_C2S_IRQ_STATUS + nID*CSIF_C2S_IRQ_SIZE, before_status);
+ if((before_status & (1 << code)) == 0){
+ CSIF_REG_WRITE(CSIF_C2S_IRQ_SET + nID*CSIF_C2S_IRQ_SIZE, 1 << code);
+ /* Release HWITC */
+ kal_hrt_give_itc_lock(KAL_ITC_CSIF_LOCK);
+ }
+ else{
+ /* Release HWITC */
+ kal_hrt_give_itc_lock(KAL_ITC_CSIF_LOCK);
+#if defined(__CSIF_DEBUG__)
+ CSIF_ASSERT((before_status & (1 << code)) == 0, nID, code, caller);
+#else
+ CSIF_ASSERT((before_status & (1 << code)) == 0, nID, code, 0);
+#endif
+ //CSIF_REG_WRITE(CSIF_C2S_IRQ_SET + nID*CSIF_C2S_IRQ_SIZE, 1 << code);
+ }
+ }
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(before_status, (csif_uint32*)(CSIF_C2S_IRQ_SET + nID*CSIF_C2S_IRQ_SIZE), 1 << code, caller);
+#endif /* __CSIF_DEBUG__ */
+}
+
+csif_uint32 CSIF_C2S_SWI_Read(CSIF_C2S_INDEX nID){
+ csif_uint32 c2s_swi_read = 0;
+ CSIF_REG_READ(CSIF_C2S_IRQ_STATUS + nID*CSIF_C2S_IRQ_SIZE, c2s_swi_read);
+ return c2s_swi_read;
+}
+
+csif_uint32 CSIF_C2S_SWI_MASKED_Read(CSIF_C2S_INDEX nID){
+ csif_uint32 c2s_swi_masked_read = 0;
+ CSIF_REG_READ(CSIF_C2S_IRQ_MASKED_STATUS + nID*CSIF_C2S_IRQ_SIZE, c2s_swi_masked_read);
+ return c2s_swi_masked_read;
+}
+
+
+
+csif_uint32 CSIF_S2C_SWI_Read(CSIF_S2C_INDEX nID){
+ csif_uint32 s2c_swi_read = 0;
+ CSIF_REG_READ(CSIF_S2C_IRQ_STATUS + nID*CSIF_S2C_IRQ_SIZE, s2c_swi_read);
+ return s2c_swi_read;
+}
+
+csif_uint32 CSIF_S2C_SWI_MASKED_Read(CSIF_S2C_INDEX nID){
+ csif_uint32 s2c_swi_masked_read = 0;
+ CSIF_REG_READ(CSIF_S2C_IRQ_MASKED_STATUS + nID*CSIF_S2C_IRQ_SIZE, s2c_swi_masked_read);
+ return s2c_swi_masked_read;
+}
+
+csif_uint32 CSIF_S2C_SWI_Enable_Read(CSIF_S2C_INDEX nID){
+ csif_uint32 enable_read = 0;
+ CSIF_REG_READ(CSIF_S2C_IRQ_ENABLE + nID*CSIF_S2C_IRQ_SIZE, enable_read);
+ return enable_read;
+}
+
+void CSIF_S2C_SWI_Enable(CSIF_S2C_INDEX nID, csif_uint32 code){
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ // assertion of user setting code out of code limit
+ csif_uint32 code_limit = CSIF_S2C_Interrupt_Num[nID];
+ CSIF_ASSERT(code < code_limit, nID, code, code_limit);
+
+ // use atomic to protect setting S2C enable CR part
+ /*TODO use Shaolin atomic */
+ //cc_spinlock_hw_take_lock(CC_SPINLOCK_CSIF_DRIVER);
+
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_SET + nID*CSIF_S2C_IRQ_SIZE, (1<<code));
+
+ // release atomic
+ /*TODO use Shaolin atomic */
+ //cc_spinlock_hw_give_lock(CC_SPINLOCK_CSIF_DRIVER);
+
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(nID, (csif_uint32*)(CSIF_S2C_IRQ_ENABLE_SET + nID*CSIF_S2C_IRQ_SIZE), (1<<code), caller);
+#endif /* __CSIF_DEBUG__ */
+#elif defined(MT6297)
+#else
+ #error "unsupport project, may need porting"
+#endif // project option
+}
+
+void CSIF_S2C_SWI_Disable(CSIF_S2C_INDEX nID, csif_uint32 code){
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ // assertion of user setting code out of code limit
+ csif_uint32 code_limit = CSIF_S2C_Interrupt_Num[nID];
+ CSIF_ASSERT(code < code_limit, nID, code, code_limit);
+
+ // use atomic to protect setting S2C enable CR part
+ /*TODO use Shaolin atomic */
+ //cc_spinlock_hw_take_lock(CC_SPINLOCK_CSIF_DRIVER);
+
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE_CLR + nID*CSIF_S2C_IRQ_SIZE, (1 << code));
+
+
+ // release atomic
+ /*TODO use Shaolin atomic */
+ //cc_spinlock_hw_give_lock(CC_SPINLOCK_CSIF_DRIVER);
+
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(nID, (csif_uint32*)(CSIF_S2C_IRQ_ENABLE_CLR + nID*CSIF_S2C_IRQ_SIZE), (1 << code), caller);
+#endif /* __CSIF_DEBUG__ */
+#elif defined(MT6297)
+#else
+ #error "unsupport project, may need porting"
+#endif // project option
+}
+
+// this enable bitmask api shouldn't let user use, SS use only
+void CSIF_S2C_SWI_Enable_bitmask(CSIF_S2C_INDEX nID, csif_uint32 bitmap){
+#if defined(MT6297)
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ /*Todo*/ /*maybe no need, because we won't use enable bitmask without backup/restore flow*/
+ /*need to atomic of backup/restore flow api*/
+ // use atomic to protect setting S2C enable CR part
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_ENABLE + nID*CSIF_S2C_IRQ_SIZE, bitmap);
+
+ // release atomic
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(nID, (csif_uint32*)(CSIF_S2C_IRQ_ENABLE + nID*CSIF_S2C_IRQ_SIZE), bitmap, caller);
+#endif /* __CSIF_DEBUG__ */
+#elif defined(MT6885) || defined(MT6873) || defined(MERCURY)
+#else
+ #error "unsupport project, may need porting"
+#endif // project option
+}
+
+csif_uint32 CSIF_S2C_Overflow_Read(CSIF_S2C_INDEX nID){
+ csif_uint32 s2c_ovfl_status = 0;
+ CSIF_REG_READ(CSIF_S2C_IRQ_OVFL_STATUS + nID*CSIF_S2C_IRQ_OVFL_SIZE, s2c_ovfl_status);
+ return s2c_ovfl_status;
+}
+
+void CSIF_S2C_Overflow_Clear(CSIF_S2C_INDEX nID, csif_uint32 code){
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ // assertion of user setting code out of code limit
+ csif_uint32 code_limit = CSIF_S2C_Interrupt_Num[nID];
+ CSIF_ASSERT(code < code_limit, nID, code, code_limit);
+ CSIF_REG_WRITE(CSIF_S2C_IRQ_OVFL_CLR + nID*CSIF_S2C_IRQ_OVFL_SIZE, 1 << code);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(nID, (csif_uint32*)(CSIF_S2C_IRQ_OVFL_CLR + nID*CSIF_S2C_IRQ_OVFL_SIZE), 1 << code, caller);
+#endif /* __CSIF_DEBUG__ */
+}
+
+csif_uint32 CSIF_C2S_Overflow_Read(CSIF_C2S_INDEX nID){
+ csif_uint32 c2s_ovfl_status = 0;
+ CSIF_REG_READ(CSIF_C2S_IRQ_OVFL_STATUS + nID*CSIF_C2S_IRQ_OVFL_SIZE, c2s_ovfl_status);
+ return c2s_ovfl_status;
+}
+
+void CSIF_C2S_Overflow_Clear(CSIF_C2S_INDEX nID, csif_uint32 code){
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ // assertion of user setting code out of code limit
+ csif_uint32 code_limit = CSIF_C2S_Interrupt_Num[nID];
+ CSIF_ASSERT(code < code_limit, nID, code, code_limit);
+ CSIF_REG_WRITE(CSIF_C2S_IRQ_OVFL_CLR + nID*CSIF_C2S_IRQ_OVFL_SIZE, 1 << code);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(nID, (csif_uint32*)(CSIF_C2S_IRQ_OVFL_CLR + nID*CSIF_C2S_IRQ_OVFL_SIZE), 1 << code, caller);
+#endif /* __CSIF_DEBUG__ */
+}
+
+void CSIF_MPU_Set(CSIF_MPU_ENUM_T mpuID, csif_uint32 start, csif_uint32 range, CSIF_MPU_TYPE_ENUM_T type){
+#if 0
+/* under construction !*/
+#if defined(__CSIF_DEBUG__)
+/* under construction !*/
+/* under construction !*/
+#endif /* __CSIF_DEBUG__ */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__CSIF_DEBUG__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /* __CSIF_DEBUG__ */
+#endif
+}
+
+csif_uint32 CSIF_CORE_IDLE_Read(void){
+ csif_uint32 core_idle = 0;
+ CSIF_REG_READ(CSIF_CORE_IDLE, core_idle);
+ return core_idle;
+}
+
+csif_uint32 CSIF_IDLE_ENABLE_Read(CSIF_S2C_INDEX nID){
+ csif_uint32 idle_enable = 0;
+ CSIF_REG_READ(CSIF_S2C_IDLE_IRQ_ENABLE + nID*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, idle_enable);
+ return idle_enable;
+}
+
+void CSIF_IDLE_ENABLE_Set(CSIF_S2C_INDEX nID, csif_uint32 enable_map){
+ CSIF_ASSERT(nID < CSIF_S2C_IDLE_IRQ_NUM, nID, enable_map, 0);
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_SET + nID*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, enable_map);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(nID, (csif_uint32*)(CSIF_S2C_IDLE_IRQ_ENABLE_SET + nID*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE), enable_map, caller);
+#endif /* __CSIF_DEBUG__ */
+}
+
+void CSIF_IDLE_ENABLE_Clr(CSIF_S2C_INDEX nID, csif_uint32 clr_bit_map){
+ CSIF_ASSERT(nID < CSIF_S2C_IDLE_IRQ_NUM, nID, clr_bit_map, 0);
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ CSIF_REG_WRITE(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + nID*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE, clr_bit_map);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(nID, (csif_uint32*)(CSIF_S2C_IDLE_IRQ_ENABLE_CLR + nID*CSIF_S2C_IDLE_IRQ_ENABLE_SIZE), clr_bit_map, caller);
+#endif /* __CSIF_DEBUG__ */
+}
+
+//************ mailbox related feature *************//
+void CSIF_MAILBOX_C2S_Send(CSIF_MAILBOX_C2S_INDEX mID, csif_uint32 mail)
+{
+ if(mail == CSIF_MAILBOX_EMPTY_VALUE || mail == CSIF_MAILBOX_ERROR_VALUE){
+ CSIF_ASSERT(0, mID, mail, 0);
+ return;
+ }
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ CSIF_REG_WRITE(CSIF_MAILBOX_SEND + mID*CSIF_MAILBOX_SIZE, mail);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(mID, (csif_uint32*)(CSIF_MAILBOX_SEND + mID*CSIF_MAILBOX_SIZE), mail, caller);
+#endif /* __CSIF_DEBUG__ */
+}
+
+
+
+CSIF_MAILBOX_STATUS_t CSIF_MAILBOX_C2S_Status_Read(CSIF_MAILBOX_C2S_INDEX mID)
+{
+ CSIF_MAILBOX_STATUS_t read_status_struct;
+ csif_uint32 read_status = 0;
+ CSIF_REG_READ(CSIF_MAILBOX_STATUS + mID*CSIF_MAILBOX_SIZE, read_status);
+ //printf("read mailbox %d status: %x\n", mID, read_status);
+ if(csif_mailbox_entry_num_table[mID] == 256)
+ {
+ read_status_struct.r_idx = (read_status & CSIF_MAILBOX_256_STATUS_R_IDX_M) >> CSIF_MAILBOX_256_STATUS_R_IDX_P;
+ read_status_struct.w_idx = (read_status & CSIF_MAILBOX_256_STATUS_W_IDX_M) >> CSIF_MAILBOX_256_STATUS_W_IDX_P;
+ read_status_struct.mail_num = (read_status & CSIF_MAILBOX_256_STATUS_MAIL_NUM_M) >> CSIF_MAILBOX_256_STATUS_MAIL_NUM_P;
+ }
+ else if(csif_mailbox_entry_num_table[mID] == 64)
+ {
+ read_status_struct.r_idx = (read_status & CSIF_MAILBOX_64_STATUS_R_IDX_M) >> CSIF_MAILBOX_64_STATUS_R_IDX_P;
+ read_status_struct.w_idx = (read_status & CSIF_MAILBOX_64_STATUS_W_IDX_M) >> CSIF_MAILBOX_64_STATUS_W_IDX_P;
+ read_status_struct.mail_num = (read_status & CSIF_MAILBOX_64_STATUS_MAIL_NUM_M) >> CSIF_MAILBOX_64_STATUS_MAIL_NUM_P;
+ }
+ else
+ {
+ // undefined CSIF mailbox entry num
+ CSIF_ASSERT(0, mID, csif_mailbox_entry_num_table[mID], 0);
+ }
+ if(csif_mailbox_entry_num_table[mID] == 256)
+ {
+ read_status_struct.r_idx = read_status_struct.r_idx & MAILBOX_256_WRAP_MASK;
+ read_status_struct.w_idx = read_status_struct.w_idx & MAILBOX_256_WRAP_MASK;
+ }
+ else if(csif_mailbox_entry_num_table[mID] == 64)
+ {
+ read_status_struct.r_idx = read_status_struct.r_idx & MAILBOX_64_WRAP_MASK;
+ read_status_struct.w_idx = read_status_struct.w_idx & MAILBOX_64_WRAP_MASK;
+ }
+ return read_status_struct;
+}
+
+csif_uint32 CSIF_MAILBOX_C2S_Max_FIFO_Usage_Read(CSIF_MAILBOX_C2S_INDEX mID)
+{
+ csif_uint32 max_record = 0;
+ CSIF_REG_READ(CSIF_MAILBOX_MAX_FIFO_USAGE + mID*CSIF_MAILBOX_SIZE, max_record);
+ return max_record;
+}
+
+// for MCU L1 LPWR debug feature, not normal case
+csif_uint32 CSIF_MAILBOX_C2S_Read(CSIF_MAILBOX_C2S_INDEX mID)
+{
+ csif_uint32 read_mail = 0;
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ CSIF_REG_READ(CSIF_MAILBOX_RECV + mID*CSIF_MAILBOX_SIZE, read_mail);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(mID, (csif_uint32*)(CSIF_MAILBOX_RECV + mID*CSIF_MAILBOX_SIZE), read_mail, caller);
+#endif /* __CSIF_DEBUG__ */
+ return read_mail;
+}
+// ----------------------------------------------- //
+
+csif_uint32 CSIF_MAILBOX_S2C_Read(CSIF_MAILBOX_S2C_INDEX mID)
+{
+ csif_uint32 read_mail = 0;
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+ CSIF_REG_READ(CSIF_MAILBOX_RECV + mID*CSIF_MAILBOX_SIZE, read_mail);
+#if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord(mID, (csif_uint32*)(CSIF_MAILBOX_RECV + mID*CSIF_MAILBOX_SIZE), read_mail, caller);
+#endif /* __CSIF_DEBUG__ */
+ return read_mail;
+}
+
+CSIF_MAILBOX_STATUS_t CSIF_MAILBOX_S2C_Status_Read(CSIF_MAILBOX_S2C_INDEX mID)
+{
+ CSIF_MAILBOX_STATUS_t read_status_struct;
+ csif_uint32 read_status = 0;
+ CSIF_REG_READ(CSIF_MAILBOX_STATUS + mID*CSIF_MAILBOX_SIZE, read_status);
+ if(csif_mailbox_entry_num_table[mID] == 256)
+ {
+ read_status_struct.r_idx = (read_status & CSIF_MAILBOX_256_STATUS_R_IDX_M) >> CSIF_MAILBOX_256_STATUS_R_IDX_P;
+ read_status_struct.w_idx = (read_status & CSIF_MAILBOX_256_STATUS_W_IDX_M) >> CSIF_MAILBOX_256_STATUS_W_IDX_P;
+ read_status_struct.mail_num = (read_status & CSIF_MAILBOX_256_STATUS_MAIL_NUM_M) >> CSIF_MAILBOX_256_STATUS_MAIL_NUM_P;
+ }
+ else if(csif_mailbox_entry_num_table[mID] == 64)
+ {
+ read_status_struct.r_idx = (read_status & CSIF_MAILBOX_64_STATUS_R_IDX_M) >> CSIF_MAILBOX_64_STATUS_R_IDX_P;
+ read_status_struct.w_idx = (read_status & CSIF_MAILBOX_64_STATUS_W_IDX_M) >> CSIF_MAILBOX_64_STATUS_W_IDX_P;
+ read_status_struct.mail_num = (read_status & CSIF_MAILBOX_64_STATUS_MAIL_NUM_M) >> CSIF_MAILBOX_64_STATUS_MAIL_NUM_P;
+ }
+ else
+ {
+ // undefined CSIF mailbox entry num
+ CSIF_ASSERT(0, mID, csif_mailbox_entry_num_table[mID], 0);
+ }
+ if(csif_mailbox_entry_num_table[mID] == 256)
+ {
+ read_status_struct.r_idx = read_status_struct.r_idx & MAILBOX_256_WRAP_MASK;
+ read_status_struct.w_idx = read_status_struct.w_idx & MAILBOX_256_WRAP_MASK;
+ }
+ else if(csif_mailbox_entry_num_table[mID] == 64)
+ {
+ read_status_struct.r_idx = read_status_struct.r_idx & MAILBOX_64_WRAP_MASK;
+ read_status_struct.w_idx = read_status_struct.w_idx & MAILBOX_64_WRAP_MASK;
+ }
+ return read_status_struct;
+}
+
+csif_uint32 CSIF_MAILBOX_S2C_Max_FIFO_Usage_Read(CSIF_MAILBOX_S2C_INDEX mID)
+{
+ csif_uint32 max_record = 0;
+ CSIF_REG_READ(CSIF_MAILBOX_MAX_FIFO_USAGE + mID*CSIF_MAILBOX_SIZE, max_record);
+ return max_record;
+}
+
+void CSIF_OLPDET_Set(csif_uint32 addr, csif_uint32 size)
+{
+ addr = addr & CSIF_DSM_MASK;
+ CSIF_ASSERT(((addr & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size >= 0) && (size <= 1024 )), addr, size, 0);
+ CSIF_ASSERT(((addr >= 0) && (addr <= CSIF_DSM_SIZE)), addr, size, 0);
+ CSIF_ASSERT((addr+size <= CSIF_DSM_SIZE), addr, size, 0);
+
+ csif_uint32 two_word_addr = 0;
+ csif_uint32 two_word_size = 0;
+ csif_uint32 set_value = 0;
+
+ // covert to 2 word unit
+ two_word_addr = addr/CSIF_OLPDET_UNIT;
+ two_word_size = size/CSIF_OLPDET_UNIT;
+ set_value = (two_word_addr << CSIF_OLPDET_SET_OFFSET_P) | (two_word_size << CSIF_OLPDET_SET_LENGTH_P);
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+
+#if !defined(MT6297) || defined(__CSIF_PROFILING__) // not Apollo, use normal OLPDET set/clr flow
+//#if !defined(MT6297) // not Apollo, use normal OLPDET set/clr flow
+ CSIF_REG_WRITE(CSIF_OLPDET_SET, set_value);
+ #if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord((size << 16 | addr), (csif_uint32*)(CSIF_OLPDET_SET), set_value, caller);
+ #endif /* __CSIF_DEBUG__ */
+#else // Apollo, for Apollo OLPDET HW bug
+ /* Use HWITC to create critical section.
+ Note that we use a special light-weight ITC Macro here to avoid
+ CHRT domain cannot DI fatal error.
+ It is a SS internal API, and does not do timing violation check.
+ Need SS's approval before using it */
+ kal_uint32 irq_mask=0, mt_mask=0, ori_prio=0;
+ KAL_ITC_LOCK_TAKE_DI_DMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+ d2d_wreg32(CSIF_OLPDET_SET, set_value);
+ /* Release HWITC */
+ KAL_ITC_LOCK_GIVE_EI_EMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+ #if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord((D2D_DEBUG_RECORD_PREFIX | size << 16 | addr), (csif_uint32*)(CSIF_OLPDET_SET), set_value, caller);
+ #endif /* __CSIF_DEBUG__ */
+#endif // end of proj option
+}
+
+void CSIF_OLPDET_Clr(csif_uint32 addr, csif_uint32 size)
+{
+ addr = addr & CSIF_DSM_MASK;
+ CSIF_ASSERT(((addr & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size >= 0) && (size <= 1024 )), addr, size, 0);
+ CSIF_ASSERT(((addr >= 0) && (addr <= CSIF_DSM_SIZE)), addr, size, 0);
+ CSIF_ASSERT((addr+size <= CSIF_DSM_SIZE), addr, size, 0);
+
+ csif_uint32 two_word_addr = 0;
+ csif_uint32 two_word_size = 0;
+ csif_uint32 set_value = 0;
+
+ // covert to 2 word unit
+ two_word_addr = addr/CSIF_OLPDET_UNIT;
+ two_word_size = size/CSIF_OLPDET_UNIT;
+ set_value = (two_word_addr << CSIF_OLPDET_CLR_OFFSET_P) | (two_word_size << CSIF_OLPDET_CLR_LENGTH_P);
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+#if !defined(MT6297) || defined(__CSIF_PROFILING__) // not Apollo, use normal OLPDET set/clr flow
+//#if !defined(MT6297) // not Apollo, use normal OLPDET set/clr flow
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR, set_value);
+ #if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord((size << 16 | addr), (csif_uint32*)(CSIF_OLPDET_CLR), set_value, caller);
+ #endif /* __CSIF_DEBUG__ */
+#else // Apollo, for Apollo OLPDET HW bug
+ /* Use HWITC to create critical section.
+ Note that we use a special light-weight ITC Macro here to avoid
+ CHRT domain cannot DI fatal error.
+ It is a SS internal API, and does not do timing violation check.
+ Need SS's approval before using it */
+ kal_uint32 irq_mask=0, mt_mask=0, ori_prio=0;
+ KAL_ITC_LOCK_TAKE_DI_DMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+ d2d_wreg32(CSIF_OLPDET_CLR, set_value);
+ /* Release HWITC */
+ KAL_ITC_LOCK_GIVE_EI_EMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+ #if defined(__CSIF_DEBUG__)
+ csif_DebugAddRecord((D2D_DEBUG_RECORD_PREFIX | size << 16 | addr), (csif_uint32*)(CSIF_OLPDET_CLR), set_value, caller);
+ #endif /* __CSIF_DEBUG__ */
+#endif // end of proj option
+}
+
+csif_uint32 CSIF_Total_Inuse_Mem_Size()
+{
+ csif_uint32 read_size;
+ CSIF_REG_READ(CSIF_OLPDET_INUSE_MAIL_SIZE, read_size);
+ return (read_size * CSIF_OLPDET_UNIT);
+}
+
+#if defined(MT6885) || defined(MT6873) || defined(MERCURY)
+csif_uint32 CSIF_Total_Max_Mem_Size()
+{
+ csif_uint32 read_size;
+ CSIF_REG_READ(CSIF_OLPDET_MAX_MAIL_SIZE, read_size);
+ return (read_size * CSIF_OLPDET_UNIT);
+}
+
+void CSIF_Total_Max_Mem_Size_Clear()
+{
+ CSIF_REG_WRITE(CSIF_OLPDET_MAX_MAIL_SIZE_CLR, 0x1);
+}
+#elif defined(MT6297)
+#else
+ #error "unsupport project, may need porting"
+#endif
+
+void CSIF_OLPDET_Multiple_Set(csif_uint32 length, CSIF_OLPDET_CONFIG_t* olpdet_config_array)
+{
+ csif_uint32 idx = 0;
+ csif_uint32 two_word_addr = 0;
+ csif_uint32 two_word_size = 0;
+ csif_uint32 set_value = 0;
+ csif_uint32 addr = 0;
+ csif_uint32 size = 0;
+
+#if defined(MT6297) && !defined(__CSIF_PROFILING__) // Apollo, for Apollo OLPDET HW bug
+ kal_uint32 irq_mask=0, mt_mask=0, ori_prio=0;
+#endif
+
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 multiIdx = kal_atomic_inc_return(&MultiOperation_debug_idx);
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+
+ CSIF_ASSERT((length >= 1 ), length, (csif_uint32)&olpdet_config_array, 0);
+
+ for(idx = 0; idx < length; idx++){
+ addr = (olpdet_config_array[idx].addr) & CSIF_DSM_MASK;
+ size = (olpdet_config_array[idx].size);
+ CSIF_ASSERT(((addr & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size >= 0) && (size <= 1024 )), addr, size, 0);
+ CSIF_ASSERT(((addr >= 0) && (addr <= CSIF_DSM_SIZE)), addr, size, 0);
+ CSIF_ASSERT((addr+size <= CSIF_DSM_SIZE), addr, size, 0);
+ // covert to 2 word unit
+ two_word_addr = addr/CSIF_OLPDET_UNIT;
+ two_word_size = size/CSIF_OLPDET_UNIT;
+ set_value = (two_word_addr << CSIF_OLPDET_SET_OFFSET_P) | (two_word_size << CSIF_OLPDET_SET_LENGTH_P);
+#if !defined(MT6297) || defined(__CSIF_PROFILING__) // not Apollo, use normal OLPDET set/clr flow
+//#if !defined(MT6297) // not Apollo, use normal OLPDET set/clr flow
+ if(idx == length - 1){
+ CSIF_REG_WRITE(CSIF_OLPDET_SET, set_value); // last operation, use bank A and MO_sync()
+ }else{
+ CSIF_REG_WRITE_BANKB(CSIF_OLPDET_SET, set_value); // continous operation, use bank B without MO_sync()
+ }
+ #if defined(__CSIF_DEBUG__)
+ csif_MultiDebugAddRecord(multiIdx, (csif_uint32*)(CSIF_OLPDET_SET), set_value, caller);
+ #endif /* __CSIF_DEBUG__ */
+#else // Apollo, for Apollo OLPDET HW bug
+ /* Use HWITC to create critical section.
+ Note that we use a special light-weight ITC Macro here to avoid
+ CHRT domain cannot DI fatal error.
+ It is a SS internal API, and does not do timing violation check.
+ Need SS's approval before using it */
+ KAL_ITC_LOCK_TAKE_DI_DMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+ d2d_wreg32(CSIF_OLPDET_SET, set_value);
+ /* Release HWITC */
+ KAL_ITC_LOCK_GIVE_EI_EMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+ #if defined(__CSIF_DEBUG__)
+ csif_MultiDebugAddRecord((D2D_DEBUG_RECORD_PREFIX | multiIdx), (csif_uint32*)(CSIF_OLPDET_SET), set_value, caller);
+ #endif /* __CSIF_DEBUG__ */
+#endif // end of proj option
+ }
+}
+
+void CSIF_OLPDET_Multiple_Clr(csif_uint32 length, CSIF_OLPDET_CONFIG_t* olpdet_config_array)
+{
+ csif_uint32 idx = 0;
+ csif_uint32 two_word_addr = 0;
+ csif_uint32 two_word_size = 0;
+ csif_uint32 set_value = 0;
+ csif_uint32 addr = 0;
+ csif_uint32 size = 0;
+
+#if defined(MT6297) && !defined(__CSIF_PROFILING__) // Apollo, for Apollo OLPDET HW bug
+ kal_uint32 irq_mask=0, mt_mask=0, ori_prio=0;
+#endif
+
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 multiIdx = kal_atomic_inc_return(&MultiOperation_debug_idx);
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+
+ CSIF_ASSERT((length >= 1 ), length, (csif_uint32)&olpdet_config_array, 0);
+
+ for(idx = 0; idx < length; idx++){
+ addr = (olpdet_config_array[idx].addr) & CSIF_DSM_MASK;
+ size = (olpdet_config_array[idx].size);
+ CSIF_ASSERT(((addr & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size & CSIF_OLPDET_UNIT_MASK) == 0), addr, size, 0);
+ CSIF_ASSERT(((size >= 0) && (size <= 1024 )), addr, size, 0);
+ CSIF_ASSERT(((addr >= 0) && (addr <= CSIF_DSM_SIZE)), addr, size, 0);
+ CSIF_ASSERT((addr+size <= CSIF_DSM_SIZE), addr, size, 0);
+ // covert to 2 word unit
+ two_word_addr = addr/CSIF_OLPDET_UNIT;
+ two_word_size = size/CSIF_OLPDET_UNIT;
+ set_value = (two_word_addr << CSIF_OLPDET_CLR_OFFSET_P) | (two_word_size << CSIF_OLPDET_CLR_LENGTH_P);
+#if !defined(MT6297) || defined(__CSIF_PROFILING__) // not Apollo, use normal OLPDET set/clr flow
+//#if !defined(MT6297) // not Apollo, use normal OLPDET set/clr flow
+ if(idx == length - 1){
+ CSIF_REG_WRITE(CSIF_OLPDET_CLR, set_value); // last operation, use bank A and MO_sync()
+ }else{
+ CSIF_REG_WRITE_BANKB(CSIF_OLPDET_CLR, set_value); // continous operation, use bank B without MO_sync()
+ }
+#if defined(__CSIF_DEBUG__)
+ csif_MultiDebugAddRecord(multiIdx, (csif_uint32*)(CSIF_OLPDET_CLR), set_value, caller);
+#endif /* __CSIF_DEBUG__ */
+#else // Apollo, for Apollo OLPDET HW bug
+ /* Use HWITC to create critical section.
+ Note that we use a special light-weight ITC Macro here to avoid
+ CHRT domain cannot DI fatal error.
+ It is a SS internal API, and does not do timing violation check.
+ Need SS's approval before using it */
+ KAL_ITC_LOCK_TAKE_DI_DMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+ d2d_wreg32(CSIF_OLPDET_CLR, set_value);
+ /* Release HWITC */
+ KAL_ITC_LOCK_GIVE_EI_EMT_PRIO(olpdet_lock, irq_mask, mt_mask, ori_prio);
+ #if defined(__CSIF_DEBUG__)
+ csif_MultiDebugAddRecord((D2D_DEBUG_RECORD_PREFIX | multiIdx), (csif_uint32*)(CSIF_OLPDET_CLR), set_value, caller);
+ #endif /* __CSIF_DEBUG__ */
+#endif // end of proj option
+ }
+}
+
+void CSIF_MAILBOX_C2S_Multiple_Send(csif_uint32 length, CSIF_MAIL_INFO_t* mail_info_array)
+{
+ csif_uint32 idx = 0;
+ csif_uint32 mID = 0;
+ csif_uint32 mail = 0;
+
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 multiIdx = kal_atomic_inc_return(&MultiOperation_debug_idx);
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+
+ CSIF_ASSERT((length >= 1 ), length, (csif_uint32)&mail_info_array, 0);
+ for(idx = 0; idx < length; idx++){
+ mID = mail_info_array[idx].mID;
+ mail = mail_info_array[idx].mail;
+ if(mail == CSIF_MAILBOX_EMPTY_VALUE || mail == CSIF_MAILBOX_ERROR_VALUE){
+ CSIF_ASSERT(0, mID, mail, 0);
+ return;
+ }
+ if(idx == length - 1){
+ CSIF_REG_WRITE((CSIF_MAILBOX_SEND + (mID*CSIF_MAILBOX_SIZE)), mail); // last operation, use bank A and MO_sync()
+ }else{
+ CSIF_REG_WRITE_BANKB((CSIF_MAILBOX_SEND + (mID*CSIF_MAILBOX_SIZE)), mail); // continous operation, use bank B without MO_sync()
+ }
+#if defined(__CSIF_DEBUG__)
+ csif_MultiDebugAddRecord(multiIdx, (csif_uint32*)(CSIF_MAILBOX_SEND + (mID*CSIF_MAILBOX_SIZE)), mail, caller);
+#endif /* __CSIF_DEBUG__ */
+ }
+}
+
+void CSIF_MAILBOX_C2S_Multiple_Send_C2S_SWI_Multiple_Set(csif_uint32 mailbox_length, CSIF_MAIL_INFO_t* mail_info_array, \
+ csif_uint32 irq_length, CSIF_IRQ_INFO_t* irq_info_array)
+{
+ csif_uint32 idx = 0;
+ csif_uint32 mID = 0;
+ csif_uint32 mail = 0;
+
+ csif_uint32 before_status = 0xFFFFFFFF;
+ csif_uint32 nID = 0;
+ csif_uint32 code = 0;
+ csif_uint32 code_limit = 0;
+
+#if defined(__CSIF_DEBUG__)
+ csif_uint32 multiIdx = kal_atomic_inc_return(&MultiOperation_debug_idx);
+ csif_uint32 caller;
+ CSIF_GET_RETURN_ADDRESS(caller);
+#endif /* __CSIF_DEBUG__ */
+
+ CSIF_ASSERT((mailbox_length >= 1 ), mailbox_length, (csif_uint32)&mail_info_array, 0);
+ CSIF_ASSERT((irq_length >= 1 ), irq_length, (csif_uint32)&irq_info_array, 0);
+ // Mailbox multiple send
+ for(idx = 0; idx < mailbox_length; idx++)
+ {
+ mID = mail_info_array[idx].mID;
+ mail = mail_info_array[idx].mail;
+ if(mail == CSIF_MAILBOX_EMPTY_VALUE || mail == CSIF_MAILBOX_ERROR_VALUE){
+ CSIF_ASSERT(0, mID, mail, 0);
+ return;
+ }
+ CSIF_REG_WRITE_BANKB((CSIF_MAILBOX_SEND + (mID*CSIF_MAILBOX_SIZE)), mail); // continous operation, use bank B without MO_sync()
+#if defined(__CSIF_DEBUG__)
+ csif_MultiDebugAddRecord(multiIdx, (csif_uint32*)(CSIF_MAILBOX_SEND + (mID*CSIF_MAILBOX_SIZE)), mail, caller);
+#endif /* __CSIF_DEBUG__ */
+ }
+ // IRQ multiple set
+ for(idx = 0; idx < irq_length; idx++)
+ {
+ nID = irq_info_array[idx].nID;
+ code = irq_info_array[idx].code;
+
+ // assertion of user setting code out of code limit
+ code_limit = CSIF_C2S_Interrupt_Num[nID];
+ CSIF_ASSERT(code < code_limit, nID, code, code_limit);
+
+ // no need this special handle in Mercury if HW support IRQ ovfl enable switch
+ if(csif_c2s_irq_ovfl_allow[nID][code] == CSIF_TRUE)
+ {
+ if(idx == irq_length - 1)
+ {
+ CSIF_REG_WRITE((CSIF_C2S_IRQ_SET + (nID*CSIF_C2S_IRQ_SIZE)), 1 << code); // last operation, use bank A and MO_sync()
+ }else
+ {
+ CSIF_REG_WRITE_BANKB((CSIF_C2S_IRQ_SET + (nID*CSIF_C2S_IRQ_SIZE)), 1 << code); // continous operation, use bank B without MO_sync()
+ }
+
+ }else
+ {
+ // Use HWITC to create critical section
+ kal_hrt_take_itc_lock(KAL_ITC_CSIF_LOCK, KAL_INFINITE_WAIT);
+ /* end of HWITC take */
+ CSIF_REG_READ(CSIF_C2S_IRQ_STATUS + nID*CSIF_C2S_IRQ_SIZE, before_status);
+ if((before_status & (1 << code)) == 0){
+ if(idx == irq_length - 1)
+ {
+ CSIF_REG_WRITE((CSIF_C2S_IRQ_SET + (nID*CSIF_C2S_IRQ_SIZE)), 1 << code); // last operation, use bank A and MO_sync()
+ }else
+ {
+ CSIF_REG_WRITE_BANKB((CSIF_C2S_IRQ_SET + (nID*CSIF_C2S_IRQ_SIZE)), 1 << code); // continous operation, use bank B without MO_sync()
+ }
+ /* Release HWITC */
+ kal_hrt_give_itc_lock(KAL_ITC_CSIF_LOCK);
+ }
+ else{
+ /* Release HWITC */
+ kal_hrt_give_itc_lock(KAL_ITC_CSIF_LOCK);
+ CSIF_ASSERT((before_status & (1 << code)) == 0, nID, code, 0);
+ //CSIF_REG_WRITE(CSIF_C2S_IRQ_SET + nID*CSIF_C2S_IRQ_SIZE, 1 << code);
+ }
+ }
+#if defined(__CSIF_DEBUG__)
+ csif_MultiDebugAddRecord(multiIdx, (csif_uint32*)(CSIF_C2S_IRQ_SET + (nID*CSIF_C2S_IRQ_SIZE)), 1 << code, caller);
+#endif /* __CSIF_DEBUG__ */
+ }
+}
+//**** mailbox debug usage ****//
+
+
+//**** CSIF test ****//
+#if defined(__CSIF_DRV_TEST__)
+void CSIF_Test(CSIF_ID_STATUS_t* status_id){
+
+}
+#endif