[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/driver/peripheral/inc/accdet_hw.h b/mcu/driver/peripheral/inc/accdet_hw.h
new file mode 100644
index 0000000..0cbdcc8
--- /dev/null
+++ b/mcu/driver/peripheral/inc/accdet_hw.h
@@ -0,0 +1,105 @@
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifndef ACCDET_HW_H
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif //ACCDET_HW_H
+/* under construction !*/
+#endif
diff --git a/mcu/driver/peripheral/inc/accdet_sw.h b/mcu/driver/peripheral/inc/accdet_sw.h
new file mode 100644
index 0000000..66a9a26
--- /dev/null
+++ b/mcu/driver/peripheral/inc/accdet_sw.h
@@ -0,0 +1,158 @@
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#ifndef ACCDET_SW_H
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_ACCDET_REG_DBG__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_ACCDET_REG_DBG__)
+#endif//#define ACCDET_SW_H
+/* under construction !*/
+#endif//#define ACCDET_SW_H
diff --git a/mcu/driver/peripheral/inc/adc_hw.h b/mcu/driver/peripheral/inc/adc_hw.h
new file mode 100644
index 0000000..ea81b64
--- /dev/null
+++ b/mcu/driver/peripheral/inc/adc_hw.h
@@ -0,0 +1,420 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * adc_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for adc driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _ADC_HW_H
+#define _ADC_HW_H
+#include "drv_features_adc.h"
+#include "drvpdn.h"
+
+#if defined(DRV_ADC_6236_SERIES)
+/*
+MT6236 BASE=0x801c_0000
+Check bit of ADC (1b) *(BASE+0x0020)[13]=[333]
+ADC_B (6b) *(BASE+0x0020)[12:7]=[332:327]
+ADC_A (7b) *(BASE+0x0020)[6:0]=[326:320]
+*/
+#define EFUSE_ADC_BASE 0x801c0020
+#define EFUSE_ADC_A 0x801c0020
+#define EFUSE_ADC_B 0x801c0020
+#define EFUSE_ADC_ENABLE 0x2000
+#define EFUSE_ADC_A_MASK 0x7F
+#define EFUSE_ADC_B_MASK 0x1F80
+#define EFUSE_ADC_A_SHIFT 0
+#define EFUSE_ADC_B_SHIFT 7
+
+#elif defined(DRV_ADC_6252_SERIES)
+/*
+MT6252 BASE=0x8000_0000
+Check bit of ADC (1b), *(BASE+0x0020)[13]=[333]
+ADC_B (6b), *(BASE+0x0020)[12:7]=[332:327]
+ADC_A (7b), *(BASE+0x0020)[6:0]=[326:320]
+*/
+#define EFUSE_ADC_BASE 0x80000020
+#define EFUSE_ADC_A 0x80000020
+#define EFUSE_ADC_B 0x80000020
+#define EFUSE_ADC_ENABLE 0x2000
+#define EFUSE_ADC_A_MASK 0x7F
+#define EFUSE_ADC_B_MASK 0x1F80
+#define EFUSE_ADC_A_SHIFT 0
+#define EFUSE_ADC_B_SHIFT 7
+
+#elif defined(DRV_ADC_6251_SERIES)
+
+#define EFUSE_ADC_BASE 0x80000100
+#define EFUSE_ADC_A 0x80000100
+#define EFUSE_ADC_B 0x80000100
+#define EFUSE_ADC_ENABLE 0x0002
+#define EFUSE_ADC_A_MASK 0x7FC00
+#define EFUSE_ADC_B_MASK 0x3FC
+#define EFUSE_ADC_A_SHIFT 10
+#define EFUSE_ADC_B_SHIFT 2
+
+#elif defined(DRV_ADC_6256_SERIES)
+
+#define EFUSE_ADC_BASE 0x80000100
+#define EFUSE_ADC_A 0x80000100
+#define EFUSE_ADC_B 0x80000100
+#define EFUSE_ADC_ENABLE 0x0002
+#define EFUSE_ADC_A_MASK 0x7FC00
+#define EFUSE_ADC_B_MASK 0x3FC
+#define EFUSE_ADC_A_SHIFT 10
+#define EFUSE_ADC_B_SHIFT 2
+
+#elif defined(DRV_ADC_6575_SERIES)
+
+#define EFUSE_ADC_BASE 0xC1019040
+#define EFUSE_ADC_ENABLE 0x0
+#define EFUSE_O_VBG 0xC1019040
+#define EFUSE_O_VBG_MASK 0x1FF00
+#define EFUSE_O_VBG_SHIFT 0x8
+#define EFUSE_ADC_OE 0xC1019044
+#define EFUSE_ADC_OE_MASK 0xFF
+#define EFUSE_ADC_OE_SHIFT 0
+#define EFUSE_ADC_GE 0xC1019048
+#define EFUSE_ADC_GE_MASK 0xFF
+#define EFUSE_ADC_GE_SHIFT 0
+
+#define TS_CON1 0xC0007804
+#define TS_CON2 0xC0007808
+
+#elif defined(DRV_ADC_6250_SERIES) // 10 bits ADC
+
+#define EFUSE_ADC_BASE 0xA01C0200
+#define EFUSE_ADC_A 0xA01C0200
+#define EFUSE_ADC_B 0xA01C0200
+#define EFUSE_ADC_ENABLE 0x0002
+#define EFUSE_ADC_A_MASK 0x1FC00 // 7 bits
+#define EFUSE_ADC_B_MASK 0xFC // 6 bits
+#define EFUSE_ADC_A_SHIFT 10
+#define EFUSE_ADC_B_SHIFT 2
+
+
+#else
+/*
+1. Check bit of ADC (1b), *(0x80000020)[18]=[210]
+2. ADC_B (6b), *(0x80000020)[17:12]=[209:204]
+3. ADC_A (7b), *(0x80000020)[11:5]=[203:197]
+*/
+#define EFUSE_ADC_BASE 0x80000020
+#define EFUSE_ADC_A 0x80000020
+#define EFUSE_ADC_B 0x80000020
+#define EFUSE_ADC_ENABLE 0x40000
+#define EFUSE_ADC_A_MASK 0xFE0
+#define EFUSE_ADC_B_MASK 0x3F000
+#define EFUSE_ADC_A_SHIFT 5
+#define EFUSE_ADC_B_SHIFT 12
+
+#endif
+
+#if defined(DRV_ADC_LIMIT_REG) || defined(FPGA)
+#if !defined(DRV_ADC_OFF)
+ /*******************
+ * GPADC Registers *
+ *******************/
+ #define AUXADC_DATA (AUXADC_base+0x0000) /* Sampled data */
+ #define AUXADC_CTRL (AUXADC_base+0x0004) /* Control of A/D Converter */
+ #define AUXADC_STAT (AUXADC_base+0x0008) /* A/D Status..reg=0,if write AUXADC_CTRL reg*/
+ #define AUXADC_CTRL2 (AUXADC_base+0x000c) /* Special Control of A/D Converter */
+
+ #define AUXADC_STAT_RDY 0x0001 /*ADC ready*/
+
+ #define AUXADC_CTRL2_CALI 0x0001 /*ADC Calibration*/
+ #define AUXADC_CTRL2_MON 0x0020 /*DACMON*/
+ #define AUXADC_CTRL2_BYP 0x0040 /*DACBYP*/
+#endif // #if !defined(DRV_ADC_OFF)
+
+ /*ADC pin selection, ADC phy. channel*/
+
+ #define ADC_MAX_CHANNEL 5
+ #define ADC_ERR_CHANNEL_NO 50
+#endif /*(DRV_ADC_LIMIT_REG,FPGA)*/
+/*************************************************************************/
+#if defined(DRV_ADC_BASIC_REG)
+#if !defined(DRV_ADC_OFF)
+ #define AUXADC_SYNC (AUXADC_base+0x0000)
+ #define AUXADC_IMM (AUXADC_base+0x0004)
+#if defined(DRV_ADC_6575_SERIES)
+ #define AUXADC_CON1_SET (AUXADC_base+0x0008)
+ #define AUXADC_CON1_CLR (AUXADC_base+0x000C)
+ #define AUXADC_SYN (AUXADC_base+0x0010)
+ #define AUXADC_CON (AUXADC_base+0x0014)
+ #define AUXADC_DAT(_line) (AUXADC_base+0x0018+(4*_line))
+#else
+ #define AUXADC_SYN (AUXADC_base+0x0008)
+ #define AUXADC_CON (AUXADC_base+0x000c)
+ #define AUXADC_DAT(_line) (AUXADC_base+0x0010+(4*_line))
+#endif
+
+#if defined(DRV_ADC_6256_SERIES)
+ #define AUX_CON2 (PLL_base+0x1708)
+#else
+ #define AUX_CON2 (ABBSYS_base+0x8708)
+#endif
+
+#if defined(DRV_ADC_6250_SERIES)
+
+ #define ABBA_WR_PATH0 (ABBSYS_base + 0x0)
+ #define ABB_WR_PATH0 (ABB_D_base + 0x0010)
+ #define ABB_AUX_CON0 (ABB_D_base + 0x0028)
+ #define ABB_RSV_CON1 (ABB_D_base + 0x0004)
+ #define AUXADC_TS_CON (AUXADC_base + 0x0058)
+
+
+ #define ABBA_AUX_PWDB 0x0100
+ #define F26M_CLK_EN 0x8000
+ #define AUX_PWDB 0x0100
+ #define AUX_FIFO_CLK_EN 0x8000
+ #define AUX_FIFO_EN 0x0080
+ #define AUXADC_FSM_CTRL 0x0040
+ #define AUXADC_26M_CLK_CTRL 0x0004
+ #define AUXADC_TP_SPL 0x0001
+#endif
+
+ /*AUXADC_SYNC*/
+ #define AUXADC_SYNC_CHAN(_line) (0x0001<<_line) /*Time event 1*/
+
+ /*AUXADC_IMM*/
+ #define AUXADC_IMM_CHAN(_line) (0x0001<<_line)
+
+ /*AUXADC_SYN*/
+ #define AUXADC_SYN_BIT (0x0001) /*Time event 0*/
+
+ /*AUXADC_CON*/
+ #define AUXADC_CON_RUN (0x0001)
+#ifndef DRV_ADC_NO_TEST_DACMON
+ #define AUXADC_CON_CALI_MASK (0x007c)
+ #define AUXADC_CON_TESTDACMON (0x0080)
+#endif // #ifndef DRV_ADC_NO_TEST_DACMON
+#if defined(DRV_ADC_SW_RESET)
+ #define AUXADC_CON_SW_RESET (0x0080)
+#endif // #if defined(DRV_ADC_SW_RESET)
+ #define AUXADC_CON_AUTOCLR0 (0x0100)
+ #define AUXADC_CON_AUTOCLR1 (0x0200)
+ #define AUXADC_CON_PUWAIT_EN (0x0800)
+ #define AUXADC_CON_AUTOSET (0x8000)
+#endif // #if !defined(DRV_ADC_OFF)
+
+
+ #define ADC_ERR_CHANNEL_NO 50
+#endif /*(MT6205B,MT6218)*/
+
+#if ( defined(DRV_ADC_BASIC_REG) || defined(DRV_ADC_TDMA_TIME) )
+#if !defined(DRV_ADC_OFF)
+ #if defined(DRV_ADC_TDMA_EVENT_REG_POS1)
+ #define AUXADC_TDMA_EVENT0 (TDMA_base+0x1c0)
+ #define AUXADC_TDMA_EVENT1 (TDMA_base+0x1c4)
+ #elif defined(DRV_ADC_TDMA_EVENT_REG_POS2)
+ #define AUXADC_TDMA_EVENT0 (TDMA_base+0x400)
+
+ #if defined(MT6229_S00)
+ #define AUXADC_TDMA_EVENT1 (TDMA_base+0x400)/*HW bug*/
+ #else
+ #define AUXADC_TDMA_EVENT1 (TDMA_base+0x404)/**/
+ #endif
+
+ #else
+ #define AUXADC_TDMA_EVENT0 (TDMA_base+0x1b0)
+ #define AUXADC_TDMA_EVENT1 (TDMA_base+0x1b4)
+ #endif
+
+ #if defined(DRV_ADC_TDMA_EN_REG_POS1)
+ #define AUXADC_TDMA_EN (TDMA_base+0x16C)
+ #else
+ #define AUXADC_TDMA_EN (TDMA_base+0x164)
+ #endif
+ /*AUXADC_TDMA_EN*/
+ #define AUXADC_TDMA_EN_EVT0 (0x0001)
+ #define AUXADC_TDMA_EN_EVT1 (0x0002)
+#endif // #if !defined(DRV_ADC_OFF)
+#endif // #if ( defined(DRV_ADC_BASIC_REG) || defined(DRV_ADC_TDMA_TIME) )
+
+
+#if defined(__OLD_PDN_ARCH__)
+#if defined(ADC_CG_PDN_CON0)
+ #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (DRVPDN_CON0)
+ #define ADC_CG_PDN_CON_BIT (DRVPDN_CON0_AUXADC)
+ #elif defined(__CLKG_DEFINE__) // #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (CG_CON0)
+ #define ADC_CG_PDN_CON_BIT (CG_CON0_AUXADC)
+ #endif // #if defined(__OLD_PDN_DEFINE__)
+
+#elif defined(ADC_CG_PDN_CON1) // #if defined(ADC_CG_PDN_CON0)
+ #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (DRVPDN_CON1)
+ #define ADC_CG_PDN_CON_BIT (DRVPDN_CON1_AUXADC)
+ #elif defined(__CLKG_DEFINE__) // #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (CG_CON1)
+ #define ADC_CG_PDN_CON_BIT (CG_CON1_AUXADC)
+ #endif // #if defined(__OLD_PDN_DEFINE__)
+#elif defined(ADC_CG_PDN_CON3) // #if defined(ADC_CG_PDN_CON0)
+ #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (DRVPDN_CON3)
+ #define ADC_CG_PDN_CON_BIT (DRVPDN_CON3_AUXADC)
+ #elif defined(__CLKG_DEFINE__) // #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (CG_CON3)
+ #define ADC_CG_PDN_CON_BIT (CG_CON3_AUXADC)
+ #endif // #if defined(__OLD_PDN_DEFINE__)
+#else // #if defined(ADC_CG_PDN_CON0)
+ #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (DRVPDN_CON2)
+ #define ADC_CG_PDN_CON_BIT (DRVPDN_CON2_AUXADC)
+ #elif defined(__CLKG_DEFINE__) // #if defined(__OLD_PDN_DEFINE__)
+ #define ADC_CG_PDN_CON_ADDR (CG_CON2)
+ #define ADC_CG_PDN_CON_BIT (CG_CON2_AUXADC)
+ #endif // #if defined(__OLD_PDN_DEFINE__)
+#endif // #if defined(ADC_CG_PDN_CON0)
+#endif // #if defined(__OLD_PDN_ARCH__)
+
+
+#if defined(DRV_ADC_NOT_EXIST)
+ #define ADC_ERR_CHANNEL_NO 50
+#endif // #if defined(DRV_ADC_NOT_EXIST)
+
+#if !defined(DRV_ADC_OFF)
+#if !defined(ADC_MAX_CHANNEL)
+ #define ADC_MAX_CHANNEL 1
+ #define ADC_ERR_CHANNEL_NO 50
+#endif // #if defined(DRV_ADC_NOT_EXIST)
+#endif // #if !defined(DRV_ADC_OFF)
+
+#endif /*_ADC_HW_H*/
+
diff --git a/mcu/driver/peripheral/inc/adc_sw.h b/mcu/driver/peripheral/inc/adc_sw.h
new file mode 100644
index 0000000..28013bc
--- /dev/null
+++ b/mcu/driver/peripheral/inc/adc_sw.h
@@ -0,0 +1,234 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * adc_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for adc driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _ADC_SW_H
+#define _ADC_SW_H
+
+#include "drv_features_adc.h"
+#include "adc_hw.h"
+#include "adc_cali.h"
+
+typedef struct {
+ double ADC_ISENSE_RESISTANCE_FACTOR; /*1/0.4*/
+ ADC_CALIDATA adc_cali_param; /*ratio = adc_volt_factor/100*/
+ kal_uint16 adc_volt_factor[ADC_MAX_CHANNEL];
+}adc_customized_struct;
+
+typedef struct {
+ kal_int32 TEMPV2;
+ kal_int32 TEMPA12;
+ kal_int32 TEMPA23;
+ kal_int32 TEMPM12;
+ kal_int32 TEMPM23;
+ kal_int32 TEMPSCALE;
+} VolToTempStruct;
+
+typedef enum {
+ vbat_adc_channel=0,
+ visense_adc_channel,
+ vbattmp_adc_channel,
+ battype_adc_channel,
+ vcharger_adc_channel,
+ pcbtmp_adc_channel,
+ aux_adc_channel,
+ chr_usb_adc_channel,
+ otg_vbus_adc_channel,
+ rftmp_adc_channel
+} adc_channel_type;
+
+
+/*************************************************************************/
+#if defined(DRV_MISC_ADC_MEASURE_REMOVE_IRQMASK)
+// Define to perform ADC race condition check when processing critical data process
+#define ADC_RACE_CONDITION_CHECK
+// Define to remove IRQ mask/restore for ADC measurement
+#define ADC_REMOVE_IRQMASK
+#endif // #if defined(DRV_MISC_ADC_MEASURE_REMOVE_IRQMASK)
+
+#if defined(ADC_RACE_CONDITION_CHECK)
+extern kal_bool gADC_RC_Check;
+// MoDIS parser skip start
+// The following two APIs are private APIs, NOT exported as public APIs
+extern void ADCRCCheckAndLock(void);
+extern void ADCRCRelease(void);
+// MoDIS parser skip end
+#endif // #if defined(ADC_RACE_CONDITION_CHECK)
+
+#if defined(ADC_REMOVE_IRQMASK)
+#define ADCSAVEANDSETIRQMASK(mask) {}
+#define ADCRESTOREIRQMASK(mask) {}
+#else // #if defined(ADC_REMOVE_IRQMASK)
+#define ADCSAVEANDSETIRQMASK(mask) {mask = SaveAndSetIRQMask();}
+#define ADCRESTOREIRQMASK(mask) RestoreIRQMask(mask)
+#endif // #if defined(ADC_REMOVE_IRQMASK)
+
+/*************************************************************************/
+// MoDIS parser skip start
+// The following APIs are private APIs
+extern kal_uint16 ADC_GetData(kal_uint8 sel);
+// adc.c
+extern kal_uint16 ADC_IMM_Data(kal_uint16 channel);
+extern kal_uint16 ADC_SYNC_Data(kal_uint16 channel);
+extern void ADC_Init(void);
+extern void adc_pwrdown_enable(void);
+extern void adc_pwrdown_disable(void);
+extern kal_uint32 ADC_GetData2Meta(kal_uint8 sel, kal_uint16 meacount);
+extern kal_uint32 ADC_GetMeaData(kal_uint8 sel, kal_uint16 meacount);
+extern void ADC_IMM_Data_on_Booting(kal_uint32 channel, kal_uint32 counts, kal_uint16 * data);
+// MoDIS parser skip end
+
+#if !defined(DRV_ADC_OFF)
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_ADC_REG_DBG__)
+#define DRV_ADC_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+#define DRV_ADC_Reg(addr) DRV_DBG_Reg(addr)
+#define DRV_ADC_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define DRV_ADC_Reg32(addr) DRV_DBG_Reg32(addr)
+#define DRV_ADC_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+#define DRV_ADC_Reg8(addr) DRV_DBG_Reg8(addr)
+#define DRV_ADC_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+#define DRV_ADC_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+#define DRV_ADC_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#define DRV_ADC_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+#define DRV_ADC_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+#define DRV_ADC_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+#define DRV_ADC_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+#define DRV_ADC_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+#define DRV_ADC_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+#else
+#define DRV_ADC_WriteReg(addr,data) DRV_WriteReg(addr,data)
+#define DRV_ADC_Reg(addr) DRV_Reg(addr)
+#define DRV_ADC_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define DRV_ADC_Reg32(addr) DRV_Reg32(addr)
+#define DRV_ADC_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+#define DRV_ADC_Reg8(addr) DRV_Reg8(addr)
+#define DRV_ADC_ClearBits(addr,data) DRV_ClearBits(addr,data)
+#define DRV_ADC_SetBits(addr,data) DRV_SetBits(addr,data)
+#define DRV_ADC_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define DRV_ADC_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+#define DRV_ADC_SetBits32(addr,data) DRV_SetBits32(addr,data)
+#define DRV_ADC_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+#define DRV_ADC_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+#define DRV_ADC_SetBits8(addr,data) DRV_SetBits8(addr,data)
+#define DRV_ADC_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_ADC_REG_DBG__)
+
+#else //!defined(DRV_ADC_OFF)
+
+#define DRV_ADC_WriteReg(addr,data)
+#define DRV_ADC_Reg(addr) drv_dummy_return()
+#define DRV_ADC_WriteReg32(addr,data)
+#define DRV_ADC_Reg32(addr) drv_dummy_return()
+#define DRV_ADC_WriteReg8(addr,data)
+#define DRV_ADC_Reg8(addr) drv_dummy_return()
+#define DRV_ADC_ClearBits(addr,data)
+#define DRV_ADC_SetBits(addr,data)
+#define DRV_ADC_SetData(addr, bitmask, value)
+#define DRV_ADC_ClearBits32(addr,data)
+#define DRV_ADC_SetBits32(addr,data)
+#define DRV_ADC_SetData32(addr, bitmask, value)
+#define DRV_ADC_ClearBits8(addr,data)
+#define DRV_ADC_SetBits8(addr,data)
+#define DRV_ADC_SetData8(addr, bitmask, value)
+
+#endif //!defined(DRV_ADC_OFF)
+
+#endif /*_ADC_SW_H*/
+
diff --git a/mcu/driver/peripheral/inc/adcsche.h b/mcu/driver/peripheral/inc/adcsche.h
new file mode 100644
index 0000000..ec69387
--- /dev/null
+++ b/mcu/driver/peripheral/inc/adcsche.h
@@ -0,0 +1,187 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * adcsche.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for ADC scheduler
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _ADCSCHE_H
+#define _ADCSCHE_H
+
+#include "adc_hw.h"
+#include "dcl.h"
+
+#define ADC_SCHE_MAX_CHANNEL (ADC_MAX_CHANNEL*2+4) /*engineering mode, chargeing mode, and MMI mode*/
+
+//typedef void (* ADC_FUNC)(kal_int32 handle, kal_int32 volt_result, double adc_result);
+
+
+/*adcsche.h*/
+typedef struct{
+ module_type ownerid;
+ sap_type sapid;
+ kal_uint32 period;
+ kal_uint8 adc_phy_id;
+ kal_uint8 adc_logic_id;
+ kal_uint8 evaluate_count; /*how many to average*/
+ kal_int32 send_primitive;
+ kal_bool conti_measure;
+ eventid adc_sche_event_id;
+ void (*complete)(signed long adc_handle, signed long volt_result, double adc_result);/*callback for upper layer*/
+}ADCScheMeasParameter;
+
+typedef struct{
+ kal_uint8 *multi_adc_phy_id;
+ kal_uint8 max_multi_channel_number;
+ void (*multi_complete)(signed long adc_handle, signed long *volt_result, double *adc_result);/*callback for upper layer*/
+}ADCMultiChanParameter;
+
+
+// The core functions for ADC
+// adcsche.c
+extern kal_uint32 adc_sche_create_object(ADC_CTRL_CREATE_OBJECT_T *prCreateObj);
+extern void adc_sche_modify_parameters(kal_uint32 adc_sche_id, kal_uint32 period, kal_uint8 evaluate_count);
+extern void adc_sche_add_item(kal_uint32 adc_sche_id, void (*mea_complete)(signed long handle, signed long volt_result, double adc_result), kal_timer_func_ptr mea_Callback);
+extern void adc_sche_remove_item(kal_uint32 adc_sche_id);
+extern void adc_sche_init(void);
+extern void adc_sche_measure(void* msg_ptr);
+extern void adc_sche_get_parameter(kal_uint32 adc_sche_id, ADCScheMeasParameter **para);
+extern void adc_pwrdown_disable(void);
+extern void adc_pwrdown_enable(void);
+extern kal_uint8 adc_sche_get_channel(adc_channel_type type);
+extern void adcsche_adc_measure_en(kal_bool adc_measure_enable);
+extern void adc_multi_channel_set(DCL_UINT32 adc_sche_id, DCL_MULTI_CHANNEL_PARA_T* pMultiChannelPara);
+
+// adcmeasure.c
+#if defined(DRV_ADC_FULL_FUNC)
+extern void adc_tdma_time_setup(kal_uint16 idle_time, kal_uint16 trx_time);
+#endif // #if defined(DRV_ADC_FULL_FUNC)
+extern void adc_measure_parameter_init(void);
+extern void adc_sche_stop_timer(kal_uint8 adc_sche_id);
+extern void adc_sche_set_timer(kal_uint8 adc_sche_id, kal_uint32 tick, kal_timer_func_ptr call_func);
+extern void adc_read_efuse_data(double *slope, double *offset);
+extern void adc_read_calibration_data_inform(void);
+extern void adc_set_adc_calibration_data(ilm_struct *lim_ptr);
+extern kal_int32 adc_adc2vol(kal_uint8 chann,double adcVoltage);
+extern kal_int32 volt2temp(kal_int32 _volt);
+extern kal_int32 volt2isense(kal_int32 _volt);
+
+#endif /*_ADCSCHE_H*/
+
diff --git a/mcu/driver/peripheral/inc/alerter_hw.h b/mcu/driver/peripheral/inc/alerter_hw.h
new file mode 100644
index 0000000..cc29fb2
--- /dev/null
+++ b/mcu/driver/peripheral/inc/alerter_hw.h
@@ -0,0 +1,127 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * alerter_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for alerter driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef ALERTER_HW_H
+#define ALERTER_HW_H
+
+#include "reg_base.h"
+
+#if !defined(DRV_ALERTER_NOT_EXIST)
+/***************************
+ * Audio Alerter Registers *
+ ***************************/
+#define ALERTER_CNT1 (ALERTER_base+0x0000) /*Alerter val counter 1*/
+#define ALERTER_THRES (ALERTER_base+0x0004) /*Alerter threshold val*/
+#define ALERTER_CNT2 (ALERTER_base+0x0008) /*Alerter val counter 2*/
+#define ALERTER_CTRL (ALERTER_base+0x000C) /*Alerter control */
+
+#define ALERTER_CTRL_MODEMASK 0x0018
+#define ALERTER_CTRL_MODE1 0x0000
+#define ALERTER_CTRL_MODE2 0x0008
+#define ALERTER_CTRL_MODE3 0x0010
+#define ALERTER_PWR (0x80000000+0x0304)
+#define ALERTER_PWR_OFF 0x0040
+#define ALERTER_CTRL_PDMOUTPUT 0x0100
+
+#define ALERTER_CTRL_EN 0x8000
+#define ALERTER_CTRL_CLK_1 0x0000
+#define ALERTER_CTRL_CLK_2 0x0001
+#define ALERTER_CTRL_CLK_4 0x0002
+#define ALERTER_CTRL_CLK_8 0x0003
+
+/*==================Macro====================*/
+#define ALERTER_setCNT1(cnt1) *(volatile kal_uint16 *)ALERTER_CNT1 = cnt1
+#define ALERTER_setCNT2(cnt2) *(volatile kal_uint16 *)ALERTER_CNT2 = cnt2
+#define ALERTER_setTHRES(thres) *(volatile kal_uint16 *)ALERTER_THRES = thres
+
+#endif /*!defined(DRV_ALERTER_NOT_EXIST)*/
+
+#endif
+
diff --git a/mcu/driver/peripheral/inc/b2psi_hw.h b/mcu/driver/peripheral/inc/b2psi_hw.h
new file mode 100644
index 0000000..f9f3b86
--- /dev/null
+++ b/mcu/driver/peripheral/inc/b2psi_hw.h
@@ -0,0 +1,81 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * b2psi.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for b2psi driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _B2PSI_HW_H
+#define _B2PSI_HW_H
+
+/*register*/
+#define B2PSI_DATA (B2PSI_base+0x0000)
+#define B2PSI_DIV (B2PSI_base+0x0008)
+#define B2PSI_STAT (B2PSI_base+0x0010)
+#define B2PSI_TIME (B2PSI_base+0x0014)
+
+/*data key*/
+#define B2PSI_DATA_KEY 0x8216
+/*read/Write mask*/
+#define B2PSI_WRITE_MASK 0x800
+#define B2PSI_READ_MASK 0x0
+/*read/write status*/
+#define B2PSI_READ_RDY 0x1
+#define B2PSI_WRITE_RDY 0x2
+
+#endif
+
diff --git a/mcu/driver/peripheral/inc/bmt_sw.h b/mcu/driver/peripheral/inc/bmt_sw.h
new file mode 100644
index 0000000..3728709
--- /dev/null
+++ b/mcu/driver/peripheral/inc/bmt_sw.h
@@ -0,0 +1,429 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2010
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * bmt_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for BMT driver and adaption.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _BMT_SW_H
+#define _BMT_SW_H
+
+#include "drv_features.h"
+#include "chr_parameter.h"
+#include "dcl.h"
+
+// ============================================================ //
+// Definitions for BMT Module Only
+// ============================================================ //
+#if defined(__EVB__)
+#if !defined(DRV_MISC_ADC_FIXED_VBAT_WA)
+#define DRV_MISC_ADC_FIXED_VBAT_WA
+#endif
+#endif
+
+#if(CHR_BATTERY_TYPE == LI_ION_BATTERY)
+#define CHR_WITH_LI_ION_BATTERY
+#else
+#define CHR_WITH_NI_MH_BATTERY
+#endif
+
+/* Battery State */
+#define CHR_PRE 0
+#define CHR_FAST 1
+#define CHR_TOPOFF 2
+#define CHR_BATFULL 3
+#define CHR_ERROR 4
+#define CHR_HOLD 5
+#define CHR_POSTFULL 6
+#define CHR_PRE_FULL_CHECK 7
+
+/* TON, TOFF */
+#define CHRTON 0
+#define CHRTOFF 1
+
+/* Safety Timer Configuration */
+#define BMT_SAFETY_TIMER_ON 1
+#define BMT_SAFETY_TIMER_OFF 0
+
+/* Counts of ADC Measurement */
+#define BMT_EVALUATE_VALUE 10
+
+/* __TC01__ Configuration */
+#if defined(__TC01__)
+#define __DRV_BMT_ALWAYS_PULSE_CHARGING__ // TC01 request pulse charging in CV
+#define __DRV_BMT_ESTIMATIVE_TIMER_ON_TOPOFF__
+#define __DRV_BMT_DISABLE_STOP_TIMER__
+#define __DRV_BMT_CHARGING_COMPLETE_MSG__
+#define __DRV_BMT_REPORT_VBAT_IN_BOOTING__
+
+#if ((!defined(L4_NOT_PRESENT)) && (!defined(__MAUI_BASIC__)) )
+#define __DRV_BATTERY_EXIST_DETECTION__
+// #define BATTERY_EXIST_DETECTION_SW_POLLING_PERIOD_IN_TICK (3250) // 15 sec = (1000/4.615) * 15
+#endif // #if ( (!defined(L4_NOT_PRESENT)) && (!defined(__MAUI_BASIC__)) )
+
+#define __BMT_CHARGE_GUARD_TIME__
+ #define BMT_TOTAL_CHARGE_TIME (6 * 60) // 6 hours = 360 mins
+ #ifdef __BMT_CHARGE_GUARD_TIME__
+ #define BMT_CHARGE_GUARD_TIME_PERIOD (2 * 60 + 50) // 2 hours and 50 mins = 170 mins
+ #if (BMT_CHARGE_GUARD_TIME_PERIOD > BMT_TOTAL_CHARGE_TIME)
+ #error "[BMT]Error!! BMT_TOTAL_CHARGE_TIME should >= BMT_CHARGE_GUARD_TIME_PERIOD!!"
+ #endif
+ #endif // __BMT_CHARGE_GUARD_TIME__
+
+#if defined(__GENERAL_EXTERNAL_CHARGER__)
+
+// Debug mode, take Fac.UART cable as charger
+//#define DEBUG_TREAT_FAC_UART_CABLE_AS_CHARGER
+
+#endif // #if defined(__GENERAL_EXTERNAL_CHARGER__)
+
+
+#else // Else of #if defined(__TC01__)
+
+#define __BMT_PAUSE_CHARGE_STOP_SAFETY_TIMER__
+
+#if defined(__DRV_BMT_BATTERY_LARGER_1600MA__)
+ #define BMT_TOTAL_CHARGE_TIME (12 * 60) // 12 hours = 720 mins
+#elif defined(__DRV_BMT_ULTRA_LOW_COST_CHARGER__)
+ #define BMT_TOTAL_CHARGE_TIME (8 * 60) // 8 hours = 480 mins
+#else
+ #define BMT_TOTAL_CHARGE_TIME (6 * 60) // 6 hours = 360 mins
+#endif //#if defined(__DRV_BMT_ULTRA_LOW_COST_CHARGER__)
+
+#endif // End of #if defined(__TC01__)
+
+// ============================================================ //
+// Useless Definitions
+// ============================================================ //
+/* Power key position */
+#if 0
+#ifndef CANNON
+/* under construction !*/
+#else
+/* under construction !*/
+#endif
+#endif
+
+// ============================================================ //
+// Data structures for BMT Module Only
+// ============================================================ //
+typedef void (* CHR_FUNC)(void);
+
+typedef struct {
+ kal_uint8 TON;/*sec*/
+ kal_uint8 TOFF;/*sec*/
+} CHRTStruct;
+
+/* Customize Charging Parameters */
+typedef struct {
+ kal_int32 TYPICAL_LI_BATTYPE;
+ kal_int32 TYPICAL_NI_BATTYPE;
+ kal_uint32 BATT_EXIST_ADC_THRESHOLD;
+ kal_int32 VCHARGER_HIGH;
+ kal_int32 VCHARGER_LOW;
+ kal_int32 BATTMP_MINUS_40C;
+ kal_int32 BATTMP_0C;
+ kal_int32 BATTMP_45C;
+ kal_int32 ICHARGE_ON_HIGH;
+ kal_int32 ICHARGE_ON_LOW;
+ kal_int32 ICHARGE_OFF_HIGH;
+
+ kal_int32 V_PRE2FAST_THRES;
+ kal_int32 FAST_ICHARGE_HIGHLEVEL; /* 600ma,for table search */
+ kal_int32 FAST_ICHARGE_LOWLEVEL; /* 400ma,for table search */
+ kal_int32 I_TOPOFF2FAST_THRES; /* 250ma,TOPOFF->FAST */
+ kal_int32 I_TOPOFF2FULL_THRES; /* 120ma,TOPOFF->BATFULL */
+
+#if defined(CHR_WITH_LI_ION_BATTERY)
+ kal_int32 V_FAST2TOPOFF_THRES;
+ kal_int32 V_FULL2FAST_THRES; /* BATFULL->FAST */
+ kal_int32 MAX_VBAT_LI;
+ kal_int32 V_PROTECT_HIGH_LI;
+ kal_int32 V_PROTECT_LOW_LI;
+#endif
+
+#if defined(CHR_WITH_NI_MH_BATTERY)
+ kal_int32 V_TEMP_FAST2FULL_THRES_NI; /* 50oC,FAST->BATFULL */
+ kal_int32 V_FULL2FAST_THRES_NI;
+ kal_int32 MAX_VBAT_NI;
+#endif
+
+ /*Time delay*/
+ /* PRE CHARGE ,search table*/
+ /*TON = 3s,TOFF=2s*/
+ kal_uint32 PRE_TON;
+ kal_uint32 PRE_TOFF;
+
+/* FAST CHARGE ,search table*/
+/*TON = 3s,TOFF=0s*/
+ kal_uint32 TOPOFF_TON;
+ kal_uint32 TOPOFF_TOFF;
+#if defined(DRV_BMT_PULSE_CHARGING)
+ kal_uint32 BATPOSTFULL_TWAIT_LI;
+ kal_uint32 BATPOSTFULL_TON_LI;
+ kal_uint32 BATPOSTFULL_TOFF_LI;
+#endif //#if defined(DRV_BMT_PULSE_CHARGING)
+
+#if defined(CHR_WITH_LI_ION_BATTERY)
+ kal_uint32 BATFULL_TON_LI; /*unit : second*/
+ kal_uint32 BATFULL_TOFF_LI;
+#else
+ kal_uint32 BATFULL_TON_NI; /*unit : second*/
+ kal_uint32 BATFULL_TOFF_NI;
+#endif
+ kal_uint32 BATFULL_TOFF;
+ kal_uint32 BATHOLD_OFF;
+ kal_uint32 bmt_measure_discard_time; /*24 ticks*/
+
+ kal_int32 CurrOffset[3];
+/*GPIO control*/
+#ifndef __CUST_NEW__
+ kal_uint8 GPIO_CHRCTRL;
+ kal_uint8 GPIO_BATDET;
+ kal_uint8 GPIO_VIBRATOR;
+#endif /* __CUST_NEW__ */
+ kal_uint8 TONOFFTABLE[6][2];
+ kal_bool bmt_check_battery;
+ kal_bool bmt_check_charger;
+ kal_bool bmt_check_temp;
+ kal_bool bmt_battery_type;
+} bmt_customized_struct;
+
+// ============================================================ //
+// Useless Data structures
+// ============================================================ //
+typedef struct{
+ void (*measure_func)(kal_uint8);
+ void (*read_back)(kal_uint8);
+}BMT_MeasFuncs;
+
+// ============================================================ //
+// Enumeration for BMT Module Only
+// ============================================================ //
+typedef enum{
+ USB_IN_STATE,
+ USB100_STATE,
+ USB500_STATE,
+ USB_OUT_STATE,
+ AC_IN_STATE,
+ AC_OUT_STATE,
+ USB_INIT_STATE
+}bmt_usb_state_enum;
+
+typedef enum{
+ BMT_AC_IN,
+ BMT_USB_IN
+}bmt_usb_charger_enum;
+
+// ============================================================ //
+// Useless Enumeration
+// ============================================================ //
+// Charging status enum
+typedef enum
+{
+ BMT_CHR_STATUS_NONE = 0x00000000,
+ BMT_CHR_STATUS_CHARGE_CURRENT_TOO_HIGH = 0x00000001, // BIT00
+ BMT_CHR_STATUS_CHARGE_CURRENT_TOO_LOW = 0x00000002, // BIT01
+ BMT_CHR_STATUS_DISCHARGE_CURRENT_TOO_HIGH = 0x00000004, // BIT02
+ BMT_CHR_STATUS_CHARGE_VBATTEMP_TOO_HIGH = 0x00000008, // BIT03
+ BMT_CHR_STATUS_CHARGE_VBATTEMP_TOO_LOW = 0x00000010, // BIT04
+ BMT_CHR_STATUS_CHARGE_VBAT_TOO_HIGH = 0x00000020, // BIT05
+ BMT_CHR_STATUS_CHARGE_VCHARGER_TOO_HIGH = 0x00000040, // BIT06
+ BMT_CHR_STATUS_CHARGE_VCHARGER_TOO_LOW = 0x00000080, // BIT07
+ BMT_CHR_STATUS_CHARGE_FULL = 0x00000100, // BIT08
+ BMT_CHR_STATUS_BATT_BAD_CONTACT = 0x00000200, // BIT09
+ BMT_CHR_STATUS_TALK_HOLD = 0x00000400, // BIT10
+
+ BMT_CHR_STATUS_MAX = 0x10000000 // BIT31
+}bmt_chr_status_enum;
+
+
+// ============================================================
+// Exported APIs (Only for BMT Module)
+
+/* For ADC schedule & measure*/
+extern kal_int32 adc_measureVoltage(kal_uint8 chann, double *adc_value);
+
+#ifdef __BMT_CHARGE_GUARD_TIME__
+extern void bmt_set_guardtimer(kal_uint32 tick);
+extern void bmt_stop_guardtimer(void);
+#endif // #ifdef __BMT_CHARGE_GUARD_TIME__
+#if defined(__DRV_BMT_ESTIMATIVE_TIMER_ON_TOPOFF__)
+extern void bmt_set_estimativetimer(kal_uint32 tick);
+extern void bmt_stop_estimativetimer(void);
+#endif // #if defined(__DRV_BMT_ESTIMATIVE_TIMER_ON_TOPOFF__)
+
+extern void bmt_stop_stoptimer(void);
+extern void BMT_Charge(kal_bool data); /* in drv directory */
+extern void bmt_initialize(void);
+extern void bmt_set_chr_current(void);
+extern void bmt_Modify_PowerOn_Type(kal_uint8 power_type);
+extern void bmt_find_and_set_the_nearest_current(PMU_CHR_CURRENT_ENUM SetCurrent);
+extern void bmt_find_and_set_the_nearest_charger_high_voltage(DCL_UINT32 voltage);
+extern kal_uint8 bmt_Get_PowerOn_Type(void);
+extern kal_bool bmt_frequently_check_on_state(void);
+#if defined(DRV_BMT_HW_PRECC_WORKAROUND)
+extern kal_bool bmt_frequently_check_off_state(void);
+#endif
+extern kal_bool BMT_VBatVoltageIsFull(kal_uint32 voltage);
+extern kal_bool BMT_Current_Voltage(DCL_ADC_CHANNEL_TYPE_ENUM ch, kal_uint32 *voltage, double *adc_value);
+extern kal_bool bmt_check_if_bat_on(void);
+extern bmt_usb_charger_enum bmt_IsUSBorCharger(void);
+
+#if defined(__DRV_BATTERY_EXIST_DETECTION__)
+extern kal_uint32 bmt_get_batt_exist_det_period(void);
+#endif // #if defined(__DRV_BATTERY_EXIST_DETECTION__)
+extern DCL_STATUS bmt_get_customized_para(BMT_CTRL_GET_CUSTOMIZED_PARA_T *GetCustomizedPara);
+
+// ============================================================
+// External Variables
+extern bmt_customized_struct *bmt_charging_para;
+extern bmt_customized_struct bmt_custom_chr_def;
+#if defined(DRV_BMT_HW_PRECC_WORKAROUND)
+extern kal_bool SW_Workaround_Flag;
+extern kal_bool Manual_Disable_Charge_Flag;
+extern kal_uint8 HW_Plug_Status;
+#endif
+
+// ============================================================
+// MoDIS parser skip start
+// Exported functions, used by driver level functions
+
+// MoDIS parser skip end
+
+// ============================================================
+// MoDIS parser skip start
+// Unknown functions, maybe previous owner forgot to delete
+
+// MoDIS parser skip end
+
+#if !defined(DRV_BMT_OFF)
+
+#else // !defined(DRV_BMT_OFF)
+
+#endif // !defined(DRV_BMT_OFF)
+
+#endif // End of #ifndef _BMT_SW_H
+
diff --git a/mcu/driver/peripheral/inc/bmt_trc.h b/mcu/driver/peripheral/inc/bmt_trc.h
new file mode 100644
index 0000000..feacb73
--- /dev/null
+++ b/mcu/driver/peripheral/inc/bmt_trc.h
@@ -0,0 +1,208 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * bmt_trc.h
+ *
+ * Project:
+ * --------
+ * MAUI
+ *
+ * Description:
+ * ------------
+ * This is trace map definition for BMT.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
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+ * removed!
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+ * removed!
+ *
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+ * removed!
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+ * removed!
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+ * removed!
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+ * removed!
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+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _BMT_TRC_H
+#define _BMT_TRC_H
+#ifndef GEN_FOR_PC
+ #ifndef _STACK_CONFIG_H
+ #error "stack_config.h should be included before tst_config.h"
+ #endif
+#else
+ #include "kal_trace.h"
+#endif /* GEN_FOR_PC */
+// For RHR ADD Usage
+#include "stack_config.h"
+#include "kal_trace.h"
+#ifndef _KAL_TRACE_H
+ #error "kal_trace.h should be included before tst_trace.h"
+#endif
+#if !defined(GEN_FOR_PC)
+#if defined(__TST_MODULE__) || defined(__CUSTOM_RELEASE__)
+#endif /* TST Trace Defintion */
+#endif
+#if !defined(GEN_FOR_PC)
+#include"bmt_trc_mod_bmt_utmd.h"
+#endif
+#endif /* _BMT_TRC_H */
diff --git a/mcu/driver/peripheral/inc/bmt_trc_mod_bmt_utmd.json b/mcu/driver/peripheral/inc/bmt_trc_mod_bmt_utmd.json
new file mode 100644
index 0000000..378c2b2
--- /dev/null
+++ b/mcu/driver/peripheral/inc/bmt_trc_mod_bmt_utmd.json
@@ -0,0 +1,1666 @@
+{
+ "endGen": "Legacy",
+ "startGen": "Legacy",
+ "legacyParameters": {},
+ "module": "MOD_BMT",
+ "traceClassDefs": [
+ {
+ "TRACE_INFO": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_INFO"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_WARNING": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_WARNING"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_ERROR": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_ERROR"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_FUNC": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_FUNC"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_STATE": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_STATE"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_1": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_GROUP1"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_2": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_GROUP2"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_3": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_GROUP3"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_4": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_GROUP4"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_5": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_GROUP5"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_6": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_GROUP6"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_7": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_GROUP7"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_8": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_GROUP8"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_9": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_GROUP9"
+ ],
+ "traceType": "Public"
+ }
+ },
+ {
+ "TRACE_GROUP_10": {
+ "debugLevel": "Ultra-Low",
+ "tag": [
+ "Baseline",
+ "TRACE_GROUP10"
+ ],
+ "traceType": "Public"
+ }
+ }
+ ],
+ "traceDefs": [
+ {
+ "BMT_CTRL_CHARGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "BMT: BMT_CtrlCharge = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHARGING_ALREADY_ON_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "BMT: Charging is already on",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CALL_STATE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "BMT_CallState: callState = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_INVALID_CHARGER_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Invalid Charger.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_ICHARGE_OVER_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "ICHARGE too high.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_ICHARGE_LOW_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "ICHARGE too low.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_VBAT_OVER_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "VBAT too high.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_VTEMP_OVER_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "BATTMP too high.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_VTEMP_LOW_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "BATTMP too low.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHR_HOLD_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "CHR_HOLD.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_VBAT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "VBAT = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_VBATTMP_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "VBATTMP = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_BATTMP_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "BATTMP = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_ICHARGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "ICHARGE = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_VSENSE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "VSENSE = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_VSENSE_VBAT_OFFSET_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "VSENSE - VBAT(OFFSET) = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_VCHARGER_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "VCHARGER = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHRPRE_ON_STATE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "STATE = BMT_CHRPRE_ON.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHRPRE_OFF_STATE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "STATE = BMT_CHRPRE_OFF.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_FAST_CHARGE_CHANGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Chage state to FAST_CHARGE.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_FAST_ON_STATE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "STATE = BMT_CHRFAST_ON.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_FAST_OFF_STATE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "STATE = BMT_CHRFAST_OFF.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_PMU_PULSECHR_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "STATE = BMT_PMU_PULSECHR.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHR_POSTFULL_CHANGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Chage state to CHR_POSTFULL.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHR_BATFULL_CHANGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Chage state to CHR_BATFULL.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHR_UNDER_EXTREMETMP_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Now it's under extreme temperature.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHR_EXTREMETMP_BATFULL_CHANGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Chage state to CHR_BATFULL because of extreme temperature.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHR_EXTREMETMP_CHARGE_RECHARGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Restart charging because of the voltage drop under extreme temperature.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHR_TOPOFF_CHANGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Chage state to CHR_TOPOFF.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHRTOPOFF_ON_STATE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "STATE = BMT_CHRTOPOFF_ON.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHR_FAST_CHANGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Chage state to CHR_FAST.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHRTOPOFF_OFF_STATE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "STATE = BMT_CHRTOPOFF_OFF.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHRBATPOSTFULL_ON_STATE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "STATE = CHR_POSTFULL_ON.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHRBATPOSTFULL_OFF_STATE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "STATE = CHR_POSTFULL_OFF.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHRBATFULL_ON_STATE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "STATE = BMT_CHRBATFULL_ON.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHRBATFULL_OFF_STATE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "STATE = BMT_CHRBATFULL_OFF.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHRHOLD_STATE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "STATE = BMT_CHRHOLD.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_BAT_FULL_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "High Battery Full.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MEASURE_STOP_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "BMT_MeasureStop.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_PWRON_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "BMT.PWRon = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_TASK_MAIN_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "=====================BMT_task_main=====================.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHARGE_GUARD_TIMER_EXPIRE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Charging guard timer(%d minutes) expired.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_SAFETY_TIMER_EXPIRE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Safety timer(%d minutes) expired.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_SAFETY_TIMER_START_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Safety timer(%d minutes) starts.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_SAFETY_AND_GUARD_TIMER_START_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Safety timer(%d minutes) and charging guard timer (%d minutes) starts.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_SAFETY_TIMER_STOP_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Safety timer(%d minutes) stops.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_STOP_TIMER_EXPIRE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Stop timer(30 min) expired.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_STOP_TIMER_START_TRC": {
+ "apiType": "index",
+ "format": "Stop timer(30 min) starts.",
+ "traceClass": "TRACE_FUNC"
+ }
+ },
+ {
+ "BMT_STOP_TIMER_STOP_TRC": {
+ "apiType": "index",
+ "format": "Stop timer(30 min) stops.",
+ "traceClass": "TRACE_FUNC"
+ }
+ },
+ {
+ "BMT_ERROR_CHECK_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "BMT_CHRERRORCHECK.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_ULC_SW_PLUGOUT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Ultra Low Cost S/W Plug Out Detected.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_OBTAIN_PHY_STAT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "BMT_ObtainBMTPHYSTAT.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHARGE_ENABLE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "BMT_Charge = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_PMU_DO_NOT_SUPPORT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "PMU does not support this cmds = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_ERRORCHECK_AT_CHARGE_ON_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Error Check at Charge On.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_ERRORCHECK_AT_CHARGE_OFF_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Error Check at Charge Off.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_ERRORCHECK_ON_COUNT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Current Error Check On Count = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_ERRORCHECK_OFF_COUNT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Current Error Check Off Count = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_SW_WORKAROUND_FLAG_TRUE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "SW_Workaround_Flag = TRUE.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_SW_WORKAROUND_FLAG_FALSE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "SW_Workaround_Flag = FALSE.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_INSIDE_SW_WORKAROUND_RANGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Inside SW Workaround Range.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_OUTSIDE_SW_WORKAROUND_RANGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Outside SW Workaround Range.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MISSING_HW_PLUG_OUT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Missing HW Plug Out.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_SW_PLUG_OUT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "SW Plug Out.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_PLUG_OUT_FALSE_ALARM_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Disable charge but hasn't detect plug out -> Plug out false alarm.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_ENABLE_CHARGE_AT_CHARGE_ON_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Enable Charge @ ON State.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_DISABLE_CHARGE_AT_CHARGE_ON_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Disable Charge @ ON State.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_POSSIBLE_PLUG_OUT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Possible plug out, need disable charge if we are at charge on state.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_LOW_CHARGE_CURRENT_AT_CHARGE_OFF_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Low charge current is due to charge off state.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_SW_POLLING_CHARGER_OV_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Charger OV by SW polling.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_SET_CUSTOMIZED_CURRENT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "bmt_set_customized_current.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_SET_AC_CHARGE_CURRENT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Set AC Charge Current.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_SET_USB_CHARGE_CURRENT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Set USB Charge Current.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_FIND_AND_SET_THE_NEAREST_CURRENT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "The nearest charge current = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHARGE_CURRENT_AND_LEVEL_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Charge current = %d, Charge Level = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_TOTAL_CHARGE_CURRENT_LEVEL_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Total charge current level = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MIN_CHARGE_CURRENT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Min charge current = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MAX_CHARGE_CURRENT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Max charge current = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CURRENT_CHARGE_CURRENT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Current charge current = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_PHY_CHECK_OVER_CHARGER_COUNT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "over_charger_count = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_PHY_CHECK_OVER_CURRENT_COUNT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "over_current_count = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_PHY_CHECK_LOW_CURRENT_COUNT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "low_current_count = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_PHY_CHECK_LOW_TRMPER_COUNT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "low_temper_count = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_PHY_CHECK_OVER_TEMPER_COUNT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "over_temper_count = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_ADC_MEASURE_WARNING_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "ADC measure warning: Phy id: %d, pre measured volt: %d, curr measured volt: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_ILLEGAL_PHY_ADC_CHANNEL_TRC": {
+ "apiType": "index",
+ "format": "Warning, ADC phy id is illegal, return value 0 only",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_ADC_CALIBRATION_FAIL_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "ADC Calinration FAIL, when charge off, ICharger = %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_ADC_NO_CALIBRATION_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Warning, ADC using Default slope = %d and offset = %d ",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_ADC_CALLBACK_INFO_TRC": {
+ "apiType": "index",
+ "format": "ADC phyid=%d, period=%d, evlcount=%d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_ADC_GET_ADC_INFO_TRC": {
+ "apiType": "index",
+ "format": "status=%d, channel=%d",
+ "traceClass": "TRACE_ERROR"
+ }
+ },
+ {
+ "BMT_CABLE_IN_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Cable in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_AC_IN_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "AC in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_NON_AC_IN_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Non Standard AC in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CABLE_OUT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Cable out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_INV_AC_IN_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "INV AC in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_AC_OUT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "AC out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_IN_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_CHARGING_HOST_IN_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB Charging host in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_IN_WAIT_500_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB in and wait for 500",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_OUT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_100_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB 100",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_500_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB 500",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHR_STATUS_CHARGE_IN_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Charge Status = bmt_chr_in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHR_STATUS_CHARGE_OUT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Charge Status = bmt_chr_out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_STATE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Usb State = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HW_PLUG_OUT_INSIDE_SW_WORKAROUND_RANGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "H/W plug out detected inside S/W workaround range -> return use S/W to check.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHARGING_START_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Charging start",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHARGING_END_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Charging end",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHARGING_CURRENT_NOT_SUPPORTED_STOP_CHARGING_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Charging current NOT supported, stop charging",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CHARGING_WDT_CLR_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Charging WDT clear",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_AC_IN_AND_START_CHARGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "AC in and start charging",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_INV_AC_IN_AND_START_CHARGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Invalid AC in and start charging",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_IN_AND_START_CHARGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB in and start charging",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_500_AND_START_CHARGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB 500 waited and start charging",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_AC_OUT_AND_STOP_CHARGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "AC out and stop charging",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_OUT_AND_STOP_CHARGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB out and stop charging",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_500_OUT_AND_STOP_CHARGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB 500 out and stop charging",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_100_OUT_AND_STOP_CHARGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB 100 out and stop charging",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_100_OUT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB 100 out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_AC_OUT_USB_STILL_IN_KEEP_CHARGING_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "AC out, USB still in, keep charging",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_AC_OUT_USB_500_STILL_IN_KEEP_CHARGING_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "AC out, USB 500 still in, keep charging",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_OUT_AC_STILL_IN_KEEP_CHARGING_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB out, AC still in, keep charging",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_IN_AC_ALREAY_IN_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB in, AC already in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_USB_500_AC_ALREAY_IN_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB 500 waited, AC already in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_TIMER_EXPIRE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "MSG_ID_TIMER_EXPIRY",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_CHARGER_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "MSG_ID_BMT_CHARGER_IND",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_USB_B_OUT": {
+ "_comment": "Trace reference not found",
+ "format": "MSG_ID_USB_B_PLUGOUT_IND",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_USB_B_IN": {
+ "_comment": "Trace reference not found",
+ "format": "MSG_ID_USB_B_PLUGIN_IND",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_USB": {
+ "_comment": "Trace reference not found",
+ "format": "MSG_ID_BMT_USB_IND",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_ADC_ADD": {
+ "_comment": "Trace reference not found",
+ "format": "MSG_ID_BMT_ADC_ADD_ITEM_REQ",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_ADC_REMOVE": {
+ "_comment": "Trace reference not found",
+ "format": "MSG_ID_BMT_ADC_REMOVE_ITEM_REQ",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_ADC_PARAM": {
+ "_comment": "Trace reference not found",
+ "format": "MSG_ID_BMT_ADC_MODIFY_PARAMETERS_REQ",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_ADC_NVRAM_READ_CNF": {
+ "_comment": "Trace reference not found",
+ "format": "MSG_ID_NVRAM_READ_CNF",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_ADC_NVRAM_SLOPE_OFFSET": {
+ "_comment": "Trace reference not found",
+ "format": "MSG_ID_NVRAM_READ_CNF slope: %d offset: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_ADC_EFUSE": {
+ "_comment": "Trace reference not found",
+ "format": "MSG_ID_EFUSE_READ",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_ADC_EFUSE_SLOPE_OFFSET": {
+ "_comment": "Trace reference not found",
+ "format": "MSG_ID_EFUSE_READ slope: %d offset: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_ADC_EFUSE_AB": {
+ "_comment": "Trace reference not found",
+ "format": "MSG_ID_EFUSE_READ EFUSE_A: %d EFUSE_B: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_ADC_EFUSE_ADC_SLOPE_OFFSET": {
+ "_comment": "Trace reference not found",
+ "format": "MSG_ID_EFUSE_READ_ADC slope: %d offset: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_ADC_EFUSE_ADC_CALIBRATION_SLOPE_OFFSET": {
+ "_comment": "Trace reference not found",
+ "format": "MSG_ID_EFUSE_READ_ADC slope%d: %d offset%d: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_BATT_ON_DET": {
+ "_comment": "Trace reference not found",
+ "format": "BMT_MSG_BATT_ON_DET Batt detection timer timeout, batt state: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_BATT_OFF_BLOCK": {
+ "_comment": "Trace reference not found",
+ "format": "BMT_MSG_BATT_ON_DET Batt NOT on, block all BMT messages except TIMER EXPIRATION",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_INTR_ENABLE": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: intr enable(%d)",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_IN": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Cable in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_OUT": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Cable out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_DBG_1": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Debug: reg1: %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_DBG_2": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Debug: reg1: %x, reg2: %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_DBG_3": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Debug: reg1: %x, reg2: %x, reg3",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_DBG_4": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Debug: reg1: %x, reg2: %x, reg3: %x, reg4: %x",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_REPEATED_IN": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Repeated cable in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_REPEATED_OUT": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Repeated cable out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_USB_IN": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: USB cable in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_USB_OUT": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: USB cable out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_AC_IN": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: AC cable in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_AC_OUT": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: AC cable out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_LGTA_IN": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: LGTA cable in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_LGTA_OUT": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: LGTA cable out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_FAC_USB_IN": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Factory USB cable in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_FAC_USB_OUT": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Factory USB cable out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_FAC_UART_IN": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Factory UART cable in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_FAC_UART_OUT": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Factory UART cable out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_EARPHONE_IN": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Earphone cable in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_EARPHONE_OUT": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Earphone cable out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_KEY_PRESSED": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Earphone key pressed",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_KEY_RELEASED": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Earphone key released",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_VIDEO_IN": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Video cable in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_VIDEO_OUT": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Video cable out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_OTG_IN": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: OTG cable in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_OTG_OUT": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: OTG cable out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_UNKNOWN_IN": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Unknown cable in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_UNKNOWN_OUT": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Unknown cable out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_FAC_MODE": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: In FAC mode",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_FAC_MODE_AC_IN": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: FAC mode AC in",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_FAC_MODE_AC_OUT": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: FAC mode AC out",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_REPEATED_IN_HISR": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Repeated cable in HISR",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_FAC_MODE_DIS_SLEEP": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: FAC mode disable sleep mode",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_FAC_MODE_EN_SLEEP": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: FAC mode enable sleep mode",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_EXT_AUDIO_WA_TURN_OFF_EARPHONE_REQ": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Ext Audio IC WA: Turn off Earphone path request",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_EXT_AUDIO_WA_TURN_ON_EARPHONE_REQ": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Ext Audio IC WA: Turn on Earphone path request",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_EXT_AUDIO_WA_TURN_OFF_EARPHONE": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Ext Audio IC WA: Turn off earphone path",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_MSG_EXT_CABLE_EXT_AUDIO_WA_TURN_ON_EARPHONE": {
+ "_comment": "Trace reference not found",
+ "format": "Ext cable det: Ext Audio IC WA: Turn on earphone path",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_FIRST_TIME_VCHG_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "First Time VCharge_AVG = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_FIRST_TIME_CHARGER_ON_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "First Time Charge ON.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_CURRENT_VCHG_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Cur_VCHG = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_AVERAGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Average VCHG = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_TOO_HIGH_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "VCHARGER too high.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_LOWEST_THRESHOLD_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "bmt_high_vchg_para->HIGH_VCHG_TABLE[0][0] = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_UPPER_THRESHOLD_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Upper Threshold: HIGH_VCHG_TABLE[i][0] = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_LOWER_THRESHOLD_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Lower Threshold: HIGH_VCHG_TABLE[i-1][0] = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_TABLE_INDEX_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Table Index = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_SET_USB_CHARGE_CURRENT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Set USB Current = %d for CHARGER_PRESENT_NON",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_USB_IN_USE_CUSTOM_CHARGE_CURRENT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "USB In->Use Custom Setting in pmu_custom.c.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_CHARGE_CURRENT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Set High VCHG Charge Current = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_RUNTIME_APPLY_CHARGE_CURRENT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Runtime Apply High VCHG Charge Current = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_MAX_RESET_TO_ZERO_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Cur_VCharge_MAX Reset to 0.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_CUR_VCHG_MAX_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Cur_VCharge_MAX = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_VCHG_DIFF_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Current VCharger - Pre_VCharge_AVG = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_TOTAL_VCHG_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Accumate Total VCharger = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_CS_VTH_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Register: Charge Current = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_PRE_CURRENT_LEVEL_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Previous Current Level = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_CUR_CURRENT_LEVEL_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Current Current Level = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_HYSTERESIS_UPPER_BOUND_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Hysteresis Upper Bound = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_HIGH_VCHG_HYSTERESIS_LOWER_BOUND_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Hysteresis Lower Bound = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_CURRENT_PMIC_STATE_TRC": {
+ "apiType": "index",
+ "format": "BMT.pmictrl_state = %d.",
+ "traceClass": "TRACE_FUNC"
+ }
+ },
+ {
+ "BMT_EXT_INVALID_CHARGER_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Ext charger: Invalid Charger.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_EXT_ICHARGE_OVER_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Ext charger: ICHARGE too high.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_EXT_ICHARGE_LOW_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Ext charger: ICHARGE too low.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_EXT_VBAT_OVER_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Ext charger: VBAT too high.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_EXT_VTEMP_OVER_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Ext charger: BATTMP too high.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_EXT_VTEMP_LOW_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Ext charger: BATTMP too low.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_EXT_CHR_HOLD_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Ext charger: CHR_HOLD.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_EXT_VBAT_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Ext charger: VBAT = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_EXT_BATTMP_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Ext charger: BATTMP = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_EXT_ICHARGE_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Ext charger: ICHARGE = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_EXT_VCHARGER_TRC": {
+ "_comment": "Trace reference not found",
+ "format": "Ext charger: VCHARGER = %d.",
+ "traceClass": "TRACE_INFO"
+ }
+ },
+ {
+ "BMT_SOFT_START_CURRENT_LEVEL": {
+ "_comment": "Trace reference not found",
+ "format": "BMT soft start get current level: %d",
+ "traceClass": "TRACE_INFO"
+ }
+ }
+ ],
+ "traceFamily": "PS"
+}
\ No newline at end of file
diff --git a/mcu/driver/peripheral/inc/dcl_gpt_hw.h b/mcu/driver/peripheral/inc/dcl_gpt_hw.h
new file mode 100644
index 0000000..c346648
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_gpt_hw.h
@@ -0,0 +1,493 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_gpt.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for GPT.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*******************************************************************************
+ * DCL_CTRL_CMD
+ *******************************************************************************/
+#ifndef DCL_GPT_HW_H_
+#define DCL_GPT_HW_H_
+#include "kal_general_types.h"
+#include "drv_comm.h"
+#include "dcl.h"
+
+typedef DCL_UINT16 GPT_DEV;
+typedef enum
+{
+ GPT1 = 1,
+ GPT2 = 2,
+ GPT3 = 3,
+ GPT4 = 4
+} GPT_DEV_T;
+
+typedef enum
+{
+ clk_16k,
+ clk_8k,
+ clk_4k,
+ clk_2k,
+ clk_1k,
+ clk_500,
+ clk_250,
+ clk_125,
+ clk_invalid=0xFF
+}gpt_clock;
+
+typedef DCL_UINT32 HGPT_CMD;
+typedef enum
+{
+
+ HGPT_CMD_CLK,
+ HGPT_CMD_RESET,
+ HGPT_CMD_START,
+ HGPT_CMD_STOP,
+ HGPT_CMD_BUSYWAIT,
+// HGPT_CMD_GPT_STATUS,
+ FHGPT_CMD_START,
+ FHGPT_CMD_STOP,
+ FHGPT_CMD_RETURN_COUNT,
+ FHGPT_CMD_LOCK
+} HGPT_CMD_T;
+
+/* For HGPT_CMD_CLK command. */
+typedef enum
+{
+ CLK_16K,
+ CLK_8K,
+ CLK_4K,
+ CLK_2K,
+ CLK_1K,
+ CLK_500,
+ CLK_250,
+ CLK_125
+} HGPT_CLK_T;
+
+typedef struct
+{
+ DCL_UINT32 u4Clock; // for HGPT_CLK_T enum
+} HGPT_CTRL_CLK_T;
+
+/* For HGPT_CMD_RESET command. */
+typedef struct
+{
+ DCL_UINT16 u2CountValue;
+ DCL_BOOL fgAutoReload;
+} HGPT_CTRL_RESET_T;
+
+/* For HGPT_CMD_RESET command. */
+typedef DCL_UINT16 FGPT_CTRL_RETURN_COUNT_T;
+typedef DCL_UINT32 FGPT_CTRL_RETURN_COUNT_T_32bit;
+typedef DCL_UINT16 BUSY_WAIT_COUNT_T;
+typedef DCL_BOOL FGPT_CTRL_LOCK_T;
+//typedef DCL_UINT8 GPT_STATUS_T;
+typedef union
+{
+ HGPT_CTRL_CLK_T rHGPTClk;
+ HGPT_CTRL_RESET_T rHGPTReset;
+ FGPT_CTRL_RETURN_COUNT_T u2RetCount;
+ FGPT_CTRL_RETURN_COUNT_T_32bit u2RetCount_32bit;
+ BUSY_WAIT_COUNT_T uBusyWaitCount;
+ FGPT_CTRL_LOCK_T ulock;
+// GPT_STATUS_T gpt_status;
+} HGPT_CTRL;
+
+//void GPTI_BusyWait(kal_uint16 len);//modified by dongming for build error about GPTI_BuisyWait follow non_static declaration
+/* DCL for HW GPT */
+/*************************************************************************
+* FUNCTION
+* DclHGPT_Initialize
+*
+* DESCRIPTION
+* This function is to initialize HW GPT module.
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* DCL_STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclHGPT_Initialize(void);
+
+/*************************************************************************
+* FUNCTION
+* DclHGPT_Open
+*
+* DESCRIPTION
+* This function is to open a HW GPT module. Note that HW GPT only supports
+* single open for each valid eDev and if DCL_GPT1 is chosen SGPT may be
+* influenced and work abnormally.
+*
+* PARAMETERS
+* eDev - only valid for DCL_GPT1 and DCL_GPT2
+* flags - no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* DCL_HANDLE_INVALID - Open failed.
+* other value - a valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclHGPT_Open(DCL_DEV dev, DCL_FLAGS flags);
+
+/*************************************************************************
+* FUNCTION
+* DclHGPT_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the HW GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclHGPT_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+
+/*************************************************************************
+* FUNCTION
+* DclHGPT_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the HW GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclHGPT_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+
+/*************************************************************************
+* FUNCTION
+* DclHGPT_Configure
+*
+* DESCRIPTION
+* This function is not supported for the HW GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclHGPT_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+
+/*************************************************************************
+* FUNCTION
+* DclHGPT_RegisterCallback
+*
+* DESCRIPTION
+* This function is to set callback function for the HW GPT module.
+*
+* PARAMETERS
+* handle - hanlde previous got from DclHGPT_Open().
+* event - only support EVENT_HGPT_TIMEOUT event.
+* callback - the callback function when HW GPT is timeout.
+*
+* RETURNS
+* STATUS_OK - successfully register the callback function.
+* STATUS_INVALID_HANDLE - It's a invalid handle.
+* STATUS_NOT_OPENED - The module has not been opened.
+* STATUS_INVALID_EVENT - The event parameter is invalid.
+*
+*************************************************************************/
+extern DCL_STATUS DclHGPT_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+
+/*************************************************************************
+* FUNCTION
+* DclHGPT_Control
+*
+* DESCRIPTION
+* This function is to send command to control the HW GPT module.
+*
+* PARAMETERS
+* handle - a valid handle return by DclHGPT_Open()
+* cmd - a control command for HW GPT module
+* 1. HGPT_CMD_CLK: to set clock for a HW GPT timer
+* 2. HGPT_CMD_RESET: to reset a HWGPT timer
+* 3. HGPT_CMD_START: to start a HW GPT timer
+* 4. HGPT_CMD_STOP: to stop a HWGPT timer
+* data - for 1. HGPT_CMD_CLK: pointer to a HGPT_CTRL_CLK_T structure
+* 2. HGPT_CMD_RESET: pointer to a HGPT_CTRL_RESET_T structure
+* 3. HGPT_CMD_START: a NULL pointer
+* 4. HGPT_CMD_STOP: a NULL pointer
+*
+* RETURNS
+* STATUS_OK - command is executed successfully.
+* STATUS_FAIL - command is failed.
+* STATUS_INVALID_CMD - The command is invalid.
+* STATUS_INVALID_HANDLE - The handle is invalid.
+* STATUS_INVALID_CTRL_DATA - The ctrl data is not valid.
+*
+*************************************************************************/
+extern DCL_STATUS DclHGPT_Control(DCL_HANDLE handle, HGPT_CMD cmd, HGPT_CTRL *data);
+
+/*************************************************************************
+* FUNCTION
+* DclHGPT_Close
+*
+* DESCRIPTION
+* This function is to close a HW GPT module by a handle previous opened.
+*
+* PARAMETERS
+* handle - hanlde previous got from DclHGPT_Open().
+*
+* RETURNS
+* STATUS_OK - successful.
+* DCL_HANDLE_INVALID - it's a invalid handle.
+*
+*************************************************************************/
+extern DCL_STATUS DclHGPT_Close(DCL_HANDLE handle);
+
+/* DCL for Free Run HW GPT */
+/*************************************************************************
+* FUNCTION
+* DclFHGPT_Initialize
+*
+* DESCRIPTION
+* This function is to initialize the free run GPT module.
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* DCL_STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclFHGPT_Initialize(void);
+
+/*************************************************************************
+* FUNCTION
+* DclFHGPT_Open
+*
+* DESCRIPTION
+* This function is to open a free run GPT module if it exists. Note
+* that it supports multiple opens and no need to close it.
+*
+* PARAMETERS
+* eDev - only valid for DCL_GPT3
+* flags - no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* DCL_HANDLE_INVALID - Open failed. It means no free run GPT exists or
+* open a wrong device.
+* other value - a valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclFHGPT_Open(DCL_DEV dev, DCL_FLAGS flags);
+
+/*************************************************************************
+* FUNCTION
+* DclFHGPT_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the free run GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclFHGPT_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+
+/*************************************************************************
+* FUNCTION
+* DclFHGPT_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the free run GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclFHGPT_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+
+/*************************************************************************
+* FUNCTION
+* DclFHGPT_Configure
+*
+* DESCRIPTION
+* This function is not supported for the free run GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclFHGPT_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+
+/*************************************************************************
+* FUNCTION
+* DclFHGPT_RegisterCallback
+*
+* DESCRIPTION
+* This function is not supported for the free run GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclFHGPT_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+
+/*************************************************************************
+* FUNCTION
+* DclFHGPT_Control
+*
+* DESCRIPTION
+* This function is to send command to control the free run GPT module.
+*
+* PARAMETERS
+* handle - a valid handle return by DclFHGPT_Open()
+* cmd - a control command for free ryb GPT module
+* FGPT_CMD_RETURN_COUNT: to get the timer count
+* data - for FGPT_CMD_RETURN_COUNT: pointer to a FGPT_CTRL_RETURN_COUNT_T type
+*
+* RETURNS
+* STATUS_OK - command is executed successfully.
+* STATUS_FAIL - command is failed. No free run GPT is supported.
+* STATUS_INVALID_CMD - The command is invalid.
+* STATUS_INVALID_HANDLE - The handle is invalid.
+*
+*************************************************************************/
+extern DCL_STATUS DclFHGPT_Control(DCL_HANDLE handle, HGPT_CMD cmd, HGPT_CTRL *data);
+
+/*************************************************************************
+* FUNCTION
+* DclFHGPT_Close
+*
+* DESCRIPTION
+* This function is not supported for the free run GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclFHGPT_Close(DCL_HANDLE handle);
+
+kal_bool GPT_IsStop(void);
+
+
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_GPT_REG_DBG__)
+#define DRV_GPT_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+#define DRV_GPT_Reg(addr) DRV_DBG_Reg(addr)
+#define DRV_GPT_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define DRV_GPT_Reg32(addr) DRV_DBG_Reg32(addr)
+#define DRV_GPT_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+#define DRV_GPT_Reg8(addr) DRV_DBG_Reg8(addr)
+#define DRV_GPT_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+#define DRV_GPT_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+#define DRV_GPT_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#define DRV_GPT_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+#define DRV_GPT_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+#define DRV_GPT_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+#define DRV_GPT_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+#define DRV_GPT_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+#define DRV_GPT_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+#else
+#define DRV_GPT_WriteReg(addr,data) DRV_WriteReg(addr,data)
+#define DRV_GPT_Reg(addr) DRV_Reg(addr)
+#define DRV_GPT_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define DRV_GPT_Reg32(addr) DRV_Reg32(addr)
+#define DRV_GPT_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+#define DRV_GPT_Reg8(addr) DRV_Reg8(addr)
+#define DRV_GPT_ClearBits(addr,data) DRV_ClearBits(addr,data)
+#define DRV_GPT_SetBits(addr,data) DRV_SetBits(addr,data)
+#define DRV_GPT_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define DRV_GPT_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+#define DRV_GPT_SetBits32(addr,data) DRV_SetBits32(addr,data)
+#define DRV_GPT_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+#define DRV_GPT_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+#define DRV_GPT_SetBits8(addr,data) DRV_SetBits8(addr,data)
+#define DRV_GPT_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_GPT_REG_DBG__)
+
+
+#endif
diff --git a/mcu/driver/peripheral/inc/dcl_hts.h b/mcu/driver/peripheral/inc/dcl_hts.h
new file mode 100644
index 0000000..ab84c4f
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_hts.h
@@ -0,0 +1,331 @@
+#ifndef DCL_HTS_H_
+#define DCL_HTS_H_
+
+#include "dcl.h"
+
+#define DCL_HTS_MAGIC_NUM 0x40000000
+
+typedef DCL_UINT32 HTS_DEV;
+typedef enum
+{
+ TOUCH_PANEL_R=1
+}HTS_DEV_T;
+
+typedef DCL_UINT32 HTS_EVENT;
+typedef enum
+{
+ DCL_EVENT_HTS_PEN_DOWN=1,
+ DCL_EVENT_HTS_PEN_UP,
+ DCL_EVENT_HTS_MAX
+}HTS_EVENT_T;
+
+//touch panel driver command of hardware layer.
+typedef DCL_UINT32 HTS_CMD;
+
+typedef enum
+{
+ HTS_CMD_GET_TP_ADC,
+ HTS_CMD_TS_READ_ADC,
+ HTS_CMD_GET_TP_LEVEL,
+ HTS_CMD_GET_TP_LEVEL_PRESSURE,
+ HTS_CMD_TP_UPDATENOTIFY,
+ HTS_CMD_GET_TP_PRESSURE,
+ HTS_CMD_TP_PRESSURE_VALUE,
+ HTS_CMD_SET_CONFIG,
+ HTS_CMD_GET_TP_POINT,
+ HTS_CMD_GET_TP_POINT_NUM,
+ HTS_CMD_GET_TP_TYPE,
+ HTS_CMD_SET_CALI_VALUE,
+ HTS_CMD_GET_CALI_VALUE,
+ HTS_CMD_SET_DEBOUNCE_TIME,
+ HTS_CMD_GET_DEBOUNCE_TIME,
+ HTS_CMD_SET_SPL_NUM,
+ HTS_CMD_GET_SPL_NUM
+}HTS_CMD_T;
+
+//HTS_CMD_SET_DEBOUNCE_TIME
+typedef struct
+{
+ DCL_UINT32 u4DebounceTime;
+}HTS_CTRL_DT_T;
+
+
+//HTS_CMD_TP_SET_PARAMETERS
+typedef struct
+{
+ DCL_UINT32 u4SampleResolution;
+ DCL_UINT32 u4ModeSelection;
+} HTS_CTRL_CONFIG_T;
+typedef enum {
+ //Not use the same values as ts_hw.h
+ //Otherwise it easy to cause bug if change ts_hw.h, but forget to change these
+ DCL_TS_CMD_DIFFERENTIAL,
+ DCL_TS_CMD_SINGLE_END,
+ DCL_TS_CMD_MODE_8BIT,
+ DCL_TS_CMD_MODE_10BIT,
+ DCL_TS_CMD_MODE_12BIT
+} HTS_PARAMETER_T;
+
+//HTS_CMD_TP_LEVEL,
+typedef struct
+{
+ DCL_BOOL fgIsUP;
+ DCL_UINT32 pressure_value;
+} HTS_CTRL_TL_T;
+
+
+//HTS_CMD_TP_READ_ADC
+typedef struct
+{
+ DCL_INT16 *pi2x;
+ DCL_INT16 *pi2y;
+} HTS_CTRL_TPRA_T;
+
+//HTS_CMD_TS_READ_ADC
+typedef enum {
+ TS_COORD_HTS_ADDR_Y,
+ TS_COORD_HTS_ADDR_Z1,
+ TS_COORD_HTS_ADDR_Z2,
+ TS_COORD_HTS_ADDR_X
+} TS_COORD_ENUM;
+typedef struct
+{
+ DCL_INT16 i2AdcValue;
+ TS_COORD_ENUM uCoord;
+} HTS_CTRL_TSRA_T;
+
+//HTS_CMD_TP_PRESSURE
+typedef struct
+{
+ DCL_BOOL fgIsPressed;
+} HTS_CTRL_TPP_T;
+
+//HTS_CMD_TP_PRESSURE_VALUE
+typedef struct
+{
+ DCL_INT32 fgPressureValue;
+} HTS_CTRL_TPPV_T;
+//HTS_CMD_READ_ADC
+typedef struct
+{
+ DCL_INT16 *pi2x;
+ DCL_INT16 *pi2y;
+} HTS_CTRL_RA_T;
+
+//HTS_CMD_ADC_TO_COORDINATE
+typedef struct
+{
+ DCL_BOOL fgValid;
+ DCL_INT16 *pi2x;
+ DCL_INT16 *pi2y;
+} HTS_CTRL_ATC_T;
+
+//HTS_CMD_GET_SPL_NUM
+typedef struct
+{
+ DCL_UINT32 u4SPLNum;
+}HTS_CTRL_SN_T;
+
+typedef union
+{
+ HTS_CTRL_TL_T rTSCtrlTL;
+ HTS_CTRL_TPRA_T rTSCtrlTPRA;
+ HTS_CTRL_TSRA_T rTSCtrlTSRA;
+ HTS_CTRL_TPP_T rTSCtrlTPP;
+ HTS_CTRL_TPPV_T rTSCtrlTPPV;
+ HTS_CTRL_RA_T rTSCtrlRA;
+ HTS_CTRL_ATC_T rTSCtrlATC;
+ HTS_CTRL_CONFIG_T rTSCtrlConfig;
+ HTS_CTRL_DT_T rTSCtrlDebouncetime;
+ HTS_CTRL_SN_T rTSCtrlSPLNum;
+}HTS_CTRL_DATA_T;
+
+
+/*************************************************************************
+* FUNCTION
+* DclHTS_Close
+*
+* DESCRIPTION
+* This function is to close the HW TS module.
+*
+* CALLS
+* It is called to close HW TS module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* DCL_STATUS_OK
+* STATUS_INVALID_ARGUMENT: invalid arguments
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclHTS_Close(DCL_HANDLE handle);
+/*************************************************************************
+* FUNCTION
+* DclHTS_Configure
+*
+* DESCRIPTION
+* This function is to configure the HW TS module.
+*
+* CALLS
+* It is called to configure of the HW TS module.
+*
+* PARAMETERS
+* handle - a valid handle return by DclHTS_Open()
+* configure - a structure which include the TS configuration.
+*
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: not open yet.
+* STATUS_INVALID_ARGUMENT: not a valid handle.
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+//extern DCL_STATUS DclHTS_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+/*************************************************************************
+* FUNCTION
+* DclHTS_Control
+*
+* DESCRIPTION
+* This function is to send command to control the TS module.
+*
+* CALLS
+* It is called to send command to control the TS module.
+*
+* PARAMETERS
+* handle - a valid handle return by DclHTS_Open()
+* cmd - a control command for TS module
+* 1. HTS_CMD_TP_LEVEL :to detect whether TP is touched or NOT
+* 2. HTS_CMD_TP_UPDATE_NOTIFY :to set a event to TP task to indicate we are at UP state
+* 3. HTS_CMD_TP_READ_ADC :to read x and y adc value from AUXADC HW. (with touch_panel_filter_thresold which avoid detect error)
+* 4. HTS_CMD_TP_PRESSURE :to check is touch panel pressed.
+* 5. HTS_CMD_TS_DRV_INIT :to initial HW driver and switch on work around funciton
+* 6. HTS_CMD_READ_ADC :to read adc from touch panel module. (with Landscape support, compile option: __PORTRAIT_LCM_SIMULATE_LANDSCAPE_LCM__)
+* 7. HTS_CMD_TS_READ_ADC :to read x or y adc value from AUXADC HW.
+*
+* data - a union of DCL_CTRL_DATA_T
+* rTSCtrlTL; //HTS_CTRL_TL_T
+* rTSCtrlTPRA; //HTS_CTRL_TPRA_T
+* rTSCtrlTPP; //HTS_CTRL_TPP_T
+* rTSCtrlRA; //HTS_CTRL_RA_T
+* rTSCtrlTSRA //HTS_CMD_TS_READ_ADC
+*
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+* STATUS_INVALID_ARGUMENT: not a valid handle.
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclHTS_Control(DCL_HANDLE handle, HTS_CMD cmd, HTS_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclHTS_Initialize
+*
+* DESCRIPTION
+* This function is to initialize HW TS module
+*
+* CALLS
+* It is called to initialize HW TS module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* DCL_STATUS_OK
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclHTS_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclHTS_Open
+*
+* DESCRIPTION
+* This function is to open the TS HW module and return a handle
+*
+* CALLS
+* It is called to open HW TS module
+*
+* PARAMETERS
+* dev - valid for DCL_TS
+* flags - no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* DCL_HANDLE_INVALID - Open failed.
+* Other value - a valid handle
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_HANDLE DclHTS_Open(HTS_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* DclHTS_ReadData
+*
+* DESCRIPTION
+* This function unsupported.
+*
+* CALLS
+* It is unsupported.
+*
+* PARAMETERS
+* handle
+* buff
+* buf_len
+* options
+*
+* RETURNS
+* STATUS_UNSUPPORTED: command unsupported
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclHTS_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclHTS_RegisterCallback
+*
+* DESCRIPTION
+* This function is to register HW TS call back funciton.
+*
+* CALLS
+* It is called to register HW TS call back funciton.
+*
+* PARAMETERS
+* event - a valid event indicate register which event's call back funciton
+* 1. DCL_EVENT_HTS_PEN_DOWN,
+* 2. DCL_EVENT_HTS_PEN_UP
+* callback - a call back funciton
+*
+* RETURNS
+* STATUS_OK: register is executed successfully.
+* STATUS_FAIL: register is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclHTS_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+
+
+
+
+
+
+#endif
+
+
+
+
+
+
+
+
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmic6320_hw.h b/mcu/driver/peripheral/inc/dcl_pmic6320_hw.h
new file mode 100644
index 0000000..e454ff1
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmic6320_hw.h
@@ -0,0 +1,745 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6320_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6320
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DCL_PMIC6320_HW_H_STRUCT__
+#define __DCL_PMIC6320_HW_H_STRUCT__
+
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6320_REG_API)
+
+#define PMIC_BASE (0x0000)
+#define DEW_BASE (0xBC00)
+#define MT6320_E1_CID 0x1020
+
+//register number
+#define CHR_CON0 0x0000
+#define CHR_CON1 0x0002
+#define CHR_CON2 0x0004
+#define CHR_CON3 0x0006
+#define CHR_CON4 0x0008
+#define CHR_CON5 0x000A
+#define CHR_CON6 0x000C
+#define CHR_CON7 0x000E
+#define CHR_CON8 0x0010
+#define CHR_CON9 0x0012
+#define CHR_CON10 0x0014
+#define CHR_CON11 0x0016
+#define CHR_CON12 0x0018
+#define CHR_CON13 0x001A
+#define CHR_CON14 0x001C
+#define CHR_CON15 0x001E
+#define CHR_CON16 0x0020
+#define CHR_CON17 0x0022
+#define CHR_CON18 0x0024
+#define CHR_CON19 0x0026
+#define CHR_CON20 0x0028
+#define CHR_CON21 0x002A
+#define CHR_CON22 0x002C
+#define CHR_CON23 0x002E
+#define CHR_CON24 0x0030
+#define CHR_CON25 0x0032
+#define CHR_CON26 0x0034
+#define CHR_CON27 0x0036
+#define CHR_CON28 0x0038
+#define CHR_CON29 0x003A
+#define CID 0x0100
+#define TOP_CKPDN 0x0102
+#define TOP_CKPDN2 0x0108
+#define TOP_GPIO_CKPDN 0x010E
+#define TOP_RST_CON 0x0114
+#define WRP_CKPDN 0x011A
+#define WRP_RST_CON 0x0120
+#define TOP_RST_MISC 0x0126
+#define TOP_CKCON1 0x0128
+#define TOP_CKCON2 0x012A
+#define TOP_CKTST1 0x012C
+#define TOP_CKTST2 0x012E
+#define OC_DEG_EN 0x0130
+#define OC_CTL0 0x0132
+#define OC_CTL1 0x0134
+#define OC_CTL2 0x0136
+#define INT_RSV 0x0138
+#define TEST_CON0 0x013A
+#define TEST_CON1 0x013C
+#define STATUS0 0x013E
+#define STATUS1 0x0140
+#define PGSTATUS 0x0142
+#define CHRSTATUS 0x0144
+#define OCSTATUS0 0x0146
+#define OCSTATUS1 0x0148
+#define OCSTATUS2 0x014A
+#define SIMLS_CON 0x014C
+#define TEST_OUT_L 0x014E
+#define TEST_OUT_H 0x0150
+#define TDSEL_CON 0x0152
+#define RDSEL_CON 0x0154
+#define GPIO_SMT_CON0 0x0156
+#define GPIO_SMT_CON1 0x0158
+#define GPIO_SMT_CON2 0x015A
+#define GPIO_SMT_CON3 0x015C
+#define DRV_CON0 0x015E
+#define DRV_CON1 0x0160
+#define DRV_CON2 0x0162
+#define DRV_CON3 0x0164
+#define DRV_CON4 0x0166
+#define DRV_CON5 0x0168
+#define DRV_CON6 0x016A
+#define DRV_CON7 0x016C
+#define DRV_CON8 0x016E
+#define DRV_CON9 0x0170
+#define DRV_CON10 0x0172
+#define DRV_CON11 0x0174
+#define DRV_CON12 0x0176
+#define INT_CON0 0x0178
+#define INT_CON1 0x017E
+#define INT_STATUS0 0x0184
+#define INT_STATUS1 0x0186
+#define FQMTR_CON0 0x0188
+#define FQMTR_CON1 0x018A
+#define FQMTR_CON2 0x018C
+#define EFUSE_CON0 0x018E
+#define EFUSE_CON1 0x0190
+#define EFUSE_CON2 0x0192
+#define EFUSE_CON3 0x0194
+#define EFUSE_CON4 0x0196
+#define EFUSE_CON5 0x0198
+#define EFUSE_CON6 0x019A
+#define EFUSE_VAL_0_15 0x019C
+#define EFUSE_VAL_16_31 0x019E
+#define EFUSE_VAL_32_47 0x01A0
+#define EFUSE_VAL_48_63 0x01A2
+#define EFUSE_VAL_64_79 0x01A4
+#define EFUSE_VAL_80_95 0x01A6
+#define EFUSE_VAL_96_111 0x01A8
+#define EFUSE_VAL_112_127 0x01AA
+#define EFUSE_VAL_128_143 0x01AC
+#define EFUSE_VAL_144_159 0x01AE
+#define EFUSE_VAL_160_175 0x01B0
+#define EFUSE_VAL_176_191 0x01B2
+#define EFUSE_DOUT_0_15 0x01B4
+#define EFUSE_DOUT_16_31 0x01B6
+#define EFUSE_DOUT_32_47 0x01B8
+#define EFUSE_DOUT_48_63 0x01BA
+#define EFUSE_DOUT_64_79 0x01BC
+#define EFUSE_DOUT_80_95 0x01BE
+#define EFUSE_DOUT_96_111 0x01C0
+#define EFUSE_DOUT_112_127 0x01C2
+#define EFUSE_DOUT_128_143 0x01C4
+#define EFUSE_DOUT_144_159 0x01C6
+#define EFUSE_DOUT_160_175 0x01C8
+#define EFUSE_DOUT_176_191 0x01CA
+#define SPI_CON 0x01CC
+#define BUCK_CON0 0x0200
+#define BUCK_CON1 0x0202
+#define BUCK_CON2 0x0204
+#define VPROC_CON0 0x0206
+#define VPROC_CON1 0x0208
+#define VPROC_CON2 0x020A
+#define VPROC_CON3 0x020C
+#define VPROC_CON4 0x020E
+#define VPROC_CON5 0x0210
+#define VPROC_CON6 0x0212
+#define VPROC_CON7 0x0214
+#define VPROC_CON8 0x0216
+#define VPROC_CON9 0x0218
+#define VPROC_CON10 0x021A
+#define VPROC_CON11 0x021C
+#define VPROC_CON12 0x021E
+#define VPROC_CON13 0x0220
+#define VPROC_CON14 0x0222
+#define VPROC_CON15 0x0224
+#define VPROC_CON16 0x0226
+#define VPROC_CON17 0x0228
+#define VPROC_CON18 0x022A
+#define VSRAM_CON0 0x022C
+#define VSRAM_CON1 0x022E
+#define VSRAM_CON2 0x0230
+#define VSRAM_CON3 0x0232
+#define VSRAM_CON4 0x0234
+#define VSRAM_CON5 0x0236
+#define VSRAM_CON6 0x0238
+#define VSRAM_CON7 0x023A
+#define VSRAM_CON8 0x023C
+#define VSRAM_CON9 0x023E
+#define VSRAM_CON10 0x0240
+#define VSRAM_CON11 0x0242
+#define VSRAM_CON12 0x0244
+#define VSRAM_CON13 0x0246
+#define VSRAM_CON14 0x0248
+#define VSRAM_CON15 0x024A
+#define VSRAM_CON16 0x024C
+#define VSRAM_CON17 0x024E
+#define VSRAM_CON18 0x0250
+#define VSRAM_CON19 0x0252
+#define VSRAM_CON20 0x0254
+#define VSRAM_CON21 0x0256
+#define VCORE_CON0 0x0258
+#define VCORE_CON1 0x025A
+#define VCORE_CON2 0x025C
+#define VCORE_CON3 0x025E
+#define VCORE_CON4 0x0260
+#define VCORE_CON5 0x0262
+#define VCORE_CON6 0x0264
+#define VCORE_CON7 0x0266
+#define VCORE_CON8 0x0268
+#define VCORE_CON9 0x026A
+#define VCORE_CON10 0x026C
+#define VCORE_CON11 0x026E
+#define VCORE_CON12 0x0270
+#define VCORE_CON13 0x0272
+#define VCORE_CON14 0x0274
+#define VCORE_CON15 0x0276
+#define VCORE_CON16 0x0278
+#define VCORE_CON17 0x027A
+#define VCORE_CON18 0x027C
+#define VM_CON0 0x027E
+#define VM_CON1 0x0280
+#define VM_CON2 0x0282
+#define VM_CON3 0x0284
+#define VM_CON4 0x0286
+#define VM_CON5 0x0288
+#define VM_CON6 0x028A
+#define VM_CON7 0x028C
+#define VM_CON8 0x028E
+#define VM_CON9 0x0290
+#define VM_CON10 0x0292
+#define VM_CON11 0x0294
+#define VM_CON12 0x0296
+#define VM_CON13 0x0298
+#define VM_CON14 0x029A
+#define VM_CON15 0x029C
+#define VM_CON16 0x029E
+#define VM_CON17 0x02A0
+#define VM_CON18 0x02A2
+#define VIO18_CON0 0x0300
+#define VIO18_CON1 0x0302
+#define VIO18_CON2 0x0304
+#define VIO18_CON3 0x0306
+#define VIO18_CON4 0x0308
+#define VIO18_CON5 0x030A
+#define VIO18_CON6 0x030C
+#define VIO18_CON7 0x030E
+#define VIO18_CON8 0x0310
+#define VIO18_CON9 0x0312
+#define VIO18_CON10 0x0314
+#define VIO18_CON11 0x0316
+#define VIO18_CON12 0x0318
+#define VIO18_CON13 0x031A
+#define VIO18_CON14 0x031C
+#define VIO18_CON15 0x031E
+#define VIO18_CON16 0x0320
+#define VIO18_CON17 0x0322
+#define VIO18_CON18 0x0324
+#define VPA_CON0 0x0326
+#define VPA_CON1 0x0328
+#define VPA_CON2 0x032A
+#define VPA_CON3 0x032C
+#define VPA_CON4 0x032E
+#define VPA_CON5 0x0330
+#define VPA_CON6 0x0332
+#define VPA_CON7 0x0334
+#define VPA_CON8 0x0336
+#define VPA_CON9 0x0338
+#define VPA_CON10 0x033A
+#define VPA_CON11 0x033C
+#define VPA_CON12 0x033E
+#define VPA_CON13 0x0340
+#define VPA_CON14 0x0342
+#define VPA_CON15 0x0344
+#define VPA_CON16 0x0346
+#define VPA_CON17 0x0348
+#define VPA_CON18 0x034A
+#define VPA_CON19 0x034C
+#define VPA_CON20 0x034E
+#define VRF18_CON0 0x0350
+#define VRF18_CON1 0x0352
+#define VRF18_CON2 0x0354
+#define VRF18_CON3 0x0356
+#define VRF18_CON4 0x0358
+#define VRF18_CON5 0x035A
+#define VRF18_CON6 0x035C
+#define VRF18_CON7 0x035E
+#define VRF18_CON8 0x0360
+#define VRF18_CON9 0x0362
+#define VRF18_CON10 0x0364
+#define VRF18_CON11 0x0366
+#define VRF18_CON12 0x0368
+#define VRF18_CON13 0x036A
+#define VRF18_CON14 0x036C
+#define VRF18_CON15 0x036E
+#define VRF18_CON16 0x0370
+#define VRF18_CON17 0x0372
+#define VRF18_CON18 0x0374
+#define VRF18_CON19 0x0376
+#define VRF18_CON20 0x0378
+#define VRF18_2_CON0 0x037A
+#define VRF18_2_CON1 0x037C
+#define VRF18_2_CON2 0x037E
+#define VRF18_2_CON3 0x0380
+#define VRF18_2_CON4 0x0382
+#define VRF18_2_CON5 0x0384
+#define VRF18_2_CON6 0x0386
+#define VRF18_2_CON7 0x0388
+#define VRF18_2_CON8 0x038A
+#define VRF18_2_CON9 0x038C
+#define VRF18_2_CON10 0x038E
+#define VRF18_2_CON11 0x0390
+#define VRF18_2_CON12 0x0392
+#define VRF18_2_CON13 0x0394
+#define VRF18_2_CON14 0x0396
+#define VRF18_2_CON15 0x0398
+#define VRF18_2_CON16 0x039A
+#define VRF18_2_CON17 0x039C
+#define VRF18_2_CON18 0x039E
+#define BUCK_K_CON0 0x03A0
+#define BUCK_K_CON1 0x03A2
+#define ANALDO_CON0 0x0400
+#define ANALDO_CON1 0x0402
+#define ANALDO_CON2 0x0404
+#define ANALDO_CON3 0x0406
+#define ANALDO_CON4 0x0408
+#define ANALDO_CON5 0x040A
+#define ANALDO_CON6 0x040C
+#define ANALDO_CON7 0x040E
+#define ANALDO_CON8 0x0410
+#define ANALDO_CON9 0x0412
+#define ANALDO_CON10 0x0414
+#define ANALDO_CON11 0x0416
+#define ANALDO_CON12 0x0418
+#define ANALDO_CON13 0x041A
+#define ANALDO_CON14 0x041C
+#define ANALDO_CON15 0x041E
+#define DIGLDO_CON0 0x0420
+#define DIGLDO_CON2 0x0422
+#define DIGLDO_CON3 0x0424
+#define DIGLDO_CON5 0x0426
+#define DIGLDO_CON6 0x0428
+#define DIGLDO_CON7 0x042A
+#define DIGLDO_CON8 0x042C
+#define DIGLDO_CON9 0x042E
+#define DIGLDO_CON10 0x0430
+#define DIGLDO_CON11 0x0432
+#define DIGLDO_CON12 0x0434
+#define DIGLDO_CON13 0x0436
+#define DIGLDO_CON14 0x0438
+#define DIGLDO_CON15 0x043A
+#define DIGLDO_CON16 0x043C
+#define DIGLDO_CON17 0x043E
+#define DIGLDO_CON18 0x0440
+#define DIGLDO_CON19 0x0442
+#define DIGLDO_CON20 0x0444
+#define DIGLDO_CON21 0x0446
+#define DIGLDO_CON23 0x0448
+#define DIGLDO_CON24 0x044A
+#define DIGLDO_CON26 0x044C
+#define DIGLDO_CON27 0x044E
+#define DIGLDO_CON28 0x0450
+#define DIGLDO_CON29 0x0452
+#define DIGLDO_CON30 0x0454
+#define DIGLDO_CON31 0x0456
+#define DIGLDO_CON32 0x0458
+#define DIGLDO_CON33 0x045A
+#define DIGLDO_CON34 0x045C
+#define DIGLDO_CON35 0x045E
+#define DIGLDO_CON36 0x0460
+#define DIGLDO_CON37 0x0462
+#define DIGLDO_CON38 0x0464
+#define DIGLDO_CON39 0x0466
+#define DIGLDO_CON40 0x0468
+#define DIGLDO_CON41 0x046A
+#define DIGLDO_CON42 0x046C
+#define DIGLDO_CON43 0x046E
+#define DIGLDO_CON44 0x0470
+#define STRUP_CON0 0x0500
+#define STRUP_CON2 0x0502
+#define STRUP_CON3 0x0504
+#define STRUP_CON4 0x0506
+#define STRUP_CON5 0x0508
+#define STRUP_CON6 0x050A
+#define STRUP_CON7 0x050C
+#define STRUP_CON8 0x050E
+#define STRUP_CON9 0x0510
+#define AUXADC_ADC0 0x0512
+#define AUXADC_ADC1 0x0514
+#define AUXADC_ADC2 0x0516
+#define AUXADC_ADC3 0x0518
+#define AUXADC_ADC4 0x051A
+#define AUXADC_ADC5 0x051C
+#define AUXADC_ADC6 0x051E
+#define AUXADC_ADC7 0x0520
+#define AUXADC_ADC8 0x0522
+#define AUXADC_ADC9 0x0524
+#define AUXADC_ADC10 0x0526
+#define AUXADC_ADC11 0x0528
+#define AUXADC_ADC12 0x052A
+#define AUXADC_ADC13 0x052C
+#define AUXADC_ADC14 0x052E
+#define AUXADC_ADC15 0x0530
+#define AUXADC_ADC16 0x0532
+#define AUXADC_ADC17 0x0534
+#define AUXADC_ADC18 0x0536
+#define AUXADC_ADC19 0x0538
+#define AUXADC_ADC20 0x053A
+#define AUXADC_ADC21 0x053C
+#define AUXADC_ADC22 0x053E
+#define AUXADC_CON0 0x0540
+#define AUXADC_CON1 0x0542
+#define AUXADC_CON2 0x0544
+#define AUXADC_CON3 0x0546
+#define AUXADC_CON4 0x0548
+#define AUXADC_CON5 0x054A
+#define AUXADC_CON6 0x054C
+#define AUXADC_CON7 0x054E
+#define AUXADC_CON8 0x0550
+#define AUXADC_CON9 0x0552
+#define AUXADC_CON10 0x0554
+#define AUXADC_CON11 0x0556
+#define AUXADC_CON12 0x0558
+#define AUXADC_CON13 0x055A
+#define AUXADC_CON14 0x055C
+#define FLASH_CON0 0x055E
+#define FLASH_CON1 0x0560
+#define FLASH_CON2 0x0562
+#define KPLED_CON0 0x0564
+#define KPLED_CON1 0x0566
+#define KPLED_CON2 0x0568
+#define ISINKS_CON0 0x056A
+#define ISINKS_CON1 0x056C
+#define ISINKS_CON2 0x056E
+#define ISINKS_CON3 0x0570
+#define ISINKS_CON4 0x0572
+#define ISINKS_CON5 0x0574
+#define ISINKS_CON6 0x0576
+#define ISINKS_CON7 0x0578
+#define ISINKS_CON8 0x057A
+#define ISINKS_CON9 0x057C
+#define ISINKS_CON10 0x057E
+#define ISINKS_CON11 0x0580
+#define ACCDET_CON0 0x0582
+#define ACCDET_CON1 0x0584
+#define ACCDET_CON2 0x0586
+#define ACCDET_CON3 0x0588
+#define ACCDET_CON4 0x058A
+#define ACCDET_CON5 0x058C
+#define ACCDET_CON6 0x058E
+#define ACCDET_CON7 0x0590
+#define ACCDET_CON8 0x0592
+#define ACCDET_CON9 0x0594
+#define ACCDET_CON10 0x0596
+#define ACCDET_CON11 0x0598
+#define ACCDET_CON12 0x059A
+#define ACCDET_CON13 0x059C
+#define ACCDET_CON14 0x059E
+#define ACCDET_CON15 0x05A0
+#define ACCDET_CON16 0x05A2
+#define SPK_CON0 0x0600
+#define SPK_CON1 0x0602
+#define SPK_CON2 0x0604
+#define SPK_CON3 0x0606
+#define SPK_CON4 0x0608
+#define SPK_CON5 0x060A
+#define SPK_CON6 0x060C
+#define SPK_CON7 0x060E
+#define SPK_CON8 0x0610
+#define SPK_CON9 0x0612
+#define SPK_CON10 0x0614
+#define SPK_CON11 0x0616
+#define FGADC_CON0 0x0618
+#define FGADC_CON1 0x061A
+#define FGADC_CON2 0x061C
+#define FGADC_CON3 0x061E
+#define FGADC_CON4 0x0620
+#define FGADC_CON5 0x0622
+#define FGADC_CON6 0x0624
+#define FGADC_CON7 0x0626
+#define FGADC_CON8 0x0628
+#define FGADC_CON9 0x062A
+#define FGADC_CON10 0x062C
+#define FGADC_CON11 0x062E
+#define FGADC_CON12 0x0630
+#define FGADC_CON13 0x0632
+#define FGADC_CON14 0x0634
+#define FGADC_CON15 0x0636
+#define FGADC_CON16 0x0638
+#define FGADC_CON17 0x063A
+#define FGADC_CON18 0x063C
+#define FGADC_CON19 0x063E
+#define RTC_MIX_CON0 0x0640
+#define RTC_MIX_CON1 0x0642
+#define AUDDAC_CON0 0x0700
+#define AUDBUF_CFG0 0x0702
+#define AUDBUF_CFG1 0x0704
+#define AUDBUF_CFG2 0x0706
+#define AUDBUF_CFG3 0x0708
+#define AUDBUF_CFG4 0x070A
+#define IBIASDIST_CFG0 0x070C
+#define AUDACCDEPOP_CFG0 0x070E
+#define AUD_IV_CFG0 0x0710
+#define AUDCLKGEN_CFG0 0x0712
+#define AUDLDO_CFG0 0x0714
+#define AUDLDO_CFG1 0x0716
+#define AUDNVREGGLB_CFG0 0x0718
+#define AUD_NCP0 0x071A
+#define AUDPREAMP_CON0 0x071C
+#define AUDADC_CON0 0x071E
+#define AUDADC_CON1 0x0720
+#define AUDADC_CON2 0x0722
+#define AUDADC_CON3 0x0724
+#define AUDADC_CON4 0x0726
+#define AUDADC_CON5 0x0728
+#define AUDADC_CON6 0x072A
+#define AUDDIGMI_CON0 0x072C
+#define AUDLSBUF_CON0 0x072E
+#define AUDLSBUF_CON1 0x0730
+#define AUDENCSPARE_CON0 0x0732
+#define AUDENCCLKSQ_CON0 0x0734
+#define AUDPREAMPGAIN_CON0 0x0736
+#define ZCD_CON0 0x0738
+#define ZCD_CON1 0x073A
+#define ZCD_CON2 0x073C
+#define ZCD_CON3 0x073E
+#define ZCD_CON4 0x0740
+#define ZCD_CON5 0x0742
+#define NCP_CLKDIV_CON0 0x0744
+#define NCP_CLKDIV_CON1 0x0746
+
+//mask is HEX
+//shift is Integer
+#define STATUS_VSIM1_EN_MASK 0x1
+#define STATUS_VSIM1_EN_SHIFT 12
+#define STATUS_VSIM2_EN_MASK 0x1
+#define STATUS_VSIM2_EN_SHIFT 11
+#define OC_STATUS_VSIM1_MASK 0x1
+#define OC_STATUS_VSIM1_SHIFT 12
+#define OC_STATUS_VSIM2_MASK 0x1
+#define OC_STATUS_VSIM2_SHIFT 11
+#define RG_SIMLS2_SRST_CONF_MASK 0xF
+#define RG_SIMLS2_SRST_CONF_SHIFT 12
+#define RG_SIMLS2_SCLK_CONF_MASK 0xF
+#define RG_SIMLS2_SCLK_CONF_SHIFT 8
+#define RG_SIMLS1_SRST_CONF_MASK 0xF
+#define RG_SIMLS1_SRST_CONF_SHIFT 4
+#define RG_SIMLS1_SCLK_CONF_MASK 0xF
+#define RG_SIMLS1_SCLK_CONF_SHIFT 0
+#define RG_SIMLS_TDSEL_MASK 0x3
+#define RG_SIMLS_TDSEL_SHIFT 7
+#define RG_SIMAP_TDSEL_MASK 0x1
+#define RG_SIMAP_TDSEL_SHIFT 0
+#define RG_SIMLS_RDSEL_MASK 0x3
+#define RG_SIMLS_RDSEL_SHIFT 7
+#define RG_SIMAP_RDSEL_MASK 0x1
+#define RG_SIMAP_RDSEL_SHIFT 0
+#define RG_OCTL_SIM1_AP_SRST_MASK 0xF
+#define RG_OCTL_SIM1_AP_SRST_SHIFT 12
+#define RG_OCTL_SIM1_AP_SCLK_MASK 0xF
+#define RG_OCTL_SIM1_AP_SCLK_SHIFT 8
+#define RG_OCTL_SIMLS1_SRST_MASK 0xF
+#define RG_OCTL_SIMLS1_SRST_SHIFT 12
+#define RG_OCTL_SIMLS1_SCLK_MASK 0xF
+#define RG_OCTL_SIMLS1_SCLK_SHIFT 8
+#define RG_OCTL_SIM2_AP_SRST_MASK 0xF
+#define RG_OCTL_SIM2_AP_SRST_SHIFT 4
+#define RG_OCTL_SIM2_AP_SCLK_MASK 0xF
+#define RG_OCTL_SIM2_AP_SCLK_SHIFT 0
+#define RG_OCTL_SIMLS2_SRST_MASK 0xF
+#define RG_OCTL_SIMLS2_SRST_SHIFT 4
+#define RG_OCTL_SIMLS2_SCLK_MASK 0xF
+#define RG_OCTL_SIMLS2_SCLK_SHIFT 0
+#define RG_VIO18_MODESET_MASK 0x1
+#define RG_VIO18_MODESET_SHIFT 8
+#define RG_VPA_MODESET_MASK 0x1
+#define RG_VPA_MODESET_SHIFT 8
+#define VPA_EN_MASK 0x1
+#define VPA_EN_SHIFT 0
+#define RG_VRF18_MODESET_MASK 0x1
+#define RG_VRF18_MODESET_SHIFT 8
+#define RG_VRF18_BK_LDO_MASK 0x1
+#define RG_VRF18_BK_LDO_SHIFT 1
+#define VRF18_EN_CTRL_MASK 0x1
+#define VRF18_EN_CTRL_SHIFT 0
+#define VRF18_EN_MASK 0x1
+#define VRF18_EN_SHIFT 0
+#define RG_VRF18_2_MODESET_MASK 0x1
+#define RG_VRF18_2_MODESET_SHIFT 8
+#define RG_VRF18_2_BK_LDO_MASK 0x1
+#define RG_VRF18_2_BK_LDO_SHIFT 1
+#define VRF18_2_EN_CTRL_MASK 0x1
+#define VRF18_2_EN_CTRL_SHIFT 0
+#define VRF18_2_EN_SEL_MASK 0x7
+#define VRF18_2_EN_SEL_SHIFT 0
+#define VRF18_2_EN_MASK 0x1
+#define VRF18_2_EN_SHIFT 0
+#define VRF28_ON_CTRL_MASK 0x1
+#define VRF28_ON_CTRL_SHIFT 14
+#define RG_VRF28_EN_MASK 0x1
+#define RG_VRF28_EN_SHIFT 12
+#define VRF28_SRCLK_EN_SEL_MASK 0x7
+#define VRF28_SRCLK_EN_SEL_SHIFT 4
+#define VRF28_ON_2_CTRL_MASK 0x1
+#define VRF28_ON_2_CTRL_SHIFT 14
+#define RG_VRF28_2_EN_MASK 0x1
+#define RG_VRF28_2_EN_SHIFT 12
+#define VRF28_2_SRCLK_EN_SEL_MASK 0x7
+#define VRF28_2_SRCLK_EN_SEL_SHIFT 4
+#define RG_VSIM1_EN_MASK 0x1
+#define RG_VSIM1_EN_SHIFT 15
+#define RG_VSIM1_STBTD_MASK 0x3
+#define RG_VSIM1_STBTD_SHIFT 12
+#define QI_VSIM1_MODE_MASK 0x1
+#define QI_VSIM1_MODE_SHIFT 7
+#define VSIM1_SRCLK_MODE_SEL_MASK 0x7
+#define VSIM1_SRCLK_MODE_SEL_SHIFT 4
+#define VSIM1_LP_MODE_SET_MASK 0x1
+#define VSIM1_LP_MODE_SET_SHIFT 1
+#define VSIM1_LP_SEL_MASK 0x1
+#define VSIM1_LP_SEL_SHIFT 0
+#define RG_VSIM2_EN_MASK 0x1
+#define RG_VSIM2_EN_SHIFT 15
+#define RG_VSIM2_STBTD_MASK 0x3
+#define RG_VSIM2_STBTD_SHIFT 12
+#define QI_VSIM2_MODE_MASK 0x1
+#define QI_VSIM2_MODE_SHIFT 7
+#define VSIM2_SRCLK_MODE_SEL_MASK 0x7
+#define VSIM2_SRCLK_MODE_SEL_SHIFT 4
+#define VSIM2_THER_SHDN_EN_MASK 0x1
+#define VSIM2_THER_SHDN_EN_SHIFT 2
+#define VSIM2_LP_MODE_SET_MASK 0x1
+#define VSIM2_LP_MODE_SET_SHIFT 1
+#define VSIM2_LP_SEL_MASK 0x1
+#define VSIM2_LP_SEL_SHIFT 0
+#define QI_VSIM1_OC_STATUS_MASK 0x1
+#define QI_VSIM1_OC_STATUS_SHIFT 3
+#define QI_VSIM2_OC_STATUS_MASK 0x1
+#define QI_VSIM2_OC_STATUS_SHIFT 2
+#define RG_VSIM1_CAL_MASK 0xF
+#define RG_VSIM1_CAL_SHIFT 8
+#define RG_VSIM1_VOSEL_MASK 0x7
+#define RG_VSIM1_VOSEL_SHIFT 5
+#define RG_VSIM1_STB_SEL_MASK 0x1
+#define RG_VSIM1_STB_SEL_SHIFT 4
+#define RG_VSIM1_OCFB_MASK 0x1
+#define RG_VSIM1_OCFB_SHIFT 2
+#define RG_VSIM1_NDIS_EN_MASK 0x1
+#define RG_VSIM1_NDIS_EN_SHIFT 0
+#define RG_VSIM2_CAL_MASK 0xF
+#define RG_VSIM2_CAL_SHIFT 8
+#define RG_VSIM2_VOSEL_MASK 0x7
+#define RG_VSIM2_VOSEL_SHIFT 5
+#define RG_VSIM2_STB_SEL_MASK 0x1
+#define RG_VSIM2_STB_SEL_SHIFT 4
+#define RG_VSIM2_OCFB_MASK 0x1
+#define RG_VSIM2_OCFB_SHIFT 2
+#define RG_VSIM2_NDIS_EN_MASK 0x1
+#define RG_VSIM2_NDIS_EN_SHIFT 0
+#define VSIM1_ON_CTRL_MASK 0x1
+#define VSIM1_ON_CTRL_SHIFT 9
+#define VSIM2_ON_CTRL_MASK 0x1
+#define VSIM2_ON_CTRL_SHIFT 8
+
+/* =================================================================*/
+
+#define DEW_EVENT_OUT_EN (DEW_BASE+0x0)
+#define DEW_DIO_EN (DEW_BASE+0x2)
+#define DEW_EVENT_SRC_EN (DEW_BASE+0x4)
+#define DEW_EVENT_SRC (DEW_BASE+0x6)
+#define DEW_EVENT_FLAG (DEW_BASE+0x8)
+#define DEW_READ_TEST (DEW_BASE+0xA)
+#define DEW_WRITE_TEST (DEW_BASE+0xC)
+#define DEW_CRC_EN (DEW_BASE+0xE)
+#define DEW_CRC_VAL (DEW_BASE+0x10)
+#define DEW_MON_GRP_SEL (DEW_BASE+0x12)
+#define DEW_MON_FLAG_SEL (DEW_BASE+0x14)
+#define DEW_EVENT_TEST (DEW_BASE+0x16)
+#define DEW_CIPHER_KEY_SEL (DEW_BASE+0x18)
+#define DEW_CIPHER_IV_SEL (DEW_BASE+0x1A)
+#define DEW_CIPHER_LOAD (DEW_BASE+0x1C)
+#define DEW_CIPHER_START (DEW_BASE+0x1E)
+#define DEW_CIPHER_RDY (DEW_BASE+0x20)
+#define DEW_CIPHER_MODE (DEW_BASE+0x22)
+#define DEW_CIPHER_SWRST (DEW_BASE+0x24)
+#define DEW_CIPHER_IV0 (DEW_BASE+0x26)
+#define DEW_CIPHER_IV1 (DEW_BASE+0x28)
+#define DEW_CIPHER_IV2 (DEW_BASE+0x2A)
+#define DEW_CIPHER_IV3 (DEW_BASE+0x2C)
+#define DEW_CIPHER_IV4 (DEW_BASE+0x2E)
+#define DEW_CIPHER_IV5 (DEW_BASE+0x30)
+
+#endif // #ifdef PMIC_6320_REG_API
+#endif // #ifndef __DCL_PMIC6320_HW_H_STRUCT__
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmic6320_sw.h b/mcu/driver/peripheral/inc/dcl_pmic6320_sw.h
new file mode 100644
index 0000000..8cf2e04
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmic6320_sw.h
@@ -0,0 +1,170 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6320_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6320
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DCL_PMIC6320_SW_H_STRUCT__
+#define __DCL_PMIC6320_SW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#ifdef PMIC_6320_REG_API
+
+#define PMIC6320_ECO_1_VERSION 0x01
+#define PMIC6320_ECO_2_VERSION 0x02
+
+// Combinational functions
+extern void pmic6320_customization_init(void);
+
+typedef enum
+{
+ STATUS_VSIM1_EN,
+ STATUS_VSIM2_EN,
+ OC_STATUS_VSIM1,
+ OC_STATUS_VSIM2,
+ RG_SIMLS2_SRST_CONF,
+ RG_SIMLS2_SCLK_CONF,
+ RG_SIMLS1_SRST_CONF,
+ RG_SIMLS1_SCLK_CONF,
+ RG_SIMLS_TDSEL,
+ RG_SIMAP_TDSEL,
+ RG_SIMLS_RDSEL,
+ RG_SIMAP_RDSEL,
+ RG_OCTL_SIM1_AP_SRST,
+ RG_OCTL_SIM1_AP_SCLK,
+ RG_OCTL_SIMLS1_SRST,
+ RG_OCTL_SIMLS1_SCLK,
+ RG_OCTL_SIM2_AP_SRST,
+ RG_OCTL_SIM2_AP_SCLK,
+ RG_OCTL_SIMLS2_SRST,
+ RG_OCTL_SIMLS2_SCLK,
+ RG_VIO18_MODESET,
+ RG_VPA_MODESET,
+ VPA_EN,
+ RG_VRF18_MODESET,
+ RG_VRF18_BK_LDO,
+ VRF18_EN_CTRL,
+ VRF18_EN,
+ RG_VRF18_2_MODESET,
+ RG_VRF18_2_BK_LDO,
+ VRF18_2_EN_CTRL,
+ VRF18_2_EN_SEL,
+ VRF18_2_EN,
+ VRF28_ON_CTRL,
+ RG_VRF28_EN,
+ VRF28_SRCLK_EN_SEL,
+ VRF28_ON_2_CTRL,
+ RG_VRF28_2_EN,
+ VRF28_2_SRCLK_EN_SEL,
+ RG_VSIM1_EN,
+ RG_VSIM1_STBTD,
+ QI_VSIM1_MODE,
+ VSIM1_SRCLK_MODE_SEL,
+ VSIM1_LP_MODE_SET,
+ VSIM1_LP_SEL,
+ RG_VSIM2_EN,
+ RG_VSIM2_STBTD,
+ QI_VSIM2_MODE,
+ VSIM2_SRCLK_MODE_SEL,
+ VSIM2_THER_SHDN_EN,
+ VSIM2_LP_MODE_SET,
+ VSIM2_LP_SEL,
+ QI_VSIM1_OC_STATUS,
+ QI_VSIM2_OC_STATUS,
+ RG_VSIM1_CAL,
+ RG_VSIM1_VOSEL,
+ RG_VSIM1_STB_SEL,
+ RG_VSIM1_OCFB,
+ RG_VSIM1_NDIS_EN,
+ RG_VSIM2_CAL,
+ RG_VSIM2_VOSEL,
+ RG_VSIM2_STB_SEL,
+ RG_VSIM2_OCFB,
+ RG_VSIM2_NDIS_EN,
+ VSIM1_ON_CTRL,
+ VSIM2_ON_CTRL,
+}PMIC_FLAGS_LIST_ENUM;
+
+#endif // #ifdef PMIC_6320_REG_API
+#endif // #ifndef __DCL_PMIC6320_SW_H_STRUCT__
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmic6323_hw.h b/mcu/driver/peripheral/inc/dcl_pmic6323_hw.h
new file mode 100644
index 0000000..ee5160d
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmic6323_hw.h
@@ -0,0 +1,537 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6323_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6323
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DCL_PMIC6323_HW_H_STRUCT__
+#define __DCL_PMIC6323_HW_H_STRUCT__
+
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6323_REG_API)
+
+#define PMIC_BASE (0x0000)
+#define GPIO_BASE (0xC000)
+#define MT6323_E1_CID 0x1023
+
+//register number
+#define CHR_CON0 0x0000
+#define CHR_CON1 0x0002
+#define CHR_CON2 0x0004
+#define CHR_CON3 0x0006
+#define CHR_CON4 0x0008
+#define CHR_CON5 0x000A
+#define CHR_CON6 0x000C
+#define CHR_CON7 0x000E
+#define CHR_CON8 0x0010
+#define CHR_CON9 0x0012
+#define CHR_CON10 0x0014
+#define CHR_CON11 0x0016
+#define CHR_CON12 0x0018
+#define CHR_CON13 0x001A
+#define CHR_CON14 0x001C
+#define CHR_CON15 0x001E
+#define CHR_CON16 0x0020
+#define CHR_CON17 0x0022
+#define CHR_CON18 0x0024
+#define CHR_CON19 0x0026
+#define CHR_CON20 0x0028
+#define CHR_CON21 0x002A
+#define CHR_CON22 0x002C
+#define CHR_CON23 0x002E
+#define CHR_CON24 0x0030
+#define CHR_CON25 0x0032
+#define CHR_CON26 0x0034
+#define CHR_CON27 0x0036
+#define CHR_CON28 0x0038
+#define CHR_CON29 0x003A
+#define STRUP_CON0 0x003C
+#define STRUP_CON2 0x003E
+#define STRUP_CON3 0x0040
+#define STRUP_CON4 0x0042
+#define STRUP_CON5 0x0044
+#define STRUP_CON6 0x0046
+#define STRUP_CON7 0x0048
+#define STRUP_CON8 0x004A
+#define STRUP_CON9 0x004C
+#define STRUP_CON10 0x004E
+#define STRUP_CON11 0x0050
+#define SPK_CON0 0x0052
+#define SPK_CON1 0x0054
+#define SPK_CON2 0x0056
+#define SPK_CON6 0x005E
+#define SPK_CON7 0x0060
+#define SPK_CON8 0x0062
+#define SPK_CON9 0x0064
+#define SPK_CON10 0x0066
+#define SPK_CON11 0x0068
+#define SPK_CON12 0x006A
+#define CID 0x0100
+#define TOP_CKPDN0 0x0102
+#define TOP_CKPDN1 0x0108
+#define TOP_CKPDN1_SET 0x010A
+#define TOP_CKPDN1_CLR 0x010C
+#define TOP_CKPDN2 0x010E
+#define TOP_RST_CON 0x0114
+#define TOP_RST_MISC 0x011A
+#define TOP_CKCON0 0x0120
+#define TOP_CKCON1 0x0126
+#define TOP_CKCON1_CLR 0x012A
+#define TOP_CKTST0 0x012C
+#define TOP_CKTST1 0x012E
+#define TOP_CKTST2 0x0130
+#define TEST_OUT 0x0132
+#define TEST_CON0 0x0134
+#define TEST_CON1 0x0136
+#define EN_STATUS0 0x0138
+#define EN_STATUS1 0x013A
+#define OCSTATUS0 0x013C
+#define OCSTATUS1 0x013E
+#define PGSTATUS 0x0140
+#define CHRSTATUS 0x0142
+#define TDSEL_CON 0x0144
+#define RDSEL_CON 0x0146
+#define SMT_CON0 0x0148
+#define SMT_CON1 0x014A
+#define SMT_CON2 0x014C
+#define SMT_CON3 0x014E
+#define SMT_CON4 0x0150
+#define DRV_CON0 0x0152
+#define DRV_CON1 0x0154
+#define DRV_CON2 0x0156
+#define DRV_CON3 0x0158
+#define DRV_CON4 0x015A
+#define SIMLS1_CON 0x015C
+#define SIMLS2_CON 0x015E
+#define INT_CON0 0x0160
+#define INT_CON1 0x0166
+#define INT_MISC_CON 0x016C
+#define INT_STATUS0 0x0172
+#define INT_STATUS1 0x0174
+#define OC_GEAR_0 0x0176
+#define OC_GEAR_1 0x0178
+#define OC_GEAR_2 0x017A
+#define OC_CTL_VPROC 0x017C
+#define OC_CTL_VSYS 0x017E
+#define OC_CTL_VPA 0x0180
+#define FQMTR_CON0 0x0182
+#define FQMTR_CON1 0x0184
+#define FQMTR_CON2 0x0186
+#define RG_SPI_CON 0x0188
+#define DEW_DIO_EN 0x018A
+#define DEW_READ_TEST 0x018C
+#define DEW_WRITE_TEST 0x018E
+#define DEW_CRC_SWRST 0x0190
+#define DEW_CRC_EN 0x0192
+#define DEW_CRC_VAL 0x0194
+#define DEW_DBG_MON_SEL 0x0196
+#define DEW_CIPHER_KEY_SEL 0x0198
+#define DEW_CIPHER_IV_SEL 0x019A
+#define DEW_CIPHER_EN 0x019C
+#define DEW_CIPHER_RDY 0x019E
+#define DEW_CIPHER_MODE 0x01A0
+#define DEW_CIPHER_SWRST 0x01A2
+#define DEW_RDDMY_NO 0x01A4
+#define DEW_RDATA_DLY_SEL 0x01A6
+#define BUCK_CON0 0x0200
+#define BUCK_CON1 0x0202
+#define BUCK_CON2 0x0204
+#define BUCK_CON3 0x0206
+#define BUCK_CON4 0x0208
+#define BUCK_CON5 0x020A
+#define VPROC_CON0 0x020C
+#define VPROC_CON1 0x020E
+#define VPROC_CON2 0x0210
+#define VPROC_CON3 0x0212
+#define VPROC_CON4 0x0214
+#define VPROC_CON5 0x0216
+#define VPROC_CON7 0x021A
+#define VPROC_CON8 0x021C
+#define VPROC_CON9 0x021E
+#define VPROC_CON10 0x0220
+#define VPROC_CON11 0x0222
+#define VPROC_CON12 0x0224
+#define VPROC_CON13 0x0226
+#define VPROC_CON14 0x0228
+#define VPROC_CON15 0x022A
+#define VPROC_CON18 0x0230
+#define VSYS_CON0 0x0232
+#define VSYS_CON1 0x0234
+#define VSYS_CON2 0x0236
+#define VSYS_CON3 0x0238
+#define VSYS_CON4 0x023A
+#define VSYS_CON5 0x023C
+#define VSYS_CON7 0x0240
+#define VSYS_CON8 0x0242
+#define VSYS_CON9 0x0244
+#define VSYS_CON10 0x0246
+#define VSYS_CON11 0x0248
+#define VSYS_CON12 0x024A
+#define VSYS_CON13 0x024C
+#define VSYS_CON14 0x024E
+#define VSYS_CON15 0x0250
+#define VSYS_CON18 0x0256
+#define VPA_CON0 0x0300
+#define VPA_CON1 0x0302
+#define VPA_CON2 0x0304
+#define VPA_CON3 0x0306
+#define VPA_CON4 0x0308
+#define VPA_CON5 0x030A
+#define VPA_CON7 0x030E
+#define VPA_CON8 0x0310
+#define VPA_CON9 0x0312
+#define VPA_CON10 0x0314
+#define VPA_CON11 0x0316
+#define VPA_CON12 0x0318
+#define VPA_CON14 0x031C
+#define VPA_CON16 0x0320
+#define VPA_CON17 0x0322
+#define VPA_CON18 0x0324
+#define VPA_CON19 0x0326
+#define VPA_CON20 0x0328
+#define BUCK_K_CON0 0x032A
+#define BUCK_K_CON1 0x032C
+#define BUCK_K_CON2 0x032E
+#define ISINK0_CON0 0x0330
+#define ISINK0_CON1 0x0332
+#define ISINK0_CON2 0x0334
+#define ISINK0_CON3 0x0336
+#define ISINK1_CON0 0x0338
+#define ISINK1_CON1 0x033A
+#define ISINK1_CON2 0x033C
+#define ISINK1_CON3 0x033E
+#define ISINK2_CON0 0x0340
+#define ISINK2_CON1 0x0342
+#define ISINK2_CON2 0x0344
+#define ISINK2_CON3 0x0346
+#define ISINK3_CON0 0x0348
+#define ISINK3_CON1 0x034A
+#define ISINK3_CON2 0x034C
+#define ISINK3_CON3 0x034E
+#define ISINK_ANA0 0x0350
+#define ISINK_ANA1 0x0352
+#define ISINK_PHASE_DLY 0x0354
+#define ISINK_EN_CTRL 0x0356
+#define ANALDO_CON0 0x0400
+#define ANALDO_CON1 0x0402
+#define ANALDO_CON2 0x0404
+#define ANALDO_CON3 0x0406
+#define ANALDO_CON4 0x0408
+#define ANALDO_CON5 0x040A
+#define ANALDO_CON6 0x040C
+#define ANALDO_CON7 0x040E
+#define ANALDO_CON8 0x0410
+#define ANALDO_CON10 0x0412
+#define ANALDO_CON15 0x0414
+#define ANALDO_CON16 0x0416
+#define ANALDO_CON17 0x0418
+#define ANALDO_CON18 0x041A
+#define ANALDO_CON19 0x041C
+#define ANALDO_CON20 0x041E
+#define ANALDO_CON21 0x0420
+#define DIGLDO_CON0 0x0500
+#define DIGLDO_CON2 0x0502
+#define DIGLDO_CON3 0x0504
+#define DIGLDO_CON5 0x0506
+#define DIGLDO_CON6 0x0508
+#define DIGLDO_CON7 0x050A
+#define DIGLDO_CON8 0x050C
+#define DIGLDO_CON9 0x050E
+#define DIGLDO_CON10 0x0510
+#define DIGLDO_CON11 0x0512
+#define DIGLDO_CON12 0x0514
+#define DIGLDO_CON13 0x0516
+#define DIGLDO_CON14 0x0518
+#define DIGLDO_CON15 0x051A
+#define DIGLDO_CON16 0x051C
+#define DIGLDO_CON17 0x051E
+#define DIGLDO_CON18 0x0520
+#define DIGLDO_CON19 0x0522
+#define DIGLDO_CON20 0x0524
+#define DIGLDO_CON21 0x0526
+#define DIGLDO_CON23 0x0528
+#define DIGLDO_CON24 0x052A
+#define DIGLDO_CON26 0x052C
+#define DIGLDO_CON27 0x052E
+#define DIGLDO_CON28 0x0530
+#define DIGLDO_CON29 0x0532
+#define DIGLDO_CON30 0x0534
+#define DIGLDO_CON31 0x0536
+#define DIGLDO_CON32 0x0538
+#define DIGLDO_CON33 0x053A
+#define DIGLDO_CON34 0x053C
+#define DIGLDO_CON35 0x053E
+#define DIGLDO_CON36 0x0540
+#define DIGLDO_CON39 0x0542
+#define DIGLDO_CON40 0x0544
+#define DIGLDO_CON41 0x0546
+#define DIGLDO_CON42 0x0548
+#define DIGLDO_CON43 0x054A
+#define DIGLDO_CON44 0x054C
+#define DIGLDO_CON45 0x054E
+#define DIGLDO_CON46 0x0550
+#define DIGLDO_CON47 0x0552
+#define DIGLDO_CON48 0x0554
+#define DIGLDO_CON49 0x0556
+#define DIGLDO_CON50 0x0558
+#define DIGLDO_CON51 0x055A
+#define DIGLDO_CON52 0x055C
+#define DIGLDO_CON53 0x055E
+#define DIGLDO_CON54 0x0560
+#define EFUSE_CON0 0x0600
+#define EFUSE_CON1 0x0602
+#define EFUSE_CON2 0x0604
+#define EFUSE_CON3 0x0606
+#define EFUSE_CON4 0x0608
+#define EFUSE_CON5 0x060A
+#define EFUSE_CON6 0x060C
+#define EFUSE_VAL_0_15 0x060E
+#define EFUSE_VAL_16_31 0x0610
+#define EFUSE_VAL_32_47 0x0612
+#define EFUSE_VAL_48_63 0x0614
+#define EFUSE_VAL_64_79 0x0616
+#define EFUSE_VAL_80_95 0x0618
+#define EFUSE_VAL_96_111 0x061A
+#define EFUSE_VAL_112_127 0x061C
+#define EFUSE_VAL_128_143 0x061E
+#define EFUSE_VAL_144_159 0x0620
+#define EFUSE_VAL_160_175 0x0622
+#define EFUSE_VAL_176_191 0x0624
+#define EFUSE_DOUT_0_15 0x0626
+#define EFUSE_DOUT_16_31 0x0628
+#define EFUSE_DOUT_32_47 0x062A
+#define EFUSE_DOUT_48_63 0x062C
+#define EFUSE_DOUT_64_79 0x062E
+#define EFUSE_DOUT_80_95 0x0630
+#define EFUSE_DOUT_96_111 0x0632
+#define EFUSE_DOUT_112_127 0x0634
+#define EFUSE_DOUT_128_143 0x0636
+#define EFUSE_DOUT_144_159 0x0638
+#define EFUSE_DOUT_160_175 0x063A
+#define EFUSE_DOUT_176_191 0x063C
+#define EFUSE_CON7 0x063E
+#define EFUSE_CON8 0x0640
+#define EFUSE_CON9 0x0642
+#define RTC_MIX_CON0 0x0644
+#define RTC_MIX_CON1 0x0646
+#define AUDTOP_CON0 0x0700
+#define AUDTOP_CON1 0x0702
+#define AUDTOP_CON2 0x0704
+#define AUDTOP_CON3 0x0706
+#define AUDTOP_CON4 0x0708
+#define AUDTOP_CON5 0x070A
+#define AUDTOP_CON6 0x070C
+#define AUDTOP_CON7 0x070E
+#define AUDTOP_CON8 0x0710
+#define AUDTOP_CON9 0x0712
+#define AUXADC_ADC0 0x0714
+#define AUXADC_ADC1 0x0716
+#define AUXADC_ADC2 0x0718
+#define AUXADC_ADC3 0x071A
+#define AUXADC_ADC4 0x071C
+#define AUXADC_ADC5 0x071E
+#define AUXADC_ADC6 0x0720
+#define AUXADC_ADC7 0x0722
+#define AUXADC_ADC8 0x0724
+#define AUXADC_ADC9 0x0726
+#define AUXADC_ADC10 0x0728
+#define AUXADC_ADC11 0x072A
+#define AUXADC_ADC12 0x072C
+#define AUXADC_ADC13 0x072E
+#define AUXADC_ADC14 0x0730
+#define AUXADC_ADC15 0x0732
+#define AUXADC_ADC16 0x0734
+#define AUXADC_ADC17 0x0736
+#define AUXADC_ADC18 0x0738
+#define AUXADC_ADC19 0x073A
+#define AUXADC_ADC20 0x073C
+#define AUXADC_RSV1 0x073E
+#define AUXADC_RSV2 0x0740
+#define AUXADC_CON0 0x0742
+#define AUXADC_CON1 0x0744
+#define AUXADC_CON2 0x0746
+#define AUXADC_CON3 0x0748
+#define AUXADC_CON4 0x074A
+#define AUXADC_CON5 0x074C
+#define AUXADC_CON6 0x074E
+#define AUXADC_CON7 0x0750
+#define AUXADC_CON8 0x0752
+#define AUXADC_CON9 0x0754
+#define AUXADC_CON10 0x0756
+#define AUXADC_CON11 0x0758
+#define AUXADC_CON12 0x075A
+#define AUXADC_CON13 0x075C
+#define AUXADC_CON14 0x075E
+#define AUXADC_CON15 0x0760
+#define AUXADC_CON16 0x0762
+#define AUXADC_CON17 0x0764
+#define AUXADC_CON18 0x0766
+#define AUXADC_CON19 0x0768
+#define AUXADC_CON20 0x076A
+#define AUXADC_CON21 0x076C
+#define AUXADC_CON22 0x076E
+#define AUXADC_CON23 0x0770
+#define AUXADC_CON24 0x0772
+#define AUXADC_CON25 0x0774
+#define AUXADC_CON26 0x0776
+#define AUXADC_CON27 0x0778
+#define ACCDET_CON0 0x077A
+#define ACCDET_CON1 0x077C
+#define ACCDET_CON2 0x077E
+#define ACCDET_CON3 0x0780
+#define ACCDET_CON4 0x0782
+#define ACCDET_CON5 0x0784
+#define ACCDET_CON6 0x0786
+#define ACCDET_CON7 0x0788
+#define ACCDET_CON8 0x078A
+#define ACCDET_CON9 0x078C
+#define ACCDET_CON10 0x078E
+#define ACCDET_CON11 0x0790
+#define ACCDET_CON12 0x0792
+#define ACCDET_CON13 0x0794
+#define ACCDET_CON14 0x0796
+#define ACCDET_CON15 0x0798
+#define ACCDET_CON16 0x079A
+
+//mask is HEX
+//shift is Integer
+#define RG_CLKSQ_EN_AUX_MD_MASK 0x1
+#define RG_CLKSQ_EN_AUX_MD_SHIFT 14
+#define RG_VPA_MODESET_MASK 0x1
+#define RG_VPA_MODESET_SHIFT 8
+#define VPA_EN_MASK 0x1
+#define VPA_EN_SHIFT 0
+#define RG_STB_SIM1_SIO_MASK 0x1
+#define RG_STB_SIM1_SIO_SHIFT 0
+#define RG_VSIM1_EN_MASK 0x1
+#define RG_VSIM1_EN_SHIFT 15
+#define VSIM1_LP_MODE_SET_MASK 0x1
+#define VSIM1_LP_MODE_SET_SHIFT 1
+#define VSIM1_LP_SEL_MASK 0x1
+#define VSIM1_LP_SEL_SHIFT 0
+#define RG_VSIM2_EN_MASK 0x1
+#define RG_VSIM2_EN_SHIFT 15
+#define VSIM2_LP_MODE_SET_MASK 0x1
+#define VSIM2_LP_MODE_SET_SHIFT 1
+#define VSIM2_LP_SEL_MASK 0x1
+#define VSIM2_LP_SEL_SHIFT 0
+#define RG_STB_SIM2_SIO_MASK 0x1
+#define RG_STB_SIM2_SIO_SHIFT 0
+#define RG_VSIM1_VOSEL_MASK 0x1
+#define RG_VSIM1_VOSEL_SHIFT 5
+#define RG_VSIM2_VOSEL_MASK 0x1
+#define RG_VSIM2_VOSEL_SHIFT 5
+#define RG_VRF18_EN_MASK 0x1
+#define RG_VRF18_EN_SHIFT 15
+#define VRF18_LP_MODE_SET_MASK 0x1
+#define VRF18_LP_MODE_SET_SHIFT 1
+#define VRF18_LP_SEL_MASK 0x1
+#define VRF18_LP_SEL_SHIFT 0
+#define VRF18_ON_CTRL_MASK 0x1
+#define VRF18_ON_CTRL_SHIFT 1
+#define RG_ADC_OUT_MD_MASK 0xFFFF
+#define RG_ADC_OUT_MD_SHIFT 0
+#define RG_ADC_RDY_MD_MASK 0x1
+#define RG_ADC_RDY_MD_SHIFT 15
+#define RG_MD_RQST_MASK 0x1
+#define RG_MD_RQST_SHIFT 15
+
+// ====================================================================== //
+#define GPIO_DOUT1_SET 0x0082
+#define GPIO_DOUT1_CLR 0x0084
+#define GPIO_DOUT2_SET 0x008A
+#define GPIO_DOUT2_CLR 0x008C
+
+#define GPIO15_DOUT_SET_MASK 0x1
+#define GPIO15_DOUT_SET_SHIFT 15
+#define GPIO15_DOUT_CLR_MASK 0x1
+#define GPIO15_DOUT_CLR_SHIFT 15
+#define GPIO17_DOUT_SET_MASK 0x1
+#define GPIO17_DOUT_SET_SHIFT 1
+#define GPIO17_DOUT_CLR_MASK 0x1
+#define GPIO17_DOUT_CLR_SHIFT 1
+
+#endif // #ifdef PMIC_6323_REG_API
+#endif // #ifndef __DCL_PMIC6323_HW_H_STRUCT__
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmic6323_sw.h b/mcu/driver/peripheral/inc/dcl_pmic6323_sw.h
new file mode 100644
index 0000000..ed9f6bc
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmic6323_sw.h
@@ -0,0 +1,120 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6323_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6323
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DCL_PMIC6323_SW_H_STRUCT__
+#define __DCL_PMIC6323_SW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#ifdef PMIC_6323_REG_API
+
+#define PMIC6323_ECO_1_VERSION 0x01
+#define PMIC6323_ECO_2_VERSION 0x02
+
+// Combinational functions
+extern void pmic6323_customization_init(void);
+
+typedef enum
+{
+ RG_VPA_MODESET,
+ VPA_EN,
+ RG_STB_SIM1_SIO,
+ RG_VSIM1_EN,
+ VSIM1_LP_MODE_SET,
+ VSIM1_LP_SEL,
+ RG_VSIM2_EN,
+ VSIM2_LP_MODE_SET,
+ VSIM2_LP_SEL,
+ RG_STB_SIM2_SIO,
+ RG_VSIM1_VOSEL,
+ RG_VSIM2_VOSEL,
+ RG_VRF18_EN,
+ VRF18_LP_MODE_SET,
+ VRF18_LP_SEL,
+ VRF18_ON_CTRL,
+ RG_ADC_OUT_MD,
+ RG_ADC_RDY_MD,
+ RG_MD_RQST,
+ GPIO15_DOUT_SET,
+ GPIO15_DOUT_CLR,
+ GPIO17_DOUT_SET,
+ GPIO17_DOUT_CLR,
+}PMIC_FLAGS_LIST_ENUM;
+
+#endif // #ifdef PMIC_6323_REG_API
+#endif // #ifndef __DCL_PMIC6323_SW_H_STRUCT__
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmic6325_hw.h b/mcu/driver/peripheral/inc/dcl_pmic6325_hw.h
new file mode 100644
index 0000000..1d050a9
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmic6325_hw.h
@@ -0,0 +1,6822 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6325_hw.h
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6325
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DCL_PMIC6325_HW_H_STRUCT__
+#define __DCL_PMIC6325_HW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#ifdef PMIC_6325_REG_API
+
+#define MT6325_PMIC_REG_BASE (0x0000)
+
+#define MT6325_STRUP_CON0 (MT6325_PMIC_REG_BASE + 0x0000)
+#define MT6325_STRUP_CON2 (MT6325_PMIC_REG_BASE + 0x0002)
+#define MT6325_STRUP_CON3 (MT6325_PMIC_REG_BASE + 0x0004)
+#define MT6325_STRUP_CON4 (MT6325_PMIC_REG_BASE + 0x0006)
+#define MT6325_STRUP_CON5 (MT6325_PMIC_REG_BASE + 0x0008)
+#define MT6325_STRUP_CON6 (MT6325_PMIC_REG_BASE + 0x000A)
+#define MT6325_STRUP_CON7 (MT6325_PMIC_REG_BASE + 0x000C)
+#define MT6325_STRUP_CON8 (MT6325_PMIC_REG_BASE + 0x000E)
+#define MT6325_STRUP_CON9 (MT6325_PMIC_REG_BASE + 0x0010)
+#define MT6325_STRUP_CON10 (MT6325_PMIC_REG_BASE + 0x0012)
+#define MT6325_STRUP_CON11 (MT6325_PMIC_REG_BASE + 0x0014)
+#define MT6325_STRUP_CON12 (MT6325_PMIC_REG_BASE + 0x0016)
+#define MT6325_STRUP_CON13 (MT6325_PMIC_REG_BASE + 0x0018)
+#define MT6325_STRUP_CON14 (MT6325_PMIC_REG_BASE + 0x001A)
+#define MT6325_STRUP_CON15 (MT6325_PMIC_REG_BASE + 0x001C)
+#define MT6325_STRUP_CON16 (MT6325_PMIC_REG_BASE + 0x001E)
+#define MT6325_STRUP_CON17 (MT6325_PMIC_REG_BASE + 0x0020)
+#define MT6325_STRUP_CON18 (MT6325_PMIC_REG_BASE + 0x0022)
+#define MT6325_STRUP_CON19 (MT6325_PMIC_REG_BASE + 0x0024)
+#define MT6325_STRUP_CON20 (MT6325_PMIC_REG_BASE + 0x0026)
+#define MT6325_STRUP_CON21 (MT6325_PMIC_REG_BASE + 0x0028)
+#define MT6325_STRUP_CON22 (MT6325_PMIC_REG_BASE + 0x002A)
+#define MT6325_STRUP_CON23 (MT6325_PMIC_REG_BASE + 0x002C)
+#define MT6325_STRUP_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x002E)
+#define MT6325_HWCID (MT6325_PMIC_REG_BASE + 0x0200)
+#define MT6325_SWCID (MT6325_PMIC_REG_BASE + 0x0202)
+#define MT6325_TOP_CON (MT6325_PMIC_REG_BASE + 0x0204)
+#define MT6325_TEST_OUT (MT6325_PMIC_REG_BASE + 0x0206)
+#define MT6325_TEST_CON0 (MT6325_PMIC_REG_BASE + 0x0208)
+#define MT6325_TEST_CON1 (MT6325_PMIC_REG_BASE + 0x020A)
+#define MT6325_TESTMODE_SW (MT6325_PMIC_REG_BASE + 0x020C)
+#define MT6325_EN_STATUS0 (MT6325_PMIC_REG_BASE + 0x020E)
+#define MT6325_EN_STATUS1 (MT6325_PMIC_REG_BASE + 0x0210)
+#define MT6325_EN_STATUS2 (MT6325_PMIC_REG_BASE + 0x0212)
+#define MT6325_OCSTATUS0 (MT6325_PMIC_REG_BASE + 0x0214)
+#define MT6325_OCSTATUS1 (MT6325_PMIC_REG_BASE + 0x0216)
+#define MT6325_OCSTATUS2 (MT6325_PMIC_REG_BASE + 0x0218)
+#define MT6325_PGSTATUS (MT6325_PMIC_REG_BASE + 0x021A)
+#define MT6325_TOPSTATUS (MT6325_PMIC_REG_BASE + 0x021C)
+#define MT6325_TDSEL_CON (MT6325_PMIC_REG_BASE + 0x021E)
+#define MT6325_RDSEL_CON (MT6325_PMIC_REG_BASE + 0x0220)
+#define MT6325_SMT_CON0 (MT6325_PMIC_REG_BASE + 0x0222)
+#define MT6325_SMT_CON1 (MT6325_PMIC_REG_BASE + 0x0224)
+#define MT6325_SMT_CON2 (MT6325_PMIC_REG_BASE + 0x0226)
+#define MT6325_DRV_CON0 (MT6325_PMIC_REG_BASE + 0x0228)
+#define MT6325_DRV_CON1 (MT6325_PMIC_REG_BASE + 0x022A)
+#define MT6325_DRV_CON2 (MT6325_PMIC_REG_BASE + 0x022C)
+#define MT6325_DRV_CON3 (MT6325_PMIC_REG_BASE + 0x022E)
+#define MT6325_TOP_STATUS (MT6325_PMIC_REG_BASE + 0x0230)
+#define MT6325_TOP_STATUS_SET (MT6325_PMIC_REG_BASE + 0x0232)
+#define MT6325_TOP_STATUS_CLR (MT6325_PMIC_REG_BASE + 0x0234)
+#define MT6325_RGS_ANA_MON (MT6325_PMIC_REG_BASE + 0x0236)
+#define MT6325_TOP_CKPDN_CON0 (MT6325_PMIC_REG_BASE + 0x0238)
+#define MT6325_TOP_CKPDN_CON0_SET (MT6325_PMIC_REG_BASE + 0x023A)
+#define MT6325_TOP_CKPDN_CON0_CLR (MT6325_PMIC_REG_BASE + 0x023C)
+#define MT6325_TOP_CKPDN_CON1 (MT6325_PMIC_REG_BASE + 0x023E)
+#define MT6325_TOP_CKPDN_CON1_SET (MT6325_PMIC_REG_BASE + 0x0240)
+#define MT6325_TOP_CKPDN_CON1_CLR (MT6325_PMIC_REG_BASE + 0x0242)
+#define MT6325_TOP_CKPDN_CON2 (MT6325_PMIC_REG_BASE + 0x0244)
+#define MT6325_TOP_CKPDN_CON2_SET (MT6325_PMIC_REG_BASE + 0x0246)
+#define MT6325_TOP_CKPDN_CON2_CLR (MT6325_PMIC_REG_BASE + 0x0248)
+#define MT6325_TOP_CKPDN_CON3 (MT6325_PMIC_REG_BASE + 0x024A)
+#define MT6325_TOP_CKPDN_CON3_SET (MT6325_PMIC_REG_BASE + 0x024C)
+#define MT6325_TOP_CKPDN_CON3_CLR (MT6325_PMIC_REG_BASE + 0x024E)
+#define MT6325_TOP_CKSEL_CON0 (MT6325_PMIC_REG_BASE + 0x0250)
+#define MT6325_TOP_CKSEL_CON0_SET (MT6325_PMIC_REG_BASE + 0x0252)
+#define MT6325_TOP_CKSEL_CON0_CLR (MT6325_PMIC_REG_BASE + 0x0254)
+#define MT6325_TOP_CKSEL_CON1 (MT6325_PMIC_REG_BASE + 0x0256)
+#define MT6325_TOP_CKSEL_CON1_SET (MT6325_PMIC_REG_BASE + 0x0258)
+#define MT6325_TOP_CKSEL_CON1_CLR (MT6325_PMIC_REG_BASE + 0x025A)
+#define MT6325_TOP_CKSEL_CON2 (MT6325_PMIC_REG_BASE + 0x025C)
+#define MT6325_TOP_CKSEL_CON2_SET (MT6325_PMIC_REG_BASE + 0x025E)
+#define MT6325_TOP_CKSEL_CON2_CLR (MT6325_PMIC_REG_BASE + 0x0260)
+#define MT6325_TOP_CKDIVSEL_CON (MT6325_PMIC_REG_BASE + 0x0262)
+#define MT6325_TOP_CKDIVSEL_CON_SET (MT6325_PMIC_REG_BASE + 0x0264)
+#define MT6325_TOP_CKDIVSEL_CON_CLR (MT6325_PMIC_REG_BASE + 0x0266)
+#define MT6325_TOP_CKHWEN_CON (MT6325_PMIC_REG_BASE + 0x0268)
+#define MT6325_TOP_CKHWEN_CON_SET (MT6325_PMIC_REG_BASE + 0x026A)
+#define MT6325_TOP_CKHWEN_CON_CLR (MT6325_PMIC_REG_BASE + 0x026C)
+#define MT6325_TOP_CKTST_CON0 (MT6325_PMIC_REG_BASE + 0x026E)
+#define MT6325_TOP_CKTST_CON1 (MT6325_PMIC_REG_BASE + 0x0270)
+#define MT6325_TOP_CKTST_CON2 (MT6325_PMIC_REG_BASE + 0x0272)
+#define MT6325_TOP_CLKSQ (MT6325_PMIC_REG_BASE + 0x0274)
+#define MT6325_TOP_CLKSQ_SET (MT6325_PMIC_REG_BASE + 0x0276)
+#define MT6325_TOP_CLKSQ_CLR (MT6325_PMIC_REG_BASE + 0x0278)
+#define MT6325_TOP_CLKSQ_RTC (MT6325_PMIC_REG_BASE + 0x027A)
+#define MT6325_TOP_CLKSQ_RTC_SET (MT6325_PMIC_REG_BASE + 0x027C)
+#define MT6325_TOP_CLKSQ_RTC_CLR (MT6325_PMIC_REG_BASE + 0x027E)
+#define MT6325_TOP_CLK_TRIM (MT6325_PMIC_REG_BASE + 0x0280)
+#define MT6325_TOP_RST_CON0 (MT6325_PMIC_REG_BASE + 0x0282)
+#define MT6325_TOP_RST_CON0_SET (MT6325_PMIC_REG_BASE + 0x0284)
+#define MT6325_TOP_RST_CON0_CLR (MT6325_PMIC_REG_BASE + 0x0286)
+#define MT6325_TOP_RST_CON1 (MT6325_PMIC_REG_BASE + 0x0288)
+#define MT6325_TOP_RST_MISC (MT6325_PMIC_REG_BASE + 0x028A)
+#define MT6325_TOP_RST_MISC_SET (MT6325_PMIC_REG_BASE + 0x028C)
+#define MT6325_TOP_RST_MISC_CLR (MT6325_PMIC_REG_BASE + 0x028E)
+#define MT6325_TOP_RST_STATUS (MT6325_PMIC_REG_BASE + 0x0290)
+#define MT6325_TOP_RST_STATUS_SET (MT6325_PMIC_REG_BASE + 0x0292)
+#define MT6325_TOP_RST_STATUS_CLR (MT6325_PMIC_REG_BASE + 0x0294)
+#define MT6325_INT_CON0 (MT6325_PMIC_REG_BASE + 0x0296)
+#define MT6325_INT_CON0_SET (MT6325_PMIC_REG_BASE + 0x0298)
+#define MT6325_INT_CON0_CLR (MT6325_PMIC_REG_BASE + 0x029A)
+#define MT6325_INT_CON1 (MT6325_PMIC_REG_BASE + 0x029C)
+#define MT6325_INT_CON1_SET (MT6325_PMIC_REG_BASE + 0x029E)
+#define MT6325_INT_CON1_CLR (MT6325_PMIC_REG_BASE + 0x02A0)
+#define MT6325_INT_CON2 (MT6325_PMIC_REG_BASE + 0x02A2)
+#define MT6325_INT_CON2_SET (MT6325_PMIC_REG_BASE + 0x02A4)
+#define MT6325_INT_CON2_CLR (MT6325_PMIC_REG_BASE + 0x02A6)
+#define MT6325_INT_MISC_CON (MT6325_PMIC_REG_BASE + 0x02A8)
+#define MT6325_INT_MISC_CON_SET (MT6325_PMIC_REG_BASE + 0x02AA)
+#define MT6325_INT_MISC_CON_CLR (MT6325_PMIC_REG_BASE + 0x02AC)
+#define MT6325_INT_STATUS0 (MT6325_PMIC_REG_BASE + 0x02AE)
+#define MT6325_INT_STATUS1 (MT6325_PMIC_REG_BASE + 0x02B0)
+#define MT6325_INT_STATUS2 (MT6325_PMIC_REG_BASE + 0x02B2)
+#define MT6325_OC_GEAR_0 (MT6325_PMIC_REG_BASE + 0x02B4)
+#define MT6325_FQMTR_CON0 (MT6325_PMIC_REG_BASE + 0x02B6)
+#define MT6325_FQMTR_CON1 (MT6325_PMIC_REG_BASE + 0x02B8)
+#define MT6325_FQMTR_CON2 (MT6325_PMIC_REG_BASE + 0x02BA)
+#define MT6325_RG_SPI_CON (MT6325_PMIC_REG_BASE + 0x02BC)
+#define MT6325_DEW_DIO_EN (MT6325_PMIC_REG_BASE + 0x02BE)
+#define MT6325_DEW_READ_TEST (MT6325_PMIC_REG_BASE + 0x02C0)
+#define MT6325_DEW_WRITE_TEST (MT6325_PMIC_REG_BASE + 0x02C2)
+#define MT6325_DEW_CRC_SWRST (MT6325_PMIC_REG_BASE + 0x02C4)
+#define MT6325_DEW_CRC_EN (MT6325_PMIC_REG_BASE + 0x02C6)
+#define MT6325_DEW_CRC_VAL (MT6325_PMIC_REG_BASE + 0x02C8)
+#define MT6325_DEW_DBG_MON_SEL (MT6325_PMIC_REG_BASE + 0x02CA)
+#define MT6325_DEW_CIPHER_KEY_SEL (MT6325_PMIC_REG_BASE + 0x02CC)
+#define MT6325_DEW_CIPHER_IV_SEL (MT6325_PMIC_REG_BASE + 0x02CE)
+#define MT6325_DEW_CIPHER_EN (MT6325_PMIC_REG_BASE + 0x02D0)
+#define MT6325_DEW_CIPHER_RDY (MT6325_PMIC_REG_BASE + 0x02D2)
+#define MT6325_DEW_CIPHER_MODE (MT6325_PMIC_REG_BASE + 0x02D4)
+#define MT6325_DEW_CIPHER_SWRST (MT6325_PMIC_REG_BASE + 0x02D6)
+#define MT6325_DEW_RDDMY_NO (MT6325_PMIC_REG_BASE + 0x02D8)
+#define MT6325_INT_TYPE_CON0 (MT6325_PMIC_REG_BASE + 0x02DA)
+#define MT6325_INT_TYPE_CON0_SET (MT6325_PMIC_REG_BASE + 0x02DC)
+#define MT6325_INT_TYPE_CON0_CLR (MT6325_PMIC_REG_BASE + 0x02DE)
+#define MT6325_INT_TYPE_CON1 (MT6325_PMIC_REG_BASE + 0x02E0)
+#define MT6325_INT_TYPE_CON1_SET (MT6325_PMIC_REG_BASE + 0x02E2)
+#define MT6325_INT_TYPE_CON1_CLR (MT6325_PMIC_REG_BASE + 0x02E4)
+#define MT6325_INT_TYPE_CON2 (MT6325_PMIC_REG_BASE + 0x02E6)
+#define MT6325_INT_TYPE_CON2_SET (MT6325_PMIC_REG_BASE + 0x02E8)
+#define MT6325_INT_TYPE_CON2_CLR (MT6325_PMIC_REG_BASE + 0x02EA)
+#define MT6325_INT_STA (MT6325_PMIC_REG_BASE + 0x02EC)
+#define MT6325_BUCK_ALL_CON0 (MT6325_PMIC_REG_BASE + 0x0400)
+#define MT6325_BUCK_ALL_CON1 (MT6325_PMIC_REG_BASE + 0x0402)
+#define MT6325_BUCK_ALL_CON2 (MT6325_PMIC_REG_BASE + 0x0404)
+#define MT6325_BUCK_ALL_CON3 (MT6325_PMIC_REG_BASE + 0x0406)
+#define MT6325_BUCK_ALL_CON4 (MT6325_PMIC_REG_BASE + 0x0408)
+#define MT6325_BUCK_ALL_CON5 (MT6325_PMIC_REG_BASE + 0x040A)
+#define MT6325_BUCK_ALL_CON6 (MT6325_PMIC_REG_BASE + 0x040C)
+#define MT6325_BUCK_ALL_CON7 (MT6325_PMIC_REG_BASE + 0x040E)
+#define MT6325_BUCK_ALL_CON8 (MT6325_PMIC_REG_BASE + 0x0410)
+#define MT6325_BUCK_ALL_CON9 (MT6325_PMIC_REG_BASE + 0x0412)
+#define MT6325_BUCK_ALL_CON10 (MT6325_PMIC_REG_BASE + 0x0414)
+#define MT6325_BUCK_ALL_CON11 (MT6325_PMIC_REG_BASE + 0x0416)
+#define MT6325_BUCK_ALL_CON12 (MT6325_PMIC_REG_BASE + 0x0418)
+#define MT6325_BUCK_ALL_CON13 (MT6325_PMIC_REG_BASE + 0x041A)
+#define MT6325_BUCK_ALL_CON14 (MT6325_PMIC_REG_BASE + 0x041C)
+#define MT6325_BUCK_ALL_CON15 (MT6325_PMIC_REG_BASE + 0x041E)
+#define MT6325_BUCK_ALL_CON16 (MT6325_PMIC_REG_BASE + 0x0420)
+#define MT6325_BUCK_ALL_CON17 (MT6325_PMIC_REG_BASE + 0x0422)
+#define MT6325_BUCK_ALL_CON18 (MT6325_PMIC_REG_BASE + 0x0424)
+#define MT6325_BUCK_ALL_CON19 (MT6325_PMIC_REG_BASE + 0x0426)
+#define MT6325_BUCK_ALL_CON20 (MT6325_PMIC_REG_BASE + 0x0428)
+#define MT6325_BUCK_ALL_CON21 (MT6325_PMIC_REG_BASE + 0x042A)
+#define MT6325_BUCK_ALL_CON22 (MT6325_PMIC_REG_BASE + 0x042C)
+#define MT6325_BUCK_ALL_CON23 (MT6325_PMIC_REG_BASE + 0x042E)
+#define MT6325_BUCK_ALL_CON24 (MT6325_PMIC_REG_BASE + 0x0430)
+#define MT6325_BUCK_ALL_CON25 (MT6325_PMIC_REG_BASE + 0x0432)
+#define MT6325_BUCK_ALL_CON26 (MT6325_PMIC_REG_BASE + 0x0434)
+#define MT6325_BUCK_ALL_CON27 (MT6325_PMIC_REG_BASE + 0x0436)
+#define MT6325_BUCK_ALL_CON28 (MT6325_PMIC_REG_BASE + 0x0438)
+#define MT6325_VDRAM_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x043A)
+#define MT6325_VDRAM_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x043C)
+#define MT6325_VDRAM_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x043E)
+#define MT6325_VDRAM_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0440)
+#define MT6325_VDRAM_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x0442)
+#define MT6325_VCORE1_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0444)
+#define MT6325_VCORE1_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0446)
+#define MT6325_VCORE1_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0448)
+#define MT6325_VCORE1_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x044A)
+#define MT6325_VCORE1_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x044C)
+#define MT6325_SMPS_TOP_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x044E)
+#define MT6325_SMPS_TOP_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0450)
+#define MT6325_SMPS_TOP_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0452)
+#define MT6325_SMPS_TOP_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0454)
+#define MT6325_SMPS_TOP_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x0456)
+#define MT6325_SMPS_TOP_ANA_CON5 (MT6325_PMIC_REG_BASE + 0x0458)
+#define MT6325_SMPS_TOP_ANA_CON6 (MT6325_PMIC_REG_BASE + 0x045A)
+#define MT6325_SMPS_TOP_ANA_CON7 (MT6325_PMIC_REG_BASE + 0x045C)
+#define MT6325_SMPS_TOP_ANA_CON8 (MT6325_PMIC_REG_BASE + 0x045E)
+#define MT6325_SMPS_TOP_ANA_CON9 (MT6325_PMIC_REG_BASE + 0x0460)
+#define MT6325_VDVFS1_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0462)
+#define MT6325_VDVFS1_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0464)
+#define MT6325_VDVFS1_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0466)
+#define MT6325_VDVFS1_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0468)
+#define MT6325_VDVFS1_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x046A)
+#define MT6325_VDVFS1_ANA_CON5 (MT6325_PMIC_REG_BASE + 0x046C)
+#define MT6325_VDVFS1_ANA_CON6 (MT6325_PMIC_REG_BASE + 0x046E)
+#define MT6325_VDVFS1_ANA_CON7 (MT6325_PMIC_REG_BASE + 0x0470)
+#define MT6325_VGPU_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0472)
+#define MT6325_VGPU_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0474)
+#define MT6325_VGPU_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0476)
+#define MT6325_VGPU_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0478)
+#define MT6325_VGPU_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x047A)
+#define MT6325_VPA_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x047C)
+#define MT6325_VPA_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x047E)
+#define MT6325_VPA_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0480)
+#define MT6325_VPA_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0482)
+#define MT6325_VCORE2_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0484)
+#define MT6325_VCORE2_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0486)
+#define MT6325_VCORE2_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0488)
+#define MT6325_VCORE2_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x048A)
+#define MT6325_VCORE2_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x048C)
+#define MT6325_VIO18_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x048E)
+#define MT6325_VIO18_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0490)
+#define MT6325_VIO18_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0492)
+#define MT6325_VIO18_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0494)
+#define MT6325_VIO18_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x0496)
+#define MT6325_VRF18_0_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0498)
+#define MT6325_VRF18_0_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x049A)
+#define MT6325_VRF18_0_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x049C)
+#define MT6325_VRF18_0_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x049E)
+#define MT6325_VRF18_0_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x04A0)
+#define MT6325_VDVFS11_CON0 (MT6325_PMIC_REG_BASE + 0x04A2)
+#define MT6325_VDVFS11_CON7 (MT6325_PMIC_REG_BASE + 0x04B0)
+#define MT6325_VDVFS11_CON8 (MT6325_PMIC_REG_BASE + 0x04B2)
+#define MT6325_VDVFS11_CON9 (MT6325_PMIC_REG_BASE + 0x04B4)
+#define MT6325_VDVFS11_CON10 (MT6325_PMIC_REG_BASE + 0x04B6)
+#define MT6325_VDVFS11_CON11 (MT6325_PMIC_REG_BASE + 0x04B8)
+#define MT6325_VDVFS11_CON12 (MT6325_PMIC_REG_BASE + 0x04BA)
+#define MT6325_VDVFS11_CON13 (MT6325_PMIC_REG_BASE + 0x04BC)
+#define MT6325_VDVFS11_CON14 (MT6325_PMIC_REG_BASE + 0x04BE)
+#define MT6325_VDVFS11_CON18 (MT6325_PMIC_REG_BASE + 0x04C6)
+#define MT6325_VDVFS12_CON0 (MT6325_PMIC_REG_BASE + 0x04C8)
+#define MT6325_VDVFS12_CON7 (MT6325_PMIC_REG_BASE + 0x04D6)
+#define MT6325_VDVFS12_CON8 (MT6325_PMIC_REG_BASE + 0x04D8)
+#define MT6325_VDVFS12_CON9 (MT6325_PMIC_REG_BASE + 0x04DA)
+#define MT6325_VDVFS12_CON10 (MT6325_PMIC_REG_BASE + 0x04DC)
+#define MT6325_VDVFS12_CON11 (MT6325_PMIC_REG_BASE + 0x04DE)
+#define MT6325_VDVFS12_CON12 (MT6325_PMIC_REG_BASE + 0x04E0)
+#define MT6325_VDVFS12_CON13 (MT6325_PMIC_REG_BASE + 0x04E2)
+#define MT6325_VDVFS12_CON14 (MT6325_PMIC_REG_BASE + 0x04E4)
+#define MT6325_VDVFS12_CON18 (MT6325_PMIC_REG_BASE + 0x04EC)
+#define MT6325_VSRAM_DVFS1_CON0 (MT6325_PMIC_REG_BASE + 0x04EE)
+#define MT6325_VSRAM_DVFS1_CON7 (MT6325_PMIC_REG_BASE + 0x04FC)
+#define MT6325_VSRAM_DVFS1_CON8 (MT6325_PMIC_REG_BASE + 0x04FE)
+#define MT6325_VSRAM_DVFS1_CON9 (MT6325_PMIC_REG_BASE + 0x0500)
+#define MT6325_VSRAM_DVFS1_CON10 (MT6325_PMIC_REG_BASE + 0x0502)
+#define MT6325_VSRAM_DVFS1_CON11 (MT6325_PMIC_REG_BASE + 0x0504)
+#define MT6325_VSRAM_DVFS1_CON12 (MT6325_PMIC_REG_BASE + 0x0506)
+#define MT6325_VSRAM_DVFS1_CON13 (MT6325_PMIC_REG_BASE + 0x0508)
+#define MT6325_VSRAM_DVFS1_CON14 (MT6325_PMIC_REG_BASE + 0x050A)
+#define MT6325_VSRAM_DVFS1_CON18 (MT6325_PMIC_REG_BASE + 0x0512)
+#define MT6325_VDRAM_CON0 (MT6325_PMIC_REG_BASE + 0x0514)
+#define MT6325_VDRAM_CON7 (MT6325_PMIC_REG_BASE + 0x0522)
+#define MT6325_VDRAM_CON8 (MT6325_PMIC_REG_BASE + 0x0524)
+#define MT6325_VDRAM_CON9 (MT6325_PMIC_REG_BASE + 0x0526)
+#define MT6325_VDRAM_CON10 (MT6325_PMIC_REG_BASE + 0x0528)
+#define MT6325_VDRAM_CON11 (MT6325_PMIC_REG_BASE + 0x052A)
+#define MT6325_VDRAM_CON12 (MT6325_PMIC_REG_BASE + 0x052C)
+#define MT6325_VDRAM_CON13 (MT6325_PMIC_REG_BASE + 0x052E)
+#define MT6325_VDRAM_CON14 (MT6325_PMIC_REG_BASE + 0x0530)
+#define MT6325_VDRAM_CON15 (MT6325_PMIC_REG_BASE + 0x0532)
+#define MT6325_VDRAM_CON18 (MT6325_PMIC_REG_BASE + 0x0538)
+#define MT6325_VRF18_0_CON0 (MT6325_PMIC_REG_BASE + 0x053A)
+#define MT6325_VRF18_0_CON7 (MT6325_PMIC_REG_BASE + 0x0548)
+#define MT6325_VRF18_0_CON8 (MT6325_PMIC_REG_BASE + 0x054A)
+#define MT6325_VRF18_0_CON9 (MT6325_PMIC_REG_BASE + 0x054C)
+#define MT6325_VRF18_0_CON10 (MT6325_PMIC_REG_BASE + 0x054E)
+#define MT6325_VRF18_0_CON11 (MT6325_PMIC_REG_BASE + 0x0550)
+#define MT6325_VRF18_0_CON12 (MT6325_PMIC_REG_BASE + 0x0552)
+#define MT6325_VRF18_0_CON13 (MT6325_PMIC_REG_BASE + 0x0554)
+#define MT6325_VRF18_0_CON14 (MT6325_PMIC_REG_BASE + 0x0556)
+#define MT6325_VRF18_0_CON15 (MT6325_PMIC_REG_BASE + 0x0558)
+#define MT6325_VRF18_0_CON18 (MT6325_PMIC_REG_BASE + 0x055E)
+#define MT6325_VGPU_CON0 (MT6325_PMIC_REG_BASE + 0x0600)
+#define MT6325_VGPU_CON7 (MT6325_PMIC_REG_BASE + 0x060E)
+#define MT6325_VGPU_CON8 (MT6325_PMIC_REG_BASE + 0x0610)
+#define MT6325_VGPU_CON9 (MT6325_PMIC_REG_BASE + 0x0612)
+#define MT6325_VGPU_CON10 (MT6325_PMIC_REG_BASE + 0x0614)
+#define MT6325_VGPU_CON11 (MT6325_PMIC_REG_BASE + 0x0616)
+#define MT6325_VGPU_CON12 (MT6325_PMIC_REG_BASE + 0x0618)
+#define MT6325_VGPU_CON13 (MT6325_PMIC_REG_BASE + 0x061A)
+#define MT6325_VGPU_CON14 (MT6325_PMIC_REG_BASE + 0x061C)
+#define MT6325_VGPU_CON15 (MT6325_PMIC_REG_BASE + 0x061E)
+#define MT6325_VGPU_CON16 (MT6325_PMIC_REG_BASE + 0x0620)
+#define MT6325_VGPU_CON17 (MT6325_PMIC_REG_BASE + 0x0622)
+#define MT6325_VGPU_CON18 (MT6325_PMIC_REG_BASE + 0x0624)
+#define MT6325_VCORE1_CON0 (MT6325_PMIC_REG_BASE + 0x0626)
+#define MT6325_VCORE1_CON7 (MT6325_PMIC_REG_BASE + 0x0634)
+#define MT6325_VCORE1_CON8 (MT6325_PMIC_REG_BASE + 0x0636)
+#define MT6325_VCORE1_CON9 (MT6325_PMIC_REG_BASE + 0x0638)
+#define MT6325_VCORE1_CON10 (MT6325_PMIC_REG_BASE + 0x063A)
+#define MT6325_VCORE1_CON11 (MT6325_PMIC_REG_BASE + 0x063C)
+#define MT6325_VCORE1_CON12 (MT6325_PMIC_REG_BASE + 0x063E)
+#define MT6325_VCORE1_CON13 (MT6325_PMIC_REG_BASE + 0x0640)
+#define MT6325_VCORE1_CON14 (MT6325_PMIC_REG_BASE + 0x0642)
+#define MT6325_VCORE1_CON15 (MT6325_PMIC_REG_BASE + 0x0644)
+#define MT6325_VCORE1_CON16 (MT6325_PMIC_REG_BASE + 0x0646)
+#define MT6325_VCORE1_CON17 (MT6325_PMIC_REG_BASE + 0x0648)
+#define MT6325_VCORE1_CON18 (MT6325_PMIC_REG_BASE + 0x064A)
+#define MT6325_VCORE2_CON0 (MT6325_PMIC_REG_BASE + 0x064C)
+#define MT6325_VCORE2_CON7 (MT6325_PMIC_REG_BASE + 0x065A)
+#define MT6325_VCORE2_CON8 (MT6325_PMIC_REG_BASE + 0x065C)
+#define MT6325_VCORE2_CON9 (MT6325_PMIC_REG_BASE + 0x065E)
+#define MT6325_VCORE2_CON10 (MT6325_PMIC_REG_BASE + 0x0660)
+#define MT6325_VCORE2_CON11 (MT6325_PMIC_REG_BASE + 0x0662)
+#define MT6325_VCORE2_CON12 (MT6325_PMIC_REG_BASE + 0x0664)
+#define MT6325_VCORE2_CON13 (MT6325_PMIC_REG_BASE + 0x0666)
+#define MT6325_VCORE2_CON14 (MT6325_PMIC_REG_BASE + 0x0668)
+#define MT6325_VCORE2_CON15 (MT6325_PMIC_REG_BASE + 0x066A)
+#define MT6325_VCORE2_CON16 (MT6325_PMIC_REG_BASE + 0x066C)
+#define MT6325_VCORE2_CON17 (MT6325_PMIC_REG_BASE + 0x066E)
+#define MT6325_VCORE2_CON18 (MT6325_PMIC_REG_BASE + 0x0670)
+#define MT6325_VCORE2_CON19 (MT6325_PMIC_REG_BASE + 0x0672)
+#define MT6325_VCORE2_CON20 (MT6325_PMIC_REG_BASE + 0x0674)
+#define MT6325_VIO18_CON0 (MT6325_PMIC_REG_BASE + 0x0676)
+#define MT6325_VIO18_CON7 (MT6325_PMIC_REG_BASE + 0x0684)
+#define MT6325_VIO18_CON8 (MT6325_PMIC_REG_BASE + 0x0686)
+#define MT6325_VIO18_CON9 (MT6325_PMIC_REG_BASE + 0x0688)
+#define MT6325_VIO18_CON10 (MT6325_PMIC_REG_BASE + 0x068A)
+#define MT6325_VIO18_CON11 (MT6325_PMIC_REG_BASE + 0x068C)
+#define MT6325_VIO18_CON12 (MT6325_PMIC_REG_BASE + 0x068E)
+#define MT6325_VIO18_CON13 (MT6325_PMIC_REG_BASE + 0x0690)
+#define MT6325_VIO18_CON14 (MT6325_PMIC_REG_BASE + 0x0692)
+#define MT6325_VIO18_CON15 (MT6325_PMIC_REG_BASE + 0x0694)
+#define MT6325_VIO18_CON16 (MT6325_PMIC_REG_BASE + 0x0696)
+#define MT6325_VIO18_CON17 (MT6325_PMIC_REG_BASE + 0x0698)
+#define MT6325_VIO18_CON18 (MT6325_PMIC_REG_BASE + 0x069A)
+#define MT6325_VPA_CON0 (MT6325_PMIC_REG_BASE + 0x069C)
+#define MT6325_VPA_CON7 (MT6325_PMIC_REG_BASE + 0x06AA)
+#define MT6325_VPA_CON8 (MT6325_PMIC_REG_BASE + 0x06AC)
+#define MT6325_VPA_CON9 (MT6325_PMIC_REG_BASE + 0x06AE)
+#define MT6325_VPA_CON10 (MT6325_PMIC_REG_BASE + 0x06B0)
+#define MT6325_VPA_CON11 (MT6325_PMIC_REG_BASE + 0x06B2)
+#define MT6325_VPA_CON12 (MT6325_PMIC_REG_BASE + 0x06B4)
+#define MT6325_VPA_CON13 (MT6325_PMIC_REG_BASE + 0x06B6)
+#define MT6325_VPA_CON14 (MT6325_PMIC_REG_BASE + 0x06B8)
+#define MT6325_VPA_CON15 (MT6325_PMIC_REG_BASE + 0x06BA)
+#define MT6325_VPA_CON16 (MT6325_PMIC_REG_BASE + 0x06BC)
+#define MT6325_VPA_CON17 (MT6325_PMIC_REG_BASE + 0x06BE)
+#define MT6325_VPA_CON18 (MT6325_PMIC_REG_BASE + 0x06C0)
+#define MT6325_VPA_CON19 (MT6325_PMIC_REG_BASE + 0x06C2)
+#define MT6325_VPA_CON20 (MT6325_PMIC_REG_BASE + 0x06C4)
+#define MT6325_VPA_CON21 (MT6325_PMIC_REG_BASE + 0x06C6)
+#define MT6325_VPA_CON22 (MT6325_PMIC_REG_BASE + 0x06C8)
+#define MT6325_VPA_CON23 (MT6325_PMIC_REG_BASE + 0x06CA)
+#define MT6325_BUCK_K_CON0 (MT6325_PMIC_REG_BASE + 0x06CC)
+#define MT6325_BUCK_K_CON1 (MT6325_PMIC_REG_BASE + 0x06CE)
+#define MT6325_BUCK_K_CON2 (MT6325_PMIC_REG_BASE + 0x06D0)
+#define MT6325_BUCK_K_CON3 (MT6325_PMIC_REG_BASE + 0x06D2)
+#define MT6325_ZCD_CON0 (MT6325_PMIC_REG_BASE + 0x0800)
+#define MT6325_ZCD_CON1 (MT6325_PMIC_REG_BASE + 0x0802)
+#define MT6325_ZCD_CON2 (MT6325_PMIC_REG_BASE + 0x0804)
+#define MT6325_ZCD_CON3 (MT6325_PMIC_REG_BASE + 0x0806)
+#define MT6325_ZCD_CON4 (MT6325_PMIC_REG_BASE + 0x0808)
+#define MT6325_ZCD_CON5 (MT6325_PMIC_REG_BASE + 0x080A)
+#define MT6325_ISINK0_CON0 (MT6325_PMIC_REG_BASE + 0x080C)
+#define MT6325_ISINK0_CON1 (MT6325_PMIC_REG_BASE + 0x080E)
+#define MT6325_ISINK0_CON2 (MT6325_PMIC_REG_BASE + 0x0810)
+#define MT6325_ISINK0_CON3 (MT6325_PMIC_REG_BASE + 0x0812)
+#define MT6325_ISINK1_CON0 (MT6325_PMIC_REG_BASE + 0x0814)
+#define MT6325_ISINK1_CON1 (MT6325_PMIC_REG_BASE + 0x0816)
+#define MT6325_ISINK1_CON2 (MT6325_PMIC_REG_BASE + 0x0818)
+#define MT6325_ISINK1_CON3 (MT6325_PMIC_REG_BASE + 0x081A)
+#define MT6325_ISINK2_CON0 (MT6325_PMIC_REG_BASE + 0x081C)
+#define MT6325_ISINK2_CON1 (MT6325_PMIC_REG_BASE + 0x081E)
+#define MT6325_ISINK2_CON2 (MT6325_PMIC_REG_BASE + 0x0820)
+#define MT6325_ISINK2_CON3 (MT6325_PMIC_REG_BASE + 0x0822)
+#define MT6325_ISINK3_CON0 (MT6325_PMIC_REG_BASE + 0x0824)
+#define MT6325_ISINK3_CON1 (MT6325_PMIC_REG_BASE + 0x0826)
+#define MT6325_ISINK3_CON2 (MT6325_PMIC_REG_BASE + 0x0828)
+#define MT6325_ISINK3_CON3 (MT6325_PMIC_REG_BASE + 0x082A)
+#define MT6325_ISINK_ANA0 (MT6325_PMIC_REG_BASE + 0x082C)
+#define MT6325_ISINK_ANA1 (MT6325_PMIC_REG_BASE + 0x082E)
+#define MT6325_ISINK_PHASE_DLY (MT6325_PMIC_REG_BASE + 0x0830)
+#define MT6325_ISINK_SFSTR (MT6325_PMIC_REG_BASE + 0x0832)
+#define MT6325_ISINK_EN_CTRL (MT6325_PMIC_REG_BASE + 0x0834)
+#define MT6325_ISINK_MODE_CTRL (MT6325_PMIC_REG_BASE + 0x0836)
+#define MT6325_ISINK_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0838)
+#define MT6325_LDO_CON0 (MT6325_PMIC_REG_BASE + 0x0A00)
+#define MT6325_LDO_CON1 (MT6325_PMIC_REG_BASE + 0x0A02)
+#define MT6325_LDO_CON2 (MT6325_PMIC_REG_BASE + 0x0A04)
+#define MT6325_LDO_CON3 (MT6325_PMIC_REG_BASE + 0x0A06)
+#define MT6325_LDO_CON4 (MT6325_PMIC_REG_BASE + 0x0A08)
+#define MT6325_LDO_CON5 (MT6325_PMIC_REG_BASE + 0x0A0A)
+#define MT6325_LDO_CON6 (MT6325_PMIC_REG_BASE + 0x0A0C)
+#define MT6325_LDO_CON7 (MT6325_PMIC_REG_BASE + 0x0A0E)
+#define MT6325_LDO_CON8 (MT6325_PMIC_REG_BASE + 0x0A10)
+#define MT6325_LDO_CON9 (MT6325_PMIC_REG_BASE + 0x0A12)
+#define MT6325_LDO_CON10 (MT6325_PMIC_REG_BASE + 0x0A14)
+#define MT6325_LDO_CON11 (MT6325_PMIC_REG_BASE + 0x0A16)
+#define MT6325_LDO_CON12 (MT6325_PMIC_REG_BASE + 0x0A18)
+#define MT6325_LDO_CON13 (MT6325_PMIC_REG_BASE + 0x0A1A)
+#define MT6325_LDO_CON14 (MT6325_PMIC_REG_BASE + 0x0A1C)
+#define MT6325_LDO_CON15 (MT6325_PMIC_REG_BASE + 0x0A1E)
+#define MT6325_LDO_CON16 (MT6325_PMIC_REG_BASE + 0x0A20)
+#define MT6325_LDO_CON17 (MT6325_PMIC_REG_BASE + 0x0A22)
+#define MT6325_LDO_CON18 (MT6325_PMIC_REG_BASE + 0x0A24)
+#define MT6325_LDO_CON19 (MT6325_PMIC_REG_BASE + 0x0A26)
+#define MT6325_LDO_CON20 (MT6325_PMIC_REG_BASE + 0x0A28)
+#define MT6325_LDO_CON21 (MT6325_PMIC_REG_BASE + 0x0A2A)
+#define MT6325_LDO_CON22 (MT6325_PMIC_REG_BASE + 0x0A2C)
+#define MT6325_LDO_CON23 (MT6325_PMIC_REG_BASE + 0x0A2E)
+#define MT6325_LDO_CON24 (MT6325_PMIC_REG_BASE + 0x0A30)
+#define MT6325_LDO_CON25 (MT6325_PMIC_REG_BASE + 0x0A32)
+#define MT6325_LDO_CON26 (MT6325_PMIC_REG_BASE + 0x0A34)
+#define MT6325_LDO_CON27 (MT6325_PMIC_REG_BASE + 0x0A36)
+#define MT6325_LDO_CON28 (MT6325_PMIC_REG_BASE + 0x0A38)
+#define MT6325_LDO_CON29 (MT6325_PMIC_REG_BASE + 0x0A3A)
+#define MT6325_LDO_CON30 (MT6325_PMIC_REG_BASE + 0x0A3C)
+#define MT6325_LDO_VCON0 (MT6325_PMIC_REG_BASE + 0x0A3E)
+#define MT6325_LDO_VCON1 (MT6325_PMIC_REG_BASE + 0x0A40)
+#define MT6325_LDO_VCON2 (MT6325_PMIC_REG_BASE + 0x0A42)
+#define MT6325_LDO_VCON3 (MT6325_PMIC_REG_BASE + 0x0A44)
+#define MT6325_LDO_VCON4 (MT6325_PMIC_REG_BASE + 0x0A46)
+#define MT6325_LDO_VCON5 (MT6325_PMIC_REG_BASE + 0x0A48)
+#define MT6325_LDO_VCON6 (MT6325_PMIC_REG_BASE + 0x0A4A)
+#define MT6325_LDO_VCON7 (MT6325_PMIC_REG_BASE + 0x0A4C)
+#define MT6325_LDO_VCON8 (MT6325_PMIC_REG_BASE + 0x0A4E)
+#define MT6325_LDO_VCON9 (MT6325_PMIC_REG_BASE + 0x0A50)
+#define MT6325_LDO_VCON10 (MT6325_PMIC_REG_BASE + 0x0A52)
+#define MT6325_LDO_VCON11 (MT6325_PMIC_REG_BASE + 0x0A54)
+#define MT6325_LDO_VCON13 (MT6325_PMIC_REG_BASE + 0x0A56)
+#define MT6325_LDO_VCON14 (MT6325_PMIC_REG_BASE + 0x0A58)
+#define MT6325_LDO_VCON15 (MT6325_PMIC_REG_BASE + 0x0A5A)
+#define MT6325_LDO_VCON16 (MT6325_PMIC_REG_BASE + 0x0A5C)
+#define MT6325_LDO_RSV0 (MT6325_PMIC_REG_BASE + 0x0A5E)
+#define MT6325_LDO_RSV1 (MT6325_PMIC_REG_BASE + 0x0A60)
+#define MT6325_LDO_RSV2 (MT6325_PMIC_REG_BASE + 0x0A62)
+#define MT6325_LDO_RSV3 (MT6325_PMIC_REG_BASE + 0x0A64)
+#define MT6325_LDO_OCFB0 (MT6325_PMIC_REG_BASE + 0x0A66)
+#define MT6325_LDO_OCFB1 (MT6325_PMIC_REG_BASE + 0x0A68)
+#define MT6325_LDO_OCFB2 (MT6325_PMIC_REG_BASE + 0x0A6A)
+#define MT6325_LDO_OCFB3 (MT6325_PMIC_REG_BASE + 0x0A6C)
+#define MT6325_LDO_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0A6E)
+#define MT6325_BIF_CON0 (MT6325_PMIC_REG_BASE + 0x0A70)
+#define MT6325_BIF_CON1 (MT6325_PMIC_REG_BASE + 0x0A72)
+#define MT6325_BIF_CON2 (MT6325_PMIC_REG_BASE + 0x0A74)
+#define MT6325_BIF_CON3 (MT6325_PMIC_REG_BASE + 0x0A76)
+#define MT6325_BIF_CON4 (MT6325_PMIC_REG_BASE + 0x0A78)
+#define MT6325_BIF_CON5 (MT6325_PMIC_REG_BASE + 0x0A7A)
+#define MT6325_BIF_CON6 (MT6325_PMIC_REG_BASE + 0x0A7C)
+#define MT6325_BIF_CON7 (MT6325_PMIC_REG_BASE + 0x0A7E)
+#define MT6325_BIF_CON8 (MT6325_PMIC_REG_BASE + 0x0A80)
+#define MT6325_BIF_CON9 (MT6325_PMIC_REG_BASE + 0x0A82)
+#define MT6325_BIF_CON10 (MT6325_PMIC_REG_BASE + 0x0A84)
+#define MT6325_BIF_CON11 (MT6325_PMIC_REG_BASE + 0x0A86)
+#define MT6325_BIF_CON12 (MT6325_PMIC_REG_BASE + 0x0A88)
+#define MT6325_BIF_CON13 (MT6325_PMIC_REG_BASE + 0x0A8A)
+#define MT6325_BIF_CON14 (MT6325_PMIC_REG_BASE + 0x0A8C)
+#define MT6325_BIF_CON15 (MT6325_PMIC_REG_BASE + 0x0A8E)
+#define MT6325_BIF_CON16 (MT6325_PMIC_REG_BASE + 0x0A90)
+#define MT6325_BIF_CON17 (MT6325_PMIC_REG_BASE + 0x0A92)
+#define MT6325_BIF_CON18 (MT6325_PMIC_REG_BASE + 0x0A94)
+#define MT6325_BIF_CON19 (MT6325_PMIC_REG_BASE + 0x0A96)
+#define MT6325_BIF_CON20 (MT6325_PMIC_REG_BASE + 0x0A98)
+#define MT6325_BIF_CON21 (MT6325_PMIC_REG_BASE + 0x0A9A)
+#define MT6325_BIF_CON22 (MT6325_PMIC_REG_BASE + 0x0A9C)
+#define MT6325_BIF_CON23 (MT6325_PMIC_REG_BASE + 0x0A9E)
+#define MT6325_BIF_CON24 (MT6325_PMIC_REG_BASE + 0x0AA0)
+#define MT6325_BIF_CON25 (MT6325_PMIC_REG_BASE + 0x0AA2)
+#define MT6325_BIF_CON26 (MT6325_PMIC_REG_BASE + 0x0AA4)
+#define MT6325_BIF_CON27 (MT6325_PMIC_REG_BASE + 0x0AA6)
+#define MT6325_BIF_CON28 (MT6325_PMIC_REG_BASE + 0x0AA8)
+#define MT6325_BIF_CON29 (MT6325_PMIC_REG_BASE + 0x0AAA)
+#define MT6325_BIF_CON30 (MT6325_PMIC_REG_BASE + 0x0AAC)
+#define MT6325_BIF_CON31 (MT6325_PMIC_REG_BASE + 0x0AAE)
+#define MT6325_BIF_CON32 (MT6325_PMIC_REG_BASE + 0x0AB0)
+#define MT6325_BIF_CON33 (MT6325_PMIC_REG_BASE + 0x0AB2)
+#define MT6325_BIF_CON34 (MT6325_PMIC_REG_BASE + 0x0AB4)
+#define MT6325_BIF_CON35 (MT6325_PMIC_REG_BASE + 0x0AB6)
+#define MT6325_BIF_CON36 (MT6325_PMIC_REG_BASE + 0x0AB8)
+#define MT6325_BATON_CON0 (MT6325_PMIC_REG_BASE + 0x0ABA)
+#define MT6325_BIF_CON37 (MT6325_PMIC_REG_BASE + 0x0ABC)
+#define MT6325_BIF_CON38 (MT6325_PMIC_REG_BASE + 0x0ABE)
+#define MT6325_BIF_CON39 (MT6325_PMIC_REG_BASE + 0x0AC0)
+#define MT6325_SPK_CON0 (MT6325_PMIC_REG_BASE + 0x0AC2)
+#define MT6325_SPK_CON1 (MT6325_PMIC_REG_BASE + 0x0AC4)
+#define MT6325_SPK_CON2 (MT6325_PMIC_REG_BASE + 0x0AC6)
+#define MT6325_SPK_CON3 (MT6325_PMIC_REG_BASE + 0x0AC8)
+#define MT6325_SPK_CON4 (MT6325_PMIC_REG_BASE + 0x0ACA)
+#define MT6325_SPK_CON5 (MT6325_PMIC_REG_BASE + 0x0ACC)
+#define MT6325_SPK_CON6 (MT6325_PMIC_REG_BASE + 0x0ACE)
+#define MT6325_SPK_CON7 (MT6325_PMIC_REG_BASE + 0x0AD0)
+#define MT6325_SPK_CON8 (MT6325_PMIC_REG_BASE + 0x0AD2)
+#define MT6325_SPK_CON9 (MT6325_PMIC_REG_BASE + 0x0AD4)
+#define MT6325_SPK_CON10 (MT6325_PMIC_REG_BASE + 0x0AD6)
+#define MT6325_SPK_CON11 (MT6325_PMIC_REG_BASE + 0x0AD8)
+#define MT6325_SPK_CON12 (MT6325_PMIC_REG_BASE + 0x0ADA)
+#define MT6325_SPK_CON13 (MT6325_PMIC_REG_BASE + 0x0ADC)
+#define MT6325_SPK_CON14 (MT6325_PMIC_REG_BASE + 0x0ADE)
+#define MT6325_SPK_CON15 (MT6325_PMIC_REG_BASE + 0x0AE0)
+#define MT6325_SPK_CON16 (MT6325_PMIC_REG_BASE + 0x0AE2)
+#define MT6325_SPK_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0AE4)
+#define MT6325_SPK_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0AE6)
+#define MT6325_SPK_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0AE8)
+#define MT6325_OTP_CON0 (MT6325_PMIC_REG_BASE + 0x0C00)
+#define MT6325_OTP_CON1 (MT6325_PMIC_REG_BASE + 0x0C02)
+#define MT6325_OTP_CON2 (MT6325_PMIC_REG_BASE + 0x0C04)
+#define MT6325_OTP_CON3 (MT6325_PMIC_REG_BASE + 0x0C06)
+#define MT6325_OTP_CON4 (MT6325_PMIC_REG_BASE + 0x0C08)
+#define MT6325_OTP_CON5 (MT6325_PMIC_REG_BASE + 0x0C0A)
+#define MT6325_OTP_CON6 (MT6325_PMIC_REG_BASE + 0x0C0C)
+#define MT6325_OTP_CON7 (MT6325_PMIC_REG_BASE + 0x0C0E)
+#define MT6325_OTP_CON8 (MT6325_PMIC_REG_BASE + 0x0C10)
+#define MT6325_OTP_CON9 (MT6325_PMIC_REG_BASE + 0x0C12)
+#define MT6325_OTP_CON10 (MT6325_PMIC_REG_BASE + 0x0C14)
+#define MT6325_OTP_CON11 (MT6325_PMIC_REG_BASE + 0x0C16)
+#define MT6325_OTP_CON12 (MT6325_PMIC_REG_BASE + 0x0C18)
+#define MT6325_OTP_CON13 (MT6325_PMIC_REG_BASE + 0x0C1A)
+#define MT6325_OTP_CON14 (MT6325_PMIC_REG_BASE + 0x0C1C)
+#define MT6325_OTP_DOUT_0_15 (MT6325_PMIC_REG_BASE + 0x0C1E)
+#define MT6325_OTP_DOUT_16_31 (MT6325_PMIC_REG_BASE + 0x0C20)
+#define MT6325_OTP_DOUT_32_47 (MT6325_PMIC_REG_BASE + 0x0C22)
+#define MT6325_OTP_DOUT_48_63 (MT6325_PMIC_REG_BASE + 0x0C24)
+#define MT6325_OTP_DOUT_64_79 (MT6325_PMIC_REG_BASE + 0x0C26)
+#define MT6325_OTP_DOUT_80_95 (MT6325_PMIC_REG_BASE + 0x0C28)
+#define MT6325_OTP_DOUT_96_111 (MT6325_PMIC_REG_BASE + 0x0C2A)
+#define MT6325_OTP_DOUT_112_127 (MT6325_PMIC_REG_BASE + 0x0C2C)
+#define MT6325_OTP_DOUT_128_143 (MT6325_PMIC_REG_BASE + 0x0C2E)
+#define MT6325_OTP_DOUT_144_159 (MT6325_PMIC_REG_BASE + 0x0C30)
+#define MT6325_OTP_DOUT_160_175 (MT6325_PMIC_REG_BASE + 0x0C32)
+#define MT6325_OTP_DOUT_176_191 (MT6325_PMIC_REG_BASE + 0x0C34)
+#define MT6325_OTP_DOUT_192_207 (MT6325_PMIC_REG_BASE + 0x0C36)
+#define MT6325_OTP_DOUT_208_223 (MT6325_PMIC_REG_BASE + 0x0C38)
+#define MT6325_OTP_DOUT_224_239 (MT6325_PMIC_REG_BASE + 0x0C3A)
+#define MT6325_OTP_DOUT_240_255 (MT6325_PMIC_REG_BASE + 0x0C3C)
+#define MT6325_OTP_DOUT_256_271 (MT6325_PMIC_REG_BASE + 0x0C3E)
+#define MT6325_OTP_DOUT_272_287 (MT6325_PMIC_REG_BASE + 0x0C40)
+#define MT6325_OTP_DOUT_288_303 (MT6325_PMIC_REG_BASE + 0x0C42)
+#define MT6325_OTP_DOUT_304_319 (MT6325_PMIC_REG_BASE + 0x0C44)
+#define MT6325_OTP_DOUT_320_335 (MT6325_PMIC_REG_BASE + 0x0C46)
+#define MT6325_OTP_DOUT_336_351 (MT6325_PMIC_REG_BASE + 0x0C48)
+#define MT6325_OTP_DOUT_352_367 (MT6325_PMIC_REG_BASE + 0x0C4A)
+#define MT6325_OTP_DOUT_368_383 (MT6325_PMIC_REG_BASE + 0x0C4C)
+#define MT6325_OTP_DOUT_384_399 (MT6325_PMIC_REG_BASE + 0x0C4E)
+#define MT6325_OTP_DOUT_400_415 (MT6325_PMIC_REG_BASE + 0x0C50)
+#define MT6325_OTP_DOUT_416_431 (MT6325_PMIC_REG_BASE + 0x0C52)
+#define MT6325_OTP_DOUT_432_447 (MT6325_PMIC_REG_BASE + 0x0C54)
+#define MT6325_OTP_DOUT_448_463 (MT6325_PMIC_REG_BASE + 0x0C56)
+#define MT6325_OTP_DOUT_464_479 (MT6325_PMIC_REG_BASE + 0x0C58)
+#define MT6325_OTP_DOUT_480_495 (MT6325_PMIC_REG_BASE + 0x0C5A)
+#define MT6325_OTP_DOUT_496_511 (MT6325_PMIC_REG_BASE + 0x0C5C)
+#define MT6325_OTP_VAL_0_15 (MT6325_PMIC_REG_BASE + 0x0C5E)
+#define MT6325_OTP_VAL_16_31 (MT6325_PMIC_REG_BASE + 0x0C60)
+#define MT6325_OTP_VAL_32_47 (MT6325_PMIC_REG_BASE + 0x0C62)
+#define MT6325_OTP_VAL_48_63 (MT6325_PMIC_REG_BASE + 0x0C64)
+#define MT6325_OTP_VAL_64_79 (MT6325_PMIC_REG_BASE + 0x0C66)
+#define MT6325_OTP_VAL_80_95 (MT6325_PMIC_REG_BASE + 0x0C68)
+#define MT6325_OTP_VAL_96_111 (MT6325_PMIC_REG_BASE + 0x0C6A)
+#define MT6325_OTP_VAL_112_127 (MT6325_PMIC_REG_BASE + 0x0C6C)
+#define MT6325_OTP_VAL_128_143 (MT6325_PMIC_REG_BASE + 0x0C6E)
+#define MT6325_OTP_VAL_144_159 (MT6325_PMIC_REG_BASE + 0x0C70)
+#define MT6325_OTP_VAL_160_175 (MT6325_PMIC_REG_BASE + 0x0C72)
+#define MT6325_OTP_VAL_176_191 (MT6325_PMIC_REG_BASE + 0x0C74)
+#define MT6325_OTP_VAL_192_207 (MT6325_PMIC_REG_BASE + 0x0C76)
+#define MT6325_OTP_VAL_208_223 (MT6325_PMIC_REG_BASE + 0x0C78)
+#define MT6325_OTP_VAL_224_239 (MT6325_PMIC_REG_BASE + 0x0C7A)
+#define MT6325_OTP_VAL_240_255 (MT6325_PMIC_REG_BASE + 0x0C7C)
+#define MT6325_OTP_VAL_256_271 (MT6325_PMIC_REG_BASE + 0x0C7E)
+#define MT6325_OTP_VAL_272_287 (MT6325_PMIC_REG_BASE + 0x0C80)
+#define MT6325_OTP_VAL_288_303 (MT6325_PMIC_REG_BASE + 0x0C82)
+#define MT6325_OTP_VAL_304_319 (MT6325_PMIC_REG_BASE + 0x0C84)
+#define MT6325_OTP_VAL_320_335 (MT6325_PMIC_REG_BASE + 0x0C86)
+#define MT6325_OTP_VAL_336_351 (MT6325_PMIC_REG_BASE + 0x0C88)
+#define MT6325_OTP_VAL_352_367 (MT6325_PMIC_REG_BASE + 0x0C8A)
+#define MT6325_OTP_VAL_368_383 (MT6325_PMIC_REG_BASE + 0x0C8C)
+#define MT6325_OTP_VAL_384_399 (MT6325_PMIC_REG_BASE + 0x0C8E)
+#define MT6325_OTP_VAL_400_415 (MT6325_PMIC_REG_BASE + 0x0C90)
+#define MT6325_OTP_VAL_416_431 (MT6325_PMIC_REG_BASE + 0x0C92)
+#define MT6325_OTP_VAL_432_447 (MT6325_PMIC_REG_BASE + 0x0C94)
+#define MT6325_OTP_VAL_448_463 (MT6325_PMIC_REG_BASE + 0x0C96)
+#define MT6325_OTP_VAL_464_479 (MT6325_PMIC_REG_BASE + 0x0C98)
+#define MT6325_OTP_VAL_480_495 (MT6325_PMIC_REG_BASE + 0x0C9A)
+#define MT6325_OTP_VAL_496_511 (MT6325_PMIC_REG_BASE + 0x0C9C)
+#define MT6325_RTC_MIX_CON0 (MT6325_PMIC_REG_BASE + 0x0C9E)
+#define MT6325_RTC_MIX_CON1 (MT6325_PMIC_REG_BASE + 0x0CA0)
+#define MT6325_RTC_MIX_CON2 (MT6325_PMIC_REG_BASE + 0x0CA2)
+#define MT6325_FGADC_CON0 (MT6325_PMIC_REG_BASE + 0x0CA4)
+#define MT6325_FGADC_CON1 (MT6325_PMIC_REG_BASE + 0x0CA6)
+#define MT6325_FGADC_CON2 (MT6325_PMIC_REG_BASE + 0x0CA8)
+#define MT6325_FGADC_CON3 (MT6325_PMIC_REG_BASE + 0x0CAA)
+#define MT6325_FGADC_CON4 (MT6325_PMIC_REG_BASE + 0x0CAC)
+#define MT6325_FGADC_CON5 (MT6325_PMIC_REG_BASE + 0x0CAE)
+#define MT6325_FGADC_CON6 (MT6325_PMIC_REG_BASE + 0x0CB0)
+#define MT6325_FGADC_CON7 (MT6325_PMIC_REG_BASE + 0x0CB2)
+#define MT6325_FGADC_CON8 (MT6325_PMIC_REG_BASE + 0x0CB4)
+#define MT6325_FGADC_CON9 (MT6325_PMIC_REG_BASE + 0x0CB6)
+#define MT6325_FGADC_CON10 (MT6325_PMIC_REG_BASE + 0x0CB8)
+#define MT6325_FGADC_CON11 (MT6325_PMIC_REG_BASE + 0x0CBA)
+#define MT6325_FGADC_CON12 (MT6325_PMIC_REG_BASE + 0x0CBC)
+#define MT6325_FGADC_CON13 (MT6325_PMIC_REG_BASE + 0x0CBE)
+#define MT6325_FGADC_CON14 (MT6325_PMIC_REG_BASE + 0x0CC0)
+#define MT6325_FGADC_CON15 (MT6325_PMIC_REG_BASE + 0x0CC2)
+#define MT6325_FGADC_CON16 (MT6325_PMIC_REG_BASE + 0x0CC4)
+#define MT6325_FGADC_CON17 (MT6325_PMIC_REG_BASE + 0x0CC6)
+#define MT6325_FGADC_CON18 (MT6325_PMIC_REG_BASE + 0x0CC8)
+#define MT6325_FGADC_CON19 (MT6325_PMIC_REG_BASE + 0x0CCA)
+#define MT6325_FGADC_CON20 (MT6325_PMIC_REG_BASE + 0x0CCC)
+#define MT6325_FGADC_CON21 (MT6325_PMIC_REG_BASE + 0x0CCE)
+#define MT6325_FGADC_CON22 (MT6325_PMIC_REG_BASE + 0x0CD0)
+#define MT6325_FGADC_CON23 (MT6325_PMIC_REG_BASE + 0x0CD2)
+#define MT6325_FGADC_CON24 (MT6325_PMIC_REG_BASE + 0x0CD4)
+#define MT6325_FGADC_CON25 (MT6325_PMIC_REG_BASE + 0x0CD6)
+#define MT6325_FGADC_CON26 (MT6325_PMIC_REG_BASE + 0x0CD8)
+#define MT6325_FGADC_CON27 (MT6325_PMIC_REG_BASE + 0x0CDA)
+#define MT6325_FGADC_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0CDC)
+#define MT6325_AUDDEC_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0CDE)
+#define MT6325_AUDDEC_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0CE0)
+#define MT6325_AUDDEC_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0CE2)
+#define MT6325_AUDDEC_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0CE4)
+#define MT6325_AUDDEC_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x0CE6)
+#define MT6325_AUDDEC_ANA_CON5 (MT6325_PMIC_REG_BASE + 0x0CE8)
+#define MT6325_AUDDEC_ANA_CON6 (MT6325_PMIC_REG_BASE + 0x0CEA)
+#define MT6325_AUDDEC_ANA_CON7 (MT6325_PMIC_REG_BASE + 0x0CEC)
+#define MT6325_AUDDEC_ANA_CON8 (MT6325_PMIC_REG_BASE + 0x0CEE)
+#define MT6325_AUDENC_ANA_CON0 (MT6325_PMIC_REG_BASE + 0x0CF0)
+#define MT6325_AUDENC_ANA_CON1 (MT6325_PMIC_REG_BASE + 0x0CF2)
+#define MT6325_AUDENC_ANA_CON2 (MT6325_PMIC_REG_BASE + 0x0CF4)
+#define MT6325_AUDENC_ANA_CON3 (MT6325_PMIC_REG_BASE + 0x0CF6)
+#define MT6325_AUDENC_ANA_CON4 (MT6325_PMIC_REG_BASE + 0x0CF8)
+#define MT6325_AUDENC_ANA_CON5 (MT6325_PMIC_REG_BASE + 0x0CFA)
+#define MT6325_AUDENC_ANA_CON6 (MT6325_PMIC_REG_BASE + 0x0CFC)
+#define MT6325_AUDENC_ANA_CON7 (MT6325_PMIC_REG_BASE + 0x0CFE)
+#define MT6325_AUDENC_ANA_CON8 (MT6325_PMIC_REG_BASE + 0x0D00)
+#define MT6325_AUDENC_ANA_CON9 (MT6325_PMIC_REG_BASE + 0x0D02)
+#define MT6325_AUDENC_ANA_CON11 (MT6325_PMIC_REG_BASE + 0x0D04)
+#define MT6325_AUDENC_ANA_CON12 (MT6325_PMIC_REG_BASE + 0x0D06)
+#define MT6325_AUDENC_ANA_CON13 (MT6325_PMIC_REG_BASE + 0x0D08)
+#define MT6325_AUDENC_ANA_CON14 (MT6325_PMIC_REG_BASE + 0x0D0A)
+#define MT6325_AUDENC_ANA_CON15 (MT6325_PMIC_REG_BASE + 0x0D0C)
+#define MT6325_AUDNCP_CLKDIV_CON0 (MT6325_PMIC_REG_BASE + 0x0D0E)
+#define MT6325_AUDNCP_CLKDIV_CON1 (MT6325_PMIC_REG_BASE + 0x0D10)
+#define MT6325_AUDNCP_CLKDIV_CON2 (MT6325_PMIC_REG_BASE + 0x0D12)
+#define MT6325_AUDNCP_CLKDIV_CON3 (MT6325_PMIC_REG_BASE + 0x0D14)
+#define MT6325_AUDNCP_CLKDIV_CON4 (MT6325_PMIC_REG_BASE + 0x0D16)
+#define MT6325_AUXADC_RSV0 (MT6325_PMIC_REG_BASE + 0x0E00)
+#define MT6325_AUXADC_STA0 (MT6325_PMIC_REG_BASE + 0x0E02)
+#define MT6325_AUXADC_STA1 (MT6325_PMIC_REG_BASE + 0x0E04)
+#define MT6325_AUXADC_RQST0 (MT6325_PMIC_REG_BASE + 0x0E06)
+#define MT6325_AUXADC_RQST0_SET (MT6325_PMIC_REG_BASE + 0x0E08)
+#define MT6325_AUXADC_RQST0_CLR (MT6325_PMIC_REG_BASE + 0x0E0A)
+#define MT6325_AUXADC_RQST1 (MT6325_PMIC_REG_BASE + 0x0E0C)
+#define MT6325_AUXADC_RQST1_SET (MT6325_PMIC_REG_BASE + 0x0E0E)
+#define MT6325_AUXADC_RQST1_CLR (MT6325_PMIC_REG_BASE + 0x0E10)
+#define MT6325_AUXADC_CK0 (MT6325_PMIC_REG_BASE + 0x0E12)
+#define MT6325_AUXADC_THR0 (MT6325_PMIC_REG_BASE + 0x0E14)
+#define MT6325_AUXADC_THR1 (MT6325_PMIC_REG_BASE + 0x0E16)
+#define MT6325_AUXADC_THR2 (MT6325_PMIC_REG_BASE + 0x0E18)
+#define MT6325_AUXADC_THR3 (MT6325_PMIC_REG_BASE + 0x0E1A)
+#define MT6325_AUXADC_THR4 (MT6325_PMIC_REG_BASE + 0x0E1C)
+#define MT6325_AUXADC_THR5 (MT6325_PMIC_REG_BASE + 0x0E1E)
+#define MT6325_AUXADC_THR6 (MT6325_PMIC_REG_BASE + 0x0E20)
+#define MT6325_AUXADC_THR7 (MT6325_PMIC_REG_BASE + 0x0E22)
+#define MT6325_AUXADC_DBG0 (MT6325_PMIC_REG_BASE + 0x0E24)
+#define MT6325_AUXADC_AUTORPT0 (MT6325_PMIC_REG_BASE + 0x0E26)
+#define MT6325_AUXADC_IMP0 (MT6325_PMIC_REG_BASE + 0x0E28)
+#define MT6325_AUXADC_VISMPS0_1 (MT6325_PMIC_REG_BASE + 0x0E2A)
+#define MT6325_AUXADC_VISMPS0_2 (MT6325_PMIC_REG_BASE + 0x0E2C)
+#define MT6325_AUXADC_VISMPS0_3 (MT6325_PMIC_REG_BASE + 0x0E2E)
+#define MT6325_AUXADC_VISMPS0_4 (MT6325_PMIC_REG_BASE + 0x0E30)
+#define MT6325_AUXADC_VISMPS0_5 (MT6325_PMIC_REG_BASE + 0x0E32)
+#define MT6325_AUXADC_VISMPS0_6 (MT6325_PMIC_REG_BASE + 0x0E34)
+#define MT6325_AUXADC_VISMPS0_7 (MT6325_PMIC_REG_BASE + 0x0E36)
+#define MT6325_AUXADC_LBAT2_1 (MT6325_PMIC_REG_BASE + 0x0E38)
+#define MT6325_AUXADC_LBAT2_2 (MT6325_PMIC_REG_BASE + 0x0E3A)
+#define MT6325_AUXADC_LBAT2_3 (MT6325_PMIC_REG_BASE + 0x0E3C)
+#define MT6325_AUXADC_LBAT2_4 (MT6325_PMIC_REG_BASE + 0x0E3E)
+#define MT6325_AUXADC_LBAT2_5 (MT6325_PMIC_REG_BASE + 0x0E40)
+#define MT6325_AUXADC_LBAT2_6 (MT6325_PMIC_REG_BASE + 0x0E42)
+#define MT6325_AUXADC_LBAT2_7 (MT6325_PMIC_REG_BASE + 0x0E44)
+#define MT6325_AUXADC_ADC0 (MT6325_PMIC_REG_BASE + 0x0E46)
+#define MT6325_AUXADC_ADC1 (MT6325_PMIC_REG_BASE + 0x0E48)
+#define MT6325_AUXADC_ADC2 (MT6325_PMIC_REG_BASE + 0x0E4A)
+#define MT6325_AUXADC_ADC3 (MT6325_PMIC_REG_BASE + 0x0E4C)
+#define MT6325_AUXADC_ADC4 (MT6325_PMIC_REG_BASE + 0x0E4E)
+#define MT6325_AUXADC_ADC5 (MT6325_PMIC_REG_BASE + 0x0E50)
+#define MT6325_AUXADC_ADC6 (MT6325_PMIC_REG_BASE + 0x0E52)
+#define MT6325_AUXADC_ADC7 (MT6325_PMIC_REG_BASE + 0x0E54)
+#define MT6325_AUXADC_ADC8 (MT6325_PMIC_REG_BASE + 0x0E56)
+#define MT6325_AUXADC_ADC9 (MT6325_PMIC_REG_BASE + 0x0E58)
+#define MT6325_AUXADC_ADC10 (MT6325_PMIC_REG_BASE + 0x0E5A)
+#define MT6325_AUXADC_ADC11 (MT6325_PMIC_REG_BASE + 0x0E5C)
+#define MT6325_AUXADC_ADC12 (MT6325_PMIC_REG_BASE + 0x0E5E)
+#define MT6325_AUXADC_ADC13 (MT6325_PMIC_REG_BASE + 0x0E60)
+#define MT6325_AUXADC_ADC14 (MT6325_PMIC_REG_BASE + 0x0E62)
+#define MT6325_AUXADC_ADC15 (MT6325_PMIC_REG_BASE + 0x0E64)
+#define MT6325_AUXADC_ADC16 (MT6325_PMIC_REG_BASE + 0x0E66)
+#define MT6325_AUXADC_ADC17 (MT6325_PMIC_REG_BASE + 0x0E68)
+#define MT6325_AUXADC_ADC18 (MT6325_PMIC_REG_BASE + 0x0E6A)
+#define MT6325_AUXADC_ADC19 (MT6325_PMIC_REG_BASE + 0x0E6C)
+#define MT6325_AUXADC_ADC20 (MT6325_PMIC_REG_BASE + 0x0E6E)
+#define MT6325_AUXADC_ADC21 (MT6325_PMIC_REG_BASE + 0x0E70)
+#define MT6325_AUXADC_ADC22 (MT6325_PMIC_REG_BASE + 0x0E72)
+#define MT6325_AUXADC_ADC23 (MT6325_PMIC_REG_BASE + 0x0E74)
+#define MT6325_AUXADC_ADC24 (MT6325_PMIC_REG_BASE + 0x0E76)
+#define MT6325_AUXADC_ADC25 (MT6325_PMIC_REG_BASE + 0x0E78)
+#define MT6325_AUXADC_ADC26 (MT6325_PMIC_REG_BASE + 0x0E7A)
+#define MT6325_AUXADC_ADC27 (MT6325_PMIC_REG_BASE + 0x0E7C)
+#define MT6325_AUXADC_ADC28 (MT6325_PMIC_REG_BASE + 0x0E7E)
+#define MT6325_AUXADC_ADC29 (MT6325_PMIC_REG_BASE + 0x0E80)
+#define MT6325_AUXADC_ADC30 (MT6325_PMIC_REG_BASE + 0x0E82)
+#define MT6325_AUXADC_RSV1 (MT6325_PMIC_REG_BASE + 0x0E84)
+#define MT6325_AUXADC_RSV2 (MT6325_PMIC_REG_BASE + 0x0E86)
+#define MT6325_AUXADC_CON0 (MT6325_PMIC_REG_BASE + 0x0E88)
+#define MT6325_AUXADC_CON1 (MT6325_PMIC_REG_BASE + 0x0E8A)
+#define MT6325_AUXADC_CON2 (MT6325_PMIC_REG_BASE + 0x0E8C)
+#define MT6325_AUXADC_CON3 (MT6325_PMIC_REG_BASE + 0x0E8E)
+#define MT6325_AUXADC_CON4 (MT6325_PMIC_REG_BASE + 0x0E90)
+#define MT6325_AUXADC_CON5 (MT6325_PMIC_REG_BASE + 0x0E92)
+#define MT6325_AUXADC_CON6 (MT6325_PMIC_REG_BASE + 0x0E94)
+#define MT6325_AUXADC_CON7 (MT6325_PMIC_REG_BASE + 0x0E96)
+#define MT6325_AUXADC_CON8 (MT6325_PMIC_REG_BASE + 0x0E98)
+#define MT6325_AUXADC_CON9 (MT6325_PMIC_REG_BASE + 0x0E9A)
+#define MT6325_AUXADC_CON10 (MT6325_PMIC_REG_BASE + 0x0E9C)
+#define MT6325_AUXADC_CON11 (MT6325_PMIC_REG_BASE + 0x0E9E)
+#define MT6325_AUXADC_CON12 (MT6325_PMIC_REG_BASE + 0x0EA0)
+#define MT6325_AUXADC_CON13 (MT6325_PMIC_REG_BASE + 0x0EA2)
+#define MT6325_AUXADC_CON14 (MT6325_PMIC_REG_BASE + 0x0EA4)
+#define MT6325_AUXADC_CON15 (MT6325_PMIC_REG_BASE + 0x0EA6)
+#define MT6325_AUXADC_CON16 (MT6325_PMIC_REG_BASE + 0x0EA8)
+#define MT6325_AUXADC_CON17 (MT6325_PMIC_REG_BASE + 0x0EAA)
+#define MT6325_AUXADC_CON18 (MT6325_PMIC_REG_BASE + 0x0EAC)
+#define MT6325_AUXADC_CON19 (MT6325_PMIC_REG_BASE + 0x0EAE)
+#define MT6325_AUXADC_CON20 (MT6325_PMIC_REG_BASE + 0x0EB0)
+#define MT6325_AUXADC_CON21 (MT6325_PMIC_REG_BASE + 0x0EB2)
+#define MT6325_AUXADC_CON22 (MT6325_PMIC_REG_BASE + 0x0EB4)
+#define MT6325_AUXADC_CON23 (MT6325_PMIC_REG_BASE + 0x0EB6)
+#define MT6325_AUXADC_CON24 (MT6325_PMIC_REG_BASE + 0x0EB8)
+#define MT6325_AUXADC_CON25 (MT6325_PMIC_REG_BASE + 0x0EBA)
+#define MT6325_AUXADC_CON26 (MT6325_PMIC_REG_BASE + 0x0EBC)
+#define MT6325_AUXADC_CON27 (MT6325_PMIC_REG_BASE + 0x0EBE)
+#define MT6325_ACCDET_CON0 (MT6325_PMIC_REG_BASE + 0x0EC0)
+#define MT6325_ACCDET_CON1 (MT6325_PMIC_REG_BASE + 0x0EC2)
+#define MT6325_ACCDET_CON2 (MT6325_PMIC_REG_BASE + 0x0EC4)
+#define MT6325_ACCDET_CON3 (MT6325_PMIC_REG_BASE + 0x0EC6)
+#define MT6325_ACCDET_CON4 (MT6325_PMIC_REG_BASE + 0x0EC8)
+#define MT6325_ACCDET_CON5 (MT6325_PMIC_REG_BASE + 0x0ECA)
+#define MT6325_ACCDET_CON6 (MT6325_PMIC_REG_BASE + 0x0ECC)
+#define MT6325_ACCDET_CON7 (MT6325_PMIC_REG_BASE + 0x0ECE)
+#define MT6325_ACCDET_CON8 (MT6325_PMIC_REG_BASE + 0x0ED0)
+#define MT6325_ACCDET_CON9 (MT6325_PMIC_REG_BASE + 0x0ED2)
+#define MT6325_ACCDET_CON10 (MT6325_PMIC_REG_BASE + 0x0ED4)
+#define MT6325_ACCDET_CON11 (MT6325_PMIC_REG_BASE + 0x0ED6)
+#define MT6325_ACCDET_CON12 (MT6325_PMIC_REG_BASE + 0x0ED8)
+#define MT6325_ACCDET_CON13 (MT6325_PMIC_REG_BASE + 0x0EDA)
+#define MT6325_ACCDET_CON14 (MT6325_PMIC_REG_BASE + 0x0EDC)
+#define MT6325_ACCDET_CON15 (MT6325_PMIC_REG_BASE + 0x0EDE)
+#define MT6325_ACCDET_CON16 (MT6325_PMIC_REG_BASE + 0x0EE0)
+#define MT6325_ACCDET_CON17 (MT6325_PMIC_REG_BASE + 0x0EE2)
+#define MT6325_ACCDET_CON18 (MT6325_PMIC_REG_BASE + 0x0EE4)
+#define MT6325_ACCDET_CON19 (MT6325_PMIC_REG_BASE + 0x0EE6)
+#define MT6325_ACCDET_CON20 (MT6325_PMIC_REG_BASE + 0x0EE8)
+#define MT6325_ACCDET_CON21 (MT6325_PMIC_REG_BASE + 0x0EEA)
+#define MT6325_ACCDET_CON22 (MT6325_PMIC_REG_BASE + 0x0EEC)
+#define MT6325_ACCDET_CON23 (MT6325_PMIC_REG_BASE + 0x0EEE)
+#define MT6325_ACCDET_CON24 (MT6325_PMIC_REG_BASE + 0x0EF0)
+#define MT6325_CHR_CON0 (MT6325_PMIC_REG_BASE + 0x0EF2)
+#define MT6325_CHR_CON1 (MT6325_PMIC_REG_BASE + 0x0EF4)
+#define MT6325_CHR_CON2 (MT6325_PMIC_REG_BASE + 0x0EF6)
+#define MT6325_CHR_CON3 (MT6325_PMIC_REG_BASE + 0x0EF8)
+#define MT6325_CHR_CON4 (MT6325_PMIC_REG_BASE + 0x0EFA)
+#define MT6325_CHR_CON5 (MT6325_PMIC_REG_BASE + 0x0EFC)
+#define MT6325_CHR_CON6 (MT6325_PMIC_REG_BASE + 0x0EFE)
+#define MT6325_CHR_CON7 (MT6325_PMIC_REG_BASE + 0x0F00)
+#define MT6325_CHR_CON8 (MT6325_PMIC_REG_BASE + 0x0F02)
+#define MT6325_CHR_CON9 (MT6325_PMIC_REG_BASE + 0x0F04)
+#define MT6325_CHR_CON10 (MT6325_PMIC_REG_BASE + 0x0F06)
+#define MT6325_CHR_CON11 (MT6325_PMIC_REG_BASE + 0x0F08)
+#define MT6325_CHR_CON12 (MT6325_PMIC_REG_BASE + 0x0F0A)
+#define MT6325_CHR_CON13 (MT6325_PMIC_REG_BASE + 0x0F0C)
+#define MT6325_CHR_CON14 (MT6325_PMIC_REG_BASE + 0x0F0E)
+#define MT6325_CHR_CON15 (MT6325_PMIC_REG_BASE + 0x0F10)
+#define MT6325_CHR_CON16 (MT6325_PMIC_REG_BASE + 0x0F12)
+#define MT6325_CHR_CON17 (MT6325_PMIC_REG_BASE + 0x0F14)
+#define MT6325_CHR_CON18 (MT6325_PMIC_REG_BASE + 0x0F16)
+#define MT6325_CHR_CON19 (MT6325_PMIC_REG_BASE + 0x0F18)
+#define MT6325_CHR_CON20 (MT6325_PMIC_REG_BASE + 0x0F1A)
+#define MT6325_CHR_CON21 (MT6325_PMIC_REG_BASE + 0x0F1C)
+#define MT6325_CHR_CON22 (MT6325_PMIC_REG_BASE + 0x0F1E)
+#define MT6325_CHR_CON23 (MT6325_PMIC_REG_BASE + 0x0F20)
+#define MT6325_CHR_CON24 (MT6325_PMIC_REG_BASE + 0x0F22)
+#define MT6325_CHR_CON25 (MT6325_PMIC_REG_BASE + 0x0F24)
+#define MT6325_CHR_CON26 (MT6325_PMIC_REG_BASE + 0x0F26)
+#define MT6325_CHR_CON27 (MT6325_PMIC_REG_BASE + 0x0F28)
+#define MT6325_CHR_CON28 (MT6325_PMIC_REG_BASE + 0x0F2A)
+#define MT6325_CHR_CON29 (MT6325_PMIC_REG_BASE + 0x0F2C)
+#define MT6325_CHR_CON30 (MT6325_PMIC_REG_BASE + 0x0F2E)
+#define MT6325_CHR_CON31 (MT6325_PMIC_REG_BASE + 0x0F30)
+#define MT6325_CHR_CON32 (MT6325_PMIC_REG_BASE + 0x0F32)
+#define MT6325_CHR_CON33 (MT6325_PMIC_REG_BASE + 0x0F34)
+#define MT6325_CHR_CON34 (MT6325_PMIC_REG_BASE + 0x0F36)
+#define MT6325_CHR_CON35 (MT6325_PMIC_REG_BASE + 0x0F38)
+#define MT6325_CHR_CON36 (MT6325_PMIC_REG_BASE + 0x0F3A)
+#define MT6325_CHR_CON37 (MT6325_PMIC_REG_BASE + 0x0F3C)
+#define MT6325_CHR_CON38 (MT6325_PMIC_REG_BASE + 0x0F3E)
+#define MT6325_CHR_CON39 (MT6325_PMIC_REG_BASE + 0x0F40)
+#define MT6325_CHR_CON40 (MT6325_PMIC_REG_BASE + 0x0F42)
+#define MT6325_CHR_CON41 (MT6325_PMIC_REG_BASE + 0x0F44)
+#define MT6325_EOSC_CALI_CON0 (MT6325_PMIC_REG_BASE + 0x0F46)
+#define MT6325_EOSC_CALI_CON1 (MT6325_PMIC_REG_BASE + 0x0F48)
+// mask is HEX; shift is Integer
+#define MT6325_THR_DET_DIS_MASK 0x1
+#define MT6325_THR_DET_DIS_SHIFT 0
+#define MT6325_RG_THR_TMODE_MASK 0x1
+#define MT6325_RG_THR_TMODE_SHIFT 1
+#define MT6325_RG_THR_TEMP_SEL_MASK 0x1
+#define MT6325_RG_THR_TEMP_SEL_SHIFT 2
+#define MT6325_RG_STRUP_THR_SEL_MASK 0x3
+#define MT6325_RG_STRUP_THR_SEL_SHIFT 3
+#define MT6325_THR_HWPDN_EN_MASK 0x1
+#define MT6325_THR_HWPDN_EN_SHIFT 5
+#define MT6325_RG_THRDET_SEL_MASK 0x1
+#define MT6325_RG_THRDET_SEL_SHIFT 6
+#define MT6325_RG_STRUP_IREF_TRIM_MASK 0x1F
+#define MT6325_RG_STRUP_IREF_TRIM_SHIFT 0
+#define MT6325_RG_USBDL_EN_MASK 0x1
+#define MT6325_RG_USBDL_EN_SHIFT 0
+#define MT6325_RG_FCHR_KEYDET_EN_MASK 0x1
+#define MT6325_RG_FCHR_KEYDET_EN_SHIFT 1
+#define MT6325_RG_FCHR_PU_EN_MASK 0x1
+#define MT6325_RG_FCHR_PU_EN_SHIFT 2
+#define MT6325_RG_EN_DRVSEL_MASK 0x1
+#define MT6325_RG_EN_DRVSEL_SHIFT 4
+#define MT6325_RG_RSTB_DRV_SEL_MASK 0x1
+#define MT6325_RG_RSTB_DRV_SEL_SHIFT 5
+#define MT6325_RG_VREF_BG_MASK 0x7
+#define MT6325_RG_VREF_BG_SHIFT 12
+#define MT6325_RG_PMU_RSV_MASK 0xF
+#define MT6325_RG_PMU_RSV_SHIFT 0
+#define MT6325_THR_TEST_MASK 0x3
+#define MT6325_THR_TEST_SHIFT 0
+#define MT6325_PMU_THR_DEB_MASK 0x7
+#define MT6325_PMU_THR_DEB_SHIFT 4
+#define MT6325_PMU_THR_STATUS_MASK 0x7
+#define MT6325_PMU_THR_STATUS_SHIFT 8
+#define MT6325_DDUVLO_DEB_EN_MASK 0x1
+#define MT6325_DDUVLO_DEB_EN_SHIFT 0
+#define MT6325_PWRBB_DEB_EN_MASK 0x1
+#define MT6325_PWRBB_DEB_EN_SHIFT 1
+#define MT6325_STRUP_OSC_EN_MASK 0x1
+#define MT6325_STRUP_OSC_EN_SHIFT 2
+#define MT6325_STRUP_OSC_EN_SEL_MASK 0x1
+#define MT6325_STRUP_OSC_EN_SEL_SHIFT 3
+#define MT6325_STRUP_FT_CTRL_MASK 0x3
+#define MT6325_STRUP_FT_CTRL_SHIFT 4
+#define MT6325_STRUP_PWRON_FORCE_MASK 0x1
+#define MT6325_STRUP_PWRON_FORCE_SHIFT 6
+#define MT6325_BIAS_GEN_EN_FORCE_MASK 0x1
+#define MT6325_BIAS_GEN_EN_FORCE_SHIFT 7
+#define MT6325_STRUP_PWRON_MASK 0x1
+#define MT6325_STRUP_PWRON_SHIFT 8
+#define MT6325_STRUP_PWRON_SEL_MASK 0x1
+#define MT6325_STRUP_PWRON_SEL_SHIFT 9
+#define MT6325_BIAS_GEN_EN_MASK 0x1
+#define MT6325_BIAS_GEN_EN_SHIFT 10
+#define MT6325_BIAS_GEN_EN_SEL_MASK 0x1
+#define MT6325_BIAS_GEN_EN_SEL_SHIFT 11
+#define MT6325_RTC_XOSC32_ENB_SW_MASK 0x1
+#define MT6325_RTC_XOSC32_ENB_SW_SHIFT 12
+#define MT6325_RTC_XOSC32_ENB_SEL_MASK 0x1
+#define MT6325_RTC_XOSC32_ENB_SEL_SHIFT 13
+#define MT6325_STRUP_DIG_IO_PG_FORCE_MASK 0x1
+#define MT6325_STRUP_DIG_IO_PG_FORCE_SHIFT 15
+#define MT6325_VDVFS11_PG_H2L_EN_MASK 0x1
+#define MT6325_VDVFS11_PG_H2L_EN_SHIFT 0
+#define MT6325_VDVFS12_PG_H2L_EN_MASK 0x1
+#define MT6325_VDVFS12_PG_H2L_EN_SHIFT 1
+#define MT6325_VCORE1_PG_H2L_EN_MASK 0x1
+#define MT6325_VCORE1_PG_H2L_EN_SHIFT 4
+#define MT6325_VCORE2_PG_H2L_EN_MASK 0x1
+#define MT6325_VCORE2_PG_H2L_EN_SHIFT 5
+#define MT6325_VGPU_PG_H2L_EN_MASK 0x1
+#define MT6325_VGPU_PG_H2L_EN_SHIFT 6
+#define MT6325_VIO18_PG_H2L_EN_MASK 0x1
+#define MT6325_VIO18_PG_H2L_EN_SHIFT 7
+#define MT6325_VAUD28_PG_H2L_EN_MASK 0x1
+#define MT6325_VAUD28_PG_H2L_EN_SHIFT 8
+#define MT6325_VTCXO_PG_H2L_EN_MASK 0x1
+#define MT6325_VTCXO_PG_H2L_EN_SHIFT 9
+#define MT6325_VUSB_PG_H2L_EN_MASK 0x1
+#define MT6325_VUSB_PG_H2L_EN_SHIFT 10
+#define MT6325_VSRAM_DVFS1_PG_H2L_EN_MASK 0x1
+#define MT6325_VSRAM_DVFS1_PG_H2L_EN_SHIFT 11
+#define MT6325_VIO28_PG_H2L_EN_MASK 0x1
+#define MT6325_VIO28_PG_H2L_EN_SHIFT 12
+#define MT6325_VDRAM_PG_H2L_EN_MASK 0x1
+#define MT6325_VDRAM_PG_H2L_EN_SHIFT 13
+#define MT6325_VDVFS11_PG_ENB_MASK 0x1
+#define MT6325_VDVFS11_PG_ENB_SHIFT 0
+#define MT6325_VDVFS12_PG_ENB_MASK 0x1
+#define MT6325_VDVFS12_PG_ENB_SHIFT 1
+#define MT6325_VCORE1_PG_ENB_MASK 0x1
+#define MT6325_VCORE1_PG_ENB_SHIFT 4
+#define MT6325_VCORE2_PG_ENB_MASK 0x1
+#define MT6325_VCORE2_PG_ENB_SHIFT 5
+#define MT6325_VGPU_PG_ENB_MASK 0x1
+#define MT6325_VGPU_PG_ENB_SHIFT 6
+#define MT6325_VIO18_PG_ENB_MASK 0x1
+#define MT6325_VIO18_PG_ENB_SHIFT 7
+#define MT6325_VAUD28_PG_ENB_MASK 0x1
+#define MT6325_VAUD28_PG_ENB_SHIFT 8
+#define MT6325_VTCXO_PG_ENB_MASK 0x1
+#define MT6325_VTCXO_PG_ENB_SHIFT 9
+#define MT6325_VUSB_PG_ENB_MASK 0x1
+#define MT6325_VUSB_PG_ENB_SHIFT 10
+#define MT6325_VSRAM_DVFS1_PG_ENB_MASK 0x1
+#define MT6325_VSRAM_DVFS1_PG_ENB_SHIFT 11
+#define MT6325_VIO28_PG_ENB_MASK 0x1
+#define MT6325_VIO28_PG_ENB_SHIFT 12
+#define MT6325_VDRAM_PG_ENB_MASK 0x1
+#define MT6325_VDRAM_PG_ENB_SHIFT 13
+#define MT6325_RG_EXT_PMIC_EN_PG_ENB_MASK 0x1
+#define MT6325_RG_EXT_PMIC_EN_PG_ENB_SHIFT 14
+#define MT6325_CLR_JUST_RST_MASK 0x1
+#define MT6325_CLR_JUST_RST_SHIFT 4
+#define MT6325_UVLO_L2H_DEB_EN_MASK 0x1
+#define MT6325_UVLO_L2H_DEB_EN_SHIFT 5
+#define MT6325_JUST_PWRKEY_RST_MASK 0x1
+#define MT6325_JUST_PWRKEY_RST_SHIFT 14
+#define MT6325_QI_OSC_EN_MASK 0x1
+#define MT6325_QI_OSC_EN_SHIFT 15
+#define MT6325_STRUP_EXT_PMIC_EN_MASK 0x1
+#define MT6325_STRUP_EXT_PMIC_EN_SHIFT 0
+#define MT6325_STRUP_EXT_PMIC_SEL_MASK 0x1
+#define MT6325_STRUP_EXT_PMIC_SEL_SHIFT 1
+#define MT6325_STRUP_CON8_RSV0_MASK 0x7F
+#define MT6325_STRUP_CON8_RSV0_SHIFT 8
+#define MT6325_QI_EXT_PMIC_EN_MASK 0x1
+#define MT6325_QI_EXT_PMIC_EN_SHIFT 15
+#define MT6325_STRUP_AUXADC_START_SW_MASK 0x1
+#define MT6325_STRUP_AUXADC_START_SW_SHIFT 4
+#define MT6325_STRUP_AUXADC_RSTB_SW_MASK 0x1
+#define MT6325_STRUP_AUXADC_RSTB_SW_SHIFT 5
+#define MT6325_STRUP_AUXADC_START_SEL_MASK 0x1
+#define MT6325_STRUP_AUXADC_START_SEL_SHIFT 6
+#define MT6325_STRUP_AUXADC_RSTB_SEL_MASK 0x1
+#define MT6325_STRUP_AUXADC_RSTB_SEL_SHIFT 7
+#define MT6325_STRUP_PWROFF_SEQ_EN_MASK 0x1
+#define MT6325_STRUP_PWROFF_SEQ_EN_SHIFT 0
+#define MT6325_STRUP_PWROFF_PREOFF_EN_MASK 0x1
+#define MT6325_STRUP_PWROFF_PREOFF_EN_SHIFT 1
+#define MT6325_STRUP_PP_EN_MASK 0x1
+#define MT6325_STRUP_PP_EN_SHIFT 0
+#define MT6325_STRUP_PP_EN_SEL_MASK 0x1
+#define MT6325_STRUP_PP_EN_SEL_SHIFT 1
+#define MT6325_STRUP_DIG0_RSV0_MASK 0xF
+#define MT6325_STRUP_DIG0_RSV0_SHIFT 2
+#define MT6325_STRUP_DIG1_RSV0_MASK 0x1F
+#define MT6325_STRUP_DIG1_RSV0_SHIFT 6
+#define MT6325_RG_UVLO_VTHL_RSV0_MASK 0x1F
+#define MT6325_RG_UVLO_VTHL_RSV0_SHIFT 11
+#define MT6325_RG_BGR_RSV6_MASK 0x1
+#define MT6325_RG_BGR_RSV6_SHIFT 0
+#define MT6325_RG_BGR_RSV5_MASK 0x1
+#define MT6325_RG_BGR_RSV5_SHIFT 1
+#define MT6325_RG_BGR_RSV4_MASK 0x1F
+#define MT6325_RG_BGR_RSV4_SHIFT 5
+#define MT6325_RG_BGR_RSV3_MASK 0x1
+#define MT6325_RG_BGR_RSV3_SHIFT 10
+#define MT6325_RG_BGR_RSV2_MASK 0x7
+#define MT6325_RG_BGR_RSV2_SHIFT 11
+#define MT6325_RG_BGR_RSV1_MASK 0x1
+#define MT6325_RG_BGR_RSV1_SHIFT 14
+#define MT6325_RG_BGR_RSV0_MASK 0x1
+#define MT6325_RG_BGR_RSV0_SHIFT 15
+#define MT6325_RG_STRUP_RSV_MASK 0xFF
+#define MT6325_RG_STRUP_RSV_SHIFT 0
+#define MT6325_RG_EN_SMT_MASK 0x1
+#define MT6325_RG_EN_SMT_SHIFT 0
+#define MT6325_RG_EN_SR_MASK 0x1
+#define MT6325_RG_EN_SR_SHIFT 1
+#define MT6325_RG_EN_E8_MASK 0x1
+#define MT6325_RG_EN_E8_SHIFT 2
+#define MT6325_RG_EN_E4_MASK 0x1
+#define MT6325_RG_EN_E4_SHIFT 3
+#define MT6325_RG_TESTMODE_SWEN_MASK 0x1
+#define MT6325_RG_TESTMODE_SWEN_SHIFT 11
+#define MT6325_STRUP_DIG0_RSV1_MASK 0xF
+#define MT6325_STRUP_DIG0_RSV1_SHIFT 12
+#define MT6325_RG_RSV_SWREG_MASK 0xFFFF
+#define MT6325_RG_RSV_SWREG_SHIFT 0
+#define MT6325_STRUP_PG_STATUS_MASK 0x1
+#define MT6325_STRUP_PG_STATUS_SHIFT 0
+#define MT6325_USBDL_MASK 0x1
+#define MT6325_USBDL_SHIFT 1
+#define MT6325_STRUP_PG_STATUS_CLR_MASK 0x1
+#define MT6325_STRUP_PG_STATUS_CLR_SHIFT 15
+#define MT6325_STRUP_PP_EN_PWROFF_CNT_MASK 0x3FF
+#define MT6325_STRUP_PP_EN_PWROFF_CNT_SHIFT 0
+#define MT6325_STRUP_DIG0_RSV2_MASK 0x3F
+#define MT6325_STRUP_DIG0_RSV2_SHIFT 10
+#define MT6325_STRUP_UVLO_U1U2_SEL_MASK 0x1
+#define MT6325_STRUP_UVLO_U1U2_SEL_SHIFT 0
+#define MT6325_STRUP_UVLO_U1U2_SEL_SWCTRL_MASK 0x1
+#define MT6325_STRUP_UVLO_U1U2_SEL_SWCTRL_SHIFT 1
+#define MT6325_STRUP_LBAT_INT_SEL_CLR_MASK 0x1
+#define MT6325_STRUP_LBAT_INT_SEL_CLR_SHIFT 2
+#define MT6325_STRUP_LBAT_INT_SEL_SWCTRL_MASK 0x1
+#define MT6325_STRUP_LBAT_INT_SEL_SWCTRL_SHIFT 3
+#define MT6325_STRUP_LBAT_INT_SEL_MASK 0x1
+#define MT6325_STRUP_LBAT_INT_SEL_SHIFT 4
+#define MT6325_STRUP_LBAT_IRQ_SET_MASK 0x1
+#define MT6325_STRUP_LBAT_IRQ_SET_SHIFT 0
+#define MT6325_STRUP_LBAT_IRQ_CLR_MASK 0x1
+#define MT6325_STRUP_LBAT_IRQ_CLR_SHIFT 1
+#define MT6325_STRUP_LBAT_IRQ_SWCTRL_MASK 0x1
+#define MT6325_STRUP_LBAT_IRQ_SWCTRL_SHIFT 2
+#define MT6325_RG_UVLO_VSYS_DEB_75K_RPCNT_MAX_MASK 0xF
+#define MT6325_RG_UVLO_VSYS_DEB_75K_RPCNT_MAX_SHIFT 0
+#define MT6325_RG_UVLO_VSYS_DEB_2M_RPCNT_MAX_MASK 0xF
+#define MT6325_RG_UVLO_VSYS_DEB_2M_RPCNT_MAX_SHIFT 4
+#define MT6325_STRUP_AUXADC_RPCNT_MAX_MASK 0x7F
+#define MT6325_STRUP_AUXADC_RPCNT_MAX_SHIFT 0
+#define MT6325_RG_RST_DRVSEL_MASK 0x1
+#define MT6325_RG_RST_DRVSEL_SHIFT 12
+#define MT6325_HWCID_MASK 0xFFFF
+#define MT6325_HWCID_SHIFT 0
+#define MT6325_SWCID_MASK 0xFFFF
+#define MT6325_SWCID_SHIFT 0
+#define MT6325_RG_SRCLKEN_IN0_EN_MASK 0x1
+#define MT6325_RG_SRCLKEN_IN0_EN_SHIFT 0
+#define MT6325_RG_SRCLKEN_IN1_EN_MASK 0x1
+#define MT6325_RG_SRCLKEN_IN1_EN_SHIFT 1
+#define MT6325_RG_OSC_SEL_MASK 0x1
+#define MT6325_RG_OSC_SEL_SHIFT 2
+#define MT6325_RG_SRCLKEN_IN0_HW_MODE_MASK 0x1
+#define MT6325_RG_SRCLKEN_IN0_HW_MODE_SHIFT 4
+#define MT6325_RG_SRCLKEN_IN1_HW_MODE_MASK 0x1
+#define MT6325_RG_SRCLKEN_IN1_HW_MODE_SHIFT 5
+#define MT6325_RG_OSC_SEL_HW_MODE_MASK 0x1
+#define MT6325_RG_OSC_SEL_HW_MODE_SHIFT 6
+#define MT6325_RG_SRCLKEN_IN_SYNC_EN_MASK 0x1
+#define MT6325_RG_SRCLKEN_IN_SYNC_EN_SHIFT 8
+#define MT6325_RG_OSC_EN_AUTO_OFF_MASK 0x1
+#define MT6325_RG_OSC_EN_AUTO_OFF_SHIFT 9
+#define MT6325_TEST_OUT_MASK 0xFF
+#define MT6325_TEST_OUT_SHIFT 0
+#define MT6325_RG_MON_FLAG_SEL_MASK 0xFF
+#define MT6325_RG_MON_FLAG_SEL_SHIFT 0
+#define MT6325_RG_MON_GRP_SEL_MASK 0x1F
+#define MT6325_RG_MON_GRP_SEL_SHIFT 8
+#define MT6325_RG_NANDTREE_MODE_MASK 0x1
+#define MT6325_RG_NANDTREE_MODE_SHIFT 0
+#define MT6325_RG_TEST_AUXADC_MASK 0x1
+#define MT6325_RG_TEST_AUXADC_SHIFT 1
+#define MT6325_RG_EFUSE_MODE_MASK 0x1
+#define MT6325_RG_EFUSE_MODE_SHIFT 2
+#define MT6325_RG_TEST_STRUP_MASK 0x1
+#define MT6325_RG_TEST_STRUP_SHIFT 3
+#define MT6325_TESTMODE_SW_MASK 0x1
+#define MT6325_TESTMODE_SW_SHIFT 0
+#define MT6325_EN_STATUS_VDVFS11_MASK 0x1
+#define MT6325_EN_STATUS_VDVFS11_SHIFT 0
+#define MT6325_EN_STATUS_VDVFS12_MASK 0x1
+#define MT6325_EN_STATUS_VDVFS12_SHIFT 1
+#define MT6325_EN_STATUS_VDRAM_MASK 0x1
+#define MT6325_EN_STATUS_VDRAM_SHIFT 2
+#define MT6325_EN_STATUS_VRF18_0_MASK 0x1
+#define MT6325_EN_STATUS_VRF18_0_SHIFT 3
+#define MT6325_EN_STATUS_VGPU_MASK 0x1
+#define MT6325_EN_STATUS_VGPU_SHIFT 4
+#define MT6325_EN_STATUS_VCORE1_MASK 0x1
+#define MT6325_EN_STATUS_VCORE1_SHIFT 5
+#define MT6325_EN_STATUS_VCORE2_MASK 0x1
+#define MT6325_EN_STATUS_VCORE2_SHIFT 6
+#define MT6325_EN_STATUS_VIO18_MASK 0x1
+#define MT6325_EN_STATUS_VIO18_SHIFT 7
+#define MT6325_EN_STATUS_VPA_MASK 0x1
+#define MT6325_EN_STATUS_VPA_SHIFT 8
+#define MT6325_EN_STATUS_VRTC_MASK 0x1
+#define MT6325_EN_STATUS_VRTC_SHIFT 9
+#define MT6325_EN_STATUS_VTCXO0_MASK 0x1
+#define MT6325_EN_STATUS_VTCXO0_SHIFT 10
+#define MT6325_EN_STATUS_VTCXO1_MASK 0x1
+#define MT6325_EN_STATUS_VTCXO1_SHIFT 11
+#define MT6325_EN_STATUS_VAUD28_MASK 0x1
+#define MT6325_EN_STATUS_VAUD28_SHIFT 12
+#define MT6325_EN_STATUS_VAUXA28_MASK 0x1
+#define MT6325_EN_STATUS_VAUXA28_SHIFT 13
+#define MT6325_EN_STATUS_VCAMA_MASK 0x1
+#define MT6325_EN_STATUS_VCAMA_SHIFT 14
+#define MT6325_EN_STATUS_VIO28_MASK 0x1
+#define MT6325_EN_STATUS_VIO28_SHIFT 15
+#define MT6325_EN_STATUS_VCAM_AF_MASK 0x1
+#define MT6325_EN_STATUS_VCAM_AF_SHIFT 0
+#define MT6325_EN_STATUS_VMC_MASK 0x1
+#define MT6325_EN_STATUS_VMC_SHIFT 1
+#define MT6325_EN_STATUS_VMCH_MASK 0x1
+#define MT6325_EN_STATUS_VMCH_SHIFT 2
+#define MT6325_EN_STATUS_VEMC33_MASK 0x1
+#define MT6325_EN_STATUS_VEMC33_SHIFT 3
+#define MT6325_EN_STATUS_VGP1_MASK 0x1
+#define MT6325_EN_STATUS_VGP1_SHIFT 4
+#define MT6325_EN_STATUS_VEFUSE_MASK 0x1
+#define MT6325_EN_STATUS_VEFUSE_SHIFT 5
+#define MT6325_EN_STATUS_VSIM1_MASK 0x1
+#define MT6325_EN_STATUS_VSIM1_SHIFT 6
+#define MT6325_EN_STATUS_VSIM2_MASK 0x1
+#define MT6325_EN_STATUS_VSIM2_SHIFT 7
+#define MT6325_EN_STATUS_VCN28_MASK 0x1
+#define MT6325_EN_STATUS_VCN28_SHIFT 8
+#define MT6325_EN_STATUS_VMIPI_MASK 0x1
+#define MT6325_EN_STATUS_VMIPI_SHIFT 9
+#define MT6325_EN_STATUS_VIBR_MASK 0x1
+#define MT6325_EN_STATUS_VIBR_SHIFT 10
+#define MT6325_EN_STATUS_VCAMD_MASK 0x1
+#define MT6325_EN_STATUS_VCAMD_SHIFT 11
+#define MT6325_EN_STATUS_VUSB33_MASK 0x1
+#define MT6325_EN_STATUS_VUSB33_SHIFT 12
+#define MT6325_EN_STATUS_VCAM_IO_MASK 0x1
+#define MT6325_EN_STATUS_VCAM_IO_SHIFT 13
+#define MT6325_EN_STATUS_VSRAM_DVFS1_MASK 0x1
+#define MT6325_EN_STATUS_VSRAM_DVFS1_SHIFT 14
+#define MT6325_EN_STATUS_VGP2_MASK 0x1
+#define MT6325_EN_STATUS_VGP2_SHIFT 15
+#define MT6325_EN_STATUS_VGP3_MASK 0x1
+#define MT6325_EN_STATUS_VGP3_SHIFT 0
+#define MT6325_EN_STATUS_VBIASN_MASK 0x1
+#define MT6325_EN_STATUS_VBIASN_SHIFT 1
+#define MT6325_EN_STATUS_VCN33_MASK 0x1
+#define MT6325_EN_STATUS_VCN33_SHIFT 2
+#define MT6325_EN_STATUS_VCN18_MASK 0x1
+#define MT6325_EN_STATUS_VCN18_SHIFT 3
+#define MT6325_EN_STATUS_VRF18_1_MASK 0x1
+#define MT6325_EN_STATUS_VRF18_1_SHIFT 4
+#define MT6325_OC_STATUS_VDVFS11_MASK 0x1
+#define MT6325_OC_STATUS_VDVFS11_SHIFT 0
+#define MT6325_OC_STATUS_VDVFS12_MASK 0x1
+#define MT6325_OC_STATUS_VDVFS12_SHIFT 1
+#define MT6325_OC_STATUS_VDRAM_MASK 0x1
+#define MT6325_OC_STATUS_VDRAM_SHIFT 2
+#define MT6325_OC_STATUS_VRF18_0_MASK 0x1
+#define MT6325_OC_STATUS_VRF18_0_SHIFT 3
+#define MT6325_OC_STATUS_VGPU_MASK 0x1
+#define MT6325_OC_STATUS_VGPU_SHIFT 4
+#define MT6325_OC_STATUS_VCORE1_MASK 0x1
+#define MT6325_OC_STATUS_VCORE1_SHIFT 5
+#define MT6325_OC_STATUS_VCORE2_MASK 0x1
+#define MT6325_OC_STATUS_VCORE2_SHIFT 6
+#define MT6325_OC_STATUS_VIO18_MASK 0x1
+#define MT6325_OC_STATUS_VIO18_SHIFT 7
+#define MT6325_OC_STATUS_VPA_MASK 0x1
+#define MT6325_OC_STATUS_VPA_SHIFT 8
+#define MT6325_OC_STATUS_VTCXO0_MASK 0x1
+#define MT6325_OC_STATUS_VTCXO0_SHIFT 9
+#define MT6325_OC_STATUS_VTCXO1_MASK 0x1
+#define MT6325_OC_STATUS_VTCXO1_SHIFT 10
+#define MT6325_OC_STATUS_VAUD28_MASK 0x1
+#define MT6325_OC_STATUS_VAUD28_SHIFT 11
+#define MT6325_OC_STATUS_VAUXA28_MASK 0x1
+#define MT6325_OC_STATUS_VAUXA28_SHIFT 12
+#define MT6325_OC_STATUS_VCAMA_MASK 0x1
+#define MT6325_OC_STATUS_VCAMA_SHIFT 13
+#define MT6325_OC_STATUS_VIO28_MASK 0x1
+#define MT6325_OC_STATUS_VIO28_SHIFT 14
+#define MT6325_OC_STATUS_VCAM_AF_MASK 0x1
+#define MT6325_OC_STATUS_VCAM_AF_SHIFT 15
+#define MT6325_OC_STATUS_VMC_MASK 0x1
+#define MT6325_OC_STATUS_VMC_SHIFT 0
+#define MT6325_OC_STATUS_VMCH_MASK 0x1
+#define MT6325_OC_STATUS_VMCH_SHIFT 1
+#define MT6325_OC_STATUS_VEMC33_MASK 0x1
+#define MT6325_OC_STATUS_VEMC33_SHIFT 2
+#define MT6325_OC_STATUS_VGP1_MASK 0x1
+#define MT6325_OC_STATUS_VGP1_SHIFT 3
+#define MT6325_OC_STATUS_VEFUSE_MASK 0x1
+#define MT6325_OC_STATUS_VEFUSE_SHIFT 4
+#define MT6325_OC_STATUS_VSIM1_MASK 0x1
+#define MT6325_OC_STATUS_VSIM1_SHIFT 5
+#define MT6325_OC_STATUS_VSIM2_MASK 0x1
+#define MT6325_OC_STATUS_VSIM2_SHIFT 6
+#define MT6325_OC_STATUS_VCN28_MASK 0x1
+#define MT6325_OC_STATUS_VCN28_SHIFT 7
+#define MT6325_OC_STATUS_VMIPI_MASK 0x1
+#define MT6325_OC_STATUS_VMIPI_SHIFT 8
+#define MT6325_OC_STATUS_VIBR_MASK 0x1
+#define MT6325_OC_STATUS_VIBR_SHIFT 10
+#define MT6325_OC_STATUS_VCAMD_MASK 0x1
+#define MT6325_OC_STATUS_VCAMD_SHIFT 11
+#define MT6325_OC_STATUS_VUSB33_MASK 0x1
+#define MT6325_OC_STATUS_VUSB33_SHIFT 12
+#define MT6325_OC_STATUS_VCAM_IO_MASK 0x1
+#define MT6325_OC_STATUS_VCAM_IO_SHIFT 13
+#define MT6325_OC_STATUS_VSRAM_DVFS1_MASK 0x1
+#define MT6325_OC_STATUS_VSRAM_DVFS1_SHIFT 14
+#define MT6325_OC_STATUS_VBIASN_MASK 0x1
+#define MT6325_OC_STATUS_VBIASN_SHIFT 15
+#define MT6325_OC_STATUS_VGP2_MASK 0x1
+#define MT6325_OC_STATUS_VGP2_SHIFT 0
+#define MT6325_OC_STATUS_VGP3_MASK 0x1
+#define MT6325_OC_STATUS_VGP3_SHIFT 1
+#define MT6325_OC_STATUS_VCN33_MASK 0x1
+#define MT6325_OC_STATUS_VCN33_SHIFT 2
+#define MT6325_OC_STATUS_VCN18_MASK 0x1
+#define MT6325_OC_STATUS_VCN18_SHIFT 3
+#define MT6325_OC_STATUS_VRF18_1_MASK 0x1
+#define MT6325_OC_STATUS_VRF18_1_SHIFT 4
+#define MT6325_VTCXO_PG_DEB_MASK 0x1
+#define MT6325_VTCXO_PG_DEB_SHIFT 3
+#define MT6325_VAUD28_PG_DEB_MASK 0x1
+#define MT6325_VAUD28_PG_DEB_SHIFT 4
+#define MT6325_VSRAM_DVFS1_PG_DEB_MASK 0x1
+#define MT6325_VSRAM_DVFS1_PG_DEB_SHIFT 5
+#define MT6325_VIO28_PG_DEB_MASK 0x1
+#define MT6325_VIO28_PG_DEB_SHIFT 6
+#define MT6325_VIO18_PG_DEB_MASK 0x1
+#define MT6325_VIO18_PG_DEB_SHIFT 8
+#define MT6325_VCORE2_PG_DEB_MASK 0x1
+#define MT6325_VCORE2_PG_DEB_SHIFT 9
+#define MT6325_VCORE1_PG_DEB_MASK 0x1
+#define MT6325_VCORE1_PG_DEB_SHIFT 10
+#define MT6325_VGPU_PG_DEB_MASK 0x1
+#define MT6325_VGPU_PG_DEB_SHIFT 11
+#define MT6325_VUSB_PG_DEB_MASK 0x1
+#define MT6325_VUSB_PG_DEB_SHIFT 12
+#define MT6325_VDRAM_PG_DEB_MASK 0x1
+#define MT6325_VDRAM_PG_DEB_SHIFT 13
+#define MT6325_VDVFS12_PG_DEB_MASK 0x1
+#define MT6325_VDVFS12_PG_DEB_SHIFT 14
+#define MT6325_VDVFS11_PG_DEB_MASK 0x1
+#define MT6325_VDVFS11_PG_DEB_SHIFT 15
+#define MT6325_PMU_TEST_MODE_SCAN_MASK 0x1
+#define MT6325_PMU_TEST_MODE_SCAN_SHIFT 0
+#define MT6325_PWRKEY_DEB_MASK 0x1
+#define MT6325_PWRKEY_DEB_SHIFT 1
+#define MT6325_HOMEKEY_DEB_MASK 0x1
+#define MT6325_HOMEKEY_DEB_SHIFT 2
+#define MT6325_RTC_XTAL_DET_DONE_MASK 0x1
+#define MT6325_RTC_XTAL_DET_DONE_SHIFT 6
+#define MT6325_XOSC32_ENB_DET_MASK 0x1
+#define MT6325_XOSC32_ENB_DET_SHIFT 7
+#define MT6325_RTC_XTAL_DET_RSV_MASK 0xF
+#define MT6325_RTC_XTAL_DET_RSV_SHIFT 8
+#define MT6325_RG_PMU_TDSEL_MASK 0x1
+#define MT6325_RG_PMU_TDSEL_SHIFT 0
+#define MT6325_RG_SPI_TDSEL_MASK 0x1
+#define MT6325_RG_SPI_TDSEL_SHIFT 1
+#define MT6325_RG_AUD_TDSEL_MASK 0x1
+#define MT6325_RG_AUD_TDSEL_SHIFT 2
+#define MT6325_RG_E32CAL_TDSEL_MASK 0x1
+#define MT6325_RG_E32CAL_TDSEL_SHIFT 3
+#define MT6325_RG_PMU_RDSEL_MASK 0x1
+#define MT6325_RG_PMU_RDSEL_SHIFT 0
+#define MT6325_RG_SPI_RDSEL_MASK 0x1
+#define MT6325_RG_SPI_RDSEL_SHIFT 1
+#define MT6325_RG_AUD_RDSEL_MASK 0x1
+#define MT6325_RG_AUD_RDSEL_SHIFT 2
+#define MT6325_RG_E32CAL_RDSEL_MASK 0x1
+#define MT6325_RG_E32CAL_RDSEL_SHIFT 3
+#define MT6325_RG_SMT_WDTRSTB_IN_MASK 0x1
+#define MT6325_RG_SMT_WDTRSTB_IN_SHIFT 0
+#define MT6325_RG_SMT_HOMEKEY_MASK 0x1
+#define MT6325_RG_SMT_HOMEKEY_SHIFT 1
+#define MT6325_RG_SMT_SRCLKEN_IN0_MASK 0x1
+#define MT6325_RG_SMT_SRCLKEN_IN0_SHIFT 2
+#define MT6325_RG_SMT_SRCLKEN_IN1_MASK 0x1
+#define MT6325_RG_SMT_SRCLKEN_IN1_SHIFT 3
+#define MT6325_RG_SMT_RTC_32K1V8_0_MASK 0x1
+#define MT6325_RG_SMT_RTC_32K1V8_0_SHIFT 4
+#define MT6325_RG_SMT_RTC_32K1V8_1_MASK 0x1
+#define MT6325_RG_SMT_RTC_32K1V8_1_SHIFT 5
+#define MT6325_RG_SMT_SPI_CLK_MASK 0x1
+#define MT6325_RG_SMT_SPI_CLK_SHIFT 0
+#define MT6325_RG_SMT_SPI_CSN_MASK 0x1
+#define MT6325_RG_SMT_SPI_CSN_SHIFT 1
+#define MT6325_RG_SMT_SPI_MOSI_MASK 0x1
+#define MT6325_RG_SMT_SPI_MOSI_SHIFT 2
+#define MT6325_RG_SMT_SPI_MISO_MASK 0x1
+#define MT6325_RG_SMT_SPI_MISO_SHIFT 3
+#define MT6325_RG_SMT_AUD_CLK_MASK 0x1
+#define MT6325_RG_SMT_AUD_CLK_SHIFT 0
+#define MT6325_RG_SMT_AUD_DAT_MOSI_MASK 0x1
+#define MT6325_RG_SMT_AUD_DAT_MOSI_SHIFT 1
+#define MT6325_RG_SMT_AUD_DAT_MISO_MASK 0x1
+#define MT6325_RG_SMT_AUD_DAT_MISO_SHIFT 2
+#define MT6325_RG_SMT_VOICE_CLK_MISO_MASK 0x1
+#define MT6325_RG_SMT_VOICE_CLK_MISO_SHIFT 3
+#define MT6325_RG_SMT_ENBB_MASK 0x1
+#define MT6325_RG_SMT_ENBB_SHIFT 4
+#define MT6325_RG_SMT_XOSC_EN_MASK 0x1
+#define MT6325_RG_SMT_XOSC_EN_SHIFT 5
+#define MT6325_RG_OCTL_SRCLKEN_IN0_MASK 0xF
+#define MT6325_RG_OCTL_SRCLKEN_IN0_SHIFT 0
+#define MT6325_RG_OCTL_SRCLKEN_IN1_MASK 0xF
+#define MT6325_RG_OCTL_SRCLKEN_IN1_SHIFT 4
+#define MT6325_RG_OCTL_RTC_32K1V8_0_MASK 0xF
+#define MT6325_RG_OCTL_RTC_32K1V8_0_SHIFT 8
+#define MT6325_RG_OCTL_RTC_32K1V8_1_MASK 0xF
+#define MT6325_RG_OCTL_RTC_32K1V8_1_SHIFT 12
+#define MT6325_RG_OCTL_SPI_CLK_MASK 0xF
+#define MT6325_RG_OCTL_SPI_CLK_SHIFT 0
+#define MT6325_RG_OCTL_SPI_CSN_MASK 0xF
+#define MT6325_RG_OCTL_SPI_CSN_SHIFT 4
+#define MT6325_RG_OCTL_SPI_MOSI_MASK 0xF
+#define MT6325_RG_OCTL_SPI_MOSI_SHIFT 8
+#define MT6325_RG_OCTL_SPI_MISO_MASK 0xF
+#define MT6325_RG_OCTL_SPI_MISO_SHIFT 12
+#define MT6325_RG_OCTL_AUD_DAT_MOSI_MASK 0xF
+#define MT6325_RG_OCTL_AUD_DAT_MOSI_SHIFT 0
+#define MT6325_RG_OCTL_AUD_DAT_MISO_MASK 0xF
+#define MT6325_RG_OCTL_AUD_DAT_MISO_SHIFT 4
+#define MT6325_RG_OCTL_AUD_CLK_MASK 0xF
+#define MT6325_RG_OCTL_AUD_CLK_SHIFT 8
+#define MT6325_RG_OCTL_VOICE_CLK_MISO_MASK 0xF
+#define MT6325_RG_OCTL_VOICE_CLK_MISO_SHIFT 12
+#define MT6325_RG_OCTL_HOMEKEY_MASK 0xF
+#define MT6325_RG_OCTL_HOMEKEY_SHIFT 0
+#define MT6325_RG_OCTL_ENBB_MASK 0xF
+#define MT6325_RG_OCTL_ENBB_SHIFT 4
+#define MT6325_RG_OCTL_XOSC_EN_MASK 0xF
+#define MT6325_RG_OCTL_XOSC_EN_SHIFT 8
+#define MT6325_TOP_STATUS_MASK 0xF
+#define MT6325_TOP_STATUS_SHIFT 0
+#define MT6325_TOP_STATUS_SET_MASK 0x3
+#define MT6325_TOP_STATUS_SET_SHIFT 0
+#define MT6325_TOP_STATUS_CLR_MASK 0x3
+#define MT6325_TOP_STATUS_CLR_SHIFT 0
+#define MT6325_RGS_VDVFS11_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VDVFS11_ENPWM_STATUS_SHIFT 0
+#define MT6325_RGS_VDVFS12_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VDVFS12_ENPWM_STATUS_SHIFT 1
+#define MT6325_RGS_VGPU_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VGPU_ENPWM_STATUS_SHIFT 2
+#define MT6325_RGS_VIO18_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VIO18_ENPWM_STATUS_SHIFT 3
+#define MT6325_RGS_VCORE1_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VCORE1_ENPWM_STATUS_SHIFT 4
+#define MT6325_RGS_VCORE2_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VCORE2_ENPWM_STATUS_SHIFT 5
+#define MT6325_RGS_VRF18_0_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VRF18_0_ENPWM_STATUS_SHIFT 6
+#define MT6325_RGS_VDRAM_ENPWM_STATUS_MASK 0x1
+#define MT6325_RGS_VDRAM_ENPWM_STATUS_SHIFT 7
+#define MT6325_RGS_PP_EN_MASK 0x1
+#define MT6325_RGS_PP_EN_SHIFT 8
+#define MT6325_RGS_BC11_ID_FLOAT_MASK 0x1
+#define MT6325_RGS_BC11_ID_FLOAT_SHIFT 9
+#define MT6325_RGS_BC11_ID_A_MASK 0x1
+#define MT6325_RGS_BC11_ID_A_SHIFT 10
+#define MT6325_RGS_BC11_ID_B_MASK 0x1
+#define MT6325_RGS_BC11_ID_B_SHIFT 11
+#define MT6325_RGS_BC11_ID_C_MASK 0x1
+#define MT6325_RGS_BC11_ID_C_SHIFT 12
+#define MT6325_RGS_BC11_ID_GD_MASK 0x1
+#define MT6325_RGS_BC11_ID_GD_SHIFT 13
+#define MT6325_RG_G_SMPS_PD_CK_PDN_MASK 0x1
+#define MT6325_RG_G_SMPS_PD_CK_PDN_SHIFT 0
+#define MT6325_RG_G_SMPS_AUD_CK_PDN_MASK 0x1
+#define MT6325_RG_G_SMPS_AUD_CK_PDN_SHIFT 1
+#define MT6325_RG_G_DRV_2M_CK_PDN_MASK 0x1
+#define MT6325_RG_G_DRV_2M_CK_PDN_SHIFT 2
+#define MT6325_RG_DRV_32K_CK_PDN_MASK 0x1
+#define MT6325_RG_DRV_32K_CK_PDN_SHIFT 3
+#define MT6325_RG_DRV_ISINK0_CK_PDN_MASK 0x1
+#define MT6325_RG_DRV_ISINK0_CK_PDN_SHIFT 4
+#define MT6325_RG_DRV_ISINK1_CK_PDN_MASK 0x1
+#define MT6325_RG_DRV_ISINK1_CK_PDN_SHIFT 5
+#define MT6325_RG_DRV_ISINK2_CK_PDN_MASK 0x1
+#define MT6325_RG_DRV_ISINK2_CK_PDN_SHIFT 6
+#define MT6325_RG_DRV_ISINK3_CK_PDN_MASK 0x1
+#define MT6325_RG_DRV_ISINK3_CK_PDN_SHIFT 7
+#define MT6325_RG_AUXADC_1M_CK_PDN_MASK 0x1
+#define MT6325_RG_AUXADC_1M_CK_PDN_SHIFT 8
+#define MT6325_RG_AUXADC_CK_PDN_MASK 0x1
+#define MT6325_RG_AUXADC_CK_PDN_SHIFT 9
+#define MT6325_RG_AUXADC_32K_CK_PDN_MASK 0x1
+#define MT6325_RG_AUXADC_32K_CK_PDN_SHIFT 10
+#define MT6325_RG_AUDNCP_CK_PDN_MASK 0x1
+#define MT6325_RG_AUDNCP_CK_PDN_SHIFT 11
+#define MT6325_RG_AUDIF_CK_PDN_MASK 0x1
+#define MT6325_RG_AUDIF_CK_PDN_SHIFT 12
+#define MT6325_RG_AUD_CK_PDN_MASK 0x1
+#define MT6325_RG_AUD_CK_PDN_SHIFT 13
+#define MT6325_RG_ZCD13M_CK_PDN_MASK 0x1
+#define MT6325_RG_ZCD13M_CK_PDN_SHIFT 14
+#define MT6325_RG_VOW12M_CK_PDN_MASK 0x1
+#define MT6325_RG_VOW12M_CK_PDN_SHIFT 15
+#define MT6325_TOP_CKPDN_CON0_SET_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON0_SET_SHIFT 0
+#define MT6325_TOP_CKPDN_CON0_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON0_CLR_SHIFT 0
+#define MT6325_RG_RTC_32K_CK_PDN_MASK 0x1
+#define MT6325_RG_RTC_32K_CK_PDN_SHIFT 0
+#define MT6325_RG_RTC_MCLK_PDN_MASK 0x1
+#define MT6325_RG_RTC_MCLK_PDN_SHIFT 1
+#define MT6325_RG_RTC_75K_CK_PDN_MASK 0x1
+#define MT6325_RG_RTC_75K_CK_PDN_SHIFT 2
+#define MT6325_RG_RTCDET_CK_PDN_MASK 0x1
+#define MT6325_RG_RTCDET_CK_PDN_SHIFT 3
+#define MT6325_RG_RTC32K_1V8_0_O_PDN_MASK 0x1
+#define MT6325_RG_RTC32K_1V8_0_O_PDN_SHIFT 4
+#define MT6325_RG_RTC32K_1V8_1_O_PDN_MASK 0x1
+#define MT6325_RG_RTC32K_1V8_1_O_PDN_SHIFT 5
+#define MT6325_RG_RTC_2SEC_OFF_DET_PDN_MASK 0x1
+#define MT6325_RG_RTC_2SEC_OFF_DET_PDN_SHIFT 6
+#define MT6325_RG_FQMTR_CK_PDN_MASK 0x1
+#define MT6325_RG_FQMTR_CK_PDN_SHIFT 7
+#define MT6325_RG_STB_1M_CK_PDN_MASK 0x1
+#define MT6325_RG_STB_1M_CK_PDN_SHIFT 8
+#define MT6325_RG_BUCK_1M_CK_PDN_MASK 0x1
+#define MT6325_RG_BUCK_1M_CK_PDN_SHIFT 9
+#define MT6325_RG_BUCK_18M_CK_PDN_MASK 0x1
+#define MT6325_RG_BUCK_18M_CK_PDN_SHIFT 10
+#define MT6325_RG_PWMOC_6M_CK_PDN_MASK 0x1
+#define MT6325_RG_PWMOC_6M_CK_PDN_SHIFT 11
+#define MT6325_RG_STB_AUD_1M_CK_PDN_MASK 0x1
+#define MT6325_RG_STB_AUD_1M_CK_PDN_SHIFT 12
+#define MT6325_RG_BUCK_AUD_1M_CK_PDN_MASK 0x1
+#define MT6325_RG_BUCK_AUD_1M_CK_PDN_SHIFT 13
+#define MT6325_RG_BUCK_AUD_18M_CK_PDN_MASK 0x1
+#define MT6325_RG_BUCK_AUD_18M_CK_PDN_SHIFT 14
+#define MT6325_RG_PWMOC_AUD_6M_CK_PDN_MASK 0x1
+#define MT6325_RG_PWMOC_AUD_6M_CK_PDN_SHIFT 15
+#define MT6325_TOP_CKPDN_CON1_SET_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON1_SET_SHIFT 0
+#define MT6325_TOP_CKPDN_CON1_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON1_CLR_SHIFT 0
+#define MT6325_RG_SPK_CK_PDN_MASK 0x1
+#define MT6325_RG_SPK_CK_PDN_SHIFT 0
+#define MT6325_RG_SPK_PWM_CK_PDN_MASK 0x1
+#define MT6325_RG_SPK_PWM_CK_PDN_SHIFT 1
+#define MT6325_RG_FGADC_ANA_CK_PDN_MASK 0x1
+#define MT6325_RG_FGADC_ANA_CK_PDN_SHIFT 2
+#define MT6325_RG_FGADC_DIG_CK_PDN_MASK 0x1
+#define MT6325_RG_FGADC_DIG_CK_PDN_SHIFT 3
+#define MT6325_RG_BIF_X72_CK_PDN_MASK 0x1
+#define MT6325_RG_BIF_X72_CK_PDN_SHIFT 4
+#define MT6325_RG_BIF_X4_CK_PDN_MASK 0x1
+#define MT6325_RG_BIF_X4_CK_PDN_SHIFT 5
+#define MT6325_RG_BIF_X1_CK_PDN_MASK 0x1
+#define MT6325_RG_BIF_X1_CK_PDN_SHIFT 6
+#define MT6325_RG_PCHR_32K_CK_PDN_MASK 0x1
+#define MT6325_RG_PCHR_32K_CK_PDN_SHIFT 7
+#define MT6325_RG_AUD18M_CK_PDN_MASK 0x1
+#define MT6325_RG_AUD18M_CK_PDN_SHIFT 8
+#define MT6325_RG_ACCDET_CK_PDN_MASK 0x1
+#define MT6325_RG_ACCDET_CK_PDN_SHIFT 9
+#define MT6325_RG_FQMTR_32K_CK_PDN_MASK 0x1
+#define MT6325_RG_FQMTR_32K_CK_PDN_SHIFT 10
+#define MT6325_RG_INTRP_CK_PDN_MASK 0x1
+#define MT6325_RG_INTRP_CK_PDN_SHIFT 11
+#define MT6325_RG_RTC_26M_CK_PDN_MASK 0x1
+#define MT6325_RG_RTC_26M_CK_PDN_SHIFT 12
+#define MT6325_RG_RTC_EOSC32_CK_PDN_MASK 0x1
+#define MT6325_RG_RTC_EOSC32_CK_PDN_SHIFT 13
+#define MT6325_RG_TRIM_75K_CK_PDN_MASK 0x1
+#define MT6325_RG_TRIM_75K_CK_PDN_SHIFT 14
+#define MT6325_RG_STRUP_LBAT_SEL_CK_PDN_MASK 0x1
+#define MT6325_RG_STRUP_LBAT_SEL_CK_PDN_SHIFT 15
+#define MT6325_TOP_CKPDN_CON2_SET_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON2_SET_SHIFT 0
+#define MT6325_TOP_CKPDN_CON2_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON2_CLR_SHIFT 0
+#define MT6325_RG_STRUP_75K_CK_PDN_MASK 0x1
+#define MT6325_RG_STRUP_75K_CK_PDN_SHIFT 0
+#define MT6325_RG_STRUP_32K_CK_PDN_MASK 0x1
+#define MT6325_RG_STRUP_32K_CK_PDN_SHIFT 1
+#define MT6325_RG_EFUSE_CK_PDN_MASK 0x1
+#define MT6325_RG_EFUSE_CK_PDN_SHIFT 2
+#define MT6325_RG_SMPS_CK_DIV_PDN_MASK 0x1
+#define MT6325_RG_SMPS_CK_DIV_PDN_SHIFT 3
+#define MT6325_RG_SPI_CK_PDN_MASK 0x1
+#define MT6325_RG_SPI_CK_PDN_SHIFT 4
+#define MT6325_RG_BGR_TEST_CK_PDN_MASK 0x1
+#define MT6325_RG_BGR_TEST_CK_PDN_SHIFT 5
+#define MT6325_RG_FGADC_FT_CK_PDN_MASK 0x1
+#define MT6325_RG_FGADC_FT_CK_PDN_SHIFT 6
+#define MT6325_RG_PCHR_TEST_CK_PDN_MASK 0x1
+#define MT6325_RG_PCHR_TEST_CK_PDN_SHIFT 7
+#define MT6325_RG_BUCK_32K_CK_PDN_MASK 0x1
+#define MT6325_RG_BUCK_32K_CK_PDN_SHIFT 8
+#define MT6325_RG_BUCK_ANA_CK_PDN_MASK 0x1
+#define MT6325_RG_BUCK_ANA_CK_PDN_SHIFT 9
+#define MT6325_RG_EOSC_CALI_TEST_CK_PDN_MASK 0x1
+#define MT6325_RG_EOSC_CALI_TEST_CK_PDN_SHIFT 10
+#define MT6325_TOP_CKPDN_CON3_RSV_MASK 0x1F
+#define MT6325_TOP_CKPDN_CON3_RSV_SHIFT 11
+#define MT6325_TOP_CKPDN_CON3_SET_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON3_SET_SHIFT 0
+#define MT6325_TOP_CKPDN_CON3_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKPDN_CON3_CLR_SHIFT 0
+#define MT6325_RG_AUDIF_CK_CKSEL_MASK 0x1
+#define MT6325_RG_AUDIF_CK_CKSEL_SHIFT 0
+#define MT6325_RG_AUD_CK_CKSEL_MASK 0x1
+#define MT6325_RG_AUD_CK_CKSEL_SHIFT 1
+#define MT6325_RG_DRV_ISINK0_CK_CKSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK0_CK_CKSEL_SHIFT 4
+#define MT6325_RG_DRV_ISINK1_CK_CKSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK1_CK_CKSEL_SHIFT 5
+#define MT6325_RG_DRV_ISINK2_CK_CKSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK2_CK_CKSEL_SHIFT 6
+#define MT6325_RG_DRV_ISINK3_CK_CKSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK3_CK_CKSEL_SHIFT 7
+#define MT6325_RG_FQMTR_CK_CKSEL_MASK 0x7
+#define MT6325_RG_FQMTR_CK_CKSEL_SHIFT 8
+#define MT6325_RG_75K_32K_SEL_MASK 0x1
+#define MT6325_RG_75K_32K_SEL_SHIFT 11
+#define MT6325_RG_AUXADC_CK_CKSEL_MASK 0x1
+#define MT6325_RG_AUXADC_CK_CKSEL_SHIFT 12
+#define MT6325_TOP_CKSEL_CON0_RSV_MASK 0x1
+#define MT6325_TOP_CKSEL_CON0_RSV_SHIFT 13
+#define MT6325_RG_OSC_SEL_HW_SRC_SEL_MASK 0x3
+#define MT6325_RG_OSC_SEL_HW_SRC_SEL_SHIFT 14
+#define MT6325_TOP_CKSEL_CON_SET_MASK 0xFFFF
+#define MT6325_TOP_CKSEL_CON_SET_SHIFT 0
+#define MT6325_TOP_CKSEL_CON_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKSEL_CON_CLR_SHIFT 0
+#define MT6325_RG_STRUP_75K_CK_CKSEL_MASK 0x3
+#define MT6325_RG_STRUP_75K_CK_CKSEL_SHIFT 0
+#define MT6325_RG_BGR_TEST_CK_CKSEL_MASK 0x1
+#define MT6325_RG_BGR_TEST_CK_CKSEL_SHIFT 2
+#define MT6325_RG_PCHR_TEST_CK_CKSEL_MASK 0x1
+#define MT6325_RG_PCHR_TEST_CK_CKSEL_SHIFT 3
+#define MT6325_RG_FGADC_ANA_CK_CKSEL_MASK 0x1
+#define MT6325_RG_FGADC_ANA_CK_CKSEL_SHIFT 4
+#define MT6325_TOP_CKSEL_CON1_RSV_MASK 0x3
+#define MT6325_TOP_CKSEL_CON1_RSV_SHIFT 8
+#define MT6325_TOP_CKSEL_CON1_SET_MASK 0xFFFF
+#define MT6325_TOP_CKSEL_CON1_SET_SHIFT 0
+#define MT6325_TOP_CKSEL_CON1_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKSEL_CON1_CLR_SHIFT 0
+#define MT6325_RG_SRCVOLTEN_SW_MASK 0x1
+#define MT6325_RG_SRCVOLTEN_SW_SHIFT 0
+#define MT6325_RG_VOWEN_SW_MASK 0x1
+#define MT6325_RG_VOWEN_SW_SHIFT 1
+#define MT6325_RG_BUCK_OSC_SEL_SW_MASK 0x1
+#define MT6325_RG_BUCK_OSC_SEL_SW_SHIFT 2
+#define MT6325_RG_VCORE2_OSC_SEL_SW_MASK 0x1
+#define MT6325_RG_VCORE2_OSC_SEL_SW_SHIFT 3
+#define MT6325_RG_SRCVOLTEN_MODE_MASK 0x1
+#define MT6325_RG_SRCVOLTEN_MODE_SHIFT 4
+#define MT6325_RG_VOWEN_MODE_MASK 0x1
+#define MT6325_RG_VOWEN_MODE_SHIFT 5
+#define MT6325_RG_BUCK_OSC_SEL_MODE_MASK 0x1
+#define MT6325_RG_BUCK_OSC_SEL_MODE_SHIFT 6
+#define MT6325_RG_VCORE2_OSC_SEL_MODE_MASK 0x1
+#define MT6325_RG_VCORE2_OSC_SEL_MODE_SHIFT 7
+#define MT6325_TOP_CKSEL_CON2_RSV_MASK 0x3
+#define MT6325_TOP_CKSEL_CON2_RSV_SHIFT 8
+#define MT6325_TOP_CKSEL_CON2_SET_MASK 0xFFFF
+#define MT6325_TOP_CKSEL_CON2_SET_SHIFT 0
+#define MT6325_TOP_CKSEL_CON2_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKSEL_CON2_CLR_SHIFT 0
+#define MT6325_RG_STRUP_LBAT_SEL_CK_DIVSEL_MASK 0x3
+#define MT6325_RG_STRUP_LBAT_SEL_CK_DIVSEL_SHIFT 0
+#define MT6325_TOP_CKDIVSEL_CON_RSV_MASK 0x3
+#define MT6325_TOP_CKDIVSEL_CON_RSV_SHIFT 2
+#define MT6325_RG_BIF_X4_CK_DIVSEL_MASK 0x7
+#define MT6325_RG_BIF_X4_CK_DIVSEL_SHIFT 4
+#define MT6325_RG_REG_CK_DIVSEL_MASK 0x3
+#define MT6325_RG_REG_CK_DIVSEL_SHIFT 8
+#define MT6325_RG_BUCK_18M_CK_DIVSEL_MASK 0x1
+#define MT6325_RG_BUCK_18M_CK_DIVSEL_SHIFT 10
+#define MT6325_RG_AUXADC_SMPS_CK_DIVSEL_MASK 0x1
+#define MT6325_RG_AUXADC_SMPS_CK_DIVSEL_SHIFT 11
+#define MT6325_RG_SPK_CK_DIVSEL_MASK 0x3
+#define MT6325_RG_SPK_CK_DIVSEL_SHIFT 12
+#define MT6325_RG_SPK_PWM_CK_DIVSEL_MASK 0x3
+#define MT6325_RG_SPK_PWM_CK_DIVSEL_SHIFT 14
+#define MT6325_TOP_CKDIVSEL_CON1_SET_MASK 0xFFFF
+#define MT6325_TOP_CKDIVSEL_CON1_SET_SHIFT 0
+#define MT6325_TOP_CKDIVSEL_CON1_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKDIVSEL_CON1_CLR_SHIFT 0
+#define MT6325_RG_G_SMPS_PD_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_G_SMPS_PD_CK_PDN_HWEN_SHIFT 0
+#define MT6325_RG_G_SMPS_AUD_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_G_SMPS_AUD_CK_PDN_HWEN_SHIFT 1
+#define MT6325_RG_G_DRV_2M_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_G_DRV_2M_CK_PDN_HWEN_SHIFT 2
+#define MT6325_RG_AUXADC_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_AUXADC_CK_PDN_HWEN_SHIFT 3
+#define MT6325_RG_BUCK_1M_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_BUCK_1M_CK_PDN_HWEN_SHIFT 4
+#define MT6325_RG_BUCK_AUD_1M_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_BUCK_AUD_1M_CK_PDN_HWEN_SHIFT 5
+#define MT6325_RG_EFUSE_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_EFUSE_CK_PDN_HWEN_SHIFT 6
+#define MT6325_RG_RTC_26M_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_RTC_26M_CK_PDN_HWEN_SHIFT 7
+#define MT6325_RG_AUD18M_CK_PDN_HWEN_MASK 0x1
+#define MT6325_RG_AUD18M_CK_PDN_HWEN_SHIFT 8
+#define MT6325_RG_AUXADC_SMPS_CK_DIVSEL_HWEN_MASK 0x1
+#define MT6325_RG_AUXADC_SMPS_CK_DIVSEL_HWEN_SHIFT 9
+#define MT6325_RG_AUXADC_CK_CKSEL_HWEN_MASK 0x1
+#define MT6325_RG_AUXADC_CK_CKSEL_HWEN_SHIFT 10
+#define MT6325_TOP_CKHWEN_CON_RSV_MASK 0x1F
+#define MT6325_TOP_CKHWEN_CON_RSV_SHIFT 11
+#define MT6325_TOP_CKHWEN_CON_SET_MASK 0xFFFF
+#define MT6325_TOP_CKHWEN_CON_SET_SHIFT 0
+#define MT6325_TOP_CKHWEN_CON_CLR_MASK 0xFFFF
+#define MT6325_TOP_CKHWEN_CON_CLR_SHIFT 0
+#define MT6325_RG_PMU75K_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_PMU75K_CK_TST_DIS_SHIFT 0
+#define MT6325_RG_SMPS_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_SMPS_CK_TST_DIS_SHIFT 1
+#define MT6325_RG_AUD26M_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_AUD26M_CK_TST_DIS_SHIFT 2
+#define MT6325_RG_VOW12M_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_VOW12M_CK_TST_DIS_SHIFT 3
+#define MT6325_RG_RTC32K_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_RTC32K_CK_TST_DIS_SHIFT 4
+#define MT6325_RG_SPK_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_SPK_CK_TST_DIS_SHIFT 5
+#define MT6325_RG_FG_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_FG_CK_TST_DIS_SHIFT 6
+#define MT6325_RG_RTC26M_CK_TST_DIS_MASK 0x1
+#define MT6325_RG_RTC26M_CK_TST_DIS_SHIFT 7
+#define MT6325_TOP_CKTST_CON0_RSV_MASK 0x7F
+#define MT6325_TOP_CKTST_CON0_RSV_SHIFT 8
+#define MT6325_RG_BUCK_ANA_AUTO_OFF_DIS_MASK 0x1
+#define MT6325_RG_BUCK_ANA_AUTO_OFF_DIS_SHIFT 15
+#define MT6325_RG_DRV_ISINK0_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK0_CK_TSTSEL_SHIFT 0
+#define MT6325_RG_DRV_ISINK1_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK1_CK_TSTSEL_SHIFT 1
+#define MT6325_RG_DRV_ISINK2_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK2_CK_TSTSEL_SHIFT 2
+#define MT6325_RG_DRV_ISINK3_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_DRV_ISINK3_CK_TSTSEL_SHIFT 3
+#define MT6325_RG_FQMTR_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_FQMTR_CK_TSTSEL_SHIFT 4
+#define MT6325_RG_RTCDET_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_RTCDET_CK_TSTSEL_SHIFT 5
+#define MT6325_RG_PMU75K_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_PMU75K_CK_TSTSEL_SHIFT 6
+#define MT6325_RG_SMPS_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_SMPS_CK_TSTSEL_SHIFT 7
+#define MT6325_RG_AUD26M_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_AUD26M_CK_TSTSEL_SHIFT 8
+#define MT6325_RG_VOW12M_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_VOW12M_CK_TSTSEL_SHIFT 9
+#define MT6325_RG_AUDIF_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_AUDIF_CK_TSTSEL_SHIFT 10
+#define MT6325_RG_AUD_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_AUD_CK_TSTSEL_SHIFT 11
+#define MT6325_RG_STRUP_75K_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_STRUP_75K_CK_TSTSEL_SHIFT 12
+#define MT6325_RG_RTC32K_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_RTC32K_CK_TSTSEL_SHIFT 13
+#define MT6325_RG_PCHR_TEST_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_PCHR_TEST_CK_TSTSEL_SHIFT 14
+#define MT6325_RG_BGR_TEST_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_BGR_TEST_CK_TSTSEL_SHIFT 15
+#define MT6325_RG_FG_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_FG_CK_TSTSEL_SHIFT 0
+#define MT6325_RG_FGADC_ANA_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_FGADC_ANA_CK_TSTSEL_SHIFT 1
+#define MT6325_RG_SPK_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_SPK_CK_TSTSEL_SHIFT 2
+#define MT6325_RG_RTC26M_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_RTC26M_CK_TSTSEL_SHIFT 3
+#define MT6325_RG_RTC_EOSC32_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_RTC_EOSC32_CK_TSTSEL_SHIFT 4
+#define MT6325_RG_EOSC_CALI_TEST_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_EOSC_CALI_TEST_CK_TSTSEL_SHIFT 5
+#define MT6325_RG_AUXADC_CK_TSTSEL_MASK 0x1
+#define MT6325_RG_AUXADC_CK_TSTSEL_SHIFT 6
+#define MT6325_TOP_CKTST_CON2_RSV_MASK 0xF
+#define MT6325_TOP_CKTST_CON2_RSV_SHIFT 7
+#define MT6325_RG_CLKSQ_EN_AUD_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_AUD_SHIFT 0
+#define MT6325_RG_CLKSQ_EN_FQR_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_FQR_SHIFT 1
+#define MT6325_RG_CLKSQ_EN_AUX_AP_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_AUX_AP_SHIFT 2
+#define MT6325_RG_CLKSQ_EN_AUX_MD_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_AUX_MD_SHIFT 3
+#define MT6325_RG_CLKSQ_EN_AUX_GPS_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_AUX_GPS_SHIFT 4
+#define MT6325_RG_CLKSQ_EN_AUX_RSV_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_AUX_RSV_SHIFT 5
+#define MT6325_RG_CLKSQ_EN_AUX_AP_MODE_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_AUX_AP_MODE_SHIFT 8
+#define MT6325_RG_CLKSQ_EN_AUX_MD_MODE_MASK 0x1
+#define MT6325_RG_CLKSQ_EN_AUX_MD_MODE_SHIFT 9
+#define MT6325_TOP_CLKSQ_RSV_MASK 0x1F
+#define MT6325_TOP_CLKSQ_RSV_SHIFT 10
+#define MT6325_DA_CLKSQ_EN_VA28_MASK 0x1
+#define MT6325_DA_CLKSQ_EN_VA28_SHIFT 15
+#define MT6325_TOP_CLKSQ_SET_MASK 0xFFFF
+#define MT6325_TOP_CLKSQ_SET_SHIFT 0
+#define MT6325_TOP_CLKSQ_CLR_MASK 0xFFFF
+#define MT6325_TOP_CLKSQ_CLR_SHIFT 0
+#define MT6325_RG_CLKSQ_RTC_EN_MASK 0x1
+#define MT6325_RG_CLKSQ_RTC_EN_SHIFT 0
+#define MT6325_RG_CLKSQ_RTC_EN_HW_MODE_MASK 0x1
+#define MT6325_RG_CLKSQ_RTC_EN_HW_MODE_SHIFT 1
+#define MT6325_TOP_CLKSQ_RTC_RSV0_MASK 0xF
+#define MT6325_TOP_CLKSQ_RTC_RSV0_SHIFT 2
+#define MT6325_RG_ENBB_SEL_MASK 0x1
+#define MT6325_RG_ENBB_SEL_SHIFT 8
+#define MT6325_RG_XOSC_EN_SEL_MASK 0x1
+#define MT6325_RG_XOSC_EN_SEL_SHIFT 9
+#define MT6325_TOP_CLKSQ_RTC_RSV1_MASK 0x3
+#define MT6325_TOP_CLKSQ_RTC_RSV1_SHIFT 10
+#define MT6325_DA_CLKSQ_EN_VDIG18_MASK 0x1
+#define MT6325_DA_CLKSQ_EN_VDIG18_SHIFT 15
+#define MT6325_TOP_CLKSQ_RTC_SET_MASK 0xFFFF
+#define MT6325_TOP_CLKSQ_RTC_SET_SHIFT 0
+#define MT6325_TOP_CLKSQ_RTC_CLR_MASK 0xFFFF
+#define MT6325_TOP_CLKSQ_RTC_CLR_SHIFT 0
+#define MT6325_OSC_75K_TRIM_MASK 0x1F
+#define MT6325_OSC_75K_TRIM_SHIFT 0
+#define MT6325_RG_OSC_75K_TRIM_EN_MASK 0x1
+#define MT6325_RG_OSC_75K_TRIM_EN_SHIFT 5
+#define MT6325_RG_OSC_75K_TRIM_RATE_MASK 0x3
+#define MT6325_RG_OSC_75K_TRIM_RATE_SHIFT 6
+#define MT6325_RG_OSC_75K_TRIM_MASK 0x1F
+#define MT6325_RG_OSC_75K_TRIM_SHIFT 8
+#define MT6325_RG_EFUSE_MAN_RST_MASK 0x1
+#define MT6325_RG_EFUSE_MAN_RST_SHIFT 0
+#define MT6325_RG_AUXADC_RST_MASK 0x1
+#define MT6325_RG_AUXADC_RST_SHIFT 1
+#define MT6325_RG_AUXADC_REG_RST_MASK 0x1
+#define MT6325_RG_AUXADC_REG_RST_SHIFT 2
+#define MT6325_RG_AUDIO_RST_MASK 0x1
+#define MT6325_RG_AUDIO_RST_SHIFT 3
+#define MT6325_RG_ACCDET_RST_MASK 0x1
+#define MT6325_RG_ACCDET_RST_SHIFT 4
+#define MT6325_RG_BIF_RST_MASK 0x1
+#define MT6325_RG_BIF_RST_SHIFT 5
+#define MT6325_RG_DRIVER_RST_MASK 0x1
+#define MT6325_RG_DRIVER_RST_SHIFT 6
+#define MT6325_RG_FGADC_RST_MASK 0x1
+#define MT6325_RG_FGADC_RST_SHIFT 7
+#define MT6325_RG_FQMTR_RST_MASK 0x1
+#define MT6325_RG_FQMTR_RST_SHIFT 8
+#define MT6325_RG_RTC_RST_MASK 0x1
+#define MT6325_RG_RTC_RST_SHIFT 9
+#define MT6325_RG_SPK_RST_MASK 0x1
+#define MT6325_RG_SPK_RST_SHIFT 10
+#define MT6325_RG_CHRWDT_RST_MASK 0x1
+#define MT6325_RG_CHRWDT_RST_SHIFT 11
+#define MT6325_RG_ZCD_RST_MASK 0x1
+#define MT6325_RG_ZCD_RST_SHIFT 12
+#define MT6325_RG_AUDNCP_RST_MASK 0x1
+#define MT6325_RG_AUDNCP_RST_SHIFT 13
+#define MT6325_RG_CLK_TRIM_RST_MASK 0x1
+#define MT6325_RG_CLK_TRIM_RST_SHIFT 14
+#define MT6325_TOP_RST_CON0_RSV_MASK 0x1
+#define MT6325_TOP_RST_CON0_RSV_SHIFT 15
+#define MT6325_TOP_RST_CON_SET_MASK 0xFFFF
+#define MT6325_TOP_RST_CON_SET_SHIFT 0
+#define MT6325_TOP_RST_CON_CLR_MASK 0xFFFF
+#define MT6325_TOP_RST_CON_CLR_SHIFT 0
+#define MT6325_RG_CHR_LDO_DET_MODE_MASK 0x1
+#define MT6325_RG_CHR_LDO_DET_MODE_SHIFT 0
+#define MT6325_RG_CHR_LDO_DET_SW_MASK 0x1
+#define MT6325_RG_CHR_LDO_DET_SW_SHIFT 1
+#define MT6325_RG_CHRWDT_FLAG_MODE_MASK 0x1
+#define MT6325_RG_CHRWDT_FLAG_MODE_SHIFT 2
+#define MT6325_RG_CHRWDT_FLAG_SW_MASK 0x1
+#define MT6325_RG_CHRWDT_FLAG_SW_SHIFT 3
+#define MT6325_TOP_RST_CON1_RSV_MASK 0xF
+#define MT6325_TOP_RST_CON1_RSV_SHIFT 4
+#define MT6325_RG_WDTRSTB_EN_MASK 0x1
+#define MT6325_RG_WDTRSTB_EN_SHIFT 0
+#define MT6325_RG_WDTRSTB_MODE_MASK 0x1
+#define MT6325_RG_WDTRSTB_MODE_SHIFT 1
+#define MT6325_WDTRSTB_STATUS_MASK 0x1
+#define MT6325_WDTRSTB_STATUS_SHIFT 2
+#define MT6325_WDTRSTB_STATUS_CLR_MASK 0x1
+#define MT6325_WDTRSTB_STATUS_CLR_SHIFT 3
+#define MT6325_RG_WDTRSTB_FB_EN_MASK 0x1
+#define MT6325_RG_WDTRSTB_FB_EN_SHIFT 4
+#define MT6325_RG_HOMEKEY_RST_EN_MASK 0x1
+#define MT6325_RG_HOMEKEY_RST_EN_SHIFT 8
+#define MT6325_RG_PWRKEY_RST_EN_MASK 0x1
+#define MT6325_RG_PWRKEY_RST_EN_SHIFT 9
+#define MT6325_RG_PWRRST_TMR_DIS_MASK 0x1
+#define MT6325_RG_PWRRST_TMR_DIS_SHIFT 10
+#define MT6325_RG_PWRKEY_RST_TD_MASK 0x3
+#define MT6325_RG_PWRKEY_RST_TD_SHIFT 12
+#define MT6325_TOP_RST_MISC_SET_MASK 0xFFFF
+#define MT6325_TOP_RST_MISC_SET_SHIFT 0
+#define MT6325_TOP_RST_MISC_CLR_MASK 0xFFFF
+#define MT6325_TOP_RST_MISC_CLR_SHIFT 0
+#define MT6325_VPWRIN_RSTB_STATUS_MASK 0x1
+#define MT6325_VPWRIN_RSTB_STATUS_SHIFT 0
+#define MT6325_DDLO_RSTB_STATUS_MASK 0x1
+#define MT6325_DDLO_RSTB_STATUS_SHIFT 1
+#define MT6325_UVLO_RSTB_STATUS_MASK 0x1
+#define MT6325_UVLO_RSTB_STATUS_SHIFT 2
+#define MT6325_RTC_DDLO_RSTB_STATUS_MASK 0x1
+#define MT6325_RTC_DDLO_RSTB_STATUS_SHIFT 3
+#define MT6325_CHRWDT_REG_RSTB_STATUS_MASK 0x1
+#define MT6325_CHRWDT_REG_RSTB_STATUS_SHIFT 4
+#define MT6325_CHRDET_REG_RSTB_STATUS_MASK 0x1
+#define MT6325_CHRDET_REG_RSTB_STATUS_SHIFT 5
+#define MT6325_TOP_RST_STATUS_RSV_MASK 0x3
+#define MT6325_TOP_RST_STATUS_RSV_SHIFT 6
+#define MT6325_TOP_RST_STATUS_SET_MASK 0xFFFF
+#define MT6325_TOP_RST_STATUS_SET_SHIFT 0
+#define MT6325_TOP_RST_STATUS_CLR_MASK 0xFFFF
+#define MT6325_TOP_RST_STATUS_CLR_SHIFT 0
+#define MT6325_RG_INT_EN_PWRKEY_MASK 0x1
+#define MT6325_RG_INT_EN_PWRKEY_SHIFT 0
+#define MT6325_RG_INT_EN_HOMEKEY_MASK 0x1
+#define MT6325_RG_INT_EN_HOMEKEY_SHIFT 1
+#define MT6325_RG_INT_EN_PWRKEY_R_MASK 0x1
+#define MT6325_RG_INT_EN_PWRKEY_R_SHIFT 2
+#define MT6325_RG_INT_EN_HOMEKEY_R_MASK 0x1
+#define MT6325_RG_INT_EN_HOMEKEY_R_SHIFT 3
+#define MT6325_RG_INT_EN_THR_H_MASK 0x1
+#define MT6325_RG_INT_EN_THR_H_SHIFT 4
+#define MT6325_RG_INT_EN_THR_L_MASK 0x1
+#define MT6325_RG_INT_EN_THR_L_SHIFT 5
+#define MT6325_RG_INT_EN_BAT_H_MASK 0x1
+#define MT6325_RG_INT_EN_BAT_H_SHIFT 6
+#define MT6325_RG_INT_EN_BAT_L_MASK 0x1
+#define MT6325_RG_INT_EN_BAT_L_SHIFT 7
+#define MT6325_RG_INT_EN_BIF_MASK 0x1
+#define MT6325_RG_INT_EN_BIF_SHIFT 8
+#define MT6325_RG_INT_EN_RTC_MASK 0x1
+#define MT6325_RG_INT_EN_RTC_SHIFT 9
+#define MT6325_RG_INT_EN_AUDIO_MASK 0x1
+#define MT6325_RG_INT_EN_AUDIO_SHIFT 10
+#define MT6325_RG_INT_EN_VOW_MASK 0x1
+#define MT6325_RG_INT_EN_VOW_SHIFT 11
+#define MT6325_RG_INT_EN_ACCDET_MASK 0x1
+#define MT6325_RG_INT_EN_ACCDET_SHIFT 12
+#define MT6325_RG_INT_EN_ACCDET_EINT_MASK 0x1
+#define MT6325_RG_INT_EN_ACCDET_EINT_SHIFT 13
+#define MT6325_RG_INT_EN_ACCDET_NEGV_MASK 0x1
+#define MT6325_RG_INT_EN_ACCDET_NEGV_SHIFT 14
+#define MT6325_RG_INT_EN_NI_LBAT_INT_MASK 0x1
+#define MT6325_RG_INT_EN_NI_LBAT_INT_SHIFT 15
+#define MT6325_INT_CON0_SET_MASK 0xFFFF
+#define MT6325_INT_CON0_SET_SHIFT 0
+#define MT6325_INT_CON0_CLR_MASK 0xFFFF
+#define MT6325_INT_CON0_CLR_SHIFT 0
+#define MT6325_RG_INT_EN_VDVFS11_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VDVFS11_OC_SHIFT 0
+#define MT6325_RG_INT_EN_VDVFS12_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VDVFS12_OC_SHIFT 1
+#define MT6325_RG_INT_EN_VRF18_0_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VRF18_0_OC_SHIFT 2
+#define MT6325_RG_INT_EN_VDRAM_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VDRAM_OC_SHIFT 3
+#define MT6325_RG_INT_EN_VGPU_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VGPU_OC_SHIFT 4
+#define MT6325_RG_INT_EN_VCORE1_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VCORE1_OC_SHIFT 5
+#define MT6325_RG_INT_EN_VCORE2_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VCORE2_OC_SHIFT 6
+#define MT6325_RG_INT_EN_VIO18_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VIO18_OC_SHIFT 7
+#define MT6325_RG_INT_EN_VPA_OC_MASK 0x1
+#define MT6325_RG_INT_EN_VPA_OC_SHIFT 8
+#define MT6325_RG_INT_EN_LDO_OC_MASK 0x1
+#define MT6325_RG_INT_EN_LDO_OC_SHIFT 9
+#define MT6325_RG_INT_EN_BAT2_H_MASK 0x1
+#define MT6325_RG_INT_EN_BAT2_H_SHIFT 10
+#define MT6325_RG_INT_EN_BAT2_L_MASK 0x1
+#define MT6325_RG_INT_EN_BAT2_L_SHIFT 11
+#define MT6325_RG_INT_EN_VISMPS0_H_MASK 0x1
+#define MT6325_RG_INT_EN_VISMPS0_H_SHIFT 12
+#define MT6325_RG_INT_EN_VISMPS0_L_MASK 0x1
+#define MT6325_RG_INT_EN_VISMPS0_L_SHIFT 13
+#define MT6325_RG_INT_EN_AUXADC_IMP_MASK 0x1
+#define MT6325_RG_INT_EN_AUXADC_IMP_SHIFT 14
+#define MT6325_INT_CON1_SET_MASK 0xFFFF
+#define MT6325_INT_CON1_SET_SHIFT 0
+#define MT6325_INT_CON1_CLR_MASK 0xFFFF
+#define MT6325_INT_CON1_CLR_SHIFT 0
+#define MT6325_RG_INT_EN_OV_MASK 0x1
+#define MT6325_RG_INT_EN_OV_SHIFT 0
+#define MT6325_RG_INT_EN_BVALID_DET_MASK 0x1
+#define MT6325_RG_INT_EN_BVALID_DET_SHIFT 1
+#define MT6325_RG_INT_EN_VBATON_UNDET_MASK 0x1
+#define MT6325_RG_INT_EN_VBATON_UNDET_SHIFT 2
+#define MT6325_RG_INT_EN_WATCHDOG_MASK 0x1
+#define MT6325_RG_INT_EN_WATCHDOG_SHIFT 3
+#define MT6325_RG_INT_EN_PCHR_CM_VDEC_MASK 0x1
+#define MT6325_RG_INT_EN_PCHR_CM_VDEC_SHIFT 4
+#define MT6325_RG_INT_EN_CHRDET_MASK 0x1
+#define MT6325_RG_INT_EN_CHRDET_SHIFT 5
+#define MT6325_RG_INT_EN_PCHR_CM_VINC_MASK 0x1
+#define MT6325_RG_INT_EN_PCHR_CM_VINC_SHIFT 6
+#define MT6325_RG_INT_EN_FG_BAT_H_MASK 0x1
+#define MT6325_RG_INT_EN_FG_BAT_H_SHIFT 7
+#define MT6325_RG_INT_EN_FG_BAT_L_MASK 0x1
+#define MT6325_RG_INT_EN_FG_BAT_L_SHIFT 8
+#define MT6325_RG_INT_EN_FG_CUR_H_MASK 0x1
+#define MT6325_RG_INT_EN_FG_CUR_H_SHIFT 9
+#define MT6325_RG_INT_EN_FG_CUR_L_MASK 0x1
+#define MT6325_RG_INT_EN_FG_CUR_L_SHIFT 10
+#define MT6325_RG_INT_EN_FG_ZCV_MASK 0x1
+#define MT6325_RG_INT_EN_FG_ZCV_SHIFT 11
+#define MT6325_RG_INT_EN_SPKL_D_MASK 0x1
+#define MT6325_RG_INT_EN_SPKL_D_SHIFT 12
+#define MT6325_RG_INT_EN_SPKL_AB_MASK 0x1
+#define MT6325_RG_INT_EN_SPKL_AB_SHIFT 13
+#define MT6325_INT_CON2_SET_MASK 0xFFFF
+#define MT6325_INT_CON2_SET_SHIFT 0
+#define MT6325_INT_CON2_CLR_MASK 0xFFFF
+#define MT6325_INT_CON2_CLR_SHIFT 0
+#define MT6325_POLARITY_MASK 0x1
+#define MT6325_POLARITY_SHIFT 0
+#define MT6325_RG_HOMEKEY_INT_SEL_MASK 0x1
+#define MT6325_RG_HOMEKEY_INT_SEL_SHIFT 1
+#define MT6325_RG_PWRKEY_INT_SEL_MASK 0x1
+#define MT6325_RG_PWRKEY_INT_SEL_SHIFT 2
+#define MT6325_RG_CHRDET_INT_SEL_MASK 0x1
+#define MT6325_RG_CHRDET_INT_SEL_SHIFT 3
+#define MT6325_RG_PCHR_CM_VINC_POLARITY_RSV_MASK 0x1
+#define MT6325_RG_PCHR_CM_VINC_POLARITY_RSV_SHIFT 4
+#define MT6325_RG_PCHR_CM_VDEC_POLARITY_RSV_MASK 0x1
+#define MT6325_RG_PCHR_CM_VDEC_POLARITY_RSV_SHIFT 5
+#define MT6325_INT_MISC_CON_SET_MASK 0xFFFF
+#define MT6325_INT_MISC_CON_SET_SHIFT 0
+#define MT6325_INT_MISC_CON_CLR_MASK 0xFFFF
+#define MT6325_INT_MISC_CON_CLR_SHIFT 0
+#define MT6325_RG_INT_STATUS_PWRKEY_MASK 0x1
+#define MT6325_RG_INT_STATUS_PWRKEY_SHIFT 0
+#define MT6325_RG_INT_STATUS_HOMEKEY_MASK 0x1
+#define MT6325_RG_INT_STATUS_HOMEKEY_SHIFT 1
+#define MT6325_RG_INT_STATUS_PWRKEY_R_MASK 0x1
+#define MT6325_RG_INT_STATUS_PWRKEY_R_SHIFT 2
+#define MT6325_RG_INT_STATUS_HOMEKEY_R_MASK 0x1
+#define MT6325_RG_INT_STATUS_HOMEKEY_R_SHIFT 3
+#define MT6325_RG_INT_STATUS_THR_H_MASK 0x1
+#define MT6325_RG_INT_STATUS_THR_H_SHIFT 4
+#define MT6325_RG_INT_STATUS_THR_L_MASK 0x1
+#define MT6325_RG_INT_STATUS_THR_L_SHIFT 5
+#define MT6325_RG_INT_STATUS_BAT_H_MASK 0x1
+#define MT6325_RG_INT_STATUS_BAT_H_SHIFT 6
+#define MT6325_RG_INT_STATUS_BAT_L_MASK 0x1
+#define MT6325_RG_INT_STATUS_BAT_L_SHIFT 7
+#define MT6325_RG_INT_STATUS_BIF_MASK 0x1
+#define MT6325_RG_INT_STATUS_BIF_SHIFT 8
+#define MT6325_RG_INT_STATUS_RTC_MASK 0x1
+#define MT6325_RG_INT_STATUS_RTC_SHIFT 9
+#define MT6325_RG_INT_STATUS_AUDIO_MASK 0x1
+#define MT6325_RG_INT_STATUS_AUDIO_SHIFT 10
+#define MT6325_RG_INT_STATUS_VOW_MASK 0x1
+#define MT6325_RG_INT_STATUS_VOW_SHIFT 11
+#define MT6325_RG_INT_STATUS_ACCDET_MASK 0x1
+#define MT6325_RG_INT_STATUS_ACCDET_SHIFT 12
+#define MT6325_RG_INT_STATUS_ACCDET_EINT_MASK 0x1
+#define MT6325_RG_INT_STATUS_ACCDET_EINT_SHIFT 13
+#define MT6325_RG_INT_STATUS_ACCDET_NEGV_MASK 0x1
+#define MT6325_RG_INT_STATUS_ACCDET_NEGV_SHIFT 14
+#define MT6325_RG_INT_STATUS_NI_LBAT_INT_MASK 0x1
+#define MT6325_RG_INT_STATUS_NI_LBAT_INT_SHIFT 15
+#define MT6325_RG_INT_STATUS_VDVFS11_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VDVFS11_OC_SHIFT 0
+#define MT6325_RG_INT_STATUS_VDVFS12_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VDVFS12_OC_SHIFT 1
+#define MT6325_RG_INT_STATUS_VRF18_0_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VRF18_0_OC_SHIFT 2
+#define MT6325_RG_INT_STATUS_VDRAM_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VDRAM_OC_SHIFT 3
+#define MT6325_RG_INT_STATUS_VGPU_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VGPU_OC_SHIFT 4
+#define MT6325_RG_INT_STATUS_VCORE1_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VCORE1_OC_SHIFT 5
+#define MT6325_RG_INT_STATUS_VCORE2_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VCORE2_OC_SHIFT 6
+#define MT6325_RG_INT_STATUS_VIO18_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VIO18_OC_SHIFT 7
+#define MT6325_RG_INT_STATUS_VPA_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_VPA_OC_SHIFT 8
+#define MT6325_RG_INT_STATUS_LDO_OC_MASK 0x1
+#define MT6325_RG_INT_STATUS_LDO_OC_SHIFT 9
+#define MT6325_RG_INT_STATUS_BAT2_H_MASK 0x1
+#define MT6325_RG_INT_STATUS_BAT2_H_SHIFT 10
+#define MT6325_RG_INT_STATUS_BAT2_L_MASK 0x1
+#define MT6325_RG_INT_STATUS_BAT2_L_SHIFT 11
+#define MT6325_RG_INT_STATUS_VISMPS0_H_MASK 0x1
+#define MT6325_RG_INT_STATUS_VISMPS0_H_SHIFT 12
+#define MT6325_RG_INT_STATUS_VISMPS0_L_MASK 0x1
+#define MT6325_RG_INT_STATUS_VISMPS0_L_SHIFT 13
+#define MT6325_RG_INT_STATUS_AUXADC_IMP_MASK 0x1
+#define MT6325_RG_INT_STATUS_AUXADC_IMP_SHIFT 14
+#define MT6325_RG_INT_STATUS_OV_MASK 0x1
+#define MT6325_RG_INT_STATUS_OV_SHIFT 0
+#define MT6325_RG_INT_STATUS_BVALID_DET_MASK 0x1
+#define MT6325_RG_INT_STATUS_BVALID_DET_SHIFT 1
+#define MT6325_RG_INT_STATUS_VBATON_UNDET_MASK 0x1
+#define MT6325_RG_INT_STATUS_VBATON_UNDET_SHIFT 2
+#define MT6325_RG_INT_STATUS_WATCHDOG_MASK 0x1
+#define MT6325_RG_INT_STATUS_WATCHDOG_SHIFT 3
+#define MT6325_RG_INT_STATUS_PCHR_CM_VDEC_MASK 0x1
+#define MT6325_RG_INT_STATUS_PCHR_CM_VDEC_SHIFT 4
+#define MT6325_RG_INT_STATUS_CHRDET_MASK 0x1
+#define MT6325_RG_INT_STATUS_CHRDET_SHIFT 5
+#define MT6325_RG_INT_STATUS_PCHR_CM_VINC_MASK 0x1
+#define MT6325_RG_INT_STATUS_PCHR_CM_VINC_SHIFT 6
+#define MT6325_RG_INT_STATUS_FG_BAT_H_MASK 0x1
+#define MT6325_RG_INT_STATUS_FG_BAT_H_SHIFT 7
+#define MT6325_RG_INT_STATUS_FG_BAT_L_MASK 0x1
+#define MT6325_RG_INT_STATUS_FG_BAT_L_SHIFT 8
+#define MT6325_RG_INT_STATUS_FG_CUR_H_MASK 0x1
+#define MT6325_RG_INT_STATUS_FG_CUR_H_SHIFT 9
+#define MT6325_RG_INT_STATUS_FG_CUR_L_MASK 0x1
+#define MT6325_RG_INT_STATUS_FG_CUR_L_SHIFT 10
+#define MT6325_RG_INT_STATUS_FG_ZCV_MASK 0x1
+#define MT6325_RG_INT_STATUS_FG_ZCV_SHIFT 11
+#define MT6325_RG_INT_STATUS_SPKL_D_MASK 0x1
+#define MT6325_RG_INT_STATUS_SPKL_D_SHIFT 12
+#define MT6325_RG_INT_STATUS_SPKL_AB_MASK 0x1
+#define MT6325_RG_INT_STATUS_SPKL_AB_SHIFT 13
+#define MT6325_OC_GEAR_LDO_MASK 0x3
+#define MT6325_OC_GEAR_LDO_SHIFT 0
+#define MT6325_FQMTR_TCKSEL_MASK 0x7
+#define MT6325_FQMTR_TCKSEL_SHIFT 0
+#define MT6325_FQMTR_BUSY_MASK 0x1
+#define MT6325_FQMTR_BUSY_SHIFT 3
+#define MT6325_FQMTR_EN_MASK 0x1
+#define MT6325_FQMTR_EN_SHIFT 15
+#define MT6325_FQMTR_WINSET_MASK 0xFFFF
+#define MT6325_FQMTR_WINSET_SHIFT 0
+#define MT6325_FQMTR_DATA_MASK 0xFFFF
+#define MT6325_FQMTR_DATA_SHIFT 0
+#define MT6325_RG_SLP_RW_EN_MASK 0x1
+#define MT6325_RG_SLP_RW_EN_SHIFT 0
+#define MT6325_RG_SPI_RSV_MASK 0x7FFF
+#define MT6325_RG_SPI_RSV_SHIFT 1
+#define MT6325_DEW_DIO_EN_MASK 0x1
+#define MT6325_DEW_DIO_EN_SHIFT 0
+#define MT6325_DEW_READ_TEST_MASK 0xFFFF
+#define MT6325_DEW_READ_TEST_SHIFT 0
+#define MT6325_DEW_WRITE_TEST_MASK 0xFFFF
+#define MT6325_DEW_WRITE_TEST_SHIFT 0
+#define MT6325_DEW_CRC_SWRST_MASK 0x1
+#define MT6325_DEW_CRC_SWRST_SHIFT 0
+#define MT6325_DEW_CRC_EN_MASK 0x1
+#define MT6325_DEW_CRC_EN_SHIFT 0
+#define MT6325_DEW_CRC_VAL_MASK 0xFF
+#define MT6325_DEW_CRC_VAL_SHIFT 0
+#define MT6325_DEW_DBG_MON_SEL_MASK 0xF
+#define MT6325_DEW_DBG_MON_SEL_SHIFT 0
+#define MT6325_DEW_CIPHER_KEY_SEL_MASK 0x3
+#define MT6325_DEW_CIPHER_KEY_SEL_SHIFT 0
+#define MT6325_DEW_CIPHER_IV_SEL_MASK 0x3
+#define MT6325_DEW_CIPHER_IV_SEL_SHIFT 0
+#define MT6325_DEW_CIPHER_EN_MASK 0x1
+#define MT6325_DEW_CIPHER_EN_SHIFT 0
+#define MT6325_DEW_CIPHER_RDY_MASK 0x1
+#define MT6325_DEW_CIPHER_RDY_SHIFT 0
+#define MT6325_DEW_CIPHER_MODE_MASK 0x1
+#define MT6325_DEW_CIPHER_MODE_SHIFT 0
+#define MT6325_DEW_CIPHER_SWRST_MASK 0x1
+#define MT6325_DEW_CIPHER_SWRST_SHIFT 0
+#define MT6325_DEW_RDDMY_NO_MASK 0xF
+#define MT6325_DEW_RDDMY_NO_SHIFT 0
+#define MT6325_INT_TYPE_CON0_MASK 0xFFFF
+#define MT6325_INT_TYPE_CON0_SHIFT 0
+#define MT6325_INT_TYPE_CON0_SET_MASK 0xFFFF
+#define MT6325_INT_TYPE_CON0_SET_SHIFT 0
+#define MT6325_INT_TYPE_CON0_CLR_MASK 0xFFFF
+#define MT6325_INT_TYPE_CON0_CLR_SHIFT 0
+#define MT6325_INT_TYPE_CON1_MASK 0x7FFF
+#define MT6325_INT_TYPE_CON1_SHIFT 0
+#define MT6325_INT_TYPE_CON1_SET_MASK 0x7FFF
+#define MT6325_INT_TYPE_CON1_SET_SHIFT 0
+#define MT6325_INT_TYPE_CON1_CLR_MASK 0x7FFF
+#define MT6325_INT_TYPE_CON1_CLR_SHIFT 0
+#define MT6325_INT_TYPE_CON2_MASK 0x3FFF
+#define MT6325_INT_TYPE_CON2_SHIFT 0
+#define MT6325_INT_TYPE_CON2_SET_MASK 0x3FFF
+#define MT6325_INT_TYPE_CON2_SET_SHIFT 0
+#define MT6325_INT_TYPE_CON2_CLR_MASK 0x3FFF
+#define MT6325_INT_TYPE_CON2_CLR_SHIFT 0
+#define MT6325_CPU_INT_STA_MASK 0x1
+#define MT6325_CPU_INT_STA_SHIFT 0
+#define MT6325_MD32_INT_STA_MASK 0x1
+#define MT6325_MD32_INT_STA_SHIFT 1
+#define MT6325_BUCK_ALL_RSV0_MASK 0xFF
+#define MT6325_BUCK_ALL_RSV0_SHIFT 8
+#define MT6325_VSLEEP_SRC0_MASK 0x1FF
+#define MT6325_VSLEEP_SRC0_SHIFT 0
+#define MT6325_VSLEEP_SRC1_MASK 0xF
+#define MT6325_VSLEEP_SRC1_SHIFT 12
+#define MT6325_R2R_SRC0_MASK 0x1FF
+#define MT6325_R2R_SRC0_SHIFT 0
+#define MT6325_R2R_SRC1_MASK 0xF
+#define MT6325_R2R_SRC1_SHIFT 12
+#define MT6325_BUCK_OSC_SEL_SRC0_MASK 0x1FF
+#define MT6325_BUCK_OSC_SEL_SRC0_SHIFT 0
+#define MT6325_SRCLKEN_DLY_SRC1_MASK 0xF
+#define MT6325_SRCLKEN_DLY_SRC1_SHIFT 12
+#define MT6325_BUCK_CON5_RSV0_MASK 0xFFFF
+#define MT6325_BUCK_CON5_RSV0_SHIFT 0
+#define MT6325_QI_VGPU_DIG_MON_MASK 0xF
+#define MT6325_QI_VGPU_DIG_MON_SHIFT 0
+#define MT6325_QI_VIO18_DIG_MON_MASK 0xF
+#define MT6325_QI_VIO18_DIG_MON_SHIFT 4
+#define MT6325_QI_VCORE1_DIG_MON_MASK 0xF
+#define MT6325_QI_VCORE1_DIG_MON_SHIFT 0
+#define MT6325_QI_VCORE2_DIG_MON_MASK 0xF
+#define MT6325_QI_VCORE2_DIG_MON_SHIFT 4
+#define MT6325_QI_VRF18_0_DIG_MON_MASK 0xF
+#define MT6325_QI_VRF18_0_DIG_MON_SHIFT 0
+#define MT6325_QI_VPA_DIG_MON_MASK 0xFF
+#define MT6325_QI_VPA_DIG_MON_SHIFT 8
+#define MT6325_QI_VDVFS11_DIG_MON_MASK 0xFF
+#define MT6325_QI_VDVFS11_DIG_MON_SHIFT 0
+#define MT6325_QI_VDVFS12_DIG_MON_MASK 0xFF
+#define MT6325_QI_VDVFS12_DIG_MON_SHIFT 8
+#define MT6325_VDVFS11_OC_EN_MASK 0x1
+#define MT6325_VDVFS11_OC_EN_SHIFT 0
+#define MT6325_VDVFS11_OC_DEG_EN_MASK 0x1
+#define MT6325_VDVFS11_OC_DEG_EN_SHIFT 1
+#define MT6325_VDVFS11_OC_WND_MASK 0x3
+#define MT6325_VDVFS11_OC_WND_SHIFT 2
+#define MT6325_VDVFS11_OC_THD_MASK 0x3
+#define MT6325_VDVFS11_OC_THD_SHIFT 6
+#define MT6325_VDVFS12_OC_EN_MASK 0x1
+#define MT6325_VDVFS12_OC_EN_SHIFT 0
+#define MT6325_VDVFS12_OC_DEG_EN_MASK 0x1
+#define MT6325_VDVFS12_OC_DEG_EN_SHIFT 1
+#define MT6325_VDVFS12_OC_WND_MASK 0x3
+#define MT6325_VDVFS12_OC_WND_SHIFT 2
+#define MT6325_VDVFS12_OC_THD_MASK 0x3
+#define MT6325_VDVFS12_OC_THD_SHIFT 6
+#define MT6325_VRF18_0_OC_EN_MASK 0x1
+#define MT6325_VRF18_0_OC_EN_SHIFT 0
+#define MT6325_VRF18_0_OC_DEG_EN_MASK 0x1
+#define MT6325_VRF18_0_OC_DEG_EN_SHIFT 1
+#define MT6325_VRF18_0_OC_WND_MASK 0x3
+#define MT6325_VRF18_0_OC_WND_SHIFT 2
+#define MT6325_VRF18_0_OC_THD_MASK 0x3
+#define MT6325_VRF18_0_OC_THD_SHIFT 6
+#define MT6325_VPA_OC_EN_MASK 0x1
+#define MT6325_VPA_OC_EN_SHIFT 0
+#define MT6325_VPA_OC_DEG_EN_MASK 0x1
+#define MT6325_VPA_OC_DEG_EN_SHIFT 1
+#define MT6325_VPA_OC_WND_MASK 0x3
+#define MT6325_VPA_OC_WND_SHIFT 2
+#define MT6325_VPA_OC_THD_MASK 0x3
+#define MT6325_VPA_OC_THD_SHIFT 6
+#define MT6325_VGPU_OC_EN_MASK 0x1
+#define MT6325_VGPU_OC_EN_SHIFT 0
+#define MT6325_VGPU_OC_DEG_EN_MASK 0x1
+#define MT6325_VGPU_OC_DEG_EN_SHIFT 1
+#define MT6325_VGPU_OC_WND_MASK 0x3
+#define MT6325_VGPU_OC_WND_SHIFT 2
+#define MT6325_VGPU_OC_THD_MASK 0x3
+#define MT6325_VGPU_OC_THD_SHIFT 6
+#define MT6325_VCORE1_OC_EN_MASK 0x1
+#define MT6325_VCORE1_OC_EN_SHIFT 0
+#define MT6325_VCORE1_OC_DEG_EN_MASK 0x1
+#define MT6325_VCORE1_OC_DEG_EN_SHIFT 1
+#define MT6325_VCORE1_OC_WND_MASK 0x3
+#define MT6325_VCORE1_OC_WND_SHIFT 2
+#define MT6325_VCORE1_OC_THD_MASK 0x3
+#define MT6325_VCORE1_OC_THD_SHIFT 6
+#define MT6325_VCORE2_OC_EN_MASK 0x1
+#define MT6325_VCORE2_OC_EN_SHIFT 0
+#define MT6325_VCORE2_OC_DEG_EN_MASK 0x1
+#define MT6325_VCORE2_OC_DEG_EN_SHIFT 1
+#define MT6325_VCORE2_OC_WND_MASK 0x3
+#define MT6325_VCORE2_OC_WND_SHIFT 2
+#define MT6325_VCORE2_OC_THD_MASK 0x3
+#define MT6325_VCORE2_OC_THD_SHIFT 6
+#define MT6325_VIO18_OC_EN_MASK 0x1
+#define MT6325_VIO18_OC_EN_SHIFT 0
+#define MT6325_VIO18_OC_DEG_EN_MASK 0x1
+#define MT6325_VIO18_OC_DEG_EN_SHIFT 1
+#define MT6325_VIO18_OC_WND_MASK 0x3
+#define MT6325_VIO18_OC_WND_SHIFT 2
+#define MT6325_VIO18_OC_THD_MASK 0x3
+#define MT6325_VIO18_OC_THD_SHIFT 6
+#define MT6325_VDRAM_OC_EN_MASK 0x1
+#define MT6325_VDRAM_OC_EN_SHIFT 0
+#define MT6325_VDRAM_OC_DEG_EN_MASK 0x1
+#define MT6325_VDRAM_OC_DEG_EN_SHIFT 1
+#define MT6325_VDRAM_OC_WND_MASK 0x3
+#define MT6325_VDRAM_OC_WND_SHIFT 2
+#define MT6325_VDRAM_OC_THD_MASK 0x3
+#define MT6325_VDRAM_OC_THD_SHIFT 6
+#define MT6325_VDVFS11_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VDVFS11_OC_FLAG_CLR_SHIFT 0
+#define MT6325_VDVFS12_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VDVFS12_OC_FLAG_CLR_SHIFT 1
+#define MT6325_VRF18_0_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VRF18_0_OC_FLAG_CLR_SHIFT 2
+#define MT6325_VPA_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VPA_OC_FLAG_CLR_SHIFT 3
+#define MT6325_VGPU_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VGPU_OC_FLAG_CLR_SHIFT 4
+#define MT6325_VCORE1_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VCORE1_OC_FLAG_CLR_SHIFT 5
+#define MT6325_VCORE2_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VCORE2_OC_FLAG_CLR_SHIFT 6
+#define MT6325_VIO18_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VIO18_OC_FLAG_CLR_SHIFT 7
+#define MT6325_VDRAM_OC_FLAG_CLR_MASK 0x1
+#define MT6325_VDRAM_OC_FLAG_CLR_SHIFT 8
+#define MT6325_VDVFS11_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VDVFS11_OC_FLAG_CLR_SEL_SHIFT 0
+#define MT6325_VDVFS12_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VDVFS12_OC_FLAG_CLR_SEL_SHIFT 1
+#define MT6325_VRF18_0_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VRF18_0_OC_FLAG_CLR_SEL_SHIFT 2
+#define MT6325_VPA_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VPA_OC_FLAG_CLR_SEL_SHIFT 3
+#define MT6325_VGPU_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VGPU_OC_FLAG_CLR_SEL_SHIFT 4
+#define MT6325_VCORE1_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VCORE1_OC_FLAG_CLR_SEL_SHIFT 5
+#define MT6325_VCORE2_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VCORE2_OC_FLAG_CLR_SEL_SHIFT 6
+#define MT6325_VIO18_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VIO18_OC_FLAG_CLR_SEL_SHIFT 7
+#define MT6325_VDRAM_OC_FLAG_CLR_SEL_MASK 0x1
+#define MT6325_VDRAM_OC_FLAG_CLR_SEL_SHIFT 8
+#define MT6325_VDVFS11_OC_STATUS_MASK 0x1
+#define MT6325_VDVFS11_OC_STATUS_SHIFT 0
+#define MT6325_VDVFS12_OC_STATUS_MASK 0x1
+#define MT6325_VDVFS12_OC_STATUS_SHIFT 1
+#define MT6325_VRF18_0_OC_STATUS_MASK 0x1
+#define MT6325_VRF18_0_OC_STATUS_SHIFT 2
+#define MT6325_VPA_OC_STATUS_MASK 0x1
+#define MT6325_VPA_OC_STATUS_SHIFT 3
+#define MT6325_VGPU_OC_STATUS_MASK 0x1
+#define MT6325_VGPU_OC_STATUS_SHIFT 4
+#define MT6325_VCORE1_OC_STATUS_MASK 0x1
+#define MT6325_VCORE1_OC_STATUS_SHIFT 5
+#define MT6325_VCORE2_OC_STATUS_MASK 0x1
+#define MT6325_VCORE2_OC_STATUS_SHIFT 6
+#define MT6325_VIO18_OC_STATUS_MASK 0x1
+#define MT6325_VIO18_OC_STATUS_SHIFT 7
+#define MT6325_VDRAM_OC_STATUS_MASK 0x1
+#define MT6325_VDRAM_OC_STATUS_SHIFT 8
+#define MT6325_VDVFS11_OC_INT_EN_MASK 0x1
+#define MT6325_VDVFS11_OC_INT_EN_SHIFT 0
+#define MT6325_VDVFS12_OC_INT_EN_MASK 0x1
+#define MT6325_VDVFS12_OC_INT_EN_SHIFT 1
+#define MT6325_VRF18_0_OC_INT_EN_MASK 0x1
+#define MT6325_VRF18_0_OC_INT_EN_SHIFT 2
+#define MT6325_VPA_OC_INT_EN_MASK 0x1
+#define MT6325_VPA_OC_INT_EN_SHIFT 3
+#define MT6325_VGPU_OC_INT_EN_MASK 0x1
+#define MT6325_VGPU_OC_INT_EN_SHIFT 4
+#define MT6325_VCORE1_OC_INT_EN_MASK 0x1
+#define MT6325_VCORE1_OC_INT_EN_SHIFT 5
+#define MT6325_VCORE2_OC_INT_EN_MASK 0x1
+#define MT6325_VCORE2_OC_INT_EN_SHIFT 6
+#define MT6325_VIO18_OC_INT_EN_MASK 0x1
+#define MT6325_VIO18_OC_INT_EN_SHIFT 7
+#define MT6325_VDRAM_OC_INT_EN_MASK 0x1
+#define MT6325_VDRAM_OC_INT_EN_SHIFT 8
+#define MT6325_VDVFS11_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VDVFS11_EN_OC_SDN_SEL_SHIFT 0
+#define MT6325_VDVFS12_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VDVFS12_EN_OC_SDN_SEL_SHIFT 1
+#define MT6325_VRF18_0_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VRF18_0_EN_OC_SDN_SEL_SHIFT 2
+#define MT6325_VPA_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VPA_EN_OC_SDN_SEL_SHIFT 3
+#define MT6325_VGPU_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VGPU_EN_OC_SDN_SEL_SHIFT 4
+#define MT6325_VCORE1_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VCORE1_EN_OC_SDN_SEL_SHIFT 5
+#define MT6325_VCORE2_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VCORE2_EN_OC_SDN_SEL_SHIFT 6
+#define MT6325_VIO18_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VIO18_EN_OC_SDN_SEL_SHIFT 7
+#define MT6325_VDRAM_EN_OC_SDN_SEL_MASK 0x1
+#define MT6325_VDRAM_EN_OC_SDN_SEL_SHIFT 8
+#define MT6325_VSRAM_DVFS1_TRACK_SLEEP_CTRL_MASK 0x1
+#define MT6325_VSRAM_DVFS1_TRACK_SLEEP_CTRL_SHIFT 0
+#define MT6325_VSRAM_DVFS1_TRACK_ON_CTRL_MASK 0x1
+#define MT6325_VSRAM_DVFS1_TRACK_ON_CTRL_SHIFT 1
+#define MT6325_VDVFS1_TRACK_ON_CTRL_MASK 0x1
+#define MT6325_VDVFS1_TRACK_ON_CTRL_SHIFT 2
+#define MT6325_VSRAM_DVFS1_VOSEL_DELTA_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_DELTA_SHIFT 0
+#define MT6325_VSRAM_DVFS1_VOSEL_OFFSET_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_OFFSET_SHIFT 8
+#define MT6325_VSRAM_DVFS1_VOSEL_ON_LB_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_ON_LB_SHIFT 0
+#define MT6325_VSRAM_DVFS1_VOSEL_ON_HB_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_ON_HB_SHIFT 8
+#define MT6325_VSRAM_DVFS1_VOSEL_SLEEP_LB_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_SLEEP_LB_SHIFT 0
+#define MT6325_QI_VDVFS11_VSLEEP_MASK 0x3
+#define MT6325_QI_VDVFS11_VSLEEP_SHIFT 0
+#define MT6325_QI_VDVFS12_VSLEEP_MASK 0x3
+#define MT6325_QI_VDVFS12_VSLEEP_SHIFT 2
+#define MT6325_QI_VGPU_VSLEEP_MASK 0x3
+#define MT6325_QI_VGPU_VSLEEP_SHIFT 4
+#define MT6325_QI_VCORE1_VSLEEP_MASK 0x3
+#define MT6325_QI_VCORE1_VSLEEP_SHIFT 6
+#define MT6325_QI_VCORE2_VSLEEP_MASK 0x3
+#define MT6325_QI_VCORE2_VSLEEP_SHIFT 8
+#define MT6325_QI_VDRAM_VSLEEP_MASK 0x3
+#define MT6325_QI_VDRAM_VSLEEP_SHIFT 10
+#define MT6325_QI_VSRAM_DVFS1_VSLEEP_MASK 0x3
+#define MT6325_QI_VSRAM_DVFS1_VSLEEP_SHIFT 12
+#define MT6325_QI_VDVFS11_VSLEEP_RSV0_MASK 0x1
+#define MT6325_QI_VDVFS11_VSLEEP_RSV0_SHIFT 0
+#define MT6325_QI_VDVFS12_VSLEEP_RSV0_MASK 0x1
+#define MT6325_QI_VDVFS12_VSLEEP_RSV0_SHIFT 1
+#define MT6325_QI_VGPU_MODE_MASK 0x1
+#define MT6325_QI_VGPU_MODE_SHIFT 2
+#define MT6325_QI_VCORE1_MODE_MASK 0x1
+#define MT6325_QI_VCORE1_MODE_SHIFT 3
+#define MT6325_QI_VCORE2_MODE_MASK 0x1
+#define MT6325_QI_VCORE2_MODE_SHIFT 4
+#define MT6325_QI_VDRAM_MODE_MASK 0x1
+#define MT6325_QI_VDRAM_MODE_SHIFT 5
+#define MT6325_QI_VRF18_0_MODE_MASK 0x1
+#define MT6325_QI_VRF18_0_MODE_SHIFT 6
+#define MT6325_QI_VIO18_MODE_MASK 0x1
+#define MT6325_QI_VIO18_MODE_SHIFT 7
+#define MT6325_RG_VDRAM_MIN_OFF_MASK 0x3
+#define MT6325_RG_VDRAM_MIN_OFF_SHIFT 0
+#define MT6325_RG_VDRAM_NVT_BUFF_OFF_EN_MASK 0x1
+#define MT6325_RG_VDRAM_NVT_BUFF_OFF_EN_SHIFT 2
+#define MT6325_RG_VDRAM_VRF18_SSTART_EN_MASK 0x1
+#define MT6325_RG_VDRAM_VRF18_SSTART_EN_SHIFT 3
+#define MT6325_RG_VDRAM_1P35UP_SEL_EN_MASK 0x1
+#define MT6325_RG_VDRAM_1P35UP_SEL_EN_SHIFT 4
+#define MT6325_RG_VDRAM_RZSEL_MASK 0x7
+#define MT6325_RG_VDRAM_RZSEL_SHIFT 5
+#define MT6325_RG_VDRAM_CC_MASK 0x3
+#define MT6325_RG_VDRAM_CC_SHIFT 8
+#define MT6325_RG_VDRAM_CSR_MASK 0x7
+#define MT6325_RG_VDRAM_CSR_SHIFT 10
+#define MT6325_RG_VDRAM_CSL_MASK 0xF
+#define MT6325_RG_VDRAM_CSL_SHIFT 0
+#define MT6325_RG_VDRAM_SLP_MASK 0x7
+#define MT6325_RG_VDRAM_SLP_SHIFT 4
+#define MT6325_RG_VDRAM_ZX_OS_MASK 0x3
+#define MT6325_RG_VDRAM_ZX_OS_SHIFT 7
+#define MT6325_RG_VDRAM_ZXOS_TRIM_MASK 0x3F
+#define MT6325_RG_VDRAM_ZXOS_TRIM_SHIFT 9
+#define MT6325_RG_VDRAM_MODESET_MASK 0x1
+#define MT6325_RG_VDRAM_MODESET_SHIFT 15
+#define MT6325_RG_VDRAM_NDIS_EN_MASK 0x1
+#define MT6325_RG_VDRAM_NDIS_EN_SHIFT 0
+#define MT6325_RG_VDRAM_CSM_MASK 0x3F
+#define MT6325_RG_VDRAM_CSM_SHIFT 1
+#define MT6325_RG_VDRAM_RSV_MASK 0xFF
+#define MT6325_RG_VDRAM_RSV_SHIFT 7
+#define MT6325_RG_VDRAM_PFM_RIP_MASK 0x7
+#define MT6325_RG_VDRAM_PFM_RIP_SHIFT 0
+#define MT6325_RG_VDRAM_TRAN_BST_MASK 0x3F
+#define MT6325_RG_VDRAM_TRAN_BST_SHIFT 3
+#define MT6325_RG_VDRAM_DTS_ENB_MASK 0x1
+#define MT6325_RG_VDRAM_DTS_ENB_SHIFT 9
+#define MT6325_RG_VDRAM_RCL_TRIM_MASK 0x1F
+#define MT6325_RG_VDRAM_RCL_TRIM_SHIFT 10
+#define MT6325_RG_VDRAM_RCL_TRIM_EN_MASK 0x1
+#define MT6325_RG_VDRAM_RCL_TRIM_EN_SHIFT 15
+#define MT6325_RG_VDRAM_C2_RSV_MASK 0x1
+#define MT6325_RG_VDRAM_C2_RSV_SHIFT 0
+#define MT6325_RG_VCORE1_MIN_OFF_MASK 0x3
+#define MT6325_RG_VCORE1_MIN_OFF_SHIFT 0
+#define MT6325_RG_VCORE1_NVT_BUFF_OFF_EN_MASK 0x1
+#define MT6325_RG_VCORE1_NVT_BUFF_OFF_EN_SHIFT 2
+#define MT6325_RG_VCORE1_VRF18_SSTART_EN_MASK 0x1
+#define MT6325_RG_VCORE1_VRF18_SSTART_EN_SHIFT 3
+#define MT6325_RG_VCORE1_1P35UP_SEL_EN_MASK 0x1
+#define MT6325_RG_VCORE1_1P35UP_SEL_EN_SHIFT 4
+#define MT6325_RG_VCORE1_RZSEL_MASK 0x7
+#define MT6325_RG_VCORE1_RZSEL_SHIFT 5
+#define MT6325_RG_VCORE1_CC_MASK 0x3
+#define MT6325_RG_VCORE1_CC_SHIFT 8
+#define MT6325_RG_VCORE1_CSR_MASK 0x7
+#define MT6325_RG_VCORE1_CSR_SHIFT 10
+#define MT6325_RG_VCORE1_CSL_MASK 0xF
+#define MT6325_RG_VCORE1_CSL_SHIFT 0
+#define MT6325_RG_VCORE1_SLP_MASK 0x7
+#define MT6325_RG_VCORE1_SLP_SHIFT 4
+#define MT6325_RG_VCORE1_ZX_OS_MASK 0x3
+#define MT6325_RG_VCORE1_ZX_OS_SHIFT 7
+#define MT6325_RG_VCORE1_ZXOS_TRIM_MASK 0x3F
+#define MT6325_RG_VCORE1_ZXOS_TRIM_SHIFT 9
+#define MT6325_RG_VCORE1_MODESET_MASK 0x1
+#define MT6325_RG_VCORE1_MODESET_SHIFT 15
+#define MT6325_RG_VCORE1_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCORE1_NDIS_EN_SHIFT 0
+#define MT6325_RG_VCORE1_CSM_MASK 0x3F
+#define MT6325_RG_VCORE1_CSM_SHIFT 1
+#define MT6325_RG_VCORE1_RSV_MASK 0xFF
+#define MT6325_RG_VCORE1_RSV_SHIFT 7
+#define MT6325_RG_VCORE1_PFM_RIP_MASK 0x7
+#define MT6325_RG_VCORE1_PFM_RIP_SHIFT 0
+#define MT6325_RG_VCORE1_TRAN_BST_MASK 0x3F
+#define MT6325_RG_VCORE1_TRAN_BST_SHIFT 3
+#define MT6325_RG_VCORE1_DTS_ENB_MASK 0x1
+#define MT6325_RG_VCORE1_DTS_ENB_SHIFT 9
+#define MT6325_RG_VCORE1_RCL_TRIM_MASK 0x1F
+#define MT6325_RG_VCORE1_RCL_TRIM_SHIFT 10
+#define MT6325_RG_VCORE1_RCL_TRIM_EN_MASK 0x1
+#define MT6325_RG_VCORE1_RCL_TRIM_EN_SHIFT 15
+#define MT6325_RG_VCORE1_C2_RSV_MASK 0x1
+#define MT6325_RG_VCORE1_C2_RSV_SHIFT 0
+#define MT6325_RG_SMPS_TESTMODE_B_MASK 0x1FF
+#define MT6325_RG_SMPS_TESTMODE_B_SHIFT 0
+#define MT6325_RG_VSRAM_DVFS1_TRIMH_MASK 0x1F
+#define MT6325_RG_VSRAM_DVFS1_TRIMH_SHIFT 9
+#define MT6325_RG_VSRAM_DVFS1_TRIML_MASK 0x1F
+#define MT6325_RG_VSRAM_DVFS1_TRIML_SHIFT 0
+#define MT6325_RG_VDVFS11_TRIMH_MASK 0x1F
+#define MT6325_RG_VDVFS11_TRIMH_SHIFT 5
+#define MT6325_RG_VDVFS11_TRIML_MASK 0x1F
+#define MT6325_RG_VDVFS11_TRIML_SHIFT 10
+#define MT6325_RG_VDVFS12_TRIMH_MASK 0x1F
+#define MT6325_RG_VDVFS12_TRIMH_SHIFT 0
+#define MT6325_RG_VDVFS12_TRIML_MASK 0x1F
+#define MT6325_RG_VDVFS12_TRIML_SHIFT 5
+#define MT6325_RG_VGPU_TRIMH_MASK 0x1F
+#define MT6325_RG_VGPU_TRIMH_SHIFT 10
+#define MT6325_RG_VGPU_TRIML_MASK 0x1F
+#define MT6325_RG_VGPU_TRIML_SHIFT 0
+#define MT6325_RG_VCORE1_TRIMH_MASK 0x1F
+#define MT6325_RG_VCORE1_TRIMH_SHIFT 5
+#define MT6325_RG_VCORE1_TRIML_MASK 0x1F
+#define MT6325_RG_VCORE1_TRIML_SHIFT 10
+#define MT6325_RG_VCORE2_TRIMH_MASK 0x1F
+#define MT6325_RG_VCORE2_TRIMH_SHIFT 0
+#define MT6325_RG_VCORE2_TRIML_MASK 0x1F
+#define MT6325_RG_VCORE2_TRIML_SHIFT 5
+#define MT6325_RG_VIO18_TRIMH_MASK 0xF
+#define MT6325_RG_VIO18_TRIMH_SHIFT 10
+#define MT6325_RG_VIO18_TRIML_MASK 0xF
+#define MT6325_RG_VIO18_TRIML_SHIFT 0
+#define MT6325_RG_VPA_TRIMH_MASK 0x1F
+#define MT6325_RG_VPA_TRIMH_SHIFT 4
+#define MT6325_RG_VPA_TRIML_MASK 0x1F
+#define MT6325_RG_VPA_TRIML_SHIFT 9
+#define MT6325_RG_VPA_TRIM_REF_MASK 0x1F
+#define MT6325_RG_VPA_TRIM_REF_SHIFT 0
+#define MT6325_RG_VRF18_0_TRIMH_MASK 0xF
+#define MT6325_RG_VRF18_0_TRIMH_SHIFT 5
+#define MT6325_RG_VRF18_0_TRIML_MASK 0xF
+#define MT6325_RG_VRF18_0_TRIML_SHIFT 9
+#define MT6325_RG_VDRAM_TRIMH_MASK 0xF
+#define MT6325_RG_VDRAM_TRIMH_SHIFT 0
+#define MT6325_RG_VDRAM_TRIML_MASK 0xF
+#define MT6325_RG_VDRAM_TRIML_SHIFT 4
+#define MT6325_RG_VSRAM_DVFS1_VSLEEP_MASK 0x7
+#define MT6325_RG_VSRAM_DVFS1_VSLEEP_SHIFT 8
+#define MT6325_RG_VDVFS11_VSLEEP_MASK 0x7
+#define MT6325_RG_VDVFS11_VSLEEP_SHIFT 11
+#define MT6325_RG_VDVFS12_VSLEEP_MASK 0x7
+#define MT6325_RG_VDVFS12_VSLEEP_SHIFT 0
+#define MT6325_RG_VGPU_VSLEEP_MASK 0x7
+#define MT6325_RG_VGPU_VSLEEP_SHIFT 3
+#define MT6325_RG_VCORE1_VSLEEP_MASK 0x7
+#define MT6325_RG_VCORE1_VSLEEP_SHIFT 6
+#define MT6325_RG_VCORE2_VSLEEP_MASK 0x7
+#define MT6325_RG_VCORE2_VSLEEP_SHIFT 9
+#define MT6325_RG_VPA_BURSTH_MASK 0x3
+#define MT6325_RG_VPA_BURSTH_SHIFT 12
+#define MT6325_RG_VPA_BURSTL_MASK 0x3
+#define MT6325_RG_VPA_BURSTL_SHIFT 14
+#define MT6325_RG_VDRAM_VSLEEP_MASK 0x7
+#define MT6325_RG_VDRAM_VSLEEP_SHIFT 0
+#define MT6325_RG_DMY100MA_EN_MASK 0x1
+#define MT6325_RG_DMY100MA_EN_SHIFT 3
+#define MT6325_RG_DMY100MA_SEL_MASK 0x3
+#define MT6325_RG_DMY100MA_SEL_SHIFT 4
+#define MT6325_RG_VDVFS1_MIN_OFF_MASK 0x3
+#define MT6325_RG_VDVFS1_MIN_OFF_SHIFT 0
+#define MT6325_RG_VDVFS1_NVT_BUFF_OFF_EN_MASK 0x1
+#define MT6325_RG_VDVFS1_NVT_BUFF_OFF_EN_SHIFT 2
+#define MT6325_RG_VDVFS1_VRF18_SSTART_EN_MASK 0x1
+#define MT6325_RG_VDVFS1_VRF18_SSTART_EN_SHIFT 3
+#define MT6325_RG_VDVFS1_1P35UP_SEL_EN_MASK 0x1
+#define MT6325_RG_VDVFS1_1P35UP_SEL_EN_SHIFT 4
+#define MT6325_RG_VDVFS11_RZSEL_MASK 0xF
+#define MT6325_RG_VDVFS11_RZSEL_SHIFT 5
+#define MT6325_RG_VDVFS12_RZSEL_MASK 0xF
+#define MT6325_RG_VDVFS12_RZSEL_SHIFT 9
+#define MT6325_RG_VDVFS11_PFM_RIP_MASK 0x7
+#define MT6325_RG_VDVFS11_PFM_RIP_SHIFT 13
+#define MT6325_RG_VDVFS11_CSR_MASK 0x7
+#define MT6325_RG_VDVFS11_CSR_SHIFT 0
+#define MT6325_RG_VDVFS12_CSR_MASK 0x7
+#define MT6325_RG_VDVFS12_CSR_SHIFT 3
+#define MT6325_RG_VDVFS11_PFM_CSR_MASK 0x7
+#define MT6325_RG_VDVFS11_PFM_CSR_SHIFT 6
+#define MT6325_RG_VDVFS12_PFM_CSR_MASK 0x7
+#define MT6325_RG_VDVFS12_PFM_CSR_SHIFT 9
+#define MT6325_RG_VDVFS11_CSL_MASK 0xF
+#define MT6325_RG_VDVFS11_CSL_SHIFT 12
+#define MT6325_RG_VDVFS12_CSL_MASK 0xF
+#define MT6325_RG_VDVFS12_CSL_SHIFT 0
+#define MT6325_RG_VDVFS11_SLP_MASK 0x7
+#define MT6325_RG_VDVFS11_SLP_SHIFT 4
+#define MT6325_RG_VDVFS12_SLP_MASK 0x7
+#define MT6325_RG_VDVFS12_SLP_SHIFT 7
+#define MT6325_RG_VDVFS11_ZX_OS_MASK 0x3
+#define MT6325_RG_VDVFS11_ZX_OS_SHIFT 10
+#define MT6325_RG_VDVFS12_ZX_OS_MASK 0x3
+#define MT6325_RG_VDVFS12_ZX_OS_SHIFT 12
+#define MT6325_RG_VDVFS11_MODESET_MASK 0x1
+#define MT6325_RG_VDVFS11_MODESET_SHIFT 14
+#define MT6325_RG_VDVFS12_MODESET_MASK 0x1
+#define MT6325_RG_VDVFS12_MODESET_SHIFT 15
+#define MT6325_RG_VDVFS11_NDIS_EN_MASK 0x1
+#define MT6325_RG_VDVFS11_NDIS_EN_SHIFT 0
+#define MT6325_RG_VDVFS12_NDIS_EN_MASK 0x1
+#define MT6325_RG_VDVFS12_NDIS_EN_SHIFT 1
+#define MT6325_RG_VDVFS11_TRANS_BST_MASK 0xFF
+#define MT6325_RG_VDVFS11_TRANS_BST_SHIFT 2
+#define MT6325_RG_VDVFS12_TRANS_BST_MASK 0xFF
+#define MT6325_RG_VDVFS12_TRANS_BST_SHIFT 0
+#define MT6325_RG_VDVFS11_UVP_EN_MASK 0x1
+#define MT6325_RG_VDVFS11_UVP_EN_SHIFT 8
+#define MT6325_RG_VDVFS12_UVP_EN_MASK 0x1
+#define MT6325_RG_VDVFS12_UVP_EN_SHIFT 9
+#define MT6325_RG_VDVFS11_CSM_MASK 0x3F
+#define MT6325_RG_VDVFS11_CSM_SHIFT 10
+#define MT6325_RG_VDVFS12_CSM_MASK 0x3F
+#define MT6325_RG_VDVFS12_CSM_SHIFT 0
+#define MT6325_RG_VDVFS11_PKMODE_MASK 0x1
+#define MT6325_RG_VDVFS11_PKMODE_SHIFT 6
+#define MT6325_RG_VDVFS12_PKMODE_MASK 0x1
+#define MT6325_RG_VDVFS12_PKMODE_SHIFT 7
+#define MT6325_RG_VDVFS11_RSV_MASK 0xFF
+#define MT6325_RG_VDVFS11_RSV_SHIFT 8
+#define MT6325_RG_VDVFS12_RSV_MASK 0xFF
+#define MT6325_RG_VDVFS12_RSV_SHIFT 0
+#define MT6325_RG_VDVFS11_ZXOS_TRIM_MASK 0xFF
+#define MT6325_RG_VDVFS11_ZXOS_TRIM_SHIFT 8
+#define MT6325_RG_VDVFS12_ZXOS_TRIM_MASK 0xFF
+#define MT6325_RG_VDVFS12_ZXOS_TRIM_SHIFT 0
+#define MT6325_RG_VDVFS11_OC_OFF_MASK 0x1
+#define MT6325_RG_VDVFS11_OC_OFF_SHIFT 8
+#define MT6325_RG_VDVFS12_OC_OFF_MASK 0x1
+#define MT6325_RG_VDVFS12_OC_OFF_SHIFT 9
+#define MT6325_RG_VDVFS11_PHS_SHED_TRIM_MASK 0xF
+#define MT6325_RG_VDVFS11_PHS_SHED_TRIM_SHIFT 10
+#define MT6325_RG_VGPU_MIN_OFF_MASK 0x3
+#define MT6325_RG_VGPU_MIN_OFF_SHIFT 0
+#define MT6325_RG_VGPU_NVT_BUFF_OFF_EN_MASK 0x1
+#define MT6325_RG_VGPU_NVT_BUFF_OFF_EN_SHIFT 2
+#define MT6325_RG_VGPU_VRF18_SSTART_EN_MASK 0x1
+#define MT6325_RG_VGPU_VRF18_SSTART_EN_SHIFT 3
+#define MT6325_RG_VGPU_1P35UP_SEL_EN_MASK 0x1
+#define MT6325_RG_VGPU_1P35UP_SEL_EN_SHIFT 4
+#define MT6325_RG_VGPU_RZSEL_MASK 0x7
+#define MT6325_RG_VGPU_RZSEL_SHIFT 5
+#define MT6325_RG_VGPU_CC_MASK 0x3
+#define MT6325_RG_VGPU_CC_SHIFT 8
+#define MT6325_RG_VGPU_CSR_MASK 0x7
+#define MT6325_RG_VGPU_CSR_SHIFT 10
+#define MT6325_RG_VGPU_CSL_MASK 0xF
+#define MT6325_RG_VGPU_CSL_SHIFT 0
+#define MT6325_RG_VGPU_SLP_MASK 0x7
+#define MT6325_RG_VGPU_SLP_SHIFT 4
+#define MT6325_RG_VGPU_ZX_OS_MASK 0x3
+#define MT6325_RG_VGPU_ZX_OS_SHIFT 7
+#define MT6325_RG_VGPU_ZXOS_TRIM_MASK 0x3F
+#define MT6325_RG_VGPU_ZXOS_TRIM_SHIFT 9
+#define MT6325_RG_VGPU_MODESET_MASK 0x1
+#define MT6325_RG_VGPU_MODESET_SHIFT 15
+#define MT6325_RG_VGPU_NDIS_EN_MASK 0x1
+#define MT6325_RG_VGPU_NDIS_EN_SHIFT 0
+#define MT6325_RG_VGPU_CSM_MASK 0x3F
+#define MT6325_RG_VGPU_CSM_SHIFT 1
+#define MT6325_RG_VGPU_RSV_MASK 0xFF
+#define MT6325_RG_VGPU_RSV_SHIFT 7
+#define MT6325_RG_VGPU_PFM_RIP_MASK 0x7
+#define MT6325_RG_VGPU_PFM_RIP_SHIFT 0
+#define MT6325_RG_VGPU_TRAN_BST_MASK 0x3F
+#define MT6325_RG_VGPU_TRAN_BST_SHIFT 3
+#define MT6325_RG_VGPU_DTS_ENB_MASK 0x1
+#define MT6325_RG_VGPU_DTS_ENB_SHIFT 9
+#define MT6325_RG_VGPU_RCL_TRIM_MASK 0x1F
+#define MT6325_RG_VGPU_RCL_TRIM_SHIFT 10
+#define MT6325_RG_VGPU_RCL_TRIM_EN_MASK 0x1
+#define MT6325_RG_VGPU_RCL_TRIM_EN_SHIFT 15
+#define MT6325_RG_VGPU_C2_RSV_MASK 0x1
+#define MT6325_RG_VGPU_C2_RSV_SHIFT 0
+#define MT6325_RG_VPA_RZSEL_MASK 0x3
+#define MT6325_RG_VPA_RZSEL_SHIFT 0
+#define MT6325_RG_VPA_CC_MASK 0x3
+#define MT6325_RG_VPA_CC_SHIFT 2
+#define MT6325_RG_VPA_CSR_MASK 0x3
+#define MT6325_RG_VPA_CSR_SHIFT 4
+#define MT6325_RG_VPA_CSMIR_MASK 0x3
+#define MT6325_RG_VPA_CSMIR_SHIFT 6
+#define MT6325_RG_VPA_CSL_MASK 0x3
+#define MT6325_RG_VPA_CSL_SHIFT 8
+#define MT6325_RG_VPA_SLP_MASK 0x3
+#define MT6325_RG_VPA_SLP_SHIFT 10
+#define MT6325_RG_VPA_ZX_OS_TRIM_MASK 0x3F
+#define MT6325_RG_VPA_ZX_OS_TRIM_SHIFT 0
+#define MT6325_RG_VPA_ZX_OS_MASK 0x3
+#define MT6325_RG_VPA_ZX_OS_SHIFT 6
+#define MT6325_RG_VPA_HZP_MASK 0x1
+#define MT6325_RG_VPA_HZP_SHIFT 8
+#define MT6325_RG_VPA_BWEX_GAT_MASK 0x1
+#define MT6325_RG_VPA_BWEX_GAT_SHIFT 9
+#define MT6325_RG_VPA_MODESET_MASK 0x1
+#define MT6325_RG_VPA_MODESET_SHIFT 10
+#define MT6325_RG_VPA_SLEW_MASK 0x3
+#define MT6325_RG_VPA_SLEW_SHIFT 11
+#define MT6325_RG_VPA_SLEW_NMOS_MASK 0x3
+#define MT6325_RG_VPA_SLEW_NMOS_SHIFT 13
+#define MT6325_RG_VPA_NDIS_EN_MASK 0x1
+#define MT6325_RG_VPA_NDIS_EN_SHIFT 15
+#define MT6325_RG_VPA_MIN_ON_MASK 0x3
+#define MT6325_RG_VPA_MIN_ON_SHIFT 0
+#define MT6325_RG_VPA_VBAT_DEL_MASK 0x3
+#define MT6325_RG_VPA_VBAT_DEL_SHIFT 2
+#define MT6325_RG_VPA_EN_MASK 0x1
+#define MT6325_RG_VPA_EN_SHIFT 4
+#define MT6325_RG_VPA_RSV1_MASK 0xFF
+#define MT6325_RG_VPA_RSV1_SHIFT 5
+#define MT6325_RG_VPA_RSV2_MASK 0xFF
+#define MT6325_RG_VPA_RSV2_SHIFT 0
+#define MT6325_RG_VCORE2_MIN_OFF_MASK 0x3
+#define MT6325_RG_VCORE2_MIN_OFF_SHIFT 0
+#define MT6325_RG_VCORE2_NVT_BUFF_OFF_EN_MASK 0x1
+#define MT6325_RG_VCORE2_NVT_BUFF_OFF_EN_SHIFT 2
+#define MT6325_RG_VCORE2_VRF18_SSTART_EN_MASK 0x1
+#define MT6325_RG_VCORE2_VRF18_SSTART_EN_SHIFT 3
+#define MT6325_RG_VCORE2_1P35UP_SEL_EN_MASK 0x1
+#define MT6325_RG_VCORE2_1P35UP_SEL_EN_SHIFT 4
+#define MT6325_RG_VCORE2_RZSEL_MASK 0x7
+#define MT6325_RG_VCORE2_RZSEL_SHIFT 5
+#define MT6325_RG_VCORE2_CC_MASK 0x3
+#define MT6325_RG_VCORE2_CC_SHIFT 8
+#define MT6325_RG_VCORE2_CSR_MASK 0x7
+#define MT6325_RG_VCORE2_CSR_SHIFT 10
+#define MT6325_RG_VCORE2_CSL_MASK 0xF
+#define MT6325_RG_VCORE2_CSL_SHIFT 0
+#define MT6325_RG_VCORE2_SLP_MASK 0x7
+#define MT6325_RG_VCORE2_SLP_SHIFT 4
+#define MT6325_RG_VCORE2_ZX_OS_MASK 0x3
+#define MT6325_RG_VCORE2_ZX_OS_SHIFT 7
+#define MT6325_RG_VCORE2_ZXOS_TRIM_MASK 0x3F
+#define MT6325_RG_VCORE2_ZXOS_TRIM_SHIFT 9
+#define MT6325_RG_VCORE2_MODESET_MASK 0x1
+#define MT6325_RG_VCORE2_MODESET_SHIFT 15
+#define MT6325_RG_VCORE2_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCORE2_NDIS_EN_SHIFT 0
+#define MT6325_RG_VCORE2_CSM_MASK 0x3F
+#define MT6325_RG_VCORE2_CSM_SHIFT 1
+#define MT6325_RG_VCORE2_RSV_MASK 0xFF
+#define MT6325_RG_VCORE2_RSV_SHIFT 7
+#define MT6325_RG_VCORE2_PFM_RIP_MASK 0x7
+#define MT6325_RG_VCORE2_PFM_RIP_SHIFT 0
+#define MT6325_RG_VCORE2_TRAN_BST_MASK 0x3F
+#define MT6325_RG_VCORE2_TRAN_BST_SHIFT 3
+#define MT6325_RG_VCORE2_DTS_ENB_MASK 0x1
+#define MT6325_RG_VCORE2_DTS_ENB_SHIFT 9
+#define MT6325_RG_VCORE2_RCL_TRIM_MASK 0x1F
+#define MT6325_RG_VCORE2_RCL_TRIM_SHIFT 10
+#define MT6325_RG_VCORE2_RCL_TRIM_EN_MASK 0x1
+#define MT6325_RG_VCORE2_RCL_TRIM_EN_SHIFT 15
+#define MT6325_RG_VCORE2_C2_RSV_MASK 0x1
+#define MT6325_RG_VCORE2_C2_RSV_SHIFT 0
+#define MT6325_RG_VIO18_MIN_OFF_MASK 0x3
+#define MT6325_RG_VIO18_MIN_OFF_SHIFT 0
+#define MT6325_RG_VIO18_NVT_BUFF_OFF_EN_MASK 0x1
+#define MT6325_RG_VIO18_NVT_BUFF_OFF_EN_SHIFT 2
+#define MT6325_RG_VIO18_VRF18_SSTART_EN_MASK 0x1
+#define MT6325_RG_VIO18_VRF18_SSTART_EN_SHIFT 3
+#define MT6325_RG_VIO18_1P35UP_SEL_EN_MASK 0x1
+#define MT6325_RG_VIO18_1P35UP_SEL_EN_SHIFT 4
+#define MT6325_RG_VIO18_RZSEL_MASK 0x7
+#define MT6325_RG_VIO18_RZSEL_SHIFT 5
+#define MT6325_RG_VIO18_CC_MASK 0x3
+#define MT6325_RG_VIO18_CC_SHIFT 8
+#define MT6325_RG_VIO18_CSR_MASK 0x7
+#define MT6325_RG_VIO18_CSR_SHIFT 10
+#define MT6325_RG_VIO18_CSL_MASK 0xF
+#define MT6325_RG_VIO18_CSL_SHIFT 0
+#define MT6325_RG_VIO18_SLP_MASK 0x7
+#define MT6325_RG_VIO18_SLP_SHIFT 4
+#define MT6325_RG_VIO18_ZX_OS_MASK 0x3
+#define MT6325_RG_VIO18_ZX_OS_SHIFT 7
+#define MT6325_RG_VIO18_MODESET_MASK 0x1
+#define MT6325_RG_VIO18_MODESET_SHIFT 9
+#define MT6325_RG_VIO18_NDIS_EN_MASK 0x1
+#define MT6325_RG_VIO18_NDIS_EN_SHIFT 10
+#define MT6325_RG_VIO18_CSM_MASK 0x3F
+#define MT6325_RG_VIO18_CSM_SHIFT 0
+#define MT6325_RG_VIO18_RSV_MASK 0xFF
+#define MT6325_RG_VIO18_RSV_SHIFT 6
+#define MT6325_RG_VIO18_ZXOS_TRIM_MASK 0x3F
+#define MT6325_RG_VIO18_ZXOS_TRIM_SHIFT 0
+#define MT6325_RG_VIO18_PFM_RIP_MASK 0x7
+#define MT6325_RG_VIO18_PFM_RIP_SHIFT 6
+#define MT6325_RG_VIO18_TRAN_BST_MASK 0x3F
+#define MT6325_RG_VIO18_TRAN_BST_SHIFT 9
+#define MT6325_RG_VIO18_DTS_ENB_MASK 0x1
+#define MT6325_RG_VIO18_DTS_ENB_SHIFT 15
+#define MT6325_RG_VIO18_RCL_TRIM_MASK 0x1F
+#define MT6325_RG_VIO18_RCL_TRIM_SHIFT 0
+#define MT6325_RG_VIO18_RCL_TRIM_EN_MASK 0x1
+#define MT6325_RG_VIO18_RCL_TRIM_EN_SHIFT 5
+#define MT6325_RG_VIO18_C2_RSV_MASK 0x1
+#define MT6325_RG_VIO18_C2_RSV_SHIFT 6
+#define MT6325_RG_VRF1_MIN_OFF_MASK 0x3
+#define MT6325_RG_VRF1_MIN_OFF_SHIFT 0
+#define MT6325_RG_VRF18_0_NVT_BUFF_OFF_EN_MASK 0x1
+#define MT6325_RG_VRF18_0_NVT_BUFF_OFF_EN_SHIFT 2
+#define MT6325_RG_VRF18_0_SSTART_EN_MASK 0x1
+#define MT6325_RG_VRF18_0_SSTART_EN_SHIFT 3
+#define MT6325_RG_VRF18_0_1P35UP_SEL_EN_MASK 0x1
+#define MT6325_RG_VRF18_0_1P35UP_SEL_EN_SHIFT 4
+#define MT6325_RG_VRF18_0_RZSEL_MASK 0x7
+#define MT6325_RG_VRF18_0_RZSEL_SHIFT 5
+#define MT6325_RG_VRF18_0_CC_MASK 0x3
+#define MT6325_RG_VRF18_0_CC_SHIFT 8
+#define MT6325_RG_VRF18_0_CSR_MASK 0x7
+#define MT6325_RG_VRF18_0_CSR_SHIFT 10
+#define MT6325_RG_VRF18_0_CSL_MASK 0xF
+#define MT6325_RG_VRF18_0_CSL_SHIFT 0
+#define MT6325_RG_VRF18_0_SLP_MASK 0x7
+#define MT6325_RG_VRF18_0_SLP_SHIFT 4
+#define MT6325_RG_VRF18_0_ZX_OS_MASK 0x3
+#define MT6325_RG_VRF18_0_ZX_OS_SHIFT 7
+#define MT6325_RG_VRF18_0_ZXOS_TRIM_MASK 0x3F
+#define MT6325_RG_VRF18_0_ZXOS_TRIM_SHIFT 9
+#define MT6325_RG_VRF18_0_MODESET_MASK 0x1
+#define MT6325_RG_VRF18_0_MODESET_SHIFT 15
+#define MT6325_RG_VRF18_0_NDIS_EN_MASK 0x1
+#define MT6325_RG_VRF18_0_NDIS_EN_SHIFT 0
+#define MT6325_RG_VRF18_0_CSM_MASK 0x3F
+#define MT6325_RG_VRF18_0_CSM_SHIFT 1
+#define MT6325_RG_VRF18_0_RSV_MASK 0xFF
+#define MT6325_RG_VRF18_0_RSV_SHIFT 7
+#define MT6325_RG_VRF18_0_PFM_RIP_MASK 0x7
+#define MT6325_RG_VRF18_0_PFM_RIP_SHIFT 0
+#define MT6325_RG_VRF18_0_TRAN_BST_MASK 0x3F
+#define MT6325_RG_VRF18_0_TRAN_BST_SHIFT 3
+#define MT6325_RG_VRF18_0_DTS_ENB_MASK 0x1
+#define MT6325_RG_VRF18_0_DTS_ENB_SHIFT 9
+#define MT6325_RG_VRF18_0_RCL_TRIM_MASK 0x1F
+#define MT6325_RG_VRF18_0_RCL_TRIM_SHIFT 10
+#define MT6325_RG_VRF18_0_RCL_TRIM_EN_MASK 0x1
+#define MT6325_RG_VRF18_0_RCL_TRIM_EN_SHIFT 15
+#define MT6325_RG_VRF18_0_C2_RSV_MASK 0x1
+#define MT6325_RG_VRF18_0_C2_RSV_SHIFT 0
+#define MT6325_VDVFS11_DIG0_RSV0_MASK 0xFF
+#define MT6325_VDVFS11_DIG0_RSV0_SHIFT 8
+#define MT6325_VDVFS11_EN_CTRL_MASK 0x1
+#define MT6325_VDVFS11_EN_CTRL_SHIFT 0
+#define MT6325_VDVFS11_VOSEL_CTRL_MASK 0x1
+#define MT6325_VDVFS11_VOSEL_CTRL_SHIFT 1
+#define MT6325_VDVFS11_DIG0_RSV1_MASK 0x1
+#define MT6325_VDVFS11_DIG0_RSV1_SHIFT 2
+#define MT6325_VDVFS11_DIG1_RSV1_MASK 0x1
+#define MT6325_VDVFS11_DIG1_RSV1_SHIFT 3
+#define MT6325_VDVFS11_EN_SEL_MASK 0x3
+#define MT6325_VDVFS11_EN_SEL_SHIFT 0
+#define MT6325_VDVFS11_VOSEL_SEL_MASK 0x3
+#define MT6325_VDVFS11_VOSEL_SEL_SHIFT 4
+#define MT6325_VDVFS11_DIG0_RSV2_MASK 0x3
+#define MT6325_VDVFS11_DIG0_RSV2_SHIFT 8
+#define MT6325_VDVFS11_DIG1_RSV2_MASK 0x3
+#define MT6325_VDVFS11_DIG1_RSV2_SHIFT 12
+#define MT6325_VDVFS11_EN_MASK 0x1
+#define MT6325_VDVFS11_EN_SHIFT 0
+#define MT6325_VDVFS11_STBTD_MASK 0x3
+#define MT6325_VDVFS11_STBTD_SHIFT 4
+#define MT6325_QI_VDVFS11_STB_MASK 0x1
+#define MT6325_QI_VDVFS11_STB_SHIFT 12
+#define MT6325_QI_VDVFS11_EN_MASK 0x1
+#define MT6325_QI_VDVFS11_EN_SHIFT 13
+#define MT6325_QI_VDVFS11_OC_STATUS_MASK 0x1
+#define MT6325_QI_VDVFS11_OC_STATUS_SHIFT 15
+#define MT6325_VDVFS11_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VDVFS11_SFCHG_FRATE_SHIFT 0
+#define MT6325_VDVFS11_SFCHG_FEN_MASK 0x1
+#define MT6325_VDVFS11_SFCHG_FEN_SHIFT 7
+#define MT6325_VDVFS11_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VDVFS11_SFCHG_RRATE_SHIFT 8
+#define MT6325_VDVFS11_SFCHG_REN_MASK 0x1
+#define MT6325_VDVFS11_SFCHG_REN_SHIFT 15
+#define MT6325_VDVFS11_VOSEL_MASK 0x7F
+#define MT6325_VDVFS11_VOSEL_SHIFT 0
+#define MT6325_VDVFS11_VOSEL_ON_MASK 0x7F
+#define MT6325_VDVFS11_VOSEL_ON_SHIFT 0
+#define MT6325_VDVFS11_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VDVFS11_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VDVFS11_VOSEL_MASK 0x7F
+#define MT6325_NI_VDVFS11_VOSEL_SHIFT 0
+#define MT6325_VDVFS11_TRANS_TD_MASK 0x3
+#define MT6325_VDVFS11_TRANS_TD_SHIFT 0
+#define MT6325_VDVFS11_TRANS_CTRL_MASK 0x3
+#define MT6325_VDVFS11_TRANS_CTRL_SHIFT 4
+#define MT6325_VDVFS11_TRANS_ONCE_MASK 0x1
+#define MT6325_VDVFS11_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VDVFS11_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VDVFS11_VOSEL_TRANS_SHIFT 7
+#define MT6325_VDVFS11_VSLEEP_EN_MASK 0x1
+#define MT6325_VDVFS11_VSLEEP_EN_SHIFT 8
+#define MT6325_VDVFS11_R2R_PDN_MASK 0x1
+#define MT6325_VDVFS11_R2R_PDN_SHIFT 10
+#define MT6325_VDVFS11_VSLEEP_SEL_MASK 0x1
+#define MT6325_VDVFS11_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VDVFS11_R2R_PDN_MASK 0x1
+#define MT6325_NI_VDVFS11_R2R_PDN_SHIFT 14
+#define MT6325_NI_VDVFS11_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VDVFS11_VSLEEP_SEL_SHIFT 15
+#define MT6325_VDVFS12_DIG0_RSV0_MASK 0xFF
+#define MT6325_VDVFS12_DIG0_RSV0_SHIFT 8
+#define MT6325_VDVFS12_EN_CTRL_MASK 0x1
+#define MT6325_VDVFS12_EN_CTRL_SHIFT 0
+#define MT6325_VDVFS12_VOSEL_CTRL_MASK 0x1
+#define MT6325_VDVFS12_VOSEL_CTRL_SHIFT 1
+#define MT6325_VDVFS12_DIG0_RSV1_MASK 0x1
+#define MT6325_VDVFS12_DIG0_RSV1_SHIFT 2
+#define MT6325_VDVFS12_DIG1_RSV1_MASK 0x1
+#define MT6325_VDVFS12_DIG1_RSV1_SHIFT 3
+#define MT6325_VDVFS12_EN_SEL_MASK 0x3
+#define MT6325_VDVFS12_EN_SEL_SHIFT 0
+#define MT6325_VDVFS12_VOSEL_SEL_MASK 0x3
+#define MT6325_VDVFS12_VOSEL_SEL_SHIFT 4
+#define MT6325_VDVFS12_DIG0_RSV2_MASK 0x3
+#define MT6325_VDVFS12_DIG0_RSV2_SHIFT 8
+#define MT6325_VDVFS12_DIG1_RSV2_MASK 0x3
+#define MT6325_VDVFS12_DIG1_RSV2_SHIFT 12
+#define MT6325_VDVFS12_EN_MASK 0x1
+#define MT6325_VDVFS12_EN_SHIFT 0
+#define MT6325_VDVFS12_STBTD_MASK 0x3
+#define MT6325_VDVFS12_STBTD_SHIFT 4
+#define MT6325_QI_VDVFS12_STB_MASK 0x1
+#define MT6325_QI_VDVFS12_STB_SHIFT 12
+#define MT6325_QI_VDVFS12_EN_MASK 0x1
+#define MT6325_QI_VDVFS12_EN_SHIFT 13
+#define MT6325_QI_VDVFS12_OC_STATUS_MASK 0x1
+#define MT6325_QI_VDVFS12_OC_STATUS_SHIFT 15
+#define MT6325_VDVFS12_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VDVFS12_SFCHG_FRATE_SHIFT 0
+#define MT6325_VDVFS12_SFCHG_FEN_MASK 0x1
+#define MT6325_VDVFS12_SFCHG_FEN_SHIFT 7
+#define MT6325_VDVFS12_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VDVFS12_SFCHG_RRATE_SHIFT 8
+#define MT6325_VDVFS12_SFCHG_REN_MASK 0x1
+#define MT6325_VDVFS12_SFCHG_REN_SHIFT 15
+#define MT6325_VDVFS12_VOSEL_MASK 0x7F
+#define MT6325_VDVFS12_VOSEL_SHIFT 0
+#define MT6325_VDVFS12_VOSEL_ON_MASK 0x7F
+#define MT6325_VDVFS12_VOSEL_ON_SHIFT 0
+#define MT6325_VDVFS12_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VDVFS12_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VDVFS12_VOSEL_MASK 0x7F
+#define MT6325_NI_VDVFS12_VOSEL_SHIFT 0
+#define MT6325_VDVFS12_TRANS_TD_MASK 0x3
+#define MT6325_VDVFS12_TRANS_TD_SHIFT 0
+#define MT6325_VDVFS12_TRANS_CTRL_MASK 0x3
+#define MT6325_VDVFS12_TRANS_CTRL_SHIFT 4
+#define MT6325_VDVFS12_TRANS_ONCE_MASK 0x1
+#define MT6325_VDVFS12_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VDVFS12_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VDVFS12_VOSEL_TRANS_SHIFT 7
+#define MT6325_VDVFS12_VSLEEP_EN_MASK 0x1
+#define MT6325_VDVFS12_VSLEEP_EN_SHIFT 8
+#define MT6325_VDVFS12_R2R_PDN_MASK 0x1
+#define MT6325_VDVFS12_R2R_PDN_SHIFT 10
+#define MT6325_VDVFS12_VSLEEP_SEL_MASK 0x1
+#define MT6325_VDVFS12_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VDVFS12_R2R_PDN_MASK 0x1
+#define MT6325_NI_VDVFS12_R2R_PDN_SHIFT 14
+#define MT6325_NI_VDVFS12_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VDVFS12_VSLEEP_SEL_SHIFT 15
+#define MT6325_VSRAM_DVFS1_DIG0_RSV0_MASK 0xFF
+#define MT6325_VSRAM_DVFS1_DIG0_RSV0_SHIFT 8
+#define MT6325_VSRAM_DVFS1_EN_CTRL_MASK 0x1
+#define MT6325_VSRAM_DVFS1_EN_CTRL_SHIFT 0
+#define MT6325_VSRAM_DVFS1_VOSEL_CTRL_MASK 0x1
+#define MT6325_VSRAM_DVFS1_VOSEL_CTRL_SHIFT 1
+#define MT6325_VSRAM_DVFS1_DIG0_RSV1_MASK 0x1
+#define MT6325_VSRAM_DVFS1_DIG0_RSV1_SHIFT 2
+#define MT6325_VSRAM_DVFS1_DIG1_RSV1_MASK 0x1
+#define MT6325_VSRAM_DVFS1_DIG1_RSV1_SHIFT 3
+#define MT6325_VSRAM_DVFS1_EN_SEL_MASK 0x3
+#define MT6325_VSRAM_DVFS1_EN_SEL_SHIFT 0
+#define MT6325_VSRAM_DVFS1_VOSEL_SEL_MASK 0x3
+#define MT6325_VSRAM_DVFS1_VOSEL_SEL_SHIFT 4
+#define MT6325_VSRAM_DVFS1_DIG0_RSV2_MASK 0x3
+#define MT6325_VSRAM_DVFS1_DIG0_RSV2_SHIFT 8
+#define MT6325_VSRAM_DVFS1_DIG1_RSV2_MASK 0x3
+#define MT6325_VSRAM_DVFS1_DIG1_RSV2_SHIFT 12
+#define MT6325_VSRAM_DVFS1_EN_MASK 0x1
+#define MT6325_VSRAM_DVFS1_EN_SHIFT 0
+#define MT6325_VSRAM_DVFS1_STBTD_MASK 0x3
+#define MT6325_VSRAM_DVFS1_STBTD_SHIFT 4
+#define MT6325_VSRAM_DVFS1_DIG0_RSV4_MASK 0x1
+#define MT6325_VSRAM_DVFS1_DIG0_RSV4_SHIFT 12
+#define MT6325_VSRAM_DVFS1_DIG0_RSV3_MASK 0x1
+#define MT6325_VSRAM_DVFS1_DIG0_RSV3_SHIFT 13
+#define MT6325_QI_VSRAM_DVFS1_OC_STATUS_MASK 0x1
+#define MT6325_QI_VSRAM_DVFS1_OC_STATUS_SHIFT 15
+#define MT6325_VSRAM_DVFS1_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_SFCHG_FRATE_SHIFT 0
+#define MT6325_VSRAM_DVFS1_SFCHG_FEN_MASK 0x1
+#define MT6325_VSRAM_DVFS1_SFCHG_FEN_SHIFT 7
+#define MT6325_VSRAM_DVFS1_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_SFCHG_RRATE_SHIFT 8
+#define MT6325_VSRAM_DVFS1_SFCHG_REN_MASK 0x1
+#define MT6325_VSRAM_DVFS1_SFCHG_REN_SHIFT 15
+#define MT6325_VSRAM_DVFS1_VOSEL_RSV_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_RSV_SHIFT 0
+#define MT6325_VSRAM_DVFS1_VOSEL_ON_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_ON_SHIFT 0
+#define MT6325_VSRAM_DVFS1_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VSRAM_DVFS1_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VSRAM_DVFS1_VOSEL_MASK 0x7F
+#define MT6325_NI_VSRAM_DVFS1_VOSEL_SHIFT 0
+#define MT6325_VSRAM_DVFS1_TRANS_TD_MASK 0x3
+#define MT6325_VSRAM_DVFS1_TRANS_TD_SHIFT 0
+#define MT6325_VSRAM_DVFS1_TRANS_CTRL_MASK 0x3
+#define MT6325_VSRAM_DVFS1_TRANS_CTRL_SHIFT 4
+#define MT6325_VSRAM_DVFS1_TRANS_ONCE_MASK 0x1
+#define MT6325_VSRAM_DVFS1_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VSRAM_DVFS1_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VSRAM_DVFS1_VOSEL_TRANS_SHIFT 7
+#define MT6325_VSRAM_DVFS1_VSLEEP_EN_MASK 0x1
+#define MT6325_VSRAM_DVFS1_VSLEEP_EN_SHIFT 8
+#define MT6325_VSRAM_DVFS1_R2R_PDN_MASK 0x1
+#define MT6325_VSRAM_DVFS1_R2R_PDN_SHIFT 10
+#define MT6325_VSRAM_DVFS1_VSLEEP_SEL_MASK 0x1
+#define MT6325_VSRAM_DVFS1_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VSRAM_DVFS1_R2R_PDN_MASK 0x1
+#define MT6325_NI_VSRAM_DVFS1_R2R_PDN_SHIFT 14
+#define MT6325_NI_VSRAM_DVFS1_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VSRAM_DVFS1_VSLEEP_SEL_SHIFT 15
+#define MT6325_VDRAM_DIG0_RSV0_MASK 0xFF
+#define MT6325_VDRAM_DIG0_RSV0_SHIFT 8
+#define MT6325_VDRAM_EN_CTRL_MASK 0x1
+#define MT6325_VDRAM_EN_CTRL_SHIFT 0
+#define MT6325_VDRAM_VOSEL_CTRL_MASK 0x1
+#define MT6325_VDRAM_VOSEL_CTRL_SHIFT 1
+#define MT6325_VDRAM_DIG0_RSV1_MASK 0x1
+#define MT6325_VDRAM_DIG0_RSV1_SHIFT 2
+#define MT6325_VDRAM_BURST_CTRL_MASK 0x1
+#define MT6325_VDRAM_BURST_CTRL_SHIFT 3
+#define MT6325_VDRAM_EN_SEL_MASK 0x3
+#define MT6325_VDRAM_EN_SEL_SHIFT 0
+#define MT6325_VDRAM_VOSEL_SEL_MASK 0x3
+#define MT6325_VDRAM_VOSEL_SEL_SHIFT 4
+#define MT6325_VDRAM_DIG0_RSV2_MASK 0x3
+#define MT6325_VDRAM_DIG0_RSV2_SHIFT 8
+#define MT6325_VDRAM_BURST_SEL_MASK 0x3
+#define MT6325_VDRAM_BURST_SEL_SHIFT 12
+#define MT6325_VDRAM_EN_MASK 0x1
+#define MT6325_VDRAM_EN_SHIFT 0
+#define MT6325_VDRAM_STBTD_MASK 0x3
+#define MT6325_VDRAM_STBTD_SHIFT 4
+#define MT6325_QI_VDRAM_STB_MASK 0x1
+#define MT6325_QI_VDRAM_STB_SHIFT 12
+#define MT6325_QI_VDRAM_EN_MASK 0x1
+#define MT6325_QI_VDRAM_EN_SHIFT 13
+#define MT6325_QI_VDRAM_OC_STATUS_MASK 0x1
+#define MT6325_QI_VDRAM_OC_STATUS_SHIFT 15
+#define MT6325_VDRAM_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VDRAM_SFCHG_FRATE_SHIFT 0
+#define MT6325_VDRAM_SFCHG_FEN_MASK 0x1
+#define MT6325_VDRAM_SFCHG_FEN_SHIFT 7
+#define MT6325_VDRAM_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VDRAM_SFCHG_RRATE_SHIFT 8
+#define MT6325_VDRAM_SFCHG_REN_MASK 0x1
+#define MT6325_VDRAM_SFCHG_REN_SHIFT 15
+#define MT6325_VDRAM_VOSEL_MASK 0x7F
+#define MT6325_VDRAM_VOSEL_SHIFT 0
+#define MT6325_VDRAM_VOSEL_ON_MASK 0x7F
+#define MT6325_VDRAM_VOSEL_ON_SHIFT 0
+#define MT6325_VDRAM_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VDRAM_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VDRAM_VOSEL_MASK 0x7F
+#define MT6325_NI_VDRAM_VOSEL_SHIFT 0
+#define MT6325_VDRAM_BURST_MASK 0x7
+#define MT6325_VDRAM_BURST_SHIFT 0
+#define MT6325_VDRAM_BURST_ON_MASK 0x7
+#define MT6325_VDRAM_BURST_ON_SHIFT 4
+#define MT6325_VDRAM_BURST_SLEEP_MASK 0x7
+#define MT6325_VDRAM_BURST_SLEEP_SHIFT 8
+#define MT6325_QI_VDRAM_BURST_MASK 0x7
+#define MT6325_QI_VDRAM_BURST_SHIFT 12
+#define MT6325_VDRAM_TRANS_TD_MASK 0x3
+#define MT6325_VDRAM_TRANS_TD_SHIFT 0
+#define MT6325_VDRAM_TRANS_CTRL_MASK 0x3
+#define MT6325_VDRAM_TRANS_CTRL_SHIFT 4
+#define MT6325_VDRAM_TRANS_ONCE_MASK 0x1
+#define MT6325_VDRAM_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VDRAM_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VDRAM_VOSEL_TRANS_SHIFT 7
+#define MT6325_VDRAM_VSLEEP_EN_MASK 0x1
+#define MT6325_VDRAM_VSLEEP_EN_SHIFT 8
+#define MT6325_VDRAM_R2R_PDN_MASK 0x1
+#define MT6325_VDRAM_R2R_PDN_SHIFT 10
+#define MT6325_VDRAM_VSLEEP_SEL_MASK 0x1
+#define MT6325_VDRAM_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VDRAM_R2R_PDN_MASK 0x1
+#define MT6325_NI_VDRAM_R2R_PDN_SHIFT 14
+#define MT6325_NI_VDRAM_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VDRAM_VSLEEP_SEL_SHIFT 15
+#define MT6325_VRF18_0_DIG0_RSV0_MASK 0xFF
+#define MT6325_VRF18_0_DIG0_RSV0_SHIFT 8
+#define MT6325_VRF18_0_EN_CTRL_MASK 0x1
+#define MT6325_VRF18_0_EN_CTRL_SHIFT 0
+#define MT6325_VRF18_0_VOSEL_CTRL_MASK 0x1
+#define MT6325_VRF18_0_VOSEL_CTRL_SHIFT 1
+#define MT6325_VRF18_0_DIG0_RSV1_MASK 0x1
+#define MT6325_VRF18_0_DIG0_RSV1_SHIFT 2
+#define MT6325_VRF18_0_BURST_CTRL_MASK 0x1
+#define MT6325_VRF18_0_BURST_CTRL_SHIFT 3
+#define MT6325_VRF18_0_EN_SEL_MASK 0x3
+#define MT6325_VRF18_0_EN_SEL_SHIFT 0
+#define MT6325_VRF18_0_VOSEL_SEL_MASK 0x3
+#define MT6325_VRF18_0_VOSEL_SEL_SHIFT 4
+#define MT6325_VRF18_0_DIG0_RSV2_MASK 0x3
+#define MT6325_VRF18_0_DIG0_RSV2_SHIFT 8
+#define MT6325_VRF18_0_BURST_SEL_MASK 0x3
+#define MT6325_VRF18_0_BURST_SEL_SHIFT 12
+#define MT6325_VRF18_0_EN_MASK 0x1
+#define MT6325_VRF18_0_EN_SHIFT 0
+#define MT6325_VRF18_0_STBTD_MASK 0x3
+#define MT6325_VRF18_0_STBTD_SHIFT 4
+#define MT6325_QI_VRF18_0_STB_MASK 0x1
+#define MT6325_QI_VRF18_0_STB_SHIFT 12
+#define MT6325_QI_VRF18_0_EN_MASK 0x1
+#define MT6325_QI_VRF18_0_EN_SHIFT 13
+#define MT6325_QI_VRF18_0_OC_STATUS_MASK 0x1
+#define MT6325_QI_VRF18_0_OC_STATUS_SHIFT 15
+#define MT6325_VRF18_0_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VRF18_0_SFCHG_FRATE_SHIFT 0
+#define MT6325_VRF18_0_SFCHG_FEN_MASK 0x1
+#define MT6325_VRF18_0_SFCHG_FEN_SHIFT 7
+#define MT6325_VRF18_0_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VRF18_0_SFCHG_RRATE_SHIFT 8
+#define MT6325_VRF18_0_SFCHG_REN_MASK 0x1
+#define MT6325_VRF18_0_SFCHG_REN_SHIFT 15
+#define MT6325_VRF18_0_VOSEL_MASK 0x7F
+#define MT6325_VRF18_0_VOSEL_SHIFT 0
+#define MT6325_VRF18_0_VOSEL_ON_MASK 0x7F
+#define MT6325_VRF18_0_VOSEL_ON_SHIFT 0
+#define MT6325_VRF18_0_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VRF18_0_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VRF18_0_VOSEL_MASK 0x7F
+#define MT6325_NI_VRF18_0_VOSEL_SHIFT 0
+#define MT6325_VRF18_0_BURST_MASK 0x7
+#define MT6325_VRF18_0_BURST_SHIFT 0
+#define MT6325_VRF18_0_BURST_ON_MASK 0x7
+#define MT6325_VRF18_0_BURST_ON_SHIFT 4
+#define MT6325_VRF18_0_BURST_SLEEP_MASK 0x7
+#define MT6325_VRF18_0_BURST_SLEEP_SHIFT 8
+#define MT6325_QI_VRF18_0_BURST_MASK 0x7
+#define MT6325_QI_VRF18_0_BURST_SHIFT 12
+#define MT6325_VRF18_0_TRANS_TD_MASK 0x3
+#define MT6325_VRF18_0_TRANS_TD_SHIFT 0
+#define MT6325_VRF18_0_TRANS_CTRL_MASK 0x3
+#define MT6325_VRF18_0_TRANS_CTRL_SHIFT 4
+#define MT6325_VRF18_0_TRANS_ONCE_MASK 0x1
+#define MT6325_VRF18_0_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VRF18_0_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VRF18_0_VOSEL_TRANS_SHIFT 7
+#define MT6325_VRF18_0_VSLEEP_EN_MASK 0x1
+#define MT6325_VRF18_0_VSLEEP_EN_SHIFT 8
+#define MT6325_VRF18_0_R2R_PDN_MASK 0x1
+#define MT6325_VRF18_0_R2R_PDN_SHIFT 10
+#define MT6325_VRF18_0_VSLEEP_SEL_MASK 0x1
+#define MT6325_VRF18_0_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VRF18_0_R2R_PDN_MASK 0x1
+#define MT6325_NI_VRF18_0_R2R_PDN_SHIFT 14
+#define MT6325_NI_VRF18_0_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VRF18_0_VSLEEP_SEL_SHIFT 15
+#define MT6325_VGPU_DIG0_RSV0_MASK 0xFF
+#define MT6325_VGPU_DIG0_RSV0_SHIFT 8
+#define MT6325_VGPU_EN_CTRL_MASK 0x1
+#define MT6325_VGPU_EN_CTRL_SHIFT 0
+#define MT6325_VGPU_VOSEL_CTRL_MASK 0x1
+#define MT6325_VGPU_VOSEL_CTRL_SHIFT 1
+#define MT6325_VGPU_DLC_CTRL_MASK 0x1
+#define MT6325_VGPU_DLC_CTRL_SHIFT 2
+#define MT6325_VGPU_BURST_CTRL_MASK 0x1
+#define MT6325_VGPU_BURST_CTRL_SHIFT 3
+#define MT6325_VGPU_EN_SEL_MASK 0x3
+#define MT6325_VGPU_EN_SEL_SHIFT 0
+#define MT6325_VGPU_VOSEL_SEL_MASK 0x3
+#define MT6325_VGPU_VOSEL_SEL_SHIFT 4
+#define MT6325_VGPU_DLC_SEL_MASK 0x3
+#define MT6325_VGPU_DLC_SEL_SHIFT 8
+#define MT6325_VGPU_BURST_SEL_MASK 0x3
+#define MT6325_VGPU_BURST_SEL_SHIFT 12
+#define MT6325_VGPU_EN_MASK 0x1
+#define MT6325_VGPU_EN_SHIFT 0
+#define MT6325_VGPU_STBTD_MASK 0x3
+#define MT6325_VGPU_STBTD_SHIFT 4
+#define MT6325_QI_VGPU_STB_MASK 0x1
+#define MT6325_QI_VGPU_STB_SHIFT 12
+#define MT6325_QI_VGPU_EN_MASK 0x1
+#define MT6325_QI_VGPU_EN_SHIFT 13
+#define MT6325_QI_VGPU_OC_STATUS_MASK 0x1
+#define MT6325_QI_VGPU_OC_STATUS_SHIFT 15
+#define MT6325_VGPU_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VGPU_SFCHG_FRATE_SHIFT 0
+#define MT6325_VGPU_SFCHG_FEN_MASK 0x1
+#define MT6325_VGPU_SFCHG_FEN_SHIFT 7
+#define MT6325_VGPU_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VGPU_SFCHG_RRATE_SHIFT 8
+#define MT6325_VGPU_SFCHG_REN_MASK 0x1
+#define MT6325_VGPU_SFCHG_REN_SHIFT 15
+#define MT6325_VGPU_VOSEL_MASK 0x7F
+#define MT6325_VGPU_VOSEL_SHIFT 0
+#define MT6325_VGPU_VOSEL_ON_MASK 0x7F
+#define MT6325_VGPU_VOSEL_ON_SHIFT 0
+#define MT6325_VGPU_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VGPU_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VGPU_VOSEL_MASK 0x7F
+#define MT6325_NI_VGPU_VOSEL_SHIFT 0
+#define MT6325_VGPU_BURST_MASK 0x7
+#define MT6325_VGPU_BURST_SHIFT 0
+#define MT6325_VGPU_BURST_ON_MASK 0x7
+#define MT6325_VGPU_BURST_ON_SHIFT 4
+#define MT6325_VGPU_BURST_SLEEP_MASK 0x7
+#define MT6325_VGPU_BURST_SLEEP_SHIFT 8
+#define MT6325_QI_VGPU_BURST_MASK 0x7
+#define MT6325_QI_VGPU_BURST_SHIFT 12
+#define MT6325_VGPU_DLC_MASK 0x3
+#define MT6325_VGPU_DLC_SHIFT 0
+#define MT6325_VGPU_DLC_ON_MASK 0x3
+#define MT6325_VGPU_DLC_ON_SHIFT 4
+#define MT6325_VGPU_DLC_SLEEP_MASK 0x3
+#define MT6325_VGPU_DLC_SLEEP_SHIFT 8
+#define MT6325_QI_VGPU_DLC_MASK 0x3
+#define MT6325_QI_VGPU_DLC_SHIFT 12
+#define MT6325_VGPU_DLC_N_MASK 0x3
+#define MT6325_VGPU_DLC_N_SHIFT 0
+#define MT6325_VGPU_DLC_N_ON_MASK 0x3
+#define MT6325_VGPU_DLC_N_ON_SHIFT 4
+#define MT6325_VGPU_DLC_N_SLEEP_MASK 0x3
+#define MT6325_VGPU_DLC_N_SLEEP_SHIFT 8
+#define MT6325_QI_VGPU_DLC_N_MASK 0x3
+#define MT6325_QI_VGPU_DLC_N_SHIFT 12
+#define MT6325_VGPU_TRANS_TD_MASK 0x3
+#define MT6325_VGPU_TRANS_TD_SHIFT 0
+#define MT6325_VGPU_TRANS_CTRL_MASK 0x3
+#define MT6325_VGPU_TRANS_CTRL_SHIFT 4
+#define MT6325_VGPU_TRANS_ONCE_MASK 0x1
+#define MT6325_VGPU_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VGPU_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VGPU_VOSEL_TRANS_SHIFT 7
+#define MT6325_VGPU_VSLEEP_EN_MASK 0x1
+#define MT6325_VGPU_VSLEEP_EN_SHIFT 8
+#define MT6325_VGPU_R2R_PDN_MASK 0x1
+#define MT6325_VGPU_R2R_PDN_SHIFT 10
+#define MT6325_VGPU_VSLEEP_SEL_MASK 0x1
+#define MT6325_VGPU_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VGPU_R2R_PDN_MASK 0x1
+#define MT6325_NI_VGPU_R2R_PDN_SHIFT 14
+#define MT6325_NI_VGPU_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VGPU_VSLEEP_SEL_SHIFT 15
+#define MT6325_VCORE1_DIG0_RSV0_MASK 0xFF
+#define MT6325_VCORE1_DIG0_RSV0_SHIFT 8
+#define MT6325_VCORE1_EN_CTRL_MASK 0x1
+#define MT6325_VCORE1_EN_CTRL_SHIFT 0
+#define MT6325_VCORE1_VOSEL_CTRL_MASK 0x1
+#define MT6325_VCORE1_VOSEL_CTRL_SHIFT 1
+#define MT6325_VCORE1_DLC_CTRL_MASK 0x1
+#define MT6325_VCORE1_DLC_CTRL_SHIFT 2
+#define MT6325_VCORE1_BURST_CTRL_MASK 0x1
+#define MT6325_VCORE1_BURST_CTRL_SHIFT 3
+#define MT6325_VCORE1_EN_SEL_MASK 0x3
+#define MT6325_VCORE1_EN_SEL_SHIFT 0
+#define MT6325_VCORE1_VOSEL_SEL_MASK 0x3
+#define MT6325_VCORE1_VOSEL_SEL_SHIFT 4
+#define MT6325_VCORE1_DLC_SEL_MASK 0x3
+#define MT6325_VCORE1_DLC_SEL_SHIFT 8
+#define MT6325_VCORE1_BURST_SEL_MASK 0x3
+#define MT6325_VCORE1_BURST_SEL_SHIFT 12
+#define MT6325_VCORE1_EN_MASK 0x1
+#define MT6325_VCORE1_EN_SHIFT 0
+#define MT6325_VCORE1_STBTD_MASK 0x3
+#define MT6325_VCORE1_STBTD_SHIFT 4
+#define MT6325_QI_VCORE1_STB_MASK 0x1
+#define MT6325_QI_VCORE1_STB_SHIFT 12
+#define MT6325_QI_VCORE1_EN_MASK 0x1
+#define MT6325_QI_VCORE1_EN_SHIFT 13
+#define MT6325_QI_VCORE1_OC_STATUS_MASK 0x1
+#define MT6325_QI_VCORE1_OC_STATUS_SHIFT 15
+#define MT6325_VCORE1_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VCORE1_SFCHG_FRATE_SHIFT 0
+#define MT6325_VCORE1_SFCHG_FEN_MASK 0x1
+#define MT6325_VCORE1_SFCHG_FEN_SHIFT 7
+#define MT6325_VCORE1_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VCORE1_SFCHG_RRATE_SHIFT 8
+#define MT6325_VCORE1_SFCHG_REN_MASK 0x1
+#define MT6325_VCORE1_SFCHG_REN_SHIFT 15
+#define MT6325_VCORE1_VOSEL_MASK 0x7F
+#define MT6325_VCORE1_VOSEL_SHIFT 0
+#define MT6325_VCORE1_VOSEL_ON_MASK 0x7F
+#define MT6325_VCORE1_VOSEL_ON_SHIFT 0
+#define MT6325_VCORE1_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VCORE1_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VCORE1_VOSEL_MASK 0x7F
+#define MT6325_NI_VCORE1_VOSEL_SHIFT 0
+#define MT6325_VCORE1_BURST_MASK 0x7
+#define MT6325_VCORE1_BURST_SHIFT 0
+#define MT6325_VCORE1_BURST_ON_MASK 0x7
+#define MT6325_VCORE1_BURST_ON_SHIFT 4
+#define MT6325_VCORE1_BURST_SLEEP_MASK 0x7
+#define MT6325_VCORE1_BURST_SLEEP_SHIFT 8
+#define MT6325_QI_VCORE1_BURST_MASK 0x7
+#define MT6325_QI_VCORE1_BURST_SHIFT 12
+#define MT6325_VCORE1_DLC_MASK 0x3
+#define MT6325_VCORE1_DLC_SHIFT 0
+#define MT6325_VCORE1_DLC_ON_MASK 0x3
+#define MT6325_VCORE1_DLC_ON_SHIFT 4
+#define MT6325_VCORE1_DLC_SLEEP_MASK 0x3
+#define MT6325_VCORE1_DLC_SLEEP_SHIFT 8
+#define MT6325_QI_VCORE1_DLC_MASK 0x3
+#define MT6325_QI_VCORE1_DLC_SHIFT 12
+#define MT6325_VCORE1_DLC_N_MASK 0x3
+#define MT6325_VCORE1_DLC_N_SHIFT 0
+#define MT6325_VCORE1_DLC_N_ON_MASK 0x3
+#define MT6325_VCORE1_DLC_N_ON_SHIFT 4
+#define MT6325_VCORE1_DLC_N_SLEEP_MASK 0x3
+#define MT6325_VCORE1_DLC_N_SLEEP_SHIFT 8
+#define MT6325_QI_VCORE1_DLC_N_MASK 0x3
+#define MT6325_QI_VCORE1_DLC_N_SHIFT 12
+#define MT6325_VCORE1_TRANS_TD_MASK 0x3
+#define MT6325_VCORE1_TRANS_TD_SHIFT 0
+#define MT6325_VCORE1_TRANS_CTRL_MASK 0x3
+#define MT6325_VCORE1_TRANS_CTRL_SHIFT 4
+#define MT6325_VCORE1_TRANS_ONCE_MASK 0x1
+#define MT6325_VCORE1_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VCORE1_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VCORE1_VOSEL_TRANS_SHIFT 7
+#define MT6325_VCORE1_VSLEEP_EN_MASK 0x1
+#define MT6325_VCORE1_VSLEEP_EN_SHIFT 8
+#define MT6325_VCORE1_R2R_PDN_MASK 0x1
+#define MT6325_VCORE1_R2R_PDN_SHIFT 10
+#define MT6325_VCORE1_VSLEEP_SEL_MASK 0x1
+#define MT6325_VCORE1_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VCORE1_R2R_PDN_MASK 0x1
+#define MT6325_NI_VCORE1_R2R_PDN_SHIFT 14
+#define MT6325_NI_VCORE1_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VCORE1_VSLEEP_SEL_SHIFT 15
+#define MT6325_VCORE2_DIG0_RSV0_MASK 0xFF
+#define MT6325_VCORE2_DIG0_RSV0_SHIFT 8
+#define MT6325_VCORE2_EN_CTRL_MASK 0x1
+#define MT6325_VCORE2_EN_CTRL_SHIFT 0
+#define MT6325_VCORE2_VOSEL_CTRL_MASK 0x1
+#define MT6325_VCORE2_VOSEL_CTRL_SHIFT 1
+#define MT6325_VCORE2_DLC_CTRL_MASK 0x1
+#define MT6325_VCORE2_DLC_CTRL_SHIFT 2
+#define MT6325_VCORE2_BURST_CTRL_MASK 0x1
+#define MT6325_VCORE2_BURST_CTRL_SHIFT 3
+#define MT6325_VCORE2_EN_SEL_MASK 0x3
+#define MT6325_VCORE2_EN_SEL_SHIFT 0
+#define MT6325_VCORE2_VOSEL_SEL_MASK 0x3
+#define MT6325_VCORE2_VOSEL_SEL_SHIFT 4
+#define MT6325_VCORE2_DLC_SEL_MASK 0x3
+#define MT6325_VCORE2_DLC_SEL_SHIFT 8
+#define MT6325_VCORE2_BURST_SEL_MASK 0x3
+#define MT6325_VCORE2_BURST_SEL_SHIFT 12
+#define MT6325_VCORE2_EN_MASK 0x1
+#define MT6325_VCORE2_EN_SHIFT 0
+#define MT6325_VCORE2_STBTD_MASK 0x3
+#define MT6325_VCORE2_STBTD_SHIFT 4
+#define MT6325_QI_VCORE2_STB_MASK 0x1
+#define MT6325_QI_VCORE2_STB_SHIFT 12
+#define MT6325_QI_VCORE2_EN_MASK 0x1
+#define MT6325_QI_VCORE2_EN_SHIFT 13
+#define MT6325_QI_VCORE2_OC_STATUS_MASK 0x1
+#define MT6325_QI_VCORE2_OC_STATUS_SHIFT 15
+#define MT6325_VCORE2_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VCORE2_SFCHG_FRATE_SHIFT 0
+#define MT6325_VCORE2_SFCHG_FEN_MASK 0x1
+#define MT6325_VCORE2_SFCHG_FEN_SHIFT 7
+#define MT6325_VCORE2_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VCORE2_SFCHG_RRATE_SHIFT 8
+#define MT6325_VCORE2_SFCHG_REN_MASK 0x1
+#define MT6325_VCORE2_SFCHG_REN_SHIFT 15
+#define MT6325_VCORE2_VOSEL_MASK 0x7F
+#define MT6325_VCORE2_VOSEL_SHIFT 0
+#define MT6325_VCORE2_VOSEL_ON_MASK 0x7F
+#define MT6325_VCORE2_VOSEL_ON_SHIFT 0
+#define MT6325_VCORE2_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VCORE2_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VCORE2_VOSEL_MASK 0x7F
+#define MT6325_NI_VCORE2_VOSEL_SHIFT 0
+#define MT6325_VCORE2_BURST_MASK 0x7
+#define MT6325_VCORE2_BURST_SHIFT 0
+#define MT6325_VCORE2_BURST_ON_MASK 0x7
+#define MT6325_VCORE2_BURST_ON_SHIFT 4
+#define MT6325_VCORE2_BURST_SLEEP_MASK 0x7
+#define MT6325_VCORE2_BURST_SLEEP_SHIFT 8
+#define MT6325_QI_VCORE2_BURST_MASK 0x7
+#define MT6325_QI_VCORE2_BURST_SHIFT 12
+#define MT6325_VCORE2_DLC_MASK 0x3
+#define MT6325_VCORE2_DLC_SHIFT 0
+#define MT6325_VCORE2_DLC_ON_MASK 0x3
+#define MT6325_VCORE2_DLC_ON_SHIFT 4
+#define MT6325_VCORE2_DLC_SLEEP_MASK 0x3
+#define MT6325_VCORE2_DLC_SLEEP_SHIFT 8
+#define MT6325_QI_VCORE2_DLC_MASK 0x3
+#define MT6325_QI_VCORE2_DLC_SHIFT 12
+#define MT6325_VCORE2_DLC_N_MASK 0x3
+#define MT6325_VCORE2_DLC_N_SHIFT 0
+#define MT6325_VCORE2_DLC_N_ON_MASK 0x3
+#define MT6325_VCORE2_DLC_N_ON_SHIFT 4
+#define MT6325_VCORE2_DLC_N_SLEEP_MASK 0x3
+#define MT6325_VCORE2_DLC_N_SLEEP_SHIFT 8
+#define MT6325_QI_VCORE2_DLC_N_MASK 0x3
+#define MT6325_QI_VCORE2_DLC_N_SHIFT 12
+#define MT6325_VCORE2_TRANS_TD_MASK 0x3
+#define MT6325_VCORE2_TRANS_TD_SHIFT 0
+#define MT6325_VCORE2_TRANS_CTRL_MASK 0x3
+#define MT6325_VCORE2_TRANS_CTRL_SHIFT 4
+#define MT6325_VCORE2_TRANS_ONCE_MASK 0x1
+#define MT6325_VCORE2_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VCORE2_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VCORE2_VOSEL_TRANS_SHIFT 7
+#define MT6325_VCORE2_VSLEEP_EN_MASK 0x1
+#define MT6325_VCORE2_VSLEEP_EN_SHIFT 8
+#define MT6325_VCORE2_R2R_PDN_MASK 0x1
+#define MT6325_VCORE2_R2R_PDN_SHIFT 10
+#define MT6325_VCORE2_VSLEEP_SEL_MASK 0x1
+#define MT6325_VCORE2_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VCORE2_R2R_PDN_MASK 0x1
+#define MT6325_NI_VCORE2_R2R_PDN_SHIFT 14
+#define MT6325_NI_VCORE2_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VCORE2_VSLEEP_SEL_SHIFT 15
+#define MT6325_VCORE2_VOSEL_AUD_MASK 0x7F
+#define MT6325_VCORE2_VOSEL_AUD_SHIFT 0
+#define MT6325_BUCK_DVFS_DONE_MASK 0x1
+#define MT6325_BUCK_DVFS_DONE_SHIFT 0
+#define MT6325_BUCK_DVFS_DONE_SW_MASK 0x1
+#define MT6325_BUCK_DVFS_DONE_SW_SHIFT 1
+#define MT6325_VCORE_DVFS_DONE_STA_MASK 0x1
+#define MT6325_VCORE_DVFS_DONE_STA_SHIFT 2
+#define MT6325_VIO18_DIG0_RSV0_MASK 0xFF
+#define MT6325_VIO18_DIG0_RSV0_SHIFT 8
+#define MT6325_VIO18_EN_CTRL_MASK 0x1
+#define MT6325_VIO18_EN_CTRL_SHIFT 0
+#define MT6325_VIO18_VOSEL_CTRL_MASK 0x1
+#define MT6325_VIO18_VOSEL_CTRL_SHIFT 1
+#define MT6325_VIO18_DLC_CTRL_MASK 0x1
+#define MT6325_VIO18_DLC_CTRL_SHIFT 2
+#define MT6325_VIO18_BURST_CTRL_MASK 0x1
+#define MT6325_VIO18_BURST_CTRL_SHIFT 3
+#define MT6325_VIO18_EN_SEL_MASK 0x3
+#define MT6325_VIO18_EN_SEL_SHIFT 0
+#define MT6325_VIO18_VOSEL_SEL_MASK 0x3
+#define MT6325_VIO18_VOSEL_SEL_SHIFT 4
+#define MT6325_VIO18_DLC_SEL_MASK 0x3
+#define MT6325_VIO18_DLC_SEL_SHIFT 8
+#define MT6325_VIO18_BURST_SEL_MASK 0x3
+#define MT6325_VIO18_BURST_SEL_SHIFT 12
+#define MT6325_VIO18_EN_MASK 0x1
+#define MT6325_VIO18_EN_SHIFT 0
+#define MT6325_VIO18_STBTD_MASK 0x3
+#define MT6325_VIO18_STBTD_SHIFT 4
+#define MT6325_QI_VIO18_STB_MASK 0x1
+#define MT6325_QI_VIO18_STB_SHIFT 12
+#define MT6325_QI_VIO18_EN_MASK 0x1
+#define MT6325_QI_VIO18_EN_SHIFT 13
+#define MT6325_QI_VIO18_OC_STATUS_MASK 0x1
+#define MT6325_QI_VIO18_OC_STATUS_SHIFT 15
+#define MT6325_VIO18_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VIO18_SFCHG_FRATE_SHIFT 0
+#define MT6325_VIO18_SFCHG_FEN_MASK 0x1
+#define MT6325_VIO18_SFCHG_FEN_SHIFT 7
+#define MT6325_VIO18_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VIO18_SFCHG_RRATE_SHIFT 8
+#define MT6325_VIO18_SFCHG_REN_MASK 0x1
+#define MT6325_VIO18_SFCHG_REN_SHIFT 15
+#define MT6325_VIO18_VOSEL_MASK 0x7F
+#define MT6325_VIO18_VOSEL_SHIFT 0
+#define MT6325_VIO18_VOSEL_ON_MASK 0x7F
+#define MT6325_VIO18_VOSEL_ON_SHIFT 0
+#define MT6325_VIO18_VOSEL_SLEEP_MASK 0x7F
+#define MT6325_VIO18_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VIO18_VOSEL_MASK 0x7F
+#define MT6325_NI_VIO18_VOSEL_SHIFT 0
+#define MT6325_VIO18_BURST_MASK 0x7
+#define MT6325_VIO18_BURST_SHIFT 0
+#define MT6325_VIO18_BURST_ON_MASK 0x7
+#define MT6325_VIO18_BURST_ON_SHIFT 4
+#define MT6325_VIO18_BURST_SLEEP_MASK 0x7
+#define MT6325_VIO18_BURST_SLEEP_SHIFT 8
+#define MT6325_QI_VIO18_BURST_MASK 0x7
+#define MT6325_QI_VIO18_BURST_SHIFT 12
+#define MT6325_VIO18_DLC_MASK 0x3
+#define MT6325_VIO18_DLC_SHIFT 0
+#define MT6325_VIO18_DLC_ON_MASK 0x3
+#define MT6325_VIO18_DLC_ON_SHIFT 4
+#define MT6325_VIO18_DLC_SLEEP_MASK 0x3
+#define MT6325_VIO18_DLC_SLEEP_SHIFT 8
+#define MT6325_QI_VIO18_DLC_MASK 0x3
+#define MT6325_QI_VIO18_DLC_SHIFT 12
+#define MT6325_VIO18_DLC_N_MASK 0x3
+#define MT6325_VIO18_DLC_N_SHIFT 0
+#define MT6325_VIO18_DLC_N_ON_MASK 0x3
+#define MT6325_VIO18_DLC_N_ON_SHIFT 4
+#define MT6325_VIO18_DLC_N_SLEEP_MASK 0x3
+#define MT6325_VIO18_DLC_N_SLEEP_SHIFT 8
+#define MT6325_QI_VIO18_DLC_N_MASK 0x3
+#define MT6325_QI_VIO18_DLC_N_SHIFT 12
+#define MT6325_VIO18_TRANS_TD_MASK 0x3
+#define MT6325_VIO18_TRANS_TD_SHIFT 0
+#define MT6325_VIO18_TRANS_CTRL_MASK 0x3
+#define MT6325_VIO18_TRANS_CTRL_SHIFT 4
+#define MT6325_VIO18_TRANS_ONCE_MASK 0x1
+#define MT6325_VIO18_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VIO18_VOSEL_TRANS_MASK 0x1
+#define MT6325_NI_VIO18_VOSEL_TRANS_SHIFT 7
+#define MT6325_VIO18_VSLEEP_EN_MASK 0x1
+#define MT6325_VIO18_VSLEEP_EN_SHIFT 8
+#define MT6325_VIO18_R2R_PDN_MASK 0x1
+#define MT6325_VIO18_R2R_PDN_SHIFT 10
+#define MT6325_VIO18_VSLEEP_SEL_MASK 0x1
+#define MT6325_VIO18_VSLEEP_SEL_SHIFT 11
+#define MT6325_NI_VIO18_R2R_PDN_MASK 0x1
+#define MT6325_NI_VIO18_R2R_PDN_SHIFT 14
+#define MT6325_NI_VIO18_VSLEEP_SEL_MASK 0x1
+#define MT6325_NI_VIO18_VSLEEP_SEL_SHIFT 15
+#define MT6325_VPA_DIG0_RSV0_MASK 0xFF
+#define MT6325_VPA_DIG0_RSV0_SHIFT 8
+#define MT6325_VPA_EN_CTRL_MASK 0x1
+#define MT6325_VPA_EN_CTRL_SHIFT 0
+#define MT6325_VPA_VOSEL_CTRL_MASK 0x1
+#define MT6325_VPA_VOSEL_CTRL_SHIFT 1
+#define MT6325_VPA_DLC_CTRL_MASK 0x1
+#define MT6325_VPA_DLC_CTRL_SHIFT 2
+#define MT6325_VPA_BURST_CTRL_MASK 0x1
+#define MT6325_VPA_BURST_CTRL_SHIFT 3
+#define MT6325_VPA_EN_SEL_MASK 0x3
+#define MT6325_VPA_EN_SEL_SHIFT 0
+#define MT6325_VPA_VOSEL_SEL_MASK 0x3
+#define MT6325_VPA_VOSEL_SEL_SHIFT 4
+#define MT6325_VPA_DLC_SEL_MASK 0x3
+#define MT6325_VPA_DLC_SEL_SHIFT 8
+#define MT6325_VPA_BURST_SEL_MASK 0x3
+#define MT6325_VPA_BURST_SEL_SHIFT 12
+#define MT6325_VPA_EN_MASK 0x1
+#define MT6325_VPA_EN_SHIFT 0
+#define MT6325_VPA_STBTD_MASK 0x3
+#define MT6325_VPA_STBTD_SHIFT 4
+#define MT6325_QI_VPA_STB_MASK 0x1
+#define MT6325_QI_VPA_STB_SHIFT 12
+#define MT6325_QI_VPA_EN_MASK 0x1
+#define MT6325_QI_VPA_EN_SHIFT 13
+#define MT6325_QI_VPA_OC_STATUS_MASK 0x1
+#define MT6325_QI_VPA_OC_STATUS_SHIFT 15
+#define MT6325_VPA_SFCHG_FRATE_MASK 0x7F
+#define MT6325_VPA_SFCHG_FRATE_SHIFT 0
+#define MT6325_VPA_SFCHG_FEN_MASK 0x1
+#define MT6325_VPA_SFCHG_FEN_SHIFT 7
+#define MT6325_VPA_SFCHG_RRATE_MASK 0x7F
+#define MT6325_VPA_SFCHG_RRATE_SHIFT 8
+#define MT6325_VPA_SFCHG_REN_MASK 0x1
+#define MT6325_VPA_SFCHG_REN_SHIFT 15
+#define MT6325_VPA_VOSEL_MASK 0x3F
+#define MT6325_VPA_VOSEL_SHIFT 0
+#define MT6325_VPA_VOSEL_ON_MASK 0x3F
+#define MT6325_VPA_VOSEL_ON_SHIFT 0
+#define MT6325_VPA_VOSEL_SLEEP_MASK 0x3F
+#define MT6325_VPA_VOSEL_SLEEP_SHIFT 0
+#define MT6325_NI_VPA_VOSEL_MASK 0x3F
+#define MT6325_NI_VPA_VOSEL_SHIFT 0
+#define MT6325_VPA_DIG0_RSV3_MASK 0x7
+#define MT6325_VPA_DIG0_RSV3_SHIFT 11
+#define MT6325_VPA_DLC_MASK 0x7
+#define MT6325_VPA_DLC_SHIFT 0
+#define MT6325_VPA_DLC_ON_MASK 0x7
+#define MT6325_VPA_DLC_ON_SHIFT 4
+#define MT6325_VPA_DLC_SLEEP_MASK 0x7
+#define MT6325_VPA_DLC_SLEEP_SHIFT 8
+#define MT6325_QI_VPA_DLC_MASK 0x7
+#define MT6325_QI_VPA_DLC_SHIFT 12
+#define MT6325_VPA_DIG0_RSV1_MASK 0xFF
+#define MT6325_VPA_DIG0_RSV1_SHIFT 0
+#define MT6325_VPA_DIG1_RSV1_MASK 0xFF
+#define MT6325_VPA_DIG1_RSV1_SHIFT 8
+#define MT6325_VPA_TRANS_TD_MASK 0x3
+#define MT6325_VPA_TRANS_TD_SHIFT 0
+#define MT6325_VPA_TRANS_CTRL_MASK 0x3
+#define MT6325_VPA_TRANS_CTRL_SHIFT 4
+#define MT6325_VPA_TRANS_ONCE_MASK 0x1
+#define MT6325_VPA_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VPA_DVS_BW_MASK 0x1
+#define MT6325_NI_VPA_DVS_BW_SHIFT 7
+#define MT6325_VPA_DIG1_RSV4_MASK 0x3
+#define MT6325_VPA_DIG1_RSV4_SHIFT 10
+#define MT6325_VPA_DIG1_RSV3_MASK 0x3
+#define MT6325_VPA_DIG1_RSV3_SHIFT 14
+#define MT6325_VPA_BURSTH_MASK 0x3
+#define MT6325_VPA_BURSTH_SHIFT 0
+#define MT6325_VPA_BURSTH_ON_MASK 0x3
+#define MT6325_VPA_BURSTH_ON_SHIFT 4
+#define MT6325_VPA_BURSTH_SLEEP_MASK 0x3
+#define MT6325_VPA_BURSTH_SLEEP_SHIFT 8
+#define MT6325_QI_VPA_BURSTH_MASK 0x3
+#define MT6325_QI_VPA_BURSTH_SHIFT 12
+#define MT6325_VPA_BURSTL_MASK 0x3
+#define MT6325_VPA_BURSTL_SHIFT 0
+#define MT6325_VPA_BURSTL_ON_MASK 0x3
+#define MT6325_VPA_BURSTL_ON_SHIFT 4
+#define MT6325_VPA_BURSTL_SLEEP_MASK 0x3
+#define MT6325_VPA_BURSTL_SLEEP_SHIFT 8
+#define MT6325_QI_VPA_BURSTL_MASK 0x3
+#define MT6325_QI_VPA_BURSTL_SHIFT 12
+#define MT6325_VPA_VOSEL_DLC011_MASK 0x3F
+#define MT6325_VPA_VOSEL_DLC011_SHIFT 0
+#define MT6325_VPA_VOSEL_DLC111_MASK 0x3F
+#define MT6325_VPA_VOSEL_DLC111_SHIFT 8
+#define MT6325_VPA_DLC_MAP_EN_MASK 0x1
+#define MT6325_VPA_DLC_MAP_EN_SHIFT 0
+#define MT6325_VPA_VOSEL_DLC001_MASK 0x3F
+#define MT6325_VPA_VOSEL_DLC001_SHIFT 8
+#define MT6325_VPA_DVS_TRANS_TD_MASK 0x3
+#define MT6325_VPA_DVS_TRANS_TD_SHIFT 0
+#define MT6325_VPA_DVS_TRANS_CTRL_MASK 0x3
+#define MT6325_VPA_DVS_TRANS_CTRL_SHIFT 4
+#define MT6325_VPA_DVS_TRANS_ONCE_MASK 0x1
+#define MT6325_VPA_DVS_TRANS_ONCE_SHIFT 6
+#define MT6325_NI_VPA_DVS_TRANST_MASK 0x1
+#define MT6325_NI_VPA_DVS_TRANST_SHIFT 7
+#define MT6325_VPA_DIG0_RSV4_MASK 0xF
+#define MT6325_VPA_DIG0_RSV4_SHIFT 8
+#define MT6325_VPA_DIG1_RSV2_MASK 0xF
+#define MT6325_VPA_DIG1_RSV2_SHIFT 12
+#define MT6325_K_RST_DONE_MASK 0x1
+#define MT6325_K_RST_DONE_SHIFT 0
+#define MT6325_K_MAP_SEL_MASK 0x1
+#define MT6325_K_MAP_SEL_SHIFT 1
+#define MT6325_K_ONCE_EN_MASK 0x1
+#define MT6325_K_ONCE_EN_SHIFT 2
+#define MT6325_K_ONCE_MASK 0x1
+#define MT6325_K_ONCE_SHIFT 3
+#define MT6325_K_START_MANUAL_MASK 0x1
+#define MT6325_K_START_MANUAL_SHIFT 4
+#define MT6325_K_SRC_SEL_MASK 0x1
+#define MT6325_K_SRC_SEL_SHIFT 5
+#define MT6325_K_AUTO_EN_MASK 0x1
+#define MT6325_K_AUTO_EN_SHIFT 6
+#define MT6325_K_INV_MASK 0x1
+#define MT6325_K_INV_SHIFT 7
+#define MT6325_K_CONTROL_SMPS_MASK 0x3F
+#define MT6325_K_CONTROL_SMPS_SHIFT 8
+#define MT6325_K_RESULT_MASK 0x1
+#define MT6325_K_RESULT_SHIFT 0
+#define MT6325_K_DONE_MASK 0x1
+#define MT6325_K_DONE_SHIFT 1
+#define MT6325_K_CONTROL_MASK 0x3F
+#define MT6325_K_CONTROL_SHIFT 2
+#define MT6325_QI_SMPS_OSC_CAL_MASK 0x3F
+#define MT6325_QI_SMPS_OSC_CAL_SHIFT 8
+#define MT6325_K_BUCK_CK_CNT_MASK 0x3FF
+#define MT6325_K_BUCK_CK_CNT_SHIFT 0
+#define MT6325_RG_AUDZCDENABLE_MASK 0x1
+#define MT6325_RG_AUDZCDENABLE_SHIFT 0
+#define MT6325_RG_AUDZCDGAINSTEPTIME_MASK 0x7
+#define MT6325_RG_AUDZCDGAINSTEPTIME_SHIFT 1
+#define MT6325_RG_AUDZCDGAINSTEPSIZE_MASK 0x3
+#define MT6325_RG_AUDZCDGAINSTEPSIZE_SHIFT 4
+#define MT6325_RG_AUDZCDTIMEOUTMODESEL_MASK 0x1
+#define MT6325_RG_AUDZCDTIMEOUTMODESEL_SHIFT 6
+#define MT6325_RG_AUDZCDCLKSEL_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDZCDCLKSEL_VAUDP15_SHIFT 7
+#define MT6325_RG_AUDZCDMUXSEL_VAUDP15_MASK 0x7
+#define MT6325_RG_AUDZCDMUXSEL_VAUDP15_SHIFT 8
+#define MT6325_RG_AUDLOLGAIN_MASK 0x1F
+#define MT6325_RG_AUDLOLGAIN_SHIFT 0
+#define MT6325_RG_AUDLORGAIN_MASK 0x1F
+#define MT6325_RG_AUDLORGAIN_SHIFT 7
+#define MT6325_RG_AUDHPLGAIN_MASK 0x1F
+#define MT6325_RG_AUDHPLGAIN_SHIFT 0
+#define MT6325_RG_AUDHPRGAIN_MASK 0x1F
+#define MT6325_RG_AUDHPRGAIN_SHIFT 7
+#define MT6325_RG_AUDHSGAIN_MASK 0x1F
+#define MT6325_RG_AUDHSGAIN_SHIFT 0
+#define MT6325_RG_AUDIVLGAIN_MASK 0x7
+#define MT6325_RG_AUDIVLGAIN_SHIFT 0
+#define MT6325_RG_AUDIVRGAIN_MASK 0x7
+#define MT6325_RG_AUDIVRGAIN_SHIFT 8
+#define MT6325_RG_AUDINTGAIN1_MASK 0x3F
+#define MT6325_RG_AUDINTGAIN1_SHIFT 0
+#define MT6325_RG_AUDINTGAIN2_MASK 0x3F
+#define MT6325_RG_AUDINTGAIN2_SHIFT 8
+#define MT6325_ISINK_DIM0_FSEL_MASK 0xFFFF
+#define MT6325_ISINK_DIM0_FSEL_SHIFT 0
+#define MT6325_ISINK0_RSV1_MASK 0xF
+#define MT6325_ISINK0_RSV1_SHIFT 0
+#define MT6325_ISINK0_RSV0_MASK 0x7
+#define MT6325_ISINK0_RSV0_SHIFT 4
+#define MT6325_ISINK_DIM0_DUTY_MASK 0x1F
+#define MT6325_ISINK_DIM0_DUTY_SHIFT 7
+#define MT6325_ISINK_CH0_STEP_MASK 0x7
+#define MT6325_ISINK_CH0_STEP_SHIFT 12
+#define MT6325_ISINK_BREATH0_TF2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH0_TF2_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH0_TF1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH0_TF1_SEL_SHIFT 4
+#define MT6325_ISINK_BREATH0_TR2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH0_TR2_SEL_SHIFT 8
+#define MT6325_ISINK_BREATH0_TR1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH0_TR1_SEL_SHIFT 12
+#define MT6325_ISINK_BREATH0_TOFF_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH0_TOFF_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH0_TON_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH0_TON_SEL_SHIFT 8
+#define MT6325_ISINK_DIM1_FSEL_MASK 0xFFFF
+#define MT6325_ISINK_DIM1_FSEL_SHIFT 0
+#define MT6325_ISINK1_RSV1_MASK 0xF
+#define MT6325_ISINK1_RSV1_SHIFT 0
+#define MT6325_ISINK1_RSV0_MASK 0x7
+#define MT6325_ISINK1_RSV0_SHIFT 4
+#define MT6325_ISINK_DIM1_DUTY_MASK 0x1F
+#define MT6325_ISINK_DIM1_DUTY_SHIFT 7
+#define MT6325_ISINK_CH1_STEP_MASK 0x7
+#define MT6325_ISINK_CH1_STEP_SHIFT 12
+#define MT6325_ISINK_BREATH1_TF2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH1_TF2_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH1_TF1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH1_TF1_SEL_SHIFT 4
+#define MT6325_ISINK_BREATH1_TR2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH1_TR2_SEL_SHIFT 8
+#define MT6325_ISINK_BREATH1_TR1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH1_TR1_SEL_SHIFT 12
+#define MT6325_ISINK_BREATH1_TOFF_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH1_TOFF_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH1_TON_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH1_TON_SEL_SHIFT 8
+#define MT6325_ISINK_DIM2_FSEL_MASK 0xFFFF
+#define MT6325_ISINK_DIM2_FSEL_SHIFT 0
+#define MT6325_ISINK2_RSV1_MASK 0xF
+#define MT6325_ISINK2_RSV1_SHIFT 0
+#define MT6325_ISINK2_RSV0_MASK 0x7
+#define MT6325_ISINK2_RSV0_SHIFT 4
+#define MT6325_ISINK_DIM2_DUTY_MASK 0x1F
+#define MT6325_ISINK_DIM2_DUTY_SHIFT 7
+#define MT6325_ISINK_CH2_STEP_MASK 0x7
+#define MT6325_ISINK_CH2_STEP_SHIFT 12
+#define MT6325_ISINK_BREATH2_TF2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH2_TF2_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH2_TF1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH2_TF1_SEL_SHIFT 4
+#define MT6325_ISINK_BREATH2_TR2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH2_TR2_SEL_SHIFT 8
+#define MT6325_ISINK_BREATH2_TR1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH2_TR1_SEL_SHIFT 12
+#define MT6325_ISINK_BREATH2_TOFF_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH2_TOFF_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH2_TON_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH2_TON_SEL_SHIFT 8
+#define MT6325_ISINK_DIM3_FSEL_MASK 0xFFFF
+#define MT6325_ISINK_DIM3_FSEL_SHIFT 0
+#define MT6325_ISINK3_RSV1_MASK 0xF
+#define MT6325_ISINK3_RSV1_SHIFT 0
+#define MT6325_ISINK3_RSV0_MASK 0x7
+#define MT6325_ISINK3_RSV0_SHIFT 4
+#define MT6325_ISINK_DIM3_DUTY_MASK 0x1F
+#define MT6325_ISINK_DIM3_DUTY_SHIFT 7
+#define MT6325_ISINK_CH3_STEP_MASK 0x7
+#define MT6325_ISINK_CH3_STEP_SHIFT 12
+#define MT6325_ISINK_BREATH3_TF2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH3_TF2_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH3_TF1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH3_TF1_SEL_SHIFT 4
+#define MT6325_ISINK_BREATH3_TR2_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH3_TR2_SEL_SHIFT 8
+#define MT6325_ISINK_BREATH3_TR1_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH3_TR1_SEL_SHIFT 12
+#define MT6325_ISINK_BREATH3_TOFF_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH3_TOFF_SEL_SHIFT 0
+#define MT6325_ISINK_BREATH3_TON_SEL_MASK 0xF
+#define MT6325_ISINK_BREATH3_TON_SEL_SHIFT 8
+#define MT6325_RG_ISINKS_RSV_MASK 0xFF
+#define MT6325_RG_ISINKS_RSV_SHIFT 0
+#define MT6325_RG_ISINK3_DOUBLE_EN_MASK 0x1
+#define MT6325_RG_ISINK3_DOUBLE_EN_SHIFT 8
+#define MT6325_RG_ISINK2_DOUBLE_EN_MASK 0x1
+#define MT6325_RG_ISINK2_DOUBLE_EN_SHIFT 9
+#define MT6325_RG_ISINK1_DOUBLE_EN_MASK 0x1
+#define MT6325_RG_ISINK1_DOUBLE_EN_SHIFT 10
+#define MT6325_RG_ISINK0_DOUBLE_EN_MASK 0x1
+#define MT6325_RG_ISINK0_DOUBLE_EN_SHIFT 11
+#define MT6325_RG_TRIM_SEL_MASK 0x7
+#define MT6325_RG_TRIM_SEL_SHIFT 12
+#define MT6325_RG_TRIM_EN_MASK 0x1
+#define MT6325_RG_TRIM_EN_SHIFT 15
+#define MT6325_NI_ISINK3_STATUS_MASK 0x1
+#define MT6325_NI_ISINK3_STATUS_SHIFT 0
+#define MT6325_NI_ISINK2_STATUS_MASK 0x1
+#define MT6325_NI_ISINK2_STATUS_SHIFT 1
+#define MT6325_NI_ISINK1_STATUS_MASK 0x1
+#define MT6325_NI_ISINK1_STATUS_SHIFT 2
+#define MT6325_NI_ISINK0_STATUS_MASK 0x1
+#define MT6325_NI_ISINK0_STATUS_SHIFT 3
+#define MT6325_ISINK_PHASE0_DLY_EN_MASK 0x1
+#define MT6325_ISINK_PHASE0_DLY_EN_SHIFT 0
+#define MT6325_ISINK_PHASE1_DLY_EN_MASK 0x1
+#define MT6325_ISINK_PHASE1_DLY_EN_SHIFT 1
+#define MT6325_ISINK_PHASE2_DLY_EN_MASK 0x1
+#define MT6325_ISINK_PHASE2_DLY_EN_SHIFT 2
+#define MT6325_ISINK_PHASE3_DLY_EN_MASK 0x1
+#define MT6325_ISINK_PHASE3_DLY_EN_SHIFT 3
+#define MT6325_ISINK_PHASE_DLY_TC_MASK 0x3
+#define MT6325_ISINK_PHASE_DLY_TC_SHIFT 4
+#define MT6325_ISINK_CHOP0_SW_MASK 0x1
+#define MT6325_ISINK_CHOP0_SW_SHIFT 12
+#define MT6325_ISINK_CHOP1_SW_MASK 0x1
+#define MT6325_ISINK_CHOP1_SW_SHIFT 13
+#define MT6325_ISINK_CHOP2_SW_MASK 0x1
+#define MT6325_ISINK_CHOP2_SW_SHIFT 14
+#define MT6325_ISINK_CHOP3_SW_MASK 0x1
+#define MT6325_ISINK_CHOP3_SW_SHIFT 15
+#define MT6325_ISINK_SFSTR3_EN_MASK 0x1
+#define MT6325_ISINK_SFSTR3_EN_SHIFT 0
+#define MT6325_ISINK_SFSTR3_TC_MASK 0x3
+#define MT6325_ISINK_SFSTR3_TC_SHIFT 1
+#define MT6325_ISINK_SFSTR2_EN_MASK 0x1
+#define MT6325_ISINK_SFSTR2_EN_SHIFT 4
+#define MT6325_ISINK_SFSTR2_TC_MASK 0x3
+#define MT6325_ISINK_SFSTR2_TC_SHIFT 5
+#define MT6325_ISINK_SFSTR1_EN_MASK 0x1
+#define MT6325_ISINK_SFSTR1_EN_SHIFT 8
+#define MT6325_ISINK_SFSTR1_TC_MASK 0x3
+#define MT6325_ISINK_SFSTR1_TC_SHIFT 9
+#define MT6325_ISINK_SFSTR0_EN_MASK 0x1
+#define MT6325_ISINK_SFSTR0_EN_SHIFT 12
+#define MT6325_ISINK_SFSTR0_TC_MASK 0x3
+#define MT6325_ISINK_SFSTR0_TC_SHIFT 13
+#define MT6325_ISINK_CH0_EN_MASK 0x1
+#define MT6325_ISINK_CH0_EN_SHIFT 0
+#define MT6325_ISINK_CH1_EN_MASK 0x1
+#define MT6325_ISINK_CH1_EN_SHIFT 1
+#define MT6325_ISINK_CH2_EN_MASK 0x1
+#define MT6325_ISINK_CH2_EN_SHIFT 2
+#define MT6325_ISINK_CH3_EN_MASK 0x1
+#define MT6325_ISINK_CH3_EN_SHIFT 3
+#define MT6325_ISINK_CHOP0_EN_MASK 0x1
+#define MT6325_ISINK_CHOP0_EN_SHIFT 4
+#define MT6325_ISINK_CHOP1_EN_MASK 0x1
+#define MT6325_ISINK_CHOP1_EN_SHIFT 5
+#define MT6325_ISINK_CHOP2_EN_MASK 0x1
+#define MT6325_ISINK_CHOP2_EN_SHIFT 6
+#define MT6325_ISINK_CHOP3_EN_MASK 0x1
+#define MT6325_ISINK_CHOP3_EN_SHIFT 7
+#define MT6325_ISINK_CH0_BIAS_EN_MASK 0x1
+#define MT6325_ISINK_CH0_BIAS_EN_SHIFT 8
+#define MT6325_ISINK_CH1_BIAS_EN_MASK 0x1
+#define MT6325_ISINK_CH1_BIAS_EN_SHIFT 9
+#define MT6325_ISINK_CH2_BIAS_EN_MASK 0x1
+#define MT6325_ISINK_CH2_BIAS_EN_SHIFT 10
+#define MT6325_ISINK_CH3_BIAS_EN_MASK 0x1
+#define MT6325_ISINK_CH3_BIAS_EN_SHIFT 11
+#define MT6325_ISINK_RSV_MASK 0xF
+#define MT6325_ISINK_RSV_SHIFT 0
+#define MT6325_ISINK_CH3_MODE_MASK 0x3
+#define MT6325_ISINK_CH3_MODE_SHIFT 8
+#define MT6325_ISINK_CH2_MODE_MASK 0x3
+#define MT6325_ISINK_CH2_MODE_SHIFT 10
+#define MT6325_ISINK_CH1_MODE_MASK 0x3
+#define MT6325_ISINK_CH1_MODE_SHIFT 12
+#define MT6325_ISINK_CH0_MODE_MASK 0x3
+#define MT6325_ISINK_CH0_MODE_SHIFT 14
+#define MT6325_RG_ISINKS_CH0_STEP_MASK 0x7
+#define MT6325_RG_ISINKS_CH0_STEP_SHIFT 0
+#define MT6325_RG_ISINKS_CH1_STEP_MASK 0x7
+#define MT6325_RG_ISINKS_CH1_STEP_SHIFT 3
+#define MT6325_RG_ISINKS_CH2_STEP_MASK 0x7
+#define MT6325_RG_ISINKS_CH2_STEP_SHIFT 6
+#define MT6325_RG_ISINKS_CH3_STEP_MASK 0x7
+#define MT6325_RG_ISINKS_CH3_STEP_SHIFT 9
+#define MT6325_RG_VTCXO0_MODE_SET_MASK 0x1
+#define MT6325_RG_VTCXO0_MODE_SET_SHIFT 0
+#define MT6325_RG_VTCXO0_EN_MASK 0x1
+#define MT6325_RG_VTCXO0_EN_SHIFT 1
+#define MT6325_RG_VTCXO0_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VTCXO0_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VTCXO0_ON_CTRL_MASK 0x1
+#define MT6325_RG_VTCXO0_ON_CTRL_SHIFT 3
+#define MT6325_RG_VTCXO0_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VTCXO0_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VTCXO0_MODE_MASK 0x1
+#define MT6325_QI_VTCXO0_MODE_SHIFT 7
+#define MT6325_RG_VTCXO0_STBTD_MASK 0x3
+#define MT6325_RG_VTCXO0_STBTD_SHIFT 8
+#define MT6325_RG_VTCXO0_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VTCXO0_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VTCXO0_STB_MASK 0x1
+#define MT6325_QI_VTCXO0_STB_SHIFT 14
+#define MT6325_QI_VTCXO0_EN_MASK 0x1
+#define MT6325_QI_VTCXO0_EN_SHIFT 15
+#define MT6325_RG_VTCXO1_MODE_SET_MASK 0x1
+#define MT6325_RG_VTCXO1_MODE_SET_SHIFT 0
+#define MT6325_RG_VTCXO1_EN_MASK 0x1
+#define MT6325_RG_VTCXO1_EN_SHIFT 1
+#define MT6325_RG_VTCXO1_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VTCXO1_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VTCXO1_ON_CTRL_MASK 0x1
+#define MT6325_RG_VTCXO1_ON_CTRL_SHIFT 3
+#define MT6325_RG_VTCXO1_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VTCXO1_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VTCXO1_MODE_MASK 0x1
+#define MT6325_QI_VTCXO1_MODE_SHIFT 7
+#define MT6325_RG_VTCXO1_STBTD_MASK 0x3
+#define MT6325_RG_VTCXO1_STBTD_SHIFT 8
+#define MT6325_RG_VTCXO1_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VTCXO1_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VTCXO1_STB_MASK 0x1
+#define MT6325_QI_VTCXO1_STB_SHIFT 14
+#define MT6325_QI_VTCXO1_EN_MASK 0x1
+#define MT6325_QI_VTCXO1_EN_SHIFT 15
+#define MT6325_RG_VAUD28_MODE_SET_MASK 0x1
+#define MT6325_RG_VAUD28_MODE_SET_SHIFT 0
+#define MT6325_RG_VAUD28_EN_MASK 0x1
+#define MT6325_RG_VAUD28_EN_SHIFT 1
+#define MT6325_RG_VAUD28_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VAUD28_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VAUD28_ON_CTRL_MASK 0x1
+#define MT6325_RG_VAUD28_ON_CTRL_SHIFT 3
+#define MT6325_RG_VAUD28_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VAUD28_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VAUD28_MODE_MASK 0x1
+#define MT6325_QI_VAUD28_MODE_SHIFT 7
+#define MT6325_RG_VAUD28_STBTD_MASK 0x3
+#define MT6325_RG_VAUD28_STBTD_SHIFT 8
+#define MT6325_RG_VAUD28_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VAUD28_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VAUD28_STB_MASK 0x1
+#define MT6325_QI_VAUD28_STB_SHIFT 14
+#define MT6325_QI_VAUD28_EN_MASK 0x1
+#define MT6325_QI_VAUD28_EN_SHIFT 15
+#define MT6325_RG_VAUXA28_MODE_SET_MASK 0x1
+#define MT6325_RG_VAUXA28_MODE_SET_SHIFT 0
+#define MT6325_RG_VAUXA28_EN_MASK 0x1
+#define MT6325_RG_VAUXA28_EN_SHIFT 1
+#define MT6325_RG_VAUXA28_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VAUXA28_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VAUXA28_ON_CTRL_MASK 0x1
+#define MT6325_RG_VAUXA28_ON_CTRL_SHIFT 3
+#define MT6325_RG_VAUXA28_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VAUXA28_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VAUXA28_MODE_MASK 0x1
+#define MT6325_QI_VAUXA28_MODE_SHIFT 7
+#define MT6325_RG_VAUXA28_STBTD_MASK 0x3
+#define MT6325_RG_VAUXA28_STBTD_SHIFT 8
+#define MT6325_RG_VAUXA28_AUXADC_PWDB_EN_MASK 0x1
+#define MT6325_RG_VAUXA28_AUXADC_PWDB_EN_SHIFT 11
+#define MT6325_RG_VAUXA28_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VAUXA28_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VAUXA28_STB_MASK 0x1
+#define MT6325_QI_VAUXA28_STB_SHIFT 14
+#define MT6325_QI_VAUXA28_EN_MASK 0x1
+#define MT6325_QI_VAUXA28_EN_SHIFT 15
+#define MT6325_RG_VBIF28_MODE_SET_MASK 0x1
+#define MT6325_RG_VBIF28_MODE_SET_SHIFT 0
+#define MT6325_RG_VBIF28_EN_MASK 0x1
+#define MT6325_RG_VBIF28_EN_SHIFT 1
+#define MT6325_RG_VBIF28_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VBIF28_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VBIF28_ON_CTRL_MASK 0x1
+#define MT6325_RG_VBIF28_ON_CTRL_SHIFT 3
+#define MT6325_RG_VBIF28_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VBIF28_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VBIF28_MODE_MASK 0x1
+#define MT6325_QI_VBIF28_MODE_SHIFT 7
+#define MT6325_RG_VBIF28_STBTD_MASK 0x3
+#define MT6325_RG_VBIF28_STBTD_SHIFT 8
+#define MT6325_RG_VBIF28_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VBIF28_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VBIF28_STB_MASK 0x1
+#define MT6325_QI_VBIF28_STB_SHIFT 14
+#define MT6325_QI_VBIF28_EN_MASK 0x1
+#define MT6325_QI_VBIF28_EN_SHIFT 15
+#define MT6325_RG_VCAMA_EN_MASK 0x1
+#define MT6325_RG_VCAMA_EN_SHIFT 1
+#define MT6325_RG_VCAMA_STBTD_MASK 0x3
+#define MT6325_RG_VCAMA_STBTD_SHIFT 8
+#define MT6325_QI_VCAMA_STB_MASK 0x1
+#define MT6325_QI_VCAMA_STB_SHIFT 14
+#define MT6325_QI_VCAMA_EN_MASK 0x1
+#define MT6325_QI_VCAMA_EN_SHIFT 15
+#define MT6325_RG_VCN28_MODE_SET_MASK 0x1
+#define MT6325_RG_VCN28_MODE_SET_SHIFT 0
+#define MT6325_RG_VCN28_EN_MASK 0x1
+#define MT6325_RG_VCN28_EN_SHIFT 1
+#define MT6325_RG_VCN28_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VCN28_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VCN28_ON_CTRL_MASK 0x1
+#define MT6325_RG_VCN28_ON_CTRL_SHIFT 3
+#define MT6325_RG_VCN28_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VCN28_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VCN28_MODE_MASK 0x1
+#define MT6325_QI_VCN28_MODE_SHIFT 7
+#define MT6325_RG_VCN28_STBTD_MASK 0x3
+#define MT6325_RG_VCN28_STBTD_SHIFT 8
+#define MT6325_RG_VCN28_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VCN28_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VCN28_STB_MASK 0x1
+#define MT6325_QI_VCN28_STB_SHIFT 14
+#define MT6325_QI_VCN28_EN_MASK 0x1
+#define MT6325_QI_VCN28_EN_SHIFT 15
+#define MT6325_RG_VCN33_MODE_SET_MASK 0x1
+#define MT6325_RG_VCN33_MODE_SET_SHIFT 0
+#define MT6325_RG_VCN33_EN_MASK 0x1
+#define MT6325_RG_VCN33_EN_SHIFT 1
+#define MT6325_RG_VCN33_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VCN33_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VCN33_ON_CTRL_MASK 0x1
+#define MT6325_RG_VCN33_ON_CTRL_SHIFT 3
+#define MT6325_RG_VCN33_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VCN33_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VCN33_MODE_MASK 0x1
+#define MT6325_QI_VCN33_MODE_SHIFT 7
+#define MT6325_RG_VCN33_STBTD_MASK 0x3
+#define MT6325_RG_VCN33_STBTD_SHIFT 8
+#define MT6325_RG_VCN33_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VCN33_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VCN33_STB_MASK 0x1
+#define MT6325_QI_VCN33_STB_SHIFT 14
+#define MT6325_QI_VCN33_EN_MASK 0x1
+#define MT6325_QI_VCN33_EN_SHIFT 15
+#define MT6325_RG_VRF18_1_MODE_SET_MASK 0x1
+#define MT6325_RG_VRF18_1_MODE_SET_SHIFT 0
+#define MT6325_RG_VRF18_1_EN_MASK 0x1
+#define MT6325_RG_VRF18_1_EN_SHIFT 1
+#define MT6325_RG_VRF18_1_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VRF18_1_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VRF18_1_ON_CTRL_MASK 0x1
+#define MT6325_RG_VRF18_1_ON_CTRL_SHIFT 3
+#define MT6325_RG_VRF18_1_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VRF18_1_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VRF18_1_MODE_MASK 0x1
+#define MT6325_QI_VRF18_1_MODE_SHIFT 7
+#define MT6325_RG_VRF18_1_STBTD_MASK 0x3
+#define MT6325_RG_VRF18_1_STBTD_SHIFT 8
+#define MT6325_RG_VRF18_1_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VRF18_1_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VRF18_1_STB_MASK 0x1
+#define MT6325_QI_VRF18_1_STB_SHIFT 14
+#define MT6325_QI_VRF18_1_EN_MASK 0x1
+#define MT6325_QI_VRF18_1_EN_SHIFT 15
+#define MT6325_RG_VUSB33_MODE_SET_MASK 0x1
+#define MT6325_RG_VUSB33_MODE_SET_SHIFT 0
+#define MT6325_RG_VUSB33_EN_MASK 0x1
+#define MT6325_RG_VUSB33_EN_SHIFT 1
+#define MT6325_RG_VUSB33_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VUSB33_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VUSB33_ON_CTRL_MASK 0x1
+#define MT6325_RG_VUSB33_ON_CTRL_SHIFT 3
+#define MT6325_RG_VUSB33_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VUSB33_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VUSB33_MODE_MASK 0x1
+#define MT6325_QI_VUSB33_MODE_SHIFT 7
+#define MT6325_RG_VUSB33_STBTD_MASK 0x3
+#define MT6325_RG_VUSB33_STBTD_SHIFT 8
+#define MT6325_RG_VUSB33_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VUSB33_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VUSB33_STB_MASK 0x1
+#define MT6325_QI_VUSB33_STB_SHIFT 14
+#define MT6325_QI_VUSB33_EN_MASK 0x1
+#define MT6325_QI_VUSB33_EN_SHIFT 15
+#define MT6325_RG_VMCH_MODE_SET_MASK 0x1
+#define MT6325_RG_VMCH_MODE_SET_SHIFT 0
+#define MT6325_RG_VMCH_EN_MASK 0x1
+#define MT6325_RG_VMCH_EN_SHIFT 1
+#define MT6325_RG_VMCH_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VMCH_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VMCH_ON_CTRL_MASK 0x1
+#define MT6325_RG_VMCH_ON_CTRL_SHIFT 3
+#define MT6325_RG_VMCH_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VMCH_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VMCH_MODE_MASK 0x1
+#define MT6325_QI_VMCH_MODE_SHIFT 7
+#define MT6325_RG_VMCH_STBTD_MASK 0x3
+#define MT6325_RG_VMCH_STBTD_SHIFT 8
+#define MT6325_RG_VMCH_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VMCH_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VMCH_STB_MASK 0x1
+#define MT6325_QI_VMCH_STB_SHIFT 14
+#define MT6325_QI_VMCH_EN_MASK 0x1
+#define MT6325_QI_VMCH_EN_SHIFT 15
+#define MT6325_RG_VMC_MODE_SET_MASK 0x1
+#define MT6325_RG_VMC_MODE_SET_SHIFT 0
+#define MT6325_RG_VMC_EN_MASK 0x1
+#define MT6325_RG_VMC_EN_SHIFT 1
+#define MT6325_RG_VMC_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VMC_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VMC_ON_CTRL_MASK 0x1
+#define MT6325_RG_VMC_ON_CTRL_SHIFT 3
+#define MT6325_RG_VMC_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VMC_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VMC_INT_DIS_MASK 0x1
+#define MT6325_QI_VMC_INT_DIS_SHIFT 6
+#define MT6325_QI_VMC_MODE_MASK 0x1
+#define MT6325_QI_VMC_MODE_SHIFT 7
+#define MT6325_RG_VMC_STBTD_MASK 0x3
+#define MT6325_RG_VMC_STBTD_SHIFT 8
+#define MT6325_RG_VMC_INT_DIS_SEL_MASK 0x3
+#define MT6325_RG_VMC_INT_DIS_SEL_SHIFT 10
+#define MT6325_RG_VMC_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VMC_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VMC_STB_MASK 0x1
+#define MT6325_QI_VMC_STB_SHIFT 14
+#define MT6325_QI_VMC_EN_MASK 0x1
+#define MT6325_QI_VMC_EN_SHIFT 15
+#define MT6325_RG_VEMC33_MODE_SET_MASK 0x1
+#define MT6325_RG_VEMC33_MODE_SET_SHIFT 0
+#define MT6325_RG_VEMC33_EN_MASK 0x1
+#define MT6325_RG_VEMC33_EN_SHIFT 1
+#define MT6325_RG_VEMC33_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VEMC33_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VEMC33_ON_CTRL_MASK 0x1
+#define MT6325_RG_VEMC33_ON_CTRL_SHIFT 3
+#define MT6325_RG_VEMC33_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VEMC33_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VEMC_3V3_MODE_MASK 0x1
+#define MT6325_QI_VEMC_3V3_MODE_SHIFT 7
+#define MT6325_RG_VEMC33_STBTD_MASK 0x3
+#define MT6325_RG_VEMC33_STBTD_SHIFT 8
+#define MT6325_RG_VEMC33_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VEMC33_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VEMC_3V3_STB_MASK 0x1
+#define MT6325_QI_VEMC_3V3_STB_SHIFT 14
+#define MT6325_QI_VEMC_3V3_EN_MASK 0x1
+#define MT6325_QI_VEMC_3V3_EN_SHIFT 15
+#define MT6325_RG_VIO28_MODE_SET_MASK 0x1
+#define MT6325_RG_VIO28_MODE_SET_SHIFT 0
+#define MT6325_RG_VIO28_EN_MASK 0x1
+#define MT6325_RG_VIO28_EN_SHIFT 1
+#define MT6325_RG_VIO28_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VIO28_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VIO28_ON_CTRL_MASK 0x1
+#define MT6325_RG_VIO28_ON_CTRL_SHIFT 3
+#define MT6325_RG_VIO28_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VIO28_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VIO28_MODE_MASK 0x1
+#define MT6325_QI_VIO28_MODE_SHIFT 7
+#define MT6325_RG_VIO28_STBTD_MASK 0x3
+#define MT6325_RG_VIO28_STBTD_SHIFT 8
+#define MT6325_RG_VIO28_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VIO28_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VIO28_STB_MASK 0x1
+#define MT6325_QI_VIO28_STB_SHIFT 14
+#define MT6325_QI_VIO28_EN_MASK 0x1
+#define MT6325_QI_VIO28_EN_SHIFT 15
+#define MT6325_RG_VCAM_AF_MODE_SET_MASK 0x1
+#define MT6325_RG_VCAM_AF_MODE_SET_SHIFT 0
+#define MT6325_RG_VCAM_AF_EN_MASK 0x1
+#define MT6325_RG_VCAM_AF_EN_SHIFT 1
+#define MT6325_RG_VCAM_AF_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VCAM_AF_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VCAM_AF_ON_CTRL_MASK 0x1
+#define MT6325_RG_VCAM_AF_ON_CTRL_SHIFT 3
+#define MT6325_RG_VCAM_AF_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VCAM_AF_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VCAMAF_MODE_MASK 0x1
+#define MT6325_QI_VCAMAF_MODE_SHIFT 7
+#define MT6325_RG_VCAM_AF_STBTD_MASK 0x3
+#define MT6325_RG_VCAM_AF_STBTD_SHIFT 8
+#define MT6325_RG_VCAM_AF_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VCAM_AF_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VCAMAF_STB_MASK 0x1
+#define MT6325_QI_VCAMAF_STB_SHIFT 14
+#define MT6325_QI_VCAMAF_EN_MASK 0x1
+#define MT6325_QI_VCAMAF_EN_SHIFT 15
+#define MT6325_RG_VGP1_MODE_SET_MASK 0x1
+#define MT6325_RG_VGP1_MODE_SET_SHIFT 0
+#define MT6325_RG_VGP1_EN_MASK 0x1
+#define MT6325_RG_VGP1_EN_SHIFT 1
+#define MT6325_RG_VGP1_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VGP1_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VGP1_ON_CTRL_MASK 0x1
+#define MT6325_RG_VGP1_ON_CTRL_SHIFT 3
+#define MT6325_RG_VGP1_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VGP1_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VGP1_MODE_MASK 0x1
+#define MT6325_QI_VGP1_MODE_SHIFT 7
+#define MT6325_RG_VGP1_STBTD_MASK 0x3
+#define MT6325_RG_VGP1_STBTD_SHIFT 8
+#define MT6325_RG_VGP1_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VGP1_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VGP1_STB_MASK 0x1
+#define MT6325_QI_VGP1_STB_SHIFT 14
+#define MT6325_QI_VGP1_EN_MASK 0x1
+#define MT6325_QI_VGP1_EN_SHIFT 15
+#define MT6325_RG_VEFUSE_MODE_SET_MASK 0x1
+#define MT6325_RG_VEFUSE_MODE_SET_SHIFT 0
+#define MT6325_RG_VEFUSE_EN_MASK 0x1
+#define MT6325_RG_VEFUSE_EN_SHIFT 1
+#define MT6325_RG_VEFUSE_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VEFUSE_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VEFUSE_ON_CTRL_MASK 0x1
+#define MT6325_RG_VEFUSE_ON_CTRL_SHIFT 3
+#define MT6325_RG_VEFUSE_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VEFUSE_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VEFUSE_MODE_MASK 0x1
+#define MT6325_QI_VEFUSE_MODE_SHIFT 7
+#define MT6325_RG_VEFUSE_STBTD_MASK 0x3
+#define MT6325_RG_VEFUSE_STBTD_SHIFT 8
+#define MT6325_RG_VEFUSE_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VEFUSE_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VEFUSE_STB_MASK 0x1
+#define MT6325_QI_VEFUSE_STB_SHIFT 14
+#define MT6325_QI_VEFUSE_EN_MASK 0x1
+#define MT6325_QI_VEFUSE_EN_SHIFT 15
+#define MT6325_RG_VSIM1_MODE_SET_MASK 0x1
+#define MT6325_RG_VSIM1_MODE_SET_SHIFT 0
+#define MT6325_RG_VSIM1_EN_MASK 0x1
+#define MT6325_RG_VSIM1_EN_SHIFT 1
+#define MT6325_RG_VSIM1_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VSIM1_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VSIM1_ON_CTRL_MASK 0x1
+#define MT6325_RG_VSIM1_ON_CTRL_SHIFT 3
+#define MT6325_RG_VSIM1_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VSIM1_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VSIM1_MODE_MASK 0x1
+#define MT6325_QI_VSIM1_MODE_SHIFT 7
+#define MT6325_RG_VSIM1_STBTD_MASK 0x3
+#define MT6325_RG_VSIM1_STBTD_SHIFT 8
+#define MT6325_RG_VSIM1_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VSIM1_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VSIM1_STB_MASK 0x1
+#define MT6325_QI_VSIM1_STB_SHIFT 14
+#define MT6325_QI_VSIM1_EN_MASK 0x1
+#define MT6325_QI_VSIM1_EN_SHIFT 15
+#define MT6325_RG_VSIM2_MODE_SET_MASK 0x1
+#define MT6325_RG_VSIM2_MODE_SET_SHIFT 0
+#define MT6325_RG_VSIM2_EN_MASK 0x1
+#define MT6325_RG_VSIM2_EN_SHIFT 1
+#define MT6325_RG_VSIM2_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VSIM2_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VSIM2_ON_CTRL_MASK 0x1
+#define MT6325_RG_VSIM2_ON_CTRL_SHIFT 3
+#define MT6325_RG_VSIM2_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VSIM2_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VSIM2_MODE_MASK 0x1
+#define MT6325_QI_VSIM2_MODE_SHIFT 7
+#define MT6325_RG_VSIM2_STBTD_MASK 0x3
+#define MT6325_RG_VSIM2_STBTD_SHIFT 8
+#define MT6325_RG_VSIM2_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VSIM2_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VSIM2_STB_MASK 0x1
+#define MT6325_QI_VSIM2_STB_SHIFT 14
+#define MT6325_QI_VSIM2_EN_MASK 0x1
+#define MT6325_QI_VSIM2_EN_SHIFT 15
+#define MT6325_RG_VMIPI_MODE_SET_MASK 0x1
+#define MT6325_RG_VMIPI_MODE_SET_SHIFT 0
+#define MT6325_RG_VMIPI_EN_MASK 0x1
+#define MT6325_RG_VMIPI_EN_SHIFT 1
+#define MT6325_RG_VMIPI_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VMIPI_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VMIPI_ON_CTRL_MASK 0x1
+#define MT6325_RG_VMIPI_ON_CTRL_SHIFT 3
+#define MT6325_RG_VMIPI_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VMIPI_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VMIPI_MODE_MASK 0x1
+#define MT6325_QI_VMIPI_MODE_SHIFT 7
+#define MT6325_RG_VMIPI_STBTD_MASK 0x3
+#define MT6325_RG_VMIPI_STBTD_SHIFT 8
+#define MT6325_RG_VMIPI_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VMIPI_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VMIPI_STB_MASK 0x1
+#define MT6325_QI_VMIPI_STB_SHIFT 14
+#define MT6325_QI_VMIPI_EN_MASK 0x1
+#define MT6325_QI_VMIPI_EN_SHIFT 15
+#define MT6325_RG_VIBR_THER_SHEN_EN_MASK 0x1
+#define MT6325_RG_VIBR_THER_SHEN_EN_SHIFT 0
+#define MT6325_RG_VIBR_EN_MASK 0x1
+#define MT6325_RG_VIBR_EN_SHIFT 1
+#define MT6325_RG_VIBR_SW_MODE_MASK 0x1
+#define MT6325_RG_VIBR_SW_MODE_SHIFT 3
+#define MT6325_RG_VIBR_FR_ORI_MASK 0x3
+#define MT6325_RG_VIBR_FR_ORI_SHIFT 4
+#define MT6325_RG_VIBR_MST_TIME_MASK 0x3
+#define MT6325_RG_VIBR_MST_TIME_SHIFT 8
+#define MT6325_RG_VIBR_MID_STATE_MASK 0x3
+#define MT6325_RG_VIBR_MID_STATE_SHIFT 10
+#define MT6325_QI_VIBR_FR_MASK 0x3
+#define MT6325_QI_VIBR_FR_SHIFT 12
+#define MT6325_RG_VIBR_PWDB_MASK 0x1
+#define MT6325_RG_VIBR_PWDB_SHIFT 15
+#define MT6325_RG_VCN18_MODE_SET_MASK 0x1
+#define MT6325_RG_VCN18_MODE_SET_SHIFT 0
+#define MT6325_RG_VCN18_EN_MASK 0x1
+#define MT6325_RG_VCN18_EN_SHIFT 1
+#define MT6325_RG_VCN18_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VCN18_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VCN18_ON_CTRL_MASK 0x1
+#define MT6325_RG_VCN18_ON_CTRL_SHIFT 3
+#define MT6325_RG_VCN18_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VCN18_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VCN18_MODE_MASK 0x1
+#define MT6325_QI_VCN18_MODE_SHIFT 7
+#define MT6325_RG_VCN18_STBTD_MASK 0x3
+#define MT6325_RG_VCN18_STBTD_SHIFT 8
+#define MT6325_RG_VCN18_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VCN18_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VCN18_STB_MASK 0x1
+#define MT6325_QI_VCN18_STB_SHIFT 14
+#define MT6325_QI_VCN18_EN_MASK 0x1
+#define MT6325_QI_VCN18_EN_SHIFT 15
+#define MT6325_NI_VDIG18_VOSEL_MASK 0x7
+#define MT6325_NI_VDIG18_VOSEL_SHIFT 0
+#define MT6325_RG_VDIG18_SRCLKEN_SEL_MASK 0x3
+#define MT6325_RG_VDIG18_SRCLKEN_SEL_SHIFT 7
+#define MT6325_RG_VDIG18_SLEEP_VOSEL_MASK 0x7
+#define MT6325_RG_VDIG18_SLEEP_VOSEL_SHIFT 9
+#define MT6325_RG_VDIG18_VOSEL_MASK 0x7
+#define MT6325_RG_VDIG18_VOSEL_SHIFT 12
+#define MT6325_RG_VDIG18_VOSEL_CTRL_MASK 0x1
+#define MT6325_RG_VDIG18_VOSEL_CTRL_SHIFT 15
+#define MT6325_RG_VGP2_MODE_SET_MASK 0x1
+#define MT6325_RG_VGP2_MODE_SET_SHIFT 0
+#define MT6325_RG_VGP2_EN_MASK 0x1
+#define MT6325_RG_VGP2_EN_SHIFT 1
+#define MT6325_RG_VGP2_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VGP2_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VGP2_ON_CTRL_MASK 0x1
+#define MT6325_RG_VGP2_ON_CTRL_SHIFT 3
+#define MT6325_RG_VGP2_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VGP2_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VGP2_MODE_MASK 0x1
+#define MT6325_QI_VGP2_MODE_SHIFT 7
+#define MT6325_RG_VGP2_STBTD_MASK 0x3
+#define MT6325_RG_VGP2_STBTD_SHIFT 8
+#define MT6325_RG_VGP2_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VGP2_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VGP2_STB_MASK 0x1
+#define MT6325_QI_VGP2_STB_SHIFT 14
+#define MT6325_QI_VGP2_EN_MASK 0x1
+#define MT6325_QI_VGP2_EN_SHIFT 15
+#define MT6325_RG_VCAMD_MODE_SET_MASK 0x1
+#define MT6325_RG_VCAMD_MODE_SET_SHIFT 0
+#define MT6325_RG_VCAMD_EN_MASK 0x1
+#define MT6325_RG_VCAMD_EN_SHIFT 1
+#define MT6325_RG_VCAMD_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VCAMD_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VCAMD_ON_CTRL_MASK 0x1
+#define MT6325_RG_VCAMD_ON_CTRL_SHIFT 3
+#define MT6325_RG_VCAMD_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VCAMD_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VCAMD_MODE_MASK 0x1
+#define MT6325_QI_VCAMD_MODE_SHIFT 7
+#define MT6325_RG_VCAMD_STBTD_MASK 0x3
+#define MT6325_RG_VCAMD_STBTD_SHIFT 8
+#define MT6325_RG_VCAMD_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VCAMD_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VCAMD_STB_MASK 0x1
+#define MT6325_QI_VCAMD_STB_SHIFT 14
+#define MT6325_QI_VCAMD_EN_MASK 0x1
+#define MT6325_QI_VCAMD_EN_SHIFT 15
+#define MT6325_RG_VCAM_IO_MODE_SET_MASK 0x1
+#define MT6325_RG_VCAM_IO_MODE_SET_SHIFT 0
+#define MT6325_RG_VCAM_IO_EN_MASK 0x1
+#define MT6325_RG_VCAM_IO_EN_SHIFT 1
+#define MT6325_RG_VCAM_IO_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VCAM_IO_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VCAM_IO_ON_CTRL_MASK 0x1
+#define MT6325_RG_VCAM_IO_ON_CTRL_SHIFT 3
+#define MT6325_RG_VCAM_IO_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VCAM_IO_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VCAMIO_MODE_MASK 0x1
+#define MT6325_QI_VCAMIO_MODE_SHIFT 7
+#define MT6325_RG_VCAM_IO_STBTD_MASK 0x3
+#define MT6325_RG_VCAM_IO_STBTD_SHIFT 8
+#define MT6325_RG_VCAM_IO_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VCAM_IO_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VCAMIO_STB_MASK 0x1
+#define MT6325_QI_VCAMIO_STB_SHIFT 14
+#define MT6325_QI_VCAMIO_EN_MASK 0x1
+#define MT6325_QI_VCAMIO_EN_SHIFT 15
+#define MT6325_RG_VSRAM_DVFS1_MODE_SET_MASK 0x1
+#define MT6325_RG_VSRAM_DVFS1_MODE_SET_SHIFT 0
+#define MT6325_RG_VSRAM_DVFS1_EN_MASK 0x1
+#define MT6325_RG_VSRAM_DVFS1_EN_SHIFT 1
+#define MT6325_RG_VSRAM_DVFS1_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VSRAM_DVFS1_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VSRAM_DVFS1_ON_CTRL_MASK 0x1
+#define MT6325_RG_VSRAM_DVFS1_ON_CTRL_SHIFT 3
+#define MT6325_RG_VSRAM_DVFS1_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VSRAM_DVFS1_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VSRAM_DVFS1_MODE_MASK 0x1
+#define MT6325_QI_VSRAM_DVFS1_MODE_SHIFT 7
+#define MT6325_RG_VSRAM_DVFS1_STBTD_MASK 0x3
+#define MT6325_RG_VSRAM_DVFS1_STBTD_SHIFT 8
+#define MT6325_RG_VSRAM_DVFS1_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VSRAM_DVFS1_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VSRAM_DVFS1_STB_MASK 0x1
+#define MT6325_QI_VSRAM_DVFS1_STB_SHIFT 14
+#define MT6325_QI_VSRAM_DVFS1_EN_MASK 0x1
+#define MT6325_QI_VSRAM_DVFS1_EN_SHIFT 15
+#define MT6325_RG_VGP3_MODE_SET_MASK 0x1
+#define MT6325_RG_VGP3_MODE_SET_SHIFT 0
+#define MT6325_RG_VGP3_EN_MASK 0x1
+#define MT6325_RG_VGP3_EN_SHIFT 1
+#define MT6325_RG_VGP3_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VGP3_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VGP3_ON_CTRL_MASK 0x1
+#define MT6325_RG_VGP3_ON_CTRL_SHIFT 3
+#define MT6325_RG_VGP3_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VGP3_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VGP3_MODE_MASK 0x1
+#define MT6325_QI_VGP3_MODE_SHIFT 7
+#define MT6325_RG_VGP3_STBTD_MASK 0x3
+#define MT6325_RG_VGP3_STBTD_SHIFT 8
+#define MT6325_RG_VGP3_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VGP3_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VGP3_STB_MASK 0x1
+#define MT6325_QI_VGP3_STB_SHIFT 14
+#define MT6325_QI_VGP3_EN_MASK 0x1
+#define MT6325_QI_VGP3_EN_SHIFT 15
+#define MT6325_RG_VBIASN_MODE_SET_MASK 0x1
+#define MT6325_RG_VBIASN_MODE_SET_SHIFT 0
+#define MT6325_RG_VBIASN_EN_MASK 0x1
+#define MT6325_RG_VBIASN_EN_SHIFT 1
+#define MT6325_RG_VBIASN_MODE_CTRL_MASK 0x1
+#define MT6325_RG_VBIASN_MODE_CTRL_SHIFT 2
+#define MT6325_RG_VBIASN_ON_CTRL_MASK 0x1
+#define MT6325_RG_VBIASN_ON_CTRL_SHIFT 3
+#define MT6325_RG_VBIASN_SRCLK_MODE_SEL_MASK 0x3
+#define MT6325_RG_VBIASN_SRCLK_MODE_SEL_SHIFT 4
+#define MT6325_QI_VBIASN_MODE_MASK 0x1
+#define MT6325_QI_VBIASN_MODE_SHIFT 7
+#define MT6325_RG_VBIASN_STBTD_MASK 0x3
+#define MT6325_RG_VBIASN_STBTD_SHIFT 8
+#define MT6325_RG_VBIASN_SRCLK_EN_SEL_MASK 0x3
+#define MT6325_RG_VBIASN_SRCLK_EN_SEL_SHIFT 12
+#define MT6325_QI_VBIASN_STB_MASK 0x1
+#define MT6325_QI_VBIASN_STB_SHIFT 14
+#define MT6325_QI_VBIASN_EN_MASK 0x1
+#define MT6325_QI_VBIASN_EN_SHIFT 15
+#define MT6325_RG_VRTC_EN_MASK 0x1
+#define MT6325_RG_VRTC_EN_SHIFT 1
+#define MT6325_QI_VRTC_EN_MASK 0x1
+#define MT6325_QI_VRTC_EN_SHIFT 15
+#define MT6325_RG_VBIASN_DIS_SEL_MASK 0x3
+#define MT6325_RG_VBIASN_DIS_SEL_SHIFT 0
+#define MT6325_RG_VBIASN_TRANS_EN_MASK 0x1
+#define MT6325_RG_VBIASN_TRANS_EN_SHIFT 2
+#define MT6325_RG_VBIASN_TRANS_CTRL_MASK 0x3
+#define MT6325_RG_VBIASN_TRANS_CTRL_SHIFT 4
+#define MT6325_RG_VBIASN_TRANS_ONCE_MASK 0x1
+#define MT6325_RG_VBIASN_TRANS_ONCE_SHIFT 6
+#define MT6325_QI_VBIASN_CHR_MASK 0x1
+#define MT6325_QI_VBIASN_CHR_SHIFT 7
+#define MT6325_RG_VTCXO1_NDIS_EN_MASK 0x1
+#define MT6325_RG_VTCXO1_NDIS_EN_SHIFT 0
+#define MT6325_RG_VTCXO1_CAL_MASK 0xF
+#define MT6325_RG_VTCXO1_CAL_SHIFT 4
+#define MT6325_RG_VTCXO0_NDIS_EN_MASK 0x1
+#define MT6325_RG_VTCXO0_NDIS_EN_SHIFT 8
+#define MT6325_RG_VTCXO0_CAL_MASK 0xF
+#define MT6325_RG_VTCXO0_CAL_SHIFT 12
+#define MT6325_RG_VBIF28_NDIS_EN_MASK 0x1
+#define MT6325_RG_VBIF28_NDIS_EN_SHIFT 0
+#define MT6325_RG_VBIF28_CAL_MASK 0xF
+#define MT6325_RG_VBIF28_CAL_SHIFT 4
+#define MT6325_RG_VAUD28_NDIS_EN_MASK 0x1
+#define MT6325_RG_VAUD28_NDIS_EN_SHIFT 8
+#define MT6325_RG_VAUD28_SENSE_SEL_MASK 0x1
+#define MT6325_RG_VAUD28_SENSE_SEL_SHIFT 9
+#define MT6325_RG_VAUD28_CAL_MASK 0xF
+#define MT6325_RG_VAUD28_CAL_SHIFT 12
+#define MT6325_RG_VCAMA_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCAMA_NDIS_EN_SHIFT 0
+#define MT6325_RG_VCAMA_VOSEL_MASK 0x3
+#define MT6325_RG_VCAMA_VOSEL_SHIFT 1
+#define MT6325_RG_VCAMA_CAL_MASK 0xF
+#define MT6325_RG_VCAMA_CAL_SHIFT 4
+#define MT6325_RG_VAUXA28_NDIS_EN_MASK 0x1
+#define MT6325_RG_VAUXA28_NDIS_EN_SHIFT 8
+#define MT6325_RG_VAUXA28_SENSE_SEL_MASK 0x1
+#define MT6325_RG_VAUXA28_SENSE_SEL_SHIFT 9
+#define MT6325_RG_VAUXA28_CAL_MASK 0xF
+#define MT6325_RG_VAUXA28_CAL_SHIFT 12
+#define MT6325_RG_VCN33_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCN33_NDIS_EN_SHIFT 0
+#define MT6325_RG_VCN33_VOSEL_MASK 0x3
+#define MT6325_RG_VCN33_VOSEL_SHIFT 1
+#define MT6325_RG_VCN33_CAL_MASK 0xF
+#define MT6325_RG_VCN33_CAL_SHIFT 4
+#define MT6325_RG_VCN28_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCN28_NDIS_EN_SHIFT 8
+#define MT6325_RG_VCN28_CAL_MASK 0xF
+#define MT6325_RG_VCN28_CAL_SHIFT 12
+#define MT6325_RG_VUSB33_NDIS_EN_MASK 0x1
+#define MT6325_RG_VUSB33_NDIS_EN_SHIFT 0
+#define MT6325_RG_VUSB33_CAL_MASK 0xF
+#define MT6325_RG_VUSB33_CAL_SHIFT 4
+#define MT6325_RG_VRF18_1_NDIS_EN_MASK 0x1
+#define MT6325_RG_VRF18_1_NDIS_EN_SHIFT 8
+#define MT6325_RG_VRF18_1_VOSEL_MASK 0x3
+#define MT6325_RG_VRF18_1_VOSEL_SHIFT 9
+#define MT6325_RG_VRF18_1_CAL_MASK 0xF
+#define MT6325_RG_VRF18_1_CAL_SHIFT 12
+#define MT6325_RG_VMC_NDIS_EN_MASK 0x1
+#define MT6325_RG_VMC_NDIS_EN_SHIFT 0
+#define MT6325_RG_VMC_VOSEL_MASK 0x1
+#define MT6325_RG_VMC_VOSEL_SHIFT 1
+#define MT6325_RG_VMC_STB_CAL_MASK 0x1
+#define MT6325_RG_VMC_STB_CAL_SHIFT 2
+#define MT6325_RG_VMC_CAL_MASK 0xF
+#define MT6325_RG_VMC_CAL_SHIFT 4
+#define MT6325_RG_VMCH_NDIS_EN_MASK 0x1
+#define MT6325_RG_VMCH_NDIS_EN_SHIFT 8
+#define MT6325_RG_VMCH_VOSEL_MASK 0x1
+#define MT6325_RG_VMCH_VOSEL_SHIFT 9
+#define MT6325_RG_VMCH_DB_EN_MASK 0x1
+#define MT6325_RG_VMCH_DB_EN_SHIFT 10
+#define MT6325_RG_VMCH_STB_SEL_MASK 0x1
+#define MT6325_RG_VMCH_STB_SEL_SHIFT 11
+#define MT6325_RG_VMCH_CAL_MASK 0xF
+#define MT6325_RG_VMCH_CAL_SHIFT 12
+#define MT6325_RG_VEMC_3V3_STB_CAL_MASK 0x3
+#define MT6325_RG_VEMC_3V3_STB_CAL_SHIFT 4
+#define MT6325_RG_VEMC_3V3_NDIS_EN_MASK 0x1
+#define MT6325_RG_VEMC_3V3_NDIS_EN_SHIFT 8
+#define MT6325_RG_VEMC_3V3_VOSEL_MASK 0x1
+#define MT6325_RG_VEMC_3V3_VOSEL_SHIFT 9
+#define MT6325_RG_VEMC_3V3_DL_EN_MASK 0x1
+#define MT6325_RG_VEMC_3V3_DL_EN_SHIFT 10
+#define MT6325_RG_VEMC_3V3_CAL_MASK 0xF
+#define MT6325_RG_VEMC_3V3_CAL_SHIFT 12
+#define MT6325_RG_VCAMAF_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCAMAF_NDIS_EN_SHIFT 0
+#define MT6325_RG_VCAMAF_VOSEL_MASK 0x7
+#define MT6325_RG_VCAMAF_VOSEL_SHIFT 1
+#define MT6325_RG_VCAMAF_CAL_MASK 0xF
+#define MT6325_RG_VCAMAF_CAL_SHIFT 4
+#define MT6325_RG_VIO28_NDIS_EN_MASK 0x1
+#define MT6325_RG_VIO28_NDIS_EN_SHIFT 8
+#define MT6325_RG_VIO28_CAL_MASK 0xF
+#define MT6325_RG_VIO28_CAL_SHIFT 12
+#define MT6325_RG_VGP2_NDIS_EN_MASK 0x1
+#define MT6325_RG_VGP2_NDIS_EN_SHIFT 0
+#define MT6325_RG_VGP2_VOSEL_MASK 0x3
+#define MT6325_RG_VGP2_VOSEL_SHIFT 1
+#define MT6325_RG_VGP2_CAL_MASK 0xF
+#define MT6325_RG_VGP2_CAL_SHIFT 4
+#define MT6325_RG_VGP1_NDIS_EN_MASK 0x1
+#define MT6325_RG_VGP1_NDIS_EN_SHIFT 8
+#define MT6325_RG_VGP1_VOSEL_MASK 0x7
+#define MT6325_RG_VGP1_VOSEL_SHIFT 9
+#define MT6325_RG_VGP1_CAL_MASK 0xF
+#define MT6325_RG_VGP1_CAL_SHIFT 12
+#define MT6325_RG_VSIM2_NDIS_EN_MASK 0x1
+#define MT6325_RG_VSIM2_NDIS_EN_SHIFT 0
+#define MT6325_RG_VSIM2_VOSEL_MASK 0x7
+#define MT6325_RG_VSIM2_VOSEL_SHIFT 1
+#define MT6325_RG_VSIM2_CAL_MASK 0xF
+#define MT6325_RG_VSIM2_CAL_SHIFT 4
+#define MT6325_RG_VSIM1_NDIS_EN_MASK 0x1
+#define MT6325_RG_VSIM1_NDIS_EN_SHIFT 8
+#define MT6325_RG_VSIM1_VOSEL_MASK 0x7
+#define MT6325_RG_VSIM1_VOSEL_SHIFT 9
+#define MT6325_RG_VSIM1_CAL_MASK 0xF
+#define MT6325_RG_VSIM1_CAL_SHIFT 12
+#define MT6325_RG_VIBR_VOSEL_MASK 0x7
+#define MT6325_RG_VIBR_VOSEL_SHIFT 1
+#define MT6325_RG_VIBR_VOCAL_MASK 0xF
+#define MT6325_RG_VIBR_VOCAL_SHIFT 4
+#define MT6325_RG_VMIPI_NDIS_EN_MASK 0x1
+#define MT6325_RG_VMIPI_NDIS_EN_SHIFT 8
+#define MT6325_RG_VMIPI_VOSEL_MASK 0x3
+#define MT6325_RG_VMIPI_VOSEL_SHIFT 9
+#define MT6325_RG_VMIPI_CAL_MASK 0xF
+#define MT6325_RG_VMIPI_CAL_SHIFT 12
+#define MT6325_RG_VEFUSE_NDIS_EN_MASK 0x1
+#define MT6325_RG_VEFUSE_NDIS_EN_SHIFT 0
+#define MT6325_RG_VEFUSE_VOSEL_MASK 0x7
+#define MT6325_RG_VEFUSE_VOSEL_SHIFT 1
+#define MT6325_RG_VEFUSE_CAL_MASK 0xF
+#define MT6325_RG_VEFUSE_CAL_SHIFT 4
+#define MT6325_RG_VCN18_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCN18_NDIS_EN_SHIFT 8
+#define MT6325_RG_VCN18_VOSEL_MASK 0x7
+#define MT6325_RG_VCN18_VOSEL_SHIFT 9
+#define MT6325_RG_VCN18_CAL_MASK 0xF
+#define MT6325_RG_VCN18_CAL_SHIFT 12
+#define MT6325_RG_VCAMD_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCAMD_NDIS_EN_SHIFT 0
+#define MT6325_RG_VCAMD_VOSEL_MASK 0x7
+#define MT6325_RG_VCAMD_VOSEL_SHIFT 1
+#define MT6325_RG_VCAMD_CAL_MASK 0xF
+#define MT6325_RG_VCAMD_CAL_SHIFT 4
+#define MT6325_RG_VCAMIO_NDIS_EN_MASK 0x1
+#define MT6325_RG_VCAMIO_NDIS_EN_SHIFT 8
+#define MT6325_RG_VCAMIO_VOSEL_MASK 0x7
+#define MT6325_RG_VCAMIO_VOSEL_SHIFT 9
+#define MT6325_RG_VCAMIO_CAL_MASK 0xF
+#define MT6325_RG_VCAMIO_CAL_SHIFT 12
+#define MT6325_RG_VSRAM_DVFS1_NDIS_EN_MASK 0x1
+#define MT6325_RG_VSRAM_DVFS1_NDIS_EN_SHIFT 0
+#define MT6325_RG_VSRAM_DVFS1_NDIS_PLCUR_MASK 0x3
+#define MT6325_RG_VSRAM_DVFS1_NDIS_PLCUR_SHIFT 4
+#define MT6325_RG_VSRAM_DVFS1_VOSEL_MASK 0x7F
+#define MT6325_RG_VSRAM_DVFS1_VOSEL_SHIFT 9
+#define MT6325_RG_VBIASN_NDIS_EN_MASK 0x1
+#define MT6325_RG_VBIASN_NDIS_EN_SHIFT 0
+#define MT6325_RG_VBIASN_CAL_MASK 0xF
+#define MT6325_RG_VBIASN_CAL_SHIFT 4
+#define MT6325_RG_VGP3_NDIS_EN_MASK 0x1
+#define MT6325_RG_VGP3_NDIS_EN_SHIFT 8
+#define MT6325_RG_VGP3_VOSEL_MASK 0x7
+#define MT6325_RG_VGP3_VOSEL_SHIFT 9
+#define MT6325_RG_VGP3_CAL_MASK 0xF
+#define MT6325_RG_VGP3_CAL_SHIFT 12
+#define MT6325_RG_VBIASN_VOSEL_MASK 0x1F
+#define MT6325_RG_VBIASN_VOSEL_SHIFT 11
+#define MT6325_RG_DLDO_1_RSV_L_MASK 0x1F
+#define MT6325_RG_DLDO_1_RSV_L_SHIFT 0
+#define MT6325_RG_LDO_RSV0_MASK 0x3F
+#define MT6325_RG_LDO_RSV0_SHIFT 5
+#define MT6325_RG_DLDO_1_RSV_H_MASK 0x1F
+#define MT6325_RG_DLDO_1_RSV_H_SHIFT 11
+#define MT6325_RG_DLDO_2_RSV_L_MASK 0x1F
+#define MT6325_RG_DLDO_2_RSV_L_SHIFT 0
+#define MT6325_RG_LDO_RSV1_MASK 0x3F
+#define MT6325_RG_LDO_RSV1_SHIFT 5
+#define MT6325_RG_DLDO_2_RSV_H_MASK 0x1F
+#define MT6325_RG_DLDO_2_RSV_H_SHIFT 11
+#define MT6325_RG_LDO_RSV3_MASK 0xFF
+#define MT6325_RG_LDO_RSV3_SHIFT 0
+#define MT6325_RG_SYSLDO_RSVL_MASK 0x7
+#define MT6325_RG_SYSLDO_RSVL_SHIFT 8
+#define MT6325_RG_SYSLDO_RSV_H_MASK 0x7
+#define MT6325_RG_SYSLDO_RSV_H_SHIFT 12
+#define MT6325_RG_ADLDO_RSV_L_MASK 0x1F
+#define MT6325_RG_ADLDO_RSV_L_SHIFT 0
+#define MT6325_RG_LDO_RSV2_MASK 0x3F
+#define MT6325_RG_LDO_RSV2_SHIFT 5
+#define MT6325_RG_ADLDO_RSV_H_MASK 0x1F
+#define MT6325_RG_ADLDO_RSV_H_SHIFT 11
+#define MT6325_RG_VMC_OCFB_EN_MASK 0x1
+#define MT6325_RG_VMC_OCFB_EN_SHIFT 0
+#define MT6325_RG_VIO28_OCFB_EN_MASK 0x1
+#define MT6325_RG_VIO28_OCFB_EN_SHIFT 1
+#define MT6325_RG_VEMC33_OCFB_EN_MASK 0x1
+#define MT6325_RG_VEMC33_OCFB_EN_SHIFT 2
+#define MT6325_RG_VMCH_OCFB_EN_MASK 0x1
+#define MT6325_RG_VMCH_OCFB_EN_SHIFT 3
+#define MT6325_RG_VUSB33_OCFB_EN_MASK 0x1
+#define MT6325_RG_VUSB33_OCFB_EN_SHIFT 4
+#define MT6325_RG_VRF18_1_OCFB_EN_MASK 0x1
+#define MT6325_RG_VRF18_1_OCFB_EN_SHIFT 5
+#define MT6325_RG_VCN33_OCFB_EN_MASK 0x1
+#define MT6325_RG_VCN33_OCFB_EN_SHIFT 6
+#define MT6325_RG_VCN28_OCFB_EN_MASK 0x1
+#define MT6325_RG_VCN28_OCFB_EN_SHIFT 7
+#define MT6325_RG_VCAMA_OCFB_EN_MASK 0x1
+#define MT6325_RG_VCAMA_OCFB_EN_SHIFT 8
+#define MT6325_RG_VAUXA28_OCFB_EN_MASK 0x1
+#define MT6325_RG_VAUXA28_OCFB_EN_SHIFT 9
+#define MT6325_RG_VBIF28_OCFB_EN_MASK 0x1
+#define MT6325_RG_VBIF28_OCFB_EN_SHIFT 10
+#define MT6325_RG_VAUD28_OCFB_EN_MASK 0x1
+#define MT6325_RG_VAUD28_OCFB_EN_SHIFT 11
+#define MT6325_RG_VTCXO1_OCFB_EN_MASK 0x1
+#define MT6325_RG_VTCXO1_OCFB_EN_SHIFT 12
+#define MT6325_RG_VTCXO0_OCFB_EN_MASK 0x1
+#define MT6325_RG_VTCXO0_OCFB_EN_SHIFT 13
+#define MT6325_LDO_DEGTD_SEL_MASK 0x3
+#define MT6325_LDO_DEGTD_SEL_SHIFT 14
+#define MT6325_RG_VBIASN_OCFB_EN_MASK 0x1
+#define MT6325_RG_VBIASN_OCFB_EN_SHIFT 1
+#define MT6325_RG_VGP3_OCFB_EN_MASK 0x1
+#define MT6325_RG_VGP3_OCFB_EN_SHIFT 2
+#define MT6325_RG_VSRAM_DVFS1_OCFB_EN_MASK 0x1
+#define MT6325_RG_VSRAM_DVFS1_OCFB_EN_SHIFT 3
+#define MT6325_RG_VCAM_IO_OCFB_EN_MASK 0x1
+#define MT6325_RG_VCAM_IO_OCFB_EN_SHIFT 4
+#define MT6325_RG_VCAMD_OCFB_EN_MASK 0x1
+#define MT6325_RG_VCAMD_OCFB_EN_SHIFT 5
+#define MT6325_RG_VGP2_OCFB_EN_MASK 0x1
+#define MT6325_RG_VGP2_OCFB_EN_SHIFT 6
+#define MT6325_RG_VCN18_OCFB_EN_MASK 0x1
+#define MT6325_RG_VCN18_OCFB_EN_SHIFT 7
+#define MT6325_RG_VMIPI_OCFB_EN_MASK 0x1
+#define MT6325_RG_VMIPI_OCFB_EN_SHIFT 8
+#define MT6325_RG_VSIM2_OCFB_EN_MASK 0x1
+#define MT6325_RG_VSIM2_OCFB_EN_SHIFT 9
+#define MT6325_RG_VSIM1_OCFB_EN_MASK 0x1
+#define MT6325_RG_VSIM1_OCFB_EN_SHIFT 10
+#define MT6325_RG_VEFUSE_OCFB_EN_MASK 0x1
+#define MT6325_RG_VEFUSE_OCFB_EN_SHIFT 11
+#define MT6325_RG_VGP1_OCFB_EN_MASK 0x1
+#define MT6325_RG_VGP1_OCFB_EN_SHIFT 12
+#define MT6325_RG_VCAM_AF_OCFB_EN_MASK 0x1
+#define MT6325_RG_VCAM_AF_OCFB_EN_SHIFT 13
+#define MT6325_QI_VMC_OCFB_EN_MASK 0x1
+#define MT6325_QI_VMC_OCFB_EN_SHIFT 0
+#define MT6325_QI_VIO28_OCFB_EN_MASK 0x1
+#define MT6325_QI_VIO28_OCFB_EN_SHIFT 1
+#define MT6325_QI_VEMC_3V3_OCFB_EN_MASK 0x1
+#define MT6325_QI_VEMC_3V3_OCFB_EN_SHIFT 2
+#define MT6325_QI_VMCH_OCFB_EN_MASK 0x1
+#define MT6325_QI_VMCH_OCFB_EN_SHIFT 3
+#define MT6325_QI_VUSB33_OCFB_EN_MASK 0x1
+#define MT6325_QI_VUSB33_OCFB_EN_SHIFT 4
+#define MT6325_QI_VRF18_1_OCFB_EN_MASK 0x1
+#define MT6325_QI_VRF18_1_OCFB_EN_SHIFT 5
+#define MT6325_QI_VCN33_OCFB_EN_MASK 0x1
+#define MT6325_QI_VCN33_OCFB_EN_SHIFT 6
+#define MT6325_QI_VCN28_OCFB_EN_MASK 0x1
+#define MT6325_QI_VCN28_OCFB_EN_SHIFT 7
+#define MT6325_QI_VCAMA_OCFB_EN_MASK 0x1
+#define MT6325_QI_VCAMA_OCFB_EN_SHIFT 8
+#define MT6325_QI_VAUXA28_OCFB_EN_MASK 0x1
+#define MT6325_QI_VAUXA28_OCFB_EN_SHIFT 9
+#define MT6325_QI_VBIF28_OCFB_EN_MASK 0x1
+#define MT6325_QI_VBIF28_OCFB_EN_SHIFT 10
+#define MT6325_QI_VAUD28_OCFB_EN_MASK 0x1
+#define MT6325_QI_VAUD28_OCFB_EN_SHIFT 11
+#define MT6325_QI_VTCXO1_OCFB_EN_MASK 0x1
+#define MT6325_QI_VTCXO1_OCFB_EN_SHIFT 12
+#define MT6325_QI_VTCXO0_OCFB_EN_MASK 0x1
+#define MT6325_QI_VTCXO0_OCFB_EN_SHIFT 13
+#define MT6325_QI_VBIASN_OCFB_EN_MASK 0x1
+#define MT6325_QI_VBIASN_OCFB_EN_SHIFT 1
+#define MT6325_QI_VGP3_OCFB_EN_MASK 0x1
+#define MT6325_QI_VGP3_OCFB_EN_SHIFT 2
+#define MT6325_QI_VSRAM_DVFS1_OCFB_EN_MASK 0x1
+#define MT6325_QI_VSRAM_DVFS1_OCFB_EN_SHIFT 3
+#define MT6325_QI_VCAMIO_OCFB_EN_MASK 0x1
+#define MT6325_QI_VCAMIO_OCFB_EN_SHIFT 4
+#define MT6325_QI_VCAMD_OCFB_EN_MASK 0x1
+#define MT6325_QI_VCAMD_OCFB_EN_SHIFT 5
+#define MT6325_QI_VGP2_OCFB_EN_MASK 0x1
+#define MT6325_QI_VGP2_OCFB_EN_SHIFT 6
+#define MT6325_QI_VCN18_OCFB_EN_MASK 0x1
+#define MT6325_QI_VCN18_OCFB_EN_SHIFT 7
+#define MT6325_QI_VMIPI_OCFB_EN_MASK 0x1
+#define MT6325_QI_VMIPI_OCFB_EN_SHIFT 8
+#define MT6325_QI_VSIM2_OCFB_EN_MASK 0x1
+#define MT6325_QI_VSIM2_OCFB_EN_SHIFT 9
+#define MT6325_QI_VSIM1_OCFB_EN_MASK 0x1
+#define MT6325_QI_VSIM1_OCFB_EN_SHIFT 10
+#define MT6325_QI_VEFUSE_OCFB_EN_MASK 0x1
+#define MT6325_QI_VEFUSE_OCFB_EN_SHIFT 11
+#define MT6325_QI_VGP1_OCFB_EN_MASK 0x1
+#define MT6325_QI_VGP1_OCFB_EN_SHIFT 12
+#define MT6325_QI_VCAMAF_OCFB_EN_MASK 0x1
+#define MT6325_QI_VCAMAF_OCFB_EN_SHIFT 13
+#define MT6325_RG_VCAMIO_EN_MASK 0x1
+#define MT6325_RG_VCAMIO_EN_SHIFT 0
+#define MT6325_RG_VCAMAF_EN_MASK 0x1
+#define MT6325_RG_VCAMAF_EN_SHIFT 1
+#define MT6325_BIF_COMMAND_0_MASK 0x7FF
+#define MT6325_BIF_COMMAND_0_SHIFT 0
+#define MT6325_BIF_COMMAND_1_MASK 0x7FF
+#define MT6325_BIF_COMMAND_1_SHIFT 0
+#define MT6325_BIF_COMMAND_2_MASK 0x7FF
+#define MT6325_BIF_COMMAND_2_SHIFT 0
+#define MT6325_BIF_COMMAND_3_MASK 0x7FF
+#define MT6325_BIF_COMMAND_3_SHIFT 0
+#define MT6325_BIF_COMMAND_4_MASK 0x7FF
+#define MT6325_BIF_COMMAND_4_SHIFT 0
+#define MT6325_BIF_COMMAND_5_MASK 0x7FF
+#define MT6325_BIF_COMMAND_5_SHIFT 0
+#define MT6325_BIF_COMMAND_6_MASK 0x7FF
+#define MT6325_BIF_COMMAND_6_SHIFT 0
+#define MT6325_BIF_COMMAND_7_MASK 0x7FF
+#define MT6325_BIF_COMMAND_7_SHIFT 0
+#define MT6325_BIF_COMMAND_8_MASK 0x7FF
+#define MT6325_BIF_COMMAND_8_SHIFT 0
+#define MT6325_BIF_COMMAND_9_MASK 0x7FF
+#define MT6325_BIF_COMMAND_9_SHIFT 0
+#define MT6325_BIF_COMMAND_10_MASK 0x7FF
+#define MT6325_BIF_COMMAND_10_SHIFT 0
+#define MT6325_BIF_COMMAND_11_MASK 0x7FF
+#define MT6325_BIF_COMMAND_11_SHIFT 0
+#define MT6325_BIF_COMMAND_12_MASK 0x7FF
+#define MT6325_BIF_COMMAND_12_SHIFT 0
+#define MT6325_BIF_COMMAND_13_MASK 0x7FF
+#define MT6325_BIF_COMMAND_13_SHIFT 0
+#define MT6325_BIF_COMMAND_14_MASK 0x7FF
+#define MT6325_BIF_COMMAND_14_SHIFT 0
+#define MT6325_BIF_RSV_MASK 0x7F
+#define MT6325_BIF_RSV_SHIFT 0
+#define MT6325_BIF_COMMAND_TYPE_MASK 0x3
+#define MT6325_BIF_COMMAND_TYPE_SHIFT 8
+#define MT6325_BIF_TRASFER_NUM_MASK 0xF
+#define MT6325_BIF_TRASFER_NUM_SHIFT 12
+#define MT6325_BIF_LOGIC_0_SET_MASK 0xF
+#define MT6325_BIF_LOGIC_0_SET_SHIFT 0
+#define MT6325_BIF_LOGIC_1_SET_MASK 0x1F
+#define MT6325_BIF_LOGIC_1_SET_SHIFT 4
+#define MT6325_BIF_STOP_SET_MASK 0x3F
+#define MT6325_BIF_STOP_SET_SHIFT 10
+#define MT6325_BIF_DEBOUNCE_WND_MASK 0x3
+#define MT6325_BIF_DEBOUNCE_WND_SHIFT 0
+#define MT6325_BIF_DEBOUNCE_THD_MASK 0x3
+#define MT6325_BIF_DEBOUNCE_THD_SHIFT 2
+#define MT6325_BIF_DEBOUNCE_EN_MASK 0x1
+#define MT6325_BIF_DEBOUNCE_EN_SHIFT 4
+#define MT6325_BIF_READ_EXPECT_NUM_MASK 0xF
+#define MT6325_BIF_READ_EXPECT_NUM_SHIFT 12
+#define MT6325_BIF_TRASACT_TRIGGER_MASK 0x1
+#define MT6325_BIF_TRASACT_TRIGGER_SHIFT 0
+#define MT6325_BIF_DATA_NUM_MASK 0xF
+#define MT6325_BIF_DATA_NUM_SHIFT 0
+#define MT6325_BIF_RESPONSE_MASK 0x1
+#define MT6325_BIF_RESPONSE_SHIFT 12
+#define MT6325_BIF_DATA_0_MASK 0xFF
+#define MT6325_BIF_DATA_0_SHIFT 0
+#define MT6325_BIF_ACK_0_MASK 0x1
+#define MT6325_BIF_ACK_0_SHIFT 8
+#define MT6325_BIF_ERROR_0_MASK 0x1
+#define MT6325_BIF_ERROR_0_SHIFT 15
+#define MT6325_BIF_DATA_1_MASK 0xFF
+#define MT6325_BIF_DATA_1_SHIFT 0
+#define MT6325_BIF_ACK_1_MASK 0x1
+#define MT6325_BIF_ACK_1_SHIFT 8
+#define MT6325_BIF_ERROR_1_MASK 0x1
+#define MT6325_BIF_ERROR_1_SHIFT 15
+#define MT6325_BIF_DATA_2_MASK 0xFF
+#define MT6325_BIF_DATA_2_SHIFT 0
+#define MT6325_BIF_ACK_2_MASK 0x1
+#define MT6325_BIF_ACK_2_SHIFT 8
+#define MT6325_BIF_ERROR_2_MASK 0x1
+#define MT6325_BIF_ERROR_2_SHIFT 15
+#define MT6325_BIF_DATA_3_MASK 0xFF
+#define MT6325_BIF_DATA_3_SHIFT 0
+#define MT6325_BIF_ACK_3_MASK 0x1
+#define MT6325_BIF_ACK_3_SHIFT 8
+#define MT6325_BIF_ERROR_3_MASK 0x1
+#define MT6325_BIF_ERROR_3_SHIFT 15
+#define MT6325_BIF_DATA_4_MASK 0xFF
+#define MT6325_BIF_DATA_4_SHIFT 0
+#define MT6325_BIF_ACK_4_MASK 0x1
+#define MT6325_BIF_ACK_4_SHIFT 8
+#define MT6325_BIF_ERROR_4_MASK 0x1
+#define MT6325_BIF_ERROR_4_SHIFT 15
+#define MT6325_BIF_DATA_5_MASK 0xFF
+#define MT6325_BIF_DATA_5_SHIFT 0
+#define MT6325_BIF_ACK_5_MASK 0x1
+#define MT6325_BIF_ACK_5_SHIFT 8
+#define MT6325_BIF_ERROR_5_MASK 0x1
+#define MT6325_BIF_ERROR_5_SHIFT 15
+#define MT6325_BIF_DATA_6_MASK 0xFF
+#define MT6325_BIF_DATA_6_SHIFT 0
+#define MT6325_BIF_ACK_6_MASK 0x1
+#define MT6325_BIF_ACK_6_SHIFT 8
+#define MT6325_BIF_ERROR_6_MASK 0x1
+#define MT6325_BIF_ERROR_6_SHIFT 15
+#define MT6325_BIF_DATA_7_MASK 0xFF
+#define MT6325_BIF_DATA_7_SHIFT 0
+#define MT6325_BIF_ACK_7_MASK 0x1
+#define MT6325_BIF_ACK_7_SHIFT 8
+#define MT6325_BIF_ERROR_7_MASK 0x1
+#define MT6325_BIF_ERROR_7_SHIFT 15
+#define MT6325_BIF_DATA_8_MASK 0xFF
+#define MT6325_BIF_DATA_8_SHIFT 0
+#define MT6325_BIF_ACK_8_MASK 0x1
+#define MT6325_BIF_ACK_8_SHIFT 8
+#define MT6325_BIF_ERROR_8_MASK 0x1
+#define MT6325_BIF_ERROR_8_SHIFT 15
+#define MT6325_BIF_DATA_9_MASK 0xFF
+#define MT6325_BIF_DATA_9_SHIFT 0
+#define MT6325_BIF_ACK_9_MASK 0x1
+#define MT6325_BIF_ACK_9_SHIFT 8
+#define MT6325_BIF_ERROR_9_MASK 0x1
+#define MT6325_BIF_ERROR_9_SHIFT 15
+#define MT6325_BIF_TEST_MODE0_MASK 0x1
+#define MT6325_BIF_TEST_MODE0_SHIFT 0
+#define MT6325_BIF_TEST_MODE1_MASK 0x1
+#define MT6325_BIF_TEST_MODE1_SHIFT 1
+#define MT6325_BIF_TEST_MODE2_MASK 0x1
+#define MT6325_BIF_TEST_MODE2_SHIFT 2
+#define MT6325_BIF_TEST_MODE3_MASK 0x1
+#define MT6325_BIF_TEST_MODE3_SHIFT 3
+#define MT6325_BIF_TEST_MODE4_MASK 0x1
+#define MT6325_BIF_TEST_MODE4_SHIFT 4
+#define MT6325_BIF_TEST_MODE5_MASK 0x1
+#define MT6325_BIF_TEST_MODE5_SHIFT 5
+#define MT6325_BIF_TEST_MODE6_MASK 0x1
+#define MT6325_BIF_TEST_MODE6_SHIFT 6
+#define MT6325_BIF_TEST_MODE7_MASK 0x1
+#define MT6325_BIF_TEST_MODE7_SHIFT 7
+#define MT6325_BIF_TEST_MODE8_MASK 0x1
+#define MT6325_BIF_TEST_MODE8_SHIFT 8
+#define MT6325_BIF_BAT_LOST_SW_MASK 0x1
+#define MT6325_BIF_BAT_LOST_SW_SHIFT 11
+#define MT6325_BIF_RX_DATA_SW_MASK 0x1
+#define MT6325_BIF_RX_DATA_SW_SHIFT 12
+#define MT6325_BIF_TX_DATA_SW_MASK 0x1
+#define MT6325_BIF_TX_DATA_SW_SHIFT 13
+#define MT6325_BIF_RX_EN_SW_MASK 0x1
+#define MT6325_BIF_RX_EN_SW_SHIFT 14
+#define MT6325_BIF_TX_EN_SW_MASK 0x1
+#define MT6325_BIF_TX_EN_SW_SHIFT 15
+#define MT6325_BIF_BACK_NORMAL_MASK 0x1
+#define MT6325_BIF_BACK_NORMAL_SHIFT 0
+#define MT6325_BIF_IRQ_CLR_MASK 0x1
+#define MT6325_BIF_IRQ_CLR_SHIFT 1
+#define MT6325_BIF_BAT_LOST_GATED_MASK 0x1
+#define MT6325_BIF_BAT_LOST_GATED_SHIFT 10
+#define MT6325_BIF_IRQ_MASK 0x1
+#define MT6325_BIF_IRQ_SHIFT 11
+#define MT6325_BIF_TIMEOUT_MASK 0x1
+#define MT6325_BIF_TIMEOUT_SHIFT 12
+#define MT6325_BIF_BAT_LOST_MASK 0x1
+#define MT6325_BIF_BAT_LOST_SHIFT 13
+#define MT6325_BIF_TOTAL_VALID_MASK 0x1
+#define MT6325_BIF_TOTAL_VALID_SHIFT 14
+#define MT6325_BIF_BUS_STATUS_MASK 0x1
+#define MT6325_BIF_BUS_STATUS_SHIFT 15
+#define MT6325_BIF_POWER_UP_COUNT_MASK 0x1F
+#define MT6325_BIF_POWER_UP_COUNT_SHIFT 0
+#define MT6325_BIF_POWER_UP_MASK 0x1
+#define MT6325_BIF_POWER_UP_SHIFT 15
+#define MT6325_BIF_RX_ERROR_UNKNOW_MASK 0x1
+#define MT6325_BIF_RX_ERROR_UNKNOW_SHIFT 2
+#define MT6325_BIF_RX_ERROR_INSUFF_MASK 0x1
+#define MT6325_BIF_RX_ERROR_INSUFF_SHIFT 3
+#define MT6325_BIF_RX_ERROR_LOWPHASE_MASK 0x1
+#define MT6325_BIF_RX_ERROR_LOWPHASE_SHIFT 4
+#define MT6325_BIF_RX_STATE_MASK 0x7
+#define MT6325_BIF_RX_STATE_SHIFT 5
+#define MT6325_BIF_FLOW_CTL_STATE_MASK 0x3
+#define MT6325_BIF_FLOW_CTL_STATE_SHIFT 8
+#define MT6325_BIF_TX_STATE_MASK 0x3
+#define MT6325_BIF_TX_STATE_SHIFT 10
+#define MT6325_QI_BIF_RX_DATA_MASK 0x1
+#define MT6325_QI_BIF_RX_DATA_SHIFT 12
+#define MT6325_QI_BIF_RX_EN_MASK 0x1
+#define MT6325_QI_BIF_RX_EN_SHIFT 13
+#define MT6325_QI_BIF_TX_DATA_MASK 0x1
+#define MT6325_QI_BIF_TX_DATA_SHIFT 14
+#define MT6325_QI_BIF_TX_EN_MASK 0x1
+#define MT6325_QI_BIF_TX_EN_SHIFT 15
+#define MT6325_BIF_TX_DATA_FIANL_MASK 0xFFFF
+#define MT6325_BIF_TX_DATA_FIANL_SHIFT 0
+#define MT6325_BIF_RX_DATA_SAMPLING_MASK 0xFFFF
+#define MT6325_BIF_RX_DATA_SAMPLING_SHIFT 0
+#define MT6325_BIF_RX_DATA_RECOVERY_MASK 0x3FFF
+#define MT6325_BIF_RX_DATA_RECOVERY_SHIFT 0
+#define MT6325_RG_BATON_HT_EN_MASK 0x1
+#define MT6325_RG_BATON_HT_EN_SHIFT 0
+#define MT6325_RG_BATON_TDET_EN_MASK 0x1
+#define MT6325_RG_BATON_TDET_EN_SHIFT 2
+#define MT6325_RG_VBIF28_AUXADC_EN_MASK 0x1
+#define MT6325_RG_VBIF28_AUXADC_EN_SHIFT 3
+#define MT6325_RG_BATON_HT_EN_DLY_TIME_MASK 0x1
+#define MT6325_RG_BATON_HT_EN_DLY_TIME_SHIFT 4
+#define MT6325_QI_BATON_HT_EN_MASK 0x1
+#define MT6325_QI_BATON_HT_EN_SHIFT 5
+#define MT6325_RGS_BATON_HV_MASK 0x1
+#define MT6325_RGS_BATON_HV_SHIFT 6
+#define MT6325_RG_BATON_HT_TRIM_RSV0_MASK 0x7
+#define MT6325_RG_BATON_HT_TRIM_RSV0_SHIFT 8
+#define MT6325_RG_HW_VTH_CTRL_MASK 0x1
+#define MT6325_RG_HW_VTH_CTRL_SHIFT 11
+#define MT6325_RG_HW_VTH2_MASK 0x3
+#define MT6325_RG_HW_VTH2_SHIFT 12
+#define MT6325_RG_HW_VTH1_MASK 0x3
+#define MT6325_RG_HW_VTH1_SHIFT 14
+#define MT6325_BIF_TIMEOUT_SET_MASK 0xFFFF
+#define MT6325_BIF_TIMEOUT_SET_SHIFT 0
+#define MT6325_BIF_RX_DEG_WND_MASK 0x3FF
+#define MT6325_BIF_RX_DEG_WND_SHIFT 0
+#define MT6325_BIF_RX_DEG_EN_MASK 0x1
+#define MT6325_BIF_RX_DEG_EN_SHIFT 15
+#define MT6325_BIF_RSV1_MASK 0xFF
+#define MT6325_BIF_RSV1_SHIFT 0
+#define MT6325_BIF_RSV0_MASK 0xFF
+#define MT6325_BIF_RSV0_SHIFT 8
+#define MT6325_SPK_EN_L_MASK 0x1
+#define MT6325_SPK_EN_L_SHIFT 0
+#define MT6325_SPKMODE_L_MASK 0x1
+#define MT6325_SPKMODE_L_SHIFT 2
+#define MT6325_SPK_TRIM_EN_L_MASK 0x1
+#define MT6325_SPK_TRIM_EN_L_SHIFT 3
+#define MT6325_SPK_OC_SHDN_DL_MASK 0x1
+#define MT6325_SPK_OC_SHDN_DL_SHIFT 8
+#define MT6325_SPK_THER_SHDN_L_EN_MASK 0x1
+#define MT6325_SPK_THER_SHDN_L_EN_SHIFT 9
+#define MT6325_SPK_OUT_STAGE_SEL_MASK 0x1
+#define MT6325_SPK_OUT_STAGE_SEL_SHIFT 10
+#define MT6325_RG_SPK_GAINL_MASK 0x3
+#define MT6325_RG_SPK_GAINL_SHIFT 12
+#define MT6325_DA_SPK_OFFSET_L_MASK 0x1F
+#define MT6325_DA_SPK_OFFSET_L_SHIFT 0
+#define MT6325_DA_SPK_LEAD_DGLH_L_MASK 0x1
+#define MT6325_DA_SPK_LEAD_DGLH_L_SHIFT 5
+#define MT6325_NI_SPK_LEAD_L_MASK 0x1
+#define MT6325_NI_SPK_LEAD_L_SHIFT 6
+#define MT6325_SPK_OFFSET_L_OV_MASK 0x1
+#define MT6325_SPK_OFFSET_L_OV_SHIFT 7
+#define MT6325_SPK_OFFSET_L_SW_MASK 0x1F
+#define MT6325_SPK_OFFSET_L_SW_SHIFT 8
+#define MT6325_SPK_LEAD_L_SW_MASK 0x1
+#define MT6325_SPK_LEAD_L_SW_SHIFT 13
+#define MT6325_SPK_OFFSET_L_MODE_MASK 0x1
+#define MT6325_SPK_OFFSET_L_MODE_SHIFT 14
+#define MT6325_SPK_TRIM_DONE_L_MASK 0x1
+#define MT6325_SPK_TRIM_DONE_L_SHIFT 15
+#define MT6325_RG_SPK_INTG_RST_L_MASK 0x1
+#define MT6325_RG_SPK_INTG_RST_L_SHIFT 0
+#define MT6325_RG_SPK_FORCE_EN_L_MASK 0x1
+#define MT6325_RG_SPK_FORCE_EN_L_SHIFT 1
+#define MT6325_RG_SPK_SLEW_L_MASK 0x3
+#define MT6325_RG_SPK_SLEW_L_SHIFT 2
+#define MT6325_RG_SPKAB_OBIAS_L_MASK 0x3
+#define MT6325_RG_SPKAB_OBIAS_L_SHIFT 4
+#define MT6325_RG_SPKRCV_EN_L_MASK 0x1
+#define MT6325_RG_SPKRCV_EN_L_SHIFT 6
+#define MT6325_RG_SPK_DRC_EN_L_MASK 0x1
+#define MT6325_RG_SPK_DRC_EN_L_SHIFT 7
+#define MT6325_RG_SPK_TEST_EN_L_MASK 0x1
+#define MT6325_RG_SPK_TEST_EN_L_SHIFT 8
+#define MT6325_RG_SPKAB_OC_EN_L_MASK 0x1
+#define MT6325_RG_SPKAB_OC_EN_L_SHIFT 9
+#define MT6325_RG_SPK_OC_EN_L_MASK 0x1
+#define MT6325_RG_SPK_OC_EN_L_SHIFT 10
+#define MT6325_SPK_EN_R_MASK 0x1
+#define MT6325_SPK_EN_R_SHIFT 0
+#define MT6325_SPKMODE_R_MASK 0x1
+#define MT6325_SPKMODE_R_SHIFT 2
+#define MT6325_SPK_TRIM_EN_R_MASK 0x1
+#define MT6325_SPK_TRIM_EN_R_SHIFT 3
+#define MT6325_SPK_OC_SHDN_DR_MASK 0x1
+#define MT6325_SPK_OC_SHDN_DR_SHIFT 8
+#define MT6325_SPK_THER_SHDN_R_EN_MASK 0x1
+#define MT6325_SPK_THER_SHDN_R_EN_SHIFT 9
+#define MT6325_RG_SPK_GAINR_MASK 0x3
+#define MT6325_RG_SPK_GAINR_SHIFT 12
+#define MT6325_DA_SPK_OFFSET_R_MASK 0x1F
+#define MT6325_DA_SPK_OFFSET_R_SHIFT 0
+#define MT6325_DA_SPK_LEAD_DGLH_R_MASK 0x1
+#define MT6325_DA_SPK_LEAD_DGLH_R_SHIFT 5
+#define MT6325_NI_SPK_LEAD_R_MASK 0x1
+#define MT6325_NI_SPK_LEAD_R_SHIFT 6
+#define MT6325_SPK_OFFSET_R_OV_MASK 0x1
+#define MT6325_SPK_OFFSET_R_OV_SHIFT 7
+#define MT6325_SPK_OFFSET_R_SW_MASK 0x1F
+#define MT6325_SPK_OFFSET_R_SW_SHIFT 8
+#define MT6325_SPK_LEAD_R_SW_MASK 0x1
+#define MT6325_SPK_LEAD_R_SW_SHIFT 13
+#define MT6325_SPK_OFFSET_R_MODE_MASK 0x1
+#define MT6325_SPK_OFFSET_R_MODE_SHIFT 14
+#define MT6325_SPK_TRIM_DONE_R_MASK 0x1
+#define MT6325_SPK_TRIM_DONE_R_SHIFT 15
+#define MT6325_RG_SPK_INTG_RST_R_MASK 0x1
+#define MT6325_RG_SPK_INTG_RST_R_SHIFT 0
+#define MT6325_RG_SPK_FORCE_EN_R_MASK 0x1
+#define MT6325_RG_SPK_FORCE_EN_R_SHIFT 1
+#define MT6325_RG_SPK_SLEW_R_MASK 0x3
+#define MT6325_RG_SPK_SLEW_R_SHIFT 2
+#define MT6325_RG_SPKAB_OBIAS_R_MASK 0x3
+#define MT6325_RG_SPKAB_OBIAS_R_SHIFT 4
+#define MT6325_RG_SPKRCV_EN_R_MASK 0x1
+#define MT6325_RG_SPKRCV_EN_R_SHIFT 6
+#define MT6325_RG_SPK_DRC_EN_R_MASK 0x1
+#define MT6325_RG_SPK_DRC_EN_R_SHIFT 7
+#define MT6325_RG_SPK_TEST_EN_R_MASK 0x1
+#define MT6325_RG_SPK_TEST_EN_R_SHIFT 8
+#define MT6325_RG_SPKAB_OC_EN_R_MASK 0x1
+#define MT6325_RG_SPKAB_OC_EN_R_SHIFT 9
+#define MT6325_RG_SPK_OC_EN_R_MASK 0x1
+#define MT6325_RG_SPK_OC_EN_R_SHIFT 10
+#define MT6325_RG_SPKPGA_GAINR_MASK 0xF
+#define MT6325_RG_SPKPGA_GAINR_SHIFT 11
+#define MT6325_SPK_TRIM_WND_MASK 0x7
+#define MT6325_SPK_TRIM_WND_SHIFT 0
+#define MT6325_SPK_TRIM_THD_MASK 0x3
+#define MT6325_SPK_TRIM_THD_SHIFT 4
+#define MT6325_SPK_OC_WND_MASK 0x3
+#define MT6325_SPK_OC_WND_SHIFT 8
+#define MT6325_SPK_OC_THD_MASK 0x3
+#define MT6325_SPK_OC_THD_SHIFT 10
+#define MT6325_SPK_D_OC_R_DEG_MASK 0x1
+#define MT6325_SPK_D_OC_R_DEG_SHIFT 12
+#define MT6325_SPK_AB_OC_R_DEG_MASK 0x1
+#define MT6325_SPK_AB_OC_R_DEG_SHIFT 13
+#define MT6325_SPK_D_OC_L_DEG_MASK 0x1
+#define MT6325_SPK_D_OC_L_DEG_SHIFT 14
+#define MT6325_SPK_AB_OC_L_DEG_MASK 0x1
+#define MT6325_SPK_AB_OC_L_DEG_SHIFT 15
+#define MT6325_SPK_TD1_MASK 0xF
+#define MT6325_SPK_TD1_SHIFT 0
+#define MT6325_SPK_TD2_MASK 0xF
+#define MT6325_SPK_TD2_SHIFT 4
+#define MT6325_SPK_TD3_MASK 0xF
+#define MT6325_SPK_TD3_SHIFT 8
+#define MT6325_SPK_TRIM_DIV_MASK 0x7
+#define MT6325_SPK_TRIM_DIV_SHIFT 12
+#define MT6325_RG_BTL_SET_MASK 0x3
+#define MT6325_RG_BTL_SET_SHIFT 0
+#define MT6325_RG_SPK_IBIAS_SEL_MASK 0x3
+#define MT6325_RG_SPK_IBIAS_SEL_SHIFT 2
+#define MT6325_RG_SPK_CCODE_MASK 0xF
+#define MT6325_RG_SPK_CCODE_SHIFT 4
+#define MT6325_RG_SPK_EN_VIEW_VCM_MASK 0x1
+#define MT6325_RG_SPK_EN_VIEW_VCM_SHIFT 8
+#define MT6325_RG_SPK_EN_VIEW_CLK_MASK 0x1
+#define MT6325_RG_SPK_EN_VIEW_CLK_SHIFT 9
+#define MT6325_RG_SPK_VCM_SEL_MASK 0x1
+#define MT6325_RG_SPK_VCM_SEL_SHIFT 10
+#define MT6325_RG_SPK_VCM_IBSEL_MASK 0x1
+#define MT6325_RG_SPK_VCM_IBSEL_SHIFT 11
+#define MT6325_RG_SPK_FBRC_EN_MASK 0x1
+#define MT6325_RG_SPK_FBRC_EN_SHIFT 12
+#define MT6325_RG_SPKAB_OVDRV_MASK 0x1
+#define MT6325_RG_SPKAB_OVDRV_SHIFT 13
+#define MT6325_RG_SPK_OCTH_D_MASK 0x1
+#define MT6325_RG_SPK_OCTH_D_SHIFT 14
+#define MT6325_RG_SPKPGA_GAINL_MASK 0xF
+#define MT6325_RG_SPKPGA_GAINL_SHIFT 8
+#define MT6325_SPK_RSV0_MASK 0x1
+#define MT6325_SPK_RSV0_SHIFT 12
+#define MT6325_SPK_VCM_FAST_EN_MASK 0x1
+#define MT6325_SPK_VCM_FAST_EN_SHIFT 13
+#define MT6325_SPK_TEST_MODE0_MASK 0x1
+#define MT6325_SPK_TEST_MODE0_SHIFT 14
+#define MT6325_SPK_TEST_MODE1_MASK 0x1
+#define MT6325_SPK_TEST_MODE1_SHIFT 15
+#define MT6325_SPK_TD_WAIT_MASK 0x7
+#define MT6325_SPK_TD_WAIT_SHIFT 0
+#define MT6325_SPK_TD_DONE_MASK 0x7
+#define MT6325_SPK_TD_DONE_SHIFT 4
+#define MT6325_SPK_EN_MODE_MASK 0x1
+#define MT6325_SPK_EN_MODE_SHIFT 0
+#define MT6325_SPK_VCM_FAST_SW_MASK 0x1
+#define MT6325_SPK_VCM_FAST_SW_SHIFT 1
+#define MT6325_SPK_RST_R_SW_MASK 0x1
+#define MT6325_SPK_RST_R_SW_SHIFT 2
+#define MT6325_SPK_RST_L_SW_MASK 0x1
+#define MT6325_SPK_RST_L_SW_SHIFT 3
+#define MT6325_SPKMODE_R_SW_MASK 0x1
+#define MT6325_SPKMODE_R_SW_SHIFT 4
+#define MT6325_SPKMODE_L_SW_MASK 0x1
+#define MT6325_SPKMODE_L_SW_SHIFT 5
+#define MT6325_SPK_DEPOP_EN_R_SW_MASK 0x1
+#define MT6325_SPK_DEPOP_EN_R_SW_SHIFT 6
+#define MT6325_SPK_DEPOP_EN_L_SW_MASK 0x1
+#define MT6325_SPK_DEPOP_EN_L_SW_SHIFT 7
+#define MT6325_SPK_EN_R_SW_MASK 0x1
+#define MT6325_SPK_EN_R_SW_SHIFT 8
+#define MT6325_SPK_EN_L_SW_MASK 0x1
+#define MT6325_SPK_EN_L_SW_SHIFT 9
+#define MT6325_SPK_OUTSTG_EN_R_SW_MASK 0x1
+#define MT6325_SPK_OUTSTG_EN_R_SW_SHIFT 10
+#define MT6325_SPK_OUTSTG_EN_L_SW_MASK 0x1
+#define MT6325_SPK_OUTSTG_EN_L_SW_SHIFT 11
+#define MT6325_SPK_TRIM_EN_R_SW_MASK 0x1
+#define MT6325_SPK_TRIM_EN_R_SW_SHIFT 12
+#define MT6325_SPK_TRIM_EN_L_SW_MASK 0x1
+#define MT6325_SPK_TRIM_EN_L_SW_SHIFT 13
+#define MT6325_SPK_TRIM_STOP_R_SW_MASK 0x1
+#define MT6325_SPK_TRIM_STOP_R_SW_SHIFT 14
+#define MT6325_SPK_TRIM_STOP_L_SW_MASK 0x1
+#define MT6325_SPK_TRIM_STOP_L_SW_SHIFT 15
+#define MT6325_RG_SPK_ISENSE_TEST_EN_MASK 0x1
+#define MT6325_RG_SPK_ISENSE_TEST_EN_SHIFT 7
+#define MT6325_RG_SPK_ISENSE_REFSEL_MASK 0x7
+#define MT6325_RG_SPK_ISENSE_REFSEL_SHIFT 8
+#define MT6325_RG_SPK_ISENSE_GAINSEL_MASK 0x7
+#define MT6325_RG_SPK_ISENSE_GAINSEL_SHIFT 11
+#define MT6325_RG_SPK_ISENSE_PDRESET_MASK 0x1
+#define MT6325_RG_SPK_ISENSE_PDRESET_SHIFT 14
+#define MT6325_RG_SPK_ISENSE_EN_MASK 0x1
+#define MT6325_RG_SPK_ISENSE_EN_SHIFT 15
+#define MT6325_RG_SPK_RSV1_MASK 0xFF
+#define MT6325_RG_SPK_RSV1_SHIFT 0
+#define MT6325_RG_SPK_RSV0_MASK 0xFF
+#define MT6325_RG_SPK_RSV0_SHIFT 8
+#define MT6325_RG_SPK_ABD_VOLSEN_GAIN_MASK 0x3
+#define MT6325_RG_SPK_ABD_VOLSEN_GAIN_SHIFT 4
+#define MT6325_RG_SPK_ABD_VOLSEN_EN_MASK 0x1
+#define MT6325_RG_SPK_ABD_VOLSEN_EN_SHIFT 6
+#define MT6325_RG_SPK_ABD_CURSEN_SEL_MASK 0x1
+#define MT6325_RG_SPK_ABD_CURSEN_SEL_SHIFT 7
+#define MT6325_RG_SPK_RSV2_MASK 0xFF
+#define MT6325_RG_SPK_RSV2_SHIFT 8
+#define MT6325_RG_SPK_TRIM2_MASK 0xFF
+#define MT6325_RG_SPK_TRIM2_SHIFT 0
+#define MT6325_RG_SPK_TRIM1_MASK 0xFF
+#define MT6325_RG_SPK_TRIM1_SHIFT 8
+#define MT6325_RG_SPK_D_CURSEN_RSETSEL_MASK 0x1F
+#define MT6325_RG_SPK_D_CURSEN_RSETSEL_SHIFT 0
+#define MT6325_RG_SPK_D_CURSEN_GAIN_MASK 0x3
+#define MT6325_RG_SPK_D_CURSEN_GAIN_SHIFT 5
+#define MT6325_RG_SPK_D_CURSEN_EN_MASK 0x1
+#define MT6325_RG_SPK_D_CURSEN_EN_SHIFT 7
+#define MT6325_RG_SPK_AB_CURSEN_RSETSEL_MASK 0x1F
+#define MT6325_RG_SPK_AB_CURSEN_RSETSEL_SHIFT 8
+#define MT6325_RG_SPK_AB_CURSEN_GAIN_MASK 0x3
+#define MT6325_RG_SPK_AB_CURSEN_GAIN_SHIFT 13
+#define MT6325_RG_SPK_AB_CURSEN_EN_MASK 0x1
+#define MT6325_RG_SPK_AB_CURSEN_EN_SHIFT 15
+#define MT6325_RG_SPKPGA_GAIN_MASK 0xF
+#define MT6325_RG_SPKPGA_GAIN_SHIFT 11
+#define MT6325_RG_SPK_RSV_MASK 0xFF
+#define MT6325_RG_SPK_RSV_SHIFT 0
+#define MT6325_RG_ISENSE_PD_RESET_MASK 0x1
+#define MT6325_RG_ISENSE_PD_RESET_SHIFT 11
+#define MT6325_RG_AUDIVLPWRUP_VAUDP12_MASK 0x1
+#define MT6325_RG_AUDIVLPWRUP_VAUDP12_SHIFT 4
+#define MT6325_RG_AUDIVLSTARTUP_VAUDP12_MASK 0x1
+#define MT6325_RG_AUDIVLSTARTUP_VAUDP12_SHIFT 5
+#define MT6325_RG_AUDIVLMUXSEL_VAUDP12_MASK 0x7
+#define MT6325_RG_AUDIVLMUXSEL_VAUDP12_SHIFT 6
+#define MT6325_RG_AUDIVLMUTE_VAUDP12_MASK 0x1
+#define MT6325_RG_AUDIVLMUTE_VAUDP12_SHIFT 9
+#define MT6325_RG_OTP_PA_MASK 0x3F
+#define MT6325_RG_OTP_PA_SHIFT 0
+#define MT6325_RG_OTP_PDIN_MASK 0xFF
+#define MT6325_RG_OTP_PDIN_SHIFT 0
+#define MT6325_RG_OTP_PTM_MASK 0x3
+#define MT6325_RG_OTP_PTM_SHIFT 0
+#define MT6325_RG_OTP_PWE_MASK 0x3
+#define MT6325_RG_OTP_PWE_SHIFT 0
+#define MT6325_RG_OTP_PPROG_MASK 0x1
+#define MT6325_RG_OTP_PPROG_SHIFT 0
+#define MT6325_RG_OTP_PWE_SRC_MASK 0x1
+#define MT6325_RG_OTP_PWE_SRC_SHIFT 0
+#define MT6325_RG_OTP_PROG_PKEY_MASK 0xFFFF
+#define MT6325_RG_OTP_PROG_PKEY_SHIFT 0
+#define MT6325_RG_OTP_RD_PKEY_MASK 0xFFFF
+#define MT6325_RG_OTP_RD_PKEY_SHIFT 0
+#define MT6325_RG_OTP_RD_TRIG_MASK 0x1
+#define MT6325_RG_OTP_RD_TRIG_SHIFT 0
+#define MT6325_RG_RD_RDY_BYPASS_MASK 0x1
+#define MT6325_RG_RD_RDY_BYPASS_SHIFT 0
+#define MT6325_RG_SKIP_OTP_OUT_MASK 0x1
+#define MT6325_RG_SKIP_OTP_OUT_SHIFT 0
+#define MT6325_RG_OTP_RD_SW_MASK 0x1
+#define MT6325_RG_OTP_RD_SW_SHIFT 0
+#define MT6325_RG_OTP_DOUT_SW_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_SW_SHIFT 0
+#define MT6325_RG_OTP_RD_BUSY_MASK 0x1
+#define MT6325_RG_OTP_RD_BUSY_SHIFT 0
+#define MT6325_RG_OTP_RD_ACK_MASK 0x1
+#define MT6325_RG_OTP_RD_ACK_SHIFT 2
+#define MT6325_RG_OTP_PA_SW_MASK 0x1F
+#define MT6325_RG_OTP_PA_SW_SHIFT 0
+#define MT6325_RG_OTP_DOUT_0_15_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_0_15_SHIFT 0
+#define MT6325_RG_OTP_DOUT_16_31_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_16_31_SHIFT 0
+#define MT6325_RG_OTP_DOUT_32_47_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_32_47_SHIFT 0
+#define MT6325_RG_OTP_DOUT_48_63_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_48_63_SHIFT 0
+#define MT6325_RG_OTP_DOUT_64_79_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_64_79_SHIFT 0
+#define MT6325_RG_OTP_DOUT_80_95_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_80_95_SHIFT 0
+#define MT6325_RG_OTP_DOUT_96_111_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_96_111_SHIFT 0
+#define MT6325_RG_OTP_DOUT_112_127_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_112_127_SHIFT 0
+#define MT6325_RG_OTP_DOUT_128_143_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_128_143_SHIFT 0
+#define MT6325_RG_OTP_DOUT_144_159_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_144_159_SHIFT 0
+#define MT6325_RG_OTP_DOUT_160_175_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_160_175_SHIFT 0
+#define MT6325_RG_OTP_DOUT_176_191_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_176_191_SHIFT 0
+#define MT6325_RG_OTP_DOUT_192_207_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_192_207_SHIFT 0
+#define MT6325_RG_OTP_DOUT_208_223_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_208_223_SHIFT 0
+#define MT6325_RG_OTP_DOUT_224_239_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_224_239_SHIFT 0
+#define MT6325_RG_OTP_DOUT_240_255_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_240_255_SHIFT 0
+#define MT6325_RG_OTP_DOUT_256_271_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_256_271_SHIFT 0
+#define MT6325_RG_OTP_DOUT_272_287_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_272_287_SHIFT 0
+#define MT6325_RG_OTP_DOUT_288_303_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_288_303_SHIFT 0
+#define MT6325_RG_OTP_DOUT_304_319_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_304_319_SHIFT 0
+#define MT6325_RG_OTP_DOUT_320_335_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_320_335_SHIFT 0
+#define MT6325_RG_OTP_DOUT_336_351_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_336_351_SHIFT 0
+#define MT6325_RG_OTP_DOUT_352_367_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_352_367_SHIFT 0
+#define MT6325_RG_OTP_DOUT_368_383_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_368_383_SHIFT 0
+#define MT6325_RG_OTP_DOUT_384_399_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_384_399_SHIFT 0
+#define MT6325_RG_OTP_DOUT_400_415_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_400_415_SHIFT 0
+#define MT6325_RG_OTP_DOUT_416_431_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_416_431_SHIFT 0
+#define MT6325_RG_OTP_DOUT_432_447_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_432_447_SHIFT 0
+#define MT6325_RG_OTP_DOUT_448_463_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_448_463_SHIFT 0
+#define MT6325_RG_OTP_DOUT_464_479_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_464_479_SHIFT 0
+#define MT6325_RG_OTP_DOUT_480_495_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_480_495_SHIFT 0
+#define MT6325_RG_OTP_DOUT_496_511_MASK 0xFFFF
+#define MT6325_RG_OTP_DOUT_496_511_SHIFT 0
+#define MT6325_RG_OTP_VAL_0_15_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_0_15_SHIFT 0
+#define MT6325_RG_OTP_VAL_16_31_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_16_31_SHIFT 0
+#define MT6325_RG_OTP_VAL_32_47_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_32_47_SHIFT 0
+#define MT6325_RG_OTP_VAL_48_63_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_48_63_SHIFT 0
+#define MT6325_RG_OTP_VAL_64_79_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_64_79_SHIFT 0
+#define MT6325_RG_OTP_VAL_80_95_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_80_95_SHIFT 0
+#define MT6325_RG_OTP_VAL_96_111_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_96_111_SHIFT 0
+#define MT6325_RG_OTP_VAL_112_127_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_112_127_SHIFT 0
+#define MT6325_RG_OTP_VAL_128_143_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_128_143_SHIFT 0
+#define MT6325_RG_OTP_VAL_144_159_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_144_159_SHIFT 0
+#define MT6325_RG_OTP_VAL_160_175_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_160_175_SHIFT 0
+#define MT6325_RG_OTP_VAL_176_191_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_176_191_SHIFT 0
+#define MT6325_RG_OTP_VAL_192_207_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_192_207_SHIFT 0
+#define MT6325_RG_OTP_VAL_208_223_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_208_223_SHIFT 0
+#define MT6325_RG_OTP_VAL_224_239_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_224_239_SHIFT 0
+#define MT6325_RG_OTP_VAL_240_255_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_240_255_SHIFT 0
+#define MT6325_RG_OTP_VAL_256_271_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_256_271_SHIFT 0
+#define MT6325_RG_OTP_VAL_272_287_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_272_287_SHIFT 0
+#define MT6325_RG_OTP_VAL_288_303_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_288_303_SHIFT 0
+#define MT6325_RG_OTP_VAL_304_319_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_304_319_SHIFT 0
+#define MT6325_RG_OTP_VAL_320_335_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_320_335_SHIFT 0
+#define MT6325_RG_OTP_VAL_336_351_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_336_351_SHIFT 0
+#define MT6325_RG_OTP_VAL_352_367_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_352_367_SHIFT 0
+#define MT6325_RG_OTP_VAL_368_383_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_368_383_SHIFT 0
+#define MT6325_RG_OTP_VAL_384_399_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_384_399_SHIFT 0
+#define MT6325_RG_OTP_VAL_400_415_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_400_415_SHIFT 0
+#define MT6325_RG_OTP_VAL_416_431_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_416_431_SHIFT 0
+#define MT6325_RG_OTP_VAL_432_447_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_432_447_SHIFT 0
+#define MT6325_RG_OTP_VAL_448_463_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_448_463_SHIFT 0
+#define MT6325_RG_OTP_VAL_464_479_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_464_479_SHIFT 0
+#define MT6325_RG_OTP_VAL_480_495_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_480_495_SHIFT 0
+#define MT6325_RG_OTP_VAL_496_511_MASK 0xFFFF
+#define MT6325_RG_OTP_VAL_496_511_SHIFT 0
+#define MT6325_MIX_EOSC32_STP_LPDTB_MASK 0x1
+#define MT6325_MIX_EOSC32_STP_LPDTB_SHIFT 1
+#define MT6325_MIX_EOSC32_STP_LPDEN_MASK 0x1
+#define MT6325_MIX_EOSC32_STP_LPDEN_SHIFT 2
+#define MT6325_MIX_XOSC32_STP_PWDB_MASK 0x1
+#define MT6325_MIX_XOSC32_STP_PWDB_SHIFT 3
+#define MT6325_MIX_XOSC32_STP_LPDTB_MASK 0x1
+#define MT6325_MIX_XOSC32_STP_LPDTB_SHIFT 4
+#define MT6325_MIX_XOSC32_STP_LPDEN_MASK 0x1
+#define MT6325_MIX_XOSC32_STP_LPDEN_SHIFT 5
+#define MT6325_MIX_XOSC32_STP_LPDRST_MASK 0x1
+#define MT6325_MIX_XOSC32_STP_LPDRST_SHIFT 6
+#define MT6325_MIX_XOSC32_STP_CALI_MASK 0x1F
+#define MT6325_MIX_XOSC32_STP_CALI_SHIFT 7
+#define MT6325_STMP_MODE_MASK 0x1
+#define MT6325_STMP_MODE_SHIFT 12
+#define MT6325_MIX_EOSC32_STP_CHOP_EN_MASK 0x1
+#define MT6325_MIX_EOSC32_STP_CHOP_EN_SHIFT 0
+#define MT6325_MIX_DCXO_STP_LVSH_EN_MASK 0x1
+#define MT6325_MIX_DCXO_STP_LVSH_EN_SHIFT 1
+#define MT6325_MIX_PMU_STP_DDLO_VRTC_MASK 0x1
+#define MT6325_MIX_PMU_STP_DDLO_VRTC_SHIFT 2
+#define MT6325_MIX_PMU_STP_DDLO_VRTC_EN_MASK 0x1
+#define MT6325_MIX_PMU_STP_DDLO_VRTC_EN_SHIFT 3
+#define MT6325_MIX_RTC_STP_XOSC32_ENB_MASK 0x1
+#define MT6325_MIX_RTC_STP_XOSC32_ENB_SHIFT 4
+#define MT6325_MIX_DCXO_STP_TEST_DEGLITCH_MODE_MASK 0x1
+#define MT6325_MIX_DCXO_STP_TEST_DEGLITCH_MODE_SHIFT 5
+#define MT6325_MIX_EOSC32_STP_RSV_MASK 0x3
+#define MT6325_MIX_EOSC32_STP_RSV_SHIFT 6
+#define MT6325_MIX_EOSC32_VCT_EN_MASK 0x1
+#define MT6325_MIX_EOSC32_VCT_EN_SHIFT 8
+#define MT6325_MIX_EOSC32_OPT_MASK 0x3
+#define MT6325_MIX_EOSC32_OPT_SHIFT 9
+#define MT6325_MIX_RTC_STP_DEBUG_OUT_MASK 0x3
+#define MT6325_MIX_RTC_STP_DEBUG_OUT_SHIFT 0
+#define MT6325_MIX_RTC_STP_DEBUG_SEL_MASK 0x3
+#define MT6325_MIX_RTC_STP_DEBUG_SEL_SHIFT 4
+#define MT6325_MIX_RTC_STP_K_EOSC32_EN_MASK 0x1
+#define MT6325_MIX_RTC_STP_K_EOSC32_EN_SHIFT 7
+#define MT6325_MIX_RTC_STP_EMBCK_SEL_MASK 0x1
+#define MT6325_MIX_RTC_STP_EMBCK_SEL_SHIFT 8
+#define MT6325_MIX_STP_BBWAKEUP_MASK 0x1
+#define MT6325_MIX_STP_BBWAKEUP_SHIFT 9
+#define MT6325_MIX_STP_RTC_DDLO_MASK 0x1
+#define MT6325_MIX_STP_RTC_DDLO_SHIFT 10
+#define MT6325_MIX_RTC_XOSC32_ENB_MASK 0x1
+#define MT6325_MIX_RTC_XOSC32_ENB_SHIFT 11
+#define MT6325_MIX_EFUSE_XOSC32_ENB_OPT_MASK 0x1
+#define MT6325_MIX_EFUSE_XOSC32_ENB_OPT_SHIFT 12
+#define MT6325_FG_ON_MASK 0x1
+#define MT6325_FG_ON_SHIFT 0
+#define MT6325_FG_CAL_MASK 0x3
+#define MT6325_FG_CAL_SHIFT 2
+#define MT6325_FG_AUTOCALRATE_MASK 0x7
+#define MT6325_FG_AUTOCALRATE_SHIFT 4
+#define MT6325_FG_SW_CR_MASK 0x1
+#define MT6325_FG_SW_CR_SHIFT 8
+#define MT6325_FG_SW_READ_PRE_MASK 0x1
+#define MT6325_FG_SW_READ_PRE_SHIFT 9
+#define MT6325_FG_LATCHDATA_ST_MASK 0x1
+#define MT6325_FG_LATCHDATA_ST_SHIFT 10
+#define MT6325_FG_SW_CLEAR_MASK 0x1
+#define MT6325_FG_SW_CLEAR_SHIFT 11
+#define MT6325_FG_OFFSET_RST_MASK 0x1
+#define MT6325_FG_OFFSET_RST_SHIFT 12
+#define MT6325_FG_TIME_RST_MASK 0x1
+#define MT6325_FG_TIME_RST_SHIFT 13
+#define MT6325_FG_CHARGE_RST_MASK 0x1
+#define MT6325_FG_CHARGE_RST_SHIFT 14
+#define MT6325_FG_SW_RSTCLR_MASK 0x1
+#define MT6325_FG_SW_RSTCLR_SHIFT 15
+#define MT6325_FG_CAR_31_16_MASK 0xFFFF
+#define MT6325_FG_CAR_31_16_SHIFT 0
+#define MT6325_FG_CAR_15_00_MASK 0xFFFF
+#define MT6325_FG_CAR_15_00_SHIFT 0
+#define MT6325_FG_NTER_29_16_MASK 0x3FFF
+#define MT6325_FG_NTER_29_16_SHIFT 0
+#define MT6325_FG_NTER_15_00_MASK 0xFFFF
+#define MT6325_FG_NTER_15_00_SHIFT 0
+#define MT6325_FG_BLTR_MASK 0xFFFF
+#define MT6325_FG_BLTR_SHIFT 0
+#define MT6325_FG_BFTR_MASK 0xFFFF
+#define MT6325_FG_BFTR_SHIFT 0
+#define MT6325_FG_CURRENT_OUT_MASK 0xFFFF
+#define MT6325_FG_CURRENT_OUT_SHIFT 0
+#define MT6325_FG_ADJUST_OFFSET_VALUE_MASK 0xFFFF
+#define MT6325_FG_ADJUST_OFFSET_VALUE_SHIFT 0
+#define MT6325_FG_OFFSET_MASK 0xFFFF
+#define MT6325_FG_OFFSET_SHIFT 0
+#define MT6325_RG_FGRINTMODE_MASK 0x1
+#define MT6325_RG_FGRINTMODE_SHIFT 0
+#define MT6325_RG_FGANALOGTEST_MASK 0xF
+#define MT6325_RG_FGANALOGTEST_SHIFT 4
+#define MT6325_RG_SPARE_MASK 0xFF
+#define MT6325_RG_SPARE_SHIFT 8
+#define MT6325_FG_OSR_MASK 0xF
+#define MT6325_FG_OSR_SHIFT 0
+#define MT6325_FG_ADJ_OFFSET_EN_MASK 0x1
+#define MT6325_FG_ADJ_OFFSET_EN_SHIFT 8
+#define MT6325_FG_ADC_AUTORST_MASK 0x1
+#define MT6325_FG_ADC_AUTORST_SHIFT 9
+#define MT6325_FG_FIR1BYPASS_MASK 0x1
+#define MT6325_FG_FIR1BYPASS_SHIFT 0
+#define MT6325_FG_FIR2BYPASS_MASK 0x1
+#define MT6325_FG_FIR2BYPASS_SHIFT 1
+#define MT6325_FG_L_CUR_INT_STS_MASK 0x1
+#define MT6325_FG_L_CUR_INT_STS_SHIFT 2
+#define MT6325_FG_H_CUR_INT_STS_MASK 0x1
+#define MT6325_FG_H_CUR_INT_STS_SHIFT 3
+#define MT6325_FG_L_INT_STS_MASK 0x1
+#define MT6325_FG_L_INT_STS_SHIFT 4
+#define MT6325_FG_H_INT_STS_MASK 0x1
+#define MT6325_FG_H_INT_STS_SHIFT 5
+#define MT6325_FG_ADC_RSTDETECT_MASK 0x1
+#define MT6325_FG_ADC_RSTDETECT_SHIFT 7
+#define MT6325_FG_SLP_EN_MASK 0x1
+#define MT6325_FG_SLP_EN_SHIFT 8
+#define MT6325_FG_ZCV_DET_EN_MASK 0x1
+#define MT6325_FG_ZCV_DET_EN_SHIFT 9
+#define MT6325_RG_FG_AUXADC_R_MASK 0x1
+#define MT6325_RG_FG_AUXADC_R_SHIFT 10
+#define MT6325_FGADC_EN_MASK 0x1
+#define MT6325_FGADC_EN_SHIFT 12
+#define MT6325_FGCAL_EN_MASK 0x1
+#define MT6325_FGCAL_EN_SHIFT 13
+#define MT6325_FG_RST_MASK 0x1
+#define MT6325_FG_RST_SHIFT 14
+#define MT6325_FG_CIC2_MASK 0xFFFF
+#define MT6325_FG_CIC2_SHIFT 0
+#define MT6325_FG_SLP_CUR_TH_MASK 0xFFFF
+#define MT6325_FG_SLP_CUR_TH_SHIFT 0
+#define MT6325_FG_SLP_TIME_MASK 0xFF
+#define MT6325_FG_SLP_TIME_SHIFT 0
+#define MT6325_FG_SRCVOLTEN_FTIME_MASK 0xFF
+#define MT6325_FG_SRCVOLTEN_FTIME_SHIFT 0
+#define MT6325_FG_DET_TIME_MASK 0xFF
+#define MT6325_FG_DET_TIME_SHIFT 8
+#define MT6325_FG_ZCV_CAR_31_16_MASK 0xFFFF
+#define MT6325_FG_ZCV_CAR_31_16_SHIFT 0
+#define MT6325_FG_ZCV_CAR_15_00_MASK 0xFFFF
+#define MT6325_FG_ZCV_CAR_15_00_SHIFT 0
+#define MT6325_FG_ZCV_CURR_MASK 0xFFFF
+#define MT6325_FG_ZCV_CURR_SHIFT 0
+#define MT6325_FG_R_CURR_MASK 0xFFFF
+#define MT6325_FG_R_CURR_SHIFT 0
+#define MT6325_FG_MODE_MASK 0x1
+#define MT6325_FG_MODE_SHIFT 0
+#define MT6325_FG_RST_SW_MASK 0x1
+#define MT6325_FG_RST_SW_SHIFT 1
+#define MT6325_FG_FGCAL_EN_SW_MASK 0x1
+#define MT6325_FG_FGCAL_EN_SW_SHIFT 2
+#define MT6325_FG_FGADC_EN_SW_MASK 0x1
+#define MT6325_FG_FGADC_EN_SW_SHIFT 3
+#define MT6325_FG_RSV1_MASK 0xF
+#define MT6325_FG_RSV1_SHIFT 4
+#define MT6325_FG_TEST_MODE0_MASK 0x1
+#define MT6325_FG_TEST_MODE0_SHIFT 14
+#define MT6325_FG_TEST_MODE1_MASK 0x1
+#define MT6325_FG_TEST_MODE1_SHIFT 15
+#define MT6325_FG_GAIN_MASK 0x1FFF
+#define MT6325_FG_GAIN_SHIFT 0
+#define MT6325_FG_CUR_HTH_MASK 0xFFFF
+#define MT6325_FG_CUR_HTH_SHIFT 0
+#define MT6325_FG_CUR_LTH_MASK 0xFFFF
+#define MT6325_FG_CUR_LTH_SHIFT 0
+#define MT6325_FG_ZCV_DET_TIME_MASK 0x3F
+#define MT6325_FG_ZCV_DET_TIME_SHIFT 0
+#define MT6325_FG_ZCV_CAR_TH_30_16_MASK 0x7FFF
+#define MT6325_FG_ZCV_CAR_TH_30_16_SHIFT 0
+#define MT6325_FG_ZCV_CAR_TH_15_00_MASK 0xFFFF
+#define MT6325_FG_ZCV_CAR_TH_15_00_SHIFT 0
+#define MT6325_RG_FGINTMODE_MASK 0x1
+#define MT6325_RG_FGINTMODE_SHIFT 4
+#define MT6325_RG_AUDDACLPWRUP_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDDACLPWRUP_VAUDP15_SHIFT 0
+#define MT6325_RG_AUDDACRPWRUP_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDDACRPWRUP_VAUDP15_SHIFT 1
+#define MT6325_RG_AUD_DAC_PWR_UP_VA28_MASK 0x1
+#define MT6325_RG_AUD_DAC_PWR_UP_VA28_SHIFT 2
+#define MT6325_RG_AUD_DAC_PWL_UP_VA28_MASK 0x1
+#define MT6325_RG_AUD_DAC_PWL_UP_VA28_SHIFT 3
+#define MT6325_RG_AUDHSPWRUP_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHSPWRUP_VAUDP15_SHIFT 4
+#define MT6325_RG_AUDHPLPWRUP_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPLPWRUP_VAUDP15_SHIFT 5
+#define MT6325_RG_AUDHPRPWRUP_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPRPWRUP_VAUDP15_SHIFT 6
+#define MT6325_RG_AUDHSMUXINPUTSEL_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDHSMUXINPUTSEL_VAUDP15_SHIFT 7
+#define MT6325_RG_AUDHPLMUXINPUTSEL_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDHPLMUXINPUTSEL_VAUDP15_SHIFT 9
+#define MT6325_RG_AUDHPRMUXINPUTSEL_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDHPRMUXINPUTSEL_VAUDP15_SHIFT 11
+#define MT6325_RG_AUDHSSCDISABLE_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHSSCDISABLE_VAUDP15_SHIFT 13
+#define MT6325_RG_AUDHPLSCDISABLE_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPLSCDISABLE_VAUDP15_SHIFT 14
+#define MT6325_RG_AUDHPRSCDISABLE_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPRSCDISABLE_VAUDP15_SHIFT 15
+#define MT6325_RG_AUDHPLBSCCURRENT_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPLBSCCURRENT_VAUDP15_SHIFT 0
+#define MT6325_RG_AUDHPRBSCCURRENT_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPRBSCCURRENT_VAUDP15_SHIFT 1
+#define MT6325_RG_AUDHSBSCCURRENT_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHSBSCCURRENT_VAUDP15_SHIFT 2
+#define MT6325_RG_AUDHPSTARTUP_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPSTARTUP_VAUDP15_SHIFT 3
+#define MT6325_RG_AUDHSSTARTUP_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHSSTARTUP_VAUDP15_SHIFT 4
+#define MT6325_RG_PRECHARGEBUF_EN_VAUDP15_MASK 0x1
+#define MT6325_RG_PRECHARGEBUF_EN_VAUDP15_SHIFT 5
+#define MT6325_RG_HPINPUTSTBENH_VAUDP15_MASK 0x1
+#define MT6325_RG_HPINPUTSTBENH_VAUDP15_SHIFT 6
+#define MT6325_RG_HPOUTPUTSTBENH_VAUDP15_MASK 0x1
+#define MT6325_RG_HPOUTPUTSTBENH_VAUDP15_SHIFT 7
+#define MT6325_RG_HPINPUTRESET0_VAUDP15_MASK 0x1
+#define MT6325_RG_HPINPUTRESET0_VAUDP15_SHIFT 8
+#define MT6325_RG_HPOUTPUTRESET0_VAUDP15_MASK 0x1
+#define MT6325_RG_HPOUTPUTRESET0_VAUDP15_SHIFT 9
+#define MT6325_RG_HPOUT_SHORTVCM_VAUDP15_MASK 0x1
+#define MT6325_RG_HPOUT_SHORTVCM_VAUDP15_SHIFT 10
+#define MT6325_RG_HSINPUTSTBENH_VAUDP15_MASK 0x1
+#define MT6325_RG_HSINPUTSTBENH_VAUDP15_SHIFT 11
+#define MT6325_RG_HSOUTPUTSTBENH_VAUDP15_MASK 0x1
+#define MT6325_RG_HSOUTPUTSTBENH_VAUDP15_SHIFT 12
+#define MT6325_RG_HSINPUTRESET0_VAUDP15_MASK 0x1
+#define MT6325_RG_HSINPUTRESET0_VAUDP15_SHIFT 13
+#define MT6325_RG_HSOUTPUTRESET0_VAUDP15_MASK 0x1
+#define MT6325_RG_HSOUTPUTRESET0_VAUDP15_SHIFT 14
+#define MT6325_RG_HPOUTSTB_RSEL_VAUDP15_MASK 0x3
+#define MT6325_RG_HPOUTSTB_RSEL_VAUDP15_SHIFT 0
+#define MT6325_RG_HSOUT_SHORTVCM_VAUDP15_MASK 0x1
+#define MT6325_RG_HSOUT_SHORTVCM_VAUDP15_SHIFT 2
+#define MT6325_RG_AUDHPLTRIM_VAUDP15_MASK 0xF
+#define MT6325_RG_AUDHPLTRIM_VAUDP15_SHIFT 3
+#define MT6325_RG_AUDHPRTRIM_VAUDP15_MASK 0xF
+#define MT6325_RG_AUDHPRTRIM_VAUDP15_SHIFT 7
+#define MT6325_RG_AUDHPTRIM_EN_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPTRIM_EN_VAUDP15_SHIFT 11
+#define MT6325_RG_AUDHPLFINETRIM_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDHPLFINETRIM_VAUDP15_SHIFT 12
+#define MT6325_RG_AUDHPRFINETRIM_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDHPRFINETRIM_VAUDP15_SHIFT 14
+#define MT6325_RG_AUDTRIMBUF_EN_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDTRIMBUF_EN_VAUDP15_SHIFT 0
+#define MT6325_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_MASK 0xF
+#define MT6325_RG_AUDTRIMBUF_INPUTMUXSEL_VAUDP15_SHIFT 1
+#define MT6325_RG_AUDTRIMBUF_GAINSEL_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDTRIMBUF_GAINSEL_VAUDP15_SHIFT 5
+#define MT6325_RG_AUDHPSPKDET_EN_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDHPSPKDET_EN_VAUDP15_SHIFT 7
+#define MT6325_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDHPSPKDET_INPUTMUXSEL_VAUDP15_SHIFT 8
+#define MT6325_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_MASK 0x3
+#define MT6325_RG_AUDHPSPKDET_OUTPUTMUXSEL_VAUDP15_SHIFT 10
+#define MT6325_RG_ABIDEC_RESERVED_VA28_MASK 0xFF
+#define MT6325_RG_ABIDEC_RESERVED_VA28_SHIFT 0
+#define MT6325_RG_ABIDEC_RESERVED_VAUDP15_MASK 0xFF
+#define MT6325_RG_ABIDEC_RESERVED_VAUDP15_SHIFT 8
+#define MT6325_RG_AUDBIASADJ_0_VAUDP15_MASK 0x3F
+#define MT6325_RG_AUDBIASADJ_0_VAUDP15_SHIFT 4
+#define MT6325_RG_AUDBIASADJ_1_VAUDP15_MASK 0x3F
+#define MT6325_RG_AUDBIASADJ_1_VAUDP15_SHIFT 10
+#define MT6325_RG_AUDIBIASPWRDN_VAUDP15_MASK 0x1
+#define MT6325_RG_AUDIBIASPWRDN_VAUDP15_SHIFT 0
+#define MT6325_RG_RSTB_DECODER_VA28_MASK 0x1
+#define MT6325_RG_RSTB_DECODER_VA28_SHIFT 1
+#define MT6325_RG_RSTB_ENCODER_VA28_MASK 0x1
+#define MT6325_RG_RSTB_ENCODER_VA28_SHIFT 2
+#define MT6325_RG_SEL_DECODER_96K_VA28_MASK 0x1
+#define MT6325_RG_SEL_DECODER_96K_VA28_SHIFT 3
+#define MT6325_RG_SEL_ENCODER_96K_VA28_MASK 0x1
+#define MT6325_RG_SEL_ENCODER_96K_VA28_SHIFT 4
+#define MT6325_RG_SEL_DELAY_VCORE_MASK 0x1
+#define MT6325_RG_SEL_DELAY_VCORE_SHIFT 5
+#define MT6325_RG_HCLDO_EN_VA18_MASK 0x1
+#define MT6325_RG_HCLDO_EN_VA18_SHIFT 6
+#define MT6325_RG_LCLDO_EN_VA18_MASK 0x1
+#define MT6325_RG_LCLDO_EN_VA18_SHIFT 7
+#define MT6325_RG_LCLDO_ENC_EN_VA28_MASK 0x1
+#define MT6325_RG_LCLDO_ENC_EN_VA28_SHIFT 8
+#define MT6325_RG_VA33REFGEN_EN_VA18_MASK 0x1
+#define MT6325_RG_VA33REFGEN_EN_VA18_SHIFT 9
+#define MT6325_RG_HCLDO_PDDIS_EN_VA18_MASK 0x1
+#define MT6325_RG_HCLDO_PDDIS_EN_VA18_SHIFT 10
+#define MT6325_RG_HCLDO_REMOTE_SENSE_VA18_MASK 0x1
+#define MT6325_RG_HCLDO_REMOTE_SENSE_VA18_SHIFT 11
+#define MT6325_RG_LCLDO_PDDIS_EN_VA18_MASK 0x1
+#define MT6325_RG_LCLDO_PDDIS_EN_VA18_SHIFT 12
+#define MT6325_RG_LCLDO_REMOTE_SENSE_VA18_MASK 0x1
+#define MT6325_RG_LCLDO_REMOTE_SENSE_VA18_SHIFT 13
+#define MT6325_RG_LCLDO_VOSEL_VA18_MASK 0x1
+#define MT6325_RG_LCLDO_VOSEL_VA18_SHIFT 14
+#define MT6325_RG_HCLDO_VOSEL_VA18_MASK 0x1
+#define MT6325_RG_HCLDO_VOSEL_VA18_SHIFT 15
+#define MT6325_RG_LCLDO_ENC_PDDIS_EN_VA28_MASK 0x1
+#define MT6325_RG_LCLDO_ENC_PDDIS_EN_VA28_SHIFT 0
+#define MT6325_RG_LCLDO_ENC_REMOTE_SENSE_VA28_MASK 0x1
+#define MT6325_RG_LCLDO_ENC_REMOTE_SENSE_VA28_SHIFT 1
+#define MT6325_RG_VA28REFGEN_EN_VA28_MASK 0x1
+#define MT6325_RG_VA28REFGEN_EN_VA28_SHIFT 2
+#define MT6325_RG_AUDPMU_RESERVED_VA28_MASK 0xF
+#define MT6325_RG_AUDPMU_RESERVED_VA28_SHIFT 3
+#define MT6325_RG_AUDPMU_RESERVED_VA18_MASK 0xF
+#define MT6325_RG_AUDPMU_RESERVED_VA18_SHIFT 7
+#define MT6325_RG_AUDPMU_RESERVED_VAUDP15_MASK 0xF
+#define MT6325_RG_AUDPMU_RESERVED_VAUDP15_SHIFT 11
+#define MT6325_RG_NVREG_EN_VAUDP15_MASK 0x1
+#define MT6325_RG_NVREG_EN_VAUDP15_SHIFT 15
+#define MT6325_RG_NVREG_PULL0V_VAUDP15_MASK 0x1
+#define MT6325_RG_NVREG_PULL0V_VAUDP15_SHIFT 0
+#define MT6325_RG_AUDGLB_PWRDN_VA28_MASK 0x1
+#define MT6325_RG_AUDGLB_PWRDN_VA28_SHIFT 1
+#define MT6325_RG_AUDPREAMPLON_MASK 0x1
+#define MT6325_RG_AUDPREAMPLON_SHIFT 0
+#define MT6325_RG_AUDPREAMPLDCCEN_MASK 0x1
+#define MT6325_RG_AUDPREAMPLDCCEN_SHIFT 1
+#define MT6325_RG_AUDPREAMPLDCRPECHARGE_MASK 0x1
+#define MT6325_RG_AUDPREAMPLDCRPECHARGE_SHIFT 2
+#define MT6325_RG_AUDPREAMPLPGATEST_MASK 0x1
+#define MT6325_RG_AUDPREAMPLPGATEST_SHIFT 3
+#define MT6325_RG_AUDPREAMPLVSCALE_MASK 0x3
+#define MT6325_RG_AUDPREAMPLVSCALE_SHIFT 4
+#define MT6325_RG_AUDPREAMPLINPUTSEL_MASK 0x3
+#define MT6325_RG_AUDPREAMPLINPUTSEL_SHIFT 6
+#define MT6325_RG_AUDADCLPWRUP_MASK 0x1
+#define MT6325_RG_AUDADCLPWRUP_SHIFT 8
+#define MT6325_RG_AUDADCLINPUTSEL_MASK 0x3
+#define MT6325_RG_AUDADCLINPUTSEL_SHIFT 9
+#define MT6325_RG_AUDPREAMPRON_MASK 0x1
+#define MT6325_RG_AUDPREAMPRON_SHIFT 0
+#define MT6325_RG_AUDPREAMPRDCCEN_MASK 0x1
+#define MT6325_RG_AUDPREAMPRDCCEN_SHIFT 1
+#define MT6325_RG_AUDPREAMPRDCRPECHARGE_MASK 0x1
+#define MT6325_RG_AUDPREAMPRDCRPECHARGE_SHIFT 2
+#define MT6325_RG_AUDPREAMPRPGATEST_MASK 0x1
+#define MT6325_RG_AUDPREAMPRPGATEST_SHIFT 3
+#define MT6325_RG_AUDPREAMPRVSCALE_MASK 0x3
+#define MT6325_RG_AUDPREAMPRVSCALE_SHIFT 4
+#define MT6325_RG_AUDPREAMPRINPUTSEL_MASK 0x3
+#define MT6325_RG_AUDPREAMPRINPUTSEL_SHIFT 6
+#define MT6325_RG_AUDADCRPWRUP_MASK 0x1
+#define MT6325_RG_AUDADCRPWRUP_SHIFT 8
+#define MT6325_RG_AUDADCRINPUTSEL_MASK 0x3
+#define MT6325_RG_AUDADCRINPUTSEL_SHIFT 9
+#define MT6325_RG_AUDULHALFBIAS_MASK 0x1
+#define MT6325_RG_AUDULHALFBIAS_SHIFT 0
+#define MT6325_RG_AUDGLBVOWLPWEN_MASK 0x1
+#define MT6325_RG_AUDGLBVOWLPWEN_SHIFT 1
+#define MT6325_RG_AUDPREAMPLPEN_MASK 0x1
+#define MT6325_RG_AUDPREAMPLPEN_SHIFT 2
+#define MT6325_RG_AUDADC1STSTAGELPEN_MASK 0x1
+#define MT6325_RG_AUDADC1STSTAGELPEN_SHIFT 3
+#define MT6325_RG_AUDADC2NDSTAGELPEN_MASK 0x1
+#define MT6325_RG_AUDADC2NDSTAGELPEN_SHIFT 4
+#define MT6325_RG_AUDADCFLASHLPEN_MASK 0x1
+#define MT6325_RG_AUDADCFLASHLPEN_SHIFT 5
+#define MT6325_RG_AUDPREAMPIDDTEST_MASK 0x3
+#define MT6325_RG_AUDPREAMPIDDTEST_SHIFT 6
+#define MT6325_RG_AUDADC1STSTAGEIDDTEST_MASK 0x3
+#define MT6325_RG_AUDADC1STSTAGEIDDTEST_SHIFT 8
+#define MT6325_RG_AUDADC2NDSTAGEIDDTEST_MASK 0x3
+#define MT6325_RG_AUDADC2NDSTAGEIDDTEST_SHIFT 10
+#define MT6325_RG_AUDADCREFBUFIDDTEST_MASK 0x3
+#define MT6325_RG_AUDADCREFBUFIDDTEST_SHIFT 12
+#define MT6325_RG_AUDADCFLASHIDDTEST_MASK 0x3
+#define MT6325_RG_AUDADCFLASHIDDTEST_SHIFT 14
+#define MT6325_RG_AUDADCDAC0P25FS_MASK 0x1
+#define MT6325_RG_AUDADCDAC0P25FS_SHIFT 0
+#define MT6325_RG_AUDADCCLKSEL_MASK 0x1
+#define MT6325_RG_AUDADCCLKSEL_SHIFT 1
+#define MT6325_RG_AUDADCCLKSOURCE_MASK 0x3
+#define MT6325_RG_AUDADCCLKSOURCE_SHIFT 2
+#define MT6325_RG_AUDADCCLKGENMODE_MASK 0x3
+#define MT6325_RG_AUDADCCLKGENMODE_SHIFT 4
+#define MT6325_RG_AUDPREAMPAAFEN_MASK 0x1
+#define MT6325_RG_AUDPREAMPAAFEN_SHIFT 8
+#define MT6325_RG_DCCVCMBUFLPMODSEL_MASK 0x1
+#define MT6325_RG_DCCVCMBUFLPMODSEL_SHIFT 9
+#define MT6325_RG_DCCVCMBUFLPSWEN_MASK 0x1
+#define MT6325_RG_DCCVCMBUFLPSWEN_SHIFT 10
+#define MT6325_RG_AUDSPAREPGA_MASK 0x1F
+#define MT6325_RG_AUDSPAREPGA_SHIFT 11
+#define MT6325_RG_AUDADC1STSTAGESDENB_MASK 0x1
+#define MT6325_RG_AUDADC1STSTAGESDENB_SHIFT 0
+#define MT6325_RG_AUDADC2NDSTAGERESET_MASK 0x1
+#define MT6325_RG_AUDADC2NDSTAGERESET_SHIFT 1
+#define MT6325_RG_AUDADC3RDSTAGERESET_MASK 0x1
+#define MT6325_RG_AUDADC3RDSTAGERESET_SHIFT 2
+#define MT6325_RG_AUDADCFSRESET_MASK 0x1
+#define MT6325_RG_AUDADCFSRESET_SHIFT 3
+#define MT6325_RG_AUDADCWIDECM_MASK 0x1
+#define MT6325_RG_AUDADCWIDECM_SHIFT 4
+#define MT6325_RG_AUDADCNOPATEST_MASK 0x1
+#define MT6325_RG_AUDADCNOPATEST_SHIFT 5
+#define MT6325_RG_AUDADCBYPASS_MASK 0x1
+#define MT6325_RG_AUDADCBYPASS_SHIFT 6
+#define MT6325_RG_AUDADCFFBYPASS_MASK 0x1
+#define MT6325_RG_AUDADCFFBYPASS_SHIFT 7
+#define MT6325_RG_AUDADCDACFBCURRENT_MASK 0x1
+#define MT6325_RG_AUDADCDACFBCURRENT_SHIFT 8
+#define MT6325_RG_AUDADCDACIDDTEST_MASK 0x3
+#define MT6325_RG_AUDADCDACIDDTEST_SHIFT 9
+#define MT6325_RG_AUDADCDACNRZ_MASK 0x1
+#define MT6325_RG_AUDADCDACNRZ_SHIFT 11
+#define MT6325_RG_AUDADCNODEM_MASK 0x1
+#define MT6325_RG_AUDADCNODEM_SHIFT 12
+#define MT6325_RG_AUDADCDACTEST_MASK 0x1
+#define MT6325_RG_AUDADCDACTEST_SHIFT 13
+#define MT6325_RG_AUDADCTESTDATA_MASK 0xFFFF
+#define MT6325_RG_AUDADCTESTDATA_SHIFT 0
+#define MT6325_RG_AUDRCTUNEL_MASK 0x1F
+#define MT6325_RG_AUDRCTUNEL_SHIFT 0
+#define MT6325_RG_AUDRCTUNELSEL_MASK 0x1
+#define MT6325_RG_AUDRCTUNELSEL_SHIFT 5
+#define MT6325_RG_AUDRCTUNER_MASK 0x1F
+#define MT6325_RG_AUDRCTUNER_SHIFT 8
+#define MT6325_RG_AUDRCTUNERSEL_MASK 0x1
+#define MT6325_RG_AUDRCTUNERSEL_SHIFT 13
+#define MT6325_RG_AUDSPAREVA28_MASK 0xFF
+#define MT6325_RG_AUDSPAREVA28_SHIFT 0
+#define MT6325_RG_AUDSPAREVA18_MASK 0xFF
+#define MT6325_RG_AUDSPAREVA18_SHIFT 8
+#define MT6325_RG_AUDDIGMICEN_MASK 0x1
+#define MT6325_RG_AUDDIGMICEN_SHIFT 0
+#define MT6325_RG_AUDDIGMICBIAS_MASK 0x3
+#define MT6325_RG_AUDDIGMICBIAS_SHIFT 1
+#define MT6325_RG_DMICHPCLKEN_MASK 0x1
+#define MT6325_RG_DMICHPCLKEN_SHIFT 3
+#define MT6325_RG_AUDDIGMICPDUTY_MASK 0x3
+#define MT6325_RG_AUDDIGMICPDUTY_SHIFT 4
+#define MT6325_RG_AUDDIGMICNDUTY_MASK 0x3
+#define MT6325_RG_AUDDIGMICNDUTY_SHIFT 6
+#define MT6325_RG_DMICMONEN_MASK 0x1
+#define MT6325_RG_DMICMONEN_SHIFT 8
+#define MT6325_RG_DMICMONSEL_MASK 0x7
+#define MT6325_RG_DMICMONSEL_SHIFT 9
+#define MT6325_RG_AUDSPAREVMIC_MASK 0xF
+#define MT6325_RG_AUDSPAREVMIC_SHIFT 12
+#define MT6325_RG_AUDPWDBMICBIAS0_MASK 0x1
+#define MT6325_RG_AUDPWDBMICBIAS0_SHIFT 0
+#define MT6325_RG_AUDMICBIAS0DCSWPEN_MASK 0x1
+#define MT6325_RG_AUDMICBIAS0DCSWPEN_SHIFT 1
+#define MT6325_RG_AUDMICBIAS0DCSWNEN_MASK 0x1
+#define MT6325_RG_AUDMICBIAS0DCSWNEN_SHIFT 2
+#define MT6325_RG_AUDMICBIAS0BYPASSEN_MASK 0x1
+#define MT6325_RG_AUDMICBIAS0BYPASSEN_SHIFT 3
+#define MT6325_RG_AUDPWDBMICBIAS1_MASK 0x1
+#define MT6325_RG_AUDPWDBMICBIAS1_SHIFT 4
+#define MT6325_RG_AUDMICBIAS1DCSWPEN_MASK 0x1
+#define MT6325_RG_AUDMICBIAS1DCSWPEN_SHIFT 5
+#define MT6325_RG_AUDMICBIAS1DCSWNEN_MASK 0x1
+#define MT6325_RG_AUDMICBIAS1DCSWNEN_SHIFT 6
+#define MT6325_RG_AUDMICBIAS1BYPASSEN_MASK 0x1
+#define MT6325_RG_AUDMICBIAS1BYPASSEN_SHIFT 7
+#define MT6325_RG_AUDMICBIASVREF_MASK 0x7
+#define MT6325_RG_AUDMICBIASVREF_SHIFT 8
+#define MT6325_RG_AUDMICBIASLOWPEN_MASK 0x1
+#define MT6325_RG_AUDMICBIASLOWPEN_SHIFT 11
+#define MT6325_RG_BANDGAPGEN_MASK 0x1
+#define MT6325_RG_BANDGAPGEN_SHIFT 12
+#define MT6325_RG_AUDENCSPAREVA28_MASK 0xFF
+#define MT6325_RG_AUDENCSPAREVA28_SHIFT 0
+#define MT6325_RG_AUDENCSPAREVA18_MASK 0xFF
+#define MT6325_RG_AUDENCSPAREVA18_SHIFT 8
+#define MT6325_RG_PLL_EN_MASK 0x1
+#define MT6325_RG_PLL_EN_SHIFT 0
+#define MT6325_RG_PLLBS_RST_MASK 0x1
+#define MT6325_RG_PLLBS_RST_SHIFT 1
+#define MT6325_RG_PLL_DCKO_SEL_MASK 0x3
+#define MT6325_RG_PLL_DCKO_SEL_SHIFT 2
+#define MT6325_RG_PLL_DIV1_MASK 0x3F
+#define MT6325_RG_PLL_DIV1_SHIFT 4
+#define MT6325_RG_PLL_RLATCH_EN_MASK 0x1
+#define MT6325_RG_PLL_RLATCH_EN_SHIFT 10
+#define MT6325_RG_PLL_PDIV1_EN_MASK 0x1
+#define MT6325_RG_PLL_PDIV1_EN_SHIFT 11
+#define MT6325_RG_PLL_PDIV1_MASK 0xF
+#define MT6325_RG_PLL_PDIV1_SHIFT 12
+#define MT6325_RG_PLL_BC_MASK 0x3
+#define MT6325_RG_PLL_BC_SHIFT 0
+#define MT6325_RG_PLL_BP_MASK 0x3
+#define MT6325_RG_PLL_BP_SHIFT 2
+#define MT6325_RG_PLL_BR_MASK 0x3
+#define MT6325_RG_PLL_BR_SHIFT 4
+#define MT6325_RG_CKO_SEL_MASK 0x3
+#define MT6325_RG_CKO_SEL_SHIFT 6
+#define MT6325_RG_PLL_IBSEL_MASK 0x3
+#define MT6325_RG_PLL_IBSEL_SHIFT 8
+#define MT6325_RG_PLL_CKT_SEL_MASK 0x3
+#define MT6325_RG_PLL_CKT_SEL_SHIFT 10
+#define MT6325_RG_PLL_VCT_EN_MASK 0x1
+#define MT6325_RG_PLL_VCT_EN_SHIFT 12
+#define MT6325_RG_PLL_CKT_EN_MASK 0x1
+#define MT6325_RG_PLL_CKT_EN_SHIFT 13
+#define MT6325_RG_PLL_HPM_EN_MASK 0x1
+#define MT6325_RG_PLL_HPM_EN_SHIFT 14
+#define MT6325_RG_PLL_DCHP_EN_MASK 0x1
+#define MT6325_RG_PLL_DCHP_EN_SHIFT 15
+#define MT6325_RG_PLL_CDIV_MASK 0x7
+#define MT6325_RG_PLL_CDIV_SHIFT 0
+#define MT6325_RG_VCOBAND_MASK 0x7
+#define MT6325_RG_VCOBAND_SHIFT 3
+#define MT6325_RG_CKDRV_EN_MASK 0x1
+#define MT6325_RG_CKDRV_EN_SHIFT 6
+#define MT6325_RG_PLL_DCHP_AEN_MASK 0x1
+#define MT6325_RG_PLL_DCHP_AEN_SHIFT 7
+#define MT6325_RG_PLL_RSVA_MASK 0xFF
+#define MT6325_RG_PLL_RSVA_SHIFT 8
+#define MT6325_RG_AUDPREAMPLGAIN_MASK 0x7
+#define MT6325_RG_AUDPREAMPLGAIN_SHIFT 0
+#define MT6325_RG_AUDPREAMPRGAIN_MASK 0x7
+#define MT6325_RG_AUDPREAMPRGAIN_SHIFT 4
+#define MT6325_RG_DIVCKS_CHG_MASK 0x1
+#define MT6325_RG_DIVCKS_CHG_SHIFT 0
+#define MT6325_RG_DIVCKS_ON_MASK 0x1
+#define MT6325_RG_DIVCKS_ON_SHIFT 0
+#define MT6325_RG_DIVCKS_PRG_MASK 0x1FF
+#define MT6325_RG_DIVCKS_PRG_SHIFT 0
+#define MT6325_RG_DIVCKS_PWD_NCP_MASK 0x1
+#define MT6325_RG_DIVCKS_PWD_NCP_SHIFT 0
+#define MT6325_RG_DIVCKS_PWD_NCP_ST_SEL_MASK 0x3
+#define MT6325_RG_DIVCKS_PWD_NCP_ST_SEL_SHIFT 0
+#define MT6325_AUXADC_DIG0_RSV0_MASK 0xFFFF
+#define MT6325_AUXADC_DIG0_RSV0_SHIFT 0
+#define MT6325_AUXADC_ADC_BUSY_IN_MASK 0x1FFF
+#define MT6325_AUXADC_ADC_BUSY_IN_SHIFT 0
+#define MT6325_AUXADC_ADC_BUSY_IN_WAKEUP_PCHR_MASK 0x1
+#define MT6325_AUXADC_ADC_BUSY_IN_WAKEUP_PCHR_SHIFT 13
+#define MT6325_AUXADC_ADC_BUSY_IN_WAKEUP_SWCHR_MASK 0x1
+#define MT6325_AUXADC_ADC_BUSY_IN_WAKEUP_SWCHR_SHIFT 14
+#define MT6325_AUXADC_RO_RSV0_MASK 0x1
+#define MT6325_AUXADC_RO_RSV0_SHIFT 15
+#define MT6325_AUXADC_ADC_BUSY_IN_VISMPS0_MASK 0x1
+#define MT6325_AUXADC_ADC_BUSY_IN_VISMPS0_SHIFT 11
+#define MT6325_AUXADC_ADC_BUSY_IN_LBAT_MASK 0x1
+#define MT6325_AUXADC_ADC_BUSY_IN_LBAT_SHIFT 12
+#define MT6325_AUXADC_ADC_BUSY_IN_LBAT2_MASK 0x1
+#define MT6325_AUXADC_ADC_BUSY_IN_LBAT2_SHIFT 13
+#define MT6325_AUXADC_ADC_BUSY_IN_THR1_MASK 0x1
+#define MT6325_AUXADC_ADC_BUSY_IN_THR1_SHIFT 14
+#define MT6325_AUXADC_ADC_BUSY_IN_THR2_MASK 0x1
+#define MT6325_AUXADC_ADC_BUSY_IN_THR2_SHIFT 15
+#define MT6325_AUXADC_RQST0_RSV1_MASK 0xFF
+#define MT6325_AUXADC_RQST0_RSV1_SHIFT 0
+#define MT6325_AUXADC_RQST0_RSV0_MASK 0xFF
+#define MT6325_AUXADC_RQST0_RSV0_SHIFT 8
+#define MT6325_AUXADC_RQST0_SET_MASK 0xFFFF
+#define MT6325_AUXADC_RQST0_SET_SHIFT 0
+#define MT6325_AUXADC_RQST0_CLR_MASK 0xFFFF
+#define MT6325_AUXADC_RQST0_CLR_SHIFT 0
+#define MT6325_AUXADC_RQST_RSV0_MASK 0xF
+#define MT6325_AUXADC_RQST_RSV0_SHIFT 0
+#define MT6325_AUXADC_RQST_CH4_BY_MD_MASK 0x1
+#define MT6325_AUXADC_RQST_CH4_BY_MD_SHIFT 4
+#define MT6325_AUXADC_RQST_CH7_BY_MD_MASK 0x1
+#define MT6325_AUXADC_RQST_CH7_BY_MD_SHIFT 7
+#define MT6325_AUXADC_RQST_CH7_BY_GPS_MASK 0x1
+#define MT6325_AUXADC_RQST_CH7_BY_GPS_SHIFT 8
+#define MT6325_AUXADC_RQST_RSV1_MASK 0x7F
+#define MT6325_AUXADC_RQST_RSV1_SHIFT 9
+#define MT6325_AUXADC_RQST1_SET_MASK 0xFFFF
+#define MT6325_AUXADC_RQST1_SET_SHIFT 0
+#define MT6325_AUXADC_RQST1_CLR_MASK 0xFFFF
+#define MT6325_AUXADC_RQST1_CLR_SHIFT 0
+#define MT6325_AUXADC_CK_ON_EXTD_MASK 0x3F
+#define MT6325_AUXADC_CK_ON_EXTD_SHIFT 0
+#define MT6325_AUXADC_STRUP_CK_ON_ENB_MASK 0x1
+#define MT6325_AUXADC_STRUP_CK_ON_ENB_SHIFT 10
+#define MT6325_AUXADC_ADC_RDY_WAKEUP_CLR_MASK 0x1
+#define MT6325_AUXADC_ADC_RDY_WAKEUP_CLR_SHIFT 11
+#define MT6325_AUXADC_SRCLKEN_CK_EN_MASK 0x1
+#define MT6325_AUXADC_SRCLKEN_CK_EN_SHIFT 12
+#define MT6325_AUXADC_CK_AON_GPS_MASK 0x1
+#define MT6325_AUXADC_CK_AON_GPS_SHIFT 13
+#define MT6325_AUXADC_CK_AON_MD_MASK 0x1
+#define MT6325_AUXADC_CK_AON_MD_SHIFT 14
+#define MT6325_AUXADC_CK_AON_MASK 0x1
+#define MT6325_AUXADC_CK_AON_SHIFT 15
+#define MT6325_AUXADC_PMU_THR_PDN_SW_MASK 0x1
+#define MT6325_AUXADC_PMU_THR_PDN_SW_SHIFT 0
+#define MT6325_AUXADC_PMU_THR_PDN_SEL_MASK 0x1
+#define MT6325_AUXADC_PMU_THR_PDN_SEL_SHIFT 1
+#define MT6325_AUXADC_PMU_THR_PDN_STATUS_MASK 0x1
+#define MT6325_AUXADC_PMU_THR_PDN_STATUS_SHIFT 2
+#define MT6325_AUXADC_RO_RSV1_MASK 0x7F
+#define MT6325_AUXADC_RO_RSV1_SHIFT 3
+#define MT6325_AUXADC_DIG1_RSV0_MASK 0x3F
+#define MT6325_AUXADC_DIG1_RSV0_SHIFT 10
+#define MT6325_AUXADC_THR_DEBT_MAX_MASK 0xFF
+#define MT6325_AUXADC_THR_DEBT_MAX_SHIFT 0
+#define MT6325_AUXADC_THR_DEBT_MIN_MASK 0xFF
+#define MT6325_AUXADC_THR_DEBT_MIN_SHIFT 8
+#define MT6325_AUXADC_THR_DET_PRD_15_0_MASK 0xFFFF
+#define MT6325_AUXADC_THR_DET_PRD_15_0_SHIFT 0
+#define MT6325_AUXADC_THR_DET_PRD_19_16_MASK 0xF
+#define MT6325_AUXADC_THR_DET_PRD_19_16_SHIFT 0
+#define MT6325_AUXADC_THR_VOLT_MAX_MASK 0xFFF
+#define MT6325_AUXADC_THR_VOLT_MAX_SHIFT 0
+#define MT6325_AUXADC_THR_IRQ_EN_MAX_MASK 0x1
+#define MT6325_AUXADC_THR_IRQ_EN_MAX_SHIFT 12
+#define MT6325_AUXADC_THR_EN_MAX_MASK 0x1
+#define MT6325_AUXADC_THR_EN_MAX_SHIFT 13
+#define MT6325_AUXADC_THR_MAX_IRQ_B_MASK 0x1
+#define MT6325_AUXADC_THR_MAX_IRQ_B_SHIFT 15
+#define MT6325_AUXADC_THR_VOLT_MIN_MASK 0xFFF
+#define MT6325_AUXADC_THR_VOLT_MIN_SHIFT 0
+#define MT6325_AUXADC_THR_IRQ_EN_MIN_MASK 0x1
+#define MT6325_AUXADC_THR_IRQ_EN_MIN_SHIFT 12
+#define MT6325_AUXADC_THR_EN_MIN_MASK 0x1
+#define MT6325_AUXADC_THR_EN_MIN_SHIFT 13
+#define MT6325_AUXADC_THR_MIN_IRQ_B_MASK 0x1
+#define MT6325_AUXADC_THR_MIN_IRQ_B_SHIFT 15
+#define MT6325_AUXADC_THR_DEBOUNCE_COUNT_MAX_MASK 0x1FF
+#define MT6325_AUXADC_THR_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define MT6325_AUXADC_THR_DEBOUNCE_COUNT_MIN_MASK 0x1FF
+#define MT6325_AUXADC_THR_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define MT6325_RG_AUXADC_FGADC_START_SW_MASK 0x1
+#define MT6325_RG_AUXADC_FGADC_START_SW_SHIFT 0
+#define MT6325_RG_AUXADC_FGADC_START_SEL_MASK 0x1
+#define MT6325_RG_AUXADC_FGADC_START_SEL_SHIFT 1
+#define MT6325_RG_AUXADC_FGADC_R_SW_MASK 0x1
+#define MT6325_RG_AUXADC_FGADC_R_SW_SHIFT 2
+#define MT6325_RG_AUXADC_FGADC_R_SEL_MASK 0x1
+#define MT6325_RG_AUXADC_FGADC_R_SEL_SHIFT 3
+#define MT6325_AUXADC_DIG0_RSV2_MASK 0x1
+#define MT6325_AUXADC_DIG0_RSV2_SHIFT 4
+#define MT6325_AUXADC_DIG1_RSV2_MASK 0xF
+#define MT6325_AUXADC_DIG1_RSV2_SHIFT 5
+#define MT6325_AUXADC_ACCDET_AUTO_SPL_MASK 0x1
+#define MT6325_AUXADC_ACCDET_AUTO_SPL_SHIFT 9
+#define MT6325_AUXADC_ACCDET_AUTO_RQST_CLR_MASK 0x1
+#define MT6325_AUXADC_ACCDET_AUTO_RQST_CLR_SHIFT 10
+#define MT6325_AUXADC_AUTORPT_PRD_MASK 0x3FF
+#define MT6325_AUXADC_AUTORPT_PRD_SHIFT 0
+#define MT6325_AUXADC_AUTORPT_EN_MASK 0x1
+#define MT6325_AUXADC_AUTORPT_EN_SHIFT 15
+#define MT6325_AUXADC_IMPEDANCE_CNT_MASK 0x3F
+#define MT6325_AUXADC_IMPEDANCE_CNT_SHIFT 0
+#define MT6325_AUXADC_IMPEDANCE_CHSEL_MASK 0x1
+#define MT6325_AUXADC_IMPEDANCE_CHSEL_SHIFT 6
+#define MT6325_AUXADC_IMPEDANCE_IRQ_CLR_MASK 0x1
+#define MT6325_AUXADC_IMPEDANCE_IRQ_CLR_SHIFT 7
+#define MT6325_AUXADC_IMPEDANCE_IRQ_STATUS_MASK 0x1
+#define MT6325_AUXADC_IMPEDANCE_IRQ_STATUS_SHIFT 8
+#define MT6325_AUXADC_CLR_IMP_CNT_STOP_MASK 0x1
+#define MT6325_AUXADC_CLR_IMP_CNT_STOP_SHIFT 14
+#define MT6325_AUXADC_IMPEDANCE_MODE_MASK 0x1
+#define MT6325_AUXADC_IMPEDANCE_MODE_SHIFT 15
+#define MT6325_AUXADC_VISMPS0_DEBT_MAX_MASK 0xFF
+#define MT6325_AUXADC_VISMPS0_DEBT_MAX_SHIFT 0
+#define MT6325_AUXADC_VISMPS0_DEBT_MIN_MASK 0xFF
+#define MT6325_AUXADC_VISMPS0_DEBT_MIN_SHIFT 8
+#define MT6325_AUXADC_VISMPS0_DET_PRD_15_0_MASK 0xFFFF
+#define MT6325_AUXADC_VISMPS0_DET_PRD_15_0_SHIFT 0
+#define MT6325_AUXADC_VISMPS0_DET_PRD_19_16_MASK 0xF
+#define MT6325_AUXADC_VISMPS0_DET_PRD_19_16_SHIFT 0
+#define MT6325_AUXADC_VISMPS0_VOLT_MAX_MASK 0xFFF
+#define MT6325_AUXADC_VISMPS0_VOLT_MAX_SHIFT 0
+#define MT6325_AUXADC_VISMPS0_IRQ_EN_MAX_MASK 0x1
+#define MT6325_AUXADC_VISMPS0_IRQ_EN_MAX_SHIFT 12
+#define MT6325_AUXADC_VISMPS0_EN_MAX_MASK 0x1
+#define MT6325_AUXADC_VISMPS0_EN_MAX_SHIFT 13
+#define MT6325_AUXADC_VISMPS0_MAX_IRQ_B_MASK 0x1
+#define MT6325_AUXADC_VISMPS0_MAX_IRQ_B_SHIFT 15
+#define MT6325_AUXADC_VISMPS0_VOLT_MIN_MASK 0xFFF
+#define MT6325_AUXADC_VISMPS0_VOLT_MIN_SHIFT 0
+#define MT6325_AUXADC_VISMPS0_IRQ_EN_MIN_MASK 0x1
+#define MT6325_AUXADC_VISMPS0_IRQ_EN_MIN_SHIFT 12
+#define MT6325_AUXADC_VISMPS0_EN_MIN_MASK 0x1
+#define MT6325_AUXADC_VISMPS0_EN_MIN_SHIFT 13
+#define MT6325_AUXADC_VISMPS0_MIN_IRQ_B_MASK 0x1
+#define MT6325_AUXADC_VISMPS0_MIN_IRQ_B_SHIFT 15
+#define MT6325_AUXADC_VISMPS0_DEBOUNCE_COUNT_MAX_MASK 0x1FF
+#define MT6325_AUXADC_VISMPS0_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define MT6325_AUXADC_VISMPS0_DEBOUNCE_COUNT_MIN_MASK 0x1FF
+#define MT6325_AUXADC_VISMPS0_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define MT6325_AUXADC_LBAT2_DEBT_MAX_MASK 0xFF
+#define MT6325_AUXADC_LBAT2_DEBT_MAX_SHIFT 0
+#define MT6325_AUXADC_LBAT2_DEBT_MIN_MASK 0xFF
+#define MT6325_AUXADC_LBAT2_DEBT_MIN_SHIFT 8
+#define MT6325_AUXADC_LBAT2_DET_PRD_15_0_MASK 0xFFFF
+#define MT6325_AUXADC_LBAT2_DET_PRD_15_0_SHIFT 0
+#define MT6325_AUXADC_LBAT2_DET_PRD_19_16_MASK 0xF
+#define MT6325_AUXADC_LBAT2_DET_PRD_19_16_SHIFT 0
+#define MT6325_AUXADC_LBAT2_VOLT_MAX_MASK 0xFFF
+#define MT6325_AUXADC_LBAT2_VOLT_MAX_SHIFT 0
+#define MT6325_AUXADC_LBAT2_IRQ_EN_MAX_MASK 0x1
+#define MT6325_AUXADC_LBAT2_IRQ_EN_MAX_SHIFT 12
+#define MT6325_AUXADC_LBAT2_EN_MAX_MASK 0x1
+#define MT6325_AUXADC_LBAT2_EN_MAX_SHIFT 13
+#define MT6325_AUXADC_LBAT2_MAX_IRQ_B_MASK 0x1
+#define MT6325_AUXADC_LBAT2_MAX_IRQ_B_SHIFT 15
+#define MT6325_AUXADC_LBAT2_VOLT_MIN_MASK 0xFFF
+#define MT6325_AUXADC_LBAT2_VOLT_MIN_SHIFT 0
+#define MT6325_AUXADC_LBAT2_IRQ_EN_MIN_MASK 0x1
+#define MT6325_AUXADC_LBAT2_IRQ_EN_MIN_SHIFT 12
+#define MT6325_AUXADC_LBAT2_EN_MIN_MASK 0x1
+#define MT6325_AUXADC_LBAT2_EN_MIN_SHIFT 13
+#define MT6325_AUXADC_LBAT2_MIN_IRQ_B_MASK 0x1
+#define MT6325_AUXADC_LBAT2_MIN_IRQ_B_SHIFT 15
+#define MT6325_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_MASK 0x1FF
+#define MT6325_AUXADC_LBAT2_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define MT6325_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_MASK 0x1FF
+#define MT6325_AUXADC_LBAT2_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define MT6325_RG_ADC_OUT_BATSNS_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_BATSNS_SHIFT 0
+#define MT6325_RG_ADC_RDY_BATSNS_MASK 0x1
+#define MT6325_RG_ADC_RDY_BATSNS_SHIFT 15
+#define MT6325_RG_ADC_OUT_ISENSE_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_ISENSE_SHIFT 0
+#define MT6325_RG_ADC_RDY_ISENSE_MASK 0x1
+#define MT6325_RG_ADC_RDY_ISENSE_SHIFT 15
+#define MT6325_RG_ADC_OUT_VCDT_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_VCDT_SHIFT 0
+#define MT6325_RG_ADC_RDY_VCDT_MASK 0x1
+#define MT6325_RG_ADC_RDY_VCDT_SHIFT 15
+#define MT6325_RG_ADC_OUT_BATON1_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_BATON1_SHIFT 0
+#define MT6325_RG_ADC_RDY_BATON1_MASK 0x1
+#define MT6325_RG_ADC_RDY_BATON1_SHIFT 15
+#define MT6325_RG_ADC_OUT_THR_SENSE1_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_THR_SENSE1_SHIFT 0
+#define MT6325_RG_ADC_RDY_THR_SENSE1_MASK 0x1
+#define MT6325_RG_ADC_RDY_THR_SENSE1_SHIFT 15
+#define MT6325_RG_ADC_OUT_THR_MD_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_THR_MD_SHIFT 0
+#define MT6325_RG_ADC_RDY_THR_MD_MASK 0x1
+#define MT6325_RG_ADC_RDY_THR_MD_SHIFT 15
+#define MT6325_RG_ADC_OUT_BATON2_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_BATON2_SHIFT 0
+#define MT6325_RG_ADC_RDY_BATON2_MASK 0x1
+#define MT6325_RG_ADC_RDY_BATON2_SHIFT 15
+#define MT6325_RG_ADC_OUT_CH5_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_CH5_SHIFT 0
+#define MT6325_RG_ADC_RDY_CH5_MASK 0x1
+#define MT6325_RG_ADC_RDY_CH5_SHIFT 15
+#define MT6325_RG_ADC_OUT_WAKEUP_PCHR_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_WAKEUP_PCHR_SHIFT 0
+#define MT6325_RG_ADC_RDY_WAKEUP_PCHR_MASK 0x1
+#define MT6325_RG_ADC_RDY_WAKEUP_PCHR_SHIFT 15
+#define MT6325_RG_ADC_OUT_WAKEUP_SWCHR_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_WAKEUP_SWCHR_SHIFT 0
+#define MT6325_RG_ADC_RDY_WAKEUP_SWCHR_MASK 0x1
+#define MT6325_RG_ADC_RDY_WAKEUP_SWCHR_SHIFT 15
+#define MT6325_RG_ADC_OUT_LBAT_MASK 0xFFF
+#define MT6325_RG_ADC_OUT_LBAT_SHIFT 0
+#define MT6325_RG_ADC_RDY_LBAT_MASK 0x1
+#define MT6325_RG_ADC_RDY_LBAT_SHIFT 15
+#define MT6325_RG_ADC_OUT_CH6_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_CH6_SHIFT 0
+#define MT6325_RG_ADC_RDY_CH6_MASK 0x1
+#define MT6325_RG_ADC_RDY_CH6_SHIFT 15
+#define MT6325_RG_ADC_RDY_GPS_MASK 0x1
+#define MT6325_RG_ADC_RDY_GPS_SHIFT 15
+#define MT6325_RG_ADC_OUT_GPS_MASK 0xFFFF
+#define MT6325_RG_ADC_OUT_GPS_SHIFT 0
+#define MT6325_RG_ADC_OUT_GPS_LSB_MASK 0x1
+#define MT6325_RG_ADC_OUT_GPS_LSB_SHIFT 15
+#define MT6325_RG_ADC_OUT_MD_MASK 0xFFFF
+#define MT6325_RG_ADC_OUT_MD_SHIFT 0
+#define MT6325_RG_ADC_OUT_MD_LSB_MASK 0x1
+#define MT6325_RG_ADC_OUT_MD_LSB_SHIFT 0
+#define MT6325_RG_ADC_RDY_MD_MASK 0x1
+#define MT6325_RG_ADC_RDY_MD_SHIFT 15
+#define MT6325_RG_ADC_OUT_INT_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_INT_SHIFT 0
+#define MT6325_RG_ADC_RDY_INT_MASK 0x1
+#define MT6325_RG_ADC_RDY_INT_SHIFT 15
+#define MT6325_RG_ADC_OUT_CIC_RAW_16_1_MASK 0xFFFF
+#define MT6325_RG_ADC_OUT_CIC_RAW_16_1_SHIFT 0
+#define MT6325_RG_ADC_OUT_CIC_RAW_0_MASK 0x1
+#define MT6325_RG_ADC_OUT_CIC_RAW_0_SHIFT 0
+#define MT6325_RG_ADC_BUSY_MASK 0x7FFF
+#define MT6325_RG_ADC_BUSY_SHIFT 1
+#define MT6325_RG_ADC_OUT_LBAT2_MASK 0xFFF
+#define MT6325_RG_ADC_OUT_LBAT2_SHIFT 0
+#define MT6325_RG_ADC_RDY_LBAT2_MASK 0x1
+#define MT6325_RG_ADC_RDY_LBAT2_SHIFT 15
+#define MT6325_RG_ADC_OUT_THR_HW_MASK 0xFFF
+#define MT6325_RG_ADC_OUT_THR_HW_SHIFT 0
+#define MT6325_RG_ADC_RDY_THR_HW_MASK 0x1
+#define MT6325_RG_ADC_RDY_THR_HW_SHIFT 15
+#define MT6325_RG_ADC_OUT_CH8_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_CH8_SHIFT 0
+#define MT6325_RG_ADC_RDY_CH8_MASK 0x1
+#define MT6325_RG_ADC_RDY_CH8_SHIFT 15
+#define MT6325_RG_ADC_OUT_CH9_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_CH9_SHIFT 0
+#define MT6325_RG_ADC_RDY_CH9_MASK 0x1
+#define MT6325_RG_ADC_RDY_CH9_SHIFT 15
+#define MT6325_RG_ADC_OUT_CH10_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_CH10_SHIFT 0
+#define MT6325_RG_ADC_RDY_CH10_MASK 0x1
+#define MT6325_RG_ADC_RDY_CH10_SHIFT 15
+#define MT6325_RG_ADC_OUT_CH11_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_CH11_SHIFT 0
+#define MT6325_RG_ADC_RDY_CH11_MASK 0x1
+#define MT6325_RG_ADC_RDY_CH11_SHIFT 15
+#define MT6325_RG_ADC_OUT_VISMPS0_MASK 0xFFF
+#define MT6325_RG_ADC_OUT_VISMPS0_SHIFT 0
+#define MT6325_RG_ADC_RDY_VISMPS0_MASK 0x1
+#define MT6325_RG_ADC_RDY_VISMPS0_SHIFT 15
+#define MT6325_RG_ADC_OUT_FGADC_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_FGADC_SHIFT 0
+#define MT6325_RG_ADC_RDY_FGADC_MASK 0x1
+#define MT6325_RG_ADC_RDY_FGADC_SHIFT 15
+#define MT6325_RG_ADC_OUT_IMP_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_IMP_SHIFT 0
+#define MT6325_RG_ADC_RDY_IMP_MASK 0x1
+#define MT6325_RG_ADC_RDY_IMP_SHIFT 15
+#define MT6325_RG_ADC_OUT_IMP_AVG_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_IMP_AVG_SHIFT 0
+#define MT6325_RG_ADC_RDY_IMP_AVG_MASK 0x1
+#define MT6325_RG_ADC_RDY_IMP_AVG_SHIFT 15
+#define MT6325_RG_ADC_OUT_FGADC2_MASK 0x7FFF
+#define MT6325_RG_ADC_OUT_FGADC2_SHIFT 0
+#define MT6325_RG_ADC_RDY_FGADC2_MASK 0x1
+#define MT6325_RG_ADC_RDY_FGADC2_SHIFT 15
+#define MT6325_RG_SW_GAIN_TRIM_MASK 0xFFFF
+#define MT6325_RG_SW_GAIN_TRIM_SHIFT 0
+#define MT6325_RG_SW_OFFSET_TRIM_MASK 0xFFFF
+#define MT6325_RG_SW_OFFSET_TRIM_SHIFT 0
+#define MT6325_RG_ADC_PWDB_MASK 0x1
+#define MT6325_RG_ADC_PWDB_SHIFT 0
+#define MT6325_RG_ADC_PWDB_SWCTRL_MASK 0x1
+#define MT6325_RG_ADC_PWDB_SWCTRL_SHIFT 2
+#define MT6325_RG_ADC_CALI_RATE_MASK 0x3
+#define MT6325_RG_ADC_CALI_RATE_SHIFT 4
+#define MT6325_RG_ADC_CALI_EN_MASK 0x1
+#define MT6325_RG_ADC_CALI_EN_SHIFT 6
+#define MT6325_RG_ADC_CALI_FORCE_MASK 0x1
+#define MT6325_RG_ADC_CALI_FORCE_SHIFT 7
+#define MT6325_RG_ADC_AUTORST_RANGE_MASK 0x3
+#define MT6325_RG_ADC_AUTORST_RANGE_SHIFT 8
+#define MT6325_RG_ADC_AUTORST_EN_MASK 0x1
+#define MT6325_RG_ADC_AUTORST_EN_SHIFT 10
+#define MT6325_RG_ADC_LATCH_EDGE_MASK 0x1
+#define MT6325_RG_ADC_LATCH_EDGE_SHIFT 11
+#define MT6325_RG_ADC_FILTER_ORDER_MASK 0x1
+#define MT6325_RG_ADC_FILTER_ORDER_SHIFT 12
+#define MT6325_RG_ADC_SWCTRL_EN_MASK 0x1
+#define MT6325_RG_ADC_SWCTRL_EN_SHIFT 0
+#define MT6325_AUXADC_ADCIN_VSEN_EN_MASK 0x1
+#define MT6325_AUXADC_ADCIN_VSEN_EN_SHIFT 1
+#define MT6325_AUXADC_ADCIN_VSEN_MUX_EN_MASK 0x1
+#define MT6325_AUXADC_ADCIN_VSEN_MUX_EN_SHIFT 2
+#define MT6325_AUXADC_ADCIN_VBAT_EN_MASK 0x1
+#define MT6325_AUXADC_ADCIN_VBAT_EN_SHIFT 4
+#define MT6325_AUXADC_ADCIN_CHR_EN_MASK 0x1
+#define MT6325_AUXADC_ADCIN_CHR_EN_SHIFT 5
+#define MT6325_RG_AUXADC_CHSEL_MASK 0xF
+#define MT6325_RG_AUXADC_CHSEL_SHIFT 12
+#define MT6325_RG_LBAT_DEBT_MAX_MASK 0xFF
+#define MT6325_RG_LBAT_DEBT_MAX_SHIFT 0
+#define MT6325_RG_LBAT_DEBT_MIN_MASK 0xFF
+#define MT6325_RG_LBAT_DEBT_MIN_SHIFT 8
+#define MT6325_RG_LBAT_DET_PRD_15_0_MASK 0xFFFF
+#define MT6325_RG_LBAT_DET_PRD_15_0_SHIFT 0
+#define MT6325_RG_LBAT_DET_PRD_19_16_MASK 0xF
+#define MT6325_RG_LBAT_DET_PRD_19_16_SHIFT 0
+#define MT6325_RG_LBAT_VOLT_MAX_MASK 0xFFF
+#define MT6325_RG_LBAT_VOLT_MAX_SHIFT 0
+#define MT6325_RG_LBAT_IRQ_EN_MAX_MASK 0x1
+#define MT6325_RG_LBAT_IRQ_EN_MAX_SHIFT 12
+#define MT6325_RG_LBAT_EN_MAX_MASK 0x1
+#define MT6325_RG_LBAT_EN_MAX_SHIFT 13
+#define MT6325_RG_LBAT_MAX_IRQ_B_MASK 0x1
+#define MT6325_RG_LBAT_MAX_IRQ_B_SHIFT 15
+#define MT6325_RG_LBAT_VOLT_MIN_MASK 0xFFF
+#define MT6325_RG_LBAT_VOLT_MIN_SHIFT 0
+#define MT6325_RG_LBAT_IRQ_EN_MIN_MASK 0x1
+#define MT6325_RG_LBAT_IRQ_EN_MIN_SHIFT 12
+#define MT6325_RG_LBAT_EN_MIN_MASK 0x1
+#define MT6325_RG_LBAT_EN_MIN_SHIFT 13
+#define MT6325_RG_LBAT_MIN_IRQ_B_MASK 0x1
+#define MT6325_RG_LBAT_MIN_IRQ_B_SHIFT 15
+#define MT6325_RG_LBAT_DEBOUNCE_COUNT_MAX_MASK 0x1FF
+#define MT6325_RG_LBAT_DEBOUNCE_COUNT_MAX_SHIFT 0
+#define MT6325_RG_LBAT_DEBOUNCE_COUNT_MIN_MASK 0x1FF
+#define MT6325_RG_LBAT_DEBOUNCE_COUNT_MIN_SHIFT 0
+#define MT6325_RG_DATA_REUSE_SEL_MASK 0x3
+#define MT6325_RG_DATA_REUSE_SEL_SHIFT 3
+#define MT6325_RG_AUXADC_BIST_ENB_MASK 0x1
+#define MT6325_RG_AUXADC_BIST_ENB_SHIFT 5
+#define MT6325_RG_OSR_MASK 0x7
+#define MT6325_RG_OSR_SHIFT 10
+#define MT6325_RG_OSR_GPS_MASK 0x7
+#define MT6325_RG_OSR_GPS_SHIFT 13
+#define MT6325_RG_ADC_TRIM_CH7_SEL_MASK 0x3
+#define MT6325_RG_ADC_TRIM_CH7_SEL_SHIFT 0
+#define MT6325_RG_ADC_TRIM_CH6_SEL_MASK 0x3
+#define MT6325_RG_ADC_TRIM_CH6_SEL_SHIFT 2
+#define MT6325_RG_ADC_TRIM_CH5_SEL_MASK 0x3
+#define MT6325_RG_ADC_TRIM_CH5_SEL_SHIFT 4
+#define MT6325_RG_ADC_TRIM_CH4_SEL_MASK 0x3
+#define MT6325_RG_ADC_TRIM_CH4_SEL_SHIFT 6
+#define MT6325_RG_ADC_TRIM_CH3_SEL_MASK 0x3
+#define MT6325_RG_ADC_TRIM_CH3_SEL_SHIFT 8
+#define MT6325_RG_ADC_TRIM_CH2_SEL_MASK 0x3
+#define MT6325_RG_ADC_TRIM_CH2_SEL_SHIFT 10
+#define MT6325_RG_ADC_TRIM_CH0_SEL_MASK 0x3
+#define MT6325_RG_ADC_TRIM_CH0_SEL_SHIFT 14
+#define MT6325_RG_VBUF_CALEN_MASK 0x1
+#define MT6325_RG_VBUF_CALEN_SHIFT 0
+#define MT6325_RG_VBUF_EXTEN_MASK 0x1
+#define MT6325_RG_VBUF_EXTEN_SHIFT 1
+#define MT6325_RG_VBUF_BYP_MASK 0x1
+#define MT6325_RG_VBUF_BYP_SHIFT 2
+#define MT6325_RG_VBUF_EN_MASK 0x1
+#define MT6325_RG_VBUF_EN_SHIFT 4
+#define MT6325_RG_SOURCE_LBAT_SEL_MASK 0x1
+#define MT6325_RG_SOURCE_LBAT_SEL_SHIFT 15
+#define MT6325_EFUSE_GAIN_CH0_TRIM_MASK 0x1FF
+#define MT6325_EFUSE_GAIN_CH0_TRIM_SHIFT 0
+#define MT6325_EFUSE_OFFSET_CH0_TRIM_MASK 0xFF
+#define MT6325_EFUSE_OFFSET_CH0_TRIM_SHIFT 0
+#define MT6325_EFUSE_GAIN_CH4_TRIM_MASK 0x1FF
+#define MT6325_EFUSE_GAIN_CH4_TRIM_SHIFT 0
+#define MT6325_EFUSE_OFFSET_CH4_TRIM_MASK 0xFF
+#define MT6325_EFUSE_OFFSET_CH4_TRIM_SHIFT 0
+#define MT6325_EFUSE_GAIN_CH7_TRIM_MASK 0xFFFF
+#define MT6325_EFUSE_GAIN_CH7_TRIM_SHIFT 0
+#define MT6325_EFUSE_OFFSET_CH7_TRIM_MASK 0xFFFF
+#define MT6325_EFUSE_OFFSET_CH7_TRIM_SHIFT 0
+#define MT6325_RG_ADC_IBIAS_MASK 0x3
+#define MT6325_RG_ADC_IBIAS_SHIFT 0
+#define MT6325_RG_ADC_RST_MASK 0x1
+#define MT6325_RG_ADC_RST_SHIFT 2
+#define MT6325_RG_ADC_LP_EN_MASK 0x1
+#define MT6325_RG_ADC_LP_EN_SHIFT 3
+#define MT6325_RG_ADC_INPUT_SHORT_MASK 0x1
+#define MT6325_RG_ADC_INPUT_SHORT_SHIFT 4
+#define MT6325_RG_ADC_CHOPPER_EN_MASK 0x1
+#define MT6325_RG_ADC_CHOPPER_EN_SHIFT 5
+#define MT6325_RG_VPWDB_ADC_MASK 0x1
+#define MT6325_RG_VPWDB_ADC_SHIFT 6
+#define MT6325_RG_VREF18_EN_MASK 0x1
+#define MT6325_RG_VREF18_EN_SHIFT 7
+#define MT6325_RG_ADC_CHS_SEL_MASK 0x3
+#define MT6325_RG_ADC_CHS_SEL_SHIFT 8
+#define MT6325_RG_ADC_DVREF_CAL_MASK 0x1
+#define MT6325_RG_ADC_DVREF_CAL_SHIFT 14
+#define MT6325_RG_ADC_DENB_MASK 0x1
+#define MT6325_RG_ADC_DENB_SHIFT 15
+#define MT6325_RG_ADC_SLEEP_MODE_EN_MASK 0x1
+#define MT6325_RG_ADC_SLEEP_MODE_EN_SHIFT 0
+#define MT6325_RG_ADC_GPS_STATUS_MASK 0x1
+#define MT6325_RG_ADC_GPS_STATUS_SHIFT 1
+#define MT6325_RG_ADC_RSV_BIT_MASK 0x1
+#define MT6325_RG_ADC_RSV_BIT_SHIFT 2
+#define MT6325_RG_ADC_TEST_MODE_EN_MASK 0x1
+#define MT6325_RG_ADC_TEST_MODE_EN_SHIFT 3
+#define MT6325_RG_ADC_TEST_OUT_SEL_MASK 0x1
+#define MT6325_RG_ADC_TEST_OUT_SEL_SHIFT 4
+#define MT6325_RG_DECI_BYPASS_EN_MASK 0x1
+#define MT6325_RG_DECI_BYPASS_EN_SHIFT 5
+#define MT6325_RG_ADC_CLK_AON_MASK 0x1
+#define MT6325_RG_ADC_CLK_AON_SHIFT 7
+#define MT6325_RG_ADC_DECI_FORCE_MASK 0x1
+#define MT6325_RG_ADC_DECI_FORCE_SHIFT 12
+#define MT6325_RG_ADC_DECI_GDLY_MASK 0x3
+#define MT6325_RG_ADC_DECI_GDLY_SHIFT 14
+#define MT6325_RG_MD_RQST_MASK 0x1
+#define MT6325_RG_MD_RQST_SHIFT 15
+#define MT6325_RG_GPS_RQST_MASK 0x1
+#define MT6325_RG_GPS_RQST_SHIFT 15
+#define MT6325_RG_AP_RQST_LIST_MASK 0x1FF
+#define MT6325_RG_AP_RQST_LIST_SHIFT 0
+#define MT6325_RG_AP_RQST_MASK 0x1
+#define MT6325_RG_AP_RQST_SHIFT 15
+#define MT6325_RG_AP_RQST_LIST_RSV_MASK 0xFF
+#define MT6325_RG_AP_RQST_LIST_RSV_SHIFT 0
+#define MT6325_RG_ADC_OUT_TRIM_ENB_MASK 0x1
+#define MT6325_RG_ADC_OUT_TRIM_ENB_SHIFT 1
+#define MT6325_RG_ADC_TRIM_COMP_MASK 0x1
+#define MT6325_RG_ADC_TRIM_COMP_SHIFT 2
+#define MT6325_RG_ADC_2S_COMP_ENB_MASK 0x1
+#define MT6325_RG_ADC_2S_COMP_ENB_SHIFT 3
+#define MT6325_RG_CIC_OUT_RAW_MASK 0x1
+#define MT6325_RG_CIC_OUT_RAW_SHIFT 4
+#define MT6325_RG_DATA_SKIP_ENB_MASK 0x1
+#define MT6325_RG_DATA_SKIP_ENB_SHIFT 5
+#define MT6325_RG_DATA_SKIP_NUM_MASK 0x3
+#define MT6325_RG_DATA_SKIP_NUM_SHIFT 6
+#define MT6325_RG_ADC_REV_MASK 0xFF
+#define MT6325_RG_ADC_REV_SHIFT 0
+#define MT6325_RG_DECI_GDLY_SEL_MODE_MASK 0x1
+#define MT6325_RG_DECI_GDLY_SEL_MODE_SHIFT 0
+#define MT6325_RG_DECI_GDLY_VREF18_SELB_MASK 0x1
+#define MT6325_RG_DECI_GDLY_VREF18_SELB_SHIFT 1
+#define MT6325_RG_ADC_RSV1_MASK 0x1FFF
+#define MT6325_RG_ADC_RSV1_SHIFT 2
+#define MT6325_RG_VREF18_ENB_MASK 0x1
+#define MT6325_RG_VREF18_ENB_SHIFT 15
+#define MT6325_RG_ADC_MD_STATUS_MASK 0x1
+#define MT6325_RG_ADC_MD_STATUS_SHIFT 0
+#define MT6325_RG_ADC_RSV2_MASK 0x3FFF
+#define MT6325_RG_ADC_RSV2_SHIFT 1
+#define MT6325_RG_VREF18_ENB_MD_MASK 0x1
+#define MT6325_RG_VREF18_ENB_MD_SHIFT 15
+#define MT6325_RG_AUDACCDETVTHBCAL_MASK 0x1
+#define MT6325_RG_AUDACCDETVTHBCAL_SHIFT 0
+#define MT6325_RG_AUDACCDETVTHACAL_MASK 0x1
+#define MT6325_RG_AUDACCDETVTHACAL_SHIFT 1
+#define MT6325_RG_AUDACCDETANASWCTRLENB_MASK 0x1
+#define MT6325_RG_AUDACCDETANASWCTRLENB_SHIFT 2
+#define MT6325_RG_ACCDETSEL_MASK 0x1
+#define MT6325_RG_ACCDETSEL_SHIFT 3
+#define MT6325_RG_AUDACCDETSWCTRL_MASK 0x7
+#define MT6325_RG_AUDACCDETSWCTRL_SHIFT 4
+#define MT6325_RG_AUDACCDETMICBIAS1PULLLOW_MASK 0x1
+#define MT6325_RG_AUDACCDETMICBIAS1PULLLOW_SHIFT 7
+#define MT6325_RG_AUDACCDETTVDET_MASK 0x1
+#define MT6325_RG_AUDACCDETTVDET_SHIFT 8
+#define MT6325_RG_AUDACCDETVIN1PULLLOW_MASK 0x1
+#define MT6325_RG_AUDACCDETVIN1PULLLOW_SHIFT 9
+#define MT6325_AUDACCDETAUXADCSWCTRL_MASK 0x1
+#define MT6325_AUDACCDETAUXADCSWCTRL_SHIFT 10
+#define MT6325_AUDACCDETAUXADCSWCTRL_SEL_MASK 0x1
+#define MT6325_AUDACCDETAUXADCSWCTRL_SEL_SHIFT 11
+#define MT6325_RG_AUDACCDETMICBIAS0PULLLOW_MASK 0x1
+#define MT6325_RG_AUDACCDETMICBIAS0PULLLOW_SHIFT 12
+#define MT6325_RG_AUDACCDETRSV_MASK 0x3
+#define MT6325_RG_AUDACCDETRSV_SHIFT 13
+#define MT6325_ACCDET_EN_MASK 0x1
+#define MT6325_ACCDET_EN_SHIFT 0
+#define MT6325_ACCDET_SEQ_INIT_MASK 0x1
+#define MT6325_ACCDET_SEQ_INIT_SHIFT 1
+#define MT6325_ACCDET_EINTDET_EN_MASK 0x1
+#define MT6325_ACCDET_EINTDET_EN_SHIFT 2
+#define MT6325_ACCDET_EINT_SEQ_INIT_MASK 0x1
+#define MT6325_ACCDET_EINT_SEQ_INIT_SHIFT 3
+#define MT6325_ACCDET_NEGVDET_EN_MASK 0x1
+#define MT6325_ACCDET_NEGVDET_EN_SHIFT 4
+#define MT6325_ACCDET_NEGVDET_EN_CTRL_MASK 0x1
+#define MT6325_ACCDET_NEGVDET_EN_CTRL_SHIFT 5
+#define MT6325_ACCDET_CMP_PWM_EN_MASK 0x1
+#define MT6325_ACCDET_CMP_PWM_EN_SHIFT 0
+#define MT6325_ACCDET_VTH_PWM_EN_MASK 0x1
+#define MT6325_ACCDET_VTH_PWM_EN_SHIFT 1
+#define MT6325_ACCDET_MBIAS_PWM_EN_MASK 0x1
+#define MT6325_ACCDET_MBIAS_PWM_EN_SHIFT 2
+#define MT6325_ACCDET_EINT_PWM_EN_MASK 0x1
+#define MT6325_ACCDET_EINT_PWM_EN_SHIFT 3
+#define MT6325_ACCDET_CMP_PWM_IDLE_MASK 0x1
+#define MT6325_ACCDET_CMP_PWM_IDLE_SHIFT 4
+#define MT6325_ACCDET_VTH_PWM_IDLE_MASK 0x1
+#define MT6325_ACCDET_VTH_PWM_IDLE_SHIFT 5
+#define MT6325_ACCDET_MBIAS_PWM_IDLE_MASK 0x1
+#define MT6325_ACCDET_MBIAS_PWM_IDLE_SHIFT 6
+#define MT6325_ACCDET_EINT_PWM_IDLE_MASK 0x1
+#define MT6325_ACCDET_EINT_PWM_IDLE_SHIFT 7
+#define MT6325_ACCDET_PWM_WIDTH_MASK 0xFFFF
+#define MT6325_ACCDET_PWM_WIDTH_SHIFT 0
+#define MT6325_ACCDET_PWM_THRESH_MASK 0xFFFF
+#define MT6325_ACCDET_PWM_THRESH_SHIFT 0
+#define MT6325_ACCDET_RISE_DELAY_MASK 0x7FFF
+#define MT6325_ACCDET_RISE_DELAY_SHIFT 0
+#define MT6325_ACCDET_FALL_DELAY_MASK 0x1
+#define MT6325_ACCDET_FALL_DELAY_SHIFT 15
+#define MT6325_ACCDET_DEBOUNCE0_MASK 0xFFFF
+#define MT6325_ACCDET_DEBOUNCE0_SHIFT 0
+#define MT6325_ACCDET_DEBOUNCE1_MASK 0xFFFF
+#define MT6325_ACCDET_DEBOUNCE1_SHIFT 0
+#define MT6325_ACCDET_DEBOUNCE2_MASK 0xFFFF
+#define MT6325_ACCDET_DEBOUNCE2_SHIFT 0
+#define MT6325_ACCDET_DEBOUNCE3_MASK 0xFFFF
+#define MT6325_ACCDET_DEBOUNCE3_SHIFT 0
+#define MT6325_ACCDET_DEBOUNCE4_MASK 0xFFFF
+#define MT6325_ACCDET_DEBOUNCE4_SHIFT 0
+#define MT6325_ACCDET_IVAL_CUR_IN_MASK 0x3
+#define MT6325_ACCDET_IVAL_CUR_IN_SHIFT 0
+#define MT6325_ACCDET_EINT_IVAL_CUR_IN_MASK 0x1
+#define MT6325_ACCDET_EINT_IVAL_CUR_IN_SHIFT 2
+#define MT6325_ACCDET_IVAL_SAM_IN_MASK 0x3
+#define MT6325_ACCDET_IVAL_SAM_IN_SHIFT 4
+#define MT6325_ACCDET_EINT_IVAL_SAM_IN_MASK 0x1
+#define MT6325_ACCDET_EINT_IVAL_SAM_IN_SHIFT 6
+#define MT6325_ACCDET_IVAL_MEM_IN_MASK 0x3
+#define MT6325_ACCDET_IVAL_MEM_IN_SHIFT 8
+#define MT6325_ACCDET_EINT_IVAL_MEM_IN_MASK 0x1
+#define MT6325_ACCDET_EINT_IVAL_MEM_IN_SHIFT 10
+#define MT6325_ACCDET_EINT_IVAL_SEL_MASK 0x1
+#define MT6325_ACCDET_EINT_IVAL_SEL_SHIFT 14
+#define MT6325_ACCDET_IVAL_SEL_MASK 0x1
+#define MT6325_ACCDET_IVAL_SEL_SHIFT 15
+#define MT6325_ACCDET_IRQ_MASK 0x1
+#define MT6325_ACCDET_IRQ_SHIFT 0
+#define MT6325_ACCDET_NEGV_IRQ_MASK 0x1
+#define MT6325_ACCDET_NEGV_IRQ_SHIFT 1
+#define MT6325_ACCDET_EINT_IRQ_MASK 0x1
+#define MT6325_ACCDET_EINT_IRQ_SHIFT 2
+#define MT6325_ACCDET_IRQ_CLR_MASK 0x1
+#define MT6325_ACCDET_IRQ_CLR_SHIFT 8
+#define MT6325_ACCDET_NEGV_IRQ_CLR_MASK 0x1
+#define MT6325_ACCDET_NEGV_IRQ_CLR_SHIFT 9
+#define MT6325_ACCDET_EINT_IRQ_CLR_MASK 0x1
+#define MT6325_ACCDET_EINT_IRQ_CLR_SHIFT 10
+#define MT6325_ACCDET_EINT_IRQ_POLARITY_MASK 0x1
+#define MT6325_ACCDET_EINT_IRQ_POLARITY_SHIFT 15
+#define MT6325_ACCDET_TEST_MODE0_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE0_SHIFT 0
+#define MT6325_ACCDET_TEST_MODE1_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE1_SHIFT 1
+#define MT6325_ACCDET_TEST_MODE2_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE2_SHIFT 2
+#define MT6325_ACCDET_TEST_MODE3_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE3_SHIFT 3
+#define MT6325_ACCDET_TEST_MODE4_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE4_SHIFT 4
+#define MT6325_ACCDET_TEST_MODE5_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE5_SHIFT 5
+#define MT6325_ACCDET_PWM_SEL_MASK 0x3
+#define MT6325_ACCDET_PWM_SEL_SHIFT 6
+#define MT6325_ACCDET_IN_SW_MASK 0x3
+#define MT6325_ACCDET_IN_SW_SHIFT 8
+#define MT6325_ACCDET_CMP_EN_SW_MASK 0x1
+#define MT6325_ACCDET_CMP_EN_SW_SHIFT 12
+#define MT6325_ACCDET_VTH_EN_SW_MASK 0x1
+#define MT6325_ACCDET_VTH_EN_SW_SHIFT 13
+#define MT6325_ACCDET_MBIAS_EN_SW_MASK 0x1
+#define MT6325_ACCDET_MBIAS_EN_SW_SHIFT 14
+#define MT6325_ACCDET_PWM_EN_SW_MASK 0x1
+#define MT6325_ACCDET_PWM_EN_SW_SHIFT 15
+#define MT6325_ACCDET_IN_MASK 0x3
+#define MT6325_ACCDET_IN_SHIFT 0
+#define MT6325_ACCDET_CUR_IN_MASK 0x3
+#define MT6325_ACCDET_CUR_IN_SHIFT 2
+#define MT6325_ACCDET_SAM_IN_MASK 0x3
+#define MT6325_ACCDET_SAM_IN_SHIFT 4
+#define MT6325_ACCDET_MEM_IN_MASK 0x3
+#define MT6325_ACCDET_MEM_IN_SHIFT 6
+#define MT6325_ACCDET_STATE_MASK 0x7
+#define MT6325_ACCDET_STATE_SHIFT 8
+#define MT6325_ACCDET_MBIAS_CLK_MASK 0x1
+#define MT6325_ACCDET_MBIAS_CLK_SHIFT 12
+#define MT6325_ACCDET_VTH_CLK_MASK 0x1
+#define MT6325_ACCDET_VTH_CLK_SHIFT 13
+#define MT6325_ACCDET_CMP_CLK_MASK 0x1
+#define MT6325_ACCDET_CMP_CLK_SHIFT 14
+#define MT6325_DA_AUDACCDETAUXADCSWCTRL_MASK 0x1
+#define MT6325_DA_AUDACCDETAUXADCSWCTRL_SHIFT 15
+#define MT6325_ACCDET_EINT_DEB_SEL_MASK 0x1
+#define MT6325_ACCDET_EINT_DEB_SEL_SHIFT 0
+#define MT6325_ACCDET_EINT_DEBOUNCE_MASK 0x7
+#define MT6325_ACCDET_EINT_DEBOUNCE_SHIFT 4
+#define MT6325_ACCDET_EINT_PWM_THRESH_MASK 0x7
+#define MT6325_ACCDET_EINT_PWM_THRESH_SHIFT 8
+#define MT6325_ACCDET_EINT_PWM_WIDTH_MASK 0x3
+#define MT6325_ACCDET_EINT_PWM_WIDTH_SHIFT 12
+#define MT6325_ACCDET_NEGV_THRESH_MASK 0x1F
+#define MT6325_ACCDET_NEGV_THRESH_SHIFT 0
+#define MT6325_ACCDET_EINT_PWM_FALL_DELAY_MASK 0x1
+#define MT6325_ACCDET_EINT_PWM_FALL_DELAY_SHIFT 5
+#define MT6325_ACCDET_EINT_PWM_RISE_DELAY_MASK 0x3FF
+#define MT6325_ACCDET_EINT_PWM_RISE_DELAY_SHIFT 6
+#define MT6325_ACCDET_TEST_MODE13_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE13_SHIFT 1
+#define MT6325_ACCDET_TEST_MODE12_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE12_SHIFT 2
+#define MT6325_ACCDET_NVDETECTOUT_SW_MASK 0x1
+#define MT6325_ACCDET_NVDETECTOUT_SW_SHIFT 3
+#define MT6325_ACCDET_TEST_MODE11_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE11_SHIFT 5
+#define MT6325_ACCDET_TEST_MODE10_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE10_SHIFT 6
+#define MT6325_ACCDET_EINTCMPOUT_SW_MASK 0x1
+#define MT6325_ACCDET_EINTCMPOUT_SW_SHIFT 7
+#define MT6325_ACCDET_TEST_MODE9_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE9_SHIFT 9
+#define MT6325_ACCDET_TEST_MODE8_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE8_SHIFT 10
+#define MT6325_ACCDET_AUXADC_CTRL_SW_MASK 0x1
+#define MT6325_ACCDET_AUXADC_CTRL_SW_SHIFT 11
+#define MT6325_ACCDET_TEST_MODE7_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE7_SHIFT 13
+#define MT6325_ACCDET_TEST_MODE6_MASK 0x1
+#define MT6325_ACCDET_TEST_MODE6_SHIFT 14
+#define MT6325_ACCDET_EINTCMP_EN_SW_MASK 0x1
+#define MT6325_ACCDET_EINTCMP_EN_SW_SHIFT 15
+#define MT6325_RG_NVCMPSWEN_MASK 0x1
+#define MT6325_RG_NVCMPSWEN_SHIFT 8
+#define MT6325_RG_NVMODSEL_MASK 0x1
+#define MT6325_RG_NVMODSEL_SHIFT 9
+#define MT6325_RG_SWBUFSWEN_MASK 0x1
+#define MT6325_RG_SWBUFSWEN_SHIFT 10
+#define MT6325_RG_SWBUFMODSEL_MASK 0x1
+#define MT6325_RG_SWBUFMODSEL_SHIFT 11
+#define MT6325_RG_NVDETVTH_MASK 0x1
+#define MT6325_RG_NVDETVTH_SHIFT 12
+#define MT6325_RG_NVDETCMPEN_MASK 0x1
+#define MT6325_RG_NVDETCMPEN_SHIFT 13
+#define MT6325_RG_EINTCONFIGACCDET_MASK 0x1
+#define MT6325_RG_EINTCONFIGACCDET_SHIFT 14
+#define MT6325_RG_EINTCOMPVTH_MASK 0x1
+#define MT6325_RG_EINTCOMPVTH_SHIFT 15
+#define MT6325_ACCDET_EINT_STATE_MASK 0x7
+#define MT6325_ACCDET_EINT_STATE_SHIFT 0
+#define MT6325_ACCDET_EINT_CUR_IN_MASK 0x1
+#define MT6325_ACCDET_EINT_CUR_IN_SHIFT 8
+#define MT6325_ACCDET_EINT_SAM_IN_MASK 0x1
+#define MT6325_ACCDET_EINT_SAM_IN_SHIFT 9
+#define MT6325_ACCDET_EINT_MEM_IN_MASK 0x1
+#define MT6325_ACCDET_EINT_MEM_IN_SHIFT 10
+#define MT6325_NVDETECTOUT_MASK 0x1
+#define MT6325_NVDETECTOUT_SHIFT 13
+#define MT6325_EINTCMPOUT_MASK 0x1
+#define MT6325_EINTCMPOUT_SHIFT 14
+#define MT6325_NI_EINTCMPEN_MASK 0x1
+#define MT6325_NI_EINTCMPEN_SHIFT 15
+#define MT6325_ACCDET_NEGV_COUNT_IN_MASK 0x3F
+#define MT6325_ACCDET_NEGV_COUNT_IN_SHIFT 0
+#define MT6325_ACCDET_NEGV_EN_FINAL_MASK 0x1
+#define MT6325_ACCDET_NEGV_EN_FINAL_SHIFT 6
+#define MT6325_ACCDET_NEGV_COUNT_END_MASK 0x1
+#define MT6325_ACCDET_NEGV_COUNT_END_SHIFT 12
+#define MT6325_ACCDET_NEGV_MINU_MASK 0x1
+#define MT6325_ACCDET_NEGV_MINU_SHIFT 13
+#define MT6325_ACCDET_NEGV_ADD_MASK 0x1
+#define MT6325_ACCDET_NEGV_ADD_SHIFT 14
+#define MT6325_ACCDET_NEGV_CMP_MASK 0x1
+#define MT6325_ACCDET_NEGV_CMP_SHIFT 15
+#define MT6325_ACCDET_CUR_DEB_MASK 0xFFFF
+#define MT6325_ACCDET_CUR_DEB_SHIFT 0
+#define MT6325_ACCDET_EINT_CUR_DEB_MASK 0x7FFF
+#define MT6325_ACCDET_EINT_CUR_DEB_SHIFT 0
+#define MT6325_ACCDET_RSV_CON0_MASK 0xFFFF
+#define MT6325_ACCDET_RSV_CON0_SHIFT 0
+#define MT6325_ACCDET_RSV_CON1_MASK 0xFFFF
+#define MT6325_ACCDET_RSV_CON1_SHIFT 0
+#define MT6325_RG_VCDT_HV_EN_MASK 0x1
+#define MT6325_RG_VCDT_HV_EN_SHIFT 0
+#define MT6325_RGS_CHR_LDO_DET_MASK 0x1
+#define MT6325_RGS_CHR_LDO_DET_SHIFT 1
+#define MT6325_RG_PCHR_AUTOMODE_MASK 0x1
+#define MT6325_RG_PCHR_AUTOMODE_SHIFT 2
+#define MT6325_RG_CSDAC_EN_MASK 0x1
+#define MT6325_RG_CSDAC_EN_SHIFT 3
+#define MT6325_RG_CHR_EN_MASK 0x1
+#define MT6325_RG_CHR_EN_SHIFT 4
+#define MT6325_RGS_CHRDET_MASK 0x1
+#define MT6325_RGS_CHRDET_SHIFT 5
+#define MT6325_RGS_VCDT_LV_DET_MASK 0x1
+#define MT6325_RGS_VCDT_LV_DET_SHIFT 6
+#define MT6325_RGS_VCDT_HV_DET_MASK 0x1
+#define MT6325_RGS_VCDT_HV_DET_SHIFT 7
+#define MT6325_RG_VCDT_LV_VTH_MASK 0xF
+#define MT6325_RG_VCDT_LV_VTH_SHIFT 0
+#define MT6325_RG_VCDT_HV_VTH_MASK 0xF
+#define MT6325_RG_VCDT_HV_VTH_SHIFT 4
+#define MT6325_RG_VBAT_CV_EN_MASK 0x1
+#define MT6325_RG_VBAT_CV_EN_SHIFT 1
+#define MT6325_RG_VBAT_CC_EN_MASK 0x1
+#define MT6325_RG_VBAT_CC_EN_SHIFT 2
+#define MT6325_RG_CS_EN_MASK 0x1
+#define MT6325_RG_CS_EN_SHIFT 3
+#define MT6325_RGS_CS_DET_MASK 0x1
+#define MT6325_RGS_CS_DET_SHIFT 5
+#define MT6325_RGS_VBAT_CV_DET_MASK 0x1
+#define MT6325_RGS_VBAT_CV_DET_SHIFT 6
+#define MT6325_RGS_VBAT_CC_DET_MASK 0x1
+#define MT6325_RGS_VBAT_CC_DET_SHIFT 7
+#define MT6325_RG_VBAT_CV_VTH_MASK 0x3F
+#define MT6325_RG_VBAT_CV_VTH_SHIFT 0
+#define MT6325_RG_VBAT_CC_VTH_MASK 0x3
+#define MT6325_RG_VBAT_CC_VTH_SHIFT 6
+#define MT6325_RG_CS_VTH_MASK 0xF
+#define MT6325_RG_CS_VTH_SHIFT 0
+#define MT6325_RG_PCHR_TOHTC_MASK 0x7
+#define MT6325_RG_PCHR_TOHTC_SHIFT 0
+#define MT6325_RG_PCHR_TOLTC_MASK 0x7
+#define MT6325_RG_PCHR_TOLTC_SHIFT 4
+#define MT6325_RG_VBAT_OV_EN_MASK 0x1
+#define MT6325_RG_VBAT_OV_EN_SHIFT 0
+#define MT6325_RG_VBAT_OV_VTH_MASK 0xF
+#define MT6325_RG_VBAT_OV_VTH_SHIFT 1
+#define MT6325_RG_VBAT_OV_DEG_MASK 0x1
+#define MT6325_RG_VBAT_OV_DEG_SHIFT 5
+#define MT6325_RGS_VBAT_OV_DET_MASK 0x1
+#define MT6325_RGS_VBAT_OV_DET_SHIFT 6
+#define MT6325_RG_BATON_EN_MASK 0x1
+#define MT6325_RG_BATON_EN_SHIFT 0
+#define MT6325_RG_BATON_HT_EN_RSV0_MASK 0x1
+#define MT6325_RG_BATON_HT_EN_RSV0_SHIFT 1
+#define MT6325_BATON_TDET_EN_MASK 0x1
+#define MT6325_BATON_TDET_EN_SHIFT 2
+#define MT6325_RG_BATON_HT_TRIM_MASK 0x7
+#define MT6325_RG_BATON_HT_TRIM_SHIFT 4
+#define MT6325_RG_BATON_HT_TRIM_SET_MASK 0x1
+#define MT6325_RG_BATON_HT_TRIM_SET_SHIFT 7
+#define MT6325_RGS_BATON_UNDET_MASK 0x1
+#define MT6325_RGS_BATON_UNDET_SHIFT 12
+#define MT6325_RG_CSDAC_DATA_MASK 0x3FF
+#define MT6325_RG_CSDAC_DATA_SHIFT 0
+#define MT6325_RG_FRC_CSVTH_USBDL_MASK 0x1
+#define MT6325_RG_FRC_CSVTH_USBDL_SHIFT 0
+#define MT6325_RGS_PCHR_FLAG_OUT_MASK 0xF
+#define MT6325_RGS_PCHR_FLAG_OUT_SHIFT 0
+#define MT6325_RG_PCHR_FLAG_EN_MASK 0x1
+#define MT6325_RG_PCHR_FLAG_EN_SHIFT 4
+#define MT6325_RG_OTG_BVALID_EN_MASK 0x1
+#define MT6325_RG_OTG_BVALID_EN_SHIFT 5
+#define MT6325_RGS_OTG_BVALID_DET_MASK 0x1
+#define MT6325_RGS_OTG_BVALID_DET_SHIFT 6
+#define MT6325_RG_PCHR_FLAG_SEL_MASK 0x3F
+#define MT6325_RG_PCHR_FLAG_SEL_SHIFT 0
+#define MT6325_RG_PCHR_TESTMODE_MASK 0x1
+#define MT6325_RG_PCHR_TESTMODE_SHIFT 0
+#define MT6325_RG_CSDAC_TESTMODE_MASK 0x1
+#define MT6325_RG_CSDAC_TESTMODE_SHIFT 1
+#define MT6325_RG_PCHR_RST_MASK 0x1
+#define MT6325_RG_PCHR_RST_SHIFT 2
+#define MT6325_RG_PCHR_FT_CTRL_MASK 0x7
+#define MT6325_RG_PCHR_FT_CTRL_SHIFT 4
+#define MT6325_RG_CHRWDT_TD_MASK 0xF
+#define MT6325_RG_CHRWDT_TD_SHIFT 0
+#define MT6325_RG_CHRWDT_EN_MASK 0x1
+#define MT6325_RG_CHRWDT_EN_SHIFT 4
+#define MT6325_RG_CHRWDT_WR_MASK 0x1
+#define MT6325_RG_CHRWDT_WR_SHIFT 8
+#define MT6325_RG_PCHR_RV_MASK 0xFF
+#define MT6325_RG_PCHR_RV_SHIFT 0
+#define MT6325_RG_CHRWDT_INT_EN_MASK 0x1
+#define MT6325_RG_CHRWDT_INT_EN_SHIFT 0
+#define MT6325_RG_CHRWDT_FLAG_WR_MASK 0x1
+#define MT6325_RG_CHRWDT_FLAG_WR_SHIFT 1
+#define MT6325_RGS_CHRWDT_OUT_MASK 0x1
+#define MT6325_RGS_CHRWDT_OUT_SHIFT 2
+#define MT6325_RG_USBDL_RST_MASK 0x1
+#define MT6325_RG_USBDL_RST_SHIFT 2
+#define MT6325_RG_USBDL_SET_MASK 0x1
+#define MT6325_RG_USBDL_SET_SHIFT 3
+#define MT6325_RG_ADCIN_VSEN_MUX_EN_MASK 0x1
+#define MT6325_RG_ADCIN_VSEN_MUX_EN_SHIFT 8
+#define MT6325_RG_ADCIN_VSEN_EXT_BATON_EN_MASK 0x1
+#define MT6325_RG_ADCIN_VSEN_EXT_BATON_EN_SHIFT 9
+#define MT6325_RG_ADCIN_VBAT_EN_MASK 0x1
+#define MT6325_RG_ADCIN_VBAT_EN_SHIFT 10
+#define MT6325_RG_ADCIN_VSEN_EN_MASK 0x1
+#define MT6325_RG_ADCIN_VSEN_EN_SHIFT 11
+#define MT6325_RG_ADCIN_CHR_EN_MASK 0x1
+#define MT6325_RG_ADCIN_CHR_EN_SHIFT 12
+#define MT6325_RG_UVLO_VTHL_MASK 0x1F
+#define MT6325_RG_UVLO_VTHL_SHIFT 0
+#define MT6325_RG_UVLO_VH_LAT_MASK 0x1
+#define MT6325_RG_UVLO_VH_LAT_SHIFT 7
+#define MT6325_RG_LBAT_INT_VTH_MASK 0x1F
+#define MT6325_RG_LBAT_INT_VTH_SHIFT 0
+#define MT6325_RG_BGR_RSEL_MASK 0x7
+#define MT6325_RG_BGR_RSEL_SHIFT 0
+#define MT6325_RG_BGR_UNCHOP_PH_MASK 0x1
+#define MT6325_RG_BGR_UNCHOP_PH_SHIFT 4
+#define MT6325_RG_BGR_UNCHOP_MASK 0x1
+#define MT6325_RG_BGR_UNCHOP_SHIFT 5
+#define MT6325_RG_BC11_BB_CTRL_MASK 0x1
+#define MT6325_RG_BC11_BB_CTRL_SHIFT 0
+#define MT6325_RG_BC11_RST_MASK 0x1
+#define MT6325_RG_BC11_RST_SHIFT 1
+#define MT6325_RG_BC11_VSRC_EN_MASK 0x3
+#define MT6325_RG_BC11_VSRC_EN_SHIFT 2
+#define MT6325_RG_BC11_ACA_EN_MASK 0x1
+#define MT6325_RG_BC11_ACA_EN_SHIFT 4
+#define MT6325_RGS_BC11_CMP_OUT_MASK 0x1
+#define MT6325_RGS_BC11_CMP_OUT_SHIFT 7
+#define MT6325_RG_BC11_VREF_VTH_MASK 0x3
+#define MT6325_RG_BC11_VREF_VTH_SHIFT 0
+#define MT6325_RG_BC11_CMP_EN_MASK 0x3
+#define MT6325_RG_BC11_CMP_EN_SHIFT 2
+#define MT6325_RG_BC11_IPD_EN_MASK 0x3
+#define MT6325_RG_BC11_IPD_EN_SHIFT 4
+#define MT6325_RG_BC11_IPU_EN_MASK 0x3
+#define MT6325_RG_BC11_IPU_EN_SHIFT 6
+#define MT6325_RG_BC11_BIAS_EN_MASK 0x1
+#define MT6325_RG_BC11_BIAS_EN_SHIFT 8
+#define MT6325_RG_CSDAC_STP_INC_MASK 0x7
+#define MT6325_RG_CSDAC_STP_INC_SHIFT 0
+#define MT6325_RG_CSDAC_STP_DEC_MASK 0x7
+#define MT6325_RG_CSDAC_STP_DEC_SHIFT 4
+#define MT6325_RG_CSDAC_DLY_MASK 0x7
+#define MT6325_RG_CSDAC_DLY_SHIFT 0
+#define MT6325_RG_CSDAC_STP_MASK 0x7
+#define MT6325_RG_CSDAC_STP_SHIFT 4
+#define MT6325_RG_LOW_ICH_DB_MASK 0x3F
+#define MT6325_RG_LOW_ICH_DB_SHIFT 0
+#define MT6325_RG_CHRIND_ON_MASK 0x1
+#define MT6325_RG_CHRIND_ON_SHIFT 6
+#define MT6325_RG_CHRIND_DIMMING_MASK 0x1
+#define MT6325_RG_CHRIND_DIMMING_SHIFT 7
+#define MT6325_RG_CV_MODE_MASK 0x1
+#define MT6325_RG_CV_MODE_SHIFT 0
+#define MT6325_RG_VCDT_MODE_MASK 0x1
+#define MT6325_RG_VCDT_MODE_SHIFT 1
+#define MT6325_RG_CSDAC_MODE_MASK 0x1
+#define MT6325_RG_CSDAC_MODE_SHIFT 2
+#define MT6325_RG_TRACKING_EN_MASK 0x1
+#define MT6325_RG_TRACKING_EN_SHIFT 4
+#define MT6325_RG_HWCV_EN_MASK 0x1
+#define MT6325_RG_HWCV_EN_SHIFT 6
+#define MT6325_RG_ULC_DET_EN_MASK 0x1
+#define MT6325_RG_ULC_DET_EN_SHIFT 7
+#define MT6325_RG_BGR_TRIM_EN_MASK 0x1
+#define MT6325_RG_BGR_TRIM_EN_SHIFT 0
+#define MT6325_RG_ICHRG_TRIM_MASK 0xF
+#define MT6325_RG_ICHRG_TRIM_SHIFT 4
+#define MT6325_RG_BGR_TRIM_MASK 0x1F
+#define MT6325_RG_BGR_TRIM_SHIFT 0
+#define MT6325_RG_OVP_TRIM_MASK 0xF
+#define MT6325_RG_OVP_TRIM_SHIFT 0
+#define MT6325_RG_CHR_OSC_TRIM_MASK 0x1F
+#define MT6325_RG_CHR_OSC_TRIM_SHIFT 0
+#define MT6325_QI_BGR_EXT_BUF_EN_MASK 0x1
+#define MT6325_QI_BGR_EXT_BUF_EN_SHIFT 5
+#define MT6325_RG_BGR_TEST_EN_MASK 0x1
+#define MT6325_RG_BGR_TEST_EN_SHIFT 6
+#define MT6325_RG_BGR_TEST_RSTB_MASK 0x1
+#define MT6325_RG_BGR_TEST_RSTB_SHIFT 7
+#define MT6325_RG_DAC_USBDL_MAX_MASK 0x3FF
+#define MT6325_RG_DAC_USBDL_MAX_SHIFT 0
+#define MT6325_RG_CM_VDEC_TRIG_MASK 0x1
+#define MT6325_RG_CM_VDEC_TRIG_SHIFT 0
+#define MT6325_PCHR_CM_VDEC_STATUS_MASK 0x3
+#define MT6325_PCHR_CM_VDEC_STATUS_SHIFT 4
+#define MT6325_RG_CM_VINC_TRIG_MASK 0x1
+#define MT6325_RG_CM_VINC_TRIG_SHIFT 0
+#define MT6325_PCHR_CM_VINC_STATUS_MASK 0x3
+#define MT6325_PCHR_CM_VINC_STATUS_SHIFT 4
+#define MT6325_RG_CM_VDEC_HPRD1_MASK 0x3F
+#define MT6325_RG_CM_VDEC_HPRD1_SHIFT 0
+#define MT6325_RG_CM_VDEC_HPRD2_MASK 0x3F
+#define MT6325_RG_CM_VDEC_HPRD2_SHIFT 8
+#define MT6325_RG_CM_VDEC_HPRD3_MASK 0x3F
+#define MT6325_RG_CM_VDEC_HPRD3_SHIFT 0
+#define MT6325_RG_CM_VDEC_HPRD4_MASK 0x3F
+#define MT6325_RG_CM_VDEC_HPRD4_SHIFT 8
+#define MT6325_RG_CM_VDEC_HPRD5_MASK 0x3F
+#define MT6325_RG_CM_VDEC_HPRD5_SHIFT 0
+#define MT6325_RG_CM_VDEC_HPRD6_MASK 0x3F
+#define MT6325_RG_CM_VDEC_HPRD6_SHIFT 8
+#define MT6325_RG_CM_VINC_HPRD1_MASK 0x3F
+#define MT6325_RG_CM_VINC_HPRD1_SHIFT 0
+#define MT6325_RG_CM_VINC_HPRD2_MASK 0x3F
+#define MT6325_RG_CM_VINC_HPRD2_SHIFT 8
+#define MT6325_RG_CM_VINC_HPRD3_MASK 0x3F
+#define MT6325_RG_CM_VINC_HPRD3_SHIFT 0
+#define MT6325_RG_CM_VINC_HPRD4_MASK 0x3F
+#define MT6325_RG_CM_VINC_HPRD4_SHIFT 8
+#define MT6325_RG_CM_VINC_HPRD5_MASK 0x3F
+#define MT6325_RG_CM_VINC_HPRD5_SHIFT 0
+#define MT6325_RG_CM_VINC_HPRD6_MASK 0x3F
+#define MT6325_RG_CM_VINC_HPRD6_SHIFT 8
+#define MT6325_RG_CM_LPRD_MASK 0x3F
+#define MT6325_RG_CM_LPRD_SHIFT 0
+#define MT6325_RG_CM_CS_VTHL_MASK 0xF
+#define MT6325_RG_CM_CS_VTHL_SHIFT 0
+#define MT6325_RG_CM_CS_VTHH_MASK 0xF
+#define MT6325_RG_CM_CS_VTHH_SHIFT 4
+#define MT6325_RG_PCHR_RSV_MASK 0xFF
+#define MT6325_RG_PCHR_RSV_SHIFT 0
+#define MT6325_EOSC_CALI_START_MASK 0x1
+#define MT6325_EOSC_CALI_START_SHIFT 0
+#define MT6325_EOSC_CALI_START_SET_MASK 0x1
+#define MT6325_EOSC_CALI_START_SET_SHIFT 1
+#define MT6325_EOSC_CALI_TD_MASK 0x7
+#define MT6325_EOSC_CALI_TD_SHIFT 5
+#define MT6325_EOSC_CALI_TD_SET_MASK 0x1
+#define MT6325_EOSC_CALI_TD_SET_SHIFT 8
+#define MT6325_EOSC_CALI_TEST_MASK 0xF
+#define MT6325_EOSC_CALI_TEST_SHIFT 9
+#define MT6325_EOSC_CALI_FLAG_SEL_MASK 0xF
+#define MT6325_EOSC_CALI_FLAG_SEL_SHIFT 0
+#define MT6325_EOSC_CALI_FLAG_EN_MASK 0x1
+#define MT6325_EOSC_CALI_FLAG_EN_SHIFT 4
+#define MT6325_FRC_VTCXO0_ON_MASK 0x1
+#define MT6325_FRC_VTCXO0_ON_SHIFT 8
+#define MT6325_FRC_VTCXO0_ON_SET_MASK 0x1
+#define MT6325_FRC_VTCXO0_ON_SET_SHIFT 9
+#define MT6325_EOSC_CALI_RSV_SET_MASK 0x1
+#define MT6325_EOSC_CALI_RSV_SET_SHIFT 10
+#define MT6325_EOSC_CALI_RSV_MASK 0xF
+#define MT6325_EOSC_CALI_RSV_SHIFT 11
+
+#endif // #ifdef PMIC_6325_REG_API
+#endif // #ifndef __DCL_PMIC6325_HW_H_STRUCT__
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmic6325_sw.h b/mcu/driver/peripheral/inc/dcl_pmic6325_sw.h
new file mode 100644
index 0000000..4eb3096
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmic6325_sw.h
@@ -0,0 +1,172 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6325_sw.h
+ *
+ * Project:
+ * --------
+ * MOLY Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6325
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DCL_PMIC6325_SW_H_STRUCT__
+#define __DCL_PMIC6325_SW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#ifdef PMIC_6325_REG_API
+
+// Combinational functions
+extern void pmic6325_customization_init(void);
+
+typedef enum
+{
+ MT6325_HWCID,
+ MT6325_SWCID,
+ MT6325_RG_VPA_MODESET,
+ MT6325_RG_VRF18_0_MODESET,
+ MT6325_VRF18_0_EN_CTRL,
+ MT6325_VRF18_0_VOSEL_CTRL,
+ MT6325_VRF18_0_EN_SEL,
+ MT6325_VRF18_0_VOSEL_SEL,
+ MT6325_VRF18_0_EN,
+ MT6325_VRF18_0_VOSEL,
+ MT6325_VRF18_0_VOSEL_ON,
+ MT6325_VRF18_0_VOSEL_SLEEP,
+ MT6325_VRF18_0_VSLEEP_EN,
+ MT6325_VPA_EN_SEL,
+ MT6325_VPA_VOSEL_SEL,
+ MT6325_VPA_EN,
+ MT6325_VPA_VOSEL,
+ MT6325_VPA_VOSEL_ON,
+ MT6325_VPA_VOSEL_SLEEP,
+ MT6325_RG_VTCXO0_MODE_SET,
+ MT6325_RG_VTCXO0_EN,
+ MT6325_RG_VTCXO0_MODE_CTRL,
+ MT6325_RG_VTCXO0_ON_CTRL,
+ MT6325_RG_VTCXO0_SRCLK_MODE_SEL,
+ MT6325_QI_VTCXO0_MODE,
+ MT6325_RG_VTCXO1_MODE_SET,
+ MT6325_RG_VTCXO1_EN,
+ MT6325_RG_VTCXO1_MODE_CTRL,
+ MT6325_RG_VTCXO1_ON_CTRL,
+ MT6325_RG_VTCXO1_SRCLK_MODE_SEL,
+ MT6325_QI_VTCXO1_MODE,
+ MT6325_RG_VRF18_1_MODE_SET,
+ MT6325_RG_VRF18_1_EN,
+ MT6325_RG_VRF18_1_MODE_CTRL,
+ MT6325_RG_VRF18_1_ON_CTRL,
+ MT6325_RG_VRF18_1_SRCLK_MODE_SEL,
+ MT6325_QI_VRF18_1_MODE,
+ MT6325_RG_VRF18_1_SRCLK_EN_SEL,
+ MT6325_RG_VSIM1_MODE_SET,
+ MT6325_RG_VSIM1_EN,
+ MT6325_RG_VSIM1_MODE_CTRL,
+ MT6325_RG_VSIM1_ON_CTRL,
+ MT6325_RG_VSIM1_SRCLK_MODE_SEL,
+ MT6325_QI_VSIM1_MODE,
+ MT6325_RG_VSIM1_STBTD,
+ MT6325_RG_VSIM1_SRCLK_EN_SEL,
+ MT6325_RG_VSIM2_MODE_SET,
+ MT6325_RG_VSIM2_EN,
+ MT6325_RG_VSIM2_MODE_CTRL,
+ MT6325_RG_VSIM2_ON_CTRL,
+ MT6325_RG_VSIM2_SRCLK_MODE_SEL,
+ MT6325_QI_VSIM2_MODE,
+ MT6325_RG_VSIM2_STBTD,
+ MT6325_RG_VSIM2_SRCLK_EN_SEL,
+ MT6325_QI_VSIM2_STB,
+ MT6325_QI_VSIM2_EN,
+ MT6325_RG_VMIPI_MODE_SET,
+ MT6325_RG_VMIPI_EN,
+ MT6325_RG_VMIPI_MODE_CTRL,
+ MT6325_RG_VMIPI_ON_CTRL,
+ MT6325_RG_VMIPI_SRCLK_MODE_SEL,
+ MT6325_QI_VMIPI_MODE,
+ MT6325_RG_VMIPI_STBTD,
+ MT6325_RG_VMIPI_SRCLK_EN_SEL,
+ MT6325_QI_VMIPI_EN,
+ MT6325_RG_VSIM2_VOSEL,
+ MT6325_RG_VSIM1_VOSEL,
+ MT6325_RG_SPK_CCODE,
+ MT6325_RG_SPK_EN_VIEW_VCM,
+ MT6325_RG_SPK_FBRC_EN,
+ MT6325_SPK_TEST_MODE0,
+ MT6325_SPK_TD_DONE,
+ MT6325_AUXADC_RQST1_SET,
+ MT6325_AUXADC_RQST1_CLR,
+ MT6325_RG_ADC_OUT_MD,
+ MT6325_RG_ADC_RDY_MD,
+ MT6325_RG_MD_RQST,
+ MT6325_RG_VREF18_ENB_MD,
+}PMIC6325_FLAGS_LIST_ENUM;
+
+#endif // #ifdef PMIC_6325_REG_API
+#endif // #ifndef __DCL_PMIC6325_SW_H_STRUCT__
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmic6326_ccci_sw.h b/mcu/driver/peripheral/inc/dcl_pmic6326_ccci_sw.h
new file mode 100644
index 0000000..9aa729e
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmic6326_ccci_sw.h
@@ -0,0 +1,255 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6326_ccci_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC6326 CCCI
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+
+#ifndef __DCL_PMU6326_CCCI_SW_H_STRUCT__
+#define __DCL_PMU6326_CCCI_SW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6326_CCCI_REG_API)
+
+typedef enum
+{
+ PMIC6326_VSIM_ENABLE = 0,
+ PMIC6326_VSIM_SET_AND_ENABLE = 1,
+ PMIC6236_LOCK = 2,
+ PMIC6326_UNLOCK = 3,
+ PMIC6326_VSIM2_ENABLE = 4,
+ PMIC6326_VSIM2_SET_AND_ENABLE = 5,
+ PMIC6326_MAX
+}pmic6326_ccci_op;
+
+typedef enum
+{
+ PMIC6326_REQ = 0, // Local side send request to remote side
+ PMIC6326_RES = 1 // Remote side send response to local side
+}pmic6326_ccci_type;
+
+/*
+ The CCCI message format (CCIF Mailbox port)
+ | 4 bytes | 4 bytes | 4 bytes | 4 bytes |
+ Magic number Message ID Logical channel Reserved
+ PMIC msg PMIC msg info
+*/
+
+/*
+ PMIC msg format
+ (MSB) (LSB)
+ | 1 byte | 1 byte | 1 byte | 1 byte |
+ Param2 Param1 Type Op
+*/
+
+/*
+ PMIC msg info format
+ (MSB) (LSB)
+ | 1 byte | 1 byte | 2 bytes |
+ Param2 Param1 Exec_time
+*/
+
+
+
+typedef struct
+{
+ kal_uint8 pmic6326_op; // Operation
+ kal_uint8 pmic6326_type; // message type: Request or Response
+ kal_uint8 pmic6326_param1;
+ kal_uint8 pmic6326_param2;
+}pmic6326_ccci_msg;
+
+typedef struct
+{
+ kal_uint16 pmic6326_exec_time; // Operation execution time (In ms)
+ kal_uint8 pmic6326_param1;
+ kal_uint8 pmic6326_param2;
+}pmic6326_ccci_msg_info;
+
+/*
+ PMIC share memory
+ (MSB) (LSB)
+ | 1 byte | 1 byte | 1 byte | 1 byte |
+ Param2 Param1 Type Op
+ | 1 byte | 1 byte | 2 bytes |
+ Param2 Param1 Exec_time
+*/
+
+typedef struct
+{
+ pmic6326_ccci_msg ccci_msg;
+ pmic6326_ccci_msg_info ccci_msg_info;
+}pmic6326_share_mem_info;
+
+
+
+// =======================================================================================
+#define MAX_PMIC6326_CCCI_POLLING_PERIOD 1000
+
+// Define to bypass PMIC CCCI driver
+// This is only for debug purpose
+// 1. Always return when upper layer call exported PMIC APIs
+// 2. Boot phase parameter check and API check always return OK
+//#define BY_PASS_PMIC_CCCI_DRIVER
+
+// If NOT define __SMART_PHONE_MODEM__, it means we are MD standalone,
+// so need to bypass communication with AP side (Ex: Get share memory info, Send CCCI command to AP)
+#if (!defined(__SMART_PHONE_MODEM__))
+#define BY_PASS_PMIC_CCCI_DRIVER
+#endif // #if (!defined(__SMART_PHONE_MODEM__))
+
+/*
+typedef enum
+{
+ VSIM,
+ VSIM2,
+ PMU_LDO_BUCK_MAX,
+ VFM,
+ VMC,
+ VRF,
+ VTCXO,
+ V3GTX,
+ V3GRX,
+ VA,
+ VIO,
+ VRTC,
+ VCAMA,
+ VCAMD,
+ VWIFI3V3,
+ VWIFI2V8,
+ VBT,
+ VUSB,
+ VGP,
+ VGP2,
+ VSDIO,
+ VCORE,
+ VCORE1,
+ VCORE2,
+ VM,
+ VMEM,
+ VRF18,
+ VIBR
+}PMU_LDO_BUCK_LIST_ENUM;
+
+typedef enum
+{
+ VPA1,
+ PMU_VPA_MAX
+}PMU_VPA_LIST_ENUM;
+
+typedef enum
+{
+ CHR,
+ PMU_CHR_MAX
+}PMU_CHR_LIST_ENUM;
+
+typedef enum
+{
+ SPK,
+ SPKL,
+ SPKR,
+ PMU_SPK_MAX
+}PMU_SPK_LIST_ENUM;
+
+typedef enum
+{
+ PMU_ISINK_MAX
+}PMU_ISINK_LIST_ENUM;
+
+typedef enum
+{
+ BOOST1,
+ BOOST2,
+ PMU_BOOST_MAX
+}PMU_BOOST_LIST_ENUM;
+
+*/
+
+#endif // #if defined(PMIC_6326_CCCI_REG_API)
+#endif // #ifndef __DCL_PMU6326_CCCI_SW_H_STRUCT__
+
+
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmic6326_hw.h b/mcu/driver/peripheral/inc/dcl_pmic6326_hw.h
new file mode 100644
index 0000000..98ca39b
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmic6326_hw.h
@@ -0,0 +1,794 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6326_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC6326
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef __DCL_PMIC6326_HW_H_STRUCT__
+#define __DCL_PMIC6326_HW_H_STRUCT__
+
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6326_REG_API)
+
+
+#define BIT00 0x00000001
+#define BIT01 0x00000002
+#define BIT02 0x00000004
+#define BIT03 0x00000008
+
+#define BIT04 0x00000010
+#define BIT05 0x00000020
+#define BIT06 0x00000040
+#define BIT07 0x00000080
+
+#define BIT08 0x00000100
+#define BIT09 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+
+
+#define PMIC6326_E1_CID_CODE 0x0000
+#define PMIC6326_E2_CID_CODE 0x0009
+#define PMIC6326_E3_CID_CODE 0x000A
+#define PMIC6326_E4_CID_CODE 0x000B
+
+#define CID_1_REG_INDEX 0x0
+#define CID_2_REG_INDEX 0x1
+
+#define EFUSE_BUFF_4_REG_INDEX 0x12
+
+#define PMIC_MAX_REG_IDX 0x96
+#define PMIC_REG_NUM 0x97 // ###***** PMIC_REG_NUM must equal (PMIC_MAX_REG_IDX + 1)
+
+
+// (0x09) STATUS 6 (RO)
+#define BOOST2_OC_STATUS_MASK 0x1
+#define BOOST2_OC_STATUS_SHIFT 0x0
+#define SPKR_OC_DET_MASK 0x1
+#define SPKR_OC_DET_SHIFT 0x1
+#define SPKL_OC_DET_MASK 0x1
+#define SPKL_OC_DET_SHIFT 0x2
+#define PWRKEY_DEB_MASK 0x1
+#define PWRKEY_DEB_SHIFT 0x3
+#define OVP_MASK 0x1
+#define OVP_SHIFT 0x4
+#define CHRDET_MASK 0x1
+#define CHRDET_SHIFT 0x5
+#define BAT_ON_MASK 0x1
+#define BAT_ON_SHIFT 0x6
+#define CV_MASK 0x1
+#define CV_SHIFT 0x7
+
+// (0x0D) INT STATUS 3 (RO)
+#define VSDIO_OC_FLAG_STATUS_MASK 0x1
+#define VSDIO_OC_FLAG_STATUS_SHIFT 0x0
+#define VGP_OC_FLAG_STATUS_MASK 0x1
+#define VGP_OC_FLAG_STATUS_SHIFT 0x1
+#define VUSB_OC_FLAG_STATUS_MASK 0x1
+#define VUSB_OC_FLAG_STATUS_SHIFT 0x2
+#define OVP_INT_FLAG_STATUS_MASK 0x1
+#define OVP_INT_FLAG_STATUS_SHIFT 0x3
+#define CHRDET_INT_FLAG_STATUS_MASK 0x1
+#define CHRDET_INT_FLAG_STATUS_SHIFT 0x4
+
+// (0x0E) INT STATUS 4 (RO)
+#define WATCHDOG_INT_FLAG_STATUS_MASK 0x1
+#define WATCHDOG_INT_FLAG_STATUS_SHIFT 0x0
+
+// (0x1A) LDO CTRL 1 VGP2
+#define VGP2_EN_MASK 0x1
+#define VGP2_EN_SHIFT 0x2
+// (0x1B) LDO CTRL 2 VRF
+#define VRF_ICAL_EN_MASK 0x3
+#define VRF_ICAL_EN_SHIFT 0x0
+#define VRF_OC_AUTO_OFF_MASK 0x1
+#define VRF_OC_AUTO_OFF_SHIFT 0x1
+#define VRF_EN_MASK 0x1
+#define VRF_EN_SHIFT 0x3
+#define VRF_CAL_MASK 0xF
+#define VRF_CAL_SHIFT 0x4
+
+// (0x1C) LDO CTRL 3 VRF
+#define VRF_CALST_MASK 0x3
+#define VRF_CALST_SHIFT 0x0
+#define VRF_CALOC_MASK 0x3
+#define VRF_CALOC_SHIFT 0x2
+#define VRF_ON_SEL_MASK 0x1
+#define VRF_ON_SEL_SHIFT 0x4
+#define VRF_EN_FORCE_MASK 0x1
+#define VRF_EN_FORCE_SHIFT 0x5
+#define VRF_PLNMOS_DIS_MASK 0x1
+#define VRF_PLNMOS_DIS_SHIFT 0x6
+#define VRF_CM_MASK 0x1
+#define VRF_CM_SHIFT 0x7
+// (0x1E) LDO CTRL 5 VTCXO
+#define VTCXO_ICAL_EN_MASK 0x3
+#define VTCXO_ICAL_EN_SHIFT 0x0
+#define VTCXO_OC_AUTO_OFF_MASK 0x1
+#define VTCXO_OC_AUTO_OFF_SHIFT 0x2
+#define VTCXO_EN_MASK 0x1
+#define VTCXO_EN_SHIFT 0x3
+#define VTCXO_CAL_MASK 0xF
+#define VTCXO_CAL_SHIFT 0x4
+// (0x1F) LDO CTRL 6 VTCXO
+#define VTCXO_CALST_MASK 0x3
+#define VTCXO_CALST_SHIFT 0x0
+#define VTCXO_CALOC_MASK 0x3
+#define VTCXO_CALOC_SHIFT 0x2
+#define VTCXO_ON_SEL_MASK 0x1
+#define VTCXO_ON_SEL_SHIFT 0x4
+#define VTCXO_EN_FORCE_MASK 0x1
+#define VTCXO_EN_FORCE_SHIFT 0x5
+#define VTCXO_PLNMOS_DIS_MASK 0x1
+#define VTCXO_PLNMOS_DIS_SHIFT 0x6
+#define VTCXO_CM_MASK 0x1
+#define VTCXO_CM_SHIFT 0x7
+// (0x21) LDO CTRL 8 V3GTX
+#define V3GTX_SEL_MASK 0x3
+#define V3GTX_SEL_SHIFT 0x0
+#define V3GTX_ICAL_EN_MASK 0x3
+#define V3GTX_ICAL_EN_SHIFT 0x2
+#define V3GTX_CAL_MASK 0xF
+#define V3GTX_CAL_SHIFT 0x4
+// (0x22) LDO CTRL 9 V3GTX
+#define V3GTX_CALST_MASK 0x3
+#define V3GTX_CALST_SHIFT 0x0
+#define V3GTX_CALOC_MASK 0x3
+#define V3GTX_CALOC_SHIFT 0x2
+#define V3GTX_OC_AUTO_OFF_MASK 0x1
+#define V3GTX_OC_AUTO_OFF_SHIFT 0x4
+#define V3GTX_EN_MASK 0x1
+#define V3GTX_EN_SHIFT 0x5
+#define V3GTX_ON_SEL_MASK 0x1
+#define V3GTX_ON_SEL_SHIFT 0x6
+#define V3GTX_EN_FORCE_MASK 0x1
+#define V3GTX_EN_FORCE_SHIFT 0x7
+
+// (0X23) LDO CTRL 10 V3GTX
+#define V3GTX_PLNMOS_DIS_MASK 0x1
+#define V3GTX_PLNMOS_DIS_SHIFT 0x0
+
+// (0x24) LDO CTRL 11 V3GRX
+#define V3GRX_SEL_MASK 0x3
+#define V3GRX_SEL_SHIFT 0x0
+#define V3GRX_ICAL_EN_MASK 0x3
+#define V3GRX_ICAL_EN_SHIFT 0x2
+#define V3GRX_CAL_MASK 0xf
+#define V3GRX_CAL_SHIFT 0x4
+// (0x25) LDO CTRL 12 V3GRX
+#define V3GRX_CALST_MASK 0x3
+#define V3GRX_CALST_SHIFT 0x0
+#define V3GRX_CALOC_MASK 0x3
+#define V3GRX_CALOC_SHIFT 0x2
+#define V3GRX_OC_AUTO_OFF_MASK 0x1
+#define V3GRX_OC_AUTO_OFF_SHIFT 0x4
+#define V3GRX_EN_MASK 0x1
+#define V3GRX_EN_SHIFT 0x5
+#define V3GRX_ON_SEL_MASK 0x1
+#define V3GRX_ON_SEL_SHIFT 0x6
+#define V3GRX_EN_FORCE_MASK 0x1
+#define V3GRX_EN_FORCE_SHIFT 0x7
+
+// (0X26) LDO CTRL 10 V3GRX
+#define V3GRX_PLNMOS_DIS_MASK 0x1
+#define V3GRX_PLNMOS_DIS_SHIFT 0x0
+
+
+// (0x2E) LDO CTRL 21 VCAMA
+#define VCAMA_SEL_MASK 0x3
+#define VCAMA_SEL_SHIFT 0x0
+#define VCAMA_ICAL_EN_MASK 0x3
+#define VCAMA_ICAL_EN_SHIFT 0x2
+#define VCAMA_CAL_MASK 0xf
+#define VCAMA_CAL_SHIFT 0x4
+// (0x2F) LDO CTRL 22 VCAMA
+#define VCAMA_CALST_MASK 0x3
+#define VCAMA_CALST_SHIFT 0x0
+#define VCAMA_CALOC_MASK 0x3
+#define VCAMA_CALOC_SHIFT 0x2
+#define VCAMA_EN_MASK 0x1
+#define VCAMA_EN_SHIFT 0x4
+#define VCAMA_EN_FORCE_MASK 0x1
+#define VCAMA_EN_FORCE_SHIFT 0x5
+#define VCAMA_PLNMOS_DIS_MASK 0x1
+#define VCAMA_PLNMOS_DIS_SHIFT 0x6
+#define VCAMA_CM_MASK 0x1
+#define VCAMA_CM_SHIFT 0x7
+
+// (0x31) LDO CTRL 24 VWIFI3V3
+#define VWIFI3V3_SEL_MASK 0x3
+#define VWIFI3V3_SEL_SHIFT 0x0
+#define VWIFI3V3_ICAL_EN_MASK 0x3
+#define VWIFI3V3_ICAL_EN_SHIFT 0x2
+#define VWIFI3V3_CAL_MASK 0xf
+#define VWIFI3V3_CAL_SHIFT 0x4
+// (0x32) LDO CTRL 25 VWIFI3V3
+#define VWIFI3V3_CALST_MASK 0x3
+#define VWIFI3V3_CALST_SHIFT 0x0
+#define VWIFI3V3_CALOC_MASK 0x3
+#define VWIFI3V3_CALOC_SHIFT 0x2
+#define VWIFI3V3_EN_MASK 0x1
+#define VWIFI3V3_EN_SHIFT 0x4
+#define VWIFI3V3_EN_FORCE_MASK 0x1
+#define VWIFI3V3_EN_FORCE_SHIFT 0x5
+#define VWIFI3V3_PLNMOS_DIS_MASK 0x1
+#define VWIFI3V3_PLNMOS_DIS_SHIFT 0x6
+#define VWIFI3V3_CM_MASK 0x1
+#define VWIFI3V3_CM_SHIFT 0x7
+
+// (0x34) LDO CTRL 27 VWIFI2V8
+#define VWIFI2V8_SEL_MASK 0x3
+#define VWIFI2V8_SEL_SHIFT 0x0
+#define VWIFI2V8_ICAL_EN_MASK 0x3
+#define VWIFI2V8_ICAL_EN_SHIFT 0x2
+#define VWIFI2V8_CAL_MASK 0xf
+#define VWIFI2V8_CAL_SHIFT 0x4
+
+// (0x35) LDO CTRL 28 VWIFI2V8
+#define VWIFI2V8_CALST_MASK 0x3
+#define VWIFI2V8_CALST_SHIFT 0x0
+#define VWIFI2V8_CALOC_MASK 0x3
+#define VWIFI2V8_CALOC_SHIFT 0x2
+#define VWIFI2V8_EN_MASK 0x1
+#define VWIFI2V8_EN_SHIFT 0x4
+#define VWIFI2V8_EN_FORCE_MASK 0x1
+#define VWIFI2V8_EN_FORCE_SHIFT 0x5
+#define VWIFI2V8_PLNMOS_DIS_MASK 0x1
+#define VWIFI2V8_PLNMOS_DIS_SHIFT 0x6
+#define VWIFI2V8_CM_MASK 0x1
+#define VWIFI2V8_CM_SHIFT 0x7
+
+
+// (0x37) LDO CTRL 30 VSIM
+#define VSIM_SEL_MASK 0x7
+#define VSIM_SEL_SHIFT 0x0
+#define VSIM_EN_MASK 0x1
+#define VSIM_EN_SHIFT 0x3
+#define VSIM_ICAL_EN_MASK 0x3
+#define VSIM_ICAL_EN_SHIFT 0x4
+#define VSIM_EN_FORCE_MASK 0x1
+#define VSIM_EN_FORCE_SHIFT 0x6
+#define VSIM_PLNMOS_DIS_MASK 0x1
+#define VSIM_PLNMOS_DIS_SHIFT 0x7
+
+// (0x38) LDO CTRL 31 VSIM
+#define VSIM_CAL_MASK 0xf
+#define VSIM_CAL_SHIFT 0x0
+
+// (0x3A) LDO CTRL 33 VUSB (From E3, USB LDO controls are moved to 0x3D ~ 0x3F)
+
+ // From E3, VGP2 OCFB enable control is at 0x3D
+#define VGP2_OCFB_EN_MASK 0x1
+#define VGP2_OCFB_EN_SHIFT 0x0
+
+#define VUSB_SEL_MASK 0x7
+#define VUSB_SEL_SHIFT 0x0
+#define VUSB_EN_MASK 0x1
+#define VUSB_EN_SHIFT 0x3
+#define VUSB_ICAL_EN_MASK 0x3
+#define VUSB_ICAL_EN_SHIFT 0x4
+#define VUSB_EN_FORCE_MASK 0x1
+#define VUSB_EN_FORCE_SHIFT 0x6
+#define VUSB_PLNMOS_DIS_MASK 0x1
+#define VUSB_PLNMOS_DIS_SHIFT 0x7
+
+// (0x3B) LDO CTRL 34 VUSB (From E3, USB LDO controls are moved to 0x3D ~ 0x3F)
+#define VUSB_CAL_MASK 0xf
+#define VUSB_CAL_SHIFT 0x0
+#define VUSB_CALST_MASK 0x3
+#define VUSB_CALST_SHIFT 0x4
+#define VUSB_CALOC_MASK 0x3
+#define VUSB_CALOC_SHIFT 0x6
+
+// (0x3D) LDO CTRL 36 VBT (From E3, BT LDO controls are moved to 0x3A ~ 0x3C)
+#define VBT_SEL_MASK 0x7
+#define VBT_SEL_SHIFT 0x0
+#define VBT_EN_MASK 0x1
+#define VBT_EN_SHIFT 0x3
+#define VBT_ICAL_EN_MASK 0x3
+#define VBT_ICAL_EN_SHIFT 0x4
+#define VBT_EN_FORCE_MASK 0x1
+#define VBT_EN_FORCE_SHIFT 0x6
+#define VBT_PLNMOS_DIS_MASK 0x1
+#define VBT_PLNMOS_DIS_SHIFT 0x7
+
+// (0x3E) LDO CTRL 37 VBT (From E3, BT LDO controls are moved to 0x3A ~ 0x3C)
+#define VBT_CAL_MASK 0xf
+#define VBT_CAL_SHIFT 0x0
+#define VBT_CALST_MASK 0x3
+#define VBT_CALST_SHIFT 0x4
+#define VBT_CALOC_MASK 0x3
+#define VBT_CALOC_SHIFT 0x6
+
+// (0x40) LDO CTRL 39 VCAMD
+#define VCAMD_SEL_MASK 0x7
+#define VCAMD_SEL_SHIFT 0x0
+#define VCAMD_EN_MASK 0x1
+#define VCAMD_EN_SHIFT 0x3
+#define VCAMD_ICAL_EN_MASK 0x3
+#define VCAMD_ICAL_EN_SHIFT 0x4
+#define VCAMD_EN_FORCE_MASK 0x1
+#define VCAMD_EN_FORCE_SHIFT 0x6
+#define VCAMD_PLNMOS_DIS_MASK 0x1
+#define VCAMD_PLNMOS_DIS_SHIFT 0x7
+
+// (0x41) LDO CTRL 40 VCAMD
+#define VCAMD_CAL_MASK 0xf
+#define VCAMD_CAL_SHIFT 0x0
+#define VCAMD_CALST_MASK 0x3
+#define VCAMD_CALST_SHIFT 0x4
+#define VCAMD_CALOC_MASK 0x3
+#define VCAMD_CALOC_SHIFT 0x6
+
+// (0x43) LDO CTRL 42 VGP
+#define VGP_SEL_MASK 0x7
+#define VGP_SEL_SHIFT 0x0
+#define VGP_EN_MASK 0x1
+#define VGP_EN_SHIFT 0x3
+#define VGP_PLNMOS_DIS_MASK 0x1
+#define VGP_PLNMOS_DIS_SHIFT 0x7
+
+// (0x44) LDO CTRL 43 VGP
+#define VGP_CAL_MASK 0xf
+#define VGP_CAL_SHIFT 0x0
+
+// (0x46) LDO CTRL 45 VSDIO
+#define VSDIO_ICAL_EN_MASK 0x3
+#define VSDIO_ICAL_EN_SHIFT 0x0
+#define VSDIO_EN_MASK 0x1
+#define VSDIO_EN_SHIFT 0x2
+#define VSDIO_EN_FORCE_MASK 0x1
+#define VSDIO_EN_FORCE_SHIFT 0x3
+#define VSDIO_CAL_MASK 0xf
+#define VSDIO_CAL_SHIFT 0x4
+
+// (0x47) LDO CTRL 46 VSDIO
+#define VSDIO_CALST_MASK 0x3
+#define VSDIO_CALST_SHIFT 0x0
+#define VSDIO_CALOC_MASK 0x3
+#define VSDIO_CALOC_SHIFT 0x2
+#define VSDIO_PLNMOS_DIS_MASK 0x1
+#define VSDIO_PLNMOS_DIS_SHIFT 0x4
+#define VSDIO_SEL_MASK 0x1
+#define VSDIO_SEL_SHIFT 0x5
+#define VSDIO_CM_MASK 0x1
+#define VSDIO_CM_SHIFT 0x6
+
+// (0x48) LDO CTRL 47 VSDIO
+#define VCORE1_DVFS_STEP_INC_MASK 0x1f
+#define VCORE1_DVFS_STEP_INC_SHIFT 0x3
+
+// (0x49) BULK CTRL 1 VGP2 (SEL L)
+#define VGP2_SELL_MASK 0x3
+#define VGP2_SELL_SHIFT 0x4
+
+// (0x4B) BULK CTRL 3 VGP2 (SEL H)
+#define VGP2_SELH_MASK 0x1
+#define VGP2_SELH_SHIFT 0x4
+
+// (0x4E) BUCK CTRL 6 VCORE1
+#define VCORE1_DVFS_0_ECO3_MASK 0xf
+#define VCORE1_DVFS_0_ECO3_SHIFT 0x4
+
+// (0x4F) BUCK CTRL 7 VCORE1
+#define VCORE1_SLEEP_0_ECO3_MASK 0x1
+#define VCORE1_SLEEP_0_ECO3_SHIFT 0x3
+#define VCORE1_DVFS_RAMP_EN_MASK 0x1
+#define VCORE1_DVFS_RAMP_EN_SHIFT 0x6
+#define VCORE1_DVFS_TARGET_UPDATE_MASK 0x1
+#define VCORE1_DVFS_TARGET_UPDATE_SHIFT 0x7
+
+// (0x51) BUCK CTRL 9 VCORE2
+#define VCORE2_DVFS_0_ECO3_MASK 0x4
+#define VCORE2_DVFS_0_ECO3_SHIFT 0xF
+
+// (0x52) BUCK CTRL 10 VCORE2
+#define VCORE2_EN_MASK 0x1
+#define VCORE2_EN_SHIFT 0x7
+#define VCORE2_SLEEP_0_ECO3_MASK 0x1
+#define VCORE2_SLEEP_0_ECO3_SHIFT 0x3
+
+
+
+// (0x53) BUCK CTRL 11 VCORE2
+#define VCORE2_ON_SEL_MASK 0x1
+#define VCORE2_ON_SEL_SHIFT 0x3
+
+// (0x54)
+#define VCORE2_PLNMOS_DIS_MASK 0x1
+#define VCORE2_PLNMOS_DIS_SHIFT 0x0
+
+
+// (0x57) BUCK CTRL 15 VMEM
+#define VCORE1_SLEEP_1_ECO3_MASK 0x1
+#define VCORE1_SLEEP_1_ECO3_SHIFT 0x0
+#define VCORE1_DVFS_1_ECO3_MASK 0xf
+#define VCORE1_DVFS_1_ECO3_SHIFT 0x4
+
+// (0x58) BULK CTRL 16 VPA
+#define VPA_TUNEH_MASK 0x1F
+#define VPA_TUNEH_SHIFT 0x0
+#define VPA_EN_FORCE_MASK 0x1
+#define VPA_EN_FORCE_SHIFT 0x5
+#define VPA_PLNMOS_DIS_MASK 0x1
+#define VPA_PLNMOS_DIS_SHIFT 0x6
+#define VPA_EN_MASK 0x1
+#define VPA_EN_SHIFT 0x7
+
+// (0x59) BULK CTRL 17 VPA
+#define VPA_TUNEL_MASK 0x1F
+#define VPA_TUNEL_SHIFT 0x0
+
+// (0x5A) BUCK CTRL 18 VPA
+#define VPA_OC_TH_MASK 0x7
+#define VPA_OC_TH_SHIFT 0x0
+
+
+#define VPA_BAT_LOW_MASK 0x1
+#define VPA_BAT_LOW_SHIFT 0x3
+
+// (0x5C) BOOST CTRL 1 BOOST1
+#define VBOOST1_TUNE_MASK 0xF
+#define VBOOST1_TUNE_SHIFT 0x0
+#define VBOOST1_TATT_MASK 0xF
+#define VBOOST1_TATT_SHIFT 0x4
+
+// (0x5D) BOOST CTRL 2 BOOST1
+#define BOOST1_OC_TH_MASK 0x7
+#define BOOST1_OC_TH_SHIFT 0x0
+#define BOOST1_EN_MASK 0x1
+#define BOOST1_EN_SHIFT 0x3
+#define BOOST1_PRE_SR_CON_MASK 0x7
+#define BOOST1_PRE_SR_CON_SHIFT 0x4
+#define BOOST1_SOFT_ST_SPEED_MASK 0x1
+#define BOOST1_SOFT_ST_SPEED_SHIFT 0x7
+
+// (0x5E) BOOST CTRL 3 BOOST1
+#define BOOST1_DIO_SR_CON_MASK 0x7
+#define BOOST1_DIO_SR_CON_SHIFT 0x0
+#define BOOST1_SYNC_EN_MASK 0x1
+#define BOOST1_SYNC_EN_SHIFT 0x3
+// #### D4 is used as VGP2_SEL[2]
+
+// (0x5F) BOOST CTRL 4 BOOST2
+#define BOOST2_TUNE_MASK 0xF
+#define BOOST2_TUNE_SHIFT 0x0
+#define BOOST2_OC_TH_MASK 0x3
+#define BOOST2_OC_TH_SHIFT 0x4
+#define BOOST2_DIM_SOURCE_MASK 0x1
+#define BOOST2_DIM_SOURCE_SHIFT 0x6
+
+// (0x60) BOOST CTRL 5 BOOST2
+#define BOOST2_PRE_SR_CON_MASK 0x7
+#define BOOST2_PRE_SR_CON_SHIFT 0x0
+#define BOOST2_EN_MASK 0x1
+#define BOOST2_EN_SHIFT 0x4
+
+// (0x61) BOOST CTRL 6 BOOST2 and BOOST
+#define BOOST_MODE_MASK 0x3
+#define BOOST_MODE_SHIFT 0x4
+
+// (0x63) DRIVER CTRL 2
+#define VBUS_EN_MASK 0x1
+#define VBUS_EN_SHIFT 0x0
+
+
+// (0x64) DRIVER CTRL 3 GEN
+#define IGEN_DRV_ISEL_MASK 0x3
+#define IGEN_DRV_ISEL_SHIFT 0x0
+#define IGEN_DRV_FORCE_MASK 0x4
+#define IGEN_DRV_FORCE_SHIFT 0x2
+#define VGEN_DRV_BGSEL_MASK 0x7
+#define VGEN_DRV_BGSEL_SHIFT 0x4
+
+// (0x65) DRIVER CTRL 4 FLASH
+#define FLASH_I_TUNE_MASK 0xf
+#define FLASH_I_TUNE_SHIFT 0x0
+#define FLASH_DIM_DIV_MASK 0xf
+#define FLASH_DIM_DIV_SHIFT 0x4
+
+// (0x66) DRIVER CTRL 5 FLASH
+#define FLASH_DIM_DUTY_MASK 0x1F
+#define FLASH_DIM_DUTY_SHIFT 0x0
+#define FLASH_EN_MASK 0x1
+#define FLASH_EN_SHIFT 0x5
+#define FLASH_BYPASS_MASK 0x1
+#define FLASH_BYPASS_SHIFT 0x6
+
+// (0x67) DRIVER CTRL 6 BL
+#define BL_DIM_DUTY_MASK 0x1F
+#define BL_DIM_DUTY_SHIFT 0x0
+#define BL_EN_MASK 0x1
+#define BL_EN_SHIFT 0x5
+#define BL_I_CAL_EN_MASK 0x1
+#define BL_I_CAL_EN_SHIFT 0x6
+#define BL_BYPASS_MASK 0x1
+#define BL_BYPASS_SHIFT 0x7
+
+// (0x68) DRIVER CTRL 7 BL
+#define BL_I_CORSE_TUNE_MASK 0x7
+#define BL_I_CORSE_TUNE_SHIFT 0x0
+#define BL_I_FINE_TUNE_MASK 0x7
+#define BL_I_FINE_TUNE_SHIFT 0x4
+
+// (0x6D) DRIVER CTRL 12 BL
+#define BL_DIM_DIV_MASK 0xF
+#define BL_DIM_DIV_SHIFT 0x0
+#define BL_NUMBER_MASK 0x7
+#define BL_NUMBER_SHIFT 0x4
+
+// (0x6E) DRIVER CTRL 13 KP
+#define KP_DIM_DIV_MASK 0xF
+#define KP_DIM_DIV_SHIFT 0x0
+#define KP_EN_MASK 0x1
+#define KP_EN_SHIFT 0x4
+
+// (0x6F) DRIVER CTRL 14 KP
+#define KP_DIM_DUTY_MASK 0x1F
+#define KP_DIM_DUTY_SHIFT 0x0
+
+// (0x70) DRIVER CTRL 15 VIBR
+#define VIBR_DIM_DIV_MASK 0xF
+#define VIBR_DIM_DIV_SHIFT 0x0
+#define VIBR_EN_MASK 0x1
+#define VIBR_EN_SHIFT 0x4
+
+// (0x71) DRIVER CTRL 16 VIBR
+#define VIBR_DIM_DUTY_MASK 0x1F
+#define VIBR_DIM_DUTY_SHIFT 0x0
+
+// (0x72) DRIVER CTRL 17
+#define DIM_CK_FORCE_ON_MASK 0x1
+#define DIM_CK_FORCE_ON_SHIFT 0x0
+
+// (0x73) CLASS_D CTRL 3 SPKL
+#define SPKL_DTIN_MASK 0xf
+#define SPKL_DTIN_SHIFT 0x0
+#define SPKL_DTIP_MASK 0xf
+#define SPKL_DTIP_SHIFT 0x4
+
+// (0x74) CLASS_D CTRL 4 SPKL
+#define SPKL_DMODE_MASK 0x3
+#define SPKL_DMODE_SHIFT 0x2
+#define SPKL_EN_MASK 0x1
+#define SPKL_EN_SHIFT 0x6
+#define SPKL_DTCAL_MASK 0x1
+#define SPKL_DTCAL_SHIFT 0x7
+
+// (0x75) CLASS_D CTRL 5 SPKL
+#define SPKL_SLEW_MASK 0x3
+#define SPKL_SLEW_SHIFT 0x6
+
+// (0x76) CLASS_D CTRL 6 SPKL
+#define SPKL_VOL_MASK 0x7
+#define SPKL_VOL_SHIFT 0x0
+
+// (0x77) CLASS_D CTRL 7 SPKL
+#define SPKL_OC_MASK 0x1
+#define SPKL_OC_SHIFT 0x0
+
+
+// (0x78) CLASS_D CTRL 8 SPKR
+#define SPKR_DTIN_MASK 0xf
+#define SPKR_DTIN_SHIFT 0x0
+#define SPKR_DTIP_MASK 0xf
+#define SPKR_DTIP_SHIFT 0x4
+
+// (0x79) CLASS_D CTRL 9 SPKR
+#define SPKR_DMODE_MASK 0x3
+#define SPKR_DMODE_SHIFT 0x2
+#define SPKR_EN_MASK 0x1
+#define SPKR_EN_SHIFT 0x6
+#define SPKR_DTCAL_MASK 0x1
+#define SPKR_DTCAL_SHIFT 0x7
+
+// (0x7A) CLASS_D CTRL 10 SPKR
+#define SPKR_SLEW_MASK 0x3
+#define SPKR_SLEW_SHIFT 0x6
+
+
+// (0x7B) CLASS_D CTRL 11 SPKR
+#define SPKR_VOL_MASK 0x7
+#define SPKR_VOL_SHIFT 0x0
+
+// (0x7C) CLASS_D CTRL 12 SPKR
+#define SPKR_OC_MASK 0x1
+#define SPKR_OC_SHIFT 0x0
+
+
+
+// (0x81) CHARGER CTRL 1
+#define CHR_CHOFST_MASK 0x7
+#define CHR_CHOFST_SHIFT 0x0
+#define CHR_OV_TH_HIGH_MASK 0x1
+#define CHR_OV_TH_HIGH_SHIFT 0x3
+#define CHR_CHR_CURRENT_MASK 0x7
+#define CHR_CHR_CURRENT_SHIFT 0x4
+#define CHR_OV_TH_FREEZE_MASK 0x1
+#define CHR_OV_TH_FREEZE_SHIFT 0x7
+
+// (0x82) CHARGER CTRL 2
+#define CHR_CV_RT_MASK 0x3
+#define CHR_CV_RT_SHIFT 0x0
+#define CHR_CHRON_FORCE_MASK 0x1
+#define CHR_CHRON_FORCE_SHIFT 0x2
+#define CHR_CHR_EN_MASK 0x1
+#define CHR_CHR_EN_SHIFT 0x3
+#define CHR_CV_TUNE_MASK 0x7
+#define CHR_CV_TUNE_SHIFT 0x4
+
+
+// (0x83) TESTMODE CTRL 3 Analog Switch
+#define ASW_ASEL_MASK 0x3
+#define ASW_ASEL_SHIFT 0x0
+#define ASW_BSEL_MASK 0x3
+#define ASW_BSEL_SHIFT 0x2
+#define ASW_A1_SEL_MASK 0x1
+#define ASW_A1_SEL_SHIFT 0x4
+#define ASW_A2_SEL_MASK 0x1
+#define ASW_A2_SEL_SHIFT 0x5
+
+
+// (0x84) TESTMODE CTRL 4 Testmode
+#define VGP2_ON_SEL_MASK 0x1
+#define VGP2_ON_SEL_SHIFT 0x7
+
+
+
+// (0x86) TESTMODE CTRL 6 BB AUXADC Related
+#define ADC_ISENSE_OUT_EN_MASK 0x1
+#define ADC_ISENSE_OUT_EN_SHIFT 0x0
+#define ADC_VBAT_OUT_EN_MASK 0x1
+#define ADC_VBAT_OUT_EN_SHIFT 0x1
+
+
+// (0x89) INT CTRL 1
+// #define in pmic6326_sw.h
+// (0x8A) INT CTRL 2
+// #define in pmic6326_sw.h
+// (0x8B) INT CTRL 3
+// #define in pmic6326_sw.h
+
+// (0x8C)
+#define VCAMA_OC_AUTO_OFF_SHIFT 0x1
+#define VCAMA_OC_AUTO_OFF_MASK 0x1
+
+#define VCAMD_OC_AUTO_OFF_SHIFT 0x6
+#define VCAMD_OC_AUTO_OFF_MASK 0x1
+
+// (0x8F)
+#define ST_GEAR_VWIFI3V3_SHIFT 0x0
+#define ST_GEAR_VWIFI3V3_MASK 0x3
+
+#define ST_GEAR_VWIFI2V8_SHIFT 0x2
+#define ST_GEAR_VWIFI2V8_MASK 0x3
+
+// (0x90)
+#define ST_GEAR_VSDIO_SHIFT 0x2
+#define ST_GEAR_VSDIO_MASK 0x3
+
+// (0x92)
+#define OC_GEAR_VWIFI3V3_SHIFT 0x0
+#define OC_GEAR_VWIFI3V3_MASK 0x3
+
+#define OC_GEAR_VWIFI2V8_SHIFT 0x2
+#define OC_GEAR_VWIFI2V8_MASK 0x3
+
+// (0x93)
+#define OC_GEAR_VSDIO_SHIFT 0x2
+#define OC_GEAR_VSDIO_MASK 0x3
+
+
+// (0x96) WATCHDOG CTRL and INT CTRL 4
+#define WDT_TIMEOUT_MASK 0x3
+#define WDT_TIMEOUT_SHIFT 0x0
+#define INTR_POLARITY_MASK 0x1
+#define INTR_POLARITY_SHIFT 0x2
+#define WDT_DISABLE_MASK 0x1
+#define WDT_DISABLE_SHIFT 0x3
+
+
+#endif //#if defined(PMIC_6326_REG_API)
+
+#endif // #ifndef __DCL_PMIC6326_HW_H_STRUCT__
+
+
+
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmic6326_sw.h b/mcu/driver/peripheral/inc/dcl_pmic6326_sw.h
new file mode 100644
index 0000000..faaf67b
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmic6326_sw.h
@@ -0,0 +1,1967 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6326_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6326
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+
+#ifndef __DCL_PMU6326_SW_H_STRUCT__
+#define __DCL_PMU6326_SW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#ifdef PMIC_6326_REG_API
+
+
+/*
+// debug 1
+// Define to keep chaging when assert
+// This flag is only for debug purpose
+//#define DRV_MISC_PMIC_ASSERT_KEEP_CHARGING
+//#define DEBUG_PMIC6326_NO_CHARGER_WATCHDOG_TIMER
+
+
+// debug 2
+// Define to enable PMIC6326 charger watch dog timer kick
+// When enable charger, PMIC6326 will enable a watch dog timer
+// We need to kick the timer periodically, to ontify PMIC6326 that BB is alive
+// If timeout, PMIC6326 will disable charge automatically
+// #### If this is NOT enabled, we will disable the watch dog timer function at boot time
+//#define ENABLE_PMIC_DRIVER_KICK_CHARGER_WATCHDOG_TIMER ==> Move to be activated by BMT charging algorithm, do NOT use this anymore
+*/
+
+
+#define PMIC6326_ECO_1_VERSION 0x01
+#define PMIC6326_ECO_2_VERSION 0x02
+#define PMIC6326_ECO_3_VERSION 0x03
+#define PMIC6326_ECO_4_VERSION 0x04
+
+
+#ifndef PMIC_OLD_STRUCTURE
+#define PMIC_OLD_STRUCTURE
+
+typedef enum
+{
+ AC_CHR=0,
+ USB_CHR
+}chr_type;
+
+// Common PMIC structures
+
+// Charger type
+typedef enum
+{
+ PMIC_AC_CHR=0,
+ PMIC_USB_CHR
+}pmic_chr_type;
+
+typedef enum
+{
+ PMIC_ADPT_AC_CHR=0,
+ PMIC_ADPT_USB_CHR,
+ PMIC_ADPT_AC_NON_STD_CHR,
+ PMIC_ADPT_USB_CHARGING_HOST_CHR,
+ PMIC_ADPT_NO_CHR // Indicate NO charger
+}pmic_adpt_chr_type;
+
+
+typedef enum
+{
+ PMIC_VSIM_1_8=0,
+ PMIC_VSIM_3_0
+}pmic_adpt_vsim_volt;
+
+
+typedef enum
+{
+ PMIC_ADPT_VCAMA_1_5=0,
+ PMIC_ADPT_VCAMA_1_8,
+ PMIC_ADPT_VCAMA_2_5,
+ PMIC_ADPT_VCAMA_2_8
+}pmic_adpt_vcama_volt;
+
+typedef enum
+{
+ PMIC_ADPT_VCAMD_1_3=0,
+ PMIC_ADPT_VCAMD_1_5,
+ PMIC_ADPT_VCAMD_1_8,
+ PMIC_ADPT_VCAMD_2_5,
+ PMIC_ADPT_VCAMD_2_8,
+ PMIC_ADPT_VCAMD_3_0,
+ PMIC_ADPT_VCAMD_3_3
+}pmic_adpt_vcamd_volt;
+
+typedef struct
+{
+ kal_uint32 chr_current;
+ kal_uint32 reg_index;
+}pmic_adpt_chr_curr_reg_idx_entry;
+
+#define PMIC_ADPT_MAX_CHARGE_CURRENT_LEVEL_NUM 16
+typedef struct
+{
+ kal_uint32 chr_current_level_num;
+ pmic_adpt_chr_curr_reg_idx_entry entry_table[PMIC_ADPT_MAX_CHARGE_CURRENT_LEVEL_NUM];
+}pmic_adpt_chr_curr_table;
+
+typedef struct
+{
+ kal_int32 chr_current_offset;
+ kal_uint32 reg_index;
+}pmic_adpt_chr_curr_offset_reg_idx_entry;
+
+#define PMIC_ADPT_MAX_CHARGE_CURRENT_OFFSET_NUM 8
+typedef struct
+{
+ kal_uint32 chr_current_offset_num;
+ pmic_adpt_chr_curr_offset_reg_idx_entry entry_table[PMIC_ADPT_MAX_CHARGE_CURRENT_OFFSET_NUM];
+}pmic_adpt_chr_curr_offset_table;
+
+////////////////////////////////////////////////////////
+
+typedef enum
+{
+ PMIC_ADPT_LDO_CTRL_CONTROLLER = 0,
+ PMIC_ADPT_LDO_CTRL_LDO_CON
+}pmic_adpt_ldo_ctrl_mode_enum;
+
+typedef enum
+{
+ PMIC_ADPT_BL_MODE_0 = 0,
+ PMIC_ADPT_BL_MODE_1,
+ PMIC_ADPT_BL_MODE_2,
+ PMIC_ADPT_BL_MODE_3,
+ PMIC_ADPT_BL_MODE_NUM
+}pmic_adpt_bl_mode_enum;
+
+typedef enum
+{
+ PMIC_ADPT_SPK_MODE_0 = 0,
+ PMIC_ADPT_SPK_MODE_1,
+ PMIC_ADPT_SPK_MODE_2,
+ PMIC_ADPT_SPK_MODE_3,
+ PMIC_ADPT_SPK_MODE_NUM
+}pmic_adpt_spk_mode_enum;
+
+typedef enum
+{
+ PMIC_ADPT_CHARGE_CURRENT_0_MA = 0,
+ PMIC_ADPT_CHARGE_CURRENT_50_MA = 50,
+ PMIC_ADPT_CHARGE_CURRENT_75_MA = 75,
+ PMIC_ADPT_CHARGE_CURRENT_100_MA = 100,
+ PMIC_ADPT_CHARGE_CURRENT_150_MA = 150,
+ PMIC_ADPT_CHARGE_CURRENT_200_MA = 200,
+ PMIC_ADPT_CHARGE_CURRENT_250_MA = 250,
+ PMIC_ADPT_CHARGE_CURRENT_300_MA = 300,
+ PMIC_ADPT_CHARGE_CURRENT_350_MA = 350,
+ PMIC_ADPT_CHARGE_CURRENT_400_MA = 400,
+ PMIC_ADPT_CHARGE_CURRENT_450_MA = 450,
+ PMIC_ADPT_CHARGE_CURRENT_500_MA = 500,
+ PMIC_ADPT_CHARGE_CURRENT_550_MA = 550,
+ PMIC_ADPT_CHARGE_CURRENT_600_MA = 600,
+ PMIC_ADPT_CHARGE_CURRENT_650_MA = 650,
+ PMIC_ADPT_CHARGE_CURRENT_700_MA = 700,
+ PMIC_ADPT_CHARGE_CURRENT_750_MA = 750,
+ PMIC_ADPT_CHARGE_CURRENT_800_MA = 800,
+ PMIC_ADPT_CHARGE_CURRENT_850_MA = 850,
+ PMIC_ADPT_CHARGE_CURRENT_900_MA = 900,
+ PMIC_ADPT_CHARGE_CURRENT_950_MA = 950,
+ PMIC_ADPT_CHARGE_CURRENT_1000_MA = 1000,
+ PMIC_ADPT_CHARGE_CURRENT_1200_MA = 1200,
+ PMIC_ADPT_CHARGE_CURRENT_1500_MA = 1500,
+ PMIC_ADPT_CHARGE_CURRENT_1800_MA = 1800,
+ PMIC_ADPT_CHARGE_CURRENT_2000_MA = 2000,
+ PMIC_ADPT_CHARGE_CURRENT_MAX
+}pmic_adpt_chr_current_enum;
+
+
+
+
+// Unified PMIC voltage data type
+// The unit value is 1uV ==> 1000000 means 1V
+typedef enum
+{
+ PMIC_ADPT_VOLT_00_000000_V = 0,
+ PMIC_ADPT_VOLT_00_100000_V = 100000,
+ PMIC_ADPT_VOLT_00_200000_V = 200000,
+ PMIC_ADPT_VOLT_00_300000_V = 300000,
+ PMIC_ADPT_VOLT_00_400000_V = 400000,
+ PMIC_ADPT_VOLT_00_500000_V = 500000,
+ PMIC_ADPT_VOLT_00_600000_V = 600000,
+ PMIC_ADPT_VOLT_00_700000_V = 700000,
+ PMIC_ADPT_VOLT_00_800000_V = 800000,
+ PMIC_ADPT_VOLT_00_825000_V = 825000,
+ PMIC_ADPT_VOLT_00_850000_V = 850000,
+ PMIC_ADPT_VOLT_00_875000_V = 875000,
+ PMIC_ADPT_VOLT_00_900000_V = 900000,
+ PMIC_ADPT_VOLT_00_925000_V = 925000,
+ PMIC_ADPT_VOLT_00_950000_V = 950000,
+ PMIC_ADPT_VOLT_00_975000_V = 975000,
+ PMIC_ADPT_VOLT_01_000000_V = 1000000,
+ PMIC_ADPT_VOLT_01_025000_V = 1025000,
+ PMIC_ADPT_VOLT_01_050000_V = 1050000,
+ PMIC_ADPT_VOLT_01_075000_V = 1075000,
+ PMIC_ADPT_VOLT_01_100000_V = 1100000,
+ PMIC_ADPT_VOLT_01_125000_V = 1125000,
+ PMIC_ADPT_VOLT_01_150000_V = 1150000,
+ PMIC_ADPT_VOLT_01_175000_V = 1175000,
+ PMIC_ADPT_VOLT_01_200000_V = 1200000,
+ PMIC_ADPT_VOLT_01_225000_V = 1225000,
+ PMIC_ADPT_VOLT_01_250000_V = 1250000,
+ PMIC_ADPT_VOLT_01_275000_V = 1275000,
+ PMIC_ADPT_VOLT_01_300000_V = 1300000,
+ PMIC_ADPT_VOLT_01_325000_V = 1325000,
+ PMIC_ADPT_VOLT_01_350000_V = 1350000,
+ PMIC_ADPT_VOLT_01_375000_V = 1375000,
+ PMIC_ADPT_VOLT_01_400000_V = 1400000,
+ PMIC_ADPT_VOLT_01_425000_V = 1425000,
+ PMIC_ADPT_VOLT_01_450000_V = 1450000,
+ PMIC_ADPT_VOLT_01_475000_V = 1475000,
+ PMIC_ADPT_VOLT_01_500000_V = 1500000,
+ PMIC_ADPT_VOLT_01_525000_V = 1525000,
+ PMIC_ADPT_VOLT_01_550000_V = 1550000,
+ PMIC_ADPT_VOLT_01_575000_V = 1575000,
+ PMIC_ADPT_VOLT_01_600000_V = 1600000,
+ PMIC_ADPT_VOLT_01_625000_V = 1625000,
+ PMIC_ADPT_VOLT_01_650000_V = 1650000,
+ PMIC_ADPT_VOLT_01_675000_V = 1675000,
+ PMIC_ADPT_VOLT_01_700000_V = 1700000,
+ PMIC_ADPT_VOLT_01_725000_V = 1725000,
+ PMIC_ADPT_VOLT_01_750000_V = 1750000,
+ PMIC_ADPT_VOLT_01_775000_V = 1775000,
+ PMIC_ADPT_VOLT_01_800000_V = 1800000,
+ PMIC_ADPT_VOLT_01_825000_V = 1825000,
+ PMIC_ADPT_VOLT_01_850000_V = 1850000,
+ PMIC_ADPT_VOLT_01_875000_V = 1875000,
+ PMIC_ADPT_VOLT_01_900000_V = 1900000,
+ PMIC_ADPT_VOLT_01_925000_V = 1925000,
+ PMIC_ADPT_VOLT_01_950000_V = 1950000,
+ PMIC_ADPT_VOLT_01_975000_V = 1975000,
+ PMIC_ADPT_VOLT_02_000000_V = 2000000,
+ PMIC_ADPT_VOLT_02_500000_V = 2500000,
+ PMIC_ADPT_VOLT_02_750000_V = 2750000,
+ PMIC_ADPT_VOLT_02_800000_V = 2800000,
+ PMIC_ADPT_VOLT_02_850000_V = 2850000,
+ PMIC_ADPT_VOLT_02_900000_V = 2900000,
+ PMIC_ADPT_VOLT_03_000000_V = 3000000,
+ PMIC_ADPT_VOLT_03_100000_V = 3100000,
+ PMIC_ADPT_VOLT_03_250000_V = 3250000,
+ PMIC_ADPT_VOLT_03_275000_V = 3275000,
+ PMIC_ADPT_VOLT_03_300000_V = 3300000,
+ PMIC_ADPT_VOLT_03_325000_V = 3325000,
+ PMIC_ADPT_VOLT_04_000000_V = 4000000,
+ PMIC_ADPT_VOLT_04_012500_V = 4012500,
+ PMIC_ADPT_VOLT_04_025000_V = 4025000,
+ PMIC_ADPT_VOLT_04_037500_V = 4037500,
+ PMIC_ADPT_VOLT_04_050000_V = 4050000,
+ PMIC_ADPT_VOLT_04_062500_V = 4062500,
+ PMIC_ADPT_VOLT_04_067500_V = 4067500,
+ PMIC_ADPT_VOLT_04_075000_V = 4075000,
+ PMIC_ADPT_VOLT_04_087500_V = 4087500,
+ PMIC_ADPT_VOLT_04_100000_V = 4100000,
+ PMIC_ADPT_VOLT_04_112500_V = 4112500,
+ PMIC_ADPT_VOLT_04_116000_V = 4116000,
+ PMIC_ADPT_VOLT_04_125000_V = 4125000,
+ PMIC_ADPT_VOLT_04_137500_V = 4137500,
+ PMIC_ADPT_VOLT_04_150000_V = 4150000,
+ PMIC_ADPT_VOLT_04_162500_V = 4162500,
+ PMIC_ADPT_VOLT_04_175000_V = 4175000,
+ PMIC_ADPT_VOLT_04_187500_V = 4187500,
+ PMIC_ADPT_VOLT_04_200000_V = 4200000,
+ PMIC_ADPT_VOLT_04_212500_V = 4212500,
+ PMIC_ADPT_VOLT_04_225000_V = 4225000,
+ PMIC_ADPT_VOLT_04_237500_V = 4237500,
+ PMIC_ADPT_VOLT_04_250000_V = 4250000,
+ PMIC_ADPT_VOLT_04_262500_V = 4262500,
+ PMIC_ADPT_VOLT_04_275000_V = 4275000,
+ PMIC_ADPT_VOLT_04_287500_V = 4287500,
+ PMIC_ADPT_VOLT_04_300000_V = 4300000,
+ PMIC_ADPT_VOLT_04_325000_V = 4325000,
+ PMIC_ADPT_VOLT_04_350000_V = 4350000,
+ PMIC_ADPT_VOLT_04_375000_V = 4375000,
+ PMIC_ADPT_VOLT_04_400000_V = 4400000,
+ PMIC_ADPT_VOLT_04_411500_V = 4411500,
+ PMIC_ADPT_VOLT_04_450000_V = 4450000,
+ PMIC_ADPT_VOLT_04_500000_V = 4500000,
+ PMIC_ADPT_VOLT_04_550000_V = 4550000,
+ PMIC_ADPT_VOLT_04_600000_V = 4600000,
+ PMIC_ADPT_VOLT_04_800000_V = 4800000,
+ PMIC_ADPT_VOLT_04_950000_V = 4950000,
+ PMIC_ADPT_VOLT_05_150000_V = 5150000,
+ PMIC_ADPT_VOLT_05_250000_V = 5250000,
+ PMIC_ADPT_VOLT_05_000000_V = 5000000,
+ PMIC_ADPT_VOLT_06_000000_V = 6000000,
+ PMIC_ADPT_VOLT_06_500000_V = 6500000,
+ PMIC_ADPT_VOLT_06_750000_V = 6750000,
+ PMIC_ADPT_VOLT_07_000000_V = 7000000,
+ PMIC_ADPT_VOLT_07_250000_V = 7250000,
+ PMIC_ADPT_VOLT_07_500000_V = 7500000,
+ PMIC_ADPT_VOLT_08_000000_V = 8000000,
+ PMIC_ADPT_VOLT_08_500000_V = 8500000,
+ PMIC_ADPT_VOLT_09_500000_V = 9500000,
+ PMIC_ADPT_VOLT_10_000000_V = 10000000,
+
+
+
+ // Backward compatible
+ PMIC_ADPT_VOLT_0_0 = 0,
+ PMIC_ADPT_VOLT_0_1 = 100000,
+ PMIC_ADPT_VOLT_0_2 = 200000,
+ PMIC_ADPT_VOLT_0_3 = 300000,
+ PMIC_ADPT_VOLT_0_4 = 400000,
+ PMIC_ADPT_VOLT_0_5 = 500000,
+ PMIC_ADPT_VOLT_0_6 = 600000,
+ PMIC_ADPT_VOLT_0_7 = 700000,
+ PMIC_ADPT_VOLT_0_8 = 800000,
+ PMIC_ADPT_VOLT_0_9 = 900000,
+ PMIC_ADPT_VOLT_1_0 = 1000000,
+ PMIC_ADPT_VOLT_1_1 = 1100000,
+ PMIC_ADPT_VOLT_1_2 = 1200000,
+ PMIC_ADPT_VOLT_1_3 = 1300000,
+ PMIC_ADPT_VOLT_1_4 = 1400000,
+ PMIC_ADPT_VOLT_1_5 = 1500000,
+ PMIC_ADPT_VOLT_1_6 = 1600000,
+ PMIC_ADPT_VOLT_1_7 = 1700000,
+ PMIC_ADPT_VOLT_1_8 = 1800000,
+ PMIC_ADPT_VOLT_1_9 = 1900000,
+ PMIC_ADPT_VOLT_2_0 = 2000000,
+ PMIC_ADPT_VOLT_2_1 = 2100000,
+ PMIC_ADPT_VOLT_2_2 = 2200000,
+ PMIC_ADPT_VOLT_2_3 = 2300000,
+ PMIC_ADPT_VOLT_2_4 = 2400000,
+ PMIC_ADPT_VOLT_2_5 = 2500000,
+ PMIC_ADPT_VOLT_2_6 = 2600000,
+ PMIC_ADPT_VOLT_2_7 = 2700000,
+ PMIC_ADPT_VOLT_2_8 = 2800000,
+ PMIC_ADPT_VOLT_2_9 = 2900000,
+ PMIC_ADPT_VOLT_3_0 = 3000000,
+ PMIC_ADPT_VOLT_3_1 = 3100000,
+ PMIC_ADPT_VOLT_3_2 = 3200000,
+ PMIC_ADPT_VOLT_3_3 = 3300000,
+ PMIC_ADPT_VOLT_3_4 = 3400000,
+ PMIC_ADPT_VOLT_3_5 = 3500000,
+ PMIC_ADPT_VOLT_3_6 = 3600000,
+ PMIC_ADPT_VOLT_3_7 = 3700000,
+ PMIC_ADPT_VOLT_3_8 = 3800000,
+ PMIC_ADPT_VOLT_3_9 = 3900000,
+ PMIC_ADPT_VOLT_4_0 = 4000000,
+ PMIC_ADPT_VOLT_4_1 = 4100000,
+ PMIC_ADPT_VOLT_4_2 = 4200000,
+ PMIC_ADPT_VOLT_4_3 = 4300000,
+ PMIC_ADPT_VOLT_4_4 = 4400000,
+ PMIC_ADPT_VOLT_4_5 = 4500000,
+ PMIC_ADPT_VOLT_4_6 = 4600000,
+ PMIC_ADPT_VOLT_4_7 = 4700000,
+ PMIC_ADPT_VOLT_4_8 = 4800000,
+ PMIC_ADPT_VOLT_4_9 = 4900000,
+ PMIC_ADPT_VOLT_5_0 = 5000000,
+ PMIC_ADPT_VOLT_5_1 = 5100000,
+ PMIC_ADPT_VOLT_5_2 = 5200000,
+ PMIC_ADPT_VOLT_5_3 = 5300000,
+ PMIC_ADPT_VOLT_5_4 = 5400000,
+ PMIC_ADPT_VOLT_5_5 = 5500000,
+ PMIC_ADPT_VOLT_5_6 = 5600000,
+ PMIC_ADPT_VOLT_5_7 = 5700000,
+ PMIC_ADPT_VOLT_5_8 = 5800000,
+ PMIC_ADPT_VOLT_5_9 = 5900000,
+ PMIC_ADPT_VOLT_6_0 = 6000000,
+ PMIC_ADPT_VOLT_6_1 = 6100000,
+ PMIC_ADPT_VOLT_6_2 = 6200000,
+ PMIC_ADPT_VOLT_6_3 = 6300000,
+ PMIC_ADPT_VOLT_6_4 = 6400000,
+ PMIC_ADPT_VOLT_6_5 = 6500000,
+ PMIC_ADPT_VOLT_6_6 = 6600000,
+ PMIC_ADPT_VOLT_6_7 = 6700000,
+ PMIC_ADPT_VOLT_6_8 = 6800000,
+ PMIC_ADPT_VOLT_6_9 = 6900000,
+ PMIC_ADPT_VOLT_7_0 = 7000000,
+ PMIC_ADPT_VOLT_7_1 = 7100000,
+ PMIC_ADPT_VOLT_7_2 = 7200000,
+ PMIC_ADPT_VOLT_7_3 = 7300000,
+ PMIC_ADPT_VOLT_7_4 = 7400000,
+ PMIC_ADPT_VOLT_7_5 = 7500000,
+ PMIC_ADPT_VOLT_7_6 = 7600000,
+ PMIC_ADPT_VOLT_7_7 = 7700000,
+ PMIC_ADPT_VOLT_7_8 = 7800000,
+ PMIC_ADPT_VOLT_7_9 = 7900000,
+ PMIC_ADPT_VOLT_8_0 = 8000000,
+
+ PMIC_ADPT_VOLT_MAX = 50000000
+
+}pmic_adpt_voltage_enum;
+
+
+// Unified PMIC speaker volume data type
+typedef enum
+{
+ PMIC_ADPT_SPK_VOL_00_00_dB = 0,
+ PMIC_ADPT_SPK_VOL_00_50_dB = 50,
+ PMIC_ADPT_SPK_VOL_01_00_dB = 100,
+ PMIC_ADPT_SPK_VOL_01_50_dB = 150,
+ PMIC_ADPT_SPK_VOL_02_00_dB = 200,
+ PMIC_ADPT_SPK_VOL_02_50_dB = 250,
+ PMIC_ADPT_SPK_VOL_03_00_dB = 300,
+ PMIC_ADPT_SPK_VOL_03_50_dB = 350,
+ PMIC_ADPT_SPK_VOL_04_00_dB = 400,
+ PMIC_ADPT_SPK_VOL_04_50_dB = 450,
+ PMIC_ADPT_SPK_VOL_05_00_dB = 500,
+ PMIC_ADPT_SPK_VOL_05_50_dB = 550,
+ PMIC_ADPT_SPK_VOL_06_00_dB = 600,
+ PMIC_ADPT_SPK_VOL_06_50_dB = 650,
+ PMIC_ADPT_SPK_VOL_07_00_dB = 700,
+ PMIC_ADPT_SPK_VOL_07_50_dB = 750,
+ PMIC_ADPT_SPK_VOL_08_00_dB = 800,
+ PMIC_ADPT_SPK_VOL_08_50_dB = 850,
+ PMIC_ADPT_SPK_VOL_09_00_dB = 900,
+ PMIC_ADPT_SPK_VOL_09_50_dB = 950,
+ PMIC_ADPT_SPK_VOL_10_00_dB = 1000,
+ PMIC_ADPT_SPK_VOL_10_50_dB = 1050,
+ PMIC_ADPT_SPK_VOL_11_00_dB = 1100,
+ PMIC_ADPT_SPK_VOL_11_50_dB = 1150,
+ PMIC_ADPT_SPK_VOL_12_00_dB = 1200,
+ PMIC_ADPT_SPK_VOL_12_50_dB = 1250,
+ PMIC_ADPT_SPK_VOL_13_00_dB = 1300,
+ PMIC_ADPT_SPK_VOL_13_50_dB = 1350,
+ PMIC_ADPT_SPK_VOL_14_00_dB = 1400,
+ PMIC_ADPT_SPK_VOL_14_50_dB = 1450,
+ PMIC_ADPT_SPK_VOL_15_00_dB = 1500,
+ PMIC_ADPT_SPK_VOL_15_50_dB = 1550,
+ PMIC_ADPT_SPK_VOL_16_00_dB = 1600,
+ PMIC_ADPT_SPK_VOL_16_50_dB = 1650,
+ PMIC_ADPT_SPK_VOL_17_00_dB = 1700,
+ PMIC_ADPT_SPK_VOL_17_50_dB = 1750,
+ PMIC_ADPT_SPK_VOL_18_00_dB = 1800,
+ PMIC_ADPT_SPK_VOL_18_50_dB = 1850,
+ PMIC_ADPT_SPK_VOL_19_00_dB = 1900,
+ PMIC_ADPT_SPK_VOL_19_50_dB = 1950,
+ PMIC_ADPT_SPK_VOL_20_00_dB = 2000,
+ PMIC_ADPT_SPK_VOL_20_50_dB = 2050,
+ PMIC_ADPT_SPK_VOL_21_00_dB = 2100,
+ PMIC_ADPT_SPK_VOL_21_50_dB = 2150,
+ PMIC_ADPT_SPK_VOL_22_00_dB = 2200,
+ PMIC_ADPT_SPK_VOL_22_50_dB = 2250,
+ PMIC_ADPT_SPK_VOL_23_00_dB = 2300,
+ PMIC_ADPT_SPK_VOL_23_50_dB = 2350,
+ PMIC_ADPT_SPK_VOL_24_00_dB = 2400,
+ PMIC_ADPT_SPK_VOL_24_50_dB = 2450,
+
+
+ PMIC_ADPT_SPK_VOL_0_dB = 0,
+ PMIC_ADPT_SPK_VOL_1_dB = 100,
+ PMIC_ADPT_SPK_VOL_2_dB = 200,
+ PMIC_ADPT_SPK_VOL_3_dB = 300,
+ PMIC_ADPT_SPK_VOL_4_dB = 400,
+ PMIC_ADPT_SPK_VOL_5_dB = 500,
+ PMIC_ADPT_SPK_VOL_6_dB = 600,
+ PMIC_ADPT_SPK_VOL_7_dB = 700,
+ PMIC_ADPT_SPK_VOL_8_dB = 800,
+ PMIC_ADPT_SPK_VOL_9_dB = 900,
+ PMIC_ADPT_SPK_VOL_10_dB = 1000,
+ PMIC_ADPT_SPK_VOL_11_dB = 1100,
+ PMIC_ADPT_SPK_VOL_12_dB = 1200,
+ PMIC_ADPT_SPK_VOL_13_dB = 1300,
+ PMIC_ADPT_SPK_VOL_14_dB = 1400,
+ PMIC_ADPT_SPK_VOL_15_dB = 1500,
+ PMIC_ADPT_SPK_VOL_16_dB = 1600,
+ PMIC_ADPT_SPK_VOL_17_dB = 1700,
+ PMIC_ADPT_SPK_VOL_18_dB = 1800,
+ PMIC_ADPT_SPK_VOL_19_dB = 1900,
+ PMIC_ADPT_SPK_VOL_20_dB = 2000,
+ PMIC_ADPT_SPK_VOL_21_dB = 2100,
+ PMIC_ADPT_SPK_VOL_22_dB = 2200,
+ PMIC_ADPT_SPK_VOL_23_dB = 2300,
+ PMIC_ADPT_SPK_VOL_24_dB = 2400,
+
+ PMIC_ADPT_SPK_VOL_MAX = 9900
+}pmic_adpt_spk_vol_enum;
+
+#endif //#define PMIC_OLD_STRUCTURE
+
+typedef enum
+{
+ AC_CHR_CALLBACK=0,
+ USB_CHR_CALLBACK
+}chr_callback_type;
+
+typedef struct
+{
+ void (*pmic_ac_det)(void);
+ void (*pmic_usb_det)(void);
+}pmic6326_chrdect_callbac_struct;
+
+
+
+// TTTTTTTTTTTTTTTTT
+// Implemented functions
+
+
+
+// (0x0D) INT STATUS 3 (RO)
+typedef enum
+{
+ VSDIO_OC_STAT = 0x01, // BIT0
+ VGP_OC_STAT = 0x02, // BIT1
+ VUSB_OC_STAT = 0x04, // BIT2
+ OVP_INT_STAT = 0x08, // BIT3
+ CHRDET_INT_STAT = 0x10, // BIT4
+ PWRKEY_INT_STAT = 0x20 // BIT5
+}int_state_3_enum;
+
+
+// (0x1B) LDO CTRL 2 VRF
+typedef enum
+{
+ VRF_BIAS_CURRENT_TIMES_1_0 = 0,
+ VRF_BIAS_CURRENT_TIMES_0_5,
+ VRF_BIAS_CURRENT_TIMES_2_0,
+ VRF_BIAS_CURRENT_TIMES_3_0
+}vrf_ical_en_enum;
+
+// (0x1C) LDO CTRL 3 VRF
+typedef enum
+{
+ VRF_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
+ VRF_MAX_SLEW_RATE_TIMES_1_OVER_21,
+ VRF_MAX_SLEW_RATE,
+ VRF_MAX_SLEW_RATE_TIMES_1_OVER_5
+}vrf_calst_enum;
+typedef enum
+{
+ VRF_OC_THRESHOLD_685MA = 0,
+ VRF_OC_THRESHOLD_635MA,
+ VRF_OC_THRESHOLD_785MA,
+ VRF_OC_THRESHOLD_735MA
+}vrf_caloc_enum;
+
+typedef enum
+{
+ VRF_DEFAULT_MILLER_CAPACITOR = 0,
+ VRF_INCREASE_MILLER_CAPACITOR
+}vrf_cm_enum;
+
+typedef enum
+{
+ VRF_ENABLE_WITH_SRCLKEN = 0,
+ VRF_ENABLE_WITH_VRF_EN
+}vrf_on_sel_enum;
+
+
+// (0x1E) LDO CTRL 5 VTCXO
+typedef enum
+{
+ VTCXO_BIAS_CURRENT_TIMES_1_0 = 0,
+ VTCXO_BIAS_CURRENT_TIMES_0_5,
+ VTCXO_BIAS_CURRENT_TIMES_2_0,
+ VTCXO_BIAS_CURRENT_TIMES_3_0
+}vtcxo_ical_en_enum;
+
+
+// (0x1F) LDO CTRL 6 VTCXO
+typedef enum
+{
+ VTCXO_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
+ VTCXO_MAX_SLEW_RATE_TIMES_1_OVER_21,
+ VTCXO_MAX_SLEW_RATE,
+ VTCXO_MAX_SLEW_RATE_TIMES_1_OVER_5
+}vtcxo_calst_enum;
+typedef enum
+{
+ VTCXO_OC_THRESHOLD_100MA = 0,
+ VTCXO_OC_THRESHOLD_109MA,
+ VTCXO_OC_THRESHOLD_82MA,
+ VTCXO_OC_THRESHOLD_91MA
+}vtcxo_caloc_enum;
+
+typedef enum
+{
+ VTCXO_ENABLE_WITH_SRCLKEN = 0,
+ VTCXO_ENABLE_WITH_VTCXO_EN
+}vtcxo_on_sel_enum;
+
+typedef enum
+{
+ VTCXO_DEFAULT_MILLER_CAPACITOR = 0,
+ VTCXO_INCREASE_MILLER_CAPACITOR
+}vtcxo_cm_enum;
+
+// (0x21) LDO CTRL 8 V3GTX
+typedef enum
+{
+ V3GTX_BIAS_CURRENT_TIMES_1_0 = 0,
+ V3GTX_BIAS_CURRENT_TIMES_0_5,
+ V3GTX_BIAS_CURRENT_TIMES_2_0,
+ V3GTX_BIAS_CURRENT_TIMES_3_0
+}v3gtx_ical_en_enum;
+
+typedef enum
+{
+ V3GTX_2_8=0,
+ V3GTX_3_0,
+ V3GTX_3_3,
+ V3GTX_2_5
+}v3gtx_vol;
+
+
+// (0x22) LDO CTRL 9 V3GTX
+typedef enum
+{
+ V3GTX_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
+ V3GTX_MAX_SLEW_RATE_TIMES_1_OVER_21,
+ V3GTX_MAX_SLEW_RATE,
+ V3GTX_MAX_SLEW_RATE_TIMES_1_OVER_5
+}v3gtx_calst_enum;
+
+typedef enum
+{
+ V3GTX_OC_THRESHOLD_400MA = 0,
+ V3GTX_OC_THRESHOLD_438MA,
+ V3GTX_OC_THRESHOLD_324MA,
+ V3GTX_OC_THRESHOLD_362MA
+}v3gtx_caloc_enum;
+
+typedef enum
+{
+ V3GTX_ENABLE_WITH_SRCLKEN = 0,
+ V3GTX_ENABLE_WITH_V3GTX_EN
+}v3gtx_on_sel_enum;
+
+
+// (0x24) LDO CTRL 11 V3GRX
+typedef enum
+{
+ V3GRX_2_8=0,
+ V3GRX_3_0,
+ V3GRX_3_3,
+ V3GRX_2_5
+}v3grx_vol;
+
+typedef enum
+{
+ V3GRX_BIAS_CURRENT_TIMES_1_0 = 0,
+ V3GRX_BIAS_CURRENT_TIMES_0_5,
+ V3GRX_BIAS_CURRENT_TIMES_2_0,
+ V3GRX_BIAS_CURRENT_TIMES_3_0
+}v3grx_ical_en_enum;
+
+
+// (0x25) LDO CTRL 12 V3GRX
+typedef enum
+{
+ V3GRX_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
+ V3GRX_MAX_SLEW_RATE_TIMES_1_OVER_21,
+ V3GRX_MAX_SLEW_RATE,
+ V3GRX_MAX_SLEW_RATE_TIMES_1_OVER_5
+}v3grx_calst_enum;
+
+typedef enum
+{
+ V3GRX_OC_THRESHOLD_200MA = 0,
+ V3GRX_OC_THRESHOLD_219MA,
+ V3GRX_OC_THRESHOLD_162MA,
+ V3GRX_OC_THRESHOLD_181MA
+}v3grx_caloc_enum;
+
+
+typedef enum
+{
+ V3GRX_ENABLE_WITH_SRCLKEN = 0,
+ V3GRX_ENABLE_WITH_V3GRX_EN
+}v3grx_on_sel_enum;
+
+
+// (0x2E) LDO CTRL 21 VCAMA
+typedef enum
+{
+ VCAMA_2_8 = 0,
+ VCAMA_2_5,
+ VCAMA_1_8,
+ VCAMA_1_5
+}vcama_sel_enum;
+typedef enum
+{
+ VCAMA_BIAS_CURRENT_X_1_0 = 0,
+ VCAMA_BIAS_CURRENT_X_0_5,
+ VCAMA_BIAS_CURRENT_X_2_0,
+ VCAMA_BIAS_CURRENT_X_3_0
+}vcama_ical_en_enum;
+
+// (0x2F) LDO CTRL 22 VCAMA
+typedef enum
+{
+ VCAMA_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
+ VCAMA_MAX_SLEW_RATE_TIMES_1_OVER_21,
+ VCAMA_MAX_SLEW_RATE,
+ VCAMA_MAX_SLEW_RATE_TIMES_1_OVER_5
+}vcama_calst_enum;
+typedef enum
+{
+ VCAMA_OC_THRESHOLD_500MA = 0,
+ VCAMA_OC_THRESHOLD_548MA,
+ VCAMA_OC_THRESHOLD_405MA,
+ VCAMA_OC_THRESHOLD_452MA
+}vcama_caloc_enum;
+
+typedef enum
+{
+ VCAMA_DEFAULT_MILLER_CAPACITOR = 0,
+ VCAMA_INCREASE_MILLER_CAPACITOR
+}vcama_cm_enum;
+
+// (0x31) LDO CTRL 24 VWIFI3V3
+typedef enum
+{
+ VWIFI3V3_2_8 = 0,
+ VWIFI3V3_3_0,
+ VWIFI3V3_3_3,
+ VWIFI3V3_2_5
+}vwifi3v3_sel_enum;
+typedef enum
+{
+ VWIFI3V3_BIAS_CURRENT_X_1_0 = 0,
+ VWIFI3V3_BIAS_CURRENT_X_0_5,
+ VWIFI3V3_BIAS_CURRENT_X_2_0,
+ VWIFI3V3_BIAS_CURRENT_X_3_0
+}vwifi3v3_ical_en_enum;
+
+// (0x32) LDO CTRL 25 VWIFI3V3
+typedef enum
+{
+ VWIFI3V3_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
+ VWIFI3V3_MAX_SLEW_RATE_TIMES_1_OVER_21,
+ VWIFI3V3_MAX_SLEW_RATE,
+ VWIFI3V3_MAX_SLEW_RATE_TIMES_1_OVER_5
+}vwifi3v3_calst_enum;
+typedef enum
+{
+ VWIFI3V3_OC_THRESHOLD_600MA = 0,
+ VWIFI3V3_OC_THRESHOLD_657MA,
+ VWIFI3V3_OC_THRESHOLD_486MA,
+ VWIFI3V3_OC_THRESHOLD_543MA
+}vwifi3v3_caloc_enum;
+
+typedef enum
+{
+ VWIFI3V3_DEFAULT_MILLER_CAPACITOR = 0,
+ VWIFI3V3_INCREASE_MILLER_CAPACITOR
+}vwifi3v3_cm_enum;
+
+// (0x34) LDO CTRL 27 VWIFI2V8
+typedef enum
+{
+ VWIFI2V8_2_8 = 0,
+ VWIFI2V8_3_0,
+ VWIFI2V8_3_3,
+ VWIFI2V8_2_5
+}vwifi2v8_sel_enum;
+typedef enum
+{
+ VWIFI2V8_BIAS_CURRENT_X_1_0 = 0,
+ VWIFI2V8_BIAS_CURRENT_X_0_5,
+ VWIFI2V8_BIAS_CURRENT_X_2_0,
+ VWIFI2V8_BIAS_CURRENT_X_3_0
+}vwifi2v8_ical_en_enum;
+
+// (0x35) LDO CTRL 28 VWIFI2V8
+typedef enum
+{
+ VWIFI2V8_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
+ VWIFI2V8_MAX_SLEW_RATE_TIMES_1_OVER_21,
+ VWIFI2V8_MAX_SLEW_RATE,
+ VWIFI2V8_MAX_SLEW_RATE_TIMES_1_OVER_5
+}vwifi2v8_calst_enum;
+typedef enum
+{
+ VWIFI2V8_OC_THRESHOLD_300MA = 0,
+ VWIFI2V8_OC_THRESHOLD_329MA,
+ VWIFI2V8_OC_THRESHOLD_243MA,
+ VWIFI2V8_OC_THRESHOLD_271MA
+}vwifi2v8_caloc_enum;
+
+typedef enum
+{
+ VWIFI2V8_DEFAULT_MILLER_CAPACITOR = 0,
+ VWIFI2V8_INCREASE_MILLER_CAPACITOR
+}vwifi2v8_cm_enum;
+
+// (0x37) LDO CTRL 30 VSIM
+typedef enum
+{
+ VSIM_1_3V = 0,
+ VSIM_1_5V,
+ VSIM_1_8V,
+ VSIM_2_5V,
+ VSIM_2_8V,
+ VSIM_3_0V,
+ VSIM_3_3V,
+ VSIM_1_2V
+}vsim_sel_enum;
+typedef enum
+{
+ VSIM_BIAS_CURRENT_X_1_0 = 0,
+ VSIM_BIAS_CURRENT_X_0_5,
+ VSIM_BIAS_CURRENT_X_2_0,
+ VSIM_BIAS_CURRENT_X_3_0
+}vsim_ical_en_enum;
+
+// (0x3A) LDO CTRL 33 VUSB
+typedef enum
+{
+ VUSB_1_3 = 0,
+ VUSB_1_5,
+ VUSB_1_8,
+ VUSB_2_5,
+ VUSB_2_8,
+ VUSB_3_0,
+ VUSB_3_3,
+ VUSB_1_2 // TTTTTTTTTTTTTT
+}vusb_sel_enum;
+typedef enum
+{
+ VUSB_BIAS_CURRENT_X_1_0 = 0,
+ VUSB_BIAS_CURRENT_X_0_5,
+ VUSB_BIAS_CURRENT_X_2_0,
+ VUSB_BIAS_CURRENT_X_3_0
+}vusb_ical_en_enum;
+
+// (0x3B) LDO CTRL 34 VUSB
+typedef enum
+{
+ VUSB_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
+ VUSB_MAX_SLEW_RATE_TIMES_1_OVER_21,
+ VUSB_MAX_SLEW_RATE,
+ VUSB_MAX_SLEW_RATE_TIMES_1_OVER_5
+}vusb_calst_enum;
+typedef enum
+{
+ VUSB_OC_THRESHOLD_200MA = 0,
+ VUSB_OC_THRESHOLD_218MA,
+ VUSB_OC_THRESHOLD_164MA,
+ VUSB_OC_THRESHOLD_182MA
+}vusb_caloc_enum;
+
+// (0x3D) LDO CTRL 36 VBT
+typedef enum
+{
+ VBT_1_3 = 0,
+ VBT_1_5,
+ VBT_1_8,
+ VBT_2_5,
+ VBT_2_8,
+ VBT_3_0,
+ VBT_3_3,
+ VBT_1_2 // TTTTTTTTTTTTTT
+}vbt_sel_enum;
+
+typedef enum
+{
+ VBT_E3_1_5 = 0,
+ VBT_E3_1_3,
+ VBT_E3_2_5,
+ VBT_E3_1_8,
+ VBT_E3_3_0,
+ VBT_E3_2_8,
+ VBT_E3_3_3
+ //VBT_E3_3_3
+}vbt_e3_sel_enum;
+
+typedef enum
+{
+ VBT_BIAS_CURRENT_X_1_0 = 0,
+ VBT_BIAS_CURRENT_X_0_5,
+ VBT_BIAS_CURRENT_X_2_0,
+ VBT_BIAS_CURRENT_X_3_0
+}vbt_ical_en_enum;
+
+// (0x3E) LDO CTRL 37 VBT
+typedef enum
+{
+ VBT_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
+ VBT_MAX_SLEW_RATE_TIMES_1_OVER_21,
+ VBT_MAX_SLEW_RATE,
+ VBT_MAX_SLEW_RATE_TIMES_1_OVER_5
+}vbt_calst_enum;
+typedef enum
+{
+ VBT_OC_THRESHOLD_200MA = 0,
+ VBT_OC_THRESHOLD_218MA,
+ VBT_OC_THRESHOLD_164MA,
+ VBT_OC_THRESHOLD_182MA
+}vbt_caloc_enum;
+
+// (0x40) LDO CTRL 39 VCAMD
+typedef enum
+{
+ VCAMD_1_3 = 0,
+ VCAMD_1_5,
+ VCAMD_1_8,
+ VCAMD_2_5,
+ VCAMD_2_8,
+ VCAMD_3_0,
+ VCAMD_3_3,
+ VCAMD_1_2 // TTTTTTTTTTTTTT
+}vcamd_sel_enum;
+typedef enum
+{
+ VCAMD_BIAS_CURRENT_X_1_0 = 0,
+ VCAMD_BIAS_CURRENT_X_0_5,
+ VCAMD_BIAS_CURRENT_X_2_0,
+ VCAMD_BIAS_CURRENT_X_3_0
+}vcamd_ical_en_enum;
+
+// (0x41) LDO CTRL 40 VCAMD
+typedef enum
+{
+ VCAMD_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
+ VCAMD_MAX_SLEW_RATE_TIMES_1_OVER_21,
+ VCAMD_MAX_SLEW_RATE,
+ VCAMD_MAX_SLEW_RATE_TIMES_1_OVER_5
+}vcamd_calst_enum;
+typedef enum
+{
+ VCAMD_OC_THRESHOLD_200MA = 0,
+ VCAMD_OC_THRESHOLD_218MA,
+ VCAMD_OC_THRESHOLD_164MA,
+ VCAMD_OC_THRESHOLD_182MA
+}vcamd_caloc_enum;
+
+// (0x43) LDO CTRL 42 VGP
+typedef enum
+{
+ VGP_1_3 = 0,
+ VGP_1_5,
+ VGP_1_8,
+ VGP_2_5,
+ VGP_2_8,
+ VGP_3_0,
+ VGP_3_3
+}vgp_sel_enum;
+
+// (0x46) LDO CTRL 45 VSDIO
+typedef enum
+{
+ VSDIO_BIAS_CURRENT_X_1_0 = 0,
+ VSDIO_BIAS_CURRENT_X_0_5,
+ VSDIO_BIAS_CURRENT_X_2_0,
+ VSDIO_BIAS_CURRENT_X_3_0
+}vsdio_ical_en_enum;
+
+// (0x47) LDO CTRL 46 VSDIO
+typedef enum
+{
+ VSDIO_MAX_SLEW_RATE_TIMES_1_OVER_17 = 0,
+ VSDIO_MAX_SLEW_RATE_TIMES_1_OVER_21,
+ VSDIO_MAX_SLEW_RATE,
+ VSDIO_MAX_SLEW_RATE_TIMES_1_OVER_5
+}vsdio_calst_enum;
+typedef enum
+{
+ VSDIO_OC_THRESHOLD_700MA = 0,
+ VSDIO_OC_THRESHOLD_767MA,
+ VSDIO_OC_THRESHOLD_567MA,
+ VSDIO_OC_THRESHOLD_633MA
+}vsdio_caloc_enum;
+typedef enum
+{
+ VSDIO_2_8 = 0,
+ VSDIO_3_0
+}vsdio_sel_enum;
+typedef enum
+{
+ VSDIO_DEFAULT_MILLER_CAPACITOR = 0,
+ VSDIO_INCREASE_MILLER_CAPACITOR
+}vsdio_cm_enum;
+
+
+// (0x53) BUCK CTRL 11 VCORE2
+typedef enum
+{
+ VCORE2_ENABLE_WITH_EN_PASS = 0,
+ VCORE2_ENABLE_WITH_VCORE2_EN
+}vcore2_on_sel_enum;
+
+// (0x5C) BOOST CTRL 1 BOOST1
+typedef enum
+{
+ VBOOST1_VOL_3_20_V = 0,
+ VBOOST1_VOL_3_35_V,
+ VBOOST1_VOL_3_50_V,
+ VBOOST1_VOL_3_65_V,
+ VBOOST1_VOL_3_80_V,
+ VBOOST1_VOL_3_95_V,
+ VBOOST1_VOL_4_10_V,
+ VBOOST1_VOL_4_25_V,
+ VBOOST1_VOL_4_40_V,
+ VBOOST1_VOL_4_55_V,
+ VBOOST1_VOL_4_70_V,
+ VBOOST1_VOL_4_85_V,
+ VBOOST1_VOL_5_00_V,
+ VBOOST1_VOL_5_15_V,
+ VBOOST1_VOL_5_30_V,
+ VBOOST1_VOL_5_45_V
+}vboost1_tune_enum;
+
+// (0x5D) BOOST CTRL 2 BOOST1
+typedef enum
+{
+ BOOST1_SOFT_START_SPEED = 0,
+ BOOST1_SOFT_START_SPEED_TIMES_2_OVER_3
+}boost1_soft_st_speed_enum;
+
+// (0x5F) BOOST CTRL 4 BOOST2
+typedef enum
+{
+ VBOOST2_VOL_6_00_V = 0,
+ VBOOST2_VOL_6_75_V,
+ VBOOST2_VOL_7_50_V,
+ VBOOST2_VOL_8_25_V,
+ VBOOST2_VOL_9_00_V,
+ VBOOST2_VOL_9_75_V,
+ VBOOST2_VOL_10_05_V,
+ VBOOST2_VOL_11_25_V,
+ VBOOST2_VOL_12_00_V,
+ VBOOST2_VOL_12_75_V,
+ VBOOST2_VOL_13_50_V,
+ VBOOST2_VOL_14_25_V,
+ VBOOST2_VOL_15_00_V,
+ VBOOST2_VOL_15_75_V,
+ VBOOST2_VOL_16_50_V,
+ VBOOST2_VOL_17_25_V
+}vboost2_tune_enum;
+
+typedef enum
+{
+ BOOST2_OC_THRESHOLD_5UA = 0,
+ BOOST2_OC_THRESHOLD_2UA,
+ BOOST2_OC_THRESHOLD_10UA,
+ BOOST2_OC_THRESHOLD_7UA
+}boost2_oc_th_enum;
+
+typedef enum
+{
+ BOOST2_DIGITAL_DIMING = 0,
+ BOOST2_ANALOG_DIMING
+}boost2_dim_source_enum;
+
+// (0x61) BOOST CTRL 6 BOOST2 and BOOST
+typedef enum
+{
+ BOOST_MODE_TYPE_I = 0,
+ BOOST_MODE_TYPE_II,
+ BOOST_MODE_TYPE_III,
+ BOOST_MODE_TYPE_IV
+}boost_mode_sel_enum;
+
+// (0x65) DRIVER CTRL 4 FLASH
+//typedef enum
+//{
+// FLASH_CURRENT_0MA=0,
+// FLASH_CURRENT_50MA,
+// FLASH_CURRENT_100MA,
+// FLASH_CURRENT_150MA,
+// FLASH_CURRENT_200MA,
+// FLASH_CURRENT_250MA,
+// FLASH_CURRENT_300MA,
+// FLASH_CURRENT_350MA,
+// FLASH_CURRENT_400MA,
+// FLASH_CURRENT_450MA,
+// FLASH_CURRENT_500MA,
+// FLASH_CURRENT_550MA
+//}flash_i_tune_enum;
+
+// (0x68) DRIVER CTRL 7 BL
+typedef enum
+{
+ BL_I_CORSE_TUNE_4MA = 0,
+ BL_I_CORSE_TUNE_8MA,
+ BL_I_CORSE_TUNE_12MA,
+ BL_I_CORSE_TUNE_16MA,
+ BL_I_CORSE_TUNE_20MA,
+ BL_I_CORSE_TUNE_24MA,
+ BL_I_CORSE_TUNE_28MA,
+ BL_I_CORSE_TUNE_32MA
+}bl_i_corse_tune_enum;
+
+typedef enum
+{
+ BL_I_FINE_TUNE_0MA = 0,
+ BL_I_FINE_TUNE_MINUS_1MA,
+ BL_I_FINE_TUNE_MINUS_2MA,
+ BL_I_FINE_TUNE_MINUS_3MA,
+ BL_I_FINE_TUNE_PLUS_4MA,
+ BL_I_FINE_TUNE_PLUS_3MA,
+ BL_I_FINE_TUNE_PLUS_2MA,
+ BL_I_FINE_TUNE_PLUS_1MA
+}bl_i_fine_tune_enum;
+
+// (0x6D) DRIVER CTRL 12 BL
+typedef enum
+{
+ BL_NUM_1 = 0,
+ BL_NUM_2,
+ BL_NUM_3,
+ BL_NUM_4,
+ BL_NUM_5,
+ BL_NUM_6,
+ BL_NUM_7,
+ BL_NUM_8
+}bl_number_enum;
+
+// (0x74) CLASS_D CTRL 4 SPKL
+typedef enum
+{
+ SPKL_FB_FORCED_DTIN_DTIP = 0,
+ SPKL_FF_FORCED_DTIN_DTIP,
+ SPKL_FB_AUTO_CAL_DTCN_DTCP,
+ SPKL_FF_AUTO_CAL_DTCN_DTCP
+}spkl_dmode_enum;
+
+typedef enum
+{
+ SPKL_DTCAL_ENABLE_CLASS_D_R_READ_TIME_CAL = 0,
+ SPKL_DTCAL_DISABLE_CLASS_D_R_READ_TIME_CAL
+}spkl_dtcal_enum;
+
+// (0x75) CLASS_D CATRL 5 SPKL
+typedef enum
+{
+ SPKL_2_4_BUFFER = 0,
+ SPKL_1_4_BUFFER = 1,
+ SPKL_4_4_BUFFER = 2,
+ SPKL_3_4_BUFFER = 3
+}spkl_slew_enum;
+
+
+// (0x76) CLASS_D CTRL 6 SPKL
+typedef enum
+{
+ SPKL_VOL_6DB = 0,
+ SPKL_VOL_9DB = 1,
+ SPKL_VOL_12DB = 2,
+ SPKL_VOL_15DB = 3,
+ SPKL_VOL_18DB = 4,
+ SPKL_VOL_21DB = 5,
+ SPKL_VOL_24DB = 6,
+ SPKL_VOL_27DB = 7
+}spkl_vol_enum;
+
+
+// (0x77) CLASS_D CTRL 7 SPKL
+typedef enum
+{
+ SPKL_OC_DISABLE = 0,
+ SPKL_OC_ENABLE = 1
+}spkl_oc_enum;
+
+
+
+// (0x79) CLASS_D CTRL 9 SPKR
+typedef enum
+{
+ SPKR_FB_FORCED_DTIN_DTIP = 0,
+ SPKR_FF_FORCED_DTIN_DTIP,
+ SPKR_FB_AUTO_CAL_DTCN_DTCP,
+ SPKR_FF_AUTO_CAL_DTCN_DTCP
+}spkr_dmode_enum;
+
+typedef enum
+{
+ SPKR_DTCAL_ENABLE_CLASS_D_R_READ_TIME_CAL = 0,
+ SPKR_DTCAL_DISABLE_CLASS_D_R_READ_TIME_CAL
+}spkr_dtcal_enum;
+
+// (0x7A) CLASS_D CTRL 10 SPKR
+typedef enum
+{
+ SPKR_2_4_BUFFER = 0,
+ SPKR_1_4_BUFFER = 1,
+ SPKR_4_4_BUFFER = 2,
+ SPKR_3_4_BUFFER = 3
+}spkr_slew_enum;
+
+
+
+// (0x7B) CLASS_D CTRL 11 SPKR
+
+typedef enum
+{
+ SPKR_VOL_6DB = 0,
+ SPKR_VOL_9DB = 1,
+ SPKR_VOL_12DB = 2,
+ SPKR_VOL_15DB = 3,
+ SPKR_VOL_18DB = 4,
+ SPKR_VOL_21DB = 5,
+ SPKR_VOL_24DB = 6,
+ SPKR_VOL_27DB = 7
+}spkr_vol_enum;
+
+// (0x7C) CLASS_D CTRL 12 SPKL Overcurrent setting
+typedef enum
+{
+ SPKR_OC_DISABLE = 0,
+ SPKR_OC_ENABLE = 1
+}spkr_oc_enum;
+
+
+
+// (0x81) CHARGER CTRL 1
+typedef enum
+{
+ CHR_CURRENT_OFFSET_NO = 0,
+ CHR_CURRENT_OFFSET_PLUS_1_STEP = 1,
+ CHR_CURRENT_OFFSET_PLUS_2_STEP = 2,
+ CHR_CURRENT_OFFSET_MINUS_2_STEP = 6,
+ CHR_CURRENT_OFFSET_MINUS_1_STEP = 7
+}cht_chr_offset_enum;
+
+typedef enum
+{
+ CHR_CURRENT_50MA = 0,
+ CHR_CURRENT_90MA,
+ CHR_CURRENT_150MA,
+ CHR_CURRENT_225MA,
+ CHR_CURRENT_300MA,
+ CHR_CURRENT_450MA,
+ CHR_CURRENT_650MA,
+ CHR_CURRENT_800MA
+}chr_chr_current_enum;
+
+// (0x83) TESTMODE CTRL 3 Analog Switch
+//typedef enum
+//{
+// ASW_ASEL_ASW_2_SETS = 0,
+// ASW_ASEL_SIMLS,
+// ASW_ASEL_ASW_1_SET,
+// ASW_ASEL_BL_CURRENT_SOURCE
+//}asw_asel_enum;
+typedef enum
+{
+ ASW_ASEL_ISINK_6_8_AS = 0, // ISINK 6~8 used as Analog Switch, others for BL
+ ASW_ASEL_ALL_ISINK_BL = 3 // All ISINK used for BL
+}asw_asel_enum;
+
+
+typedef enum
+{
+ HI_Z = 0,
+ RECEIVER,
+ TWO_OF_RGB_DRIVER
+ // TODO, the last item value
+}asw_bsel_enum;
+
+// (0x84) TESTMODE CTRL 4 Testmode
+typedef enum
+{
+ VGP2_ENABLE_WITH_SRCLKEN = 0,
+ VGP2_ENABLE_WITH_VGP2_EN
+}vgp2_on_sel_enum;
+
+
+// (0x89) INT CTRL 1
+typedef enum
+{
+ INT_EN_VCORE2_OC = 0x01,
+ INT_EN_VPA_OC = 0x02,
+ INT_EN_BOOST1_OC = 0x04,
+ INT_EN_BOOST2_OC = 0x08,
+ INT_EN_SPKL_OC = 0x10,
+ INT_EN_SPKR_OC = 0x20,
+ INT_EN_V3GTX_OC = 0x40,
+ INT_EN_V3GRX_OC = 0x80,
+ INT_EN_0X89_ALL = 0xFF,
+ INT1_EN_ALL = 0xFF
+}int_ctrl_1_enum;
+
+// (0x8A) INT CTRL 2
+typedef enum
+{
+ INT_EN_RF_OC = 0x01,
+ INT_EN_VTCXO_OC = 0x02,
+ INT_EN_VCAMA_OC = 0x04,
+ INT_EN_VWIFI3V3_OC = 0x08,
+ INT_EN_VWIFI2V8_OC = 0x10,
+ INT_EN_VSIM_OC = 0x20,
+ INT_EN_VBT_OC = 0x40,
+ INT_EN_VCAMD_OC = 0x80,
+ INT_EN_0X8A_ALL = 0xFF,
+ INT2_EN_ALL = 0xFF
+}int_ctrl_2_enum;
+
+// (0x8B) INT CTRL 3
+typedef enum
+{
+ INT_EN_VSDIO_OC = 0x01,
+ INT_EN_VGP_OC = 0x02,
+ INT_EN_VUSB_OC = 0x04,
+ INT_EN_CHRDET = 0x08,
+ INT_EN_OVP = 0x10,
+ INT_EN_WATCHDOG = 0x20,
+ INT_EN_PWRKEY = 0x40,
+ INT_EN_0X8B_ALL = 0x7F,
+ INT3_EN_ALL = 0x7F
+}int_ctrl_3_enum;
+
+
+// (0x96) WATCHDOG CTRL and INT CTRL 4
+typedef enum
+{
+ WDT_TIMEOUT_4_SEC = 0,
+ WDT_TIMEOUT_8_SEC,
+ WDT_TIMEOUT_16_SEC,
+ WDT_TIMEOUT_32_SEC
+}wdt_timout_enum;
+
+
+// Combinational functions structures
+typedef enum
+{
+ VGP2_1_3 = 0,
+ VGP2_1_5,
+ VGP2_1_8,
+ VGP2_2_5,
+ VGP2_2_8,
+ VGP2_3_0,
+ VGP2_3_3
+}vgp2_sel_enum;
+
+
+typedef enum
+{
+ ST_VWIFI3V3_200US = 0,
+ ST_VWIFI3V3_400US,
+ ST_VWIFI3V3_600US,
+ ST_VWIFI3V3_800US
+}st_gear_vwifi3v3;
+
+typedef enum
+{
+ ST_VWIFI2V8_200US = 0,
+ ST_VWIFI2V8_400US,
+ ST_VWIFI2V8_600US,
+ ST_VWIFI2V8_800US
+}st_gear_vwifi2v8;
+
+typedef enum
+{
+ ST_VSDIO_200US = 0,
+ ST_VSDIO_400US,
+ ST_VSDIO_600US,
+ ST_VSDIO_800US
+}st_gear_vsdio;
+
+typedef enum
+{
+ OC_VWIFI3V3_100US = 0,
+ OC_VWIFI3V3_200US,
+ OC_VWIFI3V3_400US,
+ OC_VWIFI3V3_800US
+}oc_gear_vwifi3v3;
+
+typedef enum
+{
+ OC_VWIFI2V8_100US = 0,
+ OC_VWIFI2V8_200US,
+ OC_VWIFI2V8_400US,
+ OC_VWIFI2V8_800US
+}oc_gear_vwifi2v8;
+
+typedef enum
+{
+ OC_VSDIO_100US = 0,
+ OC_VSDIO_200US,
+ OC_VSDIO_400US,
+ OC_VSDIO_800US
+}oc_gear_vsdio;
+
+
+extern void dcl_pmic6326_ChrDet_Registration(chr_callback_type type, void (*Callback)(void));
+
+// (0x09) STATUS 6 (RO)
+extern kal_bool dcl_pmic6326_boost2_oc_status(void);
+extern kal_bool dcl_pmic6326_spkr_oc_det_status(void);
+extern kal_bool dcl_pmic6326_spkl_oc_det_status(void);
+extern kal_bool dcl_pmic6326_pwrkey_deb_status(void);
+extern kal_bool dcl_pmic6326_ovp_status(void);
+extern kal_bool dcl_pmic6326_chrdet_status(void);
+extern kal_bool dcl_pmic6326_bat_on_status(void);
+extern kal_bool dcl_pmic6326_cv_status(void);
+
+// (0x0B) INT STATUS 1 (RO)
+extern kal_uint8 dcl_pmic6326_int_status_1(void);
+
+// (0x0C) INT STATUS 2 (RO)
+extern kal_uint8 dcl_pmic6326_int_status_2(void);
+
+// (0x0D) INT STATUS 3 (RO)
+extern kal_uint8 dcl_pmic6326_int_status_3(void);
+extern kal_bool dcl_pmic6326_vsdio_oc_int_status(void);
+extern kal_bool dcl_pmic6326_vgp_oc_int_status(void);
+extern kal_bool dcl_pmic6326_vusb_oc_int_status(void);
+extern kal_bool dcl_pmic6326_ovp_int_status(void);
+extern kal_bool dcl_pmic6326_chrdet_int_status(void);
+
+
+// (0x0E) INT STATUS 4 (RO)
+extern kal_uint8 dcl_pmic6326_int_status_4(void);
+extern kal_bool dcl_pmic6326_watchdog_int_status(void);
+extern void dcl_pmic6326_watchdog_clear(void);
+
+// (0x1B) LDO CTRL 2 VRF
+extern void dcl_pmic6326_vrf_ical_en(vrf_ical_en_enum sel);
+extern void dcl_pmic6326_vrf_oc_auto_off(kal_bool auto_off);
+extern void dcl_pmic6326_vrf_enable(kal_bool enable);
+extern void dcl_pmic6326_vrf_cal(kal_uint8 val);
+
+// (0x1C) LDO CTRL 3 VRF
+extern void dcl_pmic6326_vrf_calst(vrf_calst_enum sel);
+extern void dcl_pmic6326_vrf_caloc(vrf_caloc_enum sel);
+extern void dcl_pmic6326_vrf_on_sel(vrf_on_sel_enum sel);
+extern void dcl_pmic6326_vrf_en_force(kal_bool enable);
+extern void dcl_pmic6326_vrf_plnmos_dis(kal_bool disable);
+extern void dcl_pmic6326_vrf_cm(vrf_cm_enum sel);
+
+// (0x1E) LDO CTRL 5 VTCXO
+extern void dcl_pmic6326_vtcxo_ical_en(vtcxo_ical_en_enum sel);
+extern void dcl_pmic6326_vtcxo_oc_auto_off(kal_bool auto_off);
+extern void dcl_pmic6326_vtcxo_enable(kal_bool enable);
+extern void dcl_pmic6326_vtcxo_cal(kal_uint8 val);
+
+// (0x1F) LDO CTRL 6 VTCXO
+extern void dcl_pmic6326_vtcxo_calst(vtcxo_calst_enum sel);
+extern void dcl_pmic6326_vtcxo_caloc(vtcxo_caloc_enum sel);
+extern void dcl_pmic6326_vtcxo_on_sel(vtcxo_on_sel_enum sel);
+extern void dcl_pmic6326_vtcxo_en_force(kal_bool enable);
+extern void dcl_pmic6326_vtcxo_plnmos_dis(kal_bool disable);
+extern void dcl_pmic6326_vtcxo_cm(vtcxo_cm_enum sel);
+
+// (0x21) LDO CTRL 8 V3GTX
+extern void dcl_pmic6326_v3gtx_sel(v3gtx_vol vol);
+extern void dcl_pmic6326_v3gtx_ical_en(v3gtx_ical_en_enum sel);
+extern void dcl_pmic6326_v3gtx_cal(kal_uint8 val);
+
+// (0x22) LDO CTRL 9 V3GTX
+extern void dcl_pmic6326_v3gtx_calst(v3gtx_calst_enum sel);
+extern void dcl_pmic6326_v3gtx_caloc(v3gtx_caloc_enum sel);
+extern void dcl_pmic6326_v3gtx_oc_auto_off(kal_bool auto_off);
+extern void dcl_pmic6326_v3gtx_enable(kal_bool enable);
+extern void dcl_pmic6326_v3gtx_on_sel(v3gtx_on_sel_enum sel);
+extern void dcl_pmic6326_v3gtx_en_force(kal_bool enable);
+
+// (0x24) LDO CTRL 11 V3GRX
+extern void dcl_pmic6326_v3grx_sel(v3grx_vol vol);
+extern void dcl_pmic6326_3grx_ical_en(v3grx_ical_en_enum sel);
+extern void dcl_pmic6326_v3grx_cal(kal_uint8 val);
+
+// (0x25) LDO CTRL 12 V3GRX
+extern void dcl_pmic6326_v3grx_calst(v3grx_calst_enum sel);
+extern void dcl_pmic6326_v3grx_caloc(v3grx_caloc_enum sel);
+extern void dcl_pmic6326_v3grx_oc_auto_off(kal_bool auto_off);
+extern void dcl_pmic6326_v3grx_enable(kal_bool enable);
+extern void dcl_pmic6326_v3grx_on_sel(v3grx_on_sel_enum sel);
+extern void dcl_pmic6326_v3grx_en_force(kal_bool enable);
+
+// (0x2E) LDO CTRL 21 VCAMA
+extern void dcl_pmic6326_vcama_sel(vcama_sel_enum sel);
+extern void dcl_pmic6326_vcama_ical_en(vcama_ical_en_enum sel);
+extern void dcl_pmic6326_vcama_cal(kal_uint8 val);
+
+// (0x2F) LDO CTRL 22 VCAMA
+extern void dcl_pmic6326_vcama_calst(vcama_calst_enum sel);
+extern void dcl_pmic6326_vcama_caloc(vcama_caloc_enum sel);
+extern void dcl_pmic6326_vcama_enable(kal_bool enable);
+extern void dcl_pmic6326_vcama_en_force(kal_bool enable);
+extern void dcl_pmic6326_vcama_plnmos_dis(kal_bool disable);
+extern void dcl_pmic6326_vcama_cm(vcama_cm_enum sel);
+
+// (0x31) LDO CTRL 24 VWIFI3V3
+extern void dcl_pmic6326_vwifi3v3_sel(vwifi3v3_sel_enum sel);
+extern void dcl_pmic6326_vwifi3v3_ical_en(vwifi3v3_ical_en_enum sel);
+extern void dcl_pmic6326_vwifi3v3_cal(kal_uint8 val);
+
+// (0x32) LDO CTRL 25 VWIFI3V3
+extern void dcl_pmic6326_vwifi3v3_calst(vwifi3v3_calst_enum sel);
+extern void dcl_pmic6326_vwifi3v3_caloc(vwifi3v3_caloc_enum sel);
+extern void dcl_pmic6326_vwifi3v3_enable(kal_bool enable);
+extern void dcl_pmic6326_vwifi3v3_en_force(kal_bool enable);
+extern void dcl_pmic6326_vwifi3v3_plnmos_dis(kal_bool disable);
+extern void dcl_pmic6326_vwifi3v3_cm(vwifi3v3_cm_enum sel);
+
+// (0x34) LDO CTRL 27 VWIFI2V8
+extern void dcl_pmic6326_vwifi2v8_sel(vwifi2v8_sel_enum sel);
+extern void dcl_pmic6326_vwifi2v8_ical_en(vwifi2v8_ical_en_enum sel);
+extern void dcl_pmic6326_vwifi2v8_cal(kal_uint8 val);
+
+// (0x35) LDO CTRL 28 VWIFI2V8
+extern void dcl_pmic6326_vwifi2v8_calst(vwifi2v8_calst_enum sel);
+extern void dcl_pmic6326_vwifi2v8_caloc(vwifi2v8_caloc_enum sel);
+extern void dcl_pmic6326_vwifi2v8_enable(kal_bool enable);
+extern void dcl_pmic6326_vwifi2v8_en_force(kal_bool enable);
+extern void dcl_pmic6326_vwifi2v8_plnmos_dis(kal_bool disable);
+extern void dcl_pmic6326_vwifi2v8_cm(vwifi2v8_cm_enum sel);
+
+// (0x37) LDO CTRL 30 VSIM
+//void dcl_pmic6326_vsim_sel(vsim_sel_enum sel);
+extern void pmic6326_vsim_sel(vsim_sel_enum sel);
+extern void pmic6326_vsim_sel(vsim_sel_enum sel);
+extern void dcl_pmic6326_vsim_enable(kal_bool enable);
+extern void dcl_pmic6326_vsim_ical_en(vsim_ical_en_enum sel);
+extern void dcl_pmic6326_vsim_en_force(kal_bool enable);
+extern void dcl_pmic6326_vsim_plnmos_dis(kal_bool disable);
+
+// (0x38) LDO CTRL 31 VSIM
+extern void dcl_pmic6326_vsim_cal(kal_uint8 val);
+
+// (0x3A) LDO CTRL 33 VUSB
+// USB voltage is NOT opened for change
+//extern void dcl_pmic6326_vusb_sel(vusb_sel_enum sel);
+extern void dcl_pmic6326_vusb_enable(kal_bool enable);
+extern void dcl_pmic6326_vusb_ical_en(vusb_ical_en_enum sel);
+extern void dcl_pmic6326_vusb_en_force(kal_bool enable);
+extern void dcl_pmic6326_vusb_plnmos_dis(kal_bool disable);
+
+// (0x3B) LDO CTRL 34 VUSB
+extern void dcl_pmic6326_vusb_cal(kal_uint8 val);
+extern void dcl_pmic6326_vusb_calst(vusb_calst_enum sel);
+extern void dcl_pmic6326_vusb_caloc(vusb_caloc_enum sel);
+
+// (0x3D) LDO CTRL 36 VBT
+extern void dcl_pmic6326_vbt_sel(vbt_sel_enum sel);
+extern void dcl_pmic6326_vbt_enable(kal_bool enable);
+extern void dcl_pmic6326_vbt_ical_en(vbt_ical_en_enum sel);
+extern void dcl_pmic6326_vbt_en_force(kal_bool enable);
+extern void dcl_pmic6326_vbt_plnmos_dis(kal_bool disable);
+
+// (0x3E) LDO CTRL 37 VBT
+extern void dcl_pmic6326_vbt_cal(kal_uint8 val);
+extern void dcl_pmic6326_vbt_calst(vbt_calst_enum sel);
+extern void dcl_pmic6326_vbt_caloc(vbt_caloc_enum sel);
+
+// (0x40) LDO CTRL 39 VCAMD
+extern void dcl_pmic6326_vcamd_sel(vcamd_sel_enum sel);
+extern void dcl_pmic6326_vcamd_enable(kal_bool enable);
+extern void dcl_pmic6326_vcamd_ical_en(vcamd_ical_en_enum sel);
+extern void dcl_pmic6326_vcamd_en_force(kal_bool enable);
+extern void dcl_pmic6326_vcamd_plnmos_dis(kal_bool disable);
+
+// (0x41) LDO CTRL 40 VCAMD
+extern void dcl_pmic6326_vcamd_cal(kal_uint8 val);
+extern void dcl_pmic6326_vcamd_calst(vcamd_calst_enum sel);
+extern void dcl_pmic6326_vcamd_caloc(vcamd_caloc_enum sel);
+
+// (0x43) LDO CTRL 42 VGP
+extern void dcl_pmic6326_vgp_sel(vgp_sel_enum sel);
+extern void dcl_pmic6326_vgp_enable(kal_bool enable);
+
+// (0x44) LDO CTRL 43 VGP
+extern void dcl_pmic6326_vgp_cal(kal_uint8 val);
+
+// (0x46) LDO CTRL 45 VSDIO
+extern void dcl_pmic6326_vsdio_ical_en(vsdio_ical_en_enum sel);
+extern void dcl_pmic6326_vsdio_enable(kal_bool enable);
+extern void dcl_pmic6326_vsdio_en_force(kal_bool enable);
+extern void dcl_pmic6326_vsdio_cal(kal_uint8 val);
+
+// (0x47) LDO CTRL 46 VSDIO
+extern void dcl_pmic6326_vsdio_calst(vsdio_calst_enum sel);
+extern void dcl_pmic6326_vsdio_caloc(vsdio_caloc_enum sel);
+extern void dcl_pmic6326_vsdio_plnmos_dis(kal_bool disable);
+extern void dcl_pmic6326_vsdio_sel(vsdio_sel_enum sel);
+extern void dcl_pmic6326_vsdio_cm(vsdio_cm_enum sel);
+
+// (0x48) LDO CTRL 47 VSDIO
+extern void dcl_pmic6326_vcore1_dvfs_step_inc(kal_uint8 val);
+
+// (0x4E) BUCK CTRL 6 VCORE1
+extern void dcl_pmic6326_vcore1_dvfs_0_eco3(kal_uint8 val);
+
+// (0x4F) BUCK CTRL 7 VCORE1
+extern void dcl_pmic6326_vcore1_sleep_0_eco3(kal_uint8 val);
+extern void dcl_pmic6326_vcore1_dvfs_ramp_enable(kal_bool enable);
+extern void dcl_pmic6326_vcore1_dvfs_target_update(kal_bool update);
+
+// (0x51) BUCK CTRL 9 VCORE2
+extern void dcl_pmic6326_vcore2_dvfs_0_eco3(kal_uint8 val);
+
+
+// (0x52) BUCK CTRL 10 VCORE2
+extern void dcl_pmic6326_vcore2_enable(kal_bool enable);
+extern void dcl_pmic6326_vcore2_sleep_0_eco3(kal_uint8 val);
+
+// (0x53) BUCK CTRL 11 VCORE2
+extern void dcl_pmic6326_vcore2_on_sel(vcore2_on_sel_enum sel);
+
+// (0x54)
+extern void dcl_pmic6326_vcore2_plnmos_dis(kal_bool disable);
+
+
+// (0x57) BUCK CTRL 15 VMEM
+extern void dcl_pmic6326_vcore1_sleep_1_eco3(kal_uint8 val);
+extern void dcl_pmic6326_vcore1_dvfs_1_eco3(kal_uint8 val);
+
+// (0x58) BUCK CTRL 16 VPA
+extern void dcl_pmic6326_vpa_tuneh(kal_uint8 value);
+extern void dcl_pmic6326_vpa_en_force(kal_bool enable);
+extern void dcl_pmic6326_vpa_plnmos_dis(kal_bool disable);
+extern void dcl_pmic6326_vpa_enable(kal_bool enable);
+
+// (0x59) BUCK CTRL 17 VPA
+extern void dcl_pmic6326_vpa_tunel(kal_uint8 value);
+
+// (0x5A) BUCK CTRL 18 VPA
+extern void dcl_pmic6326_vpa_oc_tune(kal_uint8 val);
+extern void dcl_pmic6326_vpa_bat_low(kal_bool bat_low);
+
+// (0x5C) BOOST CTRL 1 BOOST1
+extern void dcl_pmic6326_vboost1_tune(vboost1_tune_enum sel);
+extern void dcl_pmic6326_vboost1_tatt(kal_uint8 val);
+
+// (0x5D) BOOST CTRL 2 BOOST1
+extern void dcl_pmic6326_boost1_oc_th(kal_uint8 val);
+extern void dcl_pmic6326_boost1_enable(kal_bool enable);
+extern void dcl_pmic6326_boost1_pre_sr_con(kal_uint8 val);
+extern void dcl_pmic6326_boost1_soft_st_speed(boost1_soft_st_speed_enum sel);
+
+// (0x5E) BOOST CTRL 3 BOOST1
+extern void dcl_pmic6326_boost1_dio_sr_con(kal_uint8 val);
+extern void dcl_pmic6326_boost1_sync_enable(kal_bool enable);
+
+
+// (0x5F) BOOST CTRL 4 BOOST2
+extern void dcl_pmic6326_boost2_tune(vboost2_tune_enum sel);
+extern void dcl_pmic6326_boots2_oc_th(boost2_oc_th_enum sel);
+extern void dcl_pmic6326_boost2_dim_source(boost2_dim_source_enum sel);
+
+// (0x60) BOOST CTRL 5 BOOST2
+extern void dcl_pmic6326_boost2_pre_sr_con(kal_uint8 val);
+extern void dcl_pmic6326_boost2_enable(kal_bool enable);
+
+// (0x61) BOOST CTRL 6 BOOST2 and BOOST
+extern void dcl_pmic6326_boost_mode(boost_mode_sel_enum sel);
+
+extern void dcl_pmic6326_vbus_enable(kal_bool enable);
+
+// (0x64) DRIVER CTRL 3 GEN
+extern void dcl_pmic6326_igen_drv_isel(kal_uint8 sel);
+extern void dcl_pmic6326_igen_drv_force(kal_bool force);
+extern void dcl_pmic6326_vgen_drv_bgsel(kal_uint8 sel);
+
+// (0x65) DRIVER CTRL 4 FLASH
+extern void dcl_pmic6326_flash_i_tune(kal_uint8 val);
+extern void dcl_pmic6326_flash_dim_div(kal_uint8 val);
+
+// (0x66) DRIVER CTRL 5 FLASH
+extern void dcl_pmic6326_flash_dim_duty(kal_uint8 duty);
+extern void dcl_pmic6326_flash_enable(kal_bool enable);
+extern void dcl_pmic6326_flash_bypass(kal_bool bypass);
+
+// (0x67) DRIVER CTRL 6 BL
+extern void dcl_pmic6326_bl_dim_duty(kal_uint8 duty);
+extern void dcl_pmic6326_bl_enable(kal_bool enable);
+extern void dcl_pmic6326_bl_i_cal_enable(kal_bool enable);
+extern void dcl_pmic6326_bl_bypass(kal_bool bypass);
+
+// (0x68) DRIVER CTRL 7 BL
+extern void dcl_pmic6326_bl_i_corse_tune(bl_i_corse_tune_enum sel);
+extern void dcl_pmic6326_bl_i_fine_tune(bl_i_fine_tune_enum sel);
+
+// (0x6D) DRIVER CTRL 12 BL
+extern void dcl_pmic6326_bl_dim_div(kal_uint8 val);
+extern void dcl_pmic6326_bl_number(bl_number_enum num);
+
+extern void dcl_pmic6326_init_bl(boost_mode_sel_enum boost_mode);
+
+// (0x6E) DRIVER CTRL 13 KP
+extern void dcl_pmic6326_kp_dim_div(kal_uint8 val);
+extern void dcl_pmic6326_kp_enable(kal_bool enable);
+
+// (0x6F) DRIVER CTRL 14 KP
+extern void dcl_pmic6326_kp_dim_duty(kal_uint8 duty);
+
+// (0x70) DRIVER CTRL 15 VIBR
+extern void dcl_pmic6326_vibr_dim_div(kal_uint8 val);
+extern void dcl_pmic6326_vibr_enable(kal_bool enable);
+
+// (0x71) DRIVER CTRL 16 VIBR
+extern void dcl_pmic6326_vibr_dim_duty(kal_uint8 duty);
+
+// (0x72) DRIVER CTRL 17 dim_ck_force_on
+extern void dcl_pmic6326_dim_ck_force_on(kal_bool enable);
+
+// (0x73) CLASS_D CTRL 3 SPKL
+extern void dcl_pmic6326_spkl_dtin(kal_uint8 val);
+extern void dcl_pmic6326_spkl_dtip(kal_uint8 val);
+
+// (0x74) CLASS_D CTRL 4 SPKL
+extern void dcl_pmic6326_spkl_dmode(spkl_dmode_enum sel);
+extern void dcl_pmic6326_spkl_enable(kal_bool enable);
+extern void dcl_pmic6326_spkl_dtcal(spkl_dtcal_enum sel);
+
+// (0x78) CLASS_D CTRL 8 SPKR
+extern void dcl_pmic6326_spkr_dtin(kal_uint8 val);
+extern void dcl_pmic6326_spkr_dtip(kal_uint8 val);
+
+// (0x79) CLASS_D CTRL 9 SPKR
+extern void dcl_pmic6326_spkr_dmode(spkr_dmode_enum sel);
+extern void dcl_pmic6326_spkr_enable(kal_bool enable);
+extern void dcl_pmic6326_spkr_dtcal(spkr_dtcal_enum sel);
+
+
+// (0x81) CHARGER CTRL 1
+extern void dcl_pmic6326_chr_offset(cht_chr_offset_enum sel);
+extern void dcl_pmic6326_chr_ov_th_high(void);
+extern void dcl_pmic6326_chr_current(chr_chr_current_enum current);
+extern chr_chr_current_enum pmic_get_chr_current(void);
+
+// (0x82) CHARGER CTRL 2
+extern void dcl_pmic6326_chr_cv_rt(void);
+extern void dcl_pmic6326_chr_force(kal_bool force);
+extern void dcl_pmic6326_chr_chr_enable(kal_bool enable);
+extern void dcl_pmic6326_chr_cv_tune(void);
+// (0x83) TESTMODE CTRL 3 Analog Switch
+extern void dcl_pmic6326_asw_asel(asw_asel_enum sel);
+extern void dcl_pmic6326_asw_bsel(asw_bsel_enum sel);
+extern void dcl_pmic6326_asw_a1sel(kal_uint8 sel);
+extern void dcl_pmic6326_asw_a2sel(kal_uint8 sel);
+// (0x86) TESTMODE CTRL 6 BB AUXADC Related
+extern void dcl_pmic6326_adc_isense_enable(kal_bool enable);
+extern void dcl_pmic6326_adc_vbat_enable(kal_bool enable);
+extern void dcl_pmic6326_adc_meas_on(kal_bool on); // exported for controling vbat, isense adc measure at same time
+
+// (0x89) INT CTRL 1
+extern void dcl_pmic6326_int_ctrl_1_enable(int_ctrl_1_enum sel, kal_bool enable);
+// (0x8A) INT CTRL 2
+extern void dcl_pmic6326_int_ctrl_2_enable(int_ctrl_2_enum sel, kal_bool enable);
+// (0x8B) INT CTRL 2
+extern void dcl_pmic6326_int_ctrl_3_enable(int_ctrl_3_enum sel, kal_bool enable);
+
+
+// (0x8F)
+extern void dcl_pmic6326_st_gear_vwifi3v3(st_gear_vwifi3v3 gear);
+extern void dcl_pmic6326_st_gear_vwifi2v8(st_gear_vwifi2v8 gear);
+// (0x90)
+extern void dcl_pmic6326_st_gear_vsdio(st_gear_vsdio gear);
+
+// (0x92)
+extern void dcl_pmic6326_oc_gear_vwifi3v3(oc_gear_vwifi3v3 gear);
+extern void dcl_pmic6326_oc_gear_vwifi2v8(oc_gear_vwifi2v8 gear);
+// (0x93)
+extern void dcl_pmic6326_oc_gear_vsdio(oc_gear_vsdio gear);
+
+
+
+
+// (0x96) WATCHDOG CTRL and INT CTRL 4
+extern void dcl_pmic6326_wdt_timeout(wdt_timout_enum sel);
+extern void dcl_pmic6326_intr_polarity(kal_bool is_assert);
+extern void dcl_pmic6326_wdt_enable(kal_bool enable);
+
+
+// Combinational functions
+extern void dcl_pmic6326_vgp2_enable(kal_bool enable);
+extern void dcl_pmic6326_vgp2_sel(vgp2_sel_enum sel);
+extern void dcl_pmic6326_vgp2_on_sel(vgp2_on_sel_enum sel);
+extern void dcl_pmic6326_vgp2_sell(kal_uint8 value);
+extern void dcl_pmic6326_vgp2_selh(kal_uint8 value);
+extern void dcl_pmic6326_vgp2_ocfb_enable(kal_bool enable);
+extern void dcl_pmic6326_vsim2_enable(kal_bool enable);
+extern void dcl_pmic6326_vsim2_sel(vsim_sel_enum sel);
+extern void dcl_pmic6326_spk_enable(kal_bool enable);
+
+extern void dcl_pmic6326_EM_reg_write(kal_uint8 reg, kal_uint8 val);
+extern kal_uint8 dcl_pmic6326_EM_reg_read(kal_uint8 reg);
+
+#if defined(DRV_MISC_PMIC_ASSERT_KEEP_CHARGING)
+extern void dcl_pmic6326_assert_chaging_kick(void);
+#endif // #if defined(DRV_MISC_PMIC_ASSERT_KEEP_CHARGING)
+
+/*
+// The following are implemented in custom files
+// MoDIS parser skip start
+extern void pmic6326_customization_init(void);
+extern void pmic6326_cust_vspk_enable(kal_bool enable);
+extern void pmic6326_csut_vsim_enable(kal_bool enable);
+extern void pmic6326_csut_vsim_sel(pmic_adpt_vsim_volt volt);
+extern void pmic6326_csut_vsim2_enable(kal_bool enable);
+extern void pmic6326_csut_vsim2_sel(pmic_adpt_vsim_volt sel);
+extern void pmic6326_csut_vusb_enable(kal_bool enable);
+extern void pmic6326_csut_vcama_enable(kal_bool enable);
+extern void pmic6326_csut_vcama_sel(pmic_adpt_vcama_volt vol);
+extern void pmic6326_csut_vcamd_enable(kal_bool enable);
+extern void pmic6326_csut_vcamd_sel(pmic_adpt_vcamd_volt volt);
+// MoDIS parser skip end
+*/
+
+
+// =======================================================================================
+
+/*
+typedef enum
+{
+ VRF,
+ VTCXO,
+ V3GTX,
+ V3GRX,
+ VA,
+ VIO,
+ VRTC,
+ VCAMA,
+ VCAMD,
+ VWIFI3V3,
+ VWIFI2V8,
+ VSIM,
+ VBT,
+ VUSB,
+ VGP,
+ VSIM2=VGP,
+ VGP2,
+ VSDIO,
+ VCORE,
+ VCORE1,
+ VCORE2,
+ VM,
+ VMEM,
+ VIBR,
+ PMU_LDO_BUCK_MAX,
+ VRF18,
+ VFM,
+ VMC
+}PMU_LDO_BUCK_LIST_ENUM;
+
+typedef enum
+{
+ VPA1,
+ PMU_VPA_MAX
+}PMU_VPA_LIST_ENUM;
+
+typedef enum
+{
+ CHR,
+ PMU_CHR_MAX
+}PMU_CHR_LIST_ENUM;
+
+typedef enum
+{
+ SPK,
+ PMU_SPK_MAX
+}PMU_SPK_LIST_ENUM;
+
+typedef enum
+{
+ PMU_ISINK_MAX
+}PMU_ISINK_LIST_ENUM;
+
+typedef enum
+{
+ BOOST1,
+ BOOST2,
+ PMU_BOOST_MAX
+}PMU_BOOST_LIST_ENUM;
+*/
+
+
+#endif // #ifdef PMIC_6326_REG_API
+#endif // #ifndef __DCL_PMU6326_SW_H_STRUCT__
+
+
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmic6327_hw.h b/mcu/driver/peripheral/inc/dcl_pmic6327_hw.h
new file mode 100644
index 0000000..fe0989e
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmic6327_hw.h
@@ -0,0 +1,1237 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2011
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6327_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC6327 H/W configuration.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef __DCL_PMIC6327_HW_H_STRUCT__
+#define __DCL_PMIC6327_HW_H_STRUCT__
+
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6327_REG_API)
+#define PMIC_BANK0 0
+
+#define PMIC6327_E1_VERSION 0x01
+
+#define PMIC6327_E1_CID_CODE 0x27
+
+//RegisterTOP
+
+// (0x000) CID0
+// (RO)
+#define CID0_ADDR 0x00
+#define CID0_MASK 0xFF
+#define CID0_SHIFT 0
+
+// (0x001) I2C0
+// (RW)
+#define SDA_DE_ADDR 0x01
+#define SDA_DE_MASK 0xF0
+#define SDA_DE_SHIFT 4
+
+// (RW)
+#define SCL_DE_ADDR 0x01
+#define SCL_DE_MASK 0x0F
+#define SCL_DE_SHIFT 0
+
+// (0x002) STATUS0
+// (RO)
+#define VMD_STATUS_ADDR 0x02
+#define VMD_STATUS_MASK 0x80
+#define VMD_STATUS_SHIFT 7
+
+// (RO)
+#define VIO18_STATUS_ADDR 0x02
+#define VIO18_STATUS_MASK 0x20
+#define VIO18_STATUS_SHIFT 5
+
+// (RO)
+#define VRF18_STATUS_ADDR 0x02
+#define VRF18_STATUS_MASK 0x10
+#define VRF18_STATUS_SHIFT 4
+
+// (RO)
+#define VTCXO_STATUS_ADDR 0x02
+#define VTCXO_STATUS_MASK 0x02
+#define VTCXO_STATUS_SHIFT 1
+
+// (RO)
+#define VA25_STATUS_ADDR 0x02
+#define VA25_STATUS_MASK 0x01
+#define VA25_STATUS_SHIFT 0
+
+// (0x003) STATUS1
+// (RO)
+#define VM_STATUS_ADDR 0x03
+#define VM_STATUS_MASK 0x40
+#define VM_STATUS_SHIFT 6
+
+// (RO)
+#define VSIM_STATUS_ADDR 0x03
+#define VSIM_STATUS_MASK 0x08
+#define VSIM_STATUS_SHIFT 3
+
+// (0x004) STATUS2
+// (RO)
+#define VMC_STATUS_ADDR 0x04
+#define VMC_STATUS_MASK 0x20
+#define VMC_STATUS_SHIFT 5
+
+// (0x005) PGSTATUS0
+// (RO)
+#define VMD_PG_STATUS_ADDR 0x05
+#define VMD_PG_STATUS_MASK 0x80
+#define VMD_PG_STATUS_SHIFT 7
+
+// (RO)
+#define VTCXO_PG_STATUS_ADDR 0x05
+#define VTCXO_PG_STATUS_MASK 0x01
+#define VTCXO_PG_STATUS_SHIFT 0
+
+// (0x006) PGSTATUS1
+// (RO)
+#define VIO18_PG_STATUS_ADDR 0x06
+#define VIO18_PG_STATUS_MASK 0x20
+#define VIO18_PG_STATUS_SHIFT 5
+
+// (RO)
+#define VA25_PG_STATUS_ADDR 0x06
+#define VA25_PG_STATUS_MASK 0x08
+#define VA25_PG_STATUS_SHIFT 3
+
+// (0x007) OCSTATUS0
+// (RO)
+#define QI_VM_OC_STATUS_ADDR 0x07
+#define QI_VM_OC_STATUS_MASK 0x40
+#define QI_VM_OC_STATUS_SHIFT 6
+
+// (RO)
+#define QI_VMC_OC_STATUS_ADDR 0x07
+#define QI_VMC_OC_STATUS_MASK 0x20
+#define QI_VMC_OC_STATUS_SHIFT 5
+
+// (RO)
+#define QI_VSIM_OC_STATUS_ADDR 0x07
+#define QI_VSIM_OC_STATUS_MASK 0x08
+#define QI_VSIM_OC_STATUS_SHIFT 3
+
+// (0x008) OCSTATUS1
+// (RO)
+#define QI_VMD_OC_STATUS_ADDR 0x08
+#define QI_VMD_OC_STATUS_MASK 0x80
+#define QI_VMD_OC_STATUS_SHIFT 7
+
+// (RO)
+#define QI_VIO18_OC_STATUS_ADDR 0x08
+#define QI_VIO18_OC_STATUS_MASK 0x20
+#define QI_VIO18_OC_STATUS_SHIFT 5
+
+// (RO)
+#define QI_VRF18_OC_STATUS_ADDR 0x08
+#define QI_VRF18_OC_STATUS_MASK 0x10
+#define QI_VRF18_OC_STATUS_SHIFT 4
+
+// (RO)
+#define QI_VTCXO_OC_STATUS_ADDR 0x08
+#define QI_VTCXO_OC_STATUS_MASK 0x02
+#define QI_VTCXO_OC_STATUS_SHIFT 1
+
+// (RO)
+#define QI_VA25_OC_STATUS_ADDR 0x08
+#define QI_VA25_OC_STATUS_MASK 0x01
+#define QI_VA25_OC_STATUS_SHIFT 0
+
+// (0x009) BGR0
+// (RW)
+#define RG_BGR_RSEL_ADDR 0x09
+#define RG_BGR_RSEL_MASK 0x70
+#define RG_BGR_RSEL_SHIFT 4
+
+// (RW)
+#define rg_sw_bgr_trim_ADDR 0x09
+#define rg_sw_bgr_trim_MASK 0x04
+#define rg_sw_bgr_trim_SHIFT 2
+
+// (RW)
+#define RG_BGR_UNCHOP_PH_ADDR 0x09
+#define RG_BGR_UNCHOP_PH_MASK 0x02
+#define RG_BGR_UNCHOP_PH_SHIFT 1
+
+// (RW)
+#define RG_BGR_UNCHOP_ADDR 0x09
+#define RG_BGR_UNCHOP_MASK 0x01
+#define RG_BGR_UNCHOP_SHIFT 0
+
+// (0x00A) BGR1
+// (RW)
+#define RG_BGR_TEST_EN_ADDR 0x0A
+#define RG_BGR_TEST_EN_MASK 0x80
+#define RG_BGR_TEST_EN_SHIFT 7
+
+// (RW)
+#define RG_BGR_TEST_RSTB_ADDR 0x0A
+#define RG_BGR_TEST_RSTB_MASK 0x40
+#define RG_BGR_TEST_RSTB_SHIFT 6
+
+// (RW)
+#define RG_BGR_TRIM_EN_ADDR 0x0A
+#define RG_BGR_TRIM_EN_MASK 0x20
+#define RG_BGR_TRIM_EN_SHIFT 5
+
+// (RW)
+#define RG_BGR_TRIM_ADDR 0x0A
+#define RG_BGR_TRIM_MASK 0x1F
+#define RG_BGR_TRIM_SHIFT 0
+
+// (0x00B) I2C_RST0
+// (RW)
+#define I2C_RST0_ADDR 0x0B
+#define I2C_RST0_MASK 0xFF
+#define I2C_RST0_SHIFT 0
+
+// (0x00C) MODES
+// (RW)
+#define SDA_DRV_SEL_ADDR 0x0C
+#define SDA_DRV_SEL_MASK 0x04
+#define SDA_DRV_SEL_SHIFT 2
+
+// (RW)
+#define RG_BGR_TRIM_MODE_ADDR 0x0C
+#define RG_BGR_TRIM_MODE_MASK 0x02
+#define RG_BGR_TRIM_MODE_SHIFT 1
+
+// (RW)
+#define RG_BUCK_TRIM_MODE_ADDR 0x0C
+#define RG_BUCK_TRIM_MODE_MASK 0x01
+#define RG_BUCK_TRIM_MODE_SHIFT 0
+
+// (0x00D) SCAN_MODE
+// (RW)
+#define RG_SCAN_KEY_ADDR 0x0D
+#define RG_SCAN_KEY_MASK 0xFF
+#define RG_SCAN_KEY_SHIFT 0
+
+// (0x00E) I2C_TIMEOUT
+// (RW)
+#define I2C_TIMEOUT_ADDR 0x0E
+#define I2C_TIMEOUT_MASK 0xF0
+#define I2C_TIMEOUT_SHIFT 4
+
+// (0x00F) PAD_GPO
+// (RW)
+#define PAD_SRCLKEN_GPO_ADDR 0x0F
+#define PAD_SRCLKEN_GPO_MASK 0xF0
+#define PAD_SRCLKEN_GPO_SHIFT 4
+
+// (RW)
+#define PAD_SYSRSTB_GPO_ADDR 0x0F
+#define PAD_SYSRSTB_GPO_MASK 0x0E
+#define PAD_SYSRSTB_GPO_SHIFT 1
+
+//Register STRUP
+
+// (0x020) STRUP_CTRL1
+// (RW)
+#define RG_THRDET_SEL_ADDR 0x20
+#define RG_THRDET_SEL_MASK 0x40
+#define RG_THRDET_SEL_SHIFT 6
+
+// (RW)
+#define RG_THR_HWPDN_EN_ADDR 0x20
+#define RG_THR_HWPDN_EN_MASK 0x20
+#define RG_THR_HWPDN_EN_SHIFT 5
+
+// (RW)
+#define RG_STRUP_THR_SEL_ADDR 0x20
+#define RG_STRUP_THR_SEL_MASK 0x18
+#define RG_STRUP_THR_SEL_SHIFT 3
+
+// (RW)
+#define RG_THR_TMODE_ADDR 0x20
+#define RG_THR_TMODE_MASK 0x02
+#define RG_THR_TMODE_SHIFT 1
+
+// (RW)
+#define RG_PMU_PGDET_DIS_ADDR 0x20
+#define RG_PMU_PGDET_DIS_MASK 0x01
+#define RG_PMU_PGDET_DIS_SHIFT 0
+
+// (0x021) STRUP_CTRL2
+// (RW)
+#define RG_VREF_BG_ADDR 0x21
+#define RG_VREF_BG_MASK 0x70
+#define RG_VREF_BG_SHIFT 4
+
+// (RW)
+#define RG_STRUP_IREF_TRIM_ADDR 0x21
+#define RG_STRUP_IREF_TRIM_MASK 0x0F
+#define RG_STRUP_IREF_TRIM_SHIFT 0
+
+// (0x022) STRUP_CTRL3
+// (RW)
+#define RG_RST_DRVSEL_ADDR 0x22
+#define RG_RST_DRVSEL_MASK 0x40
+#define RG_RST_DRVSEL_SHIFT 6
+
+// (RW)
+#define RG_UVLO_VTHL_ADDR 0x22
+#define RG_UVLO_VTHL_MASK 0x03
+#define RG_UVLO_VTHL_SHIFT 0
+
+// (0x023) STRUP_RSV1
+// (RW)
+#define RG_PMU_RSV_ADDR 0x23
+#define RG_PMU_RSV_MASK 0xF0
+#define RG_PMU_RSV_SHIFT 4
+
+// (0x024) STRUP_TST_CTL
+// (RW)
+#define RG_BIAS_GEN_EN_FORCE_ADDR 0x24
+#define RG_BIAS_GEN_EN_FORCE_MASK 0x20
+#define RG_BIAS_GEN_EN_FORCE_SHIFT 5
+
+// (RW)
+#define RG_STRUP_PWRON_FORCE_ADDR 0x24
+#define RG_STRUP_PWRON_FORCE_MASK 0x10
+#define RG_STRUP_PWRON_FORCE_SHIFT 4
+
+// (RW)
+#define RG_STRUP_FT_CTRL_ADDR 0x24
+#define RG_STRUP_FT_CTRL_MASK 0x03
+#define RG_STRUP_FT_CTRL_SHIFT 0
+
+// (0x025) STRUP_THR_CTL
+// (RO)
+#define PMU_THR_STATUS_ADDR 0x25
+#define PMU_THR_STATUS_MASK 0x70
+#define PMU_THR_STATUS_SHIFT 4
+
+// (RW)
+#define RG_THERMAL_TEST_ADDR 0x25
+#define RG_THERMAL_TEST_MASK 0x0C
+#define RG_THERMAL_TEST_SHIFT 2
+
+// (RW)
+#define RG_ESDDEG_EN_ADDR 0x25
+#define RG_ESDDEG_EN_MASK 0x01
+#define RG_ESDDEG_EN_SHIFT 0
+
+//RegisterVCORE
+
+// (0x050) VMD_CON0
+// (RW)
+#define RG_VMD_CSL_ADDR 0x50
+#define RG_VMD_CSL_MASK 0x30
+#define RG_VMD_CSL_SHIFT 4
+
+// (RW)
+#define RG_VMD_CC_ADDR 0x50
+#define RG_VMD_CC_MASK 0x0C
+#define RG_VMD_CC_SHIFT 2
+
+// (RW)
+#define RG_VMD_RZSEL_ADDR 0x50
+#define RG_VMD_RZSEL_MASK 0x03
+#define RG_VMD_RZSEL_SHIFT 0
+
+// (0x051) VMD_CON1
+// (RW)
+#define RG_VMD_SLP_ADDR 0x51
+#define RG_VMD_SLP_MASK 0xC0
+#define RG_VMD_SLP_SHIFT 6
+
+// (RW)
+#define RG_VMD_ZX_OS_ADDR 0x51
+#define RG_VMD_ZX_OS_MASK 0x30
+#define RG_VMD_ZX_OS_SHIFT 4
+
+// (RW)
+#define RG_VMD_SLEW_ADDR 0x51
+#define RG_VMD_SLEW_MASK 0x0C
+#define RG_VMD_SLEW_SHIFT 2
+
+// (RW)
+#define RG_VMD_SLEW_NMOS_ADDR 0x51
+#define RG_VMD_SLEW_NMOS_MASK 0x03
+#define RG_VMD_SLEW_NMOS_SHIFT 0
+
+// (0x052) VMD_CON2
+// (RW)
+#define RG_VMD_MODESET_ADDR 0x52
+#define RG_VMD_MODESET_MASK 0x01
+#define RG_VMD_MODESET_SHIFT 0
+
+// (0x053) VMD_CON3
+// (RO)
+#define QI_VMD_EN_ADDR 0x53
+#define QI_VMD_EN_MASK 0x80
+#define QI_VMD_EN_SHIFT 7
+
+// (RW)
+#define RG_VMD_EN_ADDR 0x53
+#define RG_VMD_EN_MASK 0x01
+#define RG_VMD_EN_SHIFT 0
+
+// (0x054) VMD_CON4
+// (RW)
+#define RG_VMD_VFBADJ_ADDR 0x54
+#define RG_VMD_VFBADJ_MASK 0x0E
+#define RG_VMD_VFBADJ_SHIFT 1
+
+// (RW)
+#define RG_VMD_NDIS_EN_ADDR 0x54
+#define RG_VMD_NDIS_EN_MASK 0x01
+#define RG_VMD_NDIS_EN_SHIFT 0
+
+// (0x055) VMD_CON5
+// (RW)
+#define RG_VMD_VOSEL_ADDR 0x55
+#define RG_VMD_VOSEL_MASK 0x1F
+#define RG_VMD_VOSEL_SHIFT 0
+
+// (0x056) VMD_CON6
+// (RW)
+#define RG_VMD_VOSEL_CON1_ADDR 0x56
+#define RG_VMD_VOSEL_CON1_MASK 0x1F
+#define RG_VMD_VOSEL_CON1_SHIFT 0
+
+// (0x057) VMD_CON7
+// (RW)
+#define RG_VMD_VOSEL_SFCHG_EN_ADDR 0x57
+#define RG_VMD_VOSEL_SFCHG_EN_MASK 0x04
+#define RG_VMD_VOSEL_SFCHG_EN_SHIFT 2
+
+// (RW)
+#define RG_VMD_CTRL_ADDR 0x57
+#define RG_VMD_CTRL_MASK 0x01
+#define RG_VMD_CTRL_SHIFT 0
+
+// (0x058) VMD_CON8
+// (RO)
+#define QI_VMD_VOSEL_ADDR 0x58
+#define QI_VMD_VOSEL_MASK 0x1F
+#define QI_VMD_VOSEL_SHIFT 0
+
+// (0x05A) VMD_CON10
+// (RW)
+#define RG_TIMESTEP_ADDR 0x5A
+#define RG_TIMESTEP_MASK 0x01
+#define RG_TIMESTEP_SHIFT 0
+
+// (RW)
+#define RG_VOLTSTEP_ADDR 0x5A
+#define RG_VOLTSTEP_MASK 0x02
+#define RG_VOLTSTEP_SHIFT 1
+
+// (0x05B) VMD_CON11
+// (RW)
+#define RG_VMD_VH_ADDR 0x5B
+#define RG_VMD_VH_MASK 0x70
+#define RG_VMD_VH_SHIFT 4
+
+// (RW)
+#define RG_VMD_VL_ADDR 0x5B
+#define RG_VMD_VL_MASK 0x0E
+#define RG_VMD_VL_SHIFT 1
+
+// (RW)
+#define RG_VMD_GM_ADDR 0x5B
+#define RG_VMD_GM_MASK 0x01
+#define RG_VMD_GM_SHIFT 0
+
+// (0x05C) VMD_CON12
+// (RW)
+#define RG_VMD_CSR_ADDR 0x5C
+#define RG_VMD_CSR_MASK 0x07
+#define RG_VMD_CSR_SHIFT 0
+
+// (0x05D) VMD_CON13
+// (RW)
+#define VMD_OC_WND_ADDR 0x5D
+#define VMD_OC_WND_MASK 0x0C
+#define VMD_OC_WND_SHIFT 2
+
+// (RW)
+#define VMD_OC_THD_ADDR 0x5D
+#define VMD_OC_THD_MASK 0x03
+#define VMD_OC_THD_SHIFT 0
+
+//RegisterVRF18
+
+// (0x060) VRF18_CON0
+// (RW)
+#define RG_VRF18_CSL_ADDR 0x60
+#define RG_VRF18_CSL_MASK 0x30
+#define RG_VRF18_CSL_SHIFT 4
+
+// (RW)
+#define RG_VRF18_CC_ADDR 0x60
+#define RG_VRF18_CC_MASK 0x0C
+#define RG_VRF18_CC_SHIFT 2
+
+// (RW)
+#define RG_VRF18_RZSEL_ADDR 0x60
+#define RG_VRF18_RZSEL_MASK 0x03
+#define RG_VRF18_RZSEL_SHIFT 0
+
+// (0x061) VRF18_CON1
+// (RW)
+#define RG_VRF18_SLP_ADDR 0x61
+#define RG_VRF18_SLP_MASK 0xC0
+#define RG_VRF18_SLP_SHIFT 6
+
+// (RW)
+#define RG_VRF18_ZX_OS_ADDR 0x61
+#define RG_VRF18_ZX_OS_MASK 0x30
+#define RG_VRF18_ZX_OS_SHIFT 4
+
+// (RW)
+#define RG_VRF18_SLEW_ADDR 0x61
+#define RG_VRF18_SLEW_MASK 0x0C
+#define RG_VRF18_SLEW_SHIFT 2
+
+// (RW)
+#define RG_VRF18_SLEW_NMOS_ADDR 0x61
+#define RG_VRF18_SLEW_NMOS_MASK 0x03
+#define RG_VRF18_SLEW_NMOS_SHIFT 0
+
+// (0x062) VRF18_CON2
+// (RW)
+#define RG_VRF18_AVP_EN_ADDR 0x62
+#define RG_VRF18_AVP_EN_MASK 0x02
+#define RG_VRF18_AVP_EN_SHIFT 1
+
+// (RW)
+#define RG_VRF18_MODESET_ADDR 0x62
+#define RG_VRF18_MODESET_MASK 0x01
+#define RG_VRF18_MODESET_SHIFT 0
+
+// (0x063) VRF18_CON3
+// (RO)
+#define QI_VRF18_EN_ADDR 0x63
+#define QI_VRF18_EN_MASK 0x80
+#define QI_VRF18_EN_SHIFT 7
+
+// (RW)
+#define RG_VRF18_ON_CTRL_ADDR 0x63
+#define RG_VRF18_ON_CTRL_MASK 0x02
+#define RG_VRF18_ON_CTRL_SHIFT 1
+
+// (RW)
+#define RG_VRF18_EN_ADDR 0x63
+#define RG_VRF18_EN_MASK 0x01
+#define RG_VRF18_EN_SHIFT 0
+
+// (0x064) VRF18_CON4
+// (RW)
+#define RG_VRF18_STBTD_ADDR 0x64
+#define RG_VRF18_STBTD_MASK 0xC0
+#define RG_VRF18_STBTD_SHIFT 6
+
+// (RW)
+#define RG_VRF18_BURST_ADDR 0x64
+#define RG_VRF18_BURST_MASK 0x30
+#define RG_VRF18_BURST_SHIFT 4
+
+// (RW)
+#define RG_VRF18_OCFB_EN_ADDR 0x64
+#define RG_VRF18_OCFB_EN_MASK 0x02
+#define RG_VRF18_OCFB_EN_SHIFT 1
+
+// (RW)
+#define RG_VRF18_NDIS_EN_ADDR 0x64
+#define RG_VRF18_NDIS_EN_MASK 0x01
+#define RG_VRF18_NDIS_EN_SHIFT 0
+
+// (0x065) VRF18_CON5
+// (RW)
+#define RG_VRF18_VOSEL_ADDR 0x65
+#define RG_VRF18_VOSEL_MASK 0x1F
+#define RG_VRF18_VOSEL_SHIFT 0
+
+// (0x066) VRF18_CON6
+// (RW)
+#define RG_VRF18_RSV_ADDR 0x66
+#define RG_VRF18_RSV_MASK 0x0F
+#define RG_VRF18_RSV_SHIFT 0
+
+// (0x069) VRF18_CON9
+// (RW)
+#define RG_VRF18_VH_ADDR 0x69
+#define RG_VRF18_VH_MASK 0x70
+#define RG_VRF18_VH_SHIFT 4
+
+// (RW)
+#define RG_VRF18_VL_ADDR 0x69
+#define RG_VRF18_VL_MASK 0x0E
+#define RG_VRF18_VL_SHIFT 1
+
+// (RW)
+#define RG_VRF18_GMSEL_ADDR 0x69
+#define RG_VRF18_GMSEL_MASK 0x01
+#define RG_VRF18_GMSEL_SHIFT 0
+
+// (0x06A) VRF18_CON10
+// (RW)
+#define RG_VRF18_CSR_ADDR 0x6A
+#define RG_VRF18_CSR_MASK 0x07
+#define RG_VRF18_CSR_SHIFT 0
+
+// (0x06B) VRF18_CON11
+// (RW)
+#define RG_VRF18_OC_WND_ADDR 0x6B
+#define RG_VRF18_OC_WND_MASK 0x0C
+#define RG_VRF18_OC_WND_SHIFT 2
+
+// (RW)
+#define RG_VRF18_OC_THD_ADDR 0x6B
+#define RG_VRF18_OC_THD_MASK 0x03
+#define RG_VRF18_OC_THD_SHIFT 0
+
+//RegisterDigLDO
+
+// (0x080) DIGLDO_CON0
+// (RW)
+#define RG_VIO18_CAL_ADDR 0x80
+#define RG_VIO18_CAL_MASK 0x0F
+#define RG_VIO18_CAL_SHIFT 0
+
+// (0x082) DIGLDO_CON1
+// (RW)
+#define RG_VIO18_STBTD_ADDR 0x82
+#define RG_VIO18_STBTD_MASK 0x30
+#define RG_VIO18_STBTD_SHIFT 4
+
+// (RW)
+#define RG_VIO18_OCFB_EN_ADDR 0x82
+#define RG_VIO18_OCFB_EN_MASK 0x04
+#define RG_VIO18_OCFB_EN_SHIFT 2
+
+// (RW)
+#define RG_VIO18_NDIS_EN_ADDR 0x82
+#define RG_VIO18_NDIS_EN_MASK 0x02
+#define RG_VIO18_NDIS_EN_SHIFT 1
+
+// (RW)
+#define RG_VIO18_EN_ADDR 0x82
+#define RG_VIO18_EN_MASK 0x01
+#define RG_VIO18_EN_SHIFT 0
+
+// (0x083) DIGLDO_CON2
+// (RW)
+#define RG_VSIM_CAL_ADDR 0x83
+#define RG_VSIM_CAL_MASK 0x0F
+#define RG_VSIM_CAL_SHIFT 0
+
+// (0x084) DIGLDO_CON3
+// (RW)
+#define RG_VSIM_VOSEL_ADDR 0x84
+#define RG_VSIM_VOSEL_MASK 0x10
+#define RG_VSIM_VOSEL_SHIFT 4
+
+// (RW)
+#define RG_VSIM_EN_ADDR 0x84
+#define RG_VSIM_EN_MASK 0x01
+#define RG_VSIM_EN_SHIFT 0
+
+// (0x085) DIGLDO_CON4
+// (RW)
+#define RG_VSIM_STBTD_ADDR 0x85
+#define RG_VSIM_STBTD_MASK 0x30
+#define RG_VSIM_STBTD_SHIFT 4
+
+// (RW)
+#define RG_VSIM_OCFB_EN_ADDR 0x85
+#define RG_VSIM_OCFB_EN_MASK 0x02
+#define RG_VSIM_OCFB_EN_SHIFT 1
+
+// (RW)
+#define RG_VSIM_NDIS_EN_ADDR 0x85
+#define RG_VSIM_NDIS_EN_MASK 0x01
+#define RG_VSIM_NDIS_EN_SHIFT 0
+
+// (0x086) DIGLDO_CON5
+// (RW)
+#define RG_VMC_CAL_ADDR 0x86
+#define RG_VMC_CAL_MASK 0x0F
+#define RG_VMC_CAL_SHIFT 0
+
+// (0x087) DIGLDO_CON6
+// (RW)
+#define RG_VMC_VOSEL_ADDR 0x87
+#define RG_VMC_VOSEL_MASK 0x70
+#define RG_VMC_VOSEL_SHIFT 4
+
+// (0x088) DIGLDO_CON7
+// (RW)
+#define RG_VMC_STBTD_ADDR 0x88
+#define RG_VMC_STBTD_MASK 0x30
+#define RG_VMC_STBTD_SHIFT 4
+
+// (RW)
+#define RG_VMC_STB_SEL_ADDR 0x88
+#define RG_VMC_STB_SEL_MASK 0x08
+#define RG_VMC_STB_SEL_SHIFT 3
+
+// (RW)
+#define RG_VMC_OCFB_EN_ADDR 0x88
+#define RG_VMC_OCFB_EN_MASK 0x04
+#define RG_VMC_OCFB_EN_SHIFT 2
+
+// (RW)
+#define RG_VMC_NDIS_EN_ADDR 0x88
+#define RG_VMC_NDIS_EN_MASK 0x02
+#define RG_VMC_NDIS_EN_SHIFT 1
+
+// (RW)
+#define RG_VMC_EN_ADDR 0x88
+#define RG_VMC_EN_MASK 0x01
+#define RG_VMC_EN_SHIFT 0
+
+// (0x089) DIGLDO_CON8
+// (RW)
+#define RG_VM_CAL_ADDR 0x89
+#define RG_VM_CAL_MASK 0x0F
+#define RG_VM_CAL_SHIFT 0
+
+// (0x08A) DIGLDO_CON9
+// (RW)
+#define RG_VM_VOSEL_ADDR 0x8A
+#define RG_VM_VOSEL_MASK 0x30
+#define RG_VM_VOSEL_SHIFT 4
+
+// (RW)
+#define RG_VM_EN_ADDR 0x8A
+#define RG_VM_EN_MASK 0x01
+#define RG_VM_EN_SHIFT 0
+
+// (0x08B) DIGLDO_CON10
+// (RW)
+#define RG_VM_STBTD_ADDR 0x8B
+#define RG_VM_STBTD_MASK 0x30
+#define RG_VM_STBTD_SHIFT 4
+
+// (RW)
+#define RG_VM_OCFB_EN_ADDR 0x8B
+#define RG_VM_OCFB_EN_MASK 0x02
+#define RG_VM_OCFB_EN_SHIFT 1
+
+// (RW)
+#define RG_VM_NDIS_EN_ADDR 0x8B
+#define RG_VM_NDIS_EN_MASK 0x01
+#define RG_VM_NDIS_EN_SHIFT 0
+
+// (0x08C) DIGLDO_CON11
+// (RO)
+#define QI_VMC_MODE_ADDR 0x8C
+#define QI_VMC_MODE_MASK 0x80
+#define QI_VMC_MODE_SHIFT 7
+
+// (RW)
+#define VMC_LP_MODE_SET_ADDR 0x8C
+#define VMC_LP_MODE_SET_MASK 0x02
+#define VMC_LP_MODE_SET_SHIFT 1
+
+// (RW)
+#define VMC_LP_SEL_ADDR 0x8C
+#define VMC_LP_SEL_MASK 0x01
+#define VMC_LP_SEL_SHIFT 0
+
+// (0x08D) DIGLDO_CON12
+// (RO)
+#define QI_VM_MODE_ADDR 0x8D
+#define QI_VM_MODE_MASK 0x80
+#define QI_VM_MODE_SHIFT 7
+
+// (RW)
+#define VM_LP_MODE_SET_ADDR 0x8D
+#define VM_LP_MODE_SET_MASK 0x02
+#define VM_LP_MODE_SET_SHIFT 1
+
+// (RW)
+#define VM_LP_SEL_ADDR 0x8D
+#define VM_LP_SEL_MASK 0x01
+#define VM_LP_SEL_SHIFT 0
+
+// (0x08F) DIGLDO_CON14
+// (RW)
+#define RG_RSV_DLDOS_ADDR 0x8F
+#define RG_RSV_DLDOS_MASK 0xFF
+#define RG_RSV_DLDOS_SHIFT 0
+
+//RegisterAnaLDO
+
+// (0x0A0) ANALDO_CON0
+// (RW)
+#define RG_VTCXO_CAL_ADDR 0xA0
+#define RG_VTCXO_CAL_MASK 0x0F
+#define RG_VTCXO_CAL_SHIFT 0
+
+// (0x0A1) ANALDO_CON1
+// (RO)
+#define QI_VTCXO_EN_ADDR 0xA1
+#define QI_VTCXO_EN_MASK 0x80
+#define QI_VTCXO_EN_SHIFT 7
+
+// (RW)
+#define VTCXO_ON_CTRL_ADDR 0xA1
+#define VTCXO_ON_CTRL_MASK 0x02
+#define VTCXO_ON_CTRL_SHIFT 1
+
+// (RW)
+#define RG_VTCXO_EN_ADDR 0xA1
+#define RG_VTCXO_EN_MASK 0x01
+#define RG_VTCXO_EN_SHIFT 0
+
+// (0x0A2) ANALDO_CON2
+// (RW)
+#define RG_VTCXO_STBTD_ADDR 0xA2
+#define RG_VTCXO_STBTD_MASK 0x30
+#define RG_VTCXO_STBTD_SHIFT 4
+
+// (RW)
+#define RG_VTCXO_OCFB_EN_ADDR 0xA2
+#define RG_VTCXO_OCFB_EN_MASK 0x02
+#define RG_VTCXO_OCFB_EN_SHIFT 1
+
+// (RW)
+#define RG_VTCXO_NDIS_EN_ADDR 0xA2
+#define RG_VTCXO_NDIS_EN_MASK 0x01
+#define RG_VTCXO_NDIS_EN_SHIFT 0
+
+// (0x0A3) ANALDO_CON3
+// (RW)
+#define RG_VA25_CAL_ADDR 0xA3
+#define RG_VA25_CAL_MASK 0x0F
+#define RG_VA25_CAL_SHIFT 0
+
+// (0x0A4) ANALDO_CON4
+// (RO)
+#define QI_VA25_EN_ADDR 0xA4
+#define QI_VA25_EN_MASK 0x80
+#define QI_VA25_EN_SHIFT 7
+
+// (RW)
+#define RG_VA25_EN_ADDR 0xA4
+#define RG_VA25_EN_MASK 0x01
+#define RG_VA25_EN_SHIFT 0
+
+// (0x0A5) ANALDO_CON5
+// (RW)
+#define RG_VA25_STBTD_ADDR 0xA5
+#define RG_VA25_STBTD_MASK 0x30
+#define RG_VA25_STBTD_SHIFT 4
+
+// (RW)
+#define RG_VA25_OCFB_EN_ADDR 0xA5
+#define RG_VA25_OCFB_EN_MASK 0x02
+#define RG_VA25_OCFB_EN_SHIFT 1
+
+// (RW)
+#define RG_VA25_NDIS_EN_ADDR 0xA5
+#define RG_VA25_NDIS_EN_MASK 0x01
+#define RG_VA25_NDIS_EN_SHIFT 0
+
+// (0x0A6) ANALDO_CON6
+// (RO)
+#define QI_VA25_MODE_ADDR 0xA6
+#define QI_VA25_MODE_MASK 0x80
+#define QI_VA25_MODE_SHIFT 7
+
+// (RW)
+#define VA25_LP_SET_ADDR 0xA6
+#define VA25_LP_SET_MASK 0x02
+#define VA25_LP_SET_SHIFT 1
+
+// (RW)
+#define VA25_LP_SEL_ADDR 0xA6
+#define VA25_LP_SEL_MASK 0x01
+#define VA25_LP_SEL_SHIFT 0
+
+// (0x0A7) ANALDO_CON7
+// (RO)
+#define QI_VTCXO_MODE_ADDR 0xA7
+#define QI_VTCXO_MODE_MASK 0x80
+#define QI_VTCXO_MODE_SHIFT 7
+
+// (RW)
+#define VTCXO_LP_SET_ADDR 0xA7
+#define VTCXO_LP_SET_MASK 0x02
+#define VTCXO_LP_SET_SHIFT 1
+
+// (RW)
+#define VTCXO_LP_SEL_ADDR 0xA7
+#define VTCXO_LP_SEL_MASK 0x01
+#define VTCXO_LP_SEL_SHIFT 0
+
+// (0x0A8) ANALDO_CON8
+// (RW)
+#define RG_VA25_STB_ADDR 0xA8
+#define RG_VA25_STB_MASK 0x02
+#define RG_VA25_STB_SHIFT 1
+
+// (RW)
+#define RG_VTCXO_STB_ADDR 0xA8
+#define RG_VTCXO_STB_MASK 0x01
+#define RG_VTCXO_STB_SHIFT 0
+
+//RegisterBuckK
+
+// (0x0B0) BUCK_K_CON0
+// (RW)
+#define RG_SMPS_TESTMODE_ADDR 0xB0
+#define RG_SMPS_TESTMODE_MASK 0x3F
+#define RG_SMPS_TESTMODE_SHIFT 0
+
+// (0x0B2) BUCK_K_CON2
+// (RW)
+#define RG_SMPS_RSV_ADDR 0xB2
+#define RG_SMPS_RSV_MASK 0xFF
+#define RG_SMPS_RSV_SHIFT 0
+
+// (0x0B3) BUCK_K_CON3
+// (RW)
+#define rg_auto_k_ADDR 0xB3
+#define rg_auto_k_MASK 0x40
+#define rg_auto_k_SHIFT 6
+
+// (RW)
+#define rg_k_start_manual_ADDR 0xB3
+#define rg_k_start_manual_MASK 0x10
+#define rg_k_start_manual_SHIFT 4
+
+// (RW)
+#define rg_k_map_sel_ADDR 0xB3
+#define rg_k_map_sel_MASK 0x02
+#define rg_k_map_sel_SHIFT 1
+
+// (RW)
+#define rg_k_rst_done_ADDR 0xB3
+#define rg_k_rst_done_MASK 0x01
+#define rg_k_rst_done_SHIFT 0
+
+// (0x0B4) BUCK_K_CON4
+// (RW)
+#define rg_k_control_smps_ADDR 0xB4
+#define rg_k_control_smps_MASK 0x3F
+#define rg_k_control_smps_SHIFT 0
+
+// (0x0B5) BUCK_K_CON5
+// (RO)
+#define k_control_ADDR 0xB5
+#define k_control_MASK 0xFC
+#define k_control_SHIFT 2
+
+// (RO)
+#define k_done_ADDR 0xB5
+#define k_done_MASK 0x02
+#define k_done_SHIFT 1
+
+// (RO)
+#define k_result_ADDR 0xB5
+#define k_result_MASK 0x01
+#define k_result_SHIFT 0
+
+// (0x0B6) BUCK_K_CON6
+// (RW)
+#define efuse_enb_ADDR 0xB6
+#define efuse_enb_MASK 0x80
+#define efuse_enb_SHIFT 7
+
+// (RW)
+#define efuse_read_ADDR 0xB6
+#define efuse_read_MASK 0x40
+#define efuse_read_SHIFT 6
+
+// (RW)
+#define efuse_program_ADDR 0xB6
+#define efuse_program_MASK 0x20
+#define efuse_program_SHIFT 5
+
+// (RW)
+#define efuse_address_ADDR 0xB6
+#define efuse_address_MASK 0x1F
+#define efuse_address_SHIFT 0
+
+// (0x0B7) BUCK_K_CON7
+// (RW)
+#define efuse_address_msb_ADDR 0xB7
+#define efuse_address_msb_MASK 0x80
+#define efuse_address_msb_SHIFT 7
+
+// (RW)
+#define rg_sw_osc_trim_ADDR 0xB7
+#define rg_sw_osc_trim_MASK 0x01
+#define rg_sw_osc_trim_SHIFT 0
+
+// (0x0B8) BUCK_K_CON8
+// (RO)
+#define efuse_dout0_ADDR 0xB8
+#define efuse_dout0_MASK 0xFF
+#define efuse_dout0_SHIFT 0
+
+// (0x0B9) BUCK_K_CON9
+// (RO)
+#define efuse_dout1_ADDR 0xB9
+#define efuse_dout1_MASK 0xFF
+#define efuse_dout1_SHIFT 0
+
+// (0x0BA) BUCK_K_CON10
+// (RO)
+#define efuse_dout2_ADDR 0xBA
+#define efuse_dout2_MASK 0xFF
+#define efuse_dout2_SHIFT 0
+
+// (0x0BB) BUCK_K_CON11
+// (RO)
+#define efuse_dout3_ADDR 0xBB
+#define efuse_dout3_MASK 0xFF
+#define efuse_dout3_SHIFT 0
+
+// (0x0BC) BUCK_K_CON12
+// (RO)
+#define efuse_dout4_ADDR 0xBC
+#define efuse_dout4_MASK 0xFF
+#define efuse_dout4_SHIFT 0
+
+// (0x0BD) BUCK_K_CON13
+// (RO)
+#define efuse_dout5_ADDR 0xBD
+#define efuse_dout5_MASK 0xFF
+#define efuse_dout5_SHIFT 0
+
+// (0x0BE) BUCK_K_CON14
+// (RO)
+#define efuse_dout6_ADDR 0xBE
+#define efuse_dout6_MASK 0xFF
+#define efuse_dout6_SHIFT 0
+
+// (0x0BF) BUCK_K_CON15
+// (RO)
+#define efuse_dout7_ADDR 0xBF
+#define efuse_dout7_MASK 0xFF
+#define efuse_dout7_SHIFT 0
+
+//RegisterPAD
+
+// (0x0D0) PAD_CTRL_CON0
+// (RW)
+#define SCK_PU_ADDR 0xD0
+#define SCK_PU_MASK 0x20
+#define SCK_PU_SHIFT 5
+
+// (RW)
+#define SCK_PD_ADDR 0xD0
+#define SCK_PD_MASK 0x10
+#define SCK_PD_SHIFT 4
+
+// (RW)
+#define SCK_E2_ADDR 0xD0
+#define SCK_E2_MASK 0x08
+#define SCK_E2_SHIFT 3
+
+// (RW)
+#define SCK_E4_ADDR 0xD0
+#define SCK_E4_MASK 0x04
+#define SCK_E4_SHIFT 2
+
+// (RW)
+#define SCK_SMT_ADDR 0xD0
+#define SCK_SMT_MASK 0x02
+#define SCK_SMT_SHIFT 1
+
+// (RW)
+#define SCK_SR_ADDR 0xD0
+#define SCK_SR_MASK 0x01
+#define SCK_SR_SHIFT 0
+
+// (0x0D1) PAD_CTRL_CON1
+// (RW)
+#define SDA_PU_ADDR 0xD1
+#define SDA_PU_MASK 0x20
+#define SDA_PU_SHIFT 5
+
+// (RW)
+#define SDA_PD_ADDR 0xD1
+#define SDA_PD_MASK 0x10
+#define SDA_PD_SHIFT 4
+
+// (RW)
+#define SDA_E2_ADDR 0xD1
+#define SDA_E2_MASK 0x08
+#define SDA_E2_SHIFT 3
+
+// (RW)
+#define SDA_E4_ADDR 0xD1
+#define SDA_E4_MASK 0x04
+#define SDA_E4_SHIFT 2
+
+// (RW)
+#define SDA_SMT_ADDR 0xD1
+#define SDA_SMT_MASK 0x02
+#define SDA_SMT_SHIFT 1
+
+// (RW)
+#define SDA_SR_ADDR 0xD1
+#define SDA_SR_MASK 0x01
+#define SDA_SR_SHIFT 0
+
+// (0x0D2) PAD_CTRL_CON2
+// (RW)
+#define SRCLKEN_PU_ADDR 0xD2
+#define SRCLKEN_PU_MASK 0x20
+#define SRCLKEN_PU_SHIFT 5
+
+// (RW)
+#define SRCLKEN_PD_ADDR 0xD2
+#define SRCLKEN_PD_MASK 0x10
+#define SRCLKEN_PD_SHIFT 4
+
+// (RW)
+#define SRCLKEN_E2_ADDR 0xD2
+#define SRCLKEN_E2_MASK 0x08
+#define SRCLKEN_E2_SHIFT 3
+
+// (RW)
+#define SRCLKEN_E4_ADDR 0xD2
+#define SRCLKEN_E4_MASK 0x04
+#define SRCLKEN_E4_SHIFT 2
+
+// (RW)
+#define SRCLKEN_SMT_ADDR 0xD2
+#define SRCLKEN_SMT_MASK 0x02
+#define SRCLKEN_SMT_SHIFT 1
+
+// (RW)
+#define SRCLKEN_SR_ADDR 0xD2
+#define SRCLKEN_SR_MASK 0x01
+#define SRCLKEN_SR_SHIFT 0
+
+// (0x0E0) VERSION
+// (RO)
+#define VERSION_ADDR 0xE0
+#define VERSION_MASK 0xFF
+#define VERSION_SHIFT 0
+
+// (0x0F0) BIST_CTRL_CON0
+// (RW)
+#define RG_VTCXO_BIST_EN_ADDR 0xF0
+#define RG_VTCXO_BIST_EN_MASK 0x08
+#define RG_VTCXO_BIST_EN_SHIFT 3
+
+// (RW)
+#define RG_VA25_BIST_EN_ADDR 0xF0
+#define RG_VA25_BIST_EN_MASK 0x01
+#define RG_VA25_BIST_EN_SHIFT 0
+
+// (0x0F1) BIST_CTRL_CON1
+// (RW)
+#define RG_VM_BIST_EN_ADDR 0xF1
+#define RG_VM_BIST_EN_MASK 0x08
+#define RG_VM_BIST_EN_SHIFT 3
+
+// (RW)
+#define RG_VMC_BIST_EN_ADDR 0xF1
+#define RG_VMC_BIST_EN_MASK 0x04
+#define RG_VMC_BIST_EN_SHIFT 2
+
+// (RW)
+#define RG_VIO18_BIST_EN_ADDR 0xF1
+#define RG_VIO18_BIST_EN_MASK 0x02
+#define RG_VIO18_BIST_EN_SHIFT 1
+
+// (RW)
+#define RG_VSIM_BIST_EN_ADDR 0xF1
+#define RG_VSIM_BIST_EN_MASK 0x01
+#define RG_VSIM_BIST_EN_SHIFT 0
+
+// (0x0F2) BIST_CTRL_CON2
+// (RW)
+#define RG_ABIST_MUX_ADDR 0xF2
+#define RG_ABIST_MUX_MASK 0x0F
+#define RG_ABIST_MUX_SHIFT 0
+
+//Register Group
+
+//Memory
+
+#define PMIC_BANK0_MAX_REG_IDX RG_ABIST_MUX_ADDR
+#define PMIC_BANK0_REG_NUM (PMIC_BANK0_MAX_REG_IDX + 1)
+
+#endif //#if defined(PMIC_6327_REG_API)
+
+#endif // #ifndef __DCL_PMIC6327_HW_H_STRUCT__
diff --git a/mcu/driver/peripheral/inc/dcl_pmic6327_sw.h b/mcu/driver/peripheral/inc/dcl_pmic6327_sw.h
new file mode 100644
index 0000000..ec68aa6
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmic6327_sw.h
@@ -0,0 +1,133 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6327_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6327
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+
+#ifndef __DCL_PMU6327_SW_H_STRUCT__
+#define __DCL_PMU6327_SW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#ifdef PMIC_6327_REG_API
+
+#define PMIC6327_ECO_1_VERSION 0x01
+#define PMIC6327_ECO_2_VERSION 0x02
+
+// Combinational functions
+extern void pmic6327_customization_init(void);
+/*
+// The following are implemented in custom files
+// MoDIS parser skip start
+extern void pmic6327_customization_init(void);
+extern void pmic6327_cust_vspk_enable(kal_bool enable);
+extern void pmic6327_csut_vsim_enable(kal_bool enable);
+extern void pmic6327_csut_vsim_sel(pmic_adpt_vsim_volt volt);
+extern void pmic6327_csut_vsim2_enable(kal_bool enable);
+extern void pmic6327_csut_vsim2_sel(pmic_adpt_vsim_volt sel);
+extern void pmic6327_csut_vusb_enable(kal_bool enable);
+extern void pmic6327_csut_vcama_enable(kal_bool enable);
+extern void pmic6327_csut_vcama_sel(pmic_adpt_vcama_volt vol);
+extern void pmic6327_csut_vcamd_enable(kal_bool enable);
+extern void pmic6327_csut_vcamd_sel(pmic_adpt_vcamd_volt volt);
+// MoDIS parser skip end
+*/
+
+typedef enum
+{
+ VIO18_STATUS,
+ VRF18_STATUS,
+ VTCXO_STATUS,
+ PMU_THR_STATUS,
+ RG_VRF18_EN,
+ RG_VRF18_VOSEL,
+ RG_VRF18_ON_CTRL,
+ RG_VRF18_MODESET,
+ RG_VIO18_EN,
+ RG_VSIM_CAL,
+ RG_VSIM_VOSEL,
+ RG_VSIM_EN,
+ RG_VMC_CAL,
+ RG_VMC_VOSEL,
+ RG_VMC_EN,
+ RG_VTCXO_CAL,
+ VTCXO_ON_CTRL,
+ RG_VTCXO_EN,
+}PMU_FLAGS_LIST_ENUM;
+
+#endif // #ifdef PMIC_6327_REG_API
+#endif // #ifndef __DCL_PMU6327_SW_H_STRUCT__
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmic6329_hw.h b/mcu/driver/peripheral/inc/dcl_pmic6329_hw.h
new file mode 100644
index 0000000..ae3a219
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmic6329_hw.h
@@ -0,0 +1,2998 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2011
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6329_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC6329 H/W configuration.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef __DCL_PMIC6329_HW_H_STRUCT__
+#define __DCL_PMIC6329_HW_H_STRUCT__
+
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6329_REG_API)
+
+#define BIT00 0x00000001
+#define BIT01 0x00000002
+#define BIT02 0x00000004
+#define BIT03 0x00000008
+
+#define BIT04 0x00000010
+#define BIT05 0x00000020
+#define BIT06 0x00000040
+#define BIT07 0x00000080
+
+#define BIT08 0x00000100
+#define BIT09 0x00000200
+#define BIT10 0x00000400
+#define BIT11 0x00000800
+
+#define BIT12 0x00001000
+#define BIT13 0x00002000
+#define BIT14 0x00004000
+#define BIT15 0x00008000
+
+#define BIT16 0x00010000
+#define BIT17 0x00020000
+#define BIT18 0x00040000
+#define BIT19 0x00080000
+
+#define BIT20 0x00100000
+#define BIT21 0x00200000
+#define BIT22 0x00400000
+#define BIT23 0x00800000
+
+#define BIT24 0x01000000
+#define BIT25 0x02000000
+#define BIT26 0x04000000
+#define BIT27 0x08000000
+
+#define BIT28 0x10000000
+#define BIT29 0x20000000
+#define BIT30 0x40000000
+#define BIT31 0x80000000
+
+#define PMIC6329_E1_CID_CODE 0x2900
+#define PMIC6329_E2_CID_CODE 0x2910
+
+#define CID_1_REG_INDEX 0x0
+#define CID_2_REG_INDEX 0x1
+
+//#define PMIC_MAX_REG_IDX 0x96
+//#define PMIC_REG_NUM 0x97 // ###***** PMIC_REG_NUM must equal (PMIC_MAX_REG_IDX + 1)
+// Anderson Modify 20110331 Start
+#define PMIC_BANK0_MAX_REG_IDX 0xF7
+#define PMIC_BANK0_REG_NUM (PMIC_BANK0_MAX_REG_IDX + 1) // ###***** PMIC_BANK0_REG_NUM must equal (PMIC_BANK0_MAX_REG_IDX + 1)
+#define PMIC_BANK1_MAX_REG_IDX 0xA5
+#define PMIC_BANK1_REG_NUM (PMIC_BANK1_MAX_REG_IDX + 1) // ###***** PMIC_BANK1_REG_NUM must equal (PMIC_BANK1_MAX_REG_IDX + 1)
+
+////////////////////////////////
+/* PMIC 6329 BANK 0 */
+////////////////////////////////
+// (0x00) CID0 (RO)
+#define CID0_ADDR 0x00
+
+#define CID0_MASK 0xFF
+#define CID0_MASK_SHIFT 0x0
+
+// (0x01) CID1 (RO)
+#define CID1_ADDR 0x01
+
+#define CID1_MASK 0xFF
+#define CID01_MASK_SHIFT 0x0
+
+// (0x02) STATUS0 (RO)
+#define STATUS0_ADDR 0x02
+
+#define VCORE_STATUS_MASK 0x1
+#define VCORE_STATUS_SHIFT 0x7
+#define VPROC_STATUS_MASK 0x1
+#define VPROC_STATUS_SHIFT 0x6
+#define VIO18_STATUS_MASK 0x1
+#define VIO18_STATUS_SHIFT 0x5
+#define VRF18_STATUS_MASK 0x1
+#define VRF18_STATUS_SHIFT 0x4
+#define VPA_STATUS_MASK 0x1
+#define VPA_STATUS_SHIFT 0x3
+#define VRF_STATUS_MASK 0x1
+#define VRF_STATUS_SHIFT 0x2
+#define VTCXO_STATUS_MASK 0x1
+#define VTCXO_STATUS_SHIFT 0x1
+#define VA1_STATUS_MASK 0x1
+#define VA1_STATUS_SHIFT 0x0
+
+// (0x03) STATUS1 (RO)
+#define STATUS1_ADDR 0x03
+
+#define VCAMA_STATUS_MASK 0x1
+#define VCAMA_STATUS_SHIFT 0x7
+#define VM12_1_STATUS_MASK 0x1
+#define VM12_1_STATUS_SHIFT 0x6
+#define VM12_INT_STATUS_MASK 0x1
+#define VM12_INT_STATUS_SHIFT 0x5
+#define VIO28_STATUS_MASK 0x1
+#define VIO28_STATUS_SHIFT 0x4
+#define VSIM1_STATUS_MASK 0x1
+#define VSIM1_STATUS_SHIFT 0x3
+#define VSIM2_STATUS_MASK 0x1
+#define VSIM2_STATUS_SHIFT 0x2
+#define VUSB_STATUS_MASK 0x1
+#define VUSB_STATUS_SHIFT 0x1
+#define VCAMD_STATUS_MASK 0x1
+#define VCAMD_STATUS_SHIFT 0x0
+
+// (0x04) STATUS2 (RO)
+#define STATUS2_ADDR 0x04
+
+#define VCAM_IO_STATUS_MASK 0x1
+#define VCAM_IO_STATUS_SHIFT 0x7
+#define VCAM_AF_STATUS_MASK 0x1
+#define VCAM_AF_STATUS_SHIFT 0x6
+#define VMC_STATUS_MASK 0x1
+#define VMC_STATUS_SHIFT 0x5
+#define VMCH_STATUS_MASK 0x1
+#define VMCH_STATUS_SHIFT 0x4
+#define VGP_STATUS_MASK 0x1
+#define VGP_STATUS_SHIFT 0x3
+#define VGP2_STATUS_MASK 0x1
+#define VGP2_STATUS_SHIFT 0x2
+#define VM12_2_STATUS_MASK 0x1
+#define VM12_2_STATUS_SHIFT 0x1
+#define VIBR_STATUS_MASK 0x1
+#define VIBR_STATUS_SHIFT 0x0
+
+// (0x05) STATUS3 (RO)
+#define STATUS3_ADDR 0x05
+
+#define VA2_STATUS_MASK 0x1
+#define VA2_STATUS_SHIFT 0x5
+#define VRTC_STATUS_MASK 0x1
+#define VRTC_STATUS_SHIFT 0x4
+#define VTCXO_PG_STATUS_MASK 0x1
+#define VTCXO_PG_STATUS_SHIFT 0x0
+
+// (0x06) PGSTATUS0 (RO)
+#define PGSTATUS0_ADDR 0x06
+
+#define VCORE_PG_STATUS_MASK 0x1
+#define VCORE_PG_STATUS_SHIFT 0x7
+#define VPROC_PG_STATUS_MASK 0x1
+#define VPROC_PG_STATUS_SHIFT 0x6
+#define VIO18_PG_STATUS_MASK 0x1
+#define VIO18_PG_STATUS_SHIFT 0x5
+#define VIO28_PG_STATUS_MASK 0x1
+#define VIO28_PG_STATUS_SHIFT 0x4
+#define VA1_PG_STATUS_MASK 0x1
+#define VA1_PG_STATUS_SHIFT 0x3
+#define VM12_1_PG_STATUS_MASK 0x1
+#define VM12_1_PG_STATUS_SHIFT 0x2
+#define VM12_2_PG_STATUS_MASK 0x1
+#define VM12_2_PG_STATUS_SHIFT 0x1
+#define VM12_INT_PG_STATUS_MASK 0x1
+#define VM12_INT_PG_STATUS_SHIFT 0x0
+
+// (0x07) RESERVERD
+
+// (0x08) RESERVERD
+
+// (0x09) CHRSATUS (RO)
+#define CHRSTATUS_ADDR 0x09
+
+#define CV_MASK 0x1
+#define CV_SHIFT 0x7
+#define RO_BATON_UNDET_MASK 0x1
+#define RO_BATON_UNDET_SHIFT 0x6
+#define PCHR_CHRDET_MASK 0x1
+#define PCHR_CHRDET_SHIFT 0x5
+#define VBAT_OV_MASK 0x1
+#define VBAT_OV_SHIFT 0x4
+#define PWRKEY_DEB_MASK 0x1
+#define PWRKEY_DEB_SHIFT 0x3
+#define USBDL_MASK 0x1
+#define USBDL_SHIFT 0x2
+#define TEST_MODE_POR_MASK 0x1
+#define TEST_MODE_POR_SHIFT 0x0
+
+// (0x0A) OCSTATUS0 (RO)
+#define OCSTATUS0_ADDR 0x0A
+
+#define VCAMA_OC_STATUS_MASK 0x1
+#define VCAMA_OC_STATUS_SHIFT 0x7
+#define VM12_1_OC_STATUS_MASK 0x1
+#define VM12_1_OC_STATUS_SHIFT 0x6
+#define VM12_OC_STATUS_MASK 0x1
+#define VM12_OC_STATUS_SHIFT 0x5
+#define VIO28_OC_STATUS_MASK 0x1
+#define VIO28_OC_STATUS_SHIFT 0x4
+#define VSIM1_OC_STATUS_MASK 0x1
+#define VSIM1_OC_STATUS_SHIFT 0x3
+#define VSIM2_OC_STATUS_MASK 0x1
+#define VSIM2_OC_STATUS_SHIFT 0x2
+#define VUSB_OC_STATUS_MASK 0x1
+#define VUSB_OC_STATUS_SHIFT 0x1
+#define VCAMD_OC_STATUS_MASK 0x1
+#define VCAMD_OC_STATUS_SHIFT 0x0
+
+// (0x0B) OCSTATUS1 (RO)
+#define OCSTATUS1_ADDR 0x0B
+
+#define VCAM_IO_OC_STATUS_MASK 0x1
+#define VCAM_IO_OC_STATUS_SHIFT 0x7
+#define VCAM_AF_OC_STATUS_MASK 0x1
+#define VCAM_AF_OC_STATUS_SHIFT 0x6
+#define VMC_OC_STATUS_MASK 0x1
+#define VMC_OC_STATUS_SHIFT 0x5
+#define VMCH_OC_STATUS_MASK 0x1
+#define VMCH_OC_STATUS_SHIFT 0x4
+#define VGP_OC_STATUS_MASK 0x1
+#define VGP_OC_STATUS_SHIFT 0x3
+#define VGP2_OC_STATUS_MASK 0x1
+#define VGP2_OC_STATUS_SHIFT 0x2
+#define VM12_2_OC_STATUS_MASK 0x1
+#define VM12_2_OC_STATUS_SHIFT 0x1
+#define VIBR_OC_STATUS_MASK 0x1
+#define VIBR_OC_STATUS_SHIFT 0x0
+
+// (0x0C) OCSTATUS2 (RO)
+#define OCSTATUS2_ADDR 0x0C
+
+#define HOMEKEY_DEB_MASK 0x1
+#define HOMEKEY_DEB_SHIFT 0x6
+#define BOOST_OC_STATUS_MASK 0x1
+#define BOOST_OC_STATUS_SHIFT 0x5
+#define VA2_OC_STATUS_MASK 0x1
+#define VA2_OC_STATUS_SHIFT 0x4
+#define NI_SPK_OC_DET_D_R_MASK 0x1
+#define NI_SPK_OC_DET_D_R_SHIFT 0x3
+#define NI_SPK_OC_DET_D_L_MASK 0x1
+#define NI_SPK_OC_DET_D_L_SHIFT 0x2
+#define NI_SPK_OC_DET_AB_R_MASK 0x1
+#define NI_SPK_OC_DET_AB_R_SHIFT 0x1
+#define NI_SPK_OC_DET_AB_L_MASK 0x1
+#define NI_SPK_OC_DET_AB_L_SHIFT 0x0
+
+// (0x0D) OCSTATUS3 (RO)
+#define OCSTATUS3_ADDR 0x0D
+
+#define VCORE_OC_STATUS_MASK 0x1
+#define VCORE_OC_STATUS_SHIFT 0x7
+#define VPROC_OC_STATUS_MASK 0x1
+#define VPROC_OC_STATUS_SHIFT 0x6
+#define VIO18_OC_STATUS_MASK 0x1
+#define VIO18_OC_STATUS_SHIFT 0x5
+#define VRF18_OC_STATUS_MASK 0x1
+#define VRF18_OC_STATUS_SHIFT 0x4
+#define VPA_OC_STATUS_MASK 0x1
+#define VPA_OC_STATUS_SHIFT 0x3
+#define VRF_OC_STATUS_MASK 0x1
+#define VRF_OC_STATUS_SHIFT 0x2
+#define VTCXO_OC_STATUS_MASK 0x1
+#define VTCXO_OC_STATUS_SHIFT 0x1
+#define VA1_OC_STATUS_MASK 0x1
+#define VA1_OC_STATUS_SHIFT 0x0
+
+// (0x0E) STRUP_CTRL1 (RW)
+#define STRUP_CTRL1_ADDR 0x0E
+
+#define RG_THRDET_SEL_MASK 0x1
+#define RG_THRDET_SEL_SHIFT 0x6
+#define RG_THR_HWPDN_EN_MASK 0x1
+#define RG_THR_HWPDN_EN_SHIFT 0x5
+#define RG_STRUP_THR_SEL_MASK 0x3
+#define RG_STRUP_THR_SEL_SHIFT 0x3
+#define RG_THR_TMODE_MASK 0x1
+#define RG_THR_TMODE_SHIFT 0x1
+#define RG_FORCE_NON_THERMAL_MASK 0x1
+#define RG_FORCE_NON_THERMAL_SHIFT 0x0
+
+// (0x0F) STRUP_CTRL2 (RW)
+#define STRUP_CTRL2_ADDR 0x0F
+
+#define RG_VREF_BG_MASK 0x7
+#define RG_VREF_BG_SHIFT 0x4
+#define RG_STRUP_IREF_TRIM_MASK 0xF
+#define RG_STRUP_IREF_TRIM_SHIFT 0x0
+
+// (0x10) STRUP_CTRL3 (RW)
+#define STRUP_CTRL3_ADDR 0x10
+
+#define RG_BB_PROC_SEL_MASK 0x1
+#define RG_BB_PROC_SEL_SHIFT 0x7
+#define RG_STRUP_RST_DRVSEL_MASK 0x1
+#define RG_STRUP_RST_DRVSEL_SHIFT 0x6
+#define RG_PMU_LEV_UNGATE_MASK 0x1
+#define RG_PMU_LEV_UNGATE_SHIFT 0x1
+#define RG_USBDL_EN_MASK 0x1
+#define RG_USBDL_EN_SHIFT 0x0
+
+// (0x11) STRUP_RSV1 (RW)
+#define STRUP_RSV1_ADDR 0x11
+
+#define RG_PMU_RSV_MASK 0xF
+#define RG_PMU_RSV_SHIFT 0x4
+
+// (0x12) STRUP_TST_CTL (RW)
+#define STRUP_TST_CTL_ADDR 0x12
+
+#define RG_BIAS_GEN_EN_FORCE_MASK 0x1
+#define RG_BIAS_GEN_EN_FORCE_SHIFT 0x5
+#define RG_STRUP_PWRON_FORCE_MASK 0x1
+#define RG_STRUP_PWRON_FORCE_SHIFT 0x4
+#define RG_STRUP_TEST_MASK 0x1
+#define RG_STRUP_TEST_SHIFT 0x3
+#define RG_STRUP_FT_CTRL_MASK 0x3
+#define RG_STRUP_FT_CTRL_SHIFT 0x0
+
+// (0x13) STRUP_THR_CTL (RO/RW)
+#define STRUP_THR_CTL_ADDR 0x13
+
+#define PMU_THR_STATUS_MASK 0x7
+#define PMU_THR_STATUS_SHIFT 0x4
+#define RG_THERMAL_TEST_MASK 0x3
+#define RG_THERMAL_TEST_SHIFT 0x2
+
+// (0x14) STRUP_VPG_EN1 (RW)
+#define STRUP_VPG_EN1_ADDR 0x14
+
+#define RG_VCORE_PG_ENB_MASK 0x1
+#define RG_VCORE_PG_ENB_SHIFT 0x7
+#define RG_VPROC_PG_ENB_MASK 0x1
+#define RG_VPROC_PG_ENB_SHIFT 0x6
+#define RG_VIO18_PG_ENB_MASK 0x1
+#define RG_VIO18_PG_ENB_SHIFT 0x5
+#define RG_VIO28_PG_ENB_MASK 0x1
+#define RG_VIO28_PG_ENB_SHIFT 0x4
+#define RG_VA1_PG_ENB_MASK 0x1
+#define RG_VA1_PG_ENB_SHIFT 0x3
+#define RG_VM12_1_PG_ENB_MASK 0x1
+#define RG_VM12_1_PG_ENB_SHIFT 0x2
+#define RG_VM12_2_PG_ENB_MASK 0x1
+#define RG_VM12_2_PG_ENB_SHIFT 0x1
+#define RG_VM12_INT_PG_ENB_MASK 0x1
+#define RG_VM12_INT_PG_ENB_SHIFT 0x0
+
+// (0x15) STRUP_VPG_EN2 (RW)
+#define STRUP_VPG_EN2_ADDR 0x15
+
+#define RG_STRUP_DIG_RSV_MASK 0xF
+#define RG_STRUP_DIG_RSV_SHIFT 0x4
+#define RG_VTCXO_PG_ENB_MASK 0x1
+#define RG_VTCXO_PG_ENB_SHIFT 0x0
+
+// (0x16) INT_CON0 (RW)
+#define INT_CON0_ADDR 0x16
+
+#define RG_OV_INT_EN_MASK 0x1
+#define RG_OV_INT_EN_SHIFT 0x7
+#define RG_CHRDET_INT_EN_MASK 0x1
+#define RG_CHRDET_INT_EN_SHIFT 0x6
+#define RG_BVALID_DET_INT_EN_MASK 0x1
+#define RG_BVALID_DET_INT_EN_SHIFT 0x5
+#define RG_VBATON_UNDET_INT_EN_MASK 0x1
+#define RG_VBATON_UNDET_INT_EN_SHIFT 0x4
+#define RG_THR_H_INT_EN_MASK 0x1
+#define RG_THR_H_INT_EN_SHIFT 0x3
+#define RG_THR_L_INT_EN_MASK 0x1
+#define RG_THR_L_INT_EN_SHIFT 0x2
+#define RG_PWRKEY_INT_EN_MASK 0x1
+#define RG_PWRKEY_INT_EN_SHIFT 0x1
+#define RG_WATCHDOG_INT_EN_MASK 0x1
+#define RG_WATCHDOG_INT_EN_SHIFT 0x0
+
+// (0x17) INT_CON1 (RW)
+#define INT_CON1_ADDR 0x17
+
+#define RG_FG_BAT_H_INT_EN_MASK 0x1
+#define RG_FG_BAT_H_INT_EN_SHIFT 0x7
+#define RG_FG_BAT_L_INT_EN_MASK 0x1
+#define RG_FG_BAT_L_INT_EN_SHIFT 0x6
+#define RG_HIGH_BAT_INT_EN_MASK 0x1
+#define RG_HIGH_BAT_INT_EN_SHIFT 0x5
+#define RG_LOW_BAT_INT_EN_MASK 0x1
+#define RG_LOW_BAT_INT_EN_SHIFT 0x4
+#define RG_SPKR_D_OC_INT_EN_MASK 0x1
+#define RG_SPKR_D_OC_INT_EN_SHIFT 0x3
+#define RG_SPKL_D_OC_INT_EN_MASK 0x1
+#define RG_SPKL_D_OC_INT_EN_SHIFT 0x2
+#define RG_SPKR_AB_OC_INT_EN_MASK 0x1
+#define RG_SPKR_AB_OC_INT_EN_SHIFT 0x1
+#define RG_SPKL_AB_OC_INT_EN_MASK 0x1
+#define RG_SPKL_AB_OC_INT_EN_SHIFT 0x0
+
+// (0x18) INT_CON2 (RW)
+#define INT_CON2_ADDR 0x18
+
+#define RG_HOMEKEY_INT_EN_MASK 0x1
+#define RG_HOMEKEY_INT_EN_SHIFT 0x5
+#define RG_VRF18_OC_INT_EN_MASK 0x1
+#define RG_VRF18_OC_INT_EN_SHIFT 0x4
+#define RG_VPA_OC_INT_EN_MASK 0x1
+#define RG_VPA_OC_INT_EN_SHIFT 0x3
+#define RG_LDO_OC_INT_EN_MASK 0x1
+#define RG_LDO_OC_INT_EN_SHIFT 0x2
+
+// (0x19) INT_STATUS5 (RO)
+#define INT_STATUS5_ADDR 0x19
+
+#define RG_OV_INT_STATUS_MASK 0x1
+#define RG_OV_INT_STATUS_SHIFT 0x7
+#define RG_CHRDET_INT_STATUS_MASK 0x1
+#define RG_CHRDET_INT_STATUS_SHIFT 0x6
+#define RG_BVALID_DET_INT_STATUS_MASK 0x1
+#define RG_BVALID_DET_INT_STATUS_SHIFT 0x5
+#define RG_VBATON_UNDET_INT_STATUS_MASK 0x1
+#define RG_VBATON_UNDET_INT_STATUS_SHIFT 0x4
+#define RG_THR_H_INT_STATUS_MASK 0x1
+#define RG_THR_H_INT_STATUS_SHIFT 0x3
+#define RG_THR_L_INT_STATUS_MASK 0x1
+#define RG_THR_L_INT_STATUS_SHIFT 0x2
+#define RG_PWRKEY_INT_STATUS_MASK 0x1
+#define RG_PWRKEY_INT_STATUS_SHIFT 0x1
+#define RG_WATCHDOG_INT_STATUS_MASK 0x1
+#define RG_WATCHDOG_INT_STATUS_SHIFT 0x0
+
+// (0x1A) INT_STATUS6 (RO)
+#define INT_STATUS6_ADDR 0x1A
+
+#define RG_FG_BAT_H_INT_STATUS_MASK 0x1
+#define RG_FG_BAT_H_INT_STATUS_SHIFT 0x7
+#define RG_FG_BAT_L_INT_STATUS_MASK 0x1
+#define RG_FG_BAT_L_INT_STATUS_SHIFT 0x6
+#define RG_HIGH_BAT_INT_STATUS_MASK 0x1
+#define RG_HIGH_BAT_INT_STATUS_SHIFT 0x5
+#define RG_LOW_BAT_INT_STATUS_MASK 0x1
+#define RG_LOW_BAT_INT_STATUS_SHIFT 0x4
+#define RG_SPKR_D_OC_INT_STATUS_MASK 0x1
+#define RG_SPKR_D_OC_INT_STATUS_SHIFT 0x3
+#define RG_SPKL_D_OC_INT_STATUS_MASK 0x1
+#define RG_SPKL_D_OC_INT_STATUS_SHIFT 0x2
+#define RG_SPKR_AB_OC_INT_STATUS_MASK 0x1
+#define RG_SPKR_AB_OC_INT_STATUS_SHIFT 0x1
+#define RG_SPKL_AB_OC_INT_STATUS_MASK 0x1
+#define RG_SPKL_AB_OC_INT_STATUS_SHIFT 0x0
+
+// (0x1B) INT_STATUS7 (RO)
+#define INT_STATUS7_ADDR 0x1B
+
+#define RG_HOMEKEY_INT_STATUS_MASK 0x1
+#define RG_HOMEKEY_INT_STATUS_SHIFT 0x5
+#define RG_VRF18_OC_INT_STATUS_MASK 0x1
+#define RG_VRF18_OC_INT_STATUS_SHIFT 0x4
+#define RG_VPA_OC_INT_STATUS_MASK 0x1
+#define RG_VPA_OC_INT_STATUS_SHIFT 0x3
+#define RG_LDO_OC_INT_STATUS_MASK 0x1
+#define RG_LDO_OC_INT_STATUS_SHIFT 0x2
+
+// (0x21) CHR_CON0 (RO/RW)
+#define CHR_CON0_ADDR 0x21
+
+#define VCDT_HV_DET_MASK 0x1
+#define VCDT_HV_DET_SHIFT 0x7
+#define VCDT_LV_DET_MASK 0x1
+#define VCDT_LV_DET_SHIFT 0x6
+#define CHRDET_MASK 0x1
+#define CHRDET_SHIFT 0x5
+#define CHR_EN_MASK 0x1
+#define CHR_EN_SHIFT 0x4
+#define CSDAC_EN_MASK 0x1
+#define CSDAC_EN_SHIFT 0x3
+#define PCHR_AUTO_MASK 0x1
+#define PCHR_AUTO_SHIFT 0x2
+#define CHR_LDO_DET_MASK 0x1
+#define CHR_LDO_DET_SHIFT 0x1
+#define VCDT_HV_EN_MASK 0x1
+#define VCDT_HV_EN_SHIFT 0x0
+
+// (0x22) CHR_CON1 (RW)
+#define CHR_CON1_ADDR 0x22
+
+#define VCDT_HV_VTH_MASK 0xF
+#define VCDT_HV_VTH_SHIFT 0x4
+#define VCDT_LV_VTH_MASK 0xF
+#define VCDT_LV_VTH_SHIFT 0x0
+
+// (0x23) CHR_CON2 (RO/RW)
+#define CHR_CON2_ADDR 0x23
+
+#define VBAT_CC_DET_MASK 0x1
+#define VBAT_CC_DET_SHIFT 0x7
+#define VBAT_CV_DET_MASK 0x1
+#define VBAT_CV_DET_SHIFT 0x6
+#define CS_DET_MASK 0x1
+#define CS_DET_SHIFT 0x5
+#define CS_EN_MASK 0x1
+#define CS_EN_SHIFT 0x3
+#define VBAT_CC_EN_MASK 0x1
+#define VBAT_CC_EN_SHIFT 0x2
+#define VBAT_CV_EN_MASK 0x1
+#define VBAT_CV_EN_SHIFT 0x1
+
+// (0x24) CHR_CON3 (RW)
+#define CHR_CON3_ADDR 0x24
+
+#define VBAT_CC_VTH_MASK 0x3
+#define VBAT_CC_VTH_SHIFT 0x6
+#define VBAT_CV_VTH_MASK 0x1F
+#define VBAT_CV_VTH_SHIFT 0x0
+
+// (0x25) CHR_CON4 (RW)
+#define CHR_CON4_ADDR 0x25
+
+#define CS_VTH_MASK 0xF
+#define CS_VTH_SHIFT 0x0
+
+// (0x26) CHR_CON5 (RW)
+#define CHR_CON5_ADDR 0x26
+
+#define TOLTC_MASK 0x7
+#define TOLTC_SHIFT 0x4
+#define TOHTC_MASK 0x7
+#define TOHTC_SHIFT 0x0
+
+// (0x27) CHR_CON6 (RO/RW)
+#define CHR_CON6_ADDR 0x27
+
+#define VBAT_OV_DET_MASK 0x1
+#define VBAT_OV_DET_SHIFT 0x6
+#define VBAT_OV_DEG_MASK 0x1
+#define VBAT_OV_DEG_SHIFT 0x5
+#define VBAT_OV_VTH_MASK 0x3
+#define VBAT_OV_VTH_SHIFT 0x1
+#define VBAT_OV_EN_MASK 0x1
+#define VBAT_OV_EN_SHIFT 0x0
+
+// (0x28) CHR_CON7 (RO/RW)
+#define CHR_CON7_ADDR 0x28
+
+#define BATON_UNDET_MASK 0x1
+#define BATON_UNDET_SHIFT 0x7
+#define BATON_HT_TRIM_MASK 0x7
+#define BATON_HT_TRIM_SHIFT 0x4
+#define BATON_HT_EN_MASK 0x1
+#define BATON_HT_EN_SHIFT 0x2
+#define BATON_EN_MASK 0x1
+#define BATON_EN_SHIFT 0x1
+
+// (0x29) CHR_CON8 (RW)
+#define CHR_CON8_ADDR 0x29
+
+#define CSDAC_DAT_H_MASK 0x3
+#define CSDAC_DAT_H_SHIFT 0x0
+
+// (0x2A) CHR_CON9 (RW)
+#define CHR_CON9_ADDR 0x2A
+
+#define CSDAC_DAT_L_MASK 0xFF
+#define CSDAC_DAT_L_SHIFT 0x0
+
+// (0x2B) CHR_CONA (RO/RW)
+#define CHR_CONA_ADDR 0x2B
+
+#define OTG_BVALID_MASK 0x1
+#define OTG_BVALID_SHIFT 0x6
+#define OTG_BVALID_EN_MASK 0x1
+#define OTG_BVALID_EN_SHIFT 0x5
+#define PCHR_FLAG_EN_MASK 0x1
+#define PCHR_FLAG_EN_SHIFT 0x4
+#define PCHR_FLAG_OUT_MASK 0xF
+#define PCHR_FLAG_OUT_SHIFT 0x0
+
+// (0x2C) CHR_CONB (RW)
+#define CHR_CONB_ADDR 0x2C
+
+#define PCHR_FLAG_SEL_MASK 0x3F
+#define PCHR_FLAG_SEL_SHIFT 0x0
+
+// (0x2D) CHR_CONC (RW)
+#define CHR_CONC_ADDR 0x2D
+
+#define PCHR_FT_CTRL_MASK 0x7
+#define PCHR_FT_CTRL_SHIFT 0x4
+#define PCHR_RST_MASK 0x1
+#define PCHR_RST_SHIFT 0x2
+#define CSDAC_TEST_MASK 0x1
+#define CSDAC_TEST_SHIFT 0x1
+#define PCHR_TEST_MASK 0x1
+#define PCHR_TEST_SHIFT 0x0
+
+// (0x2E) CHR_COND (RW)
+#define CHR_COND_ADDR 0x2E
+
+#define CHRWDT_EN_MASK 0x1
+#define CHRWDT_EN_SHIFT 0x4
+#define CHRWDT_TD_MASK 0xF
+#define CHRWDT_TD_SHIFT 0x0
+
+// (0x2F) CHR_CONE (RW)
+#define CHR_CONE_ADDR 0x2F
+
+#define PCHR_RV_MASK 0xFF
+#define PCHR_RV_SHIFT 0x0
+
+// (0x30) CHR_CONF (RO/RW)
+#define CHR_CONF_ADDR 0x30
+
+#define CHRWDT_OUT_MASK 0x1
+#define CHRWDT_OUT_SHIFT 0x2
+#define CHRWDT_FLAG_WR_MASK 0x1
+#define CHRWDT_FLAG_WR_SHIFT 0x1
+#define CHRWDT_INT_EN_MASK 0x1
+#define CHRWDT_INT_EN_SHIFT 0x0
+
+// (0x31) CHR_CON11 (RW)
+#define CHR_CON11_ADDR 0x31
+
+#define ADCIN_VCHR_EN_MASK 0x1
+#define ADCIN_VCHR_EN_SHIFT 0x6
+#define ADCIN_VSEN_EN_MASK 0x1
+#define ADCIN_VSEN_EN_SHIFT 0x5
+#define ADCIN_VBAT_EN_MASK 0x1
+#define ADCIN_VBAT_EN_SHIFT 0x4
+#define USBDL_SET_MASK 0x1
+#define USBDL_SET_SHIFT 0x3
+#define USBDL_RST_MASK 0x1
+#define USBDL_RST_SHIFT 0x2
+#define UVLO_VTHL_MASK 0x3
+#define UVLO_VTHL_SHIFT 0x0
+
+// (0x32) CHR_CON12 (RW)
+#define CHR_CON12_ADDR 0x32
+
+#define BGR_UNCHOP_MASK 0x1
+#define BGR_UNCHOP_SHIFT 0x5
+#define BGR_UNCHOP_PH_MASK 0x1
+#define BGR_UNCHOP_PH_SHIFT 0x4
+#define BGR_RSEL_MASK 0x7
+#define BGR_RSEL_SHIFT 0x0
+
+// (0x33) CHR_CON13 (RO/RW)
+#define BC11_CMP_OUT_MASK 0x1
+#define BC11_CMP_OUT_SHIFT 0x7
+#define RG_BC11_VSRC_EN_MASK 0x3
+#define RG_BC11_VSRC_EN_SHIFT 0x2
+#define BC11_RST_MASK 0x1
+#define BC11_RST_SHIFT 0x1
+#define BC11_BB_CTRL_MASK 0x1
+#define BC11_BB_CTRL_SHIFT 0x0
+
+// (0x34) CHR_CON14 (RW)
+#define BC11_BIAS_EN_MASK 0x1
+#define BC11_BIAS_EN_SHIFT 0x7
+#define BC11_IPU_EN_MASK 0x3
+#define BC11_IPU_EN_SHIFT 0x5
+#define BC11_IPD_EN_MASK 0x3
+#define BC11_IPD_EN_SHIFT 0x3
+#define BC11_CMP_EN_MASK 0x3
+#define BC11_CMP_EN_SHIFT 0x1
+#define BC11_VREF_VTH_MASK 0x1
+#define BC11_VREF_VTH_SHIFT 0x0
+
+// (0x35) CHR_CON15 (RW)
+#define CSDAC_STP_DEC_MASK 0x7
+#define CSDAC_STP_DEC_SHIFT 0x4
+#define CSDAC_STP_INC_MASK 0x7
+#define CSDAC_STP_INC_SHIFT 0x0
+
+// (0x36) CHR_CON16 (RW)
+#define CSDAC_STP_MASK 0x7
+#define CSDAC_STP_SHIFT 0x4
+#define CSDAC_DLY_MASK 0x7
+#define CSDAC_DLY_SHIFT 0x0
+
+// (0x37) CHR_CON17 (RW)
+#define RG_CHRIND_DIMMING_MASK 0x1
+#define RG_CHRIND_DIMMING_SHIFT 0x7
+#define RG_CHRIND_ON_MASK 0x1
+#define RG_CHRIND_ON_SHIFT 0x6
+#define RG_LOW_ICH_DB_MASK 0x3F
+#define RG_LOW_ICH_DB_SHIFT 0x0
+
+// (0x38) CHR_CON18 (RW)
+#define RG_ULC_DET_EN_MASK 0x1
+#define RG_ULC_DET_EN_SHIFT 0x7
+#define RG_HWCV_EN_MASK 0x1
+#define RG_HWCV_EN_SHIFT 0x6
+#define BATON_TDET_EN_MASK 0x1
+#define BATON_TDET_EN_SHIFT 0x5
+#define TRACKING_EN_MASK 0x1
+#define TRACKING_EN_SHIFT 0x4
+#define CSDAC_MODE_MASK 0x1
+#define CSDAC_MODE_SHIFT 0x2
+#define VCDT_MODE_MASK 0x1
+#define VCDT_MODE_SHIFT 0x1
+#define CV_MODE_MASK 0x1
+#define CV_MODE_SHIFT 0x0
+
+// (0x39) CHR_CON19 (RW)
+#define RG_ICHRG_TRIM_MASK 0xF
+#define RG_ICHRG_TRIM_SHIFT 0x4
+#define RG_BGR_TRIM_EN_MASK 0x1
+#define RG_BGR_TRIM_EN_SHIFT 0x0
+
+// (0x3A) CHR_CON1A (RW)
+#define RG_BGR_TRIM_MASK 0x1F
+#define RG_BGR_TRIM_SHIFT 0x0
+
+// (0x3B) CHR_CON1B (RW)
+#define RG_OVP_TRIM_MASK 0xF
+#define RG_OVP_TRIM_SHIFT 0x0
+
+// (0x3C) CHR_CON1C (RW)
+#define CHR_RSV0_MASK 0x1
+#define CHR_RSV0_SHIFT 0x7
+#define RG_BGR_TEST_RSTB_MASK 0x1
+#define RG_BGR_TEST_RSTB_SHIFT 0x6
+#define RG_BGR_TEST_EN_MASK 0x1
+#define RG_BGR_TEST_EN_SHIFT 0x5
+#define RG_CHR_OSC_TRIM_MASK 0x1F
+#define RG_CHR_OSC_TRIM_SHIFT 0x0
+
+// (0x3D) CHR_CON1D (RW)
+#define CHR_RSV1_MASK 0x3F
+#define CHR_RSV1_SHIFT 0x2
+#define RG_DAC_USBDL_MAX_9_8_MASK 0x3
+#define RG_DAC_USBDL_MAX_9_8_SHIFT 0x0
+
+// (0x3E) CHR_CON1E (RW)
+#define RG_DAC_USBDL_MAX_7_0_MASK 0xFF
+#define RG_DAC_USBDL_MAX_7_0_SHIFT 0x0
+
+// (0x3F) VPROC_CON0 (RW)
+#define RG_VPROC_CSL_MASK 0x3
+#define RG_VPROC_CSL_SHIFT 0x6
+#define RG_VPROC_CSR_MASK 0x3
+#define RG_VPROC_CSR_SHIFT 0x4
+#define RG_VPROC_CC_MASK 0x3
+#define RG_VPROC_CC_SHIFT 0x2
+#define RG_VPROC_RZSEL_MASK 0x3
+#define RG_VPROC_RZSEL_SHIFT 0x0
+
+// (0x40) VPROC_CON1 (RW)
+#define RG_VPROC_SLP_MASK 0x3
+#define RG_VPROC_SLP_SHIFT 0x6
+#define RG_VPROC_ZX_OS_MASK 0x3
+#define RG_VPROC_ZX_OS_SHIFT 0x4
+#define RG_VPROC_SLEW_MASK 0x3
+#define RG_VPROC_SLEW_SHIFT 0x2
+#define RG_VPROC_SLEW_NMOS_MASK 0x3
+#define RG_VPROC_SLEW_NMOS_SHIFT 0x0
+
+// (0x41) VPROC_CON2 (RW)
+#define RG_VPROC_AVP_OS_MASK 0x7
+#define RG_VPROC_AVP_OS_SHIFT 0x4
+#define RG_VPROC_AVP_EN_MASK 0x1
+#define RG_VPROC_AVP_EN_SHIFT 0x1
+#define RG_VPROC_MODESET_MASK 0x1
+#define RG_VPROC_MODESET_SHIFT 0x0
+
+// (0x42) VPROC_CON3 (RO/RW)
+#define VPROC_CON3_ADDR 0x42
+
+#define QI_VPROC_EN_MASK 0x1
+#define QI_VPROC_EN_SHIFT 0x7
+#define RG_VPROC_EN_MASK 0x1
+#define RG_VPROC_EN_SHIFT 0x0
+
+// (0x43) VPROC_CON4 (RW)
+#define RG_VPROC_BURST_MASK 0x3
+#define RG_VPROC_BURST_SHIFT 0x4
+#define RG_VPROC_VFBADJ_MASK 0x7
+#define RG_VPROC_VFBADJ_SHIFT 0x1
+#define RG_VPROC_NDIS_EN_MASK 0x1
+#define RG_VPROC_NDIS_EN_SHIFT 0x0
+
+// (0x44) VPROC_CON5 (RW)
+#define VPROC_CON5_ADDR 0x44
+
+#define RG_VPROC_VOSEL_MASK 0x1F
+#define RG_VPROC_VOSEL_SHIFT 0x0
+
+// (0x45) VPROC_CON6 (RW)
+#define VPROC_VOSEL_SRCLKEN0_MASK 0x1F
+#define VPROC_VOSEL_SRCLKEN0_SHIFT 0x0
+
+// (0x46) VPROC_CON7 (RW)
+#define VPROC_VOSEL_SRCLKEN1_MASK 0x1F
+#define VPROC_VOSEL_SRCLKEN1_SHIFT 0x0
+
+// (0x47) VPROC_CON8 (RW)
+#define VPROC_VOSEL_DVS00_MASK 0x1F
+#define VPROC_VOSEL_DVS00_SHIFT 0x0
+
+// (0x48) VPROC_CON9 (RW)
+#define VPROC_VOSEL_DVS01_MASK 0x1F
+#define VPROC_VOSEL_DVS01_SHIFT 0x0
+
+// (0x49) VPROC_CONA (RW)
+#define VPROC_VOSEL_DVS10_MASK 0x1F
+#define VPROC_VOSEL_DVS10_SHIFT 0x0
+
+// (0x4A) VPROC_CONB (RW)
+#define VPROC_VOSEL_DVS11_MASK 0x1F
+#define VPROC_VOSEL_DVS11_SHIFT 0x0
+
+// (0x4B) VPROC_CONC (RW)
+#define RG_VPROC_RSV_MASK 0xF
+#define RG_VPROC_RSV_SHIFT 0x4
+#define RG_VPROC_VOSEL_SFCHG_EN_MASK 0x1
+#define RG_VPROC_VOSEL_SFCHG_EN_SHIFT 0x2
+#define RG_VPROC_CTRL_MASK 0x3
+#define RG_VPROC_CTRL_SHIFT 0x0
+
+// (0x4C) VPROC_COND (RW)
+#define RG_SMPS_TESTMODE_MASK 0x3F
+#define RG_SMPS_TESTMODE_SHIFT 0x0
+
+// (0x4D) VPROC_CONE (RW)
+#define RG_SMPS_RSV_MASK 0xFF
+#define RG_SMPS_RSV_SHIFT 0x0
+
+// (0x4E) VPROC_CONF (RO)
+#define QI_VPROC_VOSEL_MASK 0x1F
+#define QI_VPROC_VOSEL_SHIFT 0x0
+
+// (0x4F) BUCK_RSV (RW)
+#define RG_BUCK_RSV_MASK 0xFF
+#define RG_BUCK_RSV_SHIFT 0x0
+
+// (0x52) VCORE_CON0 (RW)
+#define RG_VCORE_CSL_MASK 0x3
+#define RG_VCORE_CSL_SHIFT 0x6
+#define RG_VCORE_CSR_MASK 0x3
+#define RG_VCORE_CSR_SHIFT 0x4
+#define RG_VCORE_CC_MASK 0x3
+#define RG_VCORE_CC_SHIFT 0x2
+#define RG_VCORE_RZSEL_MASK 0x3
+#define RG_VCORE_RZSEL_SHIFT 0x0
+
+// (0x53) VCORE_CON1 (RW)
+#define RG_VCORE_SLP_MASK 0x3
+#define RG_VCORE_SLP_SHIFT 0x6
+#define RG_VCORE_ZX_OS_MASK 0x3
+#define RG_VCORE_ZX_OS_SHIFT 0x4
+#define RG_VCORE_SLEW_MASK 0x3
+#define RG_VCORE_SLEW_SHIFT 0x2
+#define RG_VCORE_SLEW_NMOS_MASK 0x3
+#define RG_VCORE_SLEW_NMOS_SHIFT 0x0
+
+// (0x54) VCORE_CON2 (RW)
+#define RG_VCORE_AVP_OS_MASK 0x7
+#define RG_VCORE_AVP_OS_SHIFT 0x4
+#define RG_VCORE_AVP_EN_MASK 0x1
+#define RG_VCORE_AVP_EN_SHIFT 0x1
+#define RG_VCORE_MODESET_MASK 0x1
+#define RG_VCORE_MODESET_SHIFT 0x0
+
+// (0x55) VCORE_CON3 (RO/RW)
+#define VCORE_CON3_ADDR 0x55
+
+#define QI_VCORE_EN_MASK 0x1
+#define QI_VCORE_EN_SHIFT 0x7
+#define RG_VCORE_EN_MASK 0x1
+#define RG_VCORE_EN_SHIFT 0x0
+
+// (0x56) VCORE_CON4 (RW)
+#define RG_VCORE_BURST_MASK 0x3
+#define RG_VCORE_BURST_SHIFT 0x4
+#define RG_VCORE_VFBADJ_MASK 0x7
+#define RG_VCORE_VFBADJ_SHIFT 0x1
+#define RG_VCORE_NDIS_EN_MASK 0x1
+#define RG_VCORE_NDIS_EN_SHIFT 0x0
+
+// (0x57) VCORE_CON5 (RW)
+#define VCORE_CON5_ADDR 0x57
+
+#define RG_VCORE_VOSEL_MASK 0x1F
+#define RG_VCORE_VOSEL_SHIFT 0x0
+
+// (0x58) VCORE_CON6 (RW)
+#define RG_VCORE_VOSEL_CON1_MASK 0x1F
+#define RG_VCORE_VOSEL_CON1_SHIFT 0x0
+
+// (0x59) VCORE_CON7 (RW)
+#define RG_VCORE_RSV_MASK 0xF
+#define RG_VCORE_RSV_SHIFT 0x4
+#define RG_VCORE_VOSEL_SFCHG_EN_MASK 0x1
+#define RG_VCORE_VOSEL_SFCHG_EN_SHIFT 0x2
+#define RG_VCORE_CTRL_MASK 0x1
+#define RG_VCORE_CTRL_SHIFT 0x0
+
+// (0x5A) VCORE_CON8 (RO)
+#define QI_VCORE_VOSEL_MASK 0x1F
+#define QI_VCORE_VOSEL_SHIFT 0x0
+
+// (0x5D) VRF18_CON0 (RW)
+#define RG_VRF18_CSL_MASK 0x3
+#define RG_VRF18_CSL_SHIFT 0x6
+#define RG_VRF18_CSR_MASK 0x3
+#define RG_VRF18_CSR_SHIFT 0x4
+#define RG_VRF18_CC_MASK 0x3
+#define RG_VRF18_CC_SHIFT 0x2
+#define RG_VRF18_RZSEL_MASK 0x3
+#define RG_VRF18_RZSEL_SHIFT 0x0
+
+// (0x5E) VRF18_CON1 (RW)
+#define RG_VRF18_SLP_MASK 0x3
+#define RG_VRF18_SLP_SHIFT 0x6
+#define RG_VRF18_ZX_OS_MASK 0x3
+#define RG_VRF18_ZX_OS_SHIFT 0x4
+#define RG_VRF18_SLEW_MASK 0x3
+#define RG_VRF18_SLEW_SHIFT 0x2
+#define RG_VRF18_SLEW_NMOS_MASK 0x3
+#define RG_VRF18_SLEW_NMOS_SHIFT 0x0
+
+// (0x5F) VRF18_CON2 (RW)
+#define VRF18_CON2_ADDR 0x5F
+
+#define RG_VRF18_AVP_EN_MASK 0x1
+#define RG_VRF18_AVP_EN_SHIFT 0x1
+#define RG_VRF18_MODESET_MASK 0x1
+#define RG_VRF18_MODESET_SHIFT 0x0
+
+// (0x60) VRF18_CON3 (RO/RW)
+#define VRF18_CON3_ADDR 0x60
+
+#define QI_VRF18_EN_MASK 0x1
+#define QI_VRF18_EN_SHIFT 0x7
+#define RG_VRF18_ON_CTRL_MASK 0x1
+#define RG_VRF18_ON_CTRL_SHIFT 0x1
+#define RG_VRF18_EN_MASK 0x1
+#define RG_VRF18_EN_SHIFT 0x0
+
+// (0x61) VRF18_CON4 (RW)
+#define RG_VRF18_STBTD_MASK 0x3
+#define RG_VRF18_STBTD_SHIFT 0x6
+#define RG_VRF18_BURST_MASK 0x3
+#define RG_VRF18_BURST_SHIFT 0x4
+#define RG_VRF18_OCFB_EN_MASK 0x1
+#define RG_VRF18_OCFB_EN_SHIFT 0x1
+#define RG_VRF18_NDIS_EN_MASK 0x1
+#define RG_VRF18_NDIS_EN_SHIFT 0x0
+
+// (0x62) VRF18_CON5 (RW)
+#define VRF18_CON5_ADDR 0x62
+
+#define RG_VRF18_VOSEL_MASK 0x1F
+#define RG_VRF18_VOSEL_SHIFT 0x0
+
+// (0x63) VRF18_CON6 (RW)
+#define RG_VRF18_RSV_MASK 0xF
+#define RG_VRF18_RSV_SHIFT 0x0
+
+// (0x62) VRF18_CON7 (RO)
+#define RO_QI_VRF18_OC_STATUS_MASK 0x1
+#define RO_QI_VRF18_OC_STATUS_SHIFT 0x0
+
+// (0x67) VM_CON0 (RW)
+#define RG_VIO18_CSL_MASK 0x3
+#define RG_VIO18_CSL_SHIFT 0x6
+#define RG_VIO18_CSR_MASK 0x3
+#define RG_VIO18_CSR_SHIFT 0x4
+#define RG_VIO18_CC_MASK 0x3
+#define RG_VIO18_CC_SHIFT 0x2
+#define RG_VIO18_RZSEL_MASK 0x3
+#define RG_VIO18_RZSEL_SHIFT 0x0
+
+// (0x68) VM_CON1 (RW)
+#define RG_VIO18_SLP_MASK 0x3
+#define RG_VIO18_SLP_SHIFT 0x6
+#define RG_VIO18_ZX_OS_MASK 0x3
+#define RG_VIO18_ZX_OS_SHIFT 0x4
+#define RG_VIO18_SLEW_MASK 0x3
+#define RG_VIO18_SLEW_SHIFT 0x2
+#define RG_VIO18_SELW_NMOS_MASK 0x3
+#define RG_VIO18_SELW_NMOS_SHIFT 0x0
+
+// (0x69) VM_CON2 (RW)
+#define RG_VIO18_AVP_EN_MASK 0x1
+#define RG_VIO18_AVP_EN_SHIFT 0x1
+#define RG_VIO18_MODESET_MASK 0x1
+#define RG_VIO18_MODESET_SHIFT 0x0
+
+// (0x6A) VM_CON3 (RO/RW)
+#define VM_CON3_ADDR 0x6A
+
+#define NI_VIO18_EN_MASK 0x1
+#define NI_VIO18_EN_SHIFT 0x7
+#define RG_VIO18_EN_MASK 0x1
+#define RG_VIO18_EN_SHIFT 0x0
+
+// (0x6B) VM_CON4 (RW)
+#define RG_VIO18_BURST_MASK 0x3
+#define RG_VIO18_BURST_SHIFT 0x4
+#define RG_VIO18_NDIS_EN_MASK 0x1
+#define RG_VIO18_NDIS_EN_SHIFT 0x0
+
+// (0x6C) VM_CON5 (RW)
+#define VM_CON5_ADDR 0x6C
+
+#define RG_VIO18_VOSEL_MASK 0x1F
+#define RG_VIO18_VOSEL_SHIFT 0x0
+
+// (0x6D) VM_CON6 (RW)
+#define RG_VIO18_RSV_MASK 0xF
+#define RG_VIO18_RSV_SHIFT 0x4
+
+// (0x70) VPA_CON0 (RW)
+#define RG_VPA_CSL_MASK 0x3
+#define RG_VPA_CSL_SHIFT 0x6
+#define RG_VPA_CSR_MASK 0x3
+#define RG_VPA_CSR_SHIFT 0x4
+#define RG_VPA_CC_MASK 0x3
+#define RG_VPA_CC_SHIFT 0x2
+#define RG_VPA_RZSEL_MASK 0x3
+#define RG_VPA_RZSEL_SHIFT 0x0
+
+// (0x71) VPA_CON1 (RW)
+#define RG_VPA_SLP_MASK 0x3
+#define RG_VPA_SLP_SHIFT 0x6
+#define RG_VPA_ZX_OS_MASK 0x3
+#define RG_VPA_ZX_OS_SHIFT 0x4
+#define RG_VPA_SLEW_MASK 0x3
+#define RG_VPA_SLEW_SHIFT 0x2
+#define RG_VPA_SLEW_NMOS_MASK 0x3
+#define RG_VPA_SLEW_NMOS_SHIFT 0x0
+
+// (0x72) VPA_CON2 (RW)
+#define RG_VPA_AVP_EN_MASK 0x1
+#define RG_VPA_AVP_EN_SHIFT 0x1
+#define RG_VPA_MODESET_MASK 0x1
+#define RG_VPA_MODESET_SHIFT 0x0
+
+// (0x73) VPA_CON3 (RW)
+#define VPA_CON3_ADDR 0x73
+
+#define RG_VPA_EN_MASK 0x1
+#define RG_VPA_EN_SHIFT 0x0
+
+// (0x74) VPA_CON4 (RW)
+#define RG_VPA_BURST_MASK 0x3
+#define RG_VPA_BURST_SHIFT 0x4
+#define RG_VPA_NDIS_EN_MASK 0x1
+#define RG_VPA_NDIS_EN_SHIFT 0x0
+
+// (0x75) VPA_CON5 (RW)
+#define VPA_CON5_ADDR 0x75
+
+#define RG_VPA_VOSEL_MASK 0x1F
+#define RG_VPA_VOSEL_SHIFT 0x0
+
+// (0x76) VPA_CON6 (RW)
+#define VPA_CON6_ADDR 0x76
+
+#define RG_PASEL_SET0_MASK 0x1F
+#define RG_PASEL_SET0_SHIFT 0x0
+
+// (0x77) VPA_CON7 (RW)
+#define VPA_CON7_ADDR 0x77
+
+#define RG_PASEL_SET1_MASK 0x1F
+#define RG_PASEL_SET1_SHIFT 0x0
+
+// (0x78) VPA_CON8 (RW)
+#define VPA_CON8_ADDR 0x78
+
+#define RG_PASEL_SET2_MASK 0x1F
+#define RG_PASEL_SET2_SHIFT 0x0
+
+// (0x79) VPA_CON9 (RW)
+#define VPA_CON9_ADDR 0x79
+
+#define RG_PASEL_SET3_MASK 0x1F
+#define RG_PASEL_SET3_SHIFT 0x0
+
+// (0x7A) VPA_CONA (RW)
+#define VPA_CONA_ADDR 0x7A
+
+#define RG_PASEL_SET4_MASK 0x1F
+#define RG_PASEL_SET4_SHIFT 0x0
+
+// (0x7B) VPA_CONB (RW)
+#define VPA_CONB_ADDR 0x7B
+
+#define RG_PASEL_SET5_MASK 0x1F
+#define RG_PASEL_SET5_SHIFT 0x0
+
+// (0x7C) VPA_CONC (RW)
+#define VPA_CONC_ADDR 0x7C
+
+#define RG_PASEL_SET6_MASK 0x1F
+#define RG_PASEL_SET6_SHIFT 0x0
+
+// (0x7D) VPA_COND (RW)
+#define VPA_COND_ADDR 0x7D
+
+#define RG_PASEL_SET7_MASK 0x1F
+#define RG_PASEL_SET7_SHIFT 0x0
+
+// (0x7E) VPA_CONE (RW)
+#define VPA_CONE_ADDR 0x7E
+
+#define RG_VPA_RSV_MASK 0xF
+#define RG_VPA_RSV_SHIFT 0x4
+#define RG_VPA_CTRL_MASK 0x1
+#define RG_VPA_CTRL_SHIFT 0x0
+
+// (0x7F) VPA_CONF (RO)
+#define QI_VPA_VOSEL_MASK 0x1F
+#define QI_VPA_VOSEL_SHIFT 0x0
+
+// (0x82) DIGLDO_CON0 (RW)
+#define DIGLDO_CON0_ADDR 0x82
+
+#define RG_VM12_1_CAL_MASK 0xF
+#define RG_VM12_1_CAL_SHIFT 0x0
+
+// (0x83) DIGLDO_CON1 (RO/RW)
+#define DIGLDO_CON1_ADDR 0x83
+
+#define QI_VM12_1_EN_MASK 0x1
+#define QI_VM12_1_EN_SHIFT 0x7
+#define VM12_1_EN_MASK 0x1
+#define VM12_1_EN_SHIFT 0x0
+
+// (0x84) DIGLDO_CON2 (RW)
+#define RG_VM12_1_STBTD_MASK 0x3
+#define RG_VM12_1_STBTD_SHIFT 0x4
+#define RG_VM12_1_OCFB_EN_MASK 0x1
+#define RG_VM12_1_OCFB_EN_SHIFT 0x1
+#define RG_VM12_1_NDIS_EN_MASK 0x1
+#define RG_VM12_1_NDIS_EN_SHIFT 0x0
+
+// (0x85) DIGLDO_CON3 (RO/RW)
+#define QI_VM12_1_MODE_MASK 0x1
+#define QI_VM12_1_MODE_SHIFT 0x7
+#define VM12_1_LP_SET_MASK 0x1
+#define VM12_1_LP_SET_SHIFT 0x1
+#define VM12_1_LP_SEL_MASK 0x1
+#define VM12_1_LP_SEL_SHIFT 0x0
+
+// (0x86) DIGLDO_CON4 (RW)
+#define DIGLDO_CON4_ADDR 0x86
+
+#define RG_VM12_2_CAL_MASK 0xF
+#define RG_VM12_2_CAL_SHIFT 0x0
+
+// (0x87) DIGLDO_CON5 (RO/RW)
+#define DIGLDO_CON5_ADDR 0x87
+
+#define QI_VM12_2_EN_MASK 0x1
+#define QI_VM12_2_EN_SHIFT 0x7
+#define VM12_2_EN_MASK 0x1
+#define VM12_2_EN_SHIFT 0x0
+
+// (0x88) DIGLDO_CON6 (RW)
+#define RG_VM12_2_STBTD_MASK 0x3
+#define RG_VM12_2_STBTD_SHIFT 0x4
+#define RG_VM12_2_OCFB_EN_MASK 0x1
+#define RG_VM12_2_OCFB_EN_SHIFT 0x1
+#define RG_VM12_2_NDIS_EN_MASK 0x1
+#define RG_VM12_2_NDIS_EN_SHIFT 0x0
+
+// (0x89) DIGLDO_CON7 (RO/RW)
+#define QI_VM12_2_MODE_MASK 0x1
+#define QI_VM12_2_MODE_SHIFT 0x7
+#define VM12_2_LP_SET_MASK 0x1
+#define VM12_2_LP_SET_SHIFT 0x1
+#define VM12_2_LP_SEL_MASK 0x1
+#define VM12_2_LP_SEL_SHIFT 0x0
+
+// (0x8A) DIGLDO_CON8 (RW)
+#define DIGLDO_CON8_ADDR 0x8A
+
+#define RG_VM12_INT_CAL_MASK 0x1F
+#define RG_VM12_INT_CAL_SHIFT 0x0
+
+// (0x8B) DIGLDO_CON9 (RW)
+#define VM12_INT_SLEEP_MASK 0x1F
+#define VM12_INT_SLEEP_SHIFT 0x0
+
+// (0x8C) DIGLDO_CONA (RW)
+#define VM12_INT_LOW_BOUND_MASK 0x1F
+#define VM12_INT_LOW_BOUND_SHIFT 0x0
+
+// (0x8D) DIGLDO_CONB (RO/RW)
+#define DIGLDO_CONB_ADDR 0x8D
+
+#define QI_VM12_INT_EN_MASK 0x1
+#define QI_VM12_INT_EN_SHIFT 0x7
+#define VM12_INT_EN_MASK 0x1
+#define VM12_INT_EN_SHIFT 0x0
+
+// (0x8E) DIGLDO_CONC (RW)
+#define RG_VM12_INT_STBTD_MASK 0x3
+#define RG_VM12_INT_STBTD_SHIFT 0x4
+#define RG_VM12_INT_OCFB_EN_MASK 0x1
+#define RG_VM12_INT_OCFB_EN_SHIFT 0x1
+#define RG_VM12_INT_NDIS_EN_MASK 0x1
+#define RG_VM12_INT_NDIS_EN_SHIFT 0x0
+
+// (0x8F) DIGLDO_COND (RW)
+#define VM12_INT_CTRL_SEL_MASK 0x1
+#define VM12_INT_CTRL_SEL_SHIFT 0x4
+#define RG_VM12_INT_TRIM_MASK 0x7
+#define RG_VM12_INT_TRIM_SHIFT 0x1
+#define RG_VM12_INT_CAL_SFCHG_EN_MASK 0x1
+#define RG_VM12_INT_CAL_SFCHG_EN_SHIFT 0x0
+
+// (0x90) DIGLDO_CONE (RO/RW)
+#define QI_VM12_INT_MODE_MASK 0x1
+#define QI_VM12_INT_MODE_SHIFT 0x7
+#define VM12_INT_LP_SET_MASK 0x1
+#define VM12_INT_LP_SET_SHIFT 0x1
+#define VM12_INT_LP_SEL_MASK 0x1
+#define VM12_INT_LP_SEL_SHIFT 0x0
+
+// (0x91) DIGLDO_CONF (RW)
+#define DIGLDO_CONF_ADDR 0x91
+
+#define RG_VIO28_CAL_MASK 0xF
+#define RG_VIO28_CAL_SHIFT 0x0
+
+// (0x92) DIGLDO_CON10 (RO/RW)
+#define DIGLDO_CON10_ADDR 0x92
+
+#define QI_VIO28_EN_MASK 0x1
+#define QI_VIO28_EN_SHIFT 0x7
+#define VIO28_EN_MASK 0x1
+#define VIO28_EN_SHIFT 0x0
+
+// (0x93) DIGLDO_CON11 (RW)
+#define RG_VIO28_STBTD_MASK 0x3
+#define RG_VIO28_STBTD_SHIFT 0x4
+#define RG_VIO28_OCFB_EN_MASK 0x1
+#define RG_VIO28_OCFB_EN_SHIFT 0x1
+#define RG_VIO28_NDIS_EN_MASK 0x1
+#define RG_VIO28_NDIS_EN_SHIFT 0x0
+
+// (0x94) DIGLDO_CON12 (RW)
+#define DIGLDO_CON12_ADDR 0x94
+
+#define RG_VSIM_CAL_MASK 0xF
+#define RG_VSIM_CAL_SHIFT 0x0
+
+// (0x95) DIGLDO_CON13 (RW)
+#define DIGLDO_CON13_ADDR 0x95
+
+#define RG_VSIM_VOSEL_MASK 0x1
+#define RG_VSIM_VOSEL_SHIFT 0x4
+#define RG_VSIM_EN_MASK 0x1
+#define RG_VSIM_EN_SHIFT 0x0
+
+// (0x96) DIGLDO_CON14 (RW)
+#define RG_VSIM_STBTD_MASK 0x3
+#define RG_VSIM_STBTD_SHIFT 0x4
+#define RG_VSIM_OCFB_EN_MASK 0x1
+#define RG_VSIM_OCFB_EN_SHIFT 0x1
+#define RG_VSIM_NDIS_EN_MASK 0x1
+#define RG_VSIM_NDIS_EN_SHIFT 0x0
+
+// (0x97) DIGLDO_CON15 (RW)
+#define DIGLDO_CON15_ADDR 0x97
+
+#define RG_VSIM2_CAL_MASK 0xF
+#define RG_VSIM2_CAL_SHIFT 0x0
+
+// (0x98) DIGLDO_CON16 (RW)
+#define DIGLDO_CON16_ADDR 0x98
+
+#define RG_VSIM2_VOSEL_MASK 0x7
+#define RG_VSIM2_VOSEL_SHIFT 0x4
+#define RG_VSIM2_EN_MASK 0x1
+#define RG_VSIM2_EN_SHIFT 0x0
+
+// (0x99) DIGLDO_CON17 (RW)
+#define RG_VSIM2_STBTD_MASK 0x3
+#define RG_VSIM2_STBTD_SHIFT 0x4
+#define RG_VSIM2_OCFB_EN_MASK 0x1
+#define RG_VSIM2_OCFB_EN_SHIFT 0x1
+#define RG_VSIM2_NDIS_EN_MASK 0x1
+#define RG_VSIM2_NDIS_EN_SHIFT 0x0
+
+// (0x9A) DIGLDO_CON18 (RW)
+#define DIGLDO_CON18_ADDR 0x9A
+
+#define RG_VUSB_CAL_MASK 0xF
+#define RG_VUSB_CAL_SHIFT 0x0
+
+// (0x9B) DIGLDO_CON19 (RO/RW)
+#define DIGLDO_CON19_ADDR 0x9B
+
+#define QI_VUSB_EN_MASK 0x1
+#define QI_VUSB_EN_SHIFT 0x7
+#define RG_VUSB_EN_MASK 0x1
+#define RG_VUSB_EN_SHIFT 0x0
+
+// (0x9C) DIGLDO_CON1A (RW)
+#define RG_VUSB_STBTD_MASK 0x3
+#define RG_VUSB_STBTD_SHIFT 0x4
+#define RG_VUSB_OCFB_EN_MASK 0x1
+#define RG_VUSB_OCFB_EN_SHIFT 0x1
+#define RG_VUSB_NDIS_EN_MASK 0x1
+#define RG_VUSB_NDIS_EN_SHIFT 0x0
+
+// (0x9D) DIGLDO_CON1B (RW)
+#define DIGLDO_CON1B_ADDR 0x9D
+
+#define RG_VCAMD_CAL_MASK 0xF
+#define RG_VCAMD_CAL_SHIFT 0x0
+
+// (0x9E) DIGLDO_CON1C (RW)
+#define DIGLDO_CON1C_ADDR 0x9E
+
+#define RG_VCAMD_VOSEL_MASK 0x7
+#define RG_VCAMD_VOSEL_SHIFT 0x4
+#define RG_VCAMD_EN_MASK 0x1
+#define RG_VCAMD_EN_SHIFT 0x0
+
+// (0x9F) DIGLDO_CON1D (RW)
+#define RG_VCAMD_STBTD_MASK 0x3
+#define RG_VCAMD_STBTD_SHIFT 0x4
+#define RG_VCAMD_OCFB_EN_MASK 0x1
+#define RG_VCAMD_OCFB_EN_SHIFT 0x1
+#define RG_VCAMD_NDIS_EN_MASK 0x1
+#define RG_VCAMD_NDIS_EN_SHIFT 0x0
+
+// (0xA0) DIGLDO_CON1E (RW)
+#define DIGLDO_CON1E_ADDR 0xA0
+
+#define RG_VCAM_IO_CAL_MASK 0xF
+#define RG_VCAM_IO_CAL_SHIFT 0x0
+
+// (0xA1) DIGLDO_CON1F (RW)
+#define DIGLDO_CON1F_ADDR 0xA1
+
+#define RG_VCAM_IO_VOSEL_MASK 0x7
+#define RG_VCAM_IO_VOSEL_SHIFT 0x4
+#define RG_VCAM_IO_EN_MASK 0x1
+#define RG_VCAM_IO_EN_SHIFT 0x0
+
+// (0xA2) DIGLDO_CON20 (RW)
+#define RG_VCAM_IO_STBTD_MASK 0x3
+#define RG_VCAM_IO_STBTD_SHIFT 0x4
+#define RG_VCAM_IO_OCFB_EN_MASK 0x1
+#define RG_VCAM_IO_OCFB_EN_SHIFT 0x1
+#define RG_VCAM_IO_NDIS_EN_MASK 0x1
+#define RG_VCAM_IO_NDIS_EN_SHIFT 0x0
+
+// (0xA3) DIGLDO_CON21 (RW)
+#define DIGLDO_CON21_ADDR 0xA3
+
+#define RG_VCAM_AF_CAL_MASK 0xF
+#define RG_VCAM_AF_CAL_SHIFT 0x0
+
+// (0xA4) DIGLDO_CON22 (RW)
+#define DIGLDO_CON22_ADDR 0xA4
+
+#define RG_VCAM_AF_VOSEL_MASK 0x7
+#define RG_VCAM_AF_VOSEL_SHIFT 0x4
+#define RG_VCAM_AF_EN_MASK 0x1
+#define RG_VCAM_AF_EN_SHIFT 0x0
+
+// (0xA5) DIGLDO_CON23 (RW)
+#define RG_VCAM_AF_STBTD_MASK 0x3
+#define RG_VCAM_AF_STBTD_SHIFT 0x4
+#define RG_VCAM_AF_OCFB_EN_MASK 0x1
+#define RG_VCAM_AF_OCFB_EN_SHIFT 0x1
+#define RG_VCAM_AF_NDIS_EN_MASK 0x1
+#define RG_VCAM_AF_NDIS_EN_SHIFT 0x0
+
+// (0xA6) DIGLDO_CON24 (RW)
+#define DIGLDO_CON24_ADDR 0xA6
+
+#define RG_VMC_CAL_MASK 0xF
+#define RG_VMC_CAL_SHIFT 0x0
+
+// (0xA7) DIGLDO_CON25 (RO/RW)
+#define DIGLDO_CON25_ADDR 0xA7
+
+#define QI_VMC_EN_MASK 0x1
+#define QI_VMC_EN_SHIFT 0x7
+#define RG_VMC_VOSEL_MASK 0x7
+#define RG_VMC_VOSEL_SHIFT 0x4
+#define RG_VMC_EN_MASK 0x1
+#define RG_VMC_EN_SHIFT 0x0
+
+// (0xA8) DIGLDO_CON26 (RW)
+#define RG_VMC_STBTD_MASK 0x3
+#define RG_VMC_STBTD_SHIFT 0x4
+#define RG_VMC_OCFB_EN_MASK 0x1
+#define RG_VMC_OCFB_EN_SHIFT 0x1
+#define RG_VMC_NDIS_EN_MASK 0x1
+#define RG_VMC_NDIS_EN_SHIFT 0x0
+
+// (0xA9) DIGLDO_CON27 (RO/RW)
+#define QI_VMC_MODE_MASK 0x1
+#define QI_VMC_MODE_SHIFT 0x7
+#define VMC_LP_MODE_SET_MASK 0x1
+#define VMC_LP_MODE_SET_SHIFT 0x1
+#define VMC_LP_SEL_MASK 0x1
+#define VMC_LP_SEL_SHIFT 0x0
+
+// (0xAA) DIGLDO_CON28 (RW)
+#define DIGLDO_CON28_ADDR 0xAA
+
+#define RG_VMCH_CAL_MASK 0xF
+#define RG_VMCH_CAL_SHIFT 0x0
+
+// (0xAB) DIGLDO_CON29 (RO/RW)
+#define DIGLDO_CON29_ADDR 0xAB
+
+#define QI_VMCH_EN_MASK 0x1
+#define QI_VMCH_EN_SHIFT 0x7
+#define RG_VMCH_VOSEL_MASK 0x7
+#define RG_VMCH_VOSEL_SHIFT 0x4
+#define RG_VMCH_EN_MASK 0x1
+#define RG_VMCH_EN_SHIFT 0x0
+
+// (0xAC) DIGLDO_CON2A (RW)
+#define RG_VMCH_STBTD_MASK 0x3
+#define RG_VMCH_STBTD_SHIFT 0x4
+#define RG_VMCH_OCFB_EN_MASK 0x1
+#define RG_VMCH_OCFB_EN_SHIFT 0x1
+#define RG_VMCH_NDIS_EN_MASK 0x1
+#define RG_VMCH_NDIS_EN_SHIFT 0x0
+
+// (0xAD) DIGLDO_CON2B (RO/RW)
+#define QI_VMCH_MODE_MASK 0x1
+#define QI_VMCH_MODE_SHIFT 0x7
+#define VMCH_LP_MODE_SET_MASK 0x1
+#define VMCH_LP_MODE_SET_SHIFT 0x1
+#define VMCH_LP_SEL_MASK 0x1
+#define VMCH_LP_SEL_SHIFT 0x0
+
+// (0xAE) DIGLDO_CON2C (RW)
+#define DIGLDO_CON2C_ADDR 0xAE
+
+#define RG_VGP_CAL_MASK 0xF
+#define RG_VGP_CAL_SHIFT 0x0
+
+// (0xAF) DIGLDO_CON2D (RW)
+#define DIGLDO_CON2D_ADDR 0xAF
+
+#define RG_VGP_VOSEL_MASK 0x7
+#define RG_VGP_VOSEL_SHIFT 0x4
+#define RG_VGP_EN_MASK 0x1
+#define RG_VGP_EN_SHIFT 0x0
+
+// (0xB0) DIGLDO_CON2E (RW)
+#define RG_VGP_STBTD_MASK 0x3
+#define RG_VGP_STBTD_SHIFT 0x4
+#define RG_VGP_OCFB_EN_MASK 0x1
+#define RG_VGP_OCFB_EN_SHIFT 0x1
+#define RG_VGP_NDIS_EN_MASK 0x1
+#define RG_VGP_NDIS_EN_SHIFT 0x0
+
+// (0xB1) DIGLDO_CON2F (RW)
+#define DIGLDO_CON2F_ADDR 0xB1
+
+#define RG_VGP2_CAL_MASK 0xF
+#define RG_VGP2_CAL_SHIFT 0x0
+
+// (0xB2) DIGLDO_CON30 (RW)
+#define DIGLDO_CON30_ADDR 0xB2
+
+#define RG_VGP2_VOSEL_MASK 0x7
+#define RG_VGP2_VOSEL_SHIFT 0x4
+#define RG_VGP2_EN_MASK 0x1
+#define RG_VGP2_EN_SHIFT 0x0
+
+// (0xB3) DIGLDO_CON31 (RW)
+#define RG_VGP2_STBTD_MASK 0x3
+#define RG_VGP2_STBTD_SHIFT 0x4
+#define RG_VGP2_OCFB_EN_MASK 0x1
+#define RG_VGP2_OCFB_EN_SHIFT 0x1
+#define RG_VGP2_NDIS_EN_MASK 0x1
+#define RG_VGP2_NDIS_EN_SHIFT 0x0
+
+// (0xB4) DIGLDO_CON32 (RW)
+#define DIGLDO_CON32_ADDR 0xB4
+
+#define RG_VIBR_CAL_MASK 0xF
+#define RG_VIBR_CAL_SHIFT 0x0
+
+// (0xB5) DIGLDO_CON33 (RW)
+#define DIGLDO_CON33_ADDR 0xB5
+
+#define RG_VIBR_VOSEL_MASK 0x7
+#define RG_VIBR_VOSEL_SHIFT 0x4
+#define RG_VIBR_EN_MASK 0x1
+#define RG_VIBR_EN_SHIFT 0x0
+
+// (0xB6) DIGLDO_CON34 (RW)
+#define RG_VIBR_STBTD_MASK 0x3
+#define RG_VIBR_STBTD_SHIFT 0x4
+#define RG_VIBR_THR_SHDN_EN_MASK 0x1
+#define RG_VIBR_THR_SHDN_EN_SHIFT 0x3
+#define RG_VIBR_STB_SEL_MASK 0x1
+#define RG_VIBR_STB_SEL_SHIFT 0x2
+#define RG_VIBR_OCFB_EN_MASK 0x1
+#define RG_VIBR_OCFB_EN_SHIFT 0x1
+#define RG_VIBR_NDIS_EN_MASK 0x1
+#define RG_VIBR_NDIS_EN_SHIFT 0x0
+
+// (0xB7) DIGLDO_CON35 (RO)
+#define RO_QI_VUSB_OC_STATUS_MASK 0x1
+#define RO_QI_VUSB_OC_STATUS_SHIFT 0x6
+#define RO_QI_VSIM2_OC_STATUS_MASK 0x1
+#define RO_QI_VSIM2_OC_STATUS_SHIFT 0x5
+#define RO_QI_VSIM_OC_STATUS_MASK 0x1
+#define RO_QI_VSIM_OC_STATUS_SHIFT 0x4
+#define RO_QI_VIO28_OC_STATUS_MASK 0x1
+#define RO_QI_VIO28_OC_STATUS_SHIFT 0x3
+#define RO_QI_VM12_INT_OC_STATUS_MASK 0x1
+#define RO_QI_VM12_INT_OC_STATUS_SHIFT 0x2
+#define RO_QI_VM12_2_OC_STATUS_MASK 0x1
+#define RO_QI_VM12_2_OC_STATUS_SHIFT 0x1
+#define RO_QI_VM12_1_OC_STATUS_MASK 0x1
+#define RO_QI_VM12_1_OC_STATUS_SHIFT 0x0
+
+// (0xB8) DIGLDO_CON36 (RO)
+#define RO_QI_VIBR_OC_STATUS_MASK 0x1
+#define RO_QI_VIBR_OC_STATUS_SHIFT 0x7
+#define RO_QI_VGP2_OC_STATUS_MASK 0x1
+#define RO_QI_VGP2_OC_STATUS_SHIFT 0x6
+#define RO_QI_VGP_OC_STATUS_MASK 0x1
+#define RO_QI_VGP_OC_STATUS_SHIFT 0x5
+#define RO_QI_VMCH_OC_STATUS_MASK 0x1
+#define RO_QI_VMCH_OC_STATUS_SHIFT 0x4
+#define RO_QI_VMC_OC_STATUS_MASK 0x1
+#define RO_QI_VMC_OC_STATUS_SHIFT 0x3
+#define RO_QI_VCAM_AF_OC_STATUS_MASK 0x1
+#define RO_QI_VCAM_AF_OC_STATUS_SHIFT 0x2
+#define RO_QI_VCAM_IO_OC_STATUS_MASK 0x1
+#define RO_QI_VCAM_IO_OC_STATUS_SHIFT 0x1
+#define RO_QI_VCAMD_OC_STATUS_MASK 0x1
+#define RO_QI_VCAMD_OC_STATUS_SHIFT 0x0
+
+// (0xB9) DIGLDO_CON37 (RO)
+#define QI_VM12_INT_CAL_MASK 0x1F
+#define QI_VM12_INT_CAL_SHIFT 0x0
+
+// (0xBA) DIGLDO_RSV (RW)
+#define RG_DIGLDO_RSV_MASK 0xF
+#define RG_DIGLDO_RSV_SHIFT 0x0
+
+// (0xBD) ANALDO_CON0 (RW)
+#define ANALDO_CON0_ADDR 0xBD
+
+#define RG_VRF_CAL_MASK 0xF
+#define RG_VRF_CAL_SHIFT 0x0
+
+// (0xBE) ANALDO_CON1 (RO/RW)
+#define ANALDO_CON1_ADDR 0xBE
+
+#define QI_VRF_EN_MASK 0x1
+#define QI_VRF_EN_SHIFT 0x7
+#define VRF_ON_CTRL_MASK 0x1
+#define VRF_ON_CTRL_SHIFT 0x1
+#define RG_VRF_EN_MASK 0x1
+#define RG_VRF_EN_SHIFT 0x0
+
+// (0xBF) ANALDO_CON2 (RW)
+#define RG_VRF_STBTD_MASK 0x3
+#define RG_VRF_STBTD_SHIFT 0x4
+#define RG_VRF_OCFB_EN_MASK 0x1
+#define RG_VRF_OCFB_EN_SHIFT 0x1
+#define RG_VRF_NDIS_EN_MASK 0x1
+#define RG_VRF_NDIS_EN_SHIFT 0x0
+
+// (0xC0) ANALDO_CON3 (RW)
+#define ANALDO_CON3_ADDR 0xC0
+
+#define RG_VTCXO_CAL_MASK 0xF
+#define RG_VTCXO_CAL_SHIFT 0x0
+
+// (0xC1) ANALDO_CON4 (RO/RW)
+#define ANALDO_CON4_ADDR 0xC1
+
+#define QI_VTCXO_EN_MASK 0x1
+#define QI_VTCXO_EN_SHIFT 0x7
+#define VTCXO_ON_CTRL_MASK 0x1
+#define VTCXO_ON_CTRL_SHIFT 0x1
+#define RG_VTCXO_EN_MASK 0x1
+#define RG_VTCXO_EN_SHIFT 0x0
+
+// (0xC2) ANALDO_CON5 (RW)
+#define RG_VTCXO_STBTD_MASK 0x3
+#define RG_VTCXO_STBTD_SHIFT 0x4
+#define RG_VTCXO_OCFB_EN_MASK 0x1
+#define RG_VTCXO_OCFB_EN_SHIFT 0x1
+#define RG_VTCXO_NDIS_EN_MASK 0x1
+#define RG_VTCXO_NDIS_EN_SHIFT 0x0
+
+// (0xC3) ANALDO_CON6 (RW)
+#define ANALDO_CON6_ADDR 0xC3
+
+#define RG_VA1_CAL_MASK 0xF
+#define RG_VA1_CAL_SHIFT 0x0
+
+// (0xC4) ANALDO_CON7 (RO/RW)
+#define ANALDO_CON7_ADDR 0xC4
+
+#define QI_VA1_EN_MASK 0x1
+#define QI_VA1_EN_SHIFT 0x7
+#define RG_VA1_VOSEL_MASK 0x3
+#define RG_VA1_VOSEL_SHIFT 0x4
+#define RG_VA1_EN_MASK 0x1
+#define RG_VA1_EN_SHIFT 0x0
+
+// (0xC5) ANALDO_CON8 (RW)
+#define RG_VA1_STBTD_MASK 0x3
+#define RG_VA1_STBTD_SHIFT 0x4
+#define RG_VA1_OCFB_EN_MASK 0x1
+#define RG_VA1_OCFB_EN_SHIFT 0x1
+#define RG_VA1_NDIS_EN_MASK 0x1
+#define RG_VA1_NDIS_EN_SHIFT 0x0
+
+// (0xC6) ANALDO_CON9 (RO/RW)
+#define QI_VA1_MODE_MASK 0x1
+#define QI_VA1_MODE_SHIFT 0x7
+#define VA1_LP_SET_MASK 0x1
+#define VA1_LP_SET_SHIFT 0x1
+#define VA1_LP_SEL_MASK 0x1
+#define VA1_LP_SEL_SHIFT 0x0
+
+// (0xC7) ANALDO_CONA (RW)
+#define ANALDO_CONA_ADDR 0xC7
+
+#define RG_VA2_CAL_MASK 0xF
+#define RG_VA2_CAL_SHIFT 0x0
+
+// (0xC8) ANALDO_CONB (RO/RW)
+#define ANALDO_CONB_ADDR 0xC8
+
+#define QI_VA2_EN_MASK 0x1
+#define QI_VA2_EN_SHIFT 0x7
+#define RG_VA2_VOSEL_MASK 0x1
+#define RG_VA2_VOSEL_SHIFT 0x4
+#define RG_VA2_EN_MASK 0x1
+#define RG_VA2_EN_SHIFT 0x0
+
+// (0xC9) ANALDO_CONC (RW)
+#define RG_VA2_STBTD_MASK 0x3
+#define RG_VA2_STBTD_SHIFT 0x4
+#define RG_VA2_OCFB_EN_MASK 0x1
+#define RG_VA2_OCFB_EN_SHIFT 0x1
+#define RG_VA2_NDIS_EN_MASK 0x1
+#define RG_VA2_NDIS_EN_SHIFT 0x0
+
+// (0xCA) ANALDO_COND (RW)
+#define ANALDO_COND_ADDR 0xCA
+
+#define RG_VCAMA_CAL_MASK 0xF
+#define RG_VCAMA_CAL_SHIFT 0x0
+
+// (0xCB) ANALDO_CONE (RW)
+#define ANALDO_CONE_ADDR 0xCB
+
+#define RG_VCAMA_VOSEL_MASK 0x3
+#define RG_VCAMA_VOSEL_SHIFT 0x4
+#define RG_VCAMA_EN_MASK 0x1
+#define RG_VCAMA_EN_SHIFT 0x0
+
+// (0xCC) ANALDO_CONF (RW)
+#define RG_VCAMA_STBTD_MASK 0x3
+#define RG_VCAMA_STBTD_SHIFT 0x4
+#define RG_VCAMA_OCFB_EN_MASK 0x1
+#define RG_VCAMA_OCFB_EN_SHIFT 0x1
+#define RG_VCAMA_NDIS_EN_MASK 0x1
+#define RG_VCAMA_NDIS_EN_SHIFT 0x0
+
+// (0xCD) ANALDO_CON10 (RW)
+#define RG_VCAMA_FBSEL_MASK 0x3
+#define RG_VCAMA_FBSEL_SHIFT 0x0
+
+// (0xCE) ANALDO_CON11 (RW)
+#define ANALDO_CON11_ADDR 0xCE
+
+#define RG_VRTC_VOSEL_MASK 0x3
+#define RG_VRTC_VOSEL_SHIFT 0x0
+
+// (0xCF) ANALDO_CON12 (RO/RW)
+#define ANALDO_CON12_ADDR 0xCF
+
+#define QI_VRTC_EN_MASK 0x1
+#define QI_VRTC_EN_SHIFT 0x7
+#define VRTC_EN_MASK 0x1
+#define VRTC_EN_SHIFT 0x0
+
+// (0xD0) ANALDO_CON13 (RO)
+#define RO_QI_VRF_OC_STATUS_MASK 0x1
+#define RO_QI_VRF_OC_STATUS_SHIFT 0x0
+#define RO_QI_VTCXO_OC_STATUS_MASK 0x1
+#define RO_QI_VTCXO_OC_STATUS_SHIFT 0x1
+#define RO_QI_VA1_OC_STATUS_MASK 0x1
+#define RO_QI_VA1_OC_STATUS_SHIFT 0x2
+#define RO_QI_VA2_OC_STATUS_MASK 0x1
+#define RO_QI_VA2_OC_STATUS_SHIFT 0x3
+#define RO_QI_VCAMA_OC_STATUS_MASK 0x1
+#define RO_QI_VCAMA_OC_STATUS_SHIFT 0x4
+
+// (0xD1) ANALDO_RSV (RW)
+#define RG_ANALDO_RSV_MASK 0xF
+#define RG_ANALDO_RSV_SHIFT 0x0
+
+// (0xD5) BUCK_K_CON0 (RW)
+#define RG_AUTO_K_MASK 0x1
+#define RG_AUTO_K_SHIFT 0x6
+#define RG_K_SRC_SEL_MASK 0x1
+#define RG_K_SRC_SEL_SHIFT 0x5
+#define RG_K_START_MANUAL_MASK 0x1
+#define RG_K_START_MANUAL_SHIFT 0x4
+#define RG_K_ONCE_MASK 0x1
+#define RG_K_ONCE_SHIFT 0x3
+#define RG_K_ONCE_EN_MASK 0x1
+#define RG_K_ONCE_EN_SHIFT 0x2
+#define RG_K_MAP_SEL_MASK 0x1
+#define RG_K_MAP_SEL_SHIFT 0x1
+#define RG_K_RST_DONE_MASK 0x1
+#define RG_K_RST_DONE_SHIFT 0x0
+
+// (0xD6) BUCK_K_CON1 (RW)
+#define RG_K_CONTROL_SMPS_MASK 0xF
+#define RG_K_CONTROL_SMPS_SHIFT 0x0
+
+// (0xD7) BUCK_K_CON2 (RO)
+#define K_CONTROL_MASK 0x1F
+#define K_CONTROL_SHIFT 0x3
+#define K_DONE_MASK 0x1
+#define K_DONE_SHIFT 0x1
+#define K_RESULT_MASK 0x1
+#define K_RESULT_SHIFT 0x0
+
+// (0xDA) AUXADC_CON0 (RO)
+#define RG_ADC_OUT_C0_7_0_MASK 0xFF
+#define RG_ADC_OUT_C0_7_0_SHIFT 0x0
+
+// (0xDB) AUXADC_CON1 (RO)
+#define RG_ADC_RDY_C0_MASK 0x1
+#define RG_ADC_RDY_C0_SHIFT 0x7
+#define RG_ADC_OUT_C0_9_8_MASK 0x3
+#define RG_ADC_OUT_C0_9_8_SHIFT 0x0
+
+// (0xDC) AUXADC_CON2 (RO)
+#define RG_ADC_OUT_C1_7_0_MASK 0xFF
+#define RG_ADC_OUT_C1_7_0_SHIFT 0x0
+
+// (0xDD) AUXADC_CON3 (RO)
+#define RG_ADC_RDY_C1_MASK 0x1
+#define RG_ADC_RDY_C1_SHIFT 0x7
+#define RG_ADC_OUT_C1_9_8_MASK 0x3
+#define RG_ADC_OUT_C1_9_8_SHIFT 0x0
+
+// (0xDE) AUXADC_CON4 (RO)
+#define RG_ADC_OUT_C2_7_0_MASK 0xFF
+#define RG_ADC_OUT_C2_7_0_SHIFT 0x0
+
+// (0xDF) AUXADC_CON5 (RO)
+#define RG_ADC_RDY_C2_MASK 0x1
+#define RG_ADC_RDY_C2_SHIFT 0x7
+#define RG_ADC_OUT_C2_9_8_MASK 0x3
+#define RG_ADC_OUT_C2_9_8_SHIFT 0x0
+
+// (0xE0) AUXADC_CON6 (RO)
+#define RG_ADC_OUT_C3_7_0_MASK 0xFF
+#define RG_ADC_OUT_C3_7_0_SHIFT 0x0
+
+// (0xE1) AUXADC_CON7 (RO)
+#define RG_ADC_RDY_C3_MASK 0x1
+#define RG_ADC_RDY_C3_SHIFT 0x7
+#define RG_ADC_OUT_C3_9_8_MASK 0x3
+#define RG_ADC_OUT_C3_9_8_SHIFT 0x0
+
+// (0xE2) AUXADC_CON8 (RO)
+#define RG_ADC_OUT_WAKEUP_7_0_MASK 0xFF
+#define RG_ADC_OUT_WAKEUP_7_0_SHIFT 0x0
+
+// (0xE3) AUXADC_CON9 (RO)
+#define RG_ADC_RDY_WAKEUP_MASK 0x1
+#define RG_ADC_RDY_WAKEUP_SHIFT 0x7
+#define RG_ADC_OUT_WAKEUP_9_8_MASK 0x3
+#define RG_ADC_OUT_WAKEUP_9_8_SHIFT 0x0
+
+// (0xE4) AUXADC_CON10 (RO)
+#define RG_ADC_OUT_LBAT_7_0_MASK 0xFF
+#define RG_ADC_OUT_LBAT_7_0_SHIFT 0x0
+
+// (0xE5) AUXADC_CON11 (RO)
+#define RG_ADC_RDY_LBAT_MASK 0x1
+#define RG_ADC_RDY_LBAT_SHIFT 0x7
+#define RG_ADC_OUT_LBAT_9_8_MASK 0x3
+#define RG_ADC_OUT_LBAT_9_8_SHIFT 0x0
+
+// (0xE6) AUXADC_CON12 (RO)
+#define RG_ADC_OUT_TRIM_7_0_MASK 0xFF
+#define RG_ADC_OUT_TRIM_7_0_SHIFT 0x0
+
+// (0xE7) AUXADC_CON13 (RO)
+#define RG_ADC_RDY_TRIM_MASK 0x1
+#define RG_ADC_RDY_TRIM_SHIFT 0x7
+#define RG_ADC_OUT_TRIM_9_8_MASK 0x3
+#define RG_ADC_OUT_TRIM_9_8_SHIFT 0x0
+
+// (0xE8) AUXADC_CON14 (RW)
+#define RG_AUXADC_CHSEL_MASK 0xF
+#define RG_AUXADC_CHSEL_SHIFT 0x4
+#define RG_ADC_TRIM_COMP_MASK 0x1
+#define RG_ADC_TRIM_COMP_SHIFT 0x2
+#define RG_AUXADC_BIST_ENB_MASK 0x1
+#define RG_AUXADC_BIST_ENB_SHIFT 0x1
+#define RG_AUXADC_START_MASK 0x1
+#define RG_AUXADC_START_SHIFT 0x0
+
+// (0xE9) AUXADC_CON15 (RW)
+#define RG_SPL_NUM_MASK 0xF
+#define RG_SPL_NUM_SHIFT 0x4
+#define RG_AVG_NUM_MASK 0x3
+#define RG_AVG_NUM_SHIFT 0x2
+#define RG_BUF_PWD_B_MASK 0x1
+#define RG_BUF_PWD_B_SHIFT 0x1
+#define RG_ADC_PWD_B_MASK 0x1
+#define RG_ADC_PWD_B_SHIFT 0x0
+
+// (0xEA) AUXADC_CON16 (RW)
+#define RG_LBAT_DEBT_MAX_MASK 0xFF
+#define RG_LBAT_DEBT_MAX_SHIFT 0x0
+
+// (0xEB) AUXADC_CON17 (RW)
+#define RG_LBAT_DEBT_MIN_MASK 0xFF
+#define RG_LBAT_DEBT_MIN_SHIFT 0x0
+
+// (0xEC) AUXADC_CON18 (RW)
+#define RG_LBAT_DET_PRD_7_0_MASK 0xFF
+#define RG_LBAT_DET_PRD_7_0_SHIFT 0x0
+
+// (0xED) AUXADC_CON19 (RW)
+#define RG_LBAT_DET_PRD_15_8_MASK 0xFF
+#define RG_LBAT_DET_PRD_15_8_SHIFT 0x0
+
+// (0xEE) AUXADC_CON20 (RW)
+#define RG_LBAT_DET_PRD_19_16_MASK 0xF
+#define RG_LBAT_DET_PRD_19_16_SHIFT 0x0
+
+// (0xEF) AUXADC_CON21 (RW)
+#define RG_LBAT_VOLT_MAX_7_0_MASK 0xFF
+#define RG_LBAT_VOLT_MAX_7_0_SHIFT 0x0
+
+// (0xF0) AUXADC_CON22 (RW)
+#define RG_LBAT_EN_MAX_MASK 0x1
+#define RG_LBAT_EN_MAX_SHIFT 0x7
+#define RG_LBAT_IRQ_EN_MAX_MASK 0x1
+#define RG_LBAT_IRQ_EN_MAX_SHIFT 0x4
+#define RG_LBAT_VOLT_MAX_9_8_MASK 0x3
+#define RG_LBAT_VOLT_MAX_9_8_SHIFT 0x0
+
+// (0xF1) AUXADC_CON23 (RW)
+#define RG_LBAT_VOLT_MIN_7_0_MASK 0xFF
+#define RG_LBAT_VOLT_MIN_7_0_SHIFT 0x0
+
+// (0xF2) AUXADC_CON24 (RW)
+#define RG_LBAT_EN_MIN_MASK 0x1
+#define RG_LBAT_EN_MIN_SHIFT 0x7
+#define RG_LBAT_IRQ_EN_MIN_MASK 0x1
+#define RG_LBAT_IRQ_EN_MIN_SHIFT 0x4
+#define RG_LBAT_VOLT_MIN_9_8_MASK 0x3
+#define RG_LBAT_VOLT_MIN_9_8_SHIFT 0x0
+
+// (0xF3) AUXADC_CON25 (RO)
+#define RG_LBAT_MAX_IRQ_B_MASK 0x1
+#define RG_LBAT_MAX_IRQ_B_SHIFT 0x7
+#define RG_LBAT_MIN_IRQ_B_MASK 0x1
+#define RG_LBAT_MIN_IRQ_B_SHIFT 0x6
+
+// (0xF4) AUXADC_CON26 (RW)
+#define RG_DA_DAC_7_0_MASK 0xFF
+#define RG_DA_DAC_7_0_SHIFT 0x0
+
+// (0xF5) AUXADC_CON27 (RO/RW)
+#define RG_NI_COMP_MASK 0x1
+#define RG_NI_COMP_SHIFT 0x7
+#define RG_DA_DAC_9_8_MASK 0x3
+#define RG_DA_DAC_9_8_SHIFT 0x0
+
+// (0xF6) AUXADC_CON28 (RW)
+#define RG_AUXADC_RSV_MASK 0x7
+#define RG_AUXADC_RSV_SHIFT 0x5
+#define RG_DA_DAC_SEL_MASK 0x1
+#define RG_DA_DAC_SEL_SHIFT 0x4
+#define RG_AUX_OUT_SEL_MASK 0x1
+#define RG_AUX_OUT_SEL_SHIFT 0x3
+#define RG_ARB_PRIO_2_MASK 0x1
+#define RG_ARB_PRIO_2_SHIFT 0x2
+#define RG_ARB_PRIO_1_MASK 0x1
+#define RG_ARB_PRIO_1_SHIFT 0x1
+#define RG_ARB_PRIO_0_MASK 0x1
+#define RG_ARB_PRIO_0_SHIFT 0x0
+
+// (0xF7) AUXADC_CON29 (RW)
+#define RG_AUXADC_CALI_MASK 0x3
+#define RG_AUXADC_CALI_SHIFT 0x4
+#define RG_BUF_CALI_MASK 0x3
+#define RG_BUF_CALI_SHIFT 0x0
+
+////////////////////////////////
+/* PMIC 6329 BANK 1 */
+////////////////////////////////
+// (0x00) TEST_CON0 (RW)
+#define RG_MON_GRP_SEL_MASK 0xF
+#define RG_MON_GRP_SEL_SHIFT 0x0
+
+// (0x01) TEST_CON1 (RW)
+#define RG_MON_FLAG_SEL_MASK 0xFF
+#define RG_MON_FLAG_SEL_SHIFT 0x0
+
+// (0x02) TEST_CON2 (RW)
+#define RG_IO_PASEL0_SEL_MASK 0xF
+#define RG_IO_PASEL0_SEL_SHIFT 0x4
+#define RG_IO_PASEL1_SEL_MASK 0xF
+#define RG_IO_PASEL1_SEL_SHIFT 0x0
+
+// (0x03) TEST_CON3 (RW)
+#define RG_IO_PASEL2_SEL_MASK 0xF
+#define RG_IO_PASEL2_SEL_SHIFT 0x4
+#define RG_IO_INT_SEL_MASK 0xF
+#define RG_IO_INT_SEL_SHIFT 0x0
+
+// (0x04) TEST_CON4 (RW)
+#define RG_DIO_SMT_MASK 0x1
+#define RG_DIO_SMT_SHIFT 0x5
+#define RG_DIO_E2_MASK 0x1
+#define RG_DIO_E2_SHIFT 0x4
+#define RG_DIO_E4_MASK 0x1
+#define RG_DIO_E4_SHIFT 0x3
+#define RG_DIO_SR_MASK 0x1
+#define RG_DIO_SR_SHIFT 0x2
+#define RG_SCK_PU_MASK 0x1
+#define RG_SCK_PU_SHIFT 0x1
+#define RG_SCK_PD_MASK 0x1
+#define RG_SCK_PD_SHIFT 0x0
+
+// (0x05) TEST_CON5 (RW)
+#define RG_SDA_E2_MASK 0x1
+#define RG_SDA_E2_SHIFT 0x7
+#define RG_SDA_E4_MASK 0x1
+#define RG_SDA_E4_SHIFT 0x6
+#define RG_SDA_PU_MASK 0x1
+#define RG_SDA_PU_SHIFT 0x5
+#define RG_SDA_PD_MASK 0x1
+#define RG_SDA_PD_SHIFT 0x4
+#define RG_INT_E2_MASK 0x1
+#define RG_INT_E2_SHIFT 0x3
+#define RG_INT_E4_MASK 0x1
+#define RG_INT_E4_SHIFT 0x2
+#define RG_INT_PU_MASK 0x1
+#define RG_INT_PU_SHIFT 0x1
+#define RG_INT_PD_MASK 0x1
+#define RG_INT_PD_SHIFT 0x0
+
+// (0x06) TEST_CON6 (RW)
+#define RG_DVS_PU_MASK 0x1
+#define RG_DVS_PU_SHIFT 0x5
+#define RG_DVS_PD_MASK 0x1
+#define RG_DVS_PD_SHIFT 0x4
+#define RG_PASEL_PU_MASK 0x1
+#define RG_PASEL_PU_SHIFT 0x3
+#define RG_PASEL_PD_MASK 0x1
+#define RG_PASEL_PD_SHIFT 0x2
+#define RG_SYSRSTB_PU_MASK 0x1
+#define RG_SYSRSTB_PU_SHIFT 0x1
+#define RG_SYSRSTB_PD_MASK 0x1
+#define RG_SYSRSTB_PD_SHIFT 0x0
+
+// (0x07) TEST_CON7 (RW)
+#define RG_SRCLKEN_PU_MASK 0x1
+#define RG_SRCLKEN_PU_SHIFT 0x3
+#define RG_SRCLKEN_PD_MASK 0x1
+#define RG_SRCLKEN_PD_SHIFT 0x2
+#define RG_BL_PWM_PU_MASK 0x1
+#define RG_BL_PWM_PU_SHIFT 0x1
+#define RG_BL_PWM_PD_MASK 0x1
+#define RG_BL_PWM_PD_SHIFT 0x0
+
+// (0x08) TEST_CON8 (RW)
+#define RG_SDA_IO_CONFIG_MASK 0x1
+#define RG_SDA_IO_CONFIG_SHIFT 0x3
+#define RG_TEST_STRUP_MASK 0x1
+#define RG_TEST_STRUP_SHIFT 0x2
+#define RG_OTP_W_MODE_MASK 0x1
+#define RG_OTP_W_MODE_SHIFT 0x1
+#define RG_NANDTREE_MODE_MASK 0x1
+#define RG_NANDTREE_MODE_SHIFT 0x0
+
+// (0x09) TEST_CON9 (RW)
+#define RG_TEST_AUXADC_MASK 0x1
+#define RG_TEST_AUXADC_SHIFT 0x7
+#define RG_TEST_FGPLL_MASK 0x1
+#define RG_TEST_FGPLL_SHIFT 0x6
+#define RG_TEST_FG1_MASK 0x1
+#define RG_TEST_FG1_SHIFT 0x5
+#define RG_TEST_FG2_MASK 0x1
+#define RG_TEST_FG2_SHIFT 0x4
+#define RG_TEST_IO_FG_SEL_MASK 0x1
+#define RG_TEST_IO_FG_SEL_SHIFT 0x3
+#define RG_TEST_CLASSD_MASK 0x1
+#define RG_TEST_CLASSD_SHIFT 0x2
+#define RG_TEST_DRIVER_MASK 0x1
+#define RG_TEST_DRIVER_SHIFT 0x1
+#define RG_TEST_BOOST_MASK 0x1
+#define RG_TEST_BOOST_SHIFT 0x0
+
+// (0x0A) TEST_CON10 (RO)
+#define RO_MON_MASK 0xFF
+#define RO_MON_SHIFT 0x0
+
+// (0x0B) TEST_CON11 (RO)
+#define RO_DVS1_IN_MASK 0x1
+#define RO_DVS1_IN_SHIFT 0x7
+#define RO_DVS2_IN_MASK 0x1
+#define RO_DVS2_IN_SHIFT 0x6
+#define RO_PASEL0_IN_MASK 0x1
+#define RO_PASEL0_IN_SHIFT 0x5
+#define RO_PASEL1_IN_MASK 0x1
+#define RO_PASEL1_IN_SHIFT 0x4
+#define RO_PASEL2_IN_MASK 0x1
+#define RO_PASEL2_IN_SHIFT 0x3
+#define RO_SYSRSTB_IN_MASK 0x1
+#define RO_SYSRSTB_IN_SHIFT 0x2
+#define RO_SRCLKEN_IN_MASK 0x1
+#define RO_SRCLKEN_IN_SHIFT 0x1
+#define RO_BLPWM_IN_MASK 0x1
+#define RO_BLPWM_IN_SHIFT 0x0
+
+// (0x0C) RST_CON0 (RW)
+#define RG_PWRKEY_RST_EN_MASK 0x1
+#define RG_PWRKEY_RST_EN_SHIFT 0x4
+#define RG_HOMEKEY_RST_EN_MASK 0x1
+#define RG_HOMEKEY_RST_EN_SHIFT 0x3
+#define RG_PWRKEY_RST_TD_MASK 0x3
+#define RG_PWRKEY_RST_TD_SHIFT 0x1
+#define RG_PWRRST_TMR_DIS_MASK 0x1
+#define RG_PWRRST_TMR_DIS_SHIFT 0x0
+
+// (0x0D) RST_CON1 (RW)
+#define RG_RST_PART_SEL_MASK 0x1
+#define RG_RST_PART_SEL_SHIFT 0x7
+#define RG_OTP_MAN_RST_MASK 0x1
+#define RG_OTP_MAN_RST_SHIFT 0x5
+#define RG_PCHR_MAN_RST_EN_MASK 0x1
+#define RG_PCHR_MAN_RST_EN_SHIFT 0x4
+#define RG_PCHR_MAN_RST_MASK 0x1
+#define RG_PCHR_MAN_RST_SHIFT 0x3
+#define RG_STRUP_MAN_RST_EN_MASK 0x1
+#define RG_STRUP_MAN_RST_EN_SHIFT 0x2
+#define RG_SIF_TST_CK_DIS_MASK 0x1
+#define RG_SIF_TST_CK_DIS_SHIFT 0x1
+#define RG_SYSRSTB_EN_MASK 0x1
+#define RG_SYSRSTB_EN_SHIFT 0x0
+
+// (0x14) TOP2_CON0 (RW)
+#define RG_75K_EXT_SEL_MASK 0x1
+#define RG_75K_EXT_SEL_SHIFT 0x7
+#define RG_FG_TST_CK_SEL_MASK 0x1
+#define RG_FG_TST_CK_SEL_SHIFT 0x6
+#define RG_CHR1M_TST_CK_SEL_MASK 0x1
+#define RG_CHR1M_TST_CK_SEL_SHIFT 0x5
+#define RG_CLK_TST_MASK 0x1
+#define RG_CLK_TST_SHIFT 0x4
+#define RG_AUXADC_CK_RST_MASK 0x1
+#define RG_AUXADC_CK_RST_SHIFT 0x3
+#define RG_AUXADC_CK_SEL_MASK 0x7
+#define RG_AUXADC_CK_SEL_SHIFT 0x0
+
+// (0x15) TOP2_CON1 (RW)
+#define RG_10M_CK_DIV_RST_MASK 0x1
+#define RG_10M_CK_DIV_RST_SHIFT 0x5
+#define RG_FGADC_CK_PDN_MASK 0x1
+#define RG_FGADC_CK_PDN_SHIFT 0x4
+#define RG_OTPC_CK_PDN_MASK 0x1
+#define RG_OTPC_CK_PDN_SHIFT 0x3
+#define RG_BST_DRV_CK_PDN_MASK 0x1
+#define RG_BST_DRV_CK_PDN_SHIFT 0x2
+#define RG_SPK_CK_PDN_MASK 0x1
+#define RG_SPK_CK_PDN_SHIFT 0x1
+#define RG_PWMOC_CK_PDN_MASK 0x1
+#define RG_PWMOC_CK_PDN_SHIFT 0x0
+
+// (0x16) CC_CTL1 (RW)
+#define OC_GEAR_BVALID_DET_MASK 0x3
+#define OC_GEAR_BVALID_DET_SHIFT 0x6
+#define OC_GEAR_VBATON_UNDET_MASK 0x3
+#define OC_GEAR_VBATON_UNDET_SHIFT 0x4
+#define OC_GEAR_LDO_MASK 0x3
+#define OC_GEAR_LDO_SHIFT 0x0
+
+// (0x17) INT2_RSV (RW)
+#define RG_INT_RSV_MASK 0x1F
+#define RG_INT_RSV_SHIFT 0x3
+#define POLARITY_BVALID_DET_MASK 0x1
+#define POLARITY_BVALID_DET_SHIFT 0x2
+#define POLARITY_VBATON_UNDET_MASK 0x1
+#define POLARITY_VBATON_UNDET_SHIFT 0x1
+#define POLARITY_MASK 0x1
+#define POLARITY_SHIFT 0x0
+
+// (0x18) OC_PWMCTL1 (RW)
+#define VPA_OC_WND_MASK 0x3
+#define VPA_OC_WND_SHIFT 0x6
+#define VPA_OC_THD_MASK 0x3
+#define VPA_OC_THD_SHIFT 0x4
+#define VRF18_OC_WND_MASK 0x3
+#define VRF18_OC_WND_SHIFT 0x2
+#define VRF18_OC_THD_MASK 0x3
+#define VRF18_OC_THD_SHIFT 0x0
+
+// (0x22) FLASH_CON0 (RW)
+#define FLASH_RSV0_MASK 0x7
+#define FLASH_RSV0_SHIFT 0x5
+#define FLASH_DIM_DUTY_MASK 0x1F
+#define FLASH_DIM_DUTY_SHIFT 0x0
+
+// (0x23) FLASH_CON1 (RW)
+#define FLASH_THER_SHDN_EN_MASK 0x1
+#define FLASH_THER_SHDN_EN_SHIFT 0x1
+#define FLASH_EN_MASK 0x1
+#define FLASH_EN_SHIFT 0x0
+
+// (0x24) FLASH_CON2 (RW)
+#define FLASH_DIM_DIV_MASK 0xFF
+#define FLASH_DIM_DIV_SHIFT 0x0
+
+// (0x25) FLASH_CON3 (RW)
+#define FLASH_RSV1_MASK 0x1F
+#define FLASH_RSV1_SHIFT 0x3
+#define FLASH_SEL_MASK 0x7
+#define FLASH_SEL_SHIFT 0x0
+
+// (0x26) FLASH_CON4 (RW)
+#define FLASH_SFSTREN_MASK 0x1
+#define FLASH_SFSTREN_SHIFT 0x7
+#define FLASH_SFSTR_MASK 0x3
+#define FLASH_SFSTR_SHIFT 0x4
+#define FLASH_MODE_MASK 0x1
+#define FLASH_MODE_SHIFT 0x0
+
+// (0x27) KPLED_CON0 (RW)
+#define KPLED_RSV0_MASK 0x7
+#define KPLED_RSV0_SHIFT 0x5
+#define KPLED_DIM_DUTY_MASK 0x1F
+#define KPLED_DIM_DUTY_SHIFT 0x0
+
+// (0x28) KPLED_CON1 (RW)
+#define KPLED_THER_SHDN_EN_MASK 0x1
+#define KPLED_THER_SHDN_EN_SHIFT 0x1
+#define KPLED_EN_MASK 0x1
+#define KPLED_EN_SHIFT 0x0
+
+// (0x29) KPLED_CON2 (RW)
+#define KPLED_DIM_DIV_MASK 0xFF
+#define KPLED_DIM_DIV_SHIFT 0x0
+
+// (0x2A) KPLED_CON3 (RW)
+#define KPLED_RSV1_MASK 0x1F
+#define KPLED_RSV1_SHIFT 0x3
+#define KPLED_SEL_MASK 0x7
+#define KPLED_SEL_SHIFT 0x0
+
+// (0x2B) KPLED_CON4 (RW)
+#define KPLED_SFSTREN_MASK 0x1
+#define KPLED_SFSTREN_SHIFT 0x7
+#define KPLED_SFSTR_MASK 0x3
+#define KPLED_SFSTR_SHIFT 0x4
+#define KPLED_MODE_MASK 0x1
+#define KPLED_MODE_SHIFT 0x0
+
+// (0x2C) ISINKS_CON0 (RW)
+#define ISINK_RSV0_MASK 0x7
+#define ISINK_RSV0_SHIFT 0x5
+#define ISINK_DIM0_DUTY_MASK 0xF
+#define ISINK_DIM0_DUTY_SHIFT 0x0
+
+// (0x2D) ISINKS_CON1 (RW)
+#define ISINK_DIM0_FSEL_MASK 0x1F
+#define ISINK_DIM0_FSEL_SHIFT 0x0
+
+// (0x2E) ISINKS_CON2 (RW)
+#define ISINK_RSV1_MASK 0x7
+#define ISINK_RSV1_SHIFT 0x5
+#define ISINK_DIM1_DUTY_MASK 0x1F
+#define ISINK_DIM1_DUTY_SHIFT 0x0
+
+// (0x2F) ISINKS_CON3 (RW)
+#define ISINK_DIM1_FSEL_MASK 0x1F
+#define ISINK_DIM1_FSEL_SHIFT 0x0
+
+// (0x30) ISINKS_CON4 (RW)
+#define ISINK_RSV2_MASK 0x7
+#define ISINK_RSV2_SHIFT 0x5
+#define ISINK_DIM2_DUTY_MASK 0x1F
+#define ISINK_DIM2_DUTY_SHIFT 0x0
+
+// (0x31) ISINKS_CON5 (RW)
+#define ISINK_DIM2_FSEL_MASK 0x1F
+#define ISINK_DIM2_FSEL_SHIFT 0x0
+
+// (0x32) ISINKS_CON6 (RW)
+#define ISINK_RSV3_MASK 0x3
+#define ISINK_RSV3_SHIFT 0x6
+#define ISINKS_CH5_EN_MASK 0x1
+#define ISINKS_CH5_EN_SHIFT 0x5
+#define ISINKS_CH4_EN_MASK 0x1
+#define ISINKS_CH4_EN_SHIFT 0x4
+#define ISINKS_CH3_EN_MASK 0x1
+#define ISINKS_CH3_EN_SHIFT 0x3
+#define ISINKS_CH2_EN_MASK 0x1
+#define ISINKS_CH2_EN_SHIFT 0x2
+#define ISINKS_CH1_EN_MASK 0x1
+#define ISINKS_CH1_EN_SHIFT 0x1
+#define ISINKS_CH0_EN_MASK 0x1
+#define ISINKS_CH0_EN_SHIFT 0x0
+
+// (0x33) ISINKS_CON7 (RW)
+#define ISINK_RSV4_MASK 0x3
+#define ISINK_RSV4_SHIFT 0x6
+#define ISINKS_CH5_CABC_EN_MASK 0x1
+#define ISINKS_CH5_CABC_EN_SHIFT 0x5
+#define ISINKS_CH4_CABC_EN_MASK 0x1
+#define ISINKS_CH4_CABC_EN_SHIFT 0x4
+#define ISINKS_CH3_CABC_EN_MASK 0x1
+#define ISINKS_CH3_CABC_EN_SHIFT 0x3
+#define ISINKS_CH2_CABC_EN_MASK 0x1
+#define ISINKS_CH2_CABC_EN_SHIFT 0x2
+#define ISINKS_CH1_CABC_EN_MASK 0x1
+#define ISINKS_CH1_CABC_EN_SHIFT 0x1
+#define ISINKS_CH0_CABC_EN_MASK 0x1
+#define ISINKS_CH0_CABC_EN_SHIFT 0x0
+
+// (0x34) ISINKS_CON8 (RW)
+#define ISINKS_CH0_STEP_MASK 0x7
+#define ISINKS_CH0_STEP_SHIFT 0x4
+#define ISINKS_CH0_MODE_MASK 0x3
+#define ISINKS_CH0_MODE_SHIFT 0x0
+
+// (0x35) ISINKS_CON9 (RW)
+#define ISINKS_CH1_STEP_MASK 0x7
+#define ISINKS_CH1_STEP_SHIFT 0x4
+#define ISINKS_CH1_MODE_MASK 0x3
+#define ISINKS_CH1_MODE_SHIFT 0x0
+
+// (0x36) ISINKS_CON10 (RW)
+#define ISINKS_CH2_STEP_MASK 0x7
+#define ISINKS_CH2_STEP_SHIFT 0x4
+#define ISINKS_CH2_MODE_MASK 0x3
+#define ISINKS_CH2_MODE_SHIFT 0x0
+
+// (0x37) ISINKS_CON11 (RW)
+#define ISINKS_CH3_STEP_MASK 0x7
+#define ISINKS_CH3_STEP_SHIFT 0x4
+#define ISINKS_CH3_MODE_MASK 0x3
+#define ISINKS_CH3_MODE_SHIFT 0x0
+
+// (0x38) ISINKS_CON12 (RW)
+#define ISINKS_CH4_STEP_MASK 0x7
+#define ISINKS_CH4_STEP_SHIFT 0x4
+#define ISINKS_CH4_MODE_MASK 0x3
+#define ISINKS_CH4_MODE_SHIFT 0x0
+
+// (0x39) ISINKS_CON13 (RW)
+#define ISINKS_CH5_STEP_MASK 0x7
+#define ISINKS_CH5_STEP_SHIFT 0x4
+#define ISINKS_CH5_MODE_MASK 0x3
+#define ISINKS_CH5_MODE_SHIFT 0x0
+
+// (0x3A) ISINKS_CON14 (RW)
+#define IBIAS_TRIM_EN_MASK 0x1
+#define IBIAS_TRIM_EN_SHIFT 0x6
+#define ISINKS_VREF_CAL_MASK 0x1F
+#define ISINKS_VREF_CAL_SHIFT 0x0
+
+// (0x3B) ISINKS_CON15 (RW)
+#define ISINK_RSV5_MASK 0xF
+#define ISINK_RSV5_SHIFT 0x4
+#define ISINKS_RSV_MASK 0xF
+#define ISINKS_RSV_SHIFT 0x0
+
+// (0x3C) ISINKS_CON16 (RW)
+#define DRV_RSV0_MASK 0xFF
+#define DRV_RSV0_SHIFT 0x0
+
+// (0x3F) BOOST_CON0 (RW)
+#define BOOST_ISINK_HW_SEL_MASK 0x1
+#define BOOST_ISINK_HW_SEL_SHIFT 0x7
+#define BOOST_MODE_MASK 0x3
+#define BOOST_MODE_SHIFT 0x4
+#define BOOST_CABC_EN_MASK 0x1
+#define BOOST_CABC_EN_SHIFT 0x2
+#define BOOST_EN_MASK 0x1
+#define BOOST_EN_SHIFT 0x0
+
+// (0x40) BOOST_CON1 (RW)
+#define BOOST_SR_NMOS_MASK 0x3
+#define BOOST_SR_NMOS_SHIFT 0x6
+#define BOOST_VRSEL_MASK 0xF
+#define BOOST_VRSEL_SHIFT 0x0
+
+// (0x41) BOOST_CON2 (RW)
+#define BOOST_RC_MASK 0x3
+#define BOOST_RC_SHIFT 0x4
+#define BOOST_CS_MASK 0x3
+#define BOOST_CS_SHIFT 0x2
+#define BOOST_CC_MASK 0x3
+#define BOOST_CC_SHIFT 0x0
+
+// (0x42) BOOST_CON3 (RW)
+#define BOOST_SLP_MASK 0x3
+#define BOOST_SLP_SHIFT 0x2
+#define BOOST_CL_MASK 0x3
+#define BOOST_CL_SHIFT 0x0
+
+// (0x43) BOOST_CON4 (RW)
+#define BOOST_SS_MASK 0x7
+#define BOOST_SS_SHIFT 0x4
+#define BOOST_RSV_MASK 0xF
+#define BOOST_RSV_SHIFT 0x0
+
+// (0x46) SPK_CON0 (RW)
+#define SPK_THER_SHDN_L_EN_MASK 0x1
+#define SPK_THER_SHDN_L_EN_SHIFT 0x6
+#define SPK_TRIM_EN_L_MASK 0x1
+#define SPK_TRIM_EN_L_SHIFT 0x4
+#define SPKMODE_L_MASK 0x1
+#define SPKMODE_L_SHIFT 0x2
+#define SPK_EN_L_MASK 0x1
+#define SPK_EN_L_SHIFT 0x0
+
+// (0x47) SPK_CON1 (RW)
+#define SPK_OC_EN_L_MASK 0x1
+#define SPK_OC_EN_L_SHIFT 0x7
+#define SPKAB_OC_EN_L_MASK 0x1
+#define SPKAB_OC_EN_L_SHIFT 0x6
+#define SPK_OC_SHDN_DL_MASK 0x1
+#define SPK_OC_SHDN_DL_SHIFT 0x4
+#define SPK_VOL_L_MASK 0x7
+#define SPK_VOL_L_SHIFT 0x0
+
+// (0x48) SPK_CON2 (RO/RW)
+#define SPK_RSV0_MASK 0x3F
+#define SPK_RSV0_SHIFT 0x2
+#define SPK_AB_OC_L_DEG_MASK 0x1
+#define SPK_AB_OC_L_DEG_SHIFT 0x1
+#define SPK_D_OC_L_DEG_MASK 0x1
+#define SPK_D_OC_L_DEG_SHIFT 0x0
+
+// (0x49) SPK_CON3 (RO/RW)
+#define SPK_OFFSET_L_OV_MASK 0x1
+#define SPK_OFFSET_L_OV_SHIFT 0x7
+#define SPK_OFFSET_L_MODE_MASK 0x1
+#define SPK_OFFSET_L_MODE_SHIFT 0x6
+#define SPK_LEAD_L_SW_MASK 0x1
+#define SPK_LEAD_L_SW_SHIFT 0x5
+#define SPK_OFFSET_L_SW_MASK 0x1F
+#define SPK_OFFSET_L_SW_SHIFT 0x0
+
+// (0x4A) SPK_CON4 (RO)
+#define SPK_TRIM_DONE_L_MASK 0x1
+#define SPK_TRIM_DONE_L_SHIFT 0x7
+#define SPK_LEAD_L_FLAG_MASK 0x1
+#define SPK_LEAD_L_FLAG_SHIFT 0x6
+#define SPK_LEAD_L_FLAG_DEG_MASK 0x1
+#define SPK_LEAD_L_FLAG_DEG_SHIFT 0x5
+#define SPK_OFFSET_L_MASK 0x1F
+#define SPK_OFFSET_L_SHIFT 0x0
+
+// (0x4B) SPK_CON5 (RW)
+#define SPK_RSV1_MASK 0x1
+#define SPK_RSV1_SHIFT 0x7
+#define SPKRCV_EN_L_MASK 0x1
+#define SPKRCV_EN_L_SHIFT 0x6
+#define SPKAB_OBIAS_L_MASK 0x3
+#define SPKAB_OBIAS_L_SHIFT 0x4
+#define SPK_SLEW_L_MASK 0x3
+#define SPK_SLEW_L_SHIFT 0x2
+#define SPK_FORCE_EN_L_MASK 0x1
+#define SPK_FORCE_EN_L_SHIFT 0x1
+#define SPK_INTG_RST_L_MASK 0x1
+#define SPK_INTG_RST_L_SHIFT 0x0
+
+// (0x4C) SPK_CON6 (RW)
+#define SPK_THER_SHDN_R_EN_MASK 0x1
+#define SPK_THER_SHDN_R_EN_SHIFT 0x6
+#define SPK_TRIM_EN_R_MASK 0x1
+#define SPK_TRIM_EN_R_SHIFT 0x4
+#define SPKMODE_R_MASK 0x1
+#define SPKMODE_R_SHIFT 0x2
+#define SPK_EN_R_MASK 0x1
+#define SPK_EN_R_SHIFT 0x0
+
+// (0x4D) SPK_CON7 (RW)
+#define SPK_OC_EN_R_MASK 0x1
+#define SPK_OC_EN_R_SHIFT 0x7
+#define SPKAB_OC_EN_R_MASK 0x1
+#define SPKAB_OC_EN_R_SHIFT 0x6
+#define SPK_OC_SHDN_DR_MASK 0x1
+#define SPK_OC_SHDN_DR_SHIFT 0x4
+#define SPK_VOL_R_MASK 0x7
+#define SPK_VOL_R_SHIFT 0x0
+
+// (0x4E) SPK_CON8 (RO/RW)
+#define SPK_RSV2_MASK 0x3F
+#define SPK_RSV2_SHIFT 0x2
+#define SPK_AB_OC_R_DEG_MASK 0x1
+#define SPK_AB_OC_R_DEG_SHIFT 0x1
+#define SPK_D_OC_R_DEG_MASK 0x1
+#define SPK_D_OC_R_DEG_SHIFT 0x0
+
+// (0x4F) SPK_CON9 (RO/RW)
+#define SPK_OFFSET_R_OV_MASK 0x1
+#define SPK_OFFSET_R_OV_SHIFT 0x7
+#define SPK_OFFSET_R_MODE_MASK 0x1
+#define SPK_OFFSET_R_MODE_SHIFT 0x6
+#define SPK_LEAD_R_SW_MASK 0x1
+#define SPK_LEAD_R_SW_SHIFT 0x5
+#define SPK_OFFSET_R_SW_MASK 0x1F
+#define SPK_OFFSET_R_SW_SHIFT 0x0
+
+// (0x50) SPK_CON10 (RO)
+#define SPK_TRIM_DONE_R_MASK 0x1
+#define SPK_TRIM_DONE_R_SHIFT 0x7
+#define SPK_LEAD_R_FLAG_MASK 0x1
+#define SPK_LEAD_R_FLAG_SHIFT 0x6
+#define SPK_LEAD_R_FLAG_DEG_MASK 0x1
+#define SPK_LEAD_R_FLAG_DEG_SHIFT 0x5
+#define SPK_OFFSET_R_MASK 0x1F
+#define SPK_OFFSET_R_SHIFT 0x0
+
+// (0x51) SPK_CON11 (RW)
+#define SPK_RSV3_MASK 0x1
+#define SPK_RSV3_SHIFT 0x7
+#define SPKRCV_EN_R_MASK 0x1
+#define SPKRCV_EN_R_SHIFT 0x6
+#define SPKAB_OBIAS_R_MASK 0x3
+#define SPKAB_OBIAS_R_SHIFT 0x4
+#define SPK_SLEW_R_MASK 0x3
+#define SPK_SLEW_R_SHIFT 0x2
+#define SPK_FORCE_EN_R_MASK 0x1
+#define SPK_FORCE_EN_R_SHIFT 0x1
+#define SPK_INTG_RST_R_MASK 0x1
+#define SPK_INTG_RST_R_SHIFT 0x0
+
+// (0x52) SPK_CON12 (RW)
+#define SPK_OC_AUTOFF_MASK 0x1
+#define SPK_OC_AUTOFF_SHIFT 0x3
+#define SPK_OC_DGLH_MASK 0x3
+#define SPK_OC_DGLH_SHIFT 0x1
+#define SPK_OCTH_D_MASK 0x1
+#define SPK_OCTH_D_SHIFT 0x0
+
+// (0x53) SPK_CON13 (RW)
+#define SPK_OC_WND_MASK 0x3
+#define SPK_OC_WND_SHIFT 0x4
+#define SPK_OC_THD_MASK 0x3
+#define SPK_OC_THD_SHIFT 0x0
+
+// (0x54) SPK_CON14 (RW)
+#define SPK_TRIM_DIV_MASK 0x3
+#define SPK_TRIM_DIV_SHIFT 0x4
+#define SPK_TRIM_DEG_MASK 0x3
+#define SPK_TRIM_DEG_SHIFT 0x0
+
+// (0x55) SPK_CON15 (RW)
+#define SPKAB_OBIAS_MASK 0x3
+#define SPKAB_OBIAS_SHIFT 0x6
+#define SPKAB_FB_ATT_MASK 0x3
+#define SPKAB_FB_ATT_SHIFT 0x2
+#define SPKAB_OVDRV_MASK 0x1
+#define SPKAB_OVDRV_SHIFT 0x0
+
+// (0x56) SPK_CON16 (RW)
+#define SPK_FBRC_EN_MASK 0x1
+#define SPK_FBRC_EN_SHIFT 0x6
+#define SPK_IBIAS_SEL_MASK 0x3
+#define SPK_IBIAS_SEL_SHIFT 0x4
+#define SPK_VCM_IBSEL_MASK 0x1
+#define SPK_VCM_IBSEL_SHIFT 0x3
+#define SPK_VCM_SEL_MASK 0x1
+#define SPK_VCM_SEL_SHIFT 0x2
+#define SPK_EN_VIEW_CLK_MASK 0x1
+#define SPK_EN_VIEW_CLK_SHIFT 0x1
+#define SPK_EN_VIEW_VCM_MASK 0x1
+#define SPK_EN_VIEW_VCM_SHIFT 0x0
+
+// (0x57) SPK_CON17 (RW)
+#define SPK_CCODE_MASK 0xF
+#define SPK_CCODE_SHIFT 0x4
+#define SPK_BTL_SET_MASK 0x3
+#define SPK_BTL_SET_SHIFT 0x0
+
+// (0x58) SPK_CON18 (RW)
+#define SPK_RSV_MASK 0xF
+#define SPK_RSV_SHIFT 0x0
+
+// (0x59) SPK_CON19 (RW)
+#define SPK_TD1_MASK 0x3
+#define SPK_TD1_SHIFT 0x4
+#define SPK_TD2_MASK 0x3
+#define SPK_TD2_SHIFT 0x0
+
+// (0x5A) SPK_CON20 (RW)
+#define SPK_DEPOP_EN_L_SW_MASK 0x1
+#define SPK_DEPOP_EN_L_SW_SHIFT 0x7
+#define SPK_DEPOP_EN_R_SW_MASK 0x1
+#define SPK_DEPOP_EN_R_SW_SHIFT 0x6
+#define SPKMODE_L_SW_MASK 0x1
+#define SPKMODE_L_SW_SHIFT 0x5
+#define SPKMODE_R_SW_MASK 0x1
+#define SPKMODE_R_SW_SHIFT 0x4
+#define SPK_RST_L_SW_MASK 0x1
+#define SPK_RST_L_SW_SHIFT 0x3
+#define SPK_RST_R_SW_MASK 0x1
+#define SPK_RST_R_SW_SHIFT 0x2
+#define SPK_EN_MODE_MASK 0x1
+#define SPK_EN_MODE_SHIFT 0x0
+
+// (0x5B) SPK_CON21 (RW)
+#define SPK_TRIM_EN_L_SW_MASK 0x1
+#define SPK_TRIM_EN_L_SW_SHIFT 0x7
+#define SPK_TRIM_EN_R_SW_MASK 0x1
+#define SPK_TRIM_EN_R_SW_SHIFT 0x6
+#define SPK_OUTSTG_EN_L_SW_MASK 0x1
+#define SPK_OUTSTG_EN_L_SW_SHIFT 0x5
+#define SPK_OUTSTG_EN_R_SW_MASK 0x1
+#define SPK_OUTSTG_EN_R_SW_SHIFT 0x4
+#define SPK_EN_L_SW_MASK 0x1
+#define SPK_EN_L_SW_SHIFT 0x3
+#define SPK_EN_R_SW_MASK 0x1
+#define SPK_EN_R_SW_SHIFT 0x2
+#define SPK_VCM_FAST_SW_MASK 0x1
+#define SPK_VCM_FAST_SW_SHIFT 0x0
+
+// (0x5C) SPK_CON22 (RW)
+#define SPK_TRIM_STOP_L_SW_MASK 0x1
+#define SPK_TRIM_STOP_L_SW_SHIFT 0x1
+#define SPK_TRIM_STOP_R_SW_MASK 0x1
+#define SPK_TRIM_STOP_R_SW_SHIFT 0x0
+
+// (0x5F) ASW_CON0 (RW)
+#define RG_ANA_SW_SEL_MASK 0x1
+#define RG_ANA_SW_SEL_SHIFT 0x0
+
+// (0x60) FGPLL_CON0 (RW)
+#define FGPLL_PDIV1_MASK 0xF
+#define FGPLL_PDIV1_SHIFT 0x4
+#define FGPLL_PDIV1_EN_MASK 0x1
+#define FGPLL_PDIV1_EN_SHIFT 0x3
+#define FGPLL_BS_RST_MASK 0x1
+#define FGPLL_BS_RST_SHIFT 0x1
+#define FGPLL_EN_MASK 0x1
+#define FGPLL_EN_SHIFT 0x0
+
+// (0x61) FGPLL_CON1 (RW)
+#define FGPLL_DIV1_MASK 0x3F
+#define FGPLL_DIV1_SHIFT 0x0
+
+// (0x62) FGPLL_CON2 (RW)
+#define FGPLL_BC_MASK 0x3
+#define FGPLL_BC_SHIFT 0x4
+#define FGPLL_BP_MASK 0x3
+#define FGPLL_BP_SHIFT 0x2
+#define FGPLL_BR_MASK 0x3
+#define FGPLL_BR_SHIFT 0x0
+
+// (0x63) FGPLL_CON3 (RW)
+#define FGPLL_CDIV_MASK 0x7
+#define FGPLL_CDIV_SHIFT 0x5
+#define FGPLL_VCOBAND_MASK 0x7
+#define FGPLL_VCOBAND_SHIFT 0x2
+#define FGPLL_CKO_SEL_MASK 0x3
+#define FGPLL_CKO_SEL_SHIFT 0x0
+
+// (0x64) FGPLL_CON4 (RW)
+#define FGPLL_IBSEL_MASK 0x3
+#define FGPLL_IBSEL_SHIFT 0x6
+#define FGPLL_RLATCH_EN_MASK 0x1
+#define FGPLL_RLATCH_EN_SHIFT 0x5
+#define FGPLL_CKDRV_EN_MASK 0x1
+#define FGPLL_CKDRV_EN_SHIFT 0x4
+#define FGPLL_VCT_EN_MASK 0x1
+#define FGPLL_VCT_EN_SHIFT 0x3
+#define FGPLL_CKT_SEL_MASK 0x3
+#define FGPLL_CKT_SEL_SHIFT 0x1
+#define FGPLL_CKT_EN_MASK 0x1
+#define FGPLL_CKT_EN_SHIFT 0x0
+
+// (0x65) FGPLL_CON5 (RW)
+#define FGPLL_RSVA_MASK 0xFF
+#define FGPLL_RSVA_SHIFT 0x0
+
+// (0x66) FGPLL_CON6 (RW)
+#define FGPLL_RSVB_MASK 0xFF
+#define FGPLL_RSVB_SHIFT 0x0
+
+// (0x69) FGADC_CON0 (RW)
+#define FG_CLKSRC_MASK 0x1
+#define FG_CLKSRC_SHIFT 0x7
+#define FG_AUTOCALRATE_MASK 0x7
+#define FG_AUTOCALRATE_SHIFT 0x4
+#define FG_CAL_MASK 0x3
+#define FG_CAL_SHIFT 0x2
+#define FG_VMODE_MASK 0x1
+#define FG_VMODE_SHIFT 0x1
+#define FG_ON_MASK 0x1
+#define FG_ON_SHIFT 0x0
+
+// (0x6A) FGADC_CON1 (RO/RW)
+#define FG_SW_RSTCLR_MASK 0x1
+#define FG_SW_RSTCLR_SHIFT 0x7
+#define FG_CHARGE_RST_MASK 0x1
+#define FG_CHARGE_RST_SHIFT 0x6
+#define FG_TIME_RST_MASK 0x1
+#define FG_TIME_RST_SHIFT 0x5
+#define FG_OFFSET_RST_MASK 0x1
+#define FG_OFFSET_RST_SHIFT 0x4
+#define FG_SW_CLEAR_MASK 0x1
+#define FG_SW_CLEAR_SHIFT 0x3
+#define FG_LATCHDATA_ST_MASK 0x1
+#define FG_LATCHDATA_ST_SHIFT 0x2
+#define FG_SW_READ_PRE_MASK 0x1
+#define FG_SW_READ_PRE_SHIFT 0x1
+#define FG_SW_CR_MASK 0x1
+#define FG_SW_CR_SHIFT 0x0
+
+// (0x6B) FGADC_CON2 (RO)
+#define FG_CAR_35_32_MASK 0xF
+#define FG_CAR_35_32_SHIFT 0x0
+
+// (0x6C) FGADC_CON3 (RO)
+#define FG_CAR_31_24_MASK 0xFF
+#define FG_CAR_31_24_SHIFT 0x0
+
+// (0x6D) FGADC_CON4 (RO)
+#define FG_CAR_23_16_MASK 0xFF
+#define FG_CAR_23_16_SHIFT 0x0
+
+// (0x6E) FGADC_CON5 (RO)
+#define FG_CAR_15_08_MASK 0xFF
+#define FG_CAR_15_08_SHIFT 0x0
+
+// (0x6F) FGADC_CON6 (RO)
+#define FG_CAR_07_00_MASK 0xFF
+#define FG_CAR_07_00_SHIFT 0x0
+
+// (0x70) FGADC_CON7 (RO)
+#define FG_NTER_29_24_MASK 0x3F
+#define FG_NTER_29_24_SHIFT 0x0
+
+// (0x71) FGADC_CON8 (RO)
+#define FG_NTER_23_16_MASK 0xFF
+#define FG_NTER_23_16_SHIFT 0x0
+
+// (0x72) FGADC_CON9 (RO)
+#define FG_NTER_15_08_MASK 0xFF
+#define FG_NTER_15_08_SHIFT 0x0
+
+// (0x73) FGADC_CON10 (RO)
+#define FG_NTER_07_00_MASK 0xFF
+#define FG_NTER_07_00_SHIFT 0x0
+
+// (0x74) FGADC_CON11 (RW)
+#define FG_BLTR_15_08_MASK 0xFF
+#define FG_BLTR_15_08_SHIFT 0x0
+
+// (0x75) FGADC_CON12 (RW)
+#define FG_BLTR_07_00_MASK 0xFF
+#define FG_BLTR_07_00_SHIFT 0x0
+
+// (0x76) FGADC_CON13 (RW)
+#define FG_BFTR_15_08_MASK 0xFF
+#define FG_BFTR_15_08_SHIFT 0x0
+
+// (0x77) FGADC_CON14 (RW)
+#define FG_BFTR_07_00_MASK 0xFF
+#define FG_BFTR_07_00_SHIFT 0x0
+
+// (0x78) FGADC_CON15 (RO)
+#define FG_CURRENT_OUT_15_08_MASK 0xFF
+#define FG_CURRENT_OUT_15_08_SHIFT 0x0
+
+// (0x79) FGADC_CON16 (RO)
+#define FG_CURRENT_OUT_07_00_MASK 0xFF
+#define FG_CURRENT_OUT_07_00_SHIFT 0x0
+
+// (0x7A) FGADC_CON17 (RW)
+#define FG_ADJUST_OFFSET_VALUE_15_08_MASK 0xFF
+#define FG_ADJUST_OFFSET_VALUE_15_08_SHIFT 0x0
+
+// (0x7B) FGADC_CON18 (RW)
+#define FG_ADJUST_OFFSET_VALUE_07_00_MASK 0xFF
+#define FG_ADJUST_OFFSET_VALUE_07_00_SHIFT 0x0
+
+// (0x7C) FGADC_CON19 (RO)
+#define FG_OFFSET_15_08_MASK 0xFF
+#define FG_OFFSET_15_08_SHIFT 0x0
+
+// (0x7D) FGADC_CON20 (RO)
+#define FG_OFFSET_07_00_MASK 0xFF
+#define FG_OFFSET_07_00_SHIFT 0x0
+
+// (0x7E) FGADC_CON21 (RW)
+#define FG_RSV0_MASK 0xF
+#define FG_RSV0_SHIFT 0x4
+#define FG_ANALOGTEST_MASK 0xF
+#define FG_ANALOGTEST_SHIFT 0x0
+
+// (0x7F) FGADC_CON22 (RW)
+#define FG_SPARE_MASK 0xFF
+#define FG_SPARE_SHIFT 0x0
+
+// (0x80) FGADC_CON23 (RW)
+#define FG_BLTR_BFTR_EN_MASK 0x1
+#define FG_BLTR_BFTR_EN_SHIFT 0x7
+#define FG_ADC_AUTORST_MASK 0x1
+#define FG_ADC_AUTORST_SHIFT 0x6
+#define FG_ADJ_OFFSET_EN_MASK 0x1
+#define FG_ADJ_OFFSET_EN_SHIFT 0x4
+#define FG_OSR_MASK 0x7
+#define FG_OSR_SHIFT 0x0
+
+// (0x81) FGADC_CON24 (RW)
+#define VOL_OSR_MASK 0x7
+#define VOL_OSR_SHIFT 0x0
+
+// (0x82) FGADC_CON25 (RO/RW)
+#define FG_ADC_RSTDETECT_MASK 0x1
+#define FG_ADC_RSTDETECT_SHIFT 0x7
+#define FG_H_INT_STS_MASK 0x1
+#define FG_H_INT_STS_SHIFT 0x5
+#define FG_L_INT_STS_MASK 0x1
+#define FG_L_INT_STS_SHIFT 0x4
+#define VOL_FIR1BYPASS_MASK 0x1
+#define VOL_FIR1BYPASS_SHIFT 0x2
+#define FG_FIR2BYPASS_MASK 0x1
+#define FG_FIR2BYPASS_SHIFT 0x1
+#define FG_FIR1BYPASS_MASK 0x1
+#define FG_FIR1BYPASS_SHIFT 0x0
+
+// (0x83) FGADC_CON26 (RO)
+#define VOL_CURRENT_OUT_15_08_MASK 0xFF
+#define VOL_CURRENT_OUT_15_08_SHIFT 0x0
+
+// (0x84) FGADC_CON27 (RO)
+#define VOL_CURRENT_OUT_07_00_MASK 0xFF
+#define VOL_CURRENT_OUT_07_00_SHIFT 0x0
+
+// (0x85) FGADC_CON28 (RO)
+#define FG_CIC2_15_08_MASK 0xFF
+#define FG_CIC2_15_08_SHIFT 0x0
+
+// (0x86) FGADC_CON29 (RO)
+#define FG_CIC2_07_00_MASK 0xFF
+#define FG_CIC2_07_00_SHIFT 0x0
+
+// (0x87) FGADC_CON30 (RW)
+#define FG_RSV1_MASK 0x7
+#define FG_RSV1_SHIFT 0x5
+#define FG_VMODE_SW_MASK 0x1
+#define FG_VMODE_SW_SHIFT 0x4
+#define FG_FGADC_EN_SW_MASK 0x1
+#define FG_FGADC_EN_SW_SHIFT 0x3
+#define FG_FGCAL_EN_SW_MASK 0x1
+#define FG_FGCAL_EN_SW_SHIFT 0x2
+#define FG_RST_SW_MASK 0x1
+#define FG_RST_SW_SHIFT 0x1
+#define FG_MODE_MASK 0x1
+#define FG_MODE_SHIFT 0x0
+
+// (0x88) FGADC_CON31 (RO)
+#define FG_MON_MASK 0xFF
+#define FG_MON_SHIFT 0x0
+
+// (0x89) FGADC_CON32 (RW)
+#define FG_RSV2_MASK 0xFF
+#define FG_RSV2_SHIFT 0x0
+
+// (0x8C) OTPC_CON0 (RO)
+#define RG_OTP_PDO_7_0_MASK 0xFF
+#define RG_OTP_PDO_7_0_SHIFT 0x0
+
+// (0x8D) OTPC_CON1 (RO)
+#define RG_OTP_PDO_15_8_MASK 0xFF
+#define RG_OTP_PDO_15_8_SHIFT 0x0
+
+// (0x8E) OTPC_CON2 (RO)
+#define RG_OTP_PDO_23_16_MASK 0xFF
+#define RG_OTP_PDO_23_16_SHIFT 0x0
+
+// (0x8F) OTPC_CON3 (RO)
+#define RG_OTP_PDO_31_24_MASK 0xFF
+#define RG_OTP_PDO_31_24_SHIFT 0x0
+
+// (0x90) OTPC_CON4 (RO)
+#define RG_OTP_PDO_39_32_MASK 0xFF
+#define RG_OTP_PDO_39_32_SHIFT 0x0
+
+// (0x91) OTPC_CON5 (RO)
+#define RG_OTP_PDO_47_40_MASK 0xFF
+#define RG_OTP_PDO_47_40_SHIFT 0x0
+
+// (0x92) OTPC_CON6 (RO)
+#define RG_OTP_PDO_55_48_MASK 0xFF
+#define RG_OTP_PDO_55_48_SHIFT 0x0
+
+// (0x93) OTPC_CON7 (RO)
+#define RG_OTP_PDO_63_56_MASK 0xFF
+#define RG_OTP_PDO_63_56_SHIFT 0x0
+
+// (0x94) OTPC_CON8 (RW)
+#define RG_OTP_PDIN_MASK 0xFF
+#define RG_OTP_PDIN_SHIFT 0x0
+
+// (0x95) OTPC_CON9 (RW)
+#define RG_OTP_PA_MASK 0x3
+#define RG_OTP_PA_SHIFT 0x6
+#define RG_OTP_PTM_MASK 0x3
+#define RG_OTP_PTM_SHIFT 0x4
+#define RG_OTP_PWE_MASK 0x3
+#define RG_OTP_PWE_SHIFT 0x2
+#define RG_OTP_PPROG_MASK 0x1
+#define RG_OTP_PPROG_SHIFT 0x1
+#define RG_OTP_READ_MASK 0x1
+#define RG_OTP_READ_SHIFT 0x0
+
+// (0x96) OTPC_CON10 (RW)
+#define RG_OTP_READ_PRD_MASK 0x3
+#define RG_OTP_READ_PRD_SHIFT 0x6
+
+// (0x97) OTPC_CON11 (RW)
+#define RG_OTP_TEST_SEL_MASK 0x7
+#define RG_OTP_TEST_SEL_SHIFT 0x5
+#define RG_OTP_SKIP_OUT_MASK 0x1
+#define RG_OTP_SKIP_OUT_SHIFT 0x4
+#define RG_OTP_OUT_SEL_MASK 0x3
+#define RG_OTP_OUT_SEL_SHIFT 0x2
+#define RG_OTP_RSV_MASK 0x3
+#define RG_OTP_RSV_SHIFT 0x0
+
+// (0x98) OTPC_CON12 (RW)
+#define RG_OTP_VAL_7_0_MASK 0xFF
+#define RG_OTP_VAL_7_0_SHIFT 0x0
+
+// (0x99) OTPC_CON13 (RW)
+#define RG_OTP_VAL_15_8_MASK 0xFF
+#define RG_OTP_VAL_15_8_SHIFT 0x0
+
+// (0x9A) OTPC_CON14 (RW)
+#define RG_OTP_VAL_23_16_MASK 0xFF
+#define RG_OTP_VAL_23_16_SHIFT 0x0
+
+// (0x9B) OTPC_CON15 (RW)
+#define RG_OTP_VAL_31_24_MASK 0xFF
+#define RG_OTP_VAL_31_24_SHIFT 0x0
+
+// (0x9C) OTPC_CON16 (RW)
+#define RG_OTP_VAL_39_32_MASK 0xFF
+#define RG_OTP_VAL_39_32_SHIFT 0x0
+
+// (0x9D) OTPC_CON17 (RW)
+#define RG_OTP_VAL_47_40_MASK 0xFF
+#define RG_OTP_VAL_47_40_SHIFT 0x0
+
+// (0x9E) OTPC_CON18 (RW)
+#define RG_OTP_VAL_55_48_MASK 0xFF
+#define RG_OTP_VAL_55_48_SHIFT 0x0
+
+// (0x9F) OTPC_CON19 (RW)
+#define RG_OTP_VAL_63_56_MASK 0xFF
+#define RG_OTP_VAL_63_56_SHIFT 0x0
+
+// (0xA0) OTPC_CON20 (RO/RW)
+#define RG_OTP_BUSY_MASK 0x1
+#define RG_OTP_BUSY_SHIFT 0x7
+#define RG_OTP_VLD_MASK 0x1
+#define RG_OTP_VLD_SHIFT 0x6
+#define RG_OTP_READ_RDY_BYPASS_MASK 0x1
+#define RG_OTP_READ_RDY_BYPASS_SHIFT 0x3
+
+// (0xA1) OTPC_CON21 (RW)
+#define RG_OTP_W_LOCK_MASK 0x1
+#define RG_OTP_W_LOCK_SHIFT 0x7
+#define RG_OTP_W_LOCK_KEY_TOG_MASK 0x1
+#define RG_OTP_W_LOCK_KEY_TOG_SHIFT 0x4
+#define RG_OTP_W_LOCK_KEY_MASK 0xF
+#define RG_OTP_W_LOCK_KEY_SHIFT 0x0
+
+// (0xA4) I2C_CON0 (RW)
+#define I2C_CON0_ADDR 0xA4
+
+#define SCL_DE_MASK 0x1F
+#define SCL_DE_SHIFT 0x0
+
+// (0xA5) I2C_CON1 (RW)
+#define I2C_CON1_ADDR 0xA5
+
+#define SDA_DE_MASK 0x1F
+#define SDA_DE_SHIFT 0x0
+
+#endif //#if defined(PMIC_6329_REG_API)
+
+#endif // #ifndef __DCL_PMIC6329_HW_H_STRUCT__
diff --git a/mcu/driver/peripheral/inc/dcl_pmic6329_sw.h b/mcu/driver/peripheral/inc/dcl_pmic6329_sw.h
new file mode 100644
index 0000000..2fb2508
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmic6329_sw.h
@@ -0,0 +1,148 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic6329_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMIC 6329
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+
+#ifndef __DCL_PMU6329_SW_H_STRUCT__
+#define __DCL_PMU6329_SW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#ifdef PMIC_6329_REG_API
+
+/*
+// debug 1
+// Define to keep chaging when assert
+// This flag is only for debug purpose
+//#define DRV_MISC_PMIC_ASSERT_KEEP_CHARGING
+//#define DEBUG_PMIC6329_NO_CHARGER_WATCHDOG_TIMER
+
+
+// debug 2
+// Define to enable PMIC6329 charger watch dog timer kick
+// When enable charger, PMIC6329 will enable a watch dog timer
+// We need to kick the timer periodically, to ontify PMIC6329 that BB is alive
+// If timeout, PMIC6329 will disable charge automatically
+// #### If this is NOT enabled, we will disable the watch dog timer function at boot time
+//#define ENABLE_PMIC_DRIVER_KICK_CHARGER_WATCHDOG_TIMER ==> Move to be activated by BMT charging algorithm, do NOT use this anymore
+*/
+
+#define PMIC6329_ECO_1_VERSION 0x01
+#define PMIC6329_ECO_2_VERSION 0x02
+
+#ifndef PMIC_OLD_STRUCTURE
+#define PMIC_OLD_STRUCTURE
+
+#endif //#define PMIC_OLD_STRUCTURE
+
+typedef enum
+{
+ AC_CHR_CALLBACK=0,
+ USB_CHR_CALLBACK
+}chr_callback_type;
+
+typedef struct
+{
+ void (*pmic_ac_det)(void);
+ void (*pmic_usb_det)(void);
+}pmic6329_chrdect_callbac_struct;
+
+extern void dcl_pmic6329_ChrDet_Registration(chr_callback_type type, void (*Callback)(void));
+
+// Combinational functions
+extern void dcl_pmic6329_EM_reg_write(kal_uint8 reg, kal_uint8 val);
+extern kal_uint8 dcl_pmic6329_EM_reg_read(kal_uint8 reg);
+extern void pmic6329_customization_init(void);
+/*
+// The following are implemented in custom files
+// MoDIS parser skip start
+extern void pmic6329_customization_init(void);
+extern void pmic6329_cust_vspk_enable(kal_bool enable);
+extern void pmic6329_csut_vsim_enable(kal_bool enable);
+extern void pmic6329_csut_vsim_sel(pmic_adpt_vsim_volt volt);
+extern void pmic6329_csut_vsim2_enable(kal_bool enable);
+extern void pmic6329_csut_vsim2_sel(pmic_adpt_vsim_volt sel);
+extern void pmic6329_csut_vusb_enable(kal_bool enable);
+extern void pmic6329_csut_vcama_enable(kal_bool enable);
+extern void pmic6329_csut_vcama_sel(pmic_adpt_vcama_volt vol);
+extern void pmic6329_csut_vcamd_enable(kal_bool enable);
+extern void pmic6329_csut_vcamd_sel(pmic_adpt_vcamd_volt volt);
+// MoDIS parser skip end
+*/
+
+#endif // #ifdef PMIC_6329_REG_API
+#endif // #ifndef __DCL_PMU6329_SW_H_STRUCT__
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmic_features.h b/mcu/driver/peripheral/inc/dcl_pmic_features.h
new file mode 100644
index 0000000..6730576
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmic_features.h
@@ -0,0 +1,547 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmic_features.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for PMU feature options.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef DCL_PMIC_FEATURES_H
+#define DCL_PMIC_FEATURES_H
+
+
+
+#if defined(MT6238PMU) || defined(MT6235PMU)
+ #define PMIC_FIXED_3_ADC_CH
+ #define PMIC_FIXED_CHR_EINT
+ #define PMIC_6238_CUSTOMIZATION
+ #define PMIC_6238_USB_FUNCTION
+
+ #define PMIC_PMU_SERIES
+ /* Charger/USB detect through USB PHY */
+ #define PMIC_CHR_USB_DETECT_THROUGH_USB
+ #define PMIC_CHR_USB_DET_EINT_LEVEL_ACTIVE_LOW // Charger det EINT interrupt LEVEL trigger active LOW
+ #define PMIC_CHR_USB_DET_EINT_LEVEL_TRIGGER // CHR/USB detection is LEVEL trigger
+
+ #define PMIC_6235_CV_TRIM_CALIBRATION
+
+ /* For internal use. */
+ #define PMIC_6238_REG_API
+ #define __CHARGER_SOFT_START__
+
+
+
+ #ifndef PMIC_PRESENT
+ #define PMIC_PRESENT
+ #endif
+
+#elif defined(MT6326_CCCI)
+ /* Provide VSIM sel and enable interface */
+ #define PMIC_VSIM_SEL_AND_ENABLE
+ /* Provide VSIM enable interface */
+ #define PMIC_VSIM_ENABLE
+ /* Provide VSIM2 sel and enable interface */
+ #define PMIC_VSIM2_SEL_AND_ENABLE
+ /* Provide VSIM2 enable interface */
+ #define PMIC_VSIM2_ENABLE
+ /* Provide PMIC LOCK interface */
+ #define PMIC_LOCK
+ /* For internal use. */
+ #define PMIC_6326_CCCI_REG_API
+
+ #define PMIC_CHR_DETECT_NONE
+
+ #ifndef PMIC_PRESENT
+ #define PMIC_PRESENT
+ #endif // #ifndef PMIC_PRESENT
+
+#elif defined(MT6253PMU)
+
+ #define PMIC_VSIM2_SEL
+ #define PMIC_FIXED_3_ADC_CH
+ #define PMIC_FIXED_CHR_EINT
+ #define PMIC_6253_CUSTOMIZATION
+ #define PMIC_6253_USB_FUNCTION
+
+
+ #define PMIC_PMU_SERIES
+ #define PMIC_CHR_USB_DET_EINT_LEVEL_ACTIVE_LOW // Charger det EINT interrupt LEVEL trigger active LOW
+ #define PMIC_CHR_USB_DET_EINT_LEVEL_TRIGGER // CHR/USB detection is LEVEL trigger
+ #define PMIC_CHR_USB_DETECT_THROUGH_USB
+
+
+ // PMIC support charge WDT functionality
+ // BMT driver will refer the compile option to enable/disable BMT level WDT
+ #define PMIC_CHARGE_WDT
+ /* For internal use. */
+ #define PMIC_6253_REG_API
+ #define __CHARGER_SOFT_START__
+
+ #define PMIC_6253_CV_TRIM_CALIBRATION
+
+
+
+ #ifndef PMIC_PRESENT
+ #define PMIC_PRESENT
+ #endif
+
+#define PMIC_FIXED_CHR_EINT
+#if defined(PMIC_FIXED_CHR_EINT)
+#define PMIC_FIXED_CHR_EINT_PIN 7
+#endif // #if defined(PMIC_FIXED_CHR_EINT)
+
+#elif defined(MT6236PMU)
+
+ #define PMIC_6236_REG_API
+ #define PMIC_6236_CUSTOMIZATION
+ //#define PMIC_6238_USB_FUNCTION
+
+ #define PMIC_PMU_SERIES
+ #define PMIC_CHR_USB_DET_EINT_LEVEL_ACTIVE_LOW // Charger det EINT interrupt LEVEL trigger active LOW
+ #define PMIC_CHR_USB_DET_EINT_LEVEL_TRIGGER // CHR/USB detection is LEVEL trigger
+ #define PMIC_CHR_USB_DETECT_THROUGH_USB /* Charger/USB detect through USB PHY */
+
+ #define PMIC_6236_CV_TRIM_CALIBRATION
+
+ #define PMIC_FIXED_3_ADC_CH
+ //#define PMIC_FIXED_4_ADC_CH
+ #define PMIC_FIXED_CHR_EINT
+ #define PMIC_6236_USB_FUNCTION
+
+
+ #ifndef PMIC_PRESENT
+ #define PMIC_PRESENT
+ #endif // #ifndef PMIC_PRESENT
+
+#elif defined(MT6251PMU)
+
+#define PMIC_6251_REG_API
+#define PMIC_6251_CUSTOMIZATION
+#define PMIC_SLIM_V3
+
+#define PMIC_FIXED_3_ADC_CH
+#define PMIC_FIXED_4_ADC_CH
+#define PMIC_FIXED_CHR_EINT
+
+#define PMIC_PMU_SERIES
+#define PMIC_CHR_USB_DET_EINT_LEVEL_ACTIVE_LOW // Charger det EINT interrupt LEVEL trigger active LOW
+#define PMIC_CHR_USB_DET_EINT_LEVEL_TRIGGER // CHR/USB detection is LEVEL trigger
+#define PMIC_CHR_USB_DETECT_THROUGH_PMU_BC11
+
+#ifndef PMIC_PRESENT
+#define PMIC_PRESENT
+#endif // #ifndef PMIC_PRESENT
+
+#define PMIC_FIXED_CHR_EINT
+
+/*
+#define __DRV_UPMU_LDO_V1__
+#define __DRV_UPMU_LDO_V1_STB_TD_AT_CON2_BIT6__
+#define __DRV_UPMU_BUCK_V1__
+#define __DRV_UPMU_KPLED_V1__
+#define __DRV_UPMU_BC11_V1__
+#define __DRV_UPMU_STRUP_V1__
+#define __DRV_UPMU_BOOST_V1__
+#define __DRV_UPMU_SPK_V1__
+#define __DRV_UPMU_ISINK_V1__
+*/
+#define __DRV_UPMU_CHARGER_V1__
+ #define __DRV_OTG_BVALID_DET_AT_CON5_BIT15__
+ #define __DRV_VBAT_OV_EN_AT_CON3_BIT8__
+ #define __DRV_BATON_EN_AT_CON3_BIT9__
+ #define __DRV_OTG_BVALID_EN_AT_CON5_BIT12__
+ #define __DRV_OTG_BVALID_DET_AT_CON5_BIT15__
+ #define __DRV_CHR_WDT_CLEAR_WAIT_2MS__ // design limitation, need to wait for clock sync
+ #define __DRV_VBAT_OV_VTH_CON3_3BIT_WIDTH_VTH2_AT_BIT12__
+ #define __DRV_UPMU_BC11_V1__
+ // Use USB module 1.5KOhm pull high resistor for group B identify process
+ // Need to isolate USB DP/MP line to make 1.5KOhm resistor work
+ // (1.5KOhm resistor has some enable dependency on isolation switch)
+ //#define __DRV_BC11_USE_USB_100_K_RESISTOR_4_GROUP_B__
+ // Use USB module provided USB line status check API
+ // 1. USB module provide line status check API: 2.0V <-> 0.8V
+ // Higher than 2.0V ==> HIGH
+ // Lower than 0.8V ==> LOW
+ // 2. PMU BC11 circuit provide 1.2V comparator
+ //#define __DRV_BC11_USE_USB_LINE_STATUS_API__
+ #define __DRV_UPMU_BC11_VSRC_EN_AT_TEST_CON1_BIT4__
+#if defined(MT6251_S00)
+ #define __MT6251PMU_E1_BC11_VSRC_EN_AT_TEST_CON1_BIT4__
+#endif //#if defined(MT6251_S00)
+ #define __DRV_CHR_FLAG_SEL_5BIT_WIDTH_SEL4_AT_BIT13__
+
+#elif defined(MT6252PMU) || defined(MT6253ELPMU)
+#define PMIC_6252_REG_API
+#define PMIC_6252_CUSTOMIZATION
+
+#define PMIC_FIXED_3_ADC_CH
+#define PMIC_FIXED_CHR_EINT
+#define PMIC_SLIM_V3
+
+#define PMIC_PMU_SERIES
+#define PMIC_CHR_USB_DET_EINT_LEVEL_ACTIVE_LOW // Charger det EINT interrupt LEVEL trigger active HIGH
+#define PMIC_CHR_USB_DET_EINT_LEVEL_TRIGGER // CHR/USB detection is LEVEL trigger
+#define PMIC_CHR_USB_DETECT_THROUGH_PMU_BC11
+
+#ifndef PMIC_PRESENT
+#define PMIC_PRESENT
+#endif // #ifndef PMIC_PRESENT
+
+#define __DRV_UPMU_BC11_V1__
+
+#elif defined(MT6255PMU)
+#define PMIC_6255_REG_API
+
+ #define PMIC_FIXED_3_ADC_CH
+ #define PMIC_FIXED_4_ADC_CH
+ #define PMIC_FIXED_CHR_EINT
+ #define PMIC_SLIM_V3
+
+#define PMIC_PMU_SERIES
+#define PMIC_CHR_USB_DET_EINT_LEVEL_ACTIVE_LOW// Charger det EINT interrupt LEVEL trigger active low
+#define PMIC_CHR_USB_DET_EINT_LEVEL_TRIGGER // CHR/USB detection is LEVEL trigger
+#define PMIC_CHR_USB_DETECT_THROUGH_PMU_BC11
+#define __DRV_UPMU_BC11_V1__
+
+#ifndef PMIC_PRESENT
+#define PMIC_PRESENT
+#endif // #ifndef PMIC_PRESENT
+
+
+#elif defined(MT6256PMU)
+#define PMIC_6256_REG_API
+#define PMIC_6256_CUSTOMIZATION
+
+ #define PMIC_FIXED_3_ADC_CH
+ #define PMIC_FIXED_4_ADC_CH
+ #define PMIC_FIXED_CHR_EINT
+ #define PMIC_SLIM_V3
+
+#define PMIC_PMU_SERIES
+#define PMIC_CHR_USB_DET_EINT_LEVEL_ACTIVE_LOW// Charger det EINT interrupt LEVEL trigger active low
+#define PMIC_CHR_USB_DET_EINT_LEVEL_TRIGGER // CHR/USB detection is LEVEL trigger
+#define PMIC_CHR_USB_DETECT_THROUGH_PMU_BC11
+#define __DRV_UPMU_BC11_V1__
+
+#ifndef PMIC_PRESENT
+#define PMIC_PRESENT
+#endif // #ifndef PMIC_PRESENT
+
+#elif defined(MT6276PMU)
+
+#define PMIC_6276_REG_API
+#define PMIC_6276_CUSTOMIZATION
+
+
+#define PMIC_PMU_SERIES
+#define PMIC_CHR_USB_DET_EINT_LEVEL_ACTIVE_HIGH // Charger det EINT interrupt LEVEL trigger active HIGH
+#define PMIC_CHR_USB_DET_EINT_LEVEL_TRIGGER // CHR/USB detection is LEVEL trigger
+#define PMIC_CHR_USB_DETECT_THROUGH_USB
+
+#ifndef PMIC_PRESENT
+#define PMIC_PRESENT
+#endif // #ifndef PMIC_PRESENT
+
+#define PMIC_FIXED_3_ADC_CH
+#define PMIC_FIXED_CHR_EINT
+#if defined(PMIC_FIXED_CHR_EINT)
+#define PMIC_FIXED_CHR_EINT_PIN 29
+#endif // #if defined(PMIC_FIXED_CHR_EINT)
+
+#define __DRV_UPMU_LPOSC_V1__
+#define __DRV_UPMU_LDO_V1__
+#define __DRV_UPMU_SHARE_LDO__
+#if defined(MT6276_S00)
+#define __MT6276PMU_E1_VSIM2_VOLSEL_ISSUE__
+#endif //#if defined(MT6276_S00)
+#define __DRV_UPMU_LDO_V1_STB_TD_AT_CON1_BIT0__
+#define __DRV_UPMU_BUCK_V1__
+#define __DRV_UPMU_VPA_V1__
+#define __DRV_UPMU_KPLED_V1__
+#define __DRV_UPMU_CHARGER_V1__
+#define __DRV_OTG_BVALID_EN_AT_CON3_BIT13__
+#define __DRV_BATON_EN_AT_CON3_BIT12__
+#define __DRV_UPMU_BC11_V1__
+#define __DRV_UPMU_BC11_MAPPING_V2__
+
+#elif defined(MT6573PMU)
+
+ #define PMIC_6573_REG_API
+
+ #define __DRV_UPMU_BUCK_V1__
+ #define __MT6573PMU_E1_VSIM2_VOLSEL_ISSUE__
+ #define __DRV_UPMU_VPA_V1__
+
+ #define PMIC_FIXED_3_ADC_CH
+ #define PMIC_FIXED_CHR_EINT
+ #define PMIC_CHR_DETECT_NONE
+
+ #ifndef PMIC_PRESENT
+ #define PMIC_PRESENT
+ #endif // #ifndef PMIC_PRESENT
+
+#elif defined(MT6326)
+ #define PMIC_VSIM_SEL
+ #define PMIC_VSIM2_SEL
+ #define PMIC_AUDIO_AMP
+ #define PMIC_6326_CUSTOMIZATION
+ #define PMIC_6326_USB_FUNCTION
+ #define PMIC_VCAMD_SEL
+ #define PMIC_VCAMD_EN
+ #define PMIC_VCAMA_SEL
+ #define PMIC_VCAMA_EN
+
+ #define PMIC_CHR_USB_DET_EINT_EDGE_TRIGGER // CHR/USB detection is edge trigger
+
+ /* For internal use. */
+ #define PMIC_6326_REG_API
+ // PMIC support charge WDT functionality
+ // BMT driver will refer the compile option to enable/disable BMT level WDT
+ #define PMIC_CHARGE_WDT
+
+ #define PMIC_6326_CV_TRIM_CALIBRATION
+
+ #define PMIC_PMIC_SERIES
+ /* Charger/USB detect through USB PHY */
+ #define PMIC_CHR_USB_DETECT_THROUGH_USB
+
+ #ifndef PMIC_PRESENT
+ #define PMIC_PRESENT
+ #endif // #ifndef PMIC_PRESENT
+
+ #define __CHARGER_SOFT_START__
+
+#elif defined(MT6329)
+ #define PMIC_VSIM_SEL
+ #define PMIC_VSIM2_SEL
+ #define PMIC_AUDIO_AMP
+ #define PMIC_6329_CUSTOMIZATION
+ #define PMIC_6329_USB_FUNCTION
+ #define PMIC_VCAMD_SEL
+ #define PMIC_VCAMD_EN
+ #define PMIC_VCAMA_SEL
+ #define PMIC_VCAMA_EN
+
+ #define PMIC_CHR_USB_DET_EINT_EDGE_TRIGGER // CHR/USB detection is edge trigger
+
+ /* For internal use. */
+ #define PMIC_6329_REG_API
+ // PMIC support charge WDT functionality
+ // BMT driver will refer the compile option to enable/disable BMT level WDT
+ #define PMIC_CHARGE_WDT
+
+ #define PMIC_6329_CV_TRIM_CALIBRATION
+
+ #define PMIC_PMIC_SERIES
+ /* Charger/USB detect through USB PHY */
+ #define PMIC_CHR_USB_DETECT_THROUGH_USB
+
+ #ifndef PMIC_PRESENT
+ #define PMIC_PRESENT
+ #endif // #ifndef PMIC_PRESENT
+
+ #define __CHARGER_SOFT_START__
+
+#elif defined(MT6327)
+ #define PMIC_VSIM_SEL
+
+ /* For internal use. */
+ #define PMIC_6327_REG_API
+
+ #define PMIC_PMIC_SERIES
+
+ #define PMIC_CHR_DETECT_NONE
+
+ #ifndef PMIC_PRESENT
+ #define PMIC_PRESENT
+ #endif // #ifndef PMIC_PRESENT
+
+#else
+
+ #define PMIC_CHR_DETECT_NONE
+
+#endif
+
+#endif // #ifndef DCL_PMIC_FEATURES_H
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6235_hw.h b/mcu/driver/peripheral/inc/dcl_pmu6235_hw.h
new file mode 100644
index 0000000..29840c4
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6235_hw.h
@@ -0,0 +1,483 @@
+
+
+#ifndef __DCL_PMIC6235_HW_H_STRUCT__
+#define __DCL_PMIC6235_HW_H_STRUCT__
+
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6223_REG_API) || defined(PMIC_6238_REG_API)
+
+#define PMU_BASE (MIXED_base+0x0800)
+#define PMU_END (MIXED_base+0x0840)
+
+#ifndef DRV_PMIC_OFF
+#define PMIC_CON0 (MIXED_base+0x0800)
+#define PMIC_CON1 (MIXED_base+0x0804)
+#define PMIC_CON2 (MIXED_base+0x0808)
+#define PMIC_CON3 (MIXED_base+0x080C)
+#define PMIC_CON4 (MIXED_base+0x0810)
+#define PMIC_CON5 (MIXED_base+0x0814)
+#define PMIC_CON6 (MIXED_base+0x0818)
+#define PMIC_CON7 (MIXED_base+0x081C)
+#if defined(PMIC_6238_REG_API)
+#define PMIC_CON8 (MIXED_base+0x0820)
+#define PMIC_CON9 (MIXED_base+0x0824)
+#define PMIC_CONA (MIXED_base+0x0828)
+#define PMIC_CONB (MIXED_base+0x082C)
+#define PMIC_CONC (MIXED_base+0x0830)
+#define PMIC_COND (MIXED_base+0x0834)
+#define PMIC_CONE (MIXED_base+0x0838)
+#define PMIC_CONF (MIXED_base+0x083C)
+#define PMIC_CONG (MIXED_base+0x0840)
+#endif // #if defined(PMIC_6238_REG_API)
+#endif // #ifndef DRV_PMIC_OFF
+
+/* PMIC_CON0: Control LDC of Vrf and test setting */
+#define VRF_STATUS 0x0001
+ #define VRF_STATUS_SHIFT 0
+#define VRF_EN 0x0002
+ #define VRF_EN_SHIFT 1
+#define VRF_EN_FORCE 0x0004
+ #define VRF_EN_FORCE_SHIFT 2
+#define VRF_PLNMOS_DIS 0x0008
+ #define VRF_PLNMOS_DIS_SHIFT 3
+#define ICALRF_EN 0x0030
+ #define ICALRF_EN_SHIFT 4
+#define VRF_CAL 0x03C0
+ #define VRF_CAL_SHIFT 6
+#if defined(PMIC_6238_REG_API)
+ #define VRF_ON_SEL 0x0400
+ #define VRF_ON_SEL_SHIFT 10
+#endif
+#define TPSEL 0xF000
+ #define TPSEL_SHIFT 12
+
+/* PMIC_CON1: Control LDO of Vcore, Vrtc, and status of Vio and Vm */
+#define VCORE_EN_FORCE 0x0001
+ #define VCORE_EN_FORCE_SHIFT 0
+
+#if defined(PMIC_6223_REG_API)
+#define ICALCORE_EN 0x0006
+ #define ICALCORE_EN_SHIFT 1
+#define VCORE_SEL 0x0018
+ #define VCORE_SEL_SHIFT 3
+#define VCORE_CAL 0x01E0
+ #define VCORE_CAL_SHIFT 5
+#define VCTXO_PWRSAVE_EN 0x0200
+ #define VCTXO_PWRSAVE_EN_SHIFT 9
+#define VRF_PWRSAVE_EN 0x0400
+ #define VRF_PWRSAVE_EN_SHIFT 10
+
+#elif defined(PMIC_6238_REG_API)
+#define ADC_IN_EDGE 0x0002
+ #define ADC_IN_EDGE_SHIFT 1
+#define FAST_SLOW 0x0004
+ #define FAST_SLOW_SHIFT 2
+#define PWMB 0x0008
+ #define PWMB_SHIFT 3
+#define ACC_OUT_INIT 0x00F0
+ #define ACC_OUT_INIT_SHIFT 4
+
+#endif /*PMIC_6223_REG_API*/
+
+#define VRTC_STATUS 0x1000
+ #define VRTC_STATUS_SHIFT 12
+#define VRTC_EN_FORE 0x2000
+ #define VRTC_EN_FORE_SHIFT 13
+#define VIO_STATUS 0x4000
+ #define VIO_STATUS_SHIFT 14
+
+#if defined(PMIC_6223_REG_API)
+#define VM_STATUS 0x8000
+ #define VM_STATUS_SHIFT 15
+#endif /* PMIC_6223_REG_API*/
+
+/* PMIC_CON2: Control LDO of Vio and Vm */
+#define VIO_EN_FORCE 0x0001
+ #define VIO_EN_FORCE_SHIFT 0
+#define VCALIO_EN 0x0006
+ #define VCALIO_EN_SHIFT 1
+#define ANTIUDSH_IO_DN 0x0008
+ #define ANTIUDSH_IO_DN_SHIFT 3
+#define VIO_CAL 0x00F0
+ #define VIO_CAL_SHIFT 4
+#define VM_EN_FORCE 0x0100
+ #define VM_EN_FORCE_SHIFT 8
+#define ICALM_EN 0x0600
+ #define ICALM_EN_SHIFT 9
+#define ANTIUDSH_M_DN 0x0800
+ #define ANTIUDSH_M_DN_SHIFT 11
+#define VM_CAL 0xF000
+ #define VM_CAL_SHIFT 12
+
+/* PMIC_CON3: Control and Status of LDO of Vsim, Calibration of Vrtc */
+#define VSIM_STATUS 0x0001
+ #define VSIM_STATUS_SHIFT 0
+#define VSIM_EN_FORCE 0x0002
+ #define VSIM_EN_FORCE_SHIFT 1
+#define ICALSIM_EN 0x000C
+ #define ICALSIM_EN_SHIFT 2
+#define ANTIUDSH_SIM_DN 0x0010
+ #define ANTIUDSH_SIM_DN_SHIFT 4
+#define VSIM_PLNMOS_DIS 0x0020
+ #define VSIM_PLNMOS_DIS_SHIFT 5
+#define VSIM_CAL 0x03C0
+ #define VSIM_CAL_SHIFT 6
+#define VRTC_STEP1_CAL 0x1C00
+ #define VRTC_STEP1_CAL_SHIFT 10
+#define VRTC_STEP2_CAL 0xE000
+ #define VRTC_STEP2_CAL_SHIFT 13
+
+/* PMIC_CON4: Control and Status of LDC of Vctxo and Va*/
+#define VCTXO_STATUS 0x0001
+ #define VCTXO_STATUS_SHIFT 0
+#define VCTXO_EN_FORCE 0x0002
+ #define VCTXO_EN_FORCE_SHIFT 1
+#define VCTXO_EN 0x0004
+ #define VCTXO_EN_SHIFT 2
+#define VCTXO_PLNMOS_DIS 0x0008
+ #define VCTXO_PLNMOS_DIS_SHIFT 3
+#define VCTXO_CAL 0x00F0
+ #define VCTXO_CAL_SHIFT 4
+#define VA_STATUS 0x0100
+ #define VA_STATUS_SHIFT 8
+#define VA_EN_FORCE 0x0200
+ #define VA_EN_FORCE_SHIFT 9
+#define VA_EN_SEL 0x0400
+ #define VA_EN_SEL_SHIFT 10
+#define VA_CAL 0x7800
+ #define VA_CAL_SHIFT 11
+#define VRTC_CAL_LATCH_EN 0x8000
+ #define VRTC_CAL_LATCH_EN_SHIFT 15
+
+/* PMIC_CON5: Driver Control and Charger Staus */
+#define VIBR_EN 0x0001
+ #define VIBR_EN_SHIFT 0
+#define KPLEN_EN 0x0002
+ #define KPLEN_EN_SHIFT 1
+#define RLED_EN 0x0004
+ #define RLED_EN_SHIFT 2
+#define GLEN_EN 0x0008
+ #define GLEN_EN_SHIFT 3
+#define BLEN_EN 0x0010
+ #define BLEN_EN_SHIFT 4
+#define INT_NODE_MUX 0x00E0
+#define INT_NODE_MUX_MSB 0x0080
+ #define INT_NODE_MUX_SHIFT 5
+#define VSIM_EN 0x0100
+ #define VSIM_EN_SHIFT 8
+#define VSIM_SEL 0x0200
+ #define VSIM_SEL_SHIFT 9
+#define OVP 0x0400
+ #define OVP_SHIFT 10
+#define CHR_DET 0x0800
+ #define CHR_DET_SHIFT 11
+#define BAT_ON 0x1000
+ #define BAT_ON_SHIFT 12
+#define AC_DET 0x2000
+ #define AC_DET_SHIFT 13
+#define CV 0x4000
+ #define CV_SHIFT 14
+#define CHRG_DIS 0x8000
+ #define CHRG_DIS_SHIFT 15
+
+/* PMIC_CON6: Charger Control */
+#define CHR_EN 0x0001
+ #define CHR_EN_SHIFT 0
+#define CHOFST 0x000E
+ #define CHOFST_SHIFT 1
+#define CLASS_D 0x0070
+ #define CLASS_D_SHIFT 4
+#define CHRON_FORCE 0x0080
+ #define CHRON_FORCE_SHIFT 7
+
+#if defined(PMIC_6223_REG_API)
+#define CHR_AUX 0xFF00
+ #define CHR_AUX_SHIFT 8
+ #define CHR_AUX_THERMAL 0x8800
+ #define CHR_AUX_THERMAL_SHIFT 11
+ #define CHR_AUX_REF_VOLT 0x7000
+ #define CHR_AUX_REF_VOLT_SHIFT 12
+ #define CHR_AUX_CV_VOLT 0x0700
+ #define CHR_AUX_CV_VOLT_SHIFT 8
+
+#elif defined(PMIC_6238_REG_API)
+#define CV_RT 0x0300
+ #define CV_RT_SHIFT 8
+#define CV_TUNE 0x1C00
+ #define CV_TUNE_SHIFT 10
+#define MTV_EN 0x4000
+ #define MTV_EN_SHIFT 14
+#define GPIO_DRV 0x8000
+ #define GPIO_DRV_SHIFT 15
+
+#endif
+
+/* PMIC_CON7: Start Up*/
+#define UV_SEL 0x0003
+ #define UV_SEL_SHIFT 0
+#define RBGSEL 0x001C
+ #define RBGSEL_SHIFT 2
+#define IBGSEL 0x0060
+ #define IBGSEL_SHIFT 5
+#define OSCDIS 0x0080
+ #define OSCDIS_SHIFT 7
+#define CKSEL 0x0100
+ #define CKSEL_SHIFT 8
+#define VBSSEL 0x0600
+ #define VBSSEL_SHIFT 9
+
+#if defined(PMIC_6223_REG_API)
+#define RESET_DRV 0x0800
+ #define RESET_DRV_SHIFT 11
+
+#elif defined(PMIC_6238_REG_API)
+#define BIAS_GEN_FORCE 0x0800
+ #define BIAS_GEN_FORCE_SHIFT 11
+
+#endif
+
+#define OV_HYS_ENB 0x1000
+ #define OV_HYS_ENB_SHIFT 12
+#define OV_THFREEZE 0x2000
+ #define OV_THFREEZE_SHIFT 13
+#define PWRKEY_DEB 0x8000
+ #define PWRKEY_DEB_SHIFT 15
+
+
+#if defined(PMIC_6238_REG_API)
+
+/* PMIC_CON8: DC-DC controller VCORE */
+#define SDM_ORDER 0x0001
+ #define SDM_ORDER_SHIFT 0
+#define GAIN_P 0x000E
+ #define GAIN_P_SHIFT 1
+#define GAIN 0x0070
+ #define GAIN_SHIFT 4
+#define GAIN_D 0x0380
+ #define GAIN_D_SHIFT 7
+#define DUTY_INIT 0x3C00
+ #define DUTY_INIT_SHIFT 10
+#define VOSEL 0x4000
+ #define VOSEL_SHIFT 14
+#define SDM_FB_EN 0x8000
+ #define SDM_FB_EN_SHIFT 15
+
+/* PMIC_CON9: DC-DC controller VCORE */
+#define VFBADJ 0x000F
+ #define VFBADJ_SHIFT 0
+#define DIRECT_CTRL_EN 0x0010
+ #define DIRECT_CTRL_EN_SHIFT 4
+#define DCV_CK_SEL 0x0020
+ #define DCV_CK_SEL_SHIFT 5
+#define ISEL 0x00C0
+ #define ISEL_SHIFT 6
+#define ADJCKSEL 0x0700
+ #define ADJCKSEL_SHIFT 8
+#define MODESET 0x0800
+ #define MODESET_SHIFT 11
+#define MODEEN0 0x1000
+ #define MODEEN0_SHIFT 12
+#define MODECMP 0x2000
+ #define MODECMP_SHIFT 13
+#define MODESEL1A 0x4000
+ #define MODESEL1A_SHIFT 14
+#define DCV_TEST_EN 0x8000
+ #define DCV_TEST_EN_SHIFT 15
+
+/* PMIC_CONA: DC-DC controller VCORE */
+#define PFMSEL_CURRENT 0x000F
+ #define PFMSEL_CURRENT_SHIFT 0
+#define PFMSEL_RESISTOR 0x0070
+ #define PFMSEL_RESISTOR_SHIFT 4
+#define NCDOF 0x0180
+ #define NCDOF_SHIFT 7
+#define DCVTRIM 0x0E00
+ #define DCVTRIM_SHIFT 9
+#define IASEL 0x3000
+ #define IASEL_SHIFT 12
+#define RSEL 0xC000
+ #define RSEL_SHIFT 14
+
+/* PMIC_CONB: Control and Status of LDO of Vusb */
+#define VUSB_STAUS 0x0001
+ #define VUSB_STAUS_SHIFT 0
+#define VUSB_EN_FORCE 0x0002
+ #define VUSB_EN_FORCE_SHIFT 1
+#define VUSB_EN 0x0004
+ #define VUSB_EN_SHIFT 2
+#define ICALUSB_EN 0x0018
+ #define ICALUSB_EN_SHIFT 3
+#define ANTIUDSH_USB_DN 0x0020
+ #define ANTIUDSH_USB_DN_SHIFT 5
+#define VUSB_PLNMOS_DIS 0x0040
+ #define VUSB_PLNMOS_DIS_SHIFT 6
+#define VUSB_CAL 0x0780
+ #define VUSB_CAL_SHIFT 7
+#define MODEEN1 0x0800
+ #define MODEEN1_SHIFT 11
+#define VFBADJ_SLP 0xF000
+ #define VFBADJ_SLP_SHIFT 12
+
+/* PMIC_CONC: Control and Status of LDO of Vsim2 */
+#define VSIM2_STAUS 0x0001
+ #define VSIM2_STAUS_SHIFT 0
+#define VSIM2_EN_FORCE 0x0002
+ #define VSIM2_EN_FORCE_SHIFT 1
+#define ICALSIM2_EN 0x000C
+ #define ICALSIM2_EN_SHIFT 2
+#define ANTIUDSH_SIM2_DN 0x0010
+ #define ANTIUDSH_SIM2_DN_SHIFT 4
+#define VSIM2_PLNMOS_DIS 0x0020
+ #define VSIM2_PLNMOS_DIS_SHIFT 5
+#define VSIM2_CAL 0x03C0
+ #define VSIM2_CAL_SHIFT 6
+#define CLK_SOURCE_SEL 0x0400
+ #define CLK_SOURCE_SEL_SHIFT 10
+#define VTCXO_ON_SEL 0x0800
+ #define VTCXO_ON_SEL_SHIFT 11
+#define VSIM_PWR_SAVING 0x1000
+ #define VSIM_PWR_SAVING_SHIFT 12
+#define VSIM2_EN 0x4000
+ #define VSIM2_EN_SHIFT 14
+#define VSIM2_SEL 0x8000
+ #define VSIM2_SEL_SHIFT 15
+
+/* PMIC_COND: Control and Status of LDO of Vmc, Not used from now*/
+//#define VMC_STAUS 0x0001
+// #define VMC_STAUS_SHIFT 0
+//#define VMC_EN_FORCE 0x0002
+// #define VMC_EN_FORCE_SHIFT 1
+//#define ICALMC_EN 0x000C
+// #define ICALMC_EN_SHIFT 2
+//#define ANTIUDSH_MC_DN 0x0010
+// #define ANTIUDSH_MC_DN_SHIFT 4
+//#define VMC_PLNMOS_DIS 0x0020
+// #define VMC_PLNMOS_DIS_SHIFT 5
+//#define VMC_CAL 0x03C0
+// #define VMC_CAL_SHIFT 6
+//#define VMC_EN 0x4000
+// #define VMC_EN_SHIFT 14
+//#define VMC_SEL 0x8000
+// #define VMC_SEL_SHIFT 15
+/* PMIC_COND: Control and Status of LDO of Vbt */
+#define VBT_STAUS 0x0001
+ #define VBT_STAUS_SHIFT 0
+#define VBT_EN_FORCE 0x0002
+ #define VBT_EN_FORCE_SHIFT 1
+#define ICALBT_EN 0x000C
+ #define ICALBT_EN_SHIFT 2
+#define ANTIUDSH_BT_DN 0x0010
+ #define ANTIUDSH_BT_DN_SHIFT 4
+#define VBT_PLNMOS_DIS 0x0020
+ #define VBT_PLNMOS_DIS_SHIFT 5
+#define VBT_CAL 0x03C0
+ #define VBT_CAL_SHIFT 6
+#define VBT_EN 0x4000
+ #define VBT_EN_SHIFT 14
+#define VBT_SEL 0x8000
+ #define VBT_SEL_SHIFT 15
+
+/* PMIC_CONE: Control and Status of LDO of Vcamera, NOT used from now */
+//#define VCAMERA_STAUS 0x0001
+// #define VCAMERA_STAUS_SHIFT 0
+//#define VCAMERA_EN_FORCE 0x0002
+// #define VCAMERA_EN_FORCE_SHIFT 1
+//#define ICALCAMERA_EN 0x000C
+// #define ICALCAMERA_EN_SHIFT 2
+//#define ANTIUDSH_CAMERA_DN 0x0010
+// #define ANTIUDSH_CAMERA_DN_SHIFT 4
+//#define VCAMERA_PLNMOS_DIS 0x0020
+// #define VCAMERA_PLNMOS_DIS_SHIFT 5
+//#define VCAMERA_CAL 0x03C0
+// #define VCAMERA_CAL_SHIFT 6
+//#define DCV_SLEW_CTRL 0x1C00
+// #define DCV_SLEW_CTRL_SHIFT 10
+//#define VCAMERA_EN 0x2000
+// #define VCAMERA_EN_SHIFT 13
+//#define VCAMERA_SEL 0xC000
+// #define VCAMERA_SEL_SHIFT 14
+/* PMIC_CONE: Control and Status of LDO of Vcam_d */
+#define VCAM_D_STAUS 0x0001
+ #define VCAM_D_STAUS_SHIFT 0
+#define VCAM_D_EN_FORCE 0x0002
+ #define VCAM_D_EN_FORCE_SHIFT 1
+#define ICALCAM_D_EN 0x000C
+ #define ICALCAM_D_EN_SHIFT 2
+#define ANTIUDSH_CAM_D_DN 0x0010
+ #define ANTIUDSH_CAM_D_DN_SHIFT 4
+#define VCAM_D_PLNMOS_DIS 0x0020
+ #define VCAM_D_PLNMOS_DIS_SHIFT 5
+#define VCAM_D_CAL 0x03C0
+ #define VCAM_D_CAL_SHIFT 6
+#define DCV_SLEW_CTRL 0x1C00
+ #define DCV_SLEW_CTRL_SHIFT 10
+#define VCAM_D_EN 0x2000
+ #define VCAM_D_EN_SHIFT 13
+#define VCAM_D_SEL 0xC000
+ #define VCAM_D_SEL_SHIFT 14
+
+
+/* PMIC_CONF: Control and Status of LDO of Vswa, Vtcxo, Va, NOT used from now */
+//#define VSW_A_STAUS 0x0001
+// #define VSW_A_STAUS_SHIFT 0
+//#define VSW_A_EN_FORCE 0x0002
+// #define VSW_A_EN_FORCE_SHIFT 1
+//#define ICALSW_EN 0x000C
+// #define ICALSW_EN_SHIFT 2
+//#define VSW_A_SEL 0x0030
+// #define VSW_A_SEL_SHIFT 4
+//#define VSW_A_CAL 0x03C0
+// #define VSW_A_CAL_SHIFT 6
+//#define ICALA_EN 0x0C00
+// #define ICALA_EN_SHIFT 10
+//#define ICALTCXO_EN 0x3000
+// #define ICALTCXO_EN_SHIFT 12
+//#define VSW_A_EN 0x4000
+// #define VSW_A_EN_SHIFT 14
+//#define OC_FOLD_EN 0x8000
+// #define OC_FOLD_EN_SHIFT 15
+/* PMIC_CONF: Control and Status of LDO of Vcam_a, Vtcxo, Va */
+#define VCAM_A_STAUS 0x0001
+ #define VCAM_A_STAUS_SHIFT 0
+#define VCAM_A_EN_FORCE 0x0002
+ #define VCAM_A_EN_FORCE_SHIFT 1
+#define ICALCAM_A_EN 0x000C
+ #define ICALCAM_A_EN_SHIFT 2
+#define VCAM_A_SEL 0x0030
+ #define VCAM_A_SEL_SHIFT 4
+#define VCAM_A_CAL 0x03C0
+ #define VCAM_A_CAL_SHIFT 6
+#define ICALA_EN 0x0C00
+ #define ICALA_EN_SHIFT 10
+#define ICALTCXO_EN 0x3000
+ #define ICALTCXO_EN_SHIFT 12
+#define VCAM_A_EN 0x4000
+ #define VCAM_A_EN_SHIFT 14
+#define OC_FOLD_EN 0x8000
+ #define OC_FOLD_EN_SHIFT 15
+/* PMIC_CONG: Start Up & AUXADC Related Control Register 2 */
+#define VREF_BG 0x0007
+ #define VREF_BG_SHIFT 0
+#define THR_SEL 0x0018
+ #define THR_SEL_SHIFT 3
+#define LDO_SOFT_ST 0x0020
+ #define LDO_SOFT_ST_SHIFT 5
+#define TPSEL_LED 0x0F00
+ #define TPSEL_LED_SHIFT 8
+#define ISENSE_OUT_EN 0x1000
+ #define ISENSE_OUT_EN_SHIFT 12
+#define VBAT_OUT_EN 0x2000
+ #define VBAT_OUT_EN_SHIFT 13
+
+#endif /*PMIC_6238_REG_API*/
+
+#endif /* defined(PMIC_6223_REG_API) || defined(PMIC_6238_REG_API) */
+
+
+#endif // #ifndef __DCL_PMIC6235_HW_H_STRUCT__
+
+
+
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6235_sw.h b/mcu/driver/peripheral/inc/dcl_pmu6235_sw.h
new file mode 100644
index 0000000..271fd12
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6235_sw.h
@@ -0,0 +1,621 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6235_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMU6235
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef __DCL_PMU6235_SW_H_STRUCT__
+#define __DCL_PMU6235_SW_H_STRUCT__
+
+
+#if defined(PMIC_6235_REG_API) || defined(PMIC_6238_REG_API)
+
+//workaround till pmu_sw.h is removed
+#if !defined(PMU6235_OLD_STR)
+#define PMU6235_OLD_STR
+
+typedef enum
+{
+ ICAL_RF_1_0=0,
+ ICAL_RF_0_5=1,
+ ICAL_RF_2_0=2,
+ ICAL_RF_3_0=3
+}pmu_icalrf_code;
+
+typedef enum
+{
+ ICAL_CORE_1_0=0,
+ ICAL_CORE_0_5=1,
+ ICAL_CORE_2_0=2,
+ ICAL_CORE_3_0=3
+}pmu_icalcore_code;
+
+typedef enum
+{
+ ICAL_IO_1_0=0,
+ ICAL_IO_0_5=1,
+ ICAL_IO_2_0=2,
+ ICAL_IO_3_0=3
+}pmu_icalio_code;
+
+typedef enum
+{
+ ICAL_M_1_0=0,
+ ICAL_M_0_5=1,
+ ICAL_M_2_0=2,
+ ICAL_M_3_0=3
+}pmu_icalm_code;
+
+typedef enum
+{
+ ICAL_SIM_1_0=0,
+ ICAL_SIM_0_5=1,
+ ICAL_SIM_2_0=2,
+ ICAL_SIM_3_0=3
+}pmu_icalsim_code;
+
+typedef enum
+{
+ VSIM_SEL_1_8=0,
+ VSIM_SEL_3_0
+}pmu_vsim_volt;
+
+
+
+typedef enum
+{
+ CHR_CUR_OFFSET_NONE=0,
+ CHR_CUR_OFFSET_PLUS_1=1,
+ CHR_CUR_OFFSET_PLUS_2=2,
+ CHR_CUR_OFFSET_MINUS_2=6,
+ CHR_CUR_OFFSET_MINUS_1=7
+}pmu_chr_cur_offset;
+
+typedef enum
+{
+ CHR_CUR_50=0,
+ CHR_CUR_87_5=1,
+ CHR_CUR_150=2,
+ CHR_CUR_225=3,
+ CHR_CUR_300=4,
+ CHR_CUR_450=5,
+ CHR_CUR_650=6,
+ CHR_CUR_800=7
+}pmu_chr_cur_level;
+
+
+typedef enum
+{
+ THERMAL_THRES_INIT=0x0000,
+ THERMAL_THRES_PLUS_10C=0x0001,
+ THERMAL_THRES_MINUS_20C=0x0010,
+ THERMAL_THRES_MINUS_10C=0x0011
+}pmu_chr_thermal_thres;
+
+typedef enum
+{
+ VOLT_STEP_INIT=0,
+ VOLT_STEP_MINUS_1=1,
+ VOLT_STEP_MINUS_2=2,
+ VOLT_STEP_MINUS_3=3,
+ VOLT_STEP_PLUS_4=4,
+ VOLT_STEP_PLUS_3=5,
+ VOLT_STEP_PLUS_2=6,
+ VOLT_STEP_PLUS_1=7
+}pmu_ref_volt_step;
+
+typedef enum
+{
+ VBG_VOLT_1_2_V = 0,
+ VBG_VOLT_1_205_V = 1,
+ VBG_VOLT_1_210_V = 2,
+ VBG_VOLT_1_215_V = 3,
+ VBG_VOLT_1_180_V = 4,
+ VBG_VOLT_1_185_V = 5,
+ VBG_VOLT_1_190_V = 6,
+ VBG_VOLT_1_195_V = 7
+}pmu_vbg_volt;
+
+typedef enum
+{
+ GPIO_DRV_8MA = 0,
+ GPIO_DRV_4MA = 1
+}pmu_gpio_drv_strength;
+
+typedef enum
+{
+ UVLO_VOLT_2_9_V=0,
+ UVLO_VOLT_2_75_V=1,
+ UVLO_VOLT_2_6_V=2,
+ UVLO_VOLT_AS_DDLO=3
+}pmu_uvlo_volt;
+
+typedef enum
+{
+ RBGSEL_INIT=0,
+ RBGSEL_PLUS_1_STEP=1,
+ RBGSEL_PLUS_2_STEP=2,
+ RBGSEL_PLUS_3_STEP=3,
+ RBGSEL_MINUS_4_STEP=4,
+ RBGSEL_MINUS_3_STEP=5,
+ RBGSEL_MINUS_2_STEP=6,
+ RBGSEL_MINUS_1_STEP=7
+}pmu_rbgsel;
+
+typedef enum
+{
+ IBGSEL_INIT=0,
+ IBGSEL_PLUS_1_STEP=1,
+ IBGSEL_MINUS_2_STEP=2,
+ IBGSEL_MINUS_1_STEP=3
+}pmu_ibgsel;
+
+typedef enum
+{
+ CK_SEL_10KHZ=0,
+ CK_SEL_5KHZ=1
+}pmu_cksel;
+
+typedef enum
+{
+ VBS_SEL_1200K=0,
+ VBS_SEL_1320K=1,
+ VBS_SEL_960K=2,
+ VBS_SEL_1080K=3
+}pmu_vbssel;
+
+typedef enum
+{
+ OV_HYS_ENB_LOWER=0,
+ OV_HYS_ENB_HIGHER=1
+}pmu_ov_hys_enb;
+
+typedef enum
+{
+ OV_THFREEZE_AUTO=0,
+ OV_THFREEZE_FIXED=1
+}pmu_ov_thfreeze;
+
+typedef enum
+{
+ SDM_1ST_ORDER = 0,
+ SDM_2ND_ORDER = 1
+}pmu_sdm_order;
+
+typedef enum
+{
+ PID_GAIN_P_0_25 = 0,
+ PID_GAIN_P_0_375 = 1,
+ PID_GAIN_P_0_5 = 2,
+ PID_GAIN_P_0_75 = 3,
+ PID_GAIN_P_1 = 4,
+ PID_GAIN_P_1_5 = 5,
+ PID_GAIN_P_2 = 6,
+ PID_GAIN_P_3 = 7
+}pmu_pid_gain_p;
+
+typedef enum
+{
+ PID_GAIN_0_015625 = 0,
+ PID_GAIN_0_0234375 = 1,
+ PID_GAIN_0_03125 = 2,
+ PID_GAIN_0_046875 = 3,
+ PID_GAIN_0_0625 = 4,
+ PID_GAIN_0_09375 = 5,
+ PID_GAIN_0_125 = 6,
+ PID_GAIN_0_1875 = 7
+}pmu_pid_gain;
+
+typedef enum
+{
+ PID_GAIN_D_2 = 0,
+ PID_GAIN_D_3 = 1,
+ PID_GAIN_D_4 = 2,
+ PID_GAIN_D_6 = 3,
+ PID_GAIN_D_8 = 4,
+ PID_GAIN_D_12 = 5,
+ PID_GAIN_D_16 = 6,
+ PID_GAIN_D_24 = 7
+}pmu_pid_gain_d;
+
+typedef enum
+{
+ VCORE_1_8V = 0,
+ VCORE_1_2V = 1
+}pmu_vcore_volt;
+
+typedef enum
+{
+ DCV_INTERNAL = 0,
+ DCV_CLK_TCXO = 1
+}pmu_dcv_ck;
+
+typedef enum
+{
+ ISEL_0_25 = 0,
+ ISEL_1_5 = 1,
+ ISEL_1 = 2,
+ ISEL_2 = 3
+}pmu_isel;
+
+typedef enum
+{
+ MODE_SET_PWM = 0,
+ MODE_SET_PFM = 1
+}pmu_mode_set;
+
+typedef enum
+{
+ MODE_CMP_LOW_OFFSET = 0,
+ MODE_CMP_AUTO_ZERO = 1
+}pmu_mode_cmp;
+
+typedef enum
+{
+ MODE_NDC = 0,
+ MODE_AVE_CURRENT = 1
+}pmu_mode_ave_current;
+
+#endif //#if !defined(PMU6235_OLD_STR)
+
+/* PFM max load current select. Can OR together. */
+#define PFM_MAX_160_MA_EN 0x08
+#define PFM_MAX_80_MA_EN 0x04
+#define PFM_MAX_40_MA_EN 0x02
+#define PFM_MAX_20_MA_EN 0x01
+
+/* PFM max load resistor select. Can OR together*/
+#define PFM_RESISTOR_50_OHM 0x04
+#define PFM_RESISTOR_100_OHM 0x02
+#define PFM_RESISTOR_200_OHM 0x01
+
+typedef enum
+{
+ NDC_OFFSET_MINUS_3mV = 0,
+ NDC_OFFSET_5mV = 1,
+ NDC_OFFSET_12mV = 2,
+ NDC_OFFSET_17mV = 3
+}pmu_ndc_offset;
+
+typedef enum
+{
+ IASEL_50mV = 0,
+ IASEL_100mV = 1,
+ IASEL_150mV = 2,
+ IASEL_200mV = 3
+}pmu_iasel;
+
+typedef enum
+{
+ RSEL_32k = 0,
+ RSEL_28k = 1,
+ RSEL_24k = 2,
+ RSEL_18k = 3
+}pmu_rsel;
+
+typedef enum
+{
+ ICAL_USB_1_0=0,
+ ICAL_USB_0_5=1,
+ ICAL_USB_2_0=2,
+ ICAL_USB_3_0=3
+}pmu_icalusb_code;
+
+typedef enum
+{
+ CLK_SRC_FROM_CLKSQ=0,
+ CLK_SRC_FROM_TCXO26M_CK=1
+}pmu_clk_src_sel;
+
+typedef enum
+{
+ VTCXO_LDO_WITH_VTCXO_EN=0,
+ VTCXO_LDO_WITH_RG_VTCXO_EN=1
+}pmu_vtcxo_on_sel;
+
+typedef enum
+{
+ ICAL_SIM2_1_0=0,
+ ICAL_SIM2_0_5=1,
+ ICAL_SIM2_2_0=2,
+ ICAL_SIM2_3_0=3
+}pmu_icalsim2_code;
+
+//typedef enum
+//{
+// ICAL_MC_1_0=0,
+// ICAL_MC_0_5=1,
+// ICAL_MC_2_0=2,
+// ICAL_MC_3_0=3
+//}pmu_icalmc_code;
+// vmc related items are changed as vbt
+typedef enum
+{
+ ICAL_BT_1_0=0,
+ ICAL_BT_0_5=1,
+ ICAL_BT_2_0=2,
+ ICAL_BT_3_0=3
+}pmu_icalbt_code;
+
+//typedef enum
+//{
+// VMC_SEL_1_8=0,
+// VMC_SEL_3_0
+//}pmu_vmc_volt;
+// vmc related items are changed as vbt
+typedef enum
+{
+ VBT_SEL_2_8=0,
+ VBT_SEL_3_0
+}pmu_vbt_volt;
+
+//typedef enum
+//{
+// ICAL_CAMERA_1_0=0,
+// ICAL_CAMERA_0_5=1,
+// ICAL_CAMERA_2_0=2,
+// ICAL_CAMERA_3_0=3
+//}pmu_icalcamera_code;
+// vcamera ==> vcam_d
+typedef enum
+{
+ ICAL_CAM_D_1_0=0,
+ ICAL_CAM_D_0_5=1,
+ ICAL_CAM_D_2_0=2,
+ ICAL_CAM_D_3_0=3
+}pmu_icalcam_d_code;
+
+//typedef enum
+//{
+// VCAMERA_SEL_1_3=0,
+// VCAMERA_SEL_1_5=1,
+// VCAMERA_SEL_1_8=2,
+// VCAMERA_SEL_2_8=3
+//}pmu_vcamera_volt;
+// vcamera ==> vcam_d
+typedef enum
+{
+ VCAM_D_SEL_1_3=0,
+ VCAM_D_SEL_1_5=1,
+ VCAM_D_SEL_1_8=2,
+ VCAM_D_SEL_2_8=3
+}pmu_vcam_d_volt;
+
+//typedef enum
+//{
+// ICAL_SW_1_0=0,
+// ICAL_SW_0_5=1,
+// ICAL_SW_2_0=2,
+// ICAL_SW_3_0=3
+//}pmu_icalsw_code;
+typedef enum
+{
+ ICAL_CAM_A_1_0=0,
+ ICAL_CAM_A_0_5=1,
+ ICAL_CAM_A_2_0=2,
+ ICAL_CAM_A_3_0=3
+}pmu_icalcam_a_code;
+
+//typedef enum
+//{
+// VSW_A_SEL_1_3=0,
+// VSW_A_SEL_1_5=1,
+// VSW_A_SEL_1_8=2,
+// VSW_A_SEL_2_8=3
+//}pmu_vsw_a_volt;
+typedef enum
+{
+ VCAM_A_SEL_1_3=0,
+ VCAM_A_SEL_1_5=1,
+ VCAM_A_SEL_1_8=2,
+ VCAM_A_SEL_2_8=3
+}pmu_vcam_a_volt;
+
+typedef enum
+{
+ ICAL_A_1_0=0,
+ ICAL_A_0_5=1,
+ ICAL_A_2_0=2,
+ ICAL_A_3_0=3
+}pmu_icala_code;
+
+typedef enum
+{
+ ICAL_TCXO_1_0=0,
+ ICAL_TCXO_0_5=1,
+ ICAL_TCXO_2_0=2,
+ ICAL_TCXO_3_0=3
+}pmu_icaltcxo_code;
+
+typedef enum
+{
+ VREF_BG_INIT=0,
+ VREF_BG_PLUS_1_STEP=1,
+ VREF_BG_PLUS_2_STEP=2,
+ VREF_BG_PLUS_3_STEP=3,
+ VREF_BG_MINUS_4_STEP=4,
+ VREF_BG_MINUS_3_STEP=5,
+ VREF_BG_MINUS_2_STEP=6,
+ VREF_BG_MINUS_1_STEP=7
+}pmu_vref_bg;
+
+typedef enum
+{
+ THR_SEL_INIT=0,
+ THR_SEL_PLUS_10C=1,
+ THR_SEL_MINUS_20C=2,
+ THR_SEL_MINUS_10C=3
+}pmu_thr_sel;
+
+#define PMU_ADC_VISENSE_CH_NUM 4
+#define PMU_ADC_VBAT_CH_NUM 5
+#define PMU_ADC_VCHARGER_CH_NUM 6
+
+#define PMU_ADC_FACTOR_VBAT 100
+#define PMU_ADC_FACTOR_VISENSE 100
+#define PMU_ADC_FACTOR_VCHARGER 250
+
+#define PMU_BMT_CV_TARGET_VOLTAGE PMU_VOLT_04_200000_V
+
+#if defined(PMIC_FIXED_CHR_EINT)
+#define PMU_CHR_EINT_PIN 8
+#endif // #if defined(PMIC_FIXED_CHR_EINT)
+
+/*
+typedef enum
+{
+ VCORE,
+ VIO,
+ VRF,
+ VA,
+ VRTC,
+ VM,
+ VSIM,
+ VTCXO,
+ VSIM2,
+ VUSB,
+ VBT,
+ VCAMA,
+ VCAMD,
+ PMU_LDO_BUCK_MAX,
+ VMC,
+ VIBR,
+ VRF18,
+ VFM
+}PMU_LDO_BUCK_LIST_ENUM;
+
+typedef enum
+{
+ VPA1,
+ PMU_VPA_MAX
+}PMU_VPA_LIST_ENUM;
+
+
+typedef enum
+{
+ KPLED,
+ PMU_KPLED_MAX
+}PMU_KPLED_LIST_ENUM;
+
+typedef enum
+{
+ CHR,
+ PMU_CHR_MAX
+}PMU_CHR_LIST_ENUM;
+
+typedef enum
+{
+ PMU_ISINK_MAX
+}PMU_ISINK_LIST_ENUM;
+
+typedef enum
+{
+ PMU_BOOST_MAX
+}PMU_BOOST_LIST_ENUM;
+
+typedef enum
+{
+ PMU_SPK_MAX
+}PMU_SPK_LIST_ENUM;
+*/
+
+#endif //#if defined(PMIC_6235_REG_API)
+#endif //#ifndef __DCL_PMU6255_SW_H_STRUCT__
+
+
+
+
+
+
+
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6236_hw.h b/mcu/driver/peripheral/inc/dcl_pmu6236_hw.h
new file mode 100644
index 0000000..a16ebee
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6236_hw.h
@@ -0,0 +1,808 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6236_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMU6236
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef __DCL_PMIC6236_HW_H_STRUCT__
+#define __DCL_PMIC6236_HW_H_STRUCT__
+
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6236_REG_API)
+
+#define PMU_BASE MIXED_base
+#define PMU_END (PMU_BASE+0x1000)
+
+// =====================================================================================
+
+#define PMIC_LDO_BASE0 (PMU_BASE+0x800)
+#define PMIC_LDO_BASE1 (PMU_BASE+0x804)
+
+#define PMIC_VRF_CON0 (PMU_BASE+0x800)
+#define PMIC_VRF_CON1 (PMU_BASE+0x804)
+#define PMIC_VRF_CON2 (PMU_BASE+0x808)
+#define PMIC_VRF_CON3 (PMU_BASE+0x80C)
+
+#define PMIC_VTCXO_CON0 (PMU_BASE+0x810)
+#define PMIC_VTCXO_CON1 (PMU_BASE+0x814)
+#define PMIC_VTCXO_CON2 (PMU_BASE+0x818)
+
+#define PMIC_VA_CON0 (PMU_BASE+0x820)
+#define PMIC_VA_CON1 (PMU_BASE+0x824)
+#define PMIC_VA_CON2 (PMU_BASE+0x828)
+
+#define PMIC_VCAMA_CON0 (PMU_BASE+0x830)
+#define PMIC_VCAMA_CON1 (PMU_BASE+0x834)
+#define PMIC_VCAMA_CON2 (PMU_BASE+0x838)
+
+#define PMIC_VCAMD_CON0 (PMU_BASE+0x840)
+#define PMIC_VCAMD_CON1 (PMU_BASE+0x844)
+#define PMIC_VCAMD_CON2 (PMU_BASE+0x848)
+
+#define PMIC_VIO_CON0 (PMU_BASE+0x850)
+#define PMIC_VIO_CON1 (PMU_BASE+0x854)
+#define PMIC_VIO_CON2 (PMU_BASE+0x858)
+
+#define PMIC_VUSB_CON0 (PMU_BASE+0x860)
+#define PMIC_VUSB_CON1 (PMU_BASE+0x864)
+#define PMIC_VUSB_CON2 (PMU_BASE+0x868)
+
+#define PMIC_VBT_CON0 (PMU_BASE+0x870)
+#define PMIC_VBT_CON1 (PMU_BASE+0x874)
+#define PMIC_VBT_CON2 (PMU_BASE+0x878)
+
+#define PMIC_VSIM_CON0 (PMU_BASE+0x880)
+#define PMIC_VSIM_CON1 (PMU_BASE+0x884)
+#define PMIC_VSIM_CON2 (PMU_BASE+0x888)
+#define PMIC_VSIM_CON3 (PMU_BASE+0x88C)
+
+#define PMIC_VSIM2_CON0 (PMU_BASE+0x890)
+#define PMIC_VSIM2_CON1 (PMU_BASE+0x894)
+#define PMIC_VSIM2_CON2 (PMU_BASE+0x898)
+#define PMIC_VSIM2_CON3 (PMU_BASE+0x89C)
+
+#define PMIC_VBACKUP_CON0 (PMU_BASE+0x8A0)
+#define PMIC_VBACKUP_CON1 (PMU_BASE+0x8A4)
+#define PMIC_VBACKUP_CON2 (PMU_BASE+0x8A8)
+
+#define PMIC_VBIR_CON0 (PMU_BASE+0x8B0)
+#define PMIC_VBIR_CON1 (PMU_BASE+0x8B4)
+#define PMIC_VBIR_CON2 (PMU_BASE+0x8B8)
+
+#define PMIC_VMC_CON0 (PMU_BASE+0x8C0)
+#define PMIC_VMC_CON1 (PMU_BASE+0x8C4)
+#define PMIC_VMC_CON2 (PMU_BASE+0x8C8)
+
+#define PMIC_VCORE_CON0 (PMU_BASE+0x900)
+#define PMIC_VCORE_CON1 (PMU_BASE+0x904)
+#define PMIC_VCORE_CON2 (PMU_BASE+0x908)
+#define PMIC_VCORE_CON3 (PMU_BASE+0x90C)
+#define PMIC_VCORE_CON4 (PMU_BASE+0x910)
+#define PMIC_VCORE_CON5 (PMU_BASE+0x914)
+#define PMIC_VCORE_CON6 (PMU_BASE+0x918)
+
+#define PMIC_VM_CON0 (PMU_BASE+0x920)
+#define PMIC_VM_CON1 (PMU_BASE+0x924)
+#define PMIC_VM_CON2 (PMU_BASE+0x928)
+#define PMIC_VM_CON3 (PMU_BASE+0x92C)
+#define PMIC_VM_CON4 (PMU_BASE+0x930)
+#define PMIC_VM_CON5 (PMU_BASE+0x934)
+#define PMIC_VM_CON6 (PMU_BASE+0x938)
+
+
+#define PMIC_BOOST_CON0 (PMU_BASE+0xB00)
+#define PMIC_BOOST_CON1 (PMU_BASE+0xB04)
+#define PMIC_BOOST_CON2 (PMU_BASE+0xB08)
+#define PMIC_BOOST_CON3 (PMU_BASE+0xB0C)
+
+#define PMIC_BL_CON0 (PMU_BASE+0xB80)
+#define PMIC_BL_CON1 (PMU_BASE+0xB84)
+
+
+#define PMIC_CHR_CON0 (PMU_BASE+0xA00)
+#define PMIC_CHR_CON1 (PMU_BASE+0xA04)
+#define PMIC_CHR_CON2 (PMU_BASE+0xA08)
+#define PMIC_CHR_CON3 (PMU_BASE+0xA0C)
+#define PMIC_CHR_CON4 (PMU_BASE+0xA10)
+#define PMIC_CHR_CON5 (PMU_BASE+0xA14)
+#define PMIC_CHR_CON6 (PMU_BASE+0xA18)
+#define PMIC_CHR_CON7 (PMU_BASE+0xA1C)
+#define PMIC_CHR_CON8 (PMU_BASE+0xA20)
+#define PMIC_CHR_CON9 (PMU_BASE+0xA24)
+
+#define PMIC_STRUP_CON0 (PMU_BASE+0xA80)
+#define PMIC_STRUP_CON1 (PMU_BASE+0xA84)
+
+#define PMIC_ISINK0_CON0 (PMU_BASE+0xC00)
+#define PMIC_ISINK0_CON1 (PMU_BASE+0xC04)
+
+#define PMIC_ISINK1_CON0 (PMU_BASE+0xC10)
+#define PMIC_ISINK2_CON0 (PMU_BASE+0xC20)
+#define PMIC_ISINK3_CON0 (PMU_BASE+0xC30)
+#define PMIC_ISINK4_CON0 (PMU_BASE+0xC40)
+
+#define PMIC_KPLED_CON0 (PMU_BASE+0xC80)
+#define PMIC_KPLED_CON1 (PMU_BASE+0xC84)
+
+#define PMIC_FLASH_CON0 (PMU_BASE+0xC90)
+#define PMIC_FLASH_CON1 (PMU_BASE+0xC94)
+
+
+#define PMIC_SPK_CON0 (PMU_BASE+0xD00)
+#define PMIC_SPK_CON1 (PMU_BASE+0xD04)
+#define PMIC_SPK_CON2 (PMU_BASE+0xD08)
+#define PMIC_SPK_CON3 (PMU_BASE+0xD0C)
+
+
+#define PMIC_TEST_CON0 (PMU_BASE+0xF00)
+#define PMIC_TEST_CON1 (PMU_BASE+0xF04)
+
+#define PMIC_OC_CON0 (PMU_BASE+0xE00)
+#define PMIC_OC_CON1 (PMU_BASE+0xE04)
+#define PMIC_OC_CON2 (PMU_BASE+0xE08)
+#define PMIC_OC_CON3 (PMU_BASE+0xE0C)
+#define PMIC_OC_CON4 (PMU_BASE+0xE10)
+#define PMIC_OC_CON5 (PMU_BASE+0xE14)
+#define PMIC_OC_CON6 (PMU_BASE+0xE18)
+#define PMIC_OC_CON7 (PMU_BASE+0xE1C)
+
+
+#define LDO_EN_MASK 0x0001
+#define LD0_EN_SHIFT 0
+#define LDO_ON_SEL_MASK 0x0002
+#define LDO_ON_SEL_SHIFT 1
+#define LDO_SENSE_MASK 0x0004
+#define LDO_SENSE_SHIFT 2
+#define LDO_OCFB_EN_MASK 0x2000
+#define LDO_OCFB_EN_SHIFT 13
+#define LDO_STATUS_MASK 0x8000
+#define LDO_STATUS_SHIFT 15
+
+#define LDO_CAL_MASK 0x00F0
+#define LDO_CAL_SHIFT 4
+
+
+// =====================================================================================
+// (0x800) VRF_CON0
+#define VRF_EN_MASK 0x0001
+#define VRF_EN_SHIFT 0
+#define VRF_ON_SEL_MASK 0x0002
+#define VRF_ON_SEL_SHIFT 1
+#define VRF_REMOTE_SENSE_MASK 0x0004
+#define VRF_REMOTE_SENSE_SHIFT 2
+#define VRF_NDIS_EN_MASK 0x0400
+#define VRF_NDIS_EN_SHIFT 10
+#define VRF_STB_EN_MASK 0x0800
+#define VRF_STB_EN_SHIFT 11
+#define VRF_OC_AUTO_OFF_MASK 0x1000
+#define VRF_OC_AUTO_OFF_SHIFT 12
+#define VRF_OCFB_EN_MASK 0x2000
+#define VRF_OCFB_EN_SHIFT 13
+#define VRF_STATUS_MASK 0x8000
+#define VRF_STATUS_SHIFT 15
+
+// (0x804) VRF_CON1
+#define VRF_CAL_MASK 0x00F0
+#define VRF_CAL_SHIFT 4
+
+// (0x810) VTCXO_CON0
+#define VTCXO_EN_MASK 0x0001
+#define VTCXO_EN_SHIFT 0
+#define VTCXO_ON_SEL_MASK 0x0002
+#define VTCXO_ON_SEL_SHIFT 1
+#define VTCXO_REMOTE_SENSE_MASK 0x0004
+#define VTCXO_REMOTE_SENSE_SHIFT 2
+#define VTCXO_NDIS_EN_MASK 0x0400
+#define VTCXO_NDIS_EN_SHIFT 10
+#define VTCXO_STB_EN_MASK 0x0800
+#define VTCXO_STB_EN_SHIFT 11
+#define VTCXO_OC_AUTO_OFF_MASK 0x1000
+#define VTCXO_OC_AUTO_OFF_SHIFT 12
+#define VTCXO_OCFB_EN_MASK 0x2000
+#define VTCXO_OCFB_EN_SHIFT 13
+#define VTCXO_STATUS_MASK 0x8000
+#define VTCXO_STATUS_SHIFT 15
+
+// (0x814) VTCXO_CON1
+#define VTCXO_CAL_MASK 0x00F0
+#define VTCXO_CAL_SHIFT 4
+
+// (0x820) VA_CON0
+#define VA_REMOTE_SENSE_MASK 0x0004
+#define VA_REMOTE_SENSE_SHIFT 2
+#define VA_NDIS_EN_MASK 0x0400
+#define VA_NDIS_EN_SHIFT 10
+#define VA_STB_EN_MASK 0x0800
+#define VA_STB_EN_SHIFT 11
+#define VA_OC_AUTO_OFF_MASK 0x1000
+#define VA_OC_AUTO_OFF_SHIFT 12
+#define VA_OCFB_EN_MASK 0x2000
+#define VA_OCFB_EN_SHIFT 13
+#define VA_STATUS_MASK 0x8000
+#define VA_STATUS_SHIFT 15
+
+// (0x824) VA_CON1
+#define VA_CAL_MASK 0x00F0
+#define VA_CAL_SHIFT 4
+
+// (0x830) VCAMA_CON0
+#define VCAMA_EN_MASK 0x0001
+#define VCAMA_EN_SHIFT 0
+#define VCAMA_ON_SEL_MASK 0x0002
+#define VCAMA_ON_SEL_SHIFT 1
+#define VCAMA_VOSEL_MASK 0x0030
+#define VCAMA_VOSEL_SHIFT 4
+#define VCAMA_NDIS_EN_MASK 0x0400
+#define VCAMA_NDIS_EN_SHIFT 10
+#define VCAMA_STB_EN_MASK 0x0800
+#define VCAMA_STB_EN_SHIFT 11
+#define VCAMA_OC_AUTO_OFF_MASK 0x1000
+#define VCAMA_OC_AUTO_OFF_SHIFT 12
+#define VCAMA_OCFB_EN_MASK 0x2000
+#define VCAMA_OCFB_EN_SHIFT 13
+#define VCAMA_STATUS_MASK 0x8000
+#define VCAMA_STATUS_SHIFT 15
+
+// (0x834) VCAMA_CON1
+#define VCAMA_CAL_MASK 0x00F0
+#define VCAMA_CAL_SHIFT 4
+
+// (0x838) VCAMA_CON2
+#define VCAMA_OC_TD_MASK 0x0030
+#define VCAMA_OC_TD_SHIFT 4
+#define VCAMA_STB_TD_MASK 0x00C0
+#define VCAMA_STB_TD_SHIFT 6
+
+// (0x840) VCAMD_CON0
+#define VCAMD_EN_MASK 0x0001
+#define VCAMD_EN_SHIFT 0
+#define VCAMD_ON_SEL_MASK 0x0002
+#define VCAMD_ON_SEL_SHIFT 1
+#define VCAMD_VOSEL_MASK 0x0070
+#define VCAMD_VOSEL_SHIFT 4
+#define VCAMD_NDIS_EN_MASK 0x0400
+#define VCAMD_NDIS_EN_SHIFT 10
+#define VCAMD_STB_EN_MASK 0x0800
+#define VCAMD_STB_EN_SHIFT 11
+#define VCAMD_OC_AUTO_OFF_MASK 0x1000
+#define VCAMD_OC_AUTO_OFF_SHIFT 12
+#define VCAMD_OCFB_EN_MASK 0x2000
+#define VCAMD_OCFB_EN_SHIFT 13
+#define VCAMD_STATUS_MASK 0x8000
+#define VCAMD_STATUS_SHIFT 15
+
+// (0x844) VCAMD CON1
+#define VCAMD_CAL_MASK 0x00F0
+#define VCAMD_CAL_SHIFT 4
+
+// (0x850) VIO_CON0
+#define VIO_REMOTE_SENSE_MASK 0x0004
+#define VIO_REMOTE_SENSE_SHIFT 2
+#define VIO_OC_AUTO_OFF_MASK 0x1000
+#define VIO_NDIS_EN_MASK 0x0400
+#define VIO_NDIS_EN_SHIFT 10
+#define VIO_STB_EN_MASK 0x0800
+#define VIO_STB_EN_SHIFT 11
+#define VIO_OC_AUTO_OFF_SHIFT 12
+#define VIO_OCFB_EN_MASK 0x2000
+#define VIO_OCFB_EN_SHIFT 13
+#define VIO_STATUS_MASK 0x8000
+#define VIO_STATUS_SHIFT 15
+
+// (0x854) VIO_CON1
+#define VIO_CAL_MASK 0x00F0
+#define VIO_CAL_SHIFT 4
+
+// (0x858) VIO_CON2
+#define VIO_OC_TD_MASK 0x0030
+#define VIO_OC_TD_SHIFT 4
+
+// (0x860) VUSB_CON0
+#define VUSB_EN_MASK 0x0001
+#define VUSB_EN_SHIFT 0
+#define VUSB_NDIS_EN_MASK 0x0400
+#define VUSB_NDIS_EN_SHIFT 10
+#define VUSB_STB_EN_MASK 0x0800
+#define VUSB_STB_EN_SHIFT 11
+#define VUSB_OC_AUTO_OFF_MASK 0x1000
+#define VUSB_OC_AUTO_OFF_SHIFT 12
+#define VUSB_OCFB_EN_MASK 0x2000
+#define VUSB_OCFB_EN_SHIFT 13
+#define VUSB_STATUS_MASK 0x8000
+#define VUSB_STATUS_SHIFT 15
+
+// (0x864) VUSB_CON1
+#define VUSB_CAL_MASK 0x00F0
+#define VUSB_CAL_SHIFT 4
+
+// (0x868) VUSB_CON2
+#define VUSB_OC_TD_MASK 0x0030
+#define VUSB_OC_TD_SHIFT 4
+#define VUSB_STB_TD_MASK 0x00C0
+#define VUSB_STB_TD_SHIFT 6
+
+// (0x870) VBT CON0
+#define VBT_EN_MASK 0x0001
+#define VBT_EN_SHIFT 0
+#define VBT_VOSEL_MASK 0x0010
+#define VBT_VOSEL_SHIFT 4
+#define VBT_NDIS_EN_MASK 0x0400
+#define VBT_NDIS_EN_SHIFT 10
+#define VBT_STB_EN_MASK 0x0800
+#define VBT_STB_EN_SHIFT 11
+#define VBT_OC_AUTO_OFF_MASK 0x1000
+#define VBT_OC_AUTO_OFF_SHIFT 12
+#define VBT_OCFB_EN_MASK 0x2000
+#define VBT_OCFB_EN_SHIFT 13
+#define VBT_STATUS_MASK 0x8000
+#define VBT_STATUS_SHIFT 15
+
+// (0x874) VBT CON1
+#define VBT_CAL_MASK 0x00F0
+#define VBT_CAL_SHIFT 4
+
+// (0x878) VBT CON2
+#define VBT_OC_TD_MASK 0x0030
+#define VBT_OC_TD_SHIFT 4
+#define VBT_STB_TD_MASK 0x00C0
+#define VBT_STB_TD_SHIFT 6
+
+// (0x880) VSIM CON0
+#define VSIM_EN_MASK 0x0001
+#define VSIM_EN_SHIFT 0
+#define VSIM_VOSEL_MASK 0x0010
+#define VSIM_VOSEL_SHIFT 4
+#define VSIM_NDIS_EN_MASK 0x0400
+#define VSIM_NDIS_EN_SHIFT 10
+#define VSIM_STB_EN_MASK 0x0800
+#define VSIM_STB_EN_SHIFT 11
+#define VSIM_OC_AUTO_OFF_MASK 0x1000
+#define VSIM_OC_AUTO_OFF_SHIFT 12
+#define VSIM_OCFB_EN_MASK 0x2000
+#define VSIM_OCFB_EN_SHIFT 13
+#define VSIM_STATUS_MASK 0x8000
+#define VSIM_STATUS_SHIFT 15
+
+// (0x884) VSIM_CON1
+#define VSIM_CAL_MASK 0x00F0
+#define VSIM_CAL_SHIFT 4
+
+// (0x888) VSIM_CON2
+#define VSIM_OC_TD_MASK 0x0030
+#define VSIM_OC_TD_SHIFT 4
+
+// (0x890) VSIM2 CON0
+#define VSIM2_EN_MASK 0x0001
+#define VSIM2_EN_SHIFT 0
+#define VSIM2_VOSEL_MASK 0x0070
+#define VSIM2_VOSEL_SHIFT 4
+#define VSIM2_NDIS_EN_MASK 0x0400
+#define VSIM2_NDIS_EN_SHIFT 10
+#define VSIM2_STB_EN_MASK 0x0800
+#define VSIM2_STB_EN_SHIFT 11
+#define VSIM2_OC_AUTO_OFF_MASK 0x1000
+#define VSIM2_OC_AUTO_OFF_SHIFT 12
+#define VSIM2_OCFB_EN_MASK 0x2000
+#define VSIM2_OCFB_EN_SHIFT 13
+#define VSIM2_STATUS_MASK 0x8000
+#define VSIM2_STATUS_SHIFT 15
+
+// (0x894) VSIM2_CON1
+#define VSIM2_CAL_MASK 0x00F0
+#define VSIM2_CAL_SHIFT 4
+
+// (0x898) VSIM2_CON2
+#define VSIM2_GPLDO_EN_MASK 0x0002
+#define VSIM2_GPLDO_EN_SHIFT 1
+
+
+// (0x8A0) VBACKUP_CON0
+#define VBACKUP_EN_MASK 0x0001
+#define VBACKUP_EN_SHIFT 0
+#define VBACKUP_NDIS_EN_MASK 0x0400
+#define VBACKUP_NDIS_EN_SHIFT 10
+#define VBACKUP_STB_EN_MASK 0x0800
+#define VBACKUP_STB_EN_SHIFT 11
+#define VBACKUP_OC_AUTO_OFF_MASK 0x1000
+#define VBACKUP_OC_AUTO_OFF_SHIFT 12
+#define VBACKUP_OCFB_EN_MASK 0x2000
+#define VBACKUP_OCFB_EN_SHIFT 13
+#define VBACKUP_STATUS_MASK 0x8000
+#define VBACKUP_STATUS_SHIFT 15
+
+// (0x8B0) Vibr_CON0
+#define VIBR_EN_MASK 0x0001
+#define VIBR_EN_SHIFT 0
+#define VIBR_VOSEL_MASK 0x0070
+#define VIBR_VOSEL_SHIFT 4
+#define VIBR_NDIS_EN_MASK 0x0400
+#define VIBR_NDIS_EN_SHIFT 10
+#define VIBR_STB_EN_MASK 0x0800
+#define VIBR_STB_EN_SHIFT 11
+#define VIBR_OC_AUTO_OFF_MASK 0x1000
+#define VIBR_OC_AUTO_OFF_SHIFT 12
+#define VIBR_OCFB_EN_MASK 0x2000
+#define VIBR_OCFB_EN_SHIFT 13
+#define VIBR_STATUS_MASK 0x8000
+#define VIBR_STATUS_SHIFT 15
+
+// (0x8B4) VIBR_CON1
+#define VIBR_CAL_MASK 0x00F0
+#define VIBR_CAL_SHIFT 4
+
+// (0x8C0) VMC_CON0
+#define VMC_EN_MASK 0x0001
+#define VMC_EN_SHIFT 0
+#define VMC_VOSEL_MASK 0x0070
+#define VMC_VOSEL_SHIFT 4
+#define VMC_NDIS_EN_MASK 0x0400
+#define VMC_NDIS_EN_SHIFT 10
+#define VMC_STB_EN_MASK 0x0800
+#define VMC_STB_EN_SHIFT 11
+#define VMC_OC_AUTO_OFF_MASK 0x1000
+#define VMC_OC_AUTO_OFF_SHIFT 12
+#define VMC_OCFB_EN_MASK 0x2000
+#define VMC_OCFB_EN_SHIFT 13
+#define VMC_STATUS_MASK 0x8000
+#define VMC_STATUS_SHIFT 15
+
+// (0x08C4) VMC_CON1
+#define VMC_CAL_MASK 0x00F0
+#define VMC_CAL_SHIFT 4
+
+// (0x900) VCORE_CON0
+#define VCORE_EN_MASK 0x0001
+#define VCORE_EN_SHIFT 0
+#define VCORE_REMOTE_SENSE_MASK 0x0004
+#define VCORE_REMOTE_SENSE_SHIFT 2
+#define VCORE_VFBADJ_MASK 0x01F0
+#define VCORE_VFBADJ_SHIFT 4
+#define VCORE_STB_EN_MASK 0x0800
+#define VCORE_STB_EN_SHIFT 11
+#define VCORE_OC_AUTO_OFF_MASK 0x1000
+#define VCORE_OC_AUTO_OFF_SHIFT 12
+#define VCORE_OCFB_EN_MASK 0x2000
+#define VCORE_OCFB_EN_SHIFT 13
+#define VCORE_STATUS_MASK 0x8000
+#define VCORE_STATUS_SHIFT 15
+
+// (0x904) VCORE_CON1
+#define VCORE_MODE_SET_MASK 0x0001
+#define VCORE_MODE_SET_SHIFT 0
+#define VCORE_VFBADJ_SLEEP_MASK 0x01F0
+#define VCORE_VFBADJ_SLEEP_SHIFT 4
+#define VCORE_CPMCKSEL_MASK 0x0400
+#define VCORE_CPMCKSEL_SHIFT 10
+
+// (0x908) VCORE_CON2
+#define VCORE_VOSEL_MASK 0x0007
+#define VCORE_VOSEL_SHIFT 0
+#define VCORE_CAL_MASK 0x00F0
+#define VCORE_CAL_SHIFT 4
+
+// (0x90C) VCORE_CON3
+#define VCORE_ICAL_EN_MASK 0x3000
+#define VCORE_ICAL_EN_SHIFT 12
+
+// (0x914) VCORE_CON5
+#define VCORE_CSL_MASK 0x0700
+#define VCORE_CSL_SHIFT 8
+#define VCORE_BURST_MASK 0x3000
+#define VCORE_BURST_SHIFT 12
+
+// (0x920) VM_CON0
+#define VM_REMOTE_SENSE_MASK 0x0004
+#define VM_REMOTE_SENSE_SHIFT 2
+#define VM_STB_EN_MASK 0x0800
+#define VM_STB_EN_SHIFT 11
+#define VM_OC_AUTO_OFF_MASK 0x1000
+#define VM_OC_AUTO_OFF_SHIFT 12
+#define VM_OCFB_EN_MASK 0x2000
+#define VM_OCFB_EN_SHIFT 13
+#define VM_STATUS_MASK 0x8000
+#define VM_STATUS_SHIFT 15
+
+// (0x928) VM_CON2
+#define VM_CAL_MASK 0x00F0
+#define VM_CAL_SHIFT 4
+
+// (0x92C) VM_CON3
+#define VM_ICAL_EN_MASK 0x3000
+#define VM_ICAL_EN_SHIFT 12
+
+// (0x92C) VM_CON5
+#define VM_CSL_MASK 0x0700
+#define VM_CSL_SHIFT 8
+#define VM_BURST_MASK 0x3000
+#define VM_BURST_SHIFT 12
+
+// (0xA00) CHR_CON0
+#define VCDT_LV_VTH_MASK 0x000F
+#define VCDT_LV_VTH_SHIFT 0
+#define VCDT_HV_VTH_MASK 0x00F0
+#define VCDT_HV_VTH_SHIFT 4
+#define VCDT_HV_EN_MASK 0x0100
+#define VCDT_HV_EN_SHIFT 8
+#define CSDAC_EN_MASK 0x0800
+#define CSDAC_EN_SHIFT 11
+#define CHR_EN_MASK 0x1000
+#define CHR_EN_SHIFT 12
+#define CHRDET_MASK 0x2000
+#define CHRDET_SHIFT 13
+#define VCDT_HV_DET_MASK 0x8000
+#define VCDT_HV_DET_SHIFT 15
+
+// (0xA04) CHR_CON1
+#define VBAT_CV_VTH_MASK 0x001F
+#define VBAT_CV_VTH_SHIFT 0
+#define VBAT_CC_VTH_MASK 0x00C0
+#define VBAT_CC_VTH_SHIFT 6
+#define VBAT_CV_EN_MASK 0x0100
+#define VBAT_CV_EN_SHIFT 8
+#define VBAT_CC_EN_MASK 0x0200
+#define VBAT_CC_EN_SHIFT 9
+#define VBAT_CV_DET_MASK 0x4000
+#define VBAT_CV_DET_SHIFT 14
+#define VBAT_CC_DET_MASK 0x8000
+#define VBAT_CC_DET_SHIFT 15
+
+// (0xA08) CHR_CON2
+#define CS_EN_MASK 0x1000
+#define CS_EN_SHIFT 12
+#define CS_VTH_MASK 0x0700
+#define CS_VTH_SHIFT 8
+
+// (0xA0C) CHR_CON3
+#define CSDAC_DLY_MASK 0x30
+#define CSDAC_DLY_SHIFT 4
+#define CSDAC_STP_MASK 0x3
+#define CSDAC_STP_SHIFT 0
+
+// (0xA14) CHR_CON5
+#define PCHR_FLAG_SEL_MASK 0x000F
+#define PCHR_FLAG_SEL_SHIFT 0
+#define PCHR_FLAG_EN_MASK 0x0080
+#define PCHR_FLAG_EN_SHIFT 7
+#define PCHR_FLAG_OUT_MASK 0x0F00
+#define PCHR_FLAG_OUT_SHIFT 8
+ // PCHR command result (The value is filled into PCHR_FLAG_OUT)
+ #define PCHR_STATE_MASK 0x7
+ #define PCHR_STATE_SHIFT 0
+
+
+// (0xA18) CHR_CON6
+#define CHRWDT_TD_MASK 0x0007
+#define CHRWDT_TD_SHIFT 0
+#define CHRWDT_EN_MASK 0x0010
+#define CHRWDT_EN_SHIFT 4
+
+// (0xA1C) CHR_CON7
+#define CHRWDT_INT_EN_MASK 0x0001
+#define CHRWDT_INT_EN_SHIFT 0
+#define CHRWDT_FLAG_MASK 0x0002
+#define CHRWDT_FLAG_SHIFT 1
+
+// (0xA20) CHR_CON8
+#define ADCIN_VBAT_EN 0x1000
+#define ADCIN_VBAT_EN_SHIFT 12
+#define ADCIN_VSEN_EN 0x2000
+#define ADCIN_VSEN_EN_SHIFT 13
+#define ADCIN_VCHR_EN 0x4000
+#define ADCIN_VCHR_EN_SHIFT 14
+
+// (0xB00) BOOST_CON0
+#define VBOOST_EN_MASK 0x0001
+#define VBOOST_EN_SHIFT 0
+#define VBOOST_TYPE_MASK 0x0002
+#define VBOOST_TYPE_SHIFT 1
+#define VBOOST_MODE_MASK 0x0004
+#define VBOOST_MODE_SHIFT 2
+#define VBOOST_VRSEL_MASK 0x01F0
+#define VBOOST_VRSEL_SHIFT 4
+
+// (0xB0C) BOOST_CON3
+#define VBOOST_CKS_PRG_MASK 0x003F
+#define VBOOST_CKS_PRG_SHIFT 0
+
+// (0xC00) ISINK0_CON0
+#define ISINK0_EN_MASK 0x0001
+#define ISINK0_EN_SHIFT 0
+#define ISINK0_MODE_MASK 0x0002
+#define ISINK0_MODE_SHIFT 1
+#define ISINK0_STEP_MASK 0x0070
+#define ISINK0_STEP_SHIFT 4
+#define ISINK0_STATUS_MASK 0x8000
+#define ISINK0_STATUS_SHIFT 15
+
+// (0xC10) ISINK1_CON0
+#define ISINK1_EN_MASK 0x0001
+#define ISINK1_EN_SHIFT 0
+#define ISINK1_MODE_MASK 0x0002
+#define ISINK1_MODE_SHIFT 1
+#define ISINK1_STEP_MASK 0x0070
+#define ISINK1_STEP_SHIFT 4
+#define ISINK1_STATUS_MASK 0x8000
+#define ISINK1_STATUS_SHIFT 15
+
+// (0xC20) ISINK2_CON0
+#define ISINK2_EN_MASK 0x0001
+#define ISINK2_EN_SHIFT 0
+#define ISINK2_MODE_MASK 0x0002
+#define ISINK2_MODE_SHIFT 1
+#define ISINK2_STEP_MASK 0x0070
+#define ISINK2_STEP_SHIFT 4
+#define ISINK2_STATUS_MASK 0x8000
+#define ISINK2_STATUS_SHIFT 15
+
+// (0xC30) ISINK3_CON0
+#define ISINK3_EN_MASK 0x0001
+#define ISINK3_EN_SHIFT 0
+#define ISINK3_MODE_MASK 0x0002
+#define ISINK3_MODE_SHIFT 1
+#define ISINK3_STEP_MASK 0x0070
+#define ISINK3_STEP_SHIFT 4
+#define ISINK3_STATUS_MASK 0x8000
+#define ISINK3_STATUS_SHIFT 15
+
+// (0xC40) ISINK4_CON0
+#define ISINK4_EN_MASK 0x0001
+#define ISINK4_EN_SHIFT 0
+#define ISINK4_MODE_MASK 0x0002
+#define ISINK4_MODE_SHIFT 1
+#define ISINK4_STEP_MASK 0x0070
+#define ISINK4_STEP_SHIFT 4
+#define ISINK4_STATUS_MASK 0x8000
+#define ISINK4_STATUS_SHIFT 15
+
+// (0xC80) KPLED CON0
+#define KPLED_EN_MASK 0x0001
+#define KPLED_EN_SHIFT 0
+#define KPLED_MODE_MASK 0x0002
+#define KPLED_MODE_SHIFT 1
+#define KPLED_SEL_MASK 0x0070
+#define KPLED_SEL_SHIFT 4
+#define KPLED_STATUS_MASK 0x8000
+#define KPLED_STATUS_SHIFT 15
+
+// (0xC90) FLASH_CON0
+#define FLASH_EN_MASK 0x0001
+#define FLASH_EN_SHIFT 0
+#define FLASH_MODE_MASK 0x0002
+#define FLASH_MODE_SHIFT 1
+#define FLASH_SEL_MASK 0x0070
+#define FLASH_SEL_SHIFT 4
+#define FLASH_STATUS_MASK 0x8000
+#define FLASH_STATUS_SHIFT 15
+
+// (0xD00) SPK_CON0
+#define SPK_EN_MASK 0x0001
+#define SPK_EN_SHIFT 0
+#define SPK_VOL_MASK 0x0010
+#define SPK_VOL_SHIFT 4
+#define SPK_OCFB_EN_MASK 0x2000
+#define SPK_OCFB_EN_SHIFT 13
+
+// (0xE00) PMIC_OC_CON0
+#define VRF_OC_INT_EN_MASK 0x0001
+#define VRF_OC_INT_EN_SHIFT 0
+#define VTCXO_OC_INT_EN_MASK 0x0002
+#define VTCXO_OC_INT_EN_SHIFT 1
+#define VA_OC_INT_EN_MASK 0x0004
+#define VA_OC_INT_EN_SHIFT 2
+#define VCAMA_OC_INT_EN_MASK 0x0008
+#define VCAMA_OC_INT_EN_SHIFT 3
+#define VCAMD_OC_INT_EN_MASK 0x0010
+#define VCAMD_OC_INT_EN_SHIFT 4
+#define VIO_OC_INT_EN_MASK 0x0020
+#define VIO_OC_INT_EN_SHIFT 5
+#define VUSB_OC_INT_EN_MASK 0x0040
+#define VUSB_OC_INT_EN_SHIFT 6
+#define VBT_OC_INT_EN_MASK 0x0080
+#define VBT_OC_INT_EN_SHIFT 7
+#define VSIM_OC_INT_EN_MASK 0x0100
+#define VSIM_OC_INT_EN_SHIFT 8
+#define VSIM2_OC_INT_EN_MASK 0x0200
+#define VSIM2_OC_INT_EN_SHIFT 9
+#define VBACKUP_OC_INT_EN_MASK 0x0400
+#define VBACKUP_OC_INT_EN_SHIFT 10
+#define VIBR_OC_INT_EN_MASK 0x0800
+#define VIBR_OC_INT_EN_SHIFT 11
+#define VMC_OC_INT_EN_MASK 0x1000
+#define VMC_OC_INT_EN_SHIFT 12
+
+// (0xE04) PMIC_OC_CON1
+#define VCORE_OC_INT_EN_MASK 0x0001
+#define VCORE_OC_INT_EN_SHIFT 0
+#define VM_OC_INT_EN_MASK 0x0002
+#define VM_OC_INT_EN_SHIFT 1
+
+
+
+
+////////////////////////////////////////////////////////////////
+
+
+
+#endif // #if defined(PMIC_6236_REG_API)
+
+#endif // #ifndef __DCL_PMIC6236_HW_H_STRUCT__
+
+
+
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6236_sw.h b/mcu/driver/peripheral/inc/dcl_pmu6236_sw.h
new file mode 100644
index 0000000..0a72e5c
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6236_sw.h
@@ -0,0 +1,923 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6236_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMU6236
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+
+#ifndef __DCL_PMU6236_SW_H_STRUCT__
+#define __DCL_PMU6236_SW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6236_REG_API)
+
+/* Charger external interrupt is fixed. */
+
+
+#define PMU_CHR_EINT_PIN 15
+
+/* adc number for measuring VBAT/VISENSE/VCHARGER is fixed internally. */
+
+#if defined(DRV_MISC_PMU_ADC_CHANNEL_FROM_0)
+#define PMU_ADC_VBAT_CH_NUM 0
+#define PMU_ADC_VISENSE_CH_NUM 1
+#define PMU_ADC_VCHARGER_CH_NUM 2
+#else // #if defined(DRV_MISC_PMU_ADC_CHANNEL_FROM_0)
+#define PMU_ADC_VBAT_CH_NUM 3
+#define PMU_ADC_VISENSE_CH_NUM 4
+#define PMU_ADC_VCHARGER_CH_NUM 5
+#endif // #if defined(DRV_MISC_PMU_ADC_CHANNEL_FROM_0)
+
+
+/* adc factor for VBAT/VISENSE/VCHARGER */
+#define PMU_ADC_FACTOR_VBAT 100
+#define PMU_ADC_FACTOR_VISENSE 100
+#define PMU_ADC_FACTOR_VCHARGER 473 // 369/39 * 50
+
+
+// Define to enable pmu6236 charger watch dog timer kick
+// When enable charger, pmu6236 will enable a watch dog timer
+// We need to kick the timer periodically, to ontify pmu6236 that BB is alive
+// If timeout, pmu6236 will disable charge automatically
+// #### If this is NOT enabled, we will disable the watch dog timer function at boot time
+// This should be defined when PMU driver need to perform WDT clear
+// BMT already support charge WDT, so this should be comment
+//#define pmu6236_ENABLE_DRIVER_CHARGE_WDT
+
+
+// Define to disable charge WDT of pmu6236
+// Define only for debug purpose
+//#define DEBUG_DISABLE_CHARGE_WDT
+
+#define LDO_ADDRESS_BIAS 0x10
+#define CAL_MAX 0x10
+#define PMU_START_BASE MIXED_base
+
+
+
+typedef enum{
+ PMU6236_DEFAULT_LOCAL_SENSE=0,
+ PMU6236_REMOTE_SENSE
+}pmu6236_sense_enum;
+
+typedef enum{
+ VRF_ON_SEL_SRCLKENA=0,
+ VRF_ON_SEL_VRF_EN
+}pmu6236_vrf_on_sel_enum;
+
+
+typedef enum{
+ VTCXO_ON_SEL_SRCLKENA=0,
+ VTCXO_ON_SEL_VTCXO_EN
+}pmu6236_vtcxo_on_sel_enum;
+
+typedef enum{
+ pmu6236_VSIM_1_8V = 0,
+ pmu6236_VSIM_3_0V
+}pmu6236_vsim_vosel_enum;
+
+typedef enum{
+ pmu6236_VSIM2_1_3V = 0,
+ pmu6236_VSIM2_1_5V,
+ pmu6236_VSIM2_1_8V,
+ pmu6236_VSIM2_2_5V,
+ pmu6236_VSIM2_2_8V,
+ pmu6236_VSIM2_3_0V,
+ pmu6236_VSIM2_3_3V
+// pmu6236_VSIM2_3_3V // ?????
+}pmu6236_vsim2_vosel_enum;
+
+typedef enum{
+ pmu6236_VMC_1_3V = 0,
+ pmu6236_VMC_1_5V,
+ pmu6236_VMC_1_8V,
+ pmu6236_VMC_2_5V,
+ pmu6236_VMC_2_8V,
+ pmu6236_VMC_3_0V,
+ pmu6236_VMC_3_3V
+}pmu6236_vmc_vosel_enum;
+
+typedef enum{
+ VBT_SEL_2_8V = 0,
+ VBT_SEL_3_0V
+}pmu6236_vbt_sel_enum;
+
+typedef enum{
+ VCAMD_SEL_1_3V = 0,
+ VCAMD_SEL_1_5V,
+ VCAMD_SEL_1_8V,
+ VCAMD_SEL_2_8V,
+ VCAMD_SEL_RSV1, // reserved
+ VCAMD_SEL_RSV2,
+ VCAMD_SEL_RSV3,
+ VCAMD_SEL_RSV4
+}pmu6236_vcamd_vosel_enum;
+
+typedef enum{
+ VCAMA_SEL_1_5V = 0,
+ VCAMA_SEL_1_8V,
+ VCAMA_SEL_2_5V,
+ VCAMA_SEL_2_8V
+}pmu6236_vcama_vosel_enum;
+
+typedef enum{
+ VCORE_VOSEL_1_2V = 0
+}pmu6236_vcore_vosel_enum;
+
+typedef enum{
+ VCORE_VFBADJ_1_2V = 0,
+ VCORE_VFBADJ_1_225V = 1,
+ VCORE_VFBADJ_1_25V = 2,
+ VCORE_VFBADJ_1_275V = 3,
+ VCORE_VFBADJ_1_3V = 4,
+ VCORE_VFBADJ_1_3V_rev1 = 5,
+ VCORE_VFBADJ_1_3V_rev2 = 6,
+ VCORE_VFBADJ_1_3V_rev3 = 7,
+ VCORE_VFBADJ_1_3V_rev4 = 8,
+ VCORE_VFBADJ_1_3V_rev5 = 9,
+ VCORE_VFBADJ_1_3V_rev6 = 10,
+ VCORE_VFBADJ_1_3V_rev7 = 11,
+ VCORE_VFBADJ_1_3V_rev8 = 12,
+ VCORE_VFBADJ_1_3V_rev9 = 13,
+ VCORE_VFBADJ_1_3V_rev10= 14,
+ VCORE_VFBADJ_1_3V_rev11= 15,
+ VCORE_VFBADJ_0_8V = 16,
+ VCORE_VFBADJ_0_825V = 17,
+ VCORE_VFBADJ_0_85V = 18,
+ VCORE_VFBADJ_0_875V = 19,
+ VCORE_VFBADJ_0_9V = 20,
+ VCORE_VFBADJ_0_925V = 21,
+ VCORE_VFBADJ_0_95V = 22,
+ VCORE_VFBADJ_0_975V = 23,
+ VCORE_VFBADJ_1_0V = 24,
+ VCORE_VFBADJ_1_025V = 25,
+ VCORE_VFBADJ_1_05V = 26,
+ VCORE_VFBADJ_1_075V = 27,
+ VCORE_VFBADJ_1_1V = 28,
+ VCORE_VFBADJ_1_125V = 29,
+ VCORE_VFBADJ_1_15V = 30,
+ VCORE_VFBADJ_1_175V = 31
+
+}pmu6236_vcore_vfbadj_enum;
+
+typedef enum{
+ VCORE_MODESET_AUTO = 0,
+ VCORE_MODESET_PWM
+}pmu6236_vcore_modeset_enum;
+
+typedef enum{
+ VCORE_CSL_130K = 0,
+ VCORE_CSL_120K,
+ VCORE_CSL_110K,
+ VCORE_CSL_100K,
+ VCORE_CSL_90K,
+ VCORE_CSL_80K,
+ VCORE_CSL_70K,
+ VCORE_CSL_60K
+}pmu6236_vcore_csl_enum;
+
+typedef enum{
+ VCORE_600_450 = 0,
+ VCORE_650_500,
+ VCORE_500_350,
+ VCORE_550_400
+}pmu6236_vcore_burst_enum;
+
+typedef enum{
+ VM_CSL_130K = 0,
+ VM_CSL_120K,
+ VM_CSL_110K,
+ VM_CSL_100K,
+ VM_CSL_90K,
+ VM_CSL_80K,
+ VM_CSL_70K,
+ VM_CSL_60K
+}pmu6236_vm_csl_enum;
+
+typedef enum{
+ VM_600_450 = 0,
+ VM_650_500,
+ VM_500_350,
+ VM_550_400
+}pmu6236_vm_burst_enum;
+
+typedef enum{
+ CHR_CURR_800_0MA = 0,
+ CHR_CURR_700_0MA,
+ CHR_CURR_600_0MA,
+ CHR_CURR_500_0MA,
+ CHR_CURR_400_0MA,
+ CHR_CURR_300_0MA,
+ CHR_CURR_200_0MA,
+ CHR_CURR_100_0MA
+}pmu6236_chr_current_enum;
+
+typedef enum{
+ CHR_VBAT_CC_3_250V = 0,
+ CHR_VBAT_CC_3_275V,
+ CHR_VBAT_CC_3_300V,
+ CHR_VBAT_CC_3_325V
+}pmu6236_chr_vbat_cc_enum;
+
+typedef enum{
+/*0x00*/ CHR_VBAT_CV_4_0000V = 0,
+/*0x01*/ CHR_VBAT_CV_4_0125V,
+/*0x02*/ CHR_VBAT_CV_4_0250V,
+/*0x03*/ CHR_VBAT_CV_4_0375V,
+/*0x04*/ CHR_VBAT_CV_4_0500V,
+/*0x05*/ CHR_VBAT_CV_4_0625V,
+/*0x06*/ CHR_VBAT_CV_4_0750V,
+/*0x07*/ CHR_VBAT_CV_4_0875V,
+/*0x08*/ CHR_VBAT_CV_4_1000V,
+/*0x09*/ CHR_VBAT_CV_4_1125V,
+/*0x0a*/ CHR_VBAT_CV_4_1250V,
+/*0x0b*/ CHR_VBAT_CV_4_1375V,
+/*0x0c*/ CHR_VBAT_CV_4_1500V,
+/*0x0d*/ CHR_VBAT_CV_4_1625V,
+/*0x0e*/ CHR_VBAT_CV_4_1750V,
+/*0x0f*/ CHR_VBAT_CV_4_1875V,
+/*0x10*/ CHR_VBAT_CV_4_2000V,
+/*0x11*/ CHR_VBAT_CV_4_2125V,
+/*0x12*/ CHR_VBAT_CV_4_2250V,
+/*0x13*/ CHR_VBAT_CV_4_2375V,
+/*0x14*/ CHR_VBAT_CV_4_2500V,
+/*0x15*/ CHR_VBAT_CV_4_2625V,
+/*0x16*/ CHR_VBAT_CV_4_2750V,
+/*0x17*/ CHR_VBAT_CV_4_2875V
+}pmu6236_chr_vbat_cv_enum;
+
+typedef enum{
+ CV_TUNE_1_205V = 0,
+ CV_TUNE_1_210V,
+ CV_TUNE_1_215V,
+ CV_TUNE_1_180V,
+ CV_TUNE_1_185V,
+ CV_TUNE_1_190V,
+ CV_TUNE_1_195V
+}pmu6236_cv_tune_enum;
+
+typedef enum{
+ CAL_PRECC_50_0MA = 0,
+ CAL_PRECC_87_5_MA,
+ CAL_PRECC_150_0MA,
+ CAL_PRECC_225_0MA
+}pmu6236_cal_precc_enum;
+
+typedef enum{
+ SYSTEM_PWR_SRC_DEFAULT = 0,
+ SYSTEM_PWR_SRC_REFER_PS_SET
+}pmu6236_ps_sel_enum;
+
+typedef enum{
+ SYSTEM_PWR_SRC_VBAT = 0,
+ SYSTEM_PWR_SRC_AC
+}pmu6236_ps_set_enum;
+
+typedef enum{
+ CHR_OV_5_5V = 0,
+ CHR_OV_6_0V,
+ CHR_OV_6_5V,
+ CHR_OV_7_0V
+}pmu6236_chr_ov_enum;
+
+typedef enum{
+ CHR_WDT_4_SEC = 0,
+ CHR_WDT_8_SEC,
+ CHR_WDT_16_SEC,
+ CHR_WDT_32_SEC,
+ CHR_WDT_45_MIN
+}pmu6236_chr_wdt_td_enum;
+
+typedef enum{
+ VIBR_SEL_1_3V = 0,
+ VIBR_SEL_1_5V,
+ VIBR_SEL_1_8V,
+ VIBR_SEL_2_5V,
+ VIBR_SEL_2_8V,
+ VIBR_SEL_3_0V,
+ VIBR_SEL_3_3V
+}pmu6236_vibr_vosel_enum;
+
+typedef enum{
+ SPK_VOL_12DB = 0,
+ SPK_VOL_18DB
+}pmu6236_spk_vol_enum;
+
+typedef enum{
+ VBOOST_TYPE_VOLTAGE_CONTROLLER = 0,
+ VBOOST_TYPE_CURRENT_CONVERTER
+}pmu6236_vboost_type_enum;
+
+typedef enum{
+ VBOOST_DIMMING_MODE = 0, // Controlled by PWM
+ VBOOST_PWM_MODE = 0,
+ VBOOST_REGISTER_CONTROL_MODE = 1,
+ VBOOST_NORMAL_MODE = 1
+}pmu6236_vboost_mode_enum;
+
+//typedef enum{
+// VBOOST_PWM_MODE = 0,
+// VBOOST_REGISTER_CONTROL_MODE
+//}pmu6236_vboost_mode_enum;
+
+typedef enum{
+ PMU6236_ISINK_PWM_MODE = 0,
+ PMU6236_ISINK_REGISTER_CONTROL_MODE = 1
+}pmu6236_isink_mode_enum;
+
+typedef enum{
+ ISINK_STEP_4MA = 0,
+ ISINK_STEP_8MA,
+ ISINK_STEP_12MA,
+ ISINK_STEP_16MA,
+ ISINK_STEP_20MA,
+ ISINK_STEP_24MA
+}pmu6236_isink_step_enum;
+
+
+typedef enum{
+ OC_TD_100_US = 0,
+ OC_TD_200_US,
+ OC_TD_400_US,
+ OC_TD_800_US
+}pmu6236_oc_td_enum;
+
+
+typedef enum{
+ STB_TD_100_US = 0,
+ STB_TD_200_US,
+ STB_TD_400_US,
+ STB_TD_800_US
+}pmu6236_stb_td_enum;
+
+// (0xC80) KPLED CON0
+typedef enum{
+ PMU6236_KPLED_PWM_MODE = 0,
+ PMU6236_KPLED_REGISTER_CONTROL_MODE = 1,
+ PMU6236_KPLED_NORMAL_MODE = 1
+}pmu6236_kpled_mode_enum;
+
+// (0xC90) FLASH_CON0
+typedef enum{
+ FLASH_PWM_MODE = 0,
+ FLASH_REGISTER_CONTROL_MODE = 1,
+ FLASH_NORMAL_MODE = 1
+}pmu6236_flash_mode_enum;
+
+//typedef enum{
+// KPLED_1_WLED_1_RLED = 0,
+// KPLED_4_WLED_4_RLED = 3,
+// KPLED_4_WLED_8_RLED = 7
+//}pmu6236_kpled_sel_enum;
+
+
+// Used to fill PCHR_FLAG_SEL
+typedef enum{
+ PCHR_CMD_PCHR_STATE = 2
+}pmu6236_pchr_cmd_enum;
+
+typedef enum{
+ PCHR_STATE_IDLE = 0
+}pmu6236_pchr_state_enum;
+
+/*
+typedef enum{
+ BL_MODE_1 = 0,
+ BL_MODE_2,
+ BL_MODE_3
+}pmu6236_bl_mode_enum;
+*/
+
+/*
+// =====================================================================================
+// (0x800) VRF_CON0
+extern void pmu6236_vrf_enable(kal_bool enable);
+extern void pmu6236_vrf_on_sel(pmu6236_vrf_on_sel_enum sel);
+extern void pmu6236_vrf_sense(pmu6236_sense_enum sel);
+extern void pmu6236_vrf_ndis_enable(kal_bool enable);
+extern void pmu6236_vrf_stb_enable(kal_bool enable);
+extern void pmu6236_vrf_oc_auto_off(kal_bool enable);
+extern void pmu6236_vrf_ocfb_enable(kal_bool enable);
+extern kal_bool pmu6236_vrf_status(void);
+
+// (0x804) VRF_CON1
+extern void pmu6236_vrf_cal(kal_uint8 val);
+
+// (0x810) VTCXO_CON0
+extern void pmu6236_vtcxo_enable(kal_bool enable);
+extern void pmu6236_vtcxo_on_sel(pmu6236_vtcxo_on_sel_enum sel);
+extern void pmu6236_vtcxo_ndis_enable(kal_bool enable);
+extern void pmu6236_vtcxo_stb_enable(kal_bool enable);
+extern void pmu6236_vtcxo_oc_auto_off(kal_bool enable);
+extern void pmu6236_vtcxo_ocfb_enable(kal_bool enable);
+extern kal_bool pmu6236_vtcxo_status(void);
+
+// (0x814) VTCXO_CON1
+extern void pmu6236_vtcxo_cal(kal_uint8 val);
+
+// (0x820) VA_CON0
+extern void pmu6236_va_sense(pmu6236_sense_enum sel);
+extern void pmu6236_va_ndis_enable(kal_bool enable);
+extern void pmu6236_va_stb_enable(kal_bool enable);
+extern void pmu6236_va_oc_auto_off(kal_bool enable);
+extern void pmu6236_va_ocfb_enable(kal_bool enable);
+extern kal_bool pmu6236_va_status(void);
+
+// (0x824) VA_CON1
+extern void pmu6236_va_cal(kal_uint8 val);
+
+// (0x830) VCAMA_CON0
+extern void pmu6236_vcama_enable(kal_bool enable);
+extern void pmu6236_vcama_vosel(pmu6236_vcama_vosel_enum sel);
+extern void pmu6236_vcama_ndis_enable(kal_bool enable);
+extern void pmu6236_vcama_stb_enable(kal_bool enable);
+extern void pmu6236_vcama_oc_auto_off(kal_bool enable);
+extern void pmu6236_vcama_ocfb_enable(kal_bool enable);
+extern kal_bool pmu6236_vcama_status(void);
+
+// (0x834) VCAMA_CON1
+extern void pmu6236_vcama_cal(kal_uint8 val);
+
+// (0x838) VCAMA CON2
+extern void pmu6236_vcama_oc_td(pmu6236_oc_td_enum sel);
+extern void pmu6236_vcama_stb_td(pmu6236_stb_td_enum sel);
+
+// (0x840) VCAMD_CON0
+extern void pmu6236_vcamd_enable(kal_bool enable);
+extern void pmu6236_vcamd_vosel(pmu6236_vcamd_vosel_enum sel);
+extern void pmu6236_vcamd_ndis_enable(kal_bool enable);
+extern void pmu6236_vcamd_stb_enable(kal_bool enable);
+extern void pmu6236_vcamd_oc_auto_off(kal_bool enable);
+extern void pmu6236_vcamd_ocfb_enable(kal_bool enable);
+extern kal_bool pmu6236_vcamd_status(void);
+
+// (0x844) VCAMD_CON1
+extern void pmu6236_vcamd_cal(kal_uint8 val);
+
+// (0x850) VIO_CON0
+extern void pmu6236_vio_sense(pmu6236_sense_enum sel);
+extern void pmu6236_vio_ndis_enable(kal_bool enable);
+extern void pmu6236_vio_stb_enable(kal_bool enable);
+extern void pmu6236_vio_oc_auto_off(kal_bool enable);
+extern void pmu6236_vio_ocfb_enable(kal_bool enable);
+extern kal_bool pmu6236_vio_status(void);
+
+// (0x854) VIO_CON1
+extern void pmu6236_vio_cal(kal_uint8 val);
+
+// (0x858) VIO_CON2
+extern void pmu6236_vio_oc_td(pmu6236_oc_td_enum sel);
+
+// (0x860) VUSB_CON0
+extern void pmu6236_vusb_enable(kal_bool enable);
+extern void pmu6236_vusb_ndis_enable(kal_bool enable);
+extern void pmu6236_vusb_stb_enable(kal_bool enable);
+extern void pmu6236_vusb_oc_auto_off(kal_bool enable);
+extern void pmu6236_vusb_ocfb_enable(kal_bool enable);
+extern kal_bool pmu6236_vusb_status(void);
+
+// (0x864) VUSB_CON1
+extern void pmu6236_vusb_cal(kal_uint8 val);
+
+// (0x868) VUSB_CON2
+extern void pmu6236_vusb_oc_td(pmu6236_oc_td_enum sel);
+
+// (0x870) VBT_CON0
+extern void pmu6236_vbt_enable(kal_bool enable);
+extern void pmu6236_vbt_vosel(pmu6236_vbt_sel_enum sel);
+extern void pmu6236_vbt_ndis_enable(kal_bool enable);
+extern void pmu6236_vbt_stb_enable(kal_bool enable);
+extern void pmu6236_vbt_oc_auto_off(kal_bool enable);
+extern void pmu6236_vbt_ocfb_enable(kal_bool enable);
+extern kal_bool pmu6236_vbt_status(void);
+
+// (0x874) VBT_CON1
+extern void pmu6236_vbt_cal(kal_uint8 val);
+
+// (0x878) VBT_CON2
+extern void pmu6236_vbt_oc_td(pmu6236_oc_td_enum sel);
+
+// (0x880) VSIM_CON0
+extern void pmu6236_vsim_enable(kal_bool enable);
+extern void pmu6236_vsim_vosel(pmu6236_vsim_vosel_enum sel);
+extern void pmu6236_vsim_ndis_enable(kal_bool enable);
+extern void pmu6236_vsim_stb_enable(kal_bool enable);
+extern void pmu6236_vsim_oc_auto_off(kal_bool enable);
+extern void pmu6236_vsim_ocfb_enable(kal_bool enable);
+extern kal_bool pmu6236_vsim_status(void);
+
+// (0x884) VSIM_CON1
+extern void pmu6236_vsim_cal(kal_uint8 val);
+
+// (0x888) VSIM_CON2
+extern void pmu6236_vsim_oc_td(pmu6236_oc_td_enum sel);
+
+// (0x890) VSIM2_CON0
+extern void pmu6236_vsim2_enable(kal_bool enable);
+extern void pmu6236_vsim2_vosel(pmu6236_vsim2_vosel_enum sel);
+extern void pmu6236_vsim2_ndis_enable(kal_bool enable);
+extern void pmu6236_vsim2_stb_enable(kal_bool enable);
+extern void pmu6236_vsim2_oc_auto_off(kal_bool enable);
+extern void pmu6236_vsim2_ocfb_enable(kal_bool enable);
+extern kal_bool pmu6236_vsim2_status(void);
+
+// (0x894) VSIM2_CON1
+extern void pmu6236_vsim2_cal(kal_uint8 val);
+
+// (0x898) VSIM2_CON2
+extern void pmu6236_vsim2_gpldo_en(kal_bool enable);
+
+// (0x8A0) VBACKUP_CON0
+extern void pmu6236_vbackup_enable(kal_bool enable);
+extern void pmu6236_vbackup_ndis_enable(kal_bool enable);
+extern void pmu6236_vbackup_stb_enable(kal_bool enable);
+extern void pmu6236_vbackup_oc_auto_off(kal_bool enable);
+extern void pmu6236_vbackup_ocfb_enable(kal_bool enable);
+extern kal_bool pmu6236_vbackup_status(void);
+
+// (0x8B0) VIBR_CON0
+extern void pmu6236_vibr_enable(kal_bool enable);
+extern void pmu6236_vibr_vosel(pmu6236_vibr_vosel_enum sel);
+extern void pmu6236_vibr_ndis_enable(kal_bool enable);
+extern void pmu6236_vibr_stb_enable(kal_bool enable);
+extern void pmu6236_vibr_oc_auto_off(kal_bool enable);
+extern void pmu6236_vibr_ocfb_enable(kal_bool enable);
+extern kal_bool pmu6236_vibr_status(void);
+
+// (0x8B4) VIBR_CON1
+extern void pmu6236_vibr_cal(kal_uint8 val);
+
+// (0x8C0) VMC_CON0
+extern void pmu6236_vmc_enable(kal_bool enable);
+extern void pmu6236_vmc_vosel(pmu6236_vmc_vosel_enum sel);
+extern void pmu6236_vmc_ndis_enable(kal_bool enable);
+extern void pmu6236_vmc_stb_enable(kal_bool enable);
+extern void pmu6236_vmc_oc_auto_off(kal_bool enable);
+extern void pmu6236_vmc_ocfb_enable(kal_bool enable);
+extern kal_bool pmu6236_vmc_status(void);
+
+// (0x8C4) VMC_CON1
+extern void pmu6236_vmc_cal(kal_uint8 val);
+
+// (0x900) VCORE_CON0
+extern void pmu6236_vcore_enable(kal_bool enable);
+extern void pmu6236_vcore_sense(pmu6236_sense_enum sel);
+extern void pmu6236_vcore_vfbadj(pmu6236_vcore_vfbadj_enum sel);
+extern kal_uint16 pmu6236_get_vcore_vfbadj(void);
+extern void pmu6236_vcore_stb_enable(kal_bool enable);
+extern void pmu6236_vcore_oc_auto_off(kal_bool enable);
+extern void pmu6236_vcore_ocfb_enable(kal_bool enable);
+extern kal_bool pmu6236_vcore_status(void);
+
+// (0x904) VCORE_CON1
+extern void pmu6236_vcore_modeset(pmu6236_vcore_modeset_enum mode);
+extern void pmu6236_vcore_vfbadj_slp(pmu6236_vcore_vfbadj_enum sel);
+extern kal_uint16 pmu6236_get_vcore_vfbadj_slp(void);
+
+// (0x908) VCORE_CON2
+extern void pmu6236_vcore_vosel(pmu6236_vcore_vosel_enum sel);
+extern void pmu6236_vcore_cal(kal_uint8 val);
+
+// (0x90C) VCORE_CON3
+extern void pmu6236_vcore_ical_en(kal_uint8 sel);
+
+// (0x914) VCORE_CON5
+extern void pmu6236_vcore_csl(pmu6236_vcore_csl_enum sel);
+extern void pmu6236_vcore_burst(pmu6236_vcore_burst_enum sel);
+
+// (0x920) VM_CON0
+extern void pmu6236_vm_sense(pmu6236_sense_enum sel);
+extern void pmu6236_vm_stb_enable(kal_bool enable);
+extern void pmu6236_vm_oc_auto_off(kal_bool enable);
+extern void pmu6236_vm_ocfb_enable(kal_bool enable);
+extern kal_bool pmu6236_vm_status(void);
+
+// (0x928) VM_COM2
+extern void pmu6236_vm_cal(kal_uint8 val);
+
+// (0x92C) VM_CON3
+extern void pmu6236_vm_ical_en(kal_uint8 sel);
+
+// (0x934) VM_CON5
+extern void pmu6236_vm_csl(pmu6236_vm_csl_enum val);
+extern void pmu6236_vm_burst(pmu6236_vm_burst_enum val);
+
+// (0xA00) CHR_CON0
+extern void pmu6236_chr_vcdt_lv_vth(kal_uint8 val);
+extern void pmu6236_chr_vcdt_hv_vth(kal_uint8 val);
+extern void pmu6236_chr_vcdt_hv_enable(kal_bool enable);
+extern void pmu6236_chr_enable(kal_bool enable);
+extern kal_bool pmu6236_chr_chrdet(void);
+extern kal_bool pmu6236_chr_ovp(void);
+
+// (0xA04) CHR_CON1
+extern void pmu6236_chr_vbat_cv_vth(pmu6236_chr_vbat_cv_enum cv);
+extern void pmu6236_chr_vbat_cc_vth(pmu6236_chr_vbat_cc_enum cc);
+extern void pmu6236_chr_vbat_cv_enable(kal_bool enable);
+extern void pmu6236_chr_vbat_cc_enable(kal_bool enable);
+extern kal_bool pmu6236_chr_cv_det(void);
+extern kal_bool pmu6236_chr_cc_det(void);
+
+// (0xA08) CHR_CON2
+extern void pmu6236_chr_cs_enable(kal_bool enable);
+extern void pmu6236_chr_current(pmu6236_chr_current_enum sel);
+
+// (0xA0C) CHR_CON3
+extern void pmu6236_chr_csdac_dly(kal_uint32 sel);
+extern void pmu6236_chr_csdac_stp(kal_uint32 sel);
+
+// (0xA14) CHR_CON5
+extern kal_uint16 pmu6236_chr_control_state(kal_uint16 sel);
+extern pmu6236_pchr_state_enum pmu6236_get_pchr_state(void);
+
+// (0xA18) CHR_CON6
+extern void pmu6236_chr_wdt_td(pmu6236_chr_wdt_td_enum sel);
+extern void pmu6236_chr_wdt_enable(kal_bool enable);
+
+// (0xA1C) CHR_CON7
+extern void pmu6236_chr_wdt_intr_enable(kal_bool enable);
+extern kal_bool pmu6236_chr_wdt_status(void);
+extern void pmu6236_chr_wdt_clear(void);
+
+// (0xA20) CHR_CON8
+extern void pmic6236_chr_adc_meas_on(kal_bool enable);
+
+// (0xB00) BOOST_CON0
+extern void pmu6236_vboost_enable(kal_bool enable);
+extern kal_bool pmu6236_get_vboost_enable(void);
+extern void pmu6236_vboost_type(pmu6236_vboost_type_enum sel);
+extern pmu6236_vboost_type_enum pmu6236_get_vboost_type(void);
+extern void pmu6236_vboost_mode(pmu6236_vboost_mode_enum sel);
+extern pmu6236_vboost_mode_enum pmu6236_get_vboost_mode(void);
+extern void pmu6236_vboost_vrsel(kal_uint16 val);
+extern kal_uint16 pmu6236_get_vboost_vrsel(void);
+
+// (0xB0C) BOOST_CON3
+extern void pmu6236_vboost_cks_prg(kal_uint8 val);
+
+// (0xC00) ISINK0_CON0
+extern void pmu6236_isink0_enable(kal_bool enable);
+extern void pmu6236_isink0_mode(pmu6236_isink_mode_enum sel);
+extern void pmu6236_isink0_step(pmu6236_isink_step_enum sel);
+extern kal_bool pmu6236_isink0_status(void);
+
+// (0xC10) ISINK1_CON0
+extern void pmu6236_isink1_enable(kal_bool enable);
+extern void pmu6236_isink1_mode(pmu6236_isink_mode_enum sel);
+extern void pmu6236_isink1_step(pmu6236_isink_step_enum sel);
+extern kal_bool pmu6236_isink1_status(void);
+
+// (0xC20) ISINK2_CON0
+extern void pmu6236_isink2_enable(kal_bool enable);
+extern void pmu6236_isink2_mode(pmu6236_isink_mode_enum sel);
+extern void pmu6236_isink2_step(pmu6236_isink_step_enum sel);
+extern kal_bool pmu6236_isink2_status(void);
+
+// (0xC30) ISINK3_CON0
+extern void pmu6236_isink3_enable(kal_bool enable);
+extern void pmu6236_isink3_mode(pmu6236_isink_mode_enum sel);
+extern void pmu6236_isink3_step(pmu6236_isink_step_enum sel);
+extern kal_bool pmu6236_isink3_status(void);
+
+// (0xC40) ISINK4_CON0
+extern void pmu6236_isink4_enable(kal_bool enable);
+extern void pmu6236_isink4_mode(pmu6236_isink_mode_enum sel);
+extern void pmu6236_isink4_step(pmu6236_isink_step_enum sel);
+extern kal_bool pmu6236_isink4_status(void);
+
+// (0x0C80) KPLED_CON0
+extern void pmu6236_kpled_enable(kal_bool enable);
+extern void pmu6236_kpled_mode(pmu6236_kpled_mode_enum sel);
+extern void pmu6236_kpled_sel(kal_uint8 val);
+extern kal_bool pmu6236_kpled_status(void);
+
+// (0x0C90) FLASH_CON0
+extern void pmu6236_flash_enable(kal_bool enable);
+extern void pmu6236_flash_mode(pmu6236_flash_mode_enum sel);
+extern void pmu6236_flash_sel(kal_uint8 sel);
+extern kal_bool pmu6236_flash_status(void);
+
+// (0xD00) SPK_CON0
+extern void pmu6236_spk_enable(kal_bool enable);
+extern kal_bool pmu6236_get_spk_enable(void);
+extern void pmu6236_spk_vol(pmu6236_spk_vol_enum val);
+extern pmu6236_spk_vol_enum pmu6236_get_spk_vol(void);
+extern void pmu6236_spk_ocfb_enable(kal_bool enable);
+
+// (0xE00) PMIC_OC_CON0
+extern void pmu6236_vrf_oc_int_enable(kal_bool enable);
+extern void pmu6236_vtcxo_oc_int_enable(kal_bool enable);
+extern void pmu6236_va_oc_int_enable(kal_bool enable);
+extern void pmu6236_vcama_oc_int_enable(kal_bool enable);
+extern void pmu6236_vcamd_oc_int_enable(kal_bool enable);
+extern void pmu6236_vio_oc_int_enable(kal_bool enable);
+extern void pmu6236_vusb_oc_int_enable(kal_bool enable);
+extern void pmu6236_vbt_oc_int_enable(kal_bool enable);
+extern void pmu6236_vsim_oc_int_enable(kal_bool enable);
+extern void pmu6236_vsim2_oc_int_enable(kal_bool enable);
+extern void pmu6236_vbackup_oc_int_enable(kal_bool enable);
+extern void pmu6236_vibr_oc_int_enable(kal_bool enable);
+extern void pmu6236_vmc_oc_int_enable(kal_bool enable);
+
+// (0xE04) PMIC_OC_CON1
+extern void pmu6236_vcore_oc_int_enable(kal_bool enable);
+extern void pmu6236_vm_oc_int_enable(kal_bool enable);
+
+// Other exported APIs
+extern void pmu6236_init(void);
+extern pmu6236_chr_current_enum pmu6236_ret_chr_current(void);
+extern pmu6236_chr_current_enum pmu6236_ret_usb_current(void);
+extern void pmu6236_init_bl(pmu6236_bl_mode_enum bl_mode);
+extern void pmu6236_enable_bl(kal_bool enable);
+extern void pmu6236_EM_reg_write(kal_uint32 reg, kal_uint16 val);
+extern kal_uint16 pmu6236_EM_reg_read(kal_uint32 reg);
+#if defined(PMIC_6236_CV_TRIM_CALIBRATION)
+extern pmu6236_chr_vbat_cv_enum mt6236_efuse_vbat_cv;
+#endif // #if defined(PMIC_6236_CV_TRIM_CALIBRATION)
+*/
+
+// The following are implemented in custom files
+// MoDIS parser skip start
+// MoDIS parser skip end
+
+
+/*
+typedef enum
+{
+ PMU_FAKE_LDO_BUCK_MAX
+}PMU_FAKE_LDO_BUCK_LIST_ENUM;
+
+
+typedef enum
+{
+ VRF,
+ VTCXO,
+ VA,
+ VCAMA,
+ VCAMD,
+ VIO,
+ VUSB,
+ VBT,
+ VSIM,
+ VSIM2,
+ VBACKUP,
+ VIBR,
+ VMC,
+ VCORE,
+ VM,
+ PMU_LDO_BUCK_MAX,
+ VRF18,
+ VFM
+}PMU_LDO_BUCK_LIST_ENUM;
+
+typedef enum
+{
+ VPA1,
+ PMU_VPA_MAX
+}PMU_VPA_LIST_ENUM;
+
+typedef enum
+{
+ CHR,
+ PMU_CHR_MAX
+}PMU_CHR_LIST_ENUM;
+
+typedef enum
+{
+ SPK,
+ SPKL,
+ SPKR,
+ PMU_SPK_MAX
+}PMU_SPK_LIST_ENUM;
+
+typedef enum
+{
+ ISINK0,
+ ISINK1,
+ ISINK2,
+ ISINK3,
+ ISINK4,
+ PMU_ISINK_MAX
+}PMU_ISINK_LIST_ENUM;
+
+typedef enum
+{
+ BOOST1,
+ BOOST2,
+ PMU_BOOST_MAX
+}PMU_BOOST_LIST_ENUM;
+*/
+
+
+#endif // #ifdef PMIC_6236_REG_API
+#endif // #ifndef __DCL_PMU6236_SW_H_STRUCT__
+
+
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6251_hw.h b/mcu/driver/peripheral/inc/dcl_pmu6251_hw.h
new file mode 100644
index 0000000..1e6d2ca
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6251_hw.h
@@ -0,0 +1,469 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6251_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for PMIC 6251 driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __PMU6251_HW_H__
+#define __PMU6251_HW_H__
+
+#if defined(PMIC_6251_REG_API)
+
+#define PMU_BASE MIXED_base
+#define PMU_END (PMU_BASE+0x1000)
+
+///////////////////////////////////////////////////////////////////////////////
+// LDO group
+#define VRF_CON0 (PMU_BASE + 0x0800)
+#define VTCXO_CON0 (PMU_BASE + 0x0810)
+#define VA_CON0 (PMU_BASE + 0x0820)
+#define VIO28_CON0 (PMU_BASE + 0x0850)
+#define VUSB_CON0 (PMU_BASE + 0x0860)
+#define VSF_CON0 (PMU_BASE + 0x0870)
+#define VSIM_CON0 (PMU_BASE + 0x0880)
+#define VSIM2_CON0 (PMU_BASE + 0x0890)
+#define VRTC_CON0 (PMU_BASE + 0x08A0)
+#define VIBR_CON0 (PMU_BASE + 0x08B0)
+#define VFM_CON0 (PMU_BASE + 0x08D0)
+#define VIO18_CON0 (PMU_BASE + 0x08F0)
+
+// BUCK group
+#define VCORE_CON0 (PMU_BASE + 0x0900)
+
+// BOOST group
+#define BOOST_CON0 (PMU_BASE + 0x0B00)
+
+// iSINK group
+#define ISINK0_CON0 (PMU_BASE + 0x0C00)
+#define ISINK1_CON0 (PMU_BASE + 0x0C10)
+#define ISINK2_CON0 (PMU_BASE + 0x0C20)
+#define ISINK3_CON0 (PMU_BASE + 0x0C30)
+
+// KPLED group
+#define KPLED_CON0 (PMU_BASE + 0x0C80)
+
+// SPK
+#define SPK_CON0 (PMU_BASE + 0x0D00)
+
+// CHR
+#define CHR_CON0 (PMU_BASE + 0x0A00)
+
+#if defined(__MT6251PMU_E1_BC11_VSRC_EN_AT_TEST_CON1_BIT4__)
+#define TEST_CON1 (PMU_BASE + 0x0F04)
+#endif // #if defined(__MT6251PMU_E1_BC11_VSRC_EN_AT_TEST_CON1_BIT4__)
+
+// STARTUP
+#define STRUP_CON0 (PMU_BASE + 0x0A80)
+
+///////////////////////////////////////////////////////////////////////////////
+
+
+// BC11 VSRC_EN
+#define MT6251_E1_BC11_VSRC_EN_MASK 0x0030
+#define MT6251_E1_BC11_VSRC_EN_SHIFT 4
+
+
+#define CON0_OFFSET 0x00
+#define CON1_OFFSET 0x04
+#define CON2_OFFSET 0x08
+#define CON3_OFFSET 0x0C
+#define CON4_OFFSET 0x10
+#define CON5_OFFSET 0x14
+#define CON6_OFFSET 0x18
+#define CON7_OFFSET 0x1C
+#define CON8_OFFSET 0x20
+#define CON9_OFFSET 0x24
+
+// LDO and BUCK cmds
+#define LDO_BUCK_EN_OFFSET CON0_OFFSET
+#define LDO_BUCK_EN_MASK 0x0001
+#define LDO_BUCK_EN_SHIFT 0
+
+#define LDO_BUCK_VOL_SEL_OFFSET CON0_OFFSET
+#define LDO_BUCK_VOL_SEL_MASK 0x01F0
+#define LDO_BUCK_VOL_SEL_SHIFT 4
+
+#define LDO_BUCK_OC_AUTO_OFF_OFFSET CON0_OFFSET
+#define LDO_BUCK_OC_AUTO_OFF_MASK 0x1000
+#define LDO_BUCK_OC_AUTO_OFF_SHIFT 12
+
+#define LDO_BUCK_STB_EN_OFFSET CON0_OFFSET
+#define LDO_BUCK_STB_EN_MASK 0x0800
+#define LDO_BUCK_STB_EN_SHIFT 11
+
+#define LDO_BUCK_ON_SEL_OFFSET CON0_OFFSET
+#define LDO_BUCK_ON_SEL_MASK 0x0002
+#define LDO_BUCK_ON_SEL_SHIFT 1
+
+#define LDO_BUCK_NDIS_EN_OFFSET CON0_OFFSET
+#define LDO_BUCK_NDIS_EN_MASK 0x0400
+#define LDO_BUCK_NDIS_EN_SHIFT 10
+
+#define LDO_BUCK_OCFB_EN_OFFSET CON0_OFFSET
+#define LDO_BUCK_OCFB_EN_MASK 0x2000
+#define LDO_BUCK_OCFB_EN_SHIFT 13
+
+
+// LDO cmds
+#define LDO_CAL_OFFSET CON1_OFFSET
+#define LDO_CAL_MASK 0x01F0
+#define LDO_CAL_SHIFT 4
+
+#define LDO_STB_TD_OFFSET CON1_OFFSET
+#define LDO_STB_TD_MASK 0x0003
+#define LDO_STB_TD_SHIFT 0
+
+#define LDO_OC_TD_OFFSET CON2_OFFSET
+#define LDO_OC_TD_MASK 0x0030
+#define LDO_OC_TD_SHIFT 4
+
+// BUCK cmds
+#define BUCK_VFBADJ_SLEEP_OFFSET CON1_OFFSET
+#define BUCK_VFBADJ_SLEEP_MASK 0x01F0
+#define BUCK_VFBADJ_SLEEP_SHIFT 4
+
+#define BUCK_ICAL_EN_OFFSET CON3_OFFSET
+#define BUCK_ICAL_EN_MASK 0x3000
+#define BUCK_ICAL_EN_SHIFT 12
+
+#define BUCK_CSL_OFFSET CON5_OFFSET
+#define BUCK_CSL_MASK 0x0700
+#define BUCK_CSL_SHIFT 8
+
+#define BUCK_STB_TD_OFFSET CON3_OFFSET
+#define BUCK_STB_TD_MASK 0x00C0
+#define BUCK_STB_TD_SHIFT 6
+
+#define BUCK_OC_THD_OFFSET CON3_OFFSET
+#define BUCK_OC_THD_MASK 0x0300
+#define BUCK_OC_THD_SHIFT 8
+
+#define BUCK_BURST_OFFSET CON5_OFFSET
+#define BUCK_BURST_MASK 0x3000
+#define BUCK_BURST_SHIFT 12
+
+// SPK
+#define SPK_EN_OFFSET CON0_OFFSET
+#define SPK_EN_MASK 0x0001
+#define SPK_EN_SHIFT 0
+
+#define SPK_VOL_OFFSET CON0_OFFSET
+#define SPK_VOL_MASK 0x01F0
+#define SPK_VOL_SHIFT 4
+
+#define SPK_CCODE_OFFSET CON1_OFFSET
+#define SPK_CCODE_MASK 0x00F0
+#define SPK_CCODE_SHIFT 4
+
+#define SPK_OC_EN_OFFSET CON3_OFFSET
+#define SPK_OC_EN_MASK 0x0400
+#define SPK_OC_EN_SHIFT 10
+
+#define SPK_OSC_ISEL_OFFSET CON3_OFFSET
+#define SPK_OSC_ISEL_MASK 0x00C0
+#define SPK_OSC_ISEL_SHIFT 6
+
+#define SPK_NG_DT_DLY_OFFSET CON4_OFFSET
+#define SPK_NG_DT_DLY_MASK 0x000f
+#define SPK_NG_DT_DLY_SHIFT 0
+
+#define SPK_OCP_BIAS_OFFSET CON4_OFFSET
+#define SPK_OCP_BIAS_MASK 0x7000
+#define SPK_OCP_BIAS_SHIFT 12
+
+#define SPK_OCN_BIAS_OFFSET CON4_OFFSET
+#define SPK_OCN_BIAS_MASK 0x0700
+#define SPK_OCN_BIAS_SHIFT 8
+
+
+#define SPK_PG_SLEW_I_OFFSET CON5_OFFSET
+#define SPK_PG_SLEW_I_MASK 0x3000
+#define SPK_PG_SLEW_I_SHIFT 12
+
+#define SPK_NG_SLEW_DLY_OFFSET CON5_OFFSET
+#define SPK_NG_SLEW_DLY_MASK 0x0007
+#define SPK_NG_SLEW_DLY_SHIFT 0
+
+#define SPK_PG_SLEW_DLY_OFFSET CON5_OFFSET
+#define SPK_PG_SLEW_DLY_MASK 0x0700
+#define SPK_PG_SLEW_DLY_SHIFT 8
+
+#define SPK_AB_OBIAS_OFFSET CON7_OFFSET
+#define SPK_AB_OBIAS_MASK 0x0030
+#define SPK_AB_OBIAS_SHIFT 4
+
+#define SPK_MODE_OFFSET CON7_OFFSET
+#define SPK_MODE_MASK 0x0001
+#define SPK_MODE_SHIFT 0
+
+#define SPK_AB_OC_EN_OFFSET CON7_OFFSET
+#define SPK_AB_OC_EN_MASK 0x0100
+#define SPK_AB_OC_EN_SHIFT 8
+
+//ISINK
+#define ISINK_EN_OFFSET CON0_OFFSET
+#define ISINK_EN_MASK 0x0001
+#define ISINK_EN_SHIFT 0
+
+#define ISINK_MODE_OFFSET CON0_OFFSET
+#define ISINK_MODE_MASK 0x0002
+#define ISINK_MODE_SHIFT 1
+
+#define ISINK_STEP_OFFSET CON0_OFFSET
+#define ISINK_STEP_MASK 0x01F0
+#define ISINK_STEP_SHIFT 4
+
+#define ISINK_VREF_CAL_OFFSET CON1_OFFSET
+#define ISINK_VREF_CAL_MASK 0x1F00
+#define ISINK_VREF_CAL_SHIFT 8
+
+
+//BOOST
+#define BOOST_TYPE_OFFSET CON0_OFFSET
+#define BOOST_TYPE_MASK 0x0002
+#define BOOST_TYPE_SHIFT 1
+
+#define BOOST_HW_SEL_OFFSET CON6_OFFSET
+#define BOOST_HW_SEL_MASK 0x0001
+#define BOOST_HW_SEL_SHIFT 0
+
+
+//KPLED
+#define KPLED_EN_OFFSET CON0_OFFSET
+#define KPLED_EN_MASK 0x0001
+#define KPLED_EN_SHIFT 0
+
+#define KPLED_MODE_OFFSET CON0_OFFSET
+#define KPLED_MODE_MASK 0x0002
+#define KPLED_MODE_SHIFT 1
+
+#define KPLED_SEL_OFFSET CON0_OFFSET
+#define KPLED_SEL_MASK 0x0070
+#define KPLED_SEL_SHIFT 4
+
+
+//CHR
+#define CSDAC_EN_OFFSET CON0_OFFSET
+#define CSDAC_EN_MASK 0x0800
+#define CSDAC_EN_SHIFT 11
+
+#define CHR_EN_OFFSET CON0_OFFSET
+#define CHR_EN_MASK 0x1000
+#define CHR_EN_SHIFT 12
+
+#define CHRDET_OFFSET CON0_OFFSET
+#define CHRDET_MASK 0x2000
+#define CHRDET_SHIFT 13
+
+#define VCDT_HV_VTH_OFFSET CON0_OFFSET
+#define VCDT_HV_VTH_MASK 0x00F0
+#define VCDT_HV_VTH_SHIFT 4
+
+#define VCDT_HV_EN_OFFSET CON0_OFFSET
+#define VCDT_HV_EN_MASK 0x0100
+#define VCDT_HV_EN_SHIFT 8
+
+#define VBAT_CV_VTH_OFFSET CON1_OFFSET
+#define VBAT_CV_VTH_MASK 0x001F
+#define VBAT_CV_VTH_SHIFT 0
+
+#define VBAT_CV_EN_OFFSET CON1_OFFSET
+#define VBAT_CV_EN_MASK 0x0100
+#define VBAT_CV_EN_SHIFT 8
+
+#define VBAT_CV_DET_OFFSET CON1_OFFSET
+#define VBAT_CV_DET_MASK 0x4000
+#define VBAT_CV_DET_SHIFT 14
+
+#define CS_VTH_OFFSET CON2_OFFSET
+#define CS_VTH_MASK 0x0700
+#define CS_VTH_SHIFT 8
+
+#define BATON_HT_EN_OFFSET CON3_OFFSET
+#define BATON_HT_EN_MASK 0x0400
+#define BATON_HT_EN_SHIFT 10
+
+#define CSDAC_DLY_OFFSET CON3_OFFSET
+#define CSDAC_DLY_MASK 0x0030
+#define CSDAC_DLY_SHIFT 4
+
+#define CSDAC_STP_OFFSET CON3_OFFSET
+#define CSDAC_STP_MASK 0x0003
+#define CSDAC_STP_SHIFT 0
+
+#define BATON_UNDET_OFFSET CON3_OFFSET
+#define BATON_UNDET_MASK 0x8000
+#define BATON_UNDET_SHIFT 15
+
+#define OTG_BVALID_EN_OFFSET CON5_OFFSET
+#define OTG_BVALID_EN_MASK 0x1000
+#define OTG_BVALID_EN_SHIFT 12
+
+#define CHRWDT_EN_OFFSET CON6_OFFSET
+#define CHRWDT_EN_MASK 0x0010
+#define CHRWDT_EN_SHIFT 4
+
+#define CHRWDT_TD_OFFSET CON6_OFFSET
+#define CHRWDT_TD_MASK 0x000F // TTTTTTTTT
+#define CHRWDT_TD_SHIFT 0
+
+#define CHRWDT_OUT_OFFSET CON7_OFFSET
+#define CHRWDT_OUT_MASK 0x8000
+#define CHRWDT_OTU_SHIFT 15
+
+#define CHRWDT_INT_EN_OFFSET CON7_OFFSET
+#define CHRWDT_INT_EN_MASK 0x0001
+#define CHRWDT_INT_EN_SHIFT 0
+
+#define CHRWDT_FLAG_WR_OFFSET CON7_OFFSET
+#define CHRWDT_FLAG_WR_MASK 0x0002
+#define CHRWDT_FLAG_WR_SHIFT 1
+
+#define ADC_EN_OFFSET CON8_OFFSET
+#define ADC_EN_MASK 0x7000 // All ADC channels are enabled at same time
+#define ADC_EN_SHIFT 12
+
+#define BC11_VREF_VTH_OFFSET CON9_OFFSET
+#define BC11_VREF_VTH_MASK 0x0001
+#define BC11_VREF_VTH_SHIFT 0
+
+#define BC11_CMP_EN_OFFSET CON9_OFFSET
+#define BC11_CMP_EN_MASK 0x0006
+#define BC11_CMP_EN_SHIFT 1
+
+#define BC11_IPD_EN_OFFSET CON9_OFFSET
+#define BC11_IPD_EN_MASK 0x0018
+#define BC11_IPD_EN_SHIFT 3
+
+#define BC11_IPU_EN_OFFSET CON9_OFFSET
+#define BC11_IPU_EN_MASK 0x0060
+#define BC11_IPU_EN_SHIFT 5
+
+#define BC11_BIAS_EN_OFFSET CON9_OFFSET
+#define BC11_BIAS_EN_MASK 0x0080
+#define BC11_BIAS_EN_SHIFT 7
+
+#define BC11_BB_CTRL_OFFSET CON9_OFFSET
+#define BC11_BB_CTRL_MASK 0x0100
+#define BC11_BB_CTRL_SHIFT 8
+
+#define BC11_RST_OFFSET CON9_OFFSET
+#define BC11_RST_MASK 0x0200
+#define BC11_RST_SHIFT 9
+
+#define BC11_VSRC_EN_OFFSET CON9_OFFSET
+#define BC11_VSRC_EN_MASK 0x0C00
+#define BC11_VSRC_EN_SHIFT 10
+
+#define BC11_CMP_OUT_OFFSET CON9_OFFSET
+#define BC11_CMP_OUT_MASK 0x8000
+#define BC11_CMP_OUT_SHIFT 15
+
+
+// STRUP
+// STRUP_XXX CON0
+#define USBDL_EN_OFFSET CON0_OFFSET
+#define USBDL_EN_MASK 0x0010
+#define USBDL_EN_SHIFT 4
+
+// BOOST
+#define BOOST_CKS_PRG_OFFSET CON3_OFFSET
+#define BOOST_CKS_PRG_MASK 0x003F
+#define BOOST_CKS_PRG_SHIFT 0
+
+//MISC
+#define CCI_SRCLKEN_OFFSET CON2_OFFSET
+#define CCI_SRCLKEN_MASK 0x0002
+#define CCI_SRCLKEN_SHIFT 1
+
+#endif // #if defined(PMIC_6251_REG_API)
+
+#endif // #ifndef __PMU6251_HW_H__
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6251_sw.h b/mcu/driver/peripheral/inc/dcl_pmu6251_sw.h
new file mode 100644
index 0000000..ab2353f
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6251_sw.h
@@ -0,0 +1,226 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6251_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMU6251
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DCL_PMU6251_SW_H_STRUCT__
+#define __DCL_PMU6251_SW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6251_REG_API)
+
+/* Charger external interrupt is fixed. */
+
+/* Charger external interrupt is fixed. */
+#define PMU_CHR_EINT_PIN 2
+
+
+/* adc number for measuring VBAT/VISENSE/VCHARGER is fixed internally. */
+
+#define PMU_ADC_VBAT_CH_NUM 0
+#define PMU_ADC_VISENSE_CH_NUM 1
+#define PMU_ADC_VCHARGER_CH_NUM 2
+#define PMU_ADC_VBATTEMP_CH_NUM 3
+
+
+/* adc factor for VBAT/VISENSE/VCHARGER */
+#define PMU_ADC_FACTOR_VBAT 150
+#define PMU_ADC_FACTOR_VISENSE 150
+#if defined(MT6251_S00)
+#define PMU_ADC_FACTOR_VCHARGER 344 // (351/51 * 50)
+#endif //#if defined(MT6251_S00)
+#if defined(MT6251_S01)
+#define PMU_ADC_FACTOR_VCHARGER 473 // (369/39 * 50)
+#endif //#if defined(MT6251_S01)
+#define PMU_ADC_FACTOR_VBATTEMP 100
+
+typedef enum
+{
+ LDO_BUCK_EN,
+ LDO_BUCK_VOL_SEL,
+ LDO_BUCK_OC_AUTO_OFF,
+ LDO_BUCK_STB_EN,
+ LDO_BUCK_ON_SEL,
+ LDO_BUCK_NDIS_EN,
+ LDO_BUCK_OCFB_EN,
+ LDO_CAL,
+ LDO_STB_TD,
+ LDO_OC_TD,
+ BUCK_VFBADJ_SLEEP,
+ BUCK_ICAL_EN,
+ BUCK_CSL,
+ BUCK_STB_TD,
+ BUCK_OC_THD,
+ BUCK_BURST,
+ SPK_EN,
+ SPK_PG_SLEW_I,
+ SPK_OC_EN,
+ SPK_AB_OC_EN,
+ SPK_CCODE,
+ SPK_OSC_ISEL,
+ SPK_NG_DT_DLY,
+ SPK_OCP_BIAS,
+ SPK_OCN_BIAS,
+ SPK_NG_SLEW_DLY,
+ SPK_PG_SLEW_DLY,
+ SPK_AB_OBIAS,
+ SPK_MODE,
+ SPK_VOL,
+ ISINK_EN,
+ ISINK_MODE,
+ ISINK_STEP,
+ ISINK_VREF_CAL,
+ BOOST_TYPE,
+ BOOST_HW_SEL,
+ KPLED_EN,
+ KPLED_MODE,
+ KPLED_SEL,
+ ADC_EN,
+ BATON_UNDET,
+ CSDAC_EN,
+ VBAT_CV_DET,
+ VBAT_CV_EN,
+ VBAT_CV_VTH,
+ CSDAC_DLY,
+ CSDAC_STP,
+ CHR_EN,
+ CHRDET,
+ CHRWDT_TD,
+ CS_VTH,
+ CHRWDT_EN,
+ CHRWDT_INT_EN,
+ VCDT_HV_VTH,
+ BATON_HT_EN,
+ OTG_BVALID_EN,
+ USBDL_EN,
+ CCI_SRCLKEN,
+ VCDT_HV_EN,
+ BOOST_CKS_PRG,
+ BC11_VREF_VTH,
+ BC11_CMP_EN,
+ BC11_IPD_EN,
+ BC11_IPU_EN,
+ BC11_BIAS_EN,
+ BC11_BB_CTRL,
+ BC11_RST,
+ BC11_VSRC_EN,
+ BC11_CMP_OUT,
+ PMU_FLAGS_MAX
+}PMU_FLAGS_LIST_ENUM;
+
+
+
+#define LDO_GROUP (OFFSEL(BUCK_GROUP))
+#define BUCK_GROUP (M(VCORE))
+
+#endif //#if defined(PMIC_6251_REG_API)
+
+#endif //#ifndef __DCL_PMU6251_SW_H_STRUCT__
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6252_hw.h b/mcu/driver/peripheral/inc/dcl_pmu6252_hw.h
new file mode 100644
index 0000000..c197502
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6252_hw.h
@@ -0,0 +1,438 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6251_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for PMIC 6251 driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __PMU6252_HW_H__
+#define __PMU6252_HW_H__
+
+
+#if defined(PMIC_6252_REG_API)
+
+#define PMU_BASE MIXED_base
+#define PMU_END (PMU_BASE+0x1000)
+
+///////////////////////////////////////////////////////////////////////////////
+// LDO group
+#define VRF_CON0 (PMU_BASE + 0x0800)
+#define VTCXO_CON0 (PMU_BASE + 0x0810)
+#define VA_CON0 (PMU_BASE + 0x0820)
+#define VCAMA_CON0 (PMU_BASE + 0x0830)
+#define VCAMD_CON0 (PMU_BASE + 0x0840)
+#define VIO_CON0 (PMU_BASE + 0x0850)
+#define VUSB_CON0 (PMU_BASE + 0x0860)
+#define VSIM_CON0 (PMU_BASE + 0x0880)
+#define VSIM2_CON0 (PMU_BASE + 0x0890)
+#define VRTC_CON0 (PMU_BASE + 0x08A0)
+#define VIBR_CON0 (PMU_BASE + 0x08B0)
+#define VM_CON0 (PMU_BASE + 0x08C0)
+#define VCORE_CON0 (PMU_BASE + 0x08D0)
+
+// iSINK group
+#define ISINK0_CON0 (PMU_BASE + 0x0980)
+#define ISINK1_CON0 (PMU_BASE + 0x0990)
+#define ISINK2_CON0 (PMU_BASE + 0x09A0)
+#define ISINK3_CON0 (PMU_BASE + 0x09B0)
+
+// KPLED group
+#define KPLED_CON0 (PMU_BASE + 0x09C0)
+
+// SPK
+#define SPK_CON0 (PMU_BASE + 0x09D0)
+
+// CHR
+#define CHR_CON0 (PMU_BASE + 0x0A00)
+
+// STARTUP
+#define STRUP_CON0 (PMU_BASE + 0x0900)
+
+// INT EN
+#define INT_EN0 (PMU_BASE + 0x08F0)
+#define INT_EN1 (PMU_BASE + 0x08F4)
+#define INT_CHR_DET_MASK 0x0008
+#define INT_CHR_DET_SHIFT 3
+
+///////////////////////////////////////////////////////////////////////////////
+
+// BC11 VSRC_EN
+#define MT6251_E1_BC11_VSRC_EN_MASK 0x0030
+#define MT6251_E1_BC11_VSRC_EN_SHIFT 4
+
+
+#define CON0_OFFSET 0x00
+#define CON1_OFFSET 0x04
+#define CON2_OFFSET 0x08
+#define CON3_OFFSET 0x0C
+#define CON4_OFFSET 0x10
+#define CON5_OFFSET 0x14
+#define CON6_OFFSET 0x18
+#define CON7_OFFSET 0x1C
+#define CON8_OFFSET 0x20
+#define CON9_OFFSET 0x24
+
+// LDO and BUCK cmds
+#define LDO_BUCK_EN_OFFSET CON0_OFFSET
+#define LDO_BUCK_EN_MASK 0x0001
+#define LDO_BUCK_EN_SHIFT 0
+
+#define LDO_BUCK_RS_OFFSET CON0_OFFSET
+#define LDO_BUCK_RS_MASK 0x0004
+#define LDO_BUCK_RS_SHIFT 2
+
+#define LDO_BUCK_VOL_SEL_OFFSET CON0_OFFSET
+#define LDO_BUCK_VOL_SEL_MASK 0x01F0
+#define LDO_BUCK_VOL_SEL_SHIFT 4
+
+#define LDO_BUCK_OC_AUTO_OFF_OFFSET CON0_OFFSET
+#define LDO_BUCK_OC_AUTO_OFF_MASK 0x1000
+#define LDO_BUCK_OC_AUTO_OFF_SHIFT 12
+
+/*
+#define LDO_BUCK_STB_EN_OFFSET CON0_OFFSET
+#define LDO_BUCK_STB_EN_MASK 0x0800
+#define LDO_BUCK_STB_EN_SHIFT 11
+*/
+
+#define LDO_BUCK_ON_SEL_OFFSET CON0_OFFSET
+#define LDO_BUCK_ON_SEL_MASK 0x0002
+#define LDO_BUCK_ON_SEL_SHIFT 1
+
+
+#define LDO_BUCK_NDIS_EN_OFFSET CON0_OFFSET
+#define LDO_BUCK_NDIS_EN_MASK 0x0400
+#define LDO_BUCK_NDIS_EN_SHIFT 10
+
+/*
+#define LDO_BUCK_OCFB_EN_OFFSET CON0_OFFSET
+#define LDO_BUCK_OCFB_EN_MASK 0x2000
+#define LDO_BUCK_OCFB_EN_SHIFT 13
+*/
+
+// LDO cmds
+#define LDO_CAL_OFFSET CON1_OFFSET
+#define LDO_CAL_MASK 0x01F0
+#define LDO_CAL_SHIFT 4
+
+#define LDO_OC_TD_OFFSET CON2_OFFSET
+#define LDO_OC_TD_MASK 0x0030
+#define LDO_OC_TD_SHIFT 4
+
+#define LDO_STB_TD_OFFSET CON2_OFFSET
+#define LDO_STB_TD_MASK 0x00c0
+#define LDO_STB_TD_SHIFT 6
+
+
+// BUCK cmds
+#define BUCK_VFBADJ_SLEEP_OFFSET CON1_OFFSET
+#define BUCK_VFBADJ_SLEEP_MASK 0x01F0
+#define BUCK_VFBADJ_SLEEP_SHIFT 4
+
+#define BUCK_ICAL_EN_OFFSET CON3_OFFSET
+#define BUCK_ICAL_EN_MASK 0x3000
+#define BUCK_ICAL_EN_SHIFT 12
+
+/*
+#define BUCK_STB_TD_OFFSET CON3_OFFSET
+#define BUCK_STB_TD_MASK 0x00C0
+#define BUCK_STB_TD_SHIFT 6
+
+#define BUCK_OC_THD_OFFSET CON3_OFFSET
+#define BUCK_OC_THD_MASK 0x0300
+#define BUCK_OC_THD_SHIFT 8
+
+#define BUCK_CSL_OFFSET CON5_OFFSET
+#define BUCK_CSL_MASK 0x0700
+#define BUCK_CSL_SHIFT 8
+
+#define BUCK_BURST_OFFSET CON5_OFFSET
+#define BUCK_BURST_MASK 0x3000
+#define BUCK_BURST_SHIFT 12
+*/
+
+// SPK
+#define SPK_EN_OFFSET CON0_OFFSET
+#define SPK_EN_MASK 0x0001
+#define SPK_EN_SHIFT 0
+
+#define SPK_VOL_OFFSET CON0_OFFSET
+#define SPK_VOL_MASK 0x001E
+#define SPK_VOL_SHIFT 1
+
+#define SPK_OC_EN_OFFSET CON0_OFFSET
+#define SPK_OC_EN_MASK 0x0040
+#define SPK_OC_EN_SHIFT 6
+
+#define SPK_OC_THD_OFFSET CON1_OFFSET
+#define SPK_OC_THD_MASK 0x0003 // OC_TRG
+#define SPK_OC_THD_SHIFT 0
+
+#define SPK_OC_WND_OFFSET CON1_OFFSET
+#define SPK_OC_WND_MASK 0x000C
+#define SPK_OC_WND_SHIFT 2
+
+//ISINK
+#define ISINK_EN_OFFSET CON0_OFFSET
+#define ISINK_EN_MASK 0x0001
+#define ISINK_EN_SHIFT 0
+
+#define ISINK_MODE_OFFSET CON0_OFFSET
+#define ISINK_MODE_MASK 0x0002
+#define ISINK_MODE_SHIFT 1
+
+#define ISINK_STEP_OFFSET CON0_OFFSET
+#define ISINK_STEP_MASK 0x01F0
+#define ISINK_STEP_SHIFT 4
+
+#define ISINK_VREF_CAL_OFFSET CON1_OFFSET
+#define ISINK_VREF_CAL_MASK 0x1F00
+#define ISINK_VREF_CAL_SHIFT 8
+
+/*
+//BOOST
+#define BOOST_TYPE_OFFSET CON0_OFFSET
+#define BOOST_TYPE_MASK 0x0002
+#define BOOST_TYPE_SHIFT 1
+
+#define BOOST_HW_SEL_OFFSET CON6_OFFSET
+#define BOOST_HW_SEL_MASK 0x0001
+#define BOOST_HW_SEL_SHIFT 0
+*/
+
+//KPLED
+#define KPLED_EN_OFFSET CON0_OFFSET
+#define KPLED_EN_MASK 0x0001
+#define KPLED_EN_SHIFT 0
+
+#define KPLED_MODE_OFFSET CON0_OFFSET
+#define KPLED_MODE_MASK 0x0002
+#define KPLED_MODE_SHIFT 1
+
+#define KPLED_SEL_OFFSET CON0_OFFSET
+#define KPLED_SEL_MASK 0x0070
+#define KPLED_SEL_SHIFT 4
+
+
+//CHR
+#define CSDAC_EN_OFFSET CON0_OFFSET
+#define CSDAC_EN_MASK 0x0800
+#define CSDAC_EN_SHIFT 11
+
+#define CHR_EN_OFFSET CON0_OFFSET
+#define CHR_EN_MASK 0x1000
+#define CHR_EN_SHIFT 12
+
+#define CHRDET_OFFSET CON0_OFFSET
+#define CHRDET_MASK 0x2000
+#define CHRDET_SHIFT 13
+
+#define VCDT_HV_VTH_OFFSET CON0_OFFSET
+#define VCDT_HV_VTH_MASK 0x00F0
+#define VCDT_HV_VTH_SHIFT 4
+
+#define VCDT_HV_EN_OFFSET CON0_OFFSET
+#define VCDT_HV_EN_MASK 0x0100
+#define VCDT_HV_EN_SHIFT 8
+
+#define VBAT_CV_VTH_OFFSET CON1_OFFSET
+#define VBAT_CV_VTH_MASK 0x001F
+#define VBAT_CV_VTH_SHIFT 0
+
+#define VBAT_CV_EN_OFFSET CON1_OFFSET
+#define VBAT_CV_EN_MASK 0x0100
+#define VBAT_CV_EN_SHIFT 8
+
+#define VBAT_CV_DET_OFFSET CON1_OFFSET
+#define VBAT_CV_DET_MASK 0x4000
+#define VBAT_CV_DET_SHIFT 14
+
+#define CS_VTH_OFFSET CON2_OFFSET
+#define CS_VTH_MASK 0x0700
+#define CS_VTH_SHIFT 8
+
+#define BATON_HT_EN_OFFSET CON3_OFFSET
+#define BATON_HT_EN_MASK 0x0400
+#define BATON_HT_EN_SHIFT 10
+
+#define CSDAC_DLY_OFFSET CON3_OFFSET
+#define CSDAC_DLY_MASK 0x0030
+#define CSDAC_DLY_SHIFT 4
+
+#define CSDAC_STP_OFFSET CON3_OFFSET
+#define CSDAC_STP_MASK 0x0003
+#define CSDAC_STP_SHIFT 0
+
+#define BATON_UNDET_OFFSET CON3_OFFSET
+#define BATON_UNDET_MASK 0x8000
+#define BATON_UNDET_SHIFT 15
+
+#define OTG_BVALID_EN_OFFSET CON5_OFFSET
+#define OTG_BVALID_EN_MASK 0x1000
+#define OTG_BVALID_EN_SHIFT 12
+
+#define CHRWDT_EN_OFFSET CON6_OFFSET
+#define CHRWDT_EN_MASK 0x0010
+#define CHRWDT_EN_SHIFT 4
+
+#define CHRWDT_TD_OFFSET CON6_OFFSET
+#define CHRWDT_TD_MASK 0x000F // TTTTTTTTT
+#define CHRWDT_TD_SHIFT 0
+
+#define CHRWDT_OUT_OFFSET CON7_OFFSET
+#define CHRWDT_OUT_MASK 0x8000
+#define CHRWDT_OTU_SHIFT 15
+
+#define CHRWDT_INT_EN_OFFSET CON7_OFFSET
+#define CHRWDT_INT_EN_MASK 0x0001
+#define CHRWDT_INT_EN_SHIFT 0
+
+#define CHRWDT_FLAG_WR_OFFSET CON7_OFFSET
+#define CHRWDT_FLAG_WR_MASK 0x0002
+#define CHRWDT_FLAG_WR_SHIFT 1
+
+#define ADC_EN_OFFSET CON8_OFFSET
+#define ADC_EN_MASK 0x7000 // All ADC channels are enabled at same time
+#define ADC_EN_SHIFT 12
+
+#define BC11_VREF_VTH_OFFSET CON9_OFFSET
+#define BC11_VREF_VTH_MASK 0x0001
+#define BC11_VREF_VTH_SHIFT 0
+
+#define BC11_CMP_EN_OFFSET CON9_OFFSET
+#define BC11_CMP_EN_MASK 0x0006
+#define BC11_CMP_EN_SHIFT 1
+
+#define BC11_IPD_EN_OFFSET CON9_OFFSET
+#define BC11_IPD_EN_MASK 0x0018
+#define BC11_IPD_EN_SHIFT 3
+
+#define BC11_IPU_EN_OFFSET CON9_OFFSET
+#define BC11_IPU_EN_MASK 0x0060
+#define BC11_IPU_EN_SHIFT 5
+
+#define BC11_BIAS_EN_OFFSET CON9_OFFSET
+#define BC11_BIAS_EN_MASK 0x0080
+#define BC11_BIAS_EN_SHIFT 7
+
+#define BC11_BB_CTRL_OFFSET CON9_OFFSET
+#define BC11_BB_CTRL_MASK 0x0100
+#define BC11_BB_CTRL_SHIFT 8
+
+#define BC11_RST_OFFSET CON9_OFFSET
+#define BC11_RST_MASK 0x0200
+#define BC11_RST_SHIFT 9
+
+#define BC11_VSRC_EN_OFFSET CON9_OFFSET
+#define BC11_VSRC_EN_MASK 0x0C00
+#define BC11_VSRC_EN_SHIFT 10
+
+#define BC11_CMP_OUT_OFFSET CON9_OFFSET
+#define BC11_CMP_OUT_MASK 0x8000
+#define BC11_CMP_OUT_SHIFT 15
+
+
+// STRUP
+// STRUP_XXX CON0
+#define USBDL_EN_OFFSET CON0_OFFSET
+#define USBDL_EN_MASK 0x0010
+#define USBDL_EN_SHIFT 4
+
+/*
+// BOOST
+#define BOOST_CKS_PRG_OFFSET CON3_OFFSET
+#define BOOST_CKS_PRG_MASK 0x003F
+#define BOOST_CKS_PRG_SHIFT 0
+*/
+
+//MISC
+#define CCI_SRCLKEN_OFFSET CON2_OFFSET
+#define CCI_SRCLKEN_MASK 0x0002
+#define CCI_SRCLKEN_SHIFT 1
+
+#endif // #if defined(PMIC_6252_REG_API)
+
+#endif // #ifndef __PMU6252_HW_H__
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6252_sw.h b/mcu/driver/peripheral/inc/dcl_pmu6252_sw.h
new file mode 100644
index 0000000..c25d38a
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6252_sw.h
@@ -0,0 +1,201 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6252_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMU6252
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DCL_PMU6252_SW_H_STRUCT__
+#define __DCL_PMU6252_SW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6252_REG_API)
+
+
+/* Charger external interrupt is fixed. */
+#define PMU_CHR_EINT_PIN 7
+
+
+/* adc number for measuring VBAT/VISENSE/VCHARGER is fixed internally. */
+
+#define PMU_ADC_VBAT_CH_NUM 0
+#define PMU_ADC_VISENSE_CH_NUM 1
+#define PMU_ADC_VCHARGER_CH_NUM 2
+
+
+/* adc factor for VBAT/VISENSE/VCHARGER */
+#define PMU_ADC_FACTOR_VBAT 100
+#define PMU_ADC_FACTOR_VISENSE 100
+#define PMU_ADC_FACTOR_VCHARGER 473 // 369/39 * 50
+
+typedef enum
+{
+ LDO_BUCK_EN,
+ LDO_BUCK_VOL_SEL,
+ LDO_BUCK_RS,
+ LDO_BUCK_OC_AUTO_OFF,
+ //LDO_BUCK_STB_EN,
+ LDO_BUCK_ON_SEL,
+ LDO_BUCK_NDIS_EN,
+ //LDO_BUCK_OCFB_EN,
+ LDO_CAL,
+ LDO_STB_TD,
+ LDO_OC_TD,
+ BUCK_VFBADJ_SLEEP,
+ BUCK_ICAL_EN,
+ //BUCK_CSL,
+ //BUCK_STB_TD,
+ //BUCK_OC_THD,
+ //BUCK_BURST,
+ SPK_EN,
+ SPK_OC_EN,
+ SPK_OC_THD,
+ SPK_OC_WND,
+ SPK_VOL,
+ ISINK_EN,
+ ISINK_MODE,
+ ISINK_STEP,
+ ISINK_VREF_CAL,
+ //BOOST_TYPE,
+ //BOOST_HW_SEL,
+ KPLED_EN,
+ KPLED_MODE,
+ KPLED_SEL,
+ ADC_EN,
+ BATON_UNDET,
+ CSDAC_EN,
+ VBAT_CV_DET,
+ VBAT_CV_EN,
+ VBAT_CV_VTH,
+ CSDAC_DLY,
+ CSDAC_STP,
+ CHR_EN,
+ CHRDET,
+ CHRWDT_TD,
+ CS_VTH,
+ CHRWDT_EN,
+ CHRWDT_INT_EN,
+ VCDT_HV_VTH,
+ BATON_HT_EN,
+ OTG_BVALID_EN,
+ USBDL_EN,
+ CCI_SRCLKEN,
+ VCDT_HV_EN,
+ //BOOST_CKS_PRG,
+ BC11_VREF_VTH,
+ BC11_CMP_EN,
+ BC11_IPD_EN,
+ BC11_IPU_EN,
+ BC11_BIAS_EN,
+ BC11_BB_CTRL,
+ BC11_RST,
+ BC11_VSRC_EN,
+ BC11_CMP_OUT,
+ PMU_FLAGS_MAX
+}PMU_FLAGS_LIST_ENUM;
+
+#define LDO_GROUP (OFFSEL(BUCK_GROUP))
+#define BUCK_GROUP (M(VCORE))
+
+#endif //#if defined(PMIC_6252_REG_API)
+
+#endif //#ifndef __DCL_PMU6252_SW_H_STRUCT__
+
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6253_hw.h b/mcu/driver/peripheral/inc/dcl_pmu6253_hw.h
new file mode 100644
index 0000000..63f7b6e
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6253_hw.h
@@ -0,0 +1,664 @@
+
+
+#ifndef __DCL_PMIC6253_HW_H_STRUCT__
+#define __DCL_PMIC6253_HW_H_STRUCT__
+
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6253_REG_API)
+
+#define PMU_BASE MIXED_base
+#define PMU_END (PMU_BASE+0x1000)
+
+// =====================================================================================
+#define PMIC_VRF_CON (PMU_BASE+0x800)
+#define PMIC_VIO_CON (PMU_BASE+0x804)
+#define PMIC_VM_CON (PMU_BASE+0x808)
+#define PMIC_VRTC_CON (PMU_BASE+0x80C)
+#define PMIC_VTCXO_CON (PMU_BASE+0x810)
+#define PMIC_VA_CON (PMU_BASE+0x814)
+#define PMIC_VSIM_CON (PMU_BASE+0x818)
+#define PMIC_VSIM2_CON (PMU_BASE+0x81C)
+#define PMIC_VUSB_CON (PMU_BASE+0x820)
+#if defined(__DRV_PMU53_SPEC_V1__)
+#define PMIC_VBT_CON (PMU_BASE+0x824)
+#else // #if defined(__DRV_PMU53_SPEC_V1__)
+#define PMIC_DRIVER_CON4 (PMU_BASE+0x824)
+#endif // #if defined(__DRV_PMU53_SPEC_V1__)
+#define PMIC_VCAMD_CON (PMU_BASE+0x828)
+#define PMIC_VCAMA_CON (PMU_BASE+0x82C)
+#define PMIC_GPIO_CON (PMU_BASE+0x834)
+#define PMIC_VCORE_CON (PMU_BASE+0x840)
+#define PMIC_VCORE_CON1 (PMU_BASE+0x844)
+#define PMIC_VCORE_CON2 (PMU_BASE+0x848)
+#define PMIC_VCORE_CON3 (PMU_BASE+0x84C)
+#define PMIC_VCORE_CON5 (PMU_BASE+0x854)
+#define PMIC_STARTUP_CON0 (PMU_BASE+0x860)
+#define PMIC_STARTUP_CON1 (PMU_BASE+0x864)
+#define PMIC_CHR_CON0 (PMU_BASE+0x870)
+#define PMIC_CHR_CON1 (PMU_BASE+0x874)
+#define PMIC_CHR_CON2 (PMU_BASE+0x878)
+#define PMIC_CHR_CON3 (PMU_BASE+0x87C)
+//#define PMIC_CHR_CON4 (PMU_BASE+0x8F0) ==> In 0x8F0
+//#define PMIC_CHR_CON5 (PMU_BASE+0x8F4) ==> In 0x8F4
+#define PMIC_DRIVER_CON0 (PMU_BASE+0x880)
+#define PMIC_DRIVER_CON1 (PMU_BASE+0x884)
+#define PMIC_DRIVER_CON2 (PMU_BASE+0x888)
+#define PMIC_DRIVER_CON3 (PMU_BASE+0x88C)
+#if defined(__DRV_PMU53_SPEC_V1__)
+#define PMIC_DRIVER_CON4 (PMU_BASE+0x890)
+#else // #if defined(__DRV_PMU53_SPEC_V1__)
+#define PMIC_VBT_CON (PMU_BASE+0x890)
+#endif // #if defined(__DRV_PMU53_SPEC_V1__)
+#define PMIC_BOOST_CON0 (PMU_BASE+0x8A0)
+#define PMIC_BOOST_CON1 (PMU_BASE+0x8A4)
+#define PMIC_BOOST_CON2 (PMU_BASE+0x8A8)
+#define PMIC_CLASSD_CON0 (PMU_BASE+0x8B0)
+#define PMIC_CLASSD_CON1 (PMU_BASE+0x8B4)
+#define PMIC_CLASSD_CON2 (PMU_BASE+0x8B8)
+#define PMIC_CLASSD_CON3 (PMU_BASE+0x8BC)
+#define PMIC_TEST_CON2 (PMU_BASE+0x8C8)
+#define PMIC_OC_CON0 (PMU_BASE+0x8D0)
+#define PMIC_OC_CON1 (PMU_BASE+0x8D4)
+#define PMIC_OC_CON2 (PMU_BASE+0x8D8)
+#define PMIC_OC_CON3 (PMU_BASE+0x8DC)
+#define PMIC_OC_CON4 (PMU_BASE+0x8E0)
+#define PMIC_OC_CON5 (PMU_BASE+0x8E4)
+#define PMIC_CHR_CON4 (PMU_BASE+0x8F0)
+#define PMIC_CHR_CON5 (PMU_BASE+0x8F4)
+
+// =====================================================================================
+// (0x800) VRF CON
+#define VRF_EN_MASK 0x0001
+#define VRF_EN_SHIFT 0
+#define VRF_CAL_MASK 0x00F0
+#define VRF_CAL_SHIFT 4
+#define VRF_ON_SEL_MASK 0x0400
+#define VRF_ON_SEL_SHIFT 10
+#define VRF_OCFB_EN_MASK 0x1000
+#define VRF_OCFB_EN_SHIFT 12
+#define VRF_STATUS_MASK 0x8000
+#define VRF_STATUS_SHIFT 15
+
+// (0x804) VIO CON
+#define VIO_CAL_MASK 0x00F0
+#define VIO_CAL_SHIFT 4
+#define VIO_VD_SENSE_MASK 0x0200
+#define VIO_VD_SENSE_SHIFT 9
+#define VIO_OCFB_EN_MASK 0x1000
+#define VIO_OCFB_EN_SHIFT 12
+#define VIO_STATUS_MASK 0x8000
+#define VIO_STATUS_SHIFT 15
+
+// (0x808) VM CON
+#define VM_CAL_MASK 0x00F0
+#define VM_CAL_SHIFT 4
+#define VM_VD_SENSE_MASK 0x0200
+#define VM_VD_SENSE_SHIFT 9
+#define VM_OCFB_EN_MASK 0x1000
+#define VM_OCFB_EN_SHIFT 12
+#define VM_STATUS_MASK 0x8000
+#define VM_STATUS_SHIFT 15
+
+// (0x80C) VRTC CON
+#define VRTC_CAL_MASK 0x00F0
+#define VRTC_CAL_SHIFT 4
+#define VRTC_STATUS_MASK 0x8000
+#define VRTC_STATUS_SHIFT 15
+
+// (0x810) VTCXO CON
+#define VTCXO_EN_MASK 0x0001
+#define VTCXO_EN_SHIFT 0
+#define VTCXO_CAL_MASK 0x00F0
+#define VTCXO_CAL_SHIFT 4
+#define VTCXO_ON_SEL_MASK 0x0400
+#define VTCXO_ON_SEL_SHIFT 10
+#define VTCXO_CCI_SRCLKEN_MASK 0x0800
+#define VTCXO_CCI_SRCLKEN_SHIFT 11
+#define VTCXO_OCFB_EN_MASK 0x1000
+#define VTCXO_OCFB_EN_SHIFT 12
+#define VTCXO_STATUS_MASK 0x8000
+#define VTCXO_STATUS_SHIFT 15
+
+// (0x814) VA CON
+#define VA_CAL_MASK 0x00F0
+#define VA_CAL_SHIFT 4
+#define VA_VD_SENSE_MASK 0x0200
+#define VA_VD_SENSE_SHIFT 9
+#define VA_ON_SEL_MASK 0x0400
+#define VA_ON_SEL_SHIFT 10
+#define VA_OCFB_EN_MASK 0x1000
+#define VA_OCFB_EN_SHIFT 12
+#define VA_STATUS_MASK 0x8000
+#define VA_STATUS_SHIFT 15
+
+// (0x818) VSIM CON
+#define VSIM_CCI_EN_MASK 0x0001
+#define VSIM_CCI_EN_SHIFT 0
+#define VSIM_CAL_MASK 0x00F0
+#define VSIM_CAL_SHIFT 4
+#define VSIM_DATAL_MASK 0x0200
+#define VSIM_DATAL_SHIFT 9
+#define VSIM_CCI_SEL_MASK 0x0400
+#define VSIM_CCI_SEL_SHIFT 10
+#define VSIM_CCI_PWR_SAVING_MASK 0x0800
+#define VSIM_CCI_PWR_SAVING_SHIFT 11
+#define VSIM_OCFB_EN_MASK 0x1000
+#define VSIM_OCFB_EN_SHIFT 12
+#define VSIM_STATUS_MASK 0x8000
+#define VSIM_STATUS_SHIFT 15
+
+// (0x81C) VSIM2 CON
+#define VSIM2_CCI_EN_MASK 0x0001
+#define VSIM2_CCI_EN_SHIFT 0
+#define VSIM2_CAL_MASK 0x00F0
+#define VSIM2_CAL_SHIFT 4
+#define VSIM2_DATAL_MASK 0x0200
+#define VSIM2_DATAL_SHIFT 9
+#define VSIM2_SEL_MASK 0x0400
+#define VSIM2_SEL_SHIFT 10
+#define VSIM2_STATUS_MASK 0x8000
+#define VSIM2_STATUS_SHIFT 15
+
+// (0x820) VUSB CON
+#define VUSB_EN_MASK 0x0001
+#define VUSB_EN_SHIFT 0
+#define VUSB_CAL_MASK 0x00F0
+#define VUSB_CAL_SHIFT 4
+#define VUSB_OCFB_EN_MASK 0x1000
+#define VUSB_OCFB_EN_SHIFT 12
+#define VUSB_STATUS_MASK 0x8000
+#define VUSB_STATUS_SHIFT 15
+
+#if defined(__DRV_PMU53_SPEC_V1__)
+
+// (0x824) VBT CON
+#define VBT_EN_MASK 0x0001
+#define VBT_EN_SHIFT 0
+#define VBT_CAL_MASK 0x00F0
+#define VBT_CAL_SHIFT 4
+#define VBT_SEL_MASK 0x0400
+#define VBT_SEL_SHIFT 10
+#define VBT_OCFB_EN_MASK 0x1000
+#define VBT_OCFB_EN_SHIFT 12
+#define VBT_STATUS_MASK 0x8000
+#define VBT_STATUS_SHIFT 15
+
+#else // #if defined(__DRV_PMU53_SPEC_V1__)
+
+// (0x824) PMIC_DRIVER_CON4
+#define CCI_VIBR_EN_MASK 0x0001
+#define CCI_VIBR_EN_SHIFT 0
+#define VIBR_CAL_MASK 0x00F0
+#define VIBR_CAL_SHIFT 4
+#define VIBR_SEL_MASK 0x0400
+#define VIBR_SEL_SHIFT 10
+#define VIBR_OCFB_EN_MASK 0x1000
+#define VIBR_OCFB_EN_SHIFT 12
+#define VIBR_STATUS_MASK 0x8000
+#define VIBR_STATUS_SHIFT 15
+
+#endif // #if defined(__DRV_PMU53_SPEC_V1__)
+
+// (0x828) VCAMD CON
+#define VCAMD_EN_MASK 0x0001
+#define VCAMD_EN_SHIFT 0
+#define VCAMD_CAL_MASK 0x00F0
+#define VCAMD_CAL_SHIFT 4
+#define VCAMD_SEL_MASK 0x0C00
+#define VCAMD_SEL_SHIFT 10
+#define VCAMD_OCFB_EN_MASK 0x1000
+#define VCAMD_OCFB_EN_SHIFT 12
+#define VCAMD_STATUS_MASK 0x8000
+#define VCAMD_STATUS_SHIFT 15
+
+// (0x82C) VCAMA CON
+#define VCAMA_EN_MASK 0x0001
+#define VCAMA_EN_SHIFT 0
+#define VCAMA_CAL_MASK 0x00F0
+#define VCAMA_CAL_SHIFT 4
+#define VCAMA_SEL_MASK 0x0C00
+#define VCAMA_SEL_SHIFT 10
+#define VCAMA_OCFB_EN_MASK 0x1000
+#define VCAMA_OCFB_EN_SHIFT 12
+#define VCAMA_STATUS_MASK 0x8000
+#define VCAMA_STATUS_SHIFT 15
+
+// (0x834) GPIO CON
+#define GPIO_DRV_MASK 0x0100
+#define GPIO_DRV_SHIFT 8
+#define CCI_MTV_EN_MASK 0x0200
+#define CCI_MTV_EN_SHIFT 9
+
+// (0x840) VCORE CON
+#define VCORE_EN_FORCE_MASK 0x0002
+#define VCORE_EN_FORCE_SHIFT 1
+#define VCORE_CAL_MASK 0x00F0
+#define VCORE_CAL_SHIFT 4
+#define VCORE_VD_SENSE_MASK 0x0200
+#define VCORE_VD_SENSE_SHIFT 9
+#define VCORE_STATUS_MASK 0x8000
+#define VCORE_STATUS_SHIFT 15
+
+// (0x844) VCORE CON1
+#define VCORE_MODE_SET_MASK 0x0001
+#define VCORE_MODE_SET_SHIFT 0
+#define VCORE_ADC_IN_EDGE_MASK 0x0002
+#define VCORE_ADC_IN_EDGE_SHIFT 1
+#define VCORE_FAST_SLOW_MASK 0x0004
+#define VCORE_FAST_SLOW_SHIFT 2
+#define VCORE_PWMB_MASK 0x0008
+#define VCORE_PWMB_SHIFT 3
+#define VCORE_ACC_OUT_INIT_MASK 0x00F0
+#define VCORE_ACC_OUT_INIT_SHIFT 4
+
+// (0x848) VCORE CON2
+#define VCORE_VOLSEL_MASK 0x4000
+#define VCORE_VOLSEL_SHIFT 14
+#define VCORE_FBEN_MASK 0x8000
+#define VCORE_FBEN_SHIFT 15
+
+
+// (0x84C) VCORE CON3
+#define VCORE_CCI_VFBADJ_MASK 0x000F
+#define VCORE_CCI_VFBADJ_SHIFT 0
+#define VCORE_DIRECT_CTRL_EN_MASK 0x0010
+#define VCORE_DIRECT_CTRL_EN_SHIFT 4
+#define VCORE_DCVCKSEL_MASK 0x0020
+#define VCORE_DCVCKSEL_SHIFT 5
+#define VCORE_MODEEN_MASK 0x1800
+#define VCORE_MODEEN_SHIFT 11
+#define VCORE_MODECMP_MASK 0x2000
+#define VCORE_MODECMP_SHIFT 13
+#define VCORE_MODESEL1A_MASK 0x4000
+#define VCORE_MODESEL1A_SHIFT 14
+
+// (0x854) VCORE CON5
+#define VCORE_CCI_VFBADJ_SLP_MASK 0x000F
+#define VCORE_CCI_VFBADJ_SLP_SHIFT 0
+#define VCORE_CLK_SRC_SEL_MASK 0x0010
+#define VCORE_CLK_SRC_SEL_SHIFT 4
+
+// (0x860) STARTUP CON0
+#define UV_SEL_MASK 0x0003
+#define UV_SEL_SHIFT 0
+#define PWRKEY_VCORE_MASK 0x4000
+#define PWRKEY_VCORE_SHIFT 14
+#define PWRKEY_DEB_MASK 0x8000
+#define PWRKEY_DEB_SHIFT 15
+
+// (0x864) STARTUP CON1
+#define THR_SEL_MASK 0x0018
+#define THR_SEL_SHIFT 3
+
+// (0x870) CHR CON0
+#define CHR_EN_MASK 0x0001
+#define CHR_EN_SHIFT 0
+#define CHOFST_MASK 0x000E
+#define CHOFST_SHIFT 1
+#define CHR_CC_CURRENT_MASK 0x00F0
+#define CHR_CC_CURRENT_SHIFT 4
+#define CHRON_FORCE_MASK 0x0100
+#define CHRON_FORCE_SHIFT 8
+#define CV_RT_MASK 0x0600
+#define CV_RT_SHIFT 9
+#define CV_TUNE_MASK 0x3800
+#define CV_TUNE_SHIFT 11
+
+// (0x874) CHR CON1
+#define CAL_PRE_CC_MASK 0x0003
+#define CAL_PRE_CC_SHIFT 0
+#define PS_SEL_MASK 0x0040
+#define PS_SEL_SHIFT 6
+#define PS_SET_MASK 0x0080
+#define PS_SET_SHIFT 7
+#define CHROV_SEL_MASK 0x6000
+#define CHROV_SEL_SHIFT 13
+
+// (0x878) CHR CON2
+// We use CHR_RSV[0] as CV trim extra bit, the bit is the extension of CV_RT
+// But only control in CV_TRIM_CALIBRATION process
+#define CV_TRIM_EXTRA_MASK 0x0001
+#define CV_TRIM_EXTRA_SHIFT 0
+#define OVP_MASK 0x0400
+#define OVP_SHIFT 10
+#define CHRDET_MASK 0x0800
+#define CHRDET_SHIFT 11
+#define BAT_ON_MASK 0x1000
+#define BAT_ON_SHIFT 12
+#define BAD_BATT_MASK 0x2000
+#define BAD_BATT_SHIFT 13
+#define CV_MASK 0x4000
+#define CV_SHIFT 14
+
+// (0x87C) CHR CON3
+#define WDTIMER_TD_MASK 0x0003
+#define WDTIMER_TD_SHIFT 0
+#define WDTIMER_EN_MASK 0x0004
+#define WDTIMER_EN_SHIFT 2
+
+// (0x8F0) CHR CON4 ==> Refer 0x8F0
+#define WDTIMER_INT_EN_MASK 0x0001
+#define WDTIMER_INT_EN_SHIFT 0
+#define WDTIMER_FLAG_MASK 0x0002
+#define WDTIMER_FLAG_SHIFT 1
+#define WDTIMER_CNT_19_16_MASK 0xF000
+#define WDTIMER_CNT_19_16_SHIFT 12
+
+// (0x8F4) CHR CON5 ==> Refer 0x8F4
+#define WDTIMER_CNT_15_00_MASK 0xFFFF
+#define WDTIMER_CNT_15_00_SHIFT 0
+
+
+// (0x880) DRIVER CON0
+#define ISINKS_EN_MASK 0x0001
+#define ISINKS_EN_SHIFT 0
+#define ISINKS_FORCES_OFF_MASK 0x0002
+#define ISINKS_FORCES_OFF_SHIFT 1
+#define KPLED_TYPE_MASK 0x0004
+#define KPLED_TYPE_SHIFT 2
+#define CCI_KPLED_EN_MASK 0x0008
+#define CCI_KPLED_EN_SHIFT 3
+#define KPLED_FORCE_OFF_MASK 0x0010
+#define KPLED_FORCE_OFF_SHIFT 4
+#define KPLED_SEL_MASK 0x00E0
+#define KPLED_SEL_SHIFT 5
+#define ISINK1_STATUS_MASK 0x0800
+#define ISINK1_STATUS_SHIFT 11
+#define ISINK2_STATUS_MASK 0x1000
+#define ISINK2_STATUS_SHIFT 12
+#define ISINK3_STATUS_MASK 0x2000
+#define ISINK3_STATUS_SHIFT 13
+#define ISINK4_STATUS_MASK 0x4000
+#define ISINK4_STATUS_SHIFT 14
+#define KPLED_STATUS_MASK 0x8000
+#define KPLED_STATUS_SHIFT 15
+
+// (0x884) DRIVER CON1
+#define ISINKS_DIMM_MASK 0x001F
+#define ISINKS_DIMM_SHIFT 0
+#define ISINKS_CHSEL_MASK 0x0F00
+#define ISINKS_CHSEL_SHIFT 8
+
+// (0x888) DRIVER CON2
+#define ISINKS_IRSET_CAL_MASK 0x001F
+#define ISINKS_IRSET_CAL_SHIFT 0
+#define ISINKS_VLED_STEP_MASK 0x00C0
+#define ISINKS_VLED_STEP_SHIFT 6
+
+// (0x88C) DRIVER CON3
+#define VBL_EN_MASK 0x0001
+#define VBL_EN_SHIFT 0
+#define VBOOST_EN_MASK 0x0002
+#define VBOOST_EN_SHIFT 1
+#define BL_VGEN_FORCEON_MASK 0x0004
+#define BL_VGEN_FORCEON_SHIFT 2
+#define BL_MODE_MASK 0x0010
+#define BL_MODE_SHIFT 4
+#define BL_DIMM_DUTY_MASK 0x1F00
+#define BL_DIMM_DUTY_SHIFT 8
+
+#if defined(__DRV_PMU53_SPEC_V1__)
+
+// (0x890) DRIVER CON4
+#define CCI_VIBR_EN_MASK 0x0001
+#define CCI_VIBR_EN_SHIFT 0
+#define VIBR_SEL_MASK 0x000C
+#define VIBR_SEL_SHIFT 2
+#define VIBR_CAL_MASK 0x00F0
+#define VIBR_CAL_SHIFT 4
+#define VIBR_OCFB_EN_MASK 0x1000
+#define VIBR_OCFB_EN_SHIFT 12
+#define VIBR_STATUS_MASK 0x8000
+#define VIBR_STATUS_SHIFT 15
+
+#else // #if defined(__DRV_PMU53_SPEC_V1__)
+
+// (0x890) VBT CON ==> VBT move to 0x890
+#define VBT_EN_MASK 0x0001
+#define VBT_EN_SHIFT 0
+#define VBT_SEL_MASK 0x000C
+#define VBT_SEL_SHIFT 2
+#define VBT_CAL_MASK 0x00F0
+#define VBT_CAL_SHIFT 4
+#define VBT_OCFB_EN_MASK 0x1000
+#define VBT_OCFB_EN_SHIFT 12
+#define VBT_STATUS_MASK 0x8000
+#define VBT_STATUS_SHIFT 15
+
+#endif // #if defined(__DRV_PMU53_SPEC_V1__)
+
+// (0x8A0) BOOST CON0
+#define VBOOST_SYNC_EN_MASK 0x0001
+#define VBOOST_SYNC_EN_SHIFT 0
+#define VBOOST_SS_SPEED_MASK 0x0002
+#define VBOOST_SS_SPEED_SHIFT 1
+#define VBOOST_TUNE_MASK 0x00F0
+#define VBOOST_TUNE_SHIFT 4
+#define VBOOST_CAL_MASK 0x0F00
+#define VBOOST_CAL_SHIFT 8
+#define VBOOST_TRK_STATUS_MASK 0x4000
+#define VBOOST_TRK_STATUS_SHIFT 14
+#define VBOOST_STATUS_MASK 0x8000
+#define VBOOST_STATUS_SHIFT 15
+
+// (0x8A4) BOOST CON1
+#define VBOOST_ISNS_CAL_MASK 0x0007
+#define VBOOST_ISNS_CAL_SHIFT 0
+
+// (0x8A8) BOOST CON2
+#define VBOOST_FORCEON_CLK_MASK 0x0001
+#define VBOOST_FORCEON_CLK_SHIFT 0
+#define VBOOST_DISCLK_MASK 0x0002
+#define VBOOST_DISCLK_SHIFT 1
+#define VBOOST_I_SINK_CURRECT_MATCH 0x0009
+
+
+// (0x8B0) CLASSD CON0
+#define SPK_EN_MASK 0x0001
+#define SPK_EN_SHIFT 0
+#define SPK_RST_MASK 0x0002
+#define SPK_RST_SHIFT 1
+#define SPK_EMODE_MASK 0x0004
+#define SPK_EMODE_SHIFT 2
+#define SPK_MODE_MASK 0x0008
+#define SPK_MODE_SHIFT 3
+#define SPKAB_FLOAT_MASK 0x0010
+#define SPKAB_FLOAT_SHIFT 4
+#define SPKAB_SENDED_MASK 0x0020
+#define SPKAB_SENDED_SHIFT 5
+#define SPKAB_OC_EN_MASK 0x0040
+#define SPKAB_OC_EN_SHIFT 6
+#define SPKAB_DEPOP_EN_MASK 0x0080
+#define SPKAB_DEPOP_EN_SHIFT 7
+#define SPKAB_OBIAS_MASK 0x0300
+#define SPKAB_OBIAS_SHIFT 8
+
+// (0x8B4) CLASSD CON1
+#define SPK_DTIN_MASK 0x000F
+#define SPK_DTIN_SHIFT 0
+#define SPK_DTIP_MASK 0x00F0
+#define SPK_DTIP_SHIFT 4
+#define SPK_DTCN_MASK 0x0F00
+#define SPK_DTCN_SHIFT 8
+#define SPK_DTCP_MASK 0xF000
+#define SPK_DTCP_SHIFT 12
+
+// (0x8B8) CLASSD CON2
+#define SPK_DMODE_MASK 0x0003
+#define SPK_DMODE_SHIFT 0
+#define SPK_PCHG_MASK 0x000C
+#define SPK_PCHG_SHIFT 2
+#define SPK_DTCAL_MASK 0x0010
+#define SPK_DTCAL_SHIFT 4
+#define SPK_PMODE_MASK 0x0020
+#define SPK_PMODE_SHIFT 5
+#define SPK_CMODE_MASK 0x00C0
+#define SPK_CMODE_SHIFT 6
+#define SPK_CCODE_MASK 0x0F00
+#define SPK_CCODE_SHIFT 8
+
+// (0x8BC) CLASSD CON3
+#define SPK_EN_VIEW_CLK_MASK 0x0001
+#define SPK_EN_VIEW_CLK_SHIFT 0
+#define SPK_EN_VIEW_VREF_MASK 0x0002
+#define SPK_EN_VIEW_VREF_SHIFT 1
+#define SPK_SLEW_MASK 0x000C
+#define SPK_SLEW_SHIFT 2
+#define SPK_OC_EN_MASK 0x0010
+#define SPK_OC_EN_SHIFT 4
+#define SPK_OSCISEL_MASK 0x0020
+#define SPK_OSCISEL_SHIFT 5
+#define SPK_VOL_MASK 0x0700
+#define SPK_VOL_SHIFT 8
+
+// (0x8C8) TEST CON2
+#define ADC_TMR_MASK 0x0020
+#define ADC_TMR_SHIFT 5
+#define ADC_VBAT_OUT_EN_MASK 0x0040
+#define ADC_VBAT_OUT_EN_SHIFT 6
+#define ADC_ISENSE_OUT_EN_MASK 0x0080
+#define ADC_ISENSE_OUT_EN_SHIFT 7
+
+// (0x8D0) OC CON0
+#define VRF_OC_GEAR_MASK 0x0003
+#define VRF_OC_GEAR_SHIFT 0
+#define VRF_OC_AUTO_OFF_MASK 0x0004
+#define VRF_OC_AUTO_OFF_SHIFT 2
+#define VRF_OC_INT_EN_MASK 0x0008
+#define VRF_OC_INT_EN_SHIFT 3
+#define VIO_OC_GEAR_MASK 0x0030
+#define VIO_OC_GEAR_SHIFT 4
+#define VIO_OC_AUTO_OFF_MASK 0x0040
+#define VIO_OC_AUTO_OFF_SHIFT 6
+#define VIO_OC_INT_EN_MASK 0x0080
+#define VIO_OC_INT_EN_SHIFT 7
+#define VM_OC_GEAR_MASK 0x0300
+#define VM_OC_GEAR_SHIFT 8
+#define VM_OC_AUTO_OFF_MASK 0x0400
+#define VM_OC_AUTO_OFF_SHIFT 10
+#define VM_OC_INT_EN_MASK 0x0800
+#define VM_OC_INT_EN_SHIFT 11
+#define VA_OC_GEAR_MASK 0x3000
+#define VA_OC_GEAR_SHIFT 12
+#define VA_OC_AUTO_OFF_MASK 0x4000
+#define VA_OC_AUTO_OFF_SHIFT 14
+#define VA_OC_INT_EN_MASK 0x8000
+#define VA_OC_INT_EN_SHIFT 15
+
+// (0x8D4) OC CON1
+#define VTCXO_OC_GEAR_MASK 0x3000
+#define VTCXO_OC_GEAR_SHIFT 12
+#define VTCXO_OC_AUTO_OFF_MASK 0x4000
+#define VTCXO_OC_AUTO_OFF_SHIFT 14
+#define VTCXO_OC_INT_EN_MASK 0x8000
+#define VTCXO_OC_INT_EN_SHIFT 15
+
+// (0x8D8) OC CON2
+#define VBT_OC_GEAR_MASK 0x0003
+#define VBT_OC_GEAR_SHIFT 0
+#define VBT_OC_AUTO_OFF_MASK 0x0004
+#define VBT_OC_AUTO_OFF_SHIFT 2
+#define VBT_OC_INT_EN_MASK 0x0008
+#define VBT_OC_INT_EN_SHIFT 3
+#define VUSB_OC_GEAR_MASK 0x0030
+#define VUSB_OC_GEAR_SHIFT 4
+#define VUSB_OC_AUTO_OFF_MASK 0x0040
+#define VUSB_OC_AUTO_OFF_SHIFT 6
+#define VUSB_OC_INT_EN_MASK 0x0080
+#define VUSB_OC_INT_EN_SHIFT 7
+#define VCAMD_OC_GEAR_MASK 0x0300
+#define VCAMD_OC_GEAR_SHIFT 8
+#define VCAMD_OC_AUTO_OFF_MASK 0x0400
+#define VCAMD_OC_AUTO_OFF_SHIFT 10
+#define VCAMD_OC_INT_EN_MASK 0x0800
+#define VCAMD_OC_INT_EN_SHIFT 11
+#define VCAMA_OC_GEAR_MASK 0x3000
+#define VCAMA_OC_GEAR_SHIFT 12
+#define VCAMA_OC_AUTO_OFF_MASK 0x4000
+#define VCAMA_OC_AUTO_OFF_SHIFT 14
+#define VCAMA_OC_INT_EN_MASK 0x8000
+#define VCAMA_OC_INT_EN_SHIFT 15
+
+// (0x8DC) OC CON3
+#define VSPK_OC_GEAR_MASK 0x0003
+#define VSPK_OC_GEAR_SHIFT 0
+#define VSPK_OC_AUTO_OFF_MASK 0x0004
+#define VSPK_OC_AUTO_OFF_SHIFT 2
+#define VSPK_OC_INT_EN_MASK 0x0008
+#define VSPK_OC_INT_EN_SHIFT 3
+#define VIBR_OC_GEAR_MASK 0x0030
+#define VIBR_OC_GEAR_SHIFT 4
+#define VIBR_OC_AUTO_OFF_MASK 0x0040
+#define VIBR_OC_AUTO_OFF_SHIFT 6
+#define VIBR_OC_INT_EN_MASK 0x0080
+#define VIBR_OC_INT_EN_SHIFT 7
+#define VBOOST_OC_GEAR_MASK 0x0300
+#define VBOOST_OC_GEAR_SHIFT 8
+#define VBOOST_OC_AUTO_OFF_MASK 0x0400
+#define VBOOST_OC_AUTO_OFF_SHIFT 10
+#define VBOOST_OC_INT_EN_MASK 0x0800
+#define VBOOST_OC_INT_EN_SHIFT 11
+#define VSIM_OC_GEAR_MASK 0x3000
+#define VSIM_OC_GEAR_SHIFT 12
+#define VSIM_OC_AUTO_OFF_MASK 0x4000
+#define VSIM_OC_AUTO_OFF_SHIFT 14
+#define VSIM_OC_INT_EN_MASK 0x8000
+#define VSIM_OC_INT_EN_SHIFT 15
+
+// (0x8E0) OC CON4
+#define VIBR_STBTD_MASK 0x0003
+#define VIBR_STBTD_SHIFT 0
+#define VSIM_STBTD_MASK 0x000C
+#define VSIM_STBTD_SHIFT 2
+#define VBT_STBTD_MASK 0x0030
+#define VBT_STBTD_SHIFT 4
+#define VUSB_STBTD_MASK 0x00C0
+#define VUSB_STBTD_SHIFT 6
+#define VCAMD_STBTD_MASK 0x0300
+#define VCAMD_STBTD_SHIFT 8
+#define VCAMA_STBTD_MASK 0x0C00
+#define VCAMA_STBTD_SHIFT 10
+
+// (0x8E4) OC CON5
+#define SPK_OC_FLAG_MASK 0x0001
+#define SPK_OC_FLAG_SHIFT 0
+#define VIBR_OC_FLAG_MASK 0x0002
+#define VIBR_OC_FLAG_SHIFT 1
+#define VBOOST_OC_FLAG_MASK 0x0004
+#define VBOOST_OC_FLAG_SHIFT 2
+#define VSIM_OC_FLAG_MASK 0x0008
+#define VSIM_OC_FLAG_SHIFT 3
+#define VBT_OC_FLAG_MASK 0x0010
+#define VBT_OC_FLAG_SHIFT 4
+#define VUSB_OC_FLAG_MASK 0x0020
+#define VUSB_OC_FLAG_SHIFT 5
+#define VCAMD_OC_FLAG_MASK 0x0040
+#define VCAMD_OC_FLAG_SHIFT 6
+#define VCAMA_OC_FLAG_MASK 0x0080
+#define VCAMA_OC_FLAG_SHIFT 7
+#define VTCXO_OC_FLAG_MASK 0x0800
+#define VTCXO_OC_FLAG_SHIFT 11
+#define VRF_OC_FLAG_MASK 0x1000
+#define VRF_OC_FLAG_SHIFT 12
+#define VIO_OC_FLAG_MASK 0x2000
+#define VIO_OC_FLAG_SHIFT 13
+#define VM_OC_FLAG_MASK 0x4000
+#define VM_OC_FLAG_SHIFT 14
+#define VA_OC_FLAG_MASK 0x8000
+#define VA_OC_FLAG_SHIFT 15
+
+
+// (0x8F0) CHR CON4
+
+// (0x8F4) CHR CON5
+
+#endif // #if defined(PMIC_6253_REG_API)
+
+
+#endif // #ifndef __DCL_PMIC6253_HW_H_STRUCT__
+
+
+
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6253_sw.h b/mcu/driver/peripheral/inc/dcl_pmu6253_sw.h
new file mode 100644
index 0000000..ee833fd
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6253_sw.h
@@ -0,0 +1,798 @@
+
+
+
+#ifndef __DCL_PMU6253_SW_H_STRUCT__
+#define __DCL_PMU6253_SW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6253_REG_API)
+
+/* Charger external interrupt is fixed. */
+
+#define PMU_CHR_EINT_PIN 7
+
+
+/* adc number for measuring VBAT/VISENSE/VCHARGER is fixed internally. */
+#if defined(PMIC_6253_REG_API)
+#if defined(DRV_MISC_PMU_ADC_CHANNEL_FROM_0)
+#define PMU_ADC_VBAT_CH_NUM 0
+#define PMU_ADC_VISENSE_CH_NUM 1
+#define PMU_ADC_VCHARGER_CH_NUM 2
+#else // #if defined(DRV_MISC_PMU_ADC_CHANNEL_FROM_0)
+#define PMU_ADC_VBAT_CH_NUM 3
+#define PMU_ADC_VISENSE_CH_NUM 4
+#define PMU_ADC_VCHARGER_CH_NUM 5
+#endif // #if defined(DRV_MISC_PMU_ADC_CHANNEL_FROM_0)
+#endif // #elif defined(PMIC_6253_REG_API)
+
+/* adc factor for VBAT/VISENSE/VCHARGER */
+#define PMU_ADC_FACTOR_VBAT 100
+#define PMU_ADC_FACTOR_VISENSE 100
+#define PMU_ADC_FACTOR_VCHARGER 250
+
+
+// Define to enable PMU6253 charger watch dog timer kick
+// When enable charger, PMU6253 will enable a watch dog timer
+// We need to kick the timer periodically, to ontify PMU6253 that BB is alive
+// If timeout, PMU6253 will disable charge automatically
+// #### If this is NOT enabled, we will disable the watch dog timer function at boot time
+// This should be defined when PMU driver need to perform WDT clear
+// BMT already support charge WDT, so this should be comment
+//#define PMU6253_ENABLE_DRIVER_CHARGE_WDT
+
+
+// Define to disable charge WDT of PMU6253
+// Define only for debug purpose
+//#define DEBUG_DISABLE_CHARGE_WDT
+
+
+
+// (0x800) VRF CON
+typedef enum{
+ VRF_ON_SEL_SRCLKENA=0,
+ VRF_ON_SEL_VRF_EN
+}pmu6253_vrf_on_sel_enum;
+
+typedef enum{
+ VD_SENSE_FROM_LOCAL_VOLTAGE=0,
+ VD_SENSE_FROM_REMOTE_VOLTAGE
+}pmu6253_vd_sense_enum;
+
+// (0x810) VTCXO CON
+typedef enum{
+ VTCXO_ON_SEL_SRCLKENA=0,
+ VTCXO_ON_SEL_VTCXO_EN
+}pmu6253_vtcxo_on_sel_enum;
+
+// (0x814) VA CON
+typedef enum{
+ VA_ON_SEL_ALWAYS_ON = 0,
+ VA_ON_SEL_SRCLKENA
+}pmu6253_va_on_sel_enum;
+
+// (0x818) VSIM CON
+typedef enum{
+ PMU6253_VSIM_1_8V = 0,
+ PMU6253_VSIM_3_0V
+}pmu6253_vsim_sel_enum;
+
+#if defined(__DRV_PMU53_SPEC_V1__)
+
+// (0x824) VBT CON ==> VBT move to 0x890
+typedef enum{
+ VBT_SEL_2_8V = 0,
+ VBT_SEL_3_0V
+}pmu6253_vbt_sel_enum;
+
+#else // #if defined(__DRV_PMU53_SPEC_V1__)
+
+// (0x890) VBT CON
+typedef enum{
+ VBT_SEL_1_5V = 0,
+ VBT_SEL_1_8V,
+ VBT_SEL_2_5V,
+ VBT_SEL_3_0V
+}pmu6253_vbt_sel_enum;
+
+#endif // #if defined(__DRV_PMU53_SPEC_V1__)
+
+// (0x828) VCAMD CON
+typedef enum{
+ VCAMD_SEL_1_3V = 0,
+ VCAMD_SEL_1_5V,
+ VCAMD_SEL_1_8V,
+ VCAMD_SEL_2_8V
+}pmu6253_vcamd_sel_enum;
+
+// (0x82C) VCAMA CON
+typedef enum{
+ VCAMA_SEL_1_5V = 0,
+ VCAMA_SEL_1_8V,
+ VCAMA_SEL_2_5V,
+ VCAMA_SEL_2_8V
+}pmu6253_vcama_sel_enum;
+
+// (0x834) GPIO CON
+typedef enum{
+ GPIO_DRV_8_MA=0,
+ GPIO_DRV_4_MA
+}pmu6253_gpio_drv_sel_enum;
+
+// (0x844) VCORE CON1
+typedef enum{
+ VCORE_MODESET_PWM = 0,
+ VCORE_MODESET_PFM
+}pmu6253_vcore_modeset_enum;
+
+typedef enum{
+ VCORE_ADC_IN_NEGATIVE_EDGE = 0,
+ VCORE_ADC_IN_POSITIVE_EDGE
+}pmu6253_vcore_adc_in_enum;
+
+typedef enum{
+ VCORE_26MHZ_DIVIDED_BY_32 = 0,
+ VCORE_26MHZ_DIVIDED_BY_16
+}pmu6253_vcore_fast_slow_enum;
+
+typedef enum{
+ VCORE_PWMB_3_BITS = 0,
+ VCORE_PWMB_4_BITS
+}pmu_6253_vcore_pwmb_enum;
+
+// (0x848) VCORE CON2
+typedef enum{
+ VCORE_VOLSEL_1_4V_TO_2_2V = 0,
+ VCORE_VOLSEL_0_8V_TO_1_6V
+}pmu6253_vcore_volsel_enum;
+
+// (0x84C) VCORE CON3
+typedef enum{
+ VCORE_VFBADJ_0_85V = 0,
+ VCORE_VFBADJ_0_90V,
+ VCORE_VFBADJ_0_95V,
+ VCORE_VFBADJ_1_00V,
+ VCORE_VFBADJ_1_05V,
+ VCORE_VFBADJ_1_10V,
+ VCORE_VFBADJ_1_15V,
+ VCORE_VFBADJ_1_20V,
+ VCORE_VFBADJ_1_25V,
+ VCORE_VFBADJ_1_30V,
+ VCORE_VFBADJ_1_35V,
+ VCORE_VFBADJ_1_40V,
+ VCORE_VFBADJ_1_45V,
+ VCORE_VFBADJ_1_50V,
+ VCORE_VFBADJ_1_55V,
+ VCORE_VFBADJ_1_60V
+}pmu6253_vcore_vfbadj_enum;
+
+typedef enum{
+ VCORE_DIRECT_CTRL_DVFS = 0,
+ VCORE_DIRECT_CTRL_DIRECT_FEED_THROUGH
+}pmu6253_vcore_direct_ctrl_enum;
+
+typedef enum{
+ VCORE_DCVCLKSEL_INTERNAL = 0,
+ VCORE_DCVCLKSEL_EXTERNAL
+}pmu6253_vcore_dcvclksel_enum;
+
+typedef enum{
+ VCORE_MODEEN_MANUAL_CHANGE_MODE = 0,
+ VCORE_MODEEN_MANUAL_AUTO_CHANGE_MODE,
+ VCORE_MODEEN_MANUAL_SW_CHANGE_MODE
+}pmu6253_vcore_modeen_enum;
+
+typedef enum{
+ VCORE_MODECMP_LOW_OFFSET = 0,
+ VCORE_MODECMP_AUTO_ZERO
+}pmu6253_vcore_modecmp_enum;
+
+typedef enum{
+ VCORE_MODESEL1A_NCD_MODE = 0,
+ VCORE_MODESEL1A_AVG_CURRENT_MODE
+}pmu6253_vcore_modesel1a_enum;
+
+typedef enum{
+ VCORE_CLK_SOURCE_FROM_CLKSQ = 0,
+ VCORE_CLK_SOURCE_FROM_TCXO26M_CK
+}pmu6253_vcore_clk_source_enum;
+
+// (0x860) STARTUP CON0
+typedef enum{
+ UV_SEL_2_90V = 0,
+ UV_SEL_2_75V,
+ UV_SEL_2_60V,
+ UL_SEL_FOLLOW_DDLO
+}pmu6253_uv_sel_enum;
+
+typedef enum{
+ PWRKEY_LOW = 0,
+ PWRKEY_HIGH
+}pmu6253_pwrkey_signal_enum;
+
+// (0x864) STARTUP CON1
+typedef enum{
+ THR_INIT_SETTING = 0,
+ THR_PLUS_10_DEGREE_C,
+ THR_MINUS_20_DEGREE_C,
+ THR_MINUS_10_DEGREE_C
+}pmu6253_thr_sel_num;
+
+// (0x870) CHR CON0
+typedef enum{
+ CHOFST_PLUS_0_STEP = 0,
+ CHOFST_PLUS_1_STEP = 1,
+ CHOFST_PLUS_2_STEP = 2,
+ CHOFST_MINUS_2_STEP = 6,
+ CHOFST_MINUS_1_STEP = 7
+}pmu6253_chofst_enum;
+
+typedef enum{
+ CHR_CURR_50_0MA = 0,
+ CHR_CURR_87_5MA,
+ CHR_CURR_150_0MA,
+ CHR_CURR_225_0MA,
+ CHR_CURR_300_0MA,
+ CHR_CURR_450_0MA,
+ CHR_CURR_650_0MA,
+ CHR_CURR_800_0MA
+}pmu6253_chr_current_enum;
+
+typedef enum{
+ CV_TUNE_1_200V = 0,
+ CV_TUNE_1_205V,
+ CV_TUNE_1_210V,
+ CV_TUNE_1_215V,
+ CV_TUNE_1_180V,
+ CV_TUNE_1_185V,
+ CV_TUNE_1_190V,
+ CV_TUNE_1_195V
+}pmu6253_cv_tune_enum;
+
+// (0x874) CHR CON1
+typedef enum{
+ CAL_PRECC_50_0MA = 0,
+ CAL_PRECC_87_5_MA,
+ CAL_PRECC_150_0MA,
+ CAL_PRECC_225_0MA
+}pmu6253_cal_precc_enum;
+
+typedef enum{
+ SYSTEM_PWR_SRC_DEFAULT = 0,
+ SYSTEM_PWR_SRC_REFER_PS_SET
+}pmu6253_ps_sel_enum;
+
+typedef enum{
+ SYSTEM_PWR_SRC_VBAT = 0,
+ SYSTEM_PWR_SRC_AC
+}pmu6253_ps_set_enum;
+
+typedef enum{
+ CHR_OV_5_5V = 0,
+ CHR_OV_6_0V,
+ CHR_OV_6_5V,
+ CHR_OV_7_0V
+}pmu6253_chr_ov_enum;
+
+// (0x87C) CHR CON3
+typedef enum{
+ CHR_WDT_4_SEC = 0,
+ CHR_WDT_8_SEC,
+ CHR_WDT_16_SEC,
+ CHR_WDT_32_SEC
+}pmu6253_chr_wdt_td_enum;
+
+// (0x880) DRIVER CON0
+typedef enum{
+ KPLED_WLED = 0,
+ KPLED_RLED
+}pmu6253_kpled_type_enum;
+
+
+typedef enum{
+ LED_1_SET = 1,
+ LED_4_WLED_4_RLED = 3,
+ LED_4_WLED_8_RLED = 7
+}pmu6253_kpled_sel_enum;
+
+typedef enum{
+ ISINK1_TURN_ON = 1, // Bit 0
+ ISINK2_TURN_ON = 2, // Bit 1
+ ISINK3_TURN_ON = 4, // Bit 2
+ ISINK4_TURN_ON = 8, // Bit 3
+ ISINKALL_TURN_ON = 0xF // 0xF (Bit[3..0])
+}pmu6253_isinks_chsel_enum;
+
+// (0x888) DRIVER CON2
+typedef enum{
+ ISINKS_VLED_STEP_5_MA = 0,
+ ISINKS_VLED_STEP_10_MA,
+ ISINKS_VLED_STEP_15_MA,
+ ISINKS_VLED_STEP_20_MA
+}pmu6253_isinks_vled_enum;
+
+#if defined(__DRV_PMU53_SPEC_V1__)
+
+// (0x890) DRIVER CON4
+typedef enum{
+ VIBR_SEL_1_5V = 0,
+ VIBR_SEL_1_8V,
+ VIBR_SEL_2_5V,
+ VIBR_SEL_3_0V
+}pmu6253_vibr_sel_enum;
+
+#else // #if defined(__DRV_PMU53_SPEC_V1__)
+
+// (0x824) DRIVER CON4
+typedef enum{
+ VIBR_SEL_2_8V = 0,
+ VIBR_SEL_3_0V
+}pmu6253_vibr_sel_enum;
+
+#endif // #if defined(__DRV_PMU53_SPEC_V1__)
+
+typedef enum{
+ VBOOST_SS_SPEED_NORMAL = 0,
+ VBOOST_SS_SPEED_2_OVER_3
+}pmu6253_vboost_ss_speed_enum;
+
+// (0x8B0) CLASSD CON0
+typedef enum{
+ SPK_EMODE_NO_EXTENSION = 1,
+ SPK_EMODE_LEAD_EXTENSION,
+ SPK_EMODE_LAG_EXTENSION
+}pmu6253_spk_emode_enum;
+
+typedef enum{
+ PMU6253_SPK_CLASS_D_MODE = 0,
+ PMU6253_SPK_CLASS_AB_MODE
+}pmu6253_spk_mode_enum;
+
+typedef enum{
+ SPK_AB_BIAS_3_225MA = 0,
+ SPK_AB_BIAS_6_381MA,
+ SPK_AB_BIAS_9_533MA,
+ SPK_AB_BIAS_12_684MA
+}pmu6253_spkab_obias_enum;
+
+// (0x8B8) CLASSD CON2
+typedef enum{
+ SPK_DMODE_FB_FORCED = 0,
+ SPK_DMODE_FB_AUTO,
+ SPK_DMODE_FF_FORCED,
+ SPK_DMODE_FF_AUTO
+}pmu6253_spk_dmode_enum;
+
+typedef enum{
+ SPK_PCHG_103_0NS = 0,
+ SPK_PCHG_55_67NS,
+ SPK_PCHG_39_09NS,
+ SPK_PCHG_30_47NS
+}pmu6253_spk_pchg_enum;
+
+typedef enum{
+ SPK_SPK_CCODE = 1,
+ SPK_TRIANGLE_WAVE = 2,
+ SPK_PRNG_WAVE = 3
+}pmu6253_spk_freq_ctrl_enum;
+
+typedef enum{
+ SPK_SLEW_2_OVER_4 = 0,
+ SPK_SLEW_1_OVER_4,
+ SPK_SLEW_4_OVER_4,
+ SPK_SLEW_3_OVER_4
+}pmu6253_spk_slew_enum;
+
+// (0x8D0) OC CON0
+typedef enum{
+ OC_GEAR_100_US = 0,
+ OC_GEAR_200_US,
+ OC_GEAR_400_US,
+ OC_GEAR_800_US
+}pmu6253_gear_enum;
+
+// (0x8E0) OC CON4
+typedef enum{
+ SS_DELAY_200US = 0,
+ SS_DELAY_400US,
+ SS_DELAY_600US,
+ SS_DELAY_800US
+}pmu6253_soft_start_delay;
+
+
+// (0x8E4) OC CON5
+typedef enum{
+ SPK_OC_FLAG = 0x0001,
+ VIBR_OC_FLAG = 0x0002,
+ VBOOST_OC_FLAG = 0x0004,
+ VSIM_OC_FLAG = 0x0008,
+ VBT_OC_FLAG = 0x0010,
+ VUSB_OC_FLAG = 0x0020,
+ VCAMD_OC_FLAG = 0x0040,
+ VCAMA_OC_FLAG = 0x0080,
+ VTCXO_OC_FLAG = 0x0800,
+ VRF_OC_FLAG = 0x1000,
+ VIO_OC_FLAG = 0x2000,
+ VM_OC_FLAG = 0x4000,
+ VA_OC_FLAG = 0x8000
+}pmu6253_oc_bit_enum;
+
+
+// =====================================================================================
+// (0x800) VRF CON
+extern void dcl_pmu6253_vrf_enable(kal_bool enable);
+extern void dcl_pmu6253_vrf_cal(kal_uint8 val);
+extern void dcl_pmu6253_vrf_on_sel(pmu6253_vrf_on_sel_enum sel);
+extern void dcl_pmu6253_vrf_ocfb_enable(kal_bool enable);
+extern kal_bool dcl_pmu6253_vrf_status(void);
+
+// (0x804) VIO CON
+extern void dcl_pmu6253_vio_cal(kal_uint8 val);
+extern void dcl_pmu6253_vio_vd_sense(pmu6253_vd_sense_enum sel);
+extern void dcl_pmu6253_vio_ocfb_enable(kal_bool enable);
+extern kal_bool dcl_pmu6253_vio_status(void);
+
+// (0x808) VM CON
+extern void dcl_pmu6253_vm_cal(kal_uint8 val);
+extern void dcl_pmu6253_vm_vd_sense(pmu6253_vd_sense_enum sel);
+extern void dcl_pmu6253_vm_ocfb_enable(kal_bool enable);
+extern kal_bool dcl_pmu6253_vm_status(void);
+
+// (0x80C) VRTC CON
+extern void dcl_pmu6253_vrtc_cal(kal_uint8 val);
+extern kal_bool dcl_pmu6253_vrtc_status(void);
+
+// (0x810) VTCXO CON
+extern void dcl_pmu6253_vtcxo_enable(kal_bool enable);
+extern void dcl_pmu6253_vtcxo_cal(kal_uint8 val);
+extern void dcl_pmu6253_vtcxo_on_sel(pmu6253_vtcxo_on_sel_enum sel);
+extern void dcl_pmu6253_vtcxo_srclken(kal_bool enable);
+extern void dcl_pmu6253_vtcxo_ocfb_enable(kal_bool enable);
+extern kal_bool dcl_pmu6253_vtcxo_status(void);
+
+// (0x814) VA CON
+extern void dcl_pmu6253_va_cal(kal_uint8 val);
+extern void dcl_pmu6253_va_vd_sense(pmu6253_vd_sense_enum sel);
+extern void dcl_pmu6253_va_on_sel(pmu6253_va_on_sel_enum sel);
+extern void dcl_pmu6253_va_ocfb_enable(kal_bool enable);
+extern kal_bool dcl_pmu6253_va_status(void);
+
+// (0x818) VSIM CON
+extern void dcl_pmu6253_vsim_enable(kal_bool enable);
+extern void dcl_pmu6253_vsim_cal(kal_uint8 val);
+extern void dcl_pmu6253_vsim_datal(kal_bool pull_low);
+extern void dcl_pmu6253_vsim_sel(pmu6253_vsim_sel_enum sel);
+extern void dcl_pmu6253_vsim_pwr_saving(kal_bool enable);
+extern void dcl_pmu6253_vsim_ocfb_enable(kal_bool enable);
+extern kal_bool dcl_pmu6253_vsim_status(void);
+
+// (0x81C) VSIM2 CON
+extern void dcl_pmu6253_vsim2_enable(kal_bool enable);
+extern void dcl_pmu6253_vsim2_cal(kal_uint8 val);
+extern void dcl_pmu6253_vsim2_datal(kal_bool pull_low);
+extern void dcl_pmu6253_vsim2_sel(pmu6253_vsim_sel_enum sel);
+extern kal_bool dcl_pmu6253_vsim2_status(void);
+
+// (0x820) VUSB CON
+extern void dcl_pmu6253_vusb_enable(kal_bool enable);
+extern void dcl_pmu6253_vusb_cal(kal_uint8 val);
+extern void dcl_pmu6253_vusb_ocfb_enable(kal_bool enable);
+extern kal_bool dcl_pmu6253_vusb_status(void);
+
+// (0x824) VBT CON
+extern void dcl_pmu6253_vbt_enable(kal_bool enable);
+extern void dcl_pmu6253_vbt_cal(kal_uint8 val);
+extern void dcl_pmu6253_vbt_sel(pmu6253_vbt_sel_enum sel);
+extern void dcl_pmu6253_vbt_ocfb_enable(kal_bool enable);
+extern kal_bool dcl_pmu6253_vbt_status(void);
+
+// (0x828) VCAMD CON
+extern void dcl_pmu6253_vcamd_enable(kal_bool enable);
+extern void dcl_pmu6253_vcamd_cal(kal_uint8 val);
+extern void dcl_pmu6253_vcamd_sel(pmu6253_vcamd_sel_enum sel);
+extern void dcl_pmu6253_vcamd_ocfb_enable(kal_bool enable);
+extern kal_bool dcl_pmu6253_vcamd_status(void);
+
+// (0x82C) VCAMA CON
+extern void dcl_pmu6253_vcama_enable(kal_bool enable);
+extern void dcl_pmu6253_vcama_cal(kal_uint8 val);
+extern void dcl_pmu6253_vcama_sel(pmu6253_vcama_sel_enum sel);
+extern void dcl_pmu6253_vcama_ocfb_enable(kal_bool enable);
+extern kal_bool dcl_pmu6253_vcama_status(void);
+
+// (0x834) GPIO CON
+extern void dcl_pmu6253_gpio_drv(pmu6253_gpio_drv_sel_enum sel);
+extern void dcl_pmu6253_mtv_enable(kal_bool enable);
+
+// (0x840) VCORE CON
+extern void dcl_pmu6253_vcore_en_force(kal_bool enable);
+extern void dcl_pmu6253_vcore_cal(kal_uint8 val);
+extern void dcl_pmu6253_vcore_vd_sense(pmu6253_vd_sense_enum sel);
+extern kal_bool dcl_pmu6253_vcore_status(void);
+
+// (0x844) VCORE CON1
+extern void dcl_pmu6253_vcore_modeset(pmu6253_vcore_modeset_enum mode);
+extern void dcl_pmu6253_vcore_adc_in_edge(pmu6253_vcore_adc_in_enum edge);
+extern void dcl_pmu6253_vcore_fast_slow(pmu6253_vcore_fast_slow_enum sel);
+extern void dcl_pmu6253_vcore_pwmb(pmu_6253_vcore_pwmb_enum sel);
+extern void dcl_pmu6253_vcore_acc_out_init(kal_uint8 val);
+
+// (0x848) VCORE CON2
+extern void dcl_pmu6253_vcore_volsel(pmu6253_vcore_volsel_enum sel);
+extern void dcl_pmu6253_vcore_fben(kal_bool enable);
+
+// (0x84C) VCORE CON3
+extern void dcl_pmu6253_vcore_vfbadj(pmu6253_vcore_vfbadj_enum sel);
+extern void dcl_pmu6253_vcore_direct_ctrl_en(pmu6253_vcore_direct_ctrl_enum sel);
+extern void dcl_pmu6253_vcore_dcvclksel(pmu6253_vcore_dcvclksel_enum sel);
+extern void dcl_pmu6253_vcore_modeen(pmu6253_vcore_modeen_enum sel);
+extern void dcl_pmu6253_vcore_modecmp(pmu6253_vcore_modecmp_enum sel);
+extern void dcl_pmu6253_vcore_modesel1A(pmu6253_vcore_modesel1a_enum sel);
+
+// (0x854) VCORE CON5
+extern void dcl_pmu6253_vcore_vfbadj_slp(pmu6253_vcore_vfbadj_enum sel);
+extern void dcl_pmu6253_vcore_clk_source_sel(pmu6253_vcore_clk_source_enum sel);
+
+// (0x860) STARTUP CON0
+extern void dcl_pmu6253_uv_sel(pmu6253_uv_sel_enum sel);
+extern void dcl_pmu6253_pwrkey_vcore(pmu6253_pwrkey_signal_enum sel);
+extern void dcl_pmu6253_pwrkey_deb(pmu6253_pwrkey_signal_enum sel);
+
+// (0x864) STARTUP CON1
+extern void dcl_pmu6253_thr_sel(pmu6253_thr_sel_num sel);
+
+// (0x870) CHR CON0
+extern void dcl_pmu6253_chr_enable(kal_bool enable);
+extern void dcl_pmu6253_chofst(pmu6253_chofst_enum sel);
+extern void dcl_pmu6253_chr_current(pmu6253_chr_current_enum sel);
+extern pmu6253_chr_current_enum pmu6253_chr_get_current(void);
+extern void dcl_pmu6253_chr_force_enable(kal_bool enable);
+extern void dcl_pmu6253_cv_rt(kal_uint8 val);
+extern void dcl_pmu6253_cv_tune(pmu6253_cv_tune_enum sel);
+
+// (0x874) CHR CON1
+extern void dcl_pmu6253_cal_precc(pmu6253_cal_precc_enum sel);
+extern void dcl_pmu6253_ps_sel(pmu6253_ps_sel_enum sel);
+extern void dcl_pmu6253_ps_set(pmu6253_ps_set_enum sel);
+extern void dcl_pmu6253_chr_ov_sel(pmu6253_chr_ov_enum sel);
+
+// (0x878) CHR CON2
+extern kal_bool dcl_pmu6253_chrdet(void);
+extern kal_bool dcl_pmu6253_ovp(void);
+extern kal_bool dcl_pmu6253_bat_on(void);
+extern kal_bool dcl_pmu6253_bad_bat(void);
+extern kal_bool dcl_pmu6253_cv_mode(void);
+
+// (0x87C) CHR CON3
+extern void dcl_pmu6253_chr_wdt_td(pmu6253_chr_wdt_td_enum sel);
+extern void dcl_pmu6253_chr_wdt_enable(kal_bool enable);
+
+// (0x8F0) CHR CON4
+extern void dcl_pmu6253_chr_wdt_intr_enable(kal_bool enable);
+extern kal_bool dcl_pmu6253_chr_wdt_status(void);
+extern void dcl_pmu6253_chr_wdt_clear(void);
+
+// (0x8F4) CHR CON5
+//extern void dcl_pmu6253_chr_wdt_cnt(kal_uint32 val32);
+
+// (0x880) DRIVER CON0
+extern void dcl_pmu6253_isinks_enable(kal_bool enable);
+extern void dcl_pmu6253_isinks_force_off(kal_bool off);
+extern void dcl_pmu6253_kpled_type(pmu6253_kpled_type_enum sel);
+extern void dcl_pmu6253_kpled_enable(kal_bool enable);
+extern void dcl_pmu6253_kpled_force_off(kal_bool off);
+extern void dcl_pmu6253_kpled_sel(pmu6253_kpled_sel_enum sel);
+extern kal_bool dcl_pmu6253_isink1_status(void);
+extern kal_bool dcl_pmu6253_isink2_status(void);
+extern kal_bool dcl_pmu6253_isink3_status(void);
+extern kal_bool dcl_pmu6253_isink4_status(void);
+extern kal_bool dcl_pmu6253_kpled_status(void);
+
+// (0x884) DRIVER CON1
+extern void dcl_pmu6253_isinks_dimm(kal_uint8 sel);
+extern void dcl_pmu6253_isinks_chsel(pmu6253_isinks_chsel_enum sel);
+
+// (0x888) DRIVER CON2
+extern void dcl_pmu6253_sinks_irset_cal(kal_uint8 val);
+extern void dcl_pmu6253_isinks_vled_step(pmu6253_isinks_vled_enum sel);
+
+// (0x88C) DRIVER CON3
+extern void dcl_pmu6253_bl_enable(kal_bool enable);
+extern void dcl_pmu6253_vboost_enable(kal_bool enable);
+extern void dcl_pmu6253_bl_vgen_forceon(kal_bool on);
+extern void dcl_pmu6253_bl_mode(kal_uint8 val);
+extern void dcl_pmu6253_dimm_duty(kal_uint8 val);
+
+// (0x890) DRIVER CON4
+extern void dcl_pmu6253_vibr_enable(kal_bool enable);
+extern void dcl_pmu6253_vibr_sel(pmu6253_vibr_sel_enum sel);
+extern void dcl_pmu6253_vibr_cal(kal_uint8 val);
+extern void dcl_pmu6253_vibr_ocfb_enable(kal_bool enable);
+extern kal_bool dcl_pmu6253_vibr_status(void);
+
+// (0x8A0) BOOST CON0
+extern void dcl_pmu6253_vboost_sync_enable(kal_bool enable);
+extern void dcl_pmu6253_vboost_ss_speed(pmu6253_vboost_ss_speed_enum sel);
+extern void dcl_pmu6253_vboost_tune(kal_uint8 val);
+extern void dcl_pmu6253_vboost_cal(kal_uint8 val);
+extern kal_bool dcl_pmu6253_vboost_trk_status(void);
+extern kal_bool dcl_pmu6253_vboost_status(void);
+
+// (0x8A4) BOOST CON1
+extern void dcl_pmu6253_isns_cal(kal_uint8 val);
+
+// (0x8A8) BOOST CON2
+extern void dcl_pmu6253_vboost_forceon_clk(kal_bool forceon);
+extern void dcl_pmu6253_vboost_disclk(kal_bool forceoff);
+
+// (0x8B0) CLASSD CON0
+extern void dcl_pmu6253_spk_enable(kal_bool enable);
+extern void dcl_pmu6253_spk_reset(kal_bool reset);
+extern void dcl_pmu6253_spk_emode(pmu6253_spk_emode_enum sel);
+extern void dcl_pmu6253_spk_mode(pmu6253_spk_mode_enum sel);
+extern void dcl_pmu6253_spkab_float(kal_bool enable);
+extern void dcl_pmu6253_spkab_sended(kal_bool enable);
+extern void dcl_pmu6253_spkab_oc_enable(kal_bool enable);
+extern void dcl_pmu6253_spkab_depop_enable(kal_bool enable);
+extern void dcl_pmu6253_spkab_obias(pmu6253_spkab_obias_enum sel);
+
+// (0x8B4) CLASSD CON1
+extern void dcl_pmu6253_spk_dtin(kal_uint8 val);
+extern void dcl_pmu6253_spk_dtip(kal_uint8 val);
+extern void dcl_pmu6253_spk_dtcn(kal_uint8 val);
+extern void dcl_pmu6253_spk_dtcp(kal_uint8 val);
+
+// (0x8B8) CLASSD CON2
+extern void dcl_pmu6253_spk_dmode(pmu6253_spk_dmode_enum sel);
+extern void dcl_pmu6253_spk_pchg(pmu6253_spk_pchg_enum sel);
+extern void dcl_pmu6253_spk_dtcal(kal_bool enable);
+extern void dcl_pmu6253_spk_pmode_enable(kal_bool enable);
+extern void dcl_pmu6253_spk_cmode(pmu6253_spk_freq_ctrl_enum sel);
+extern void dcl_pmu6253_spk_ccode(kal_uint8 val);
+
+// (0x8BC) CLASSD CON3
+extern void dcl_pmu6253_spk_enable_view_clk(kal_bool enable);
+extern void dcl_pmu6253_spk_enable_view_vref(kal_bool enable);
+extern void dcl_pmu6253_spk_slew(pmu6253_spk_slew_enum sel);
+extern void dcl_pmu6253_spk_oc_enable(kal_bool enable);
+extern void dcl_pmu6253_spk_oscisel_half(kal_bool half);
+extern void dcl_pmu6253_spk_vol(kal_uint8 val);
+extern kal_uint8 pmu6253_spk_get_vol(void);
+
+// (0x8C8) TEST CON2
+extern void dcl_pmu6253_adc_vol_divided_by_2(kal_bool enable);
+extern void dcl_pmu6253_adc_meas_on(kal_bool enable);
+
+// (0x8D0) OC CON0
+extern void dcl_pmu6253_vrf_oc_gear(pmu6253_gear_enum sel);
+extern void dcl_pmu6253_vrf_oc_auto_off(kal_bool enable);
+extern void dcl_pmu6253_vrf_oc_int_enable(kal_bool enable);
+extern void dcl_pmu6253_vio_oc_gear(pmu6253_gear_enum sel);
+extern void dcl_pmu6253_vio_oc_auto_off(kal_bool enable);
+extern void dcl_pmu6253_vio_oc_int_enable(kal_bool enable);
+extern void dcl_pmu6253_vm_oc_gear(pmu6253_gear_enum sel);
+extern void dcl_pmu6253_vm_oc_auto_off(kal_bool enable);
+extern void dcl_pmu6253_vm_oc_int_enable(kal_bool enable);
+extern void dcl_pmu6253_va_oc_gear(pmu6253_gear_enum sel);
+extern void dcl_pmu6253_va_oc_auto_off(kal_bool enable);
+extern void dcl_pmu6253_va_oc_int_enable(kal_bool enable);
+
+// (0x8D4) OC CON1
+extern void dcl_pmu6253_vtcxo_oc_gear(pmu6253_gear_enum sel);
+extern void dcl_pmu6253_vtcxo_oc_auto_off(kal_bool enable);
+extern void dcl_pmu6253_vtcxo_oc_int_enable(kal_bool enable);
+
+// (0x8D8) OC CON2
+extern void dcl_pmu6253_vbt_oc_gear(pmu6253_gear_enum sel);
+extern void dcl_pmu6253_vbt_oc_auto_off(kal_bool enable);
+extern void dcl_pmu6253_vbt_oc_int_enable(kal_bool enable);
+extern void dcl_pmu6253_vusb_oc_gear(pmu6253_gear_enum sel);
+extern void dcl_pmu6253_vusb_oc_auto_off(kal_bool enable);
+extern void dcl_pmu6253_vusb_oc_int_enable(kal_bool enable);
+extern void dcl_pmu6253_vcamd_oc_gear(pmu6253_gear_enum sel);
+extern void dcl_pmu6253_vcamd_oc_auto_off(kal_bool enable);
+extern void dcl_pmu6253_vcamd_oc_int_enable(kal_bool enable);
+extern void dcl_pmu6253_vcama_oc_gear(pmu6253_gear_enum sel);
+extern void dcl_pmu6253_vcama_oc_auto_off(kal_bool enable);
+extern void dcl_pmu6253_vcama_oc_int_enable(kal_bool enable);
+
+// (0x8DC) OC CON3
+extern void dcl_pmu6253_spk_oc_gear(pmu6253_gear_enum sel);
+extern void dcl_pmu6253_spk_oc_auto_off(kal_bool enable);
+extern void dcl_pmu6253_spk_oc_int_enable(kal_bool enable);
+extern void dcl_pmu6253_vibr_oc_gear(pmu6253_gear_enum sel);
+extern void dcl_pmu6253_vibr_oc_auto_off(kal_bool enable);
+extern void dcl_pmu6253_vibr_oc_int_enable(kal_bool enable);
+extern void dcl_pmu6253_vboost_oc_gear(pmu6253_gear_enum sel);
+extern void dcl_pmu6253_vboost_oc_auto_off(kal_bool enable);
+extern void dcl_pmu6253_vboost_oc_int_enable(kal_bool enable);
+extern void dcl_pmu6253_vsim_oc_gear(pmu6253_gear_enum sel);
+extern void dcl_pmu6253_vsim_oc_auto_off(kal_bool enable);
+extern void dcl_pmu6253_vsim_oc_int_enable(kal_bool enable);
+
+// (0x8E0) OC CON4
+extern void dcl_pmu6253_vibr_stbtd(pmu6253_soft_start_delay sel);
+extern void dcl_pmu6253_vsim_stbtd(pmu6253_soft_start_delay sel);
+extern void dcl_pmu6253_vbt_stbtd(pmu6253_soft_start_delay sel);
+extern void dcl_pmu6253_vusb_stbtd(pmu6253_soft_start_delay sel);
+extern void dcl_pmu6253_vcamd_stbtd(pmu6253_soft_start_delay sel);
+extern void dcl_pmu6253_vcama_stbtd(pmu6253_soft_start_delay sel);
+
+// (0x8E4) OC CON5
+extern kal_bool dcl_pmu6253_oc_flag(pmu6253_oc_bit_enum sel);
+extern void dcl_pmu6253_clear_oc_flag(pmu6253_oc_bit_enum sel);
+extern void dcl_pmu6253_clear_all_oc_flag(void);
+
+
+// ====== Other exported APIs =============
+extern pmu6253_chr_current_enum pmu6253_ret_chr_current(void);
+extern pmu6253_chr_current_enum pmu6253_ret_usb_current(void);
+extern void dcl_pmu6253_init(void);
+
+
+
+/*
+typedef enum
+{
+ PMU_FAKE_LDO_BUCK_MAX
+}PMU_FAKE_LDO_BUCK_LIST_ENUM;
+
+typedef enum
+{
+ VRF,
+ VIO,
+ VM,
+ VRTC,
+ VTCXO,
+ VA,
+ VSIM,
+ VSIM2,
+ VUSB,
+ VBT,
+ VCAMA,
+ VCAMD,
+ VCORE,
+ VIBR,
+ PMU_LDO_BUCK_MAX,
+ VRF18,
+ VFM,
+ VMC
+}PMU_LDO_BUCK_LIST_ENUM;
+
+typedef enum
+{
+ VPA1,
+ PMU_VPA_MAX
+}PMU_VPA_LIST_ENUM;
+
+typedef enum
+{
+ CHR,
+ PMU_CHR_MAX
+}PMU_CHR_LIST_ENUM;
+
+typedef enum
+{
+ SPK,
+ SPKL,
+ SPKR,
+ PMU_SPK_MAX
+}PMU_SPK_LIST_ENUM;
+
+typedef enum
+{
+ PMU_ISINK_MAX
+}PMU_ISINK_LIST_ENUM;
+
+typedef enum
+{
+ PMU_BOOST_MAX
+}PMU_BOOST_LIST_ENUM;
+*/
+
+
+#endif // #ifdef PMIC_6253_REG_API
+#endif // #ifndef __DCL_PMU6253_SW_H_STRUCT__
+
+
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6255_hw.h b/mcu/driver/peripheral/inc/dcl_pmu6255_hw.h
new file mode 100644
index 0000000..6d63464
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6255_hw.h
@@ -0,0 +1,2425 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2011
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6255_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for PMU 6255 driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __PMU6255_HW_H__
+#define __PMU6255_HW_H__
+
+
+#if defined(PMIC_6255_REG_API)
+
+#define PMU_BASE MIXED_base
+
+#define PMU_END (PMU_BASE + 0x1000)
+
+///////////////////////////////////////////////////////////////////////////////
+
+#define WR_PATH (PMU_BASE + 0x0000)
+#define AFUNC_DIN (PMU_BASE + 0x0004)
+#define AFUNC_XOSC (PMU_BASE + 0x0008)
+#define ABIST_CON0 (PMU_BASE + 0x0010)
+#define ABIST_CON1 (PMU_BASE + 0x0014)
+#define ABIST_CON2 (PMU_BASE + 0x0018)
+#define ABIST_CON3 (PMU_BASE + 0x001C)
+#define AFUNC_RTC (PMU_BASE + 0x0020)
+#define EFUSE_CON0 (PMU_BASE + 0x0100)
+#define EFUSE_CON1 (PMU_BASE + 0x0104)
+#define EFUSE_CON2 (PMU_BASE + 0x0108)
+#define EFUSE_CON3 (PMU_BASE + 0x010C)
+#define EFUSE_CON4 (PMU_BASE + 0x0110)
+#define VSF_CON0 (PMU_BASE + 0x0700)
+#define VSF_CON1 (PMU_BASE + 0x0704)
+#define VSF_CON2 (PMU_BASE + 0x0708)
+#define VSF_CON3 (PMU_BASE + 0x070C)
+#define VRF_CON0 (PMU_BASE + 0x0800)
+#define VRF_CON1 (PMU_BASE + 0x0804)
+#define VRF_CON2 (PMU_BASE + 0x0808)
+#define VRF_CON3 (PMU_BASE + 0x080C)
+#define VTCXO_CON0 (PMU_BASE + 0x0810)
+#define VTCXO_CON1 (PMU_BASE + 0x0814)
+#define VTCXO_CON2 (PMU_BASE + 0x0818)
+#define VA_CON0 (PMU_BASE + 0x0820)
+#define VA_CON1 (PMU_BASE + 0x0824)
+#define VA_CON2 (PMU_BASE + 0x0828)
+#define VCAMA_CON0 (PMU_BASE + 0x0830)
+#define VCAMA_CON1 (PMU_BASE + 0x0834)
+#define VCAMA_CON2 (PMU_BASE + 0x0838)
+#define VCAMD_CON0 (PMU_BASE + 0x0840)
+#define VCAMD_CON1 (PMU_BASE + 0x0844)
+#define VCAMD_CON2 (PMU_BASE + 0x0848)
+#define VIO28_CON0 (PMU_BASE + 0x0850)
+#define VIO28_CON1 (PMU_BASE + 0x0854)
+#define VIO28_CON2 (PMU_BASE + 0x0858)
+#define VUSB_CON0 (PMU_BASE + 0x0860)
+#define VUSB_CON1 (PMU_BASE + 0x0864)
+#define VUSB_CON2 (PMU_BASE + 0x0868)
+#define VBT_CON0 (PMU_BASE + 0x0870)
+#define VBT_CON1 (PMU_BASE + 0x0874)
+#define VBT_CON2 (PMU_BASE + 0x0878)
+#define VSIM_CON0 (PMU_BASE + 0x0880)
+#define VSIM_CON1 (PMU_BASE + 0x0884)
+#define VSIM_CON2 (PMU_BASE + 0x0888)
+#define VSIM_CON3 (PMU_BASE + 0x088C)
+#define VSIM2_CON0 (PMU_BASE + 0x0890)
+#define VSIM2_CON1 (PMU_BASE + 0x0894)
+#define VSIM2_CON2 (PMU_BASE + 0x0898)
+#define VSIM2_CON3 (PMU_BASE + 0x089C)
+#define VRTC_CON0 (PMU_BASE + 0x08A0)
+#define VRTC_CON1 (PMU_BASE + 0x08A4)
+#define VRTC_CON2 (PMU_BASE + 0x08A8)
+#define VIBR_CON0 (PMU_BASE + 0x08B0)
+#define VIBR_CON1 (PMU_BASE + 0x08B4)
+#define VIBR_CON2 (PMU_BASE + 0x08B8)
+#define VMC_CON0 (PMU_BASE + 0x08C0)
+#define VMC_CON1 (PMU_BASE + 0x08C4)
+#define VMC_CON2 (PMU_BASE + 0x08C8)
+#define VIO18_CON0 (PMU_BASE + 0x08F0)
+#define VIO18_CON1 (PMU_BASE + 0x08F4)
+#define VIO18_CON2 (PMU_BASE + 0x08F8)
+#define VCORE_CON0 (PMU_BASE + 0x0900)
+#define VCORE_CON1 (PMU_BASE + 0x0904)
+#define VCORE_CON2 (PMU_BASE + 0x0908)
+#define VCORE_CON3 (PMU_BASE + 0x090C)
+#define VCORE_CON4 (PMU_BASE + 0x0910)
+#define VCORE_CON5 (PMU_BASE + 0x0914)
+#define VCORE_CON6 (PMU_BASE + 0x0918)
+#define CHR_CON0 (PMU_BASE + 0x0A00)
+#define CHR_CON1 (PMU_BASE + 0x0A04)
+#define CHR_CON2 (PMU_BASE + 0x0A08)
+#define CHR_CON3 (PMU_BASE + 0x0A0C)
+#define CHR_CON4 (PMU_BASE + 0x0A10)
+#define CHR_CON5 (PMU_BASE + 0x0A14)
+#define CHR_CON6 (PMU_BASE + 0x0A18)
+#define CHR_CON7 (PMU_BASE + 0x0A1C)
+#define CHR_CON8 (PMU_BASE + 0x0A20)
+#define CHR_CON9 (PMU_BASE + 0x0A24)
+#define CHR_CON10 (PMU_BASE + 0x0A28)
+#define CHR_CON11 (PMU_BASE + 0x0A2C)
+#define CHR_CON12 (PMU_BASE + 0x0A30)
+#define CHR_CON13 (PMU_BASE + 0x0A34)
+#define CHR_CON14 (PMU_BASE + 0x0A38)
+#define STRUP_CON0 (PMU_BASE + 0x0A80)
+#define STRUP_CON1 (PMU_BASE + 0x0A84)
+#define STRUP_CON2 (PMU_BASE + 0x0A88)
+#define STRUP_CON3 (PMU_BASE + 0x0A8C)
+#define BOOST_CON3 (PMU_BASE + 0x0B0C)
+#define ISINK0_CON0 (PMU_BASE + 0x0C00)
+#define ISINK0_CON1 (PMU_BASE + 0x0C04)
+#define ISINK0_CON2 (PMU_BASE + 0x0C08)
+#define ISINK1_CON0 (PMU_BASE + 0x0C10)
+#define ISINK2_CON0 (PMU_BASE + 0x0C20)
+#define ISINK3_CON0 (PMU_BASE + 0x0C30)
+#define ISINK4_CON0 (PMU_BASE + 0x0C40)
+#define ISINK5_CON0 (PMU_BASE + 0x0C50)
+#define KPLED_CON0 (PMU_BASE + 0x0C80)
+#define KPLED_CON1 (PMU_BASE + 0x0C84)
+#define SPK_CON0 (PMU_BASE + 0x0D00)
+#define SPK_CON3 (PMU_BASE + 0x0D0C)
+#define SPK_CON7 (PMU_BASE + 0x0D1C)
+#define SPK_CON8 (PMU_BASE + 0x0D20)
+#define PMU_OC_CON0 (PMU_BASE + 0x0E00)
+#define PMU_OC_CON1 (PMU_BASE + 0x0E04)
+#define PMU_OC_CON3 (PMU_BASE + 0x0E0C)
+#define PMU_OC_CON4 (PMU_BASE + 0x0E10)
+#define PMU_OC_CON5 (PMU_BASE + 0x0E14)
+#define PMU_OC_CON7 (PMU_BASE + 0x0E1C)
+#define PMU_OC_CON8 (PMU_BASE + 0x0E20)
+#define PMU_OC_CON9 (PMU_BASE + 0x0E24)
+#define PMU_OC_CONB (PMU_BASE + 0x0E2C)
+#define PMU_TEST_CON0 (PMU_BASE + 0x0F00)
+#define PMU_TEST_CON1 (PMU_BASE + 0x0F04)
+#define PMU_TEST_CON2 (PMU_BASE + 0x0F08)
+
+///////////////////////////////////////////////////////////////////////////////
+
+#define CON0_OFFSET 0x00
+#define CON1_OFFSET 0x04
+#define CON2_OFFSET 0x08
+#define CON3_OFFSET 0x0C
+#define CON4_OFFSET 0x10
+#define CON5_OFFSET 0x14
+#define CON6_OFFSET 0x18
+#define CON7_OFFSET 0x1C
+#define CON8_OFFSET 0x20
+#define CON9_OFFSET 0x24
+#define CON10_OFFSET 0x28
+#define CONA_OFFSET 0x28
+#define CON11_OFFSET 0x2C
+#define CONB_OFFSET 0x2C
+#define CON12_OFFSET 0x30
+#define CON13_OFFSET 0x34
+#define CON14_OFFSET 0x38
+
+
+#define SIMLS_PWDB_OFFSET CON0_OFFSET
+#define SIMLS_PWDB_MASK 0x0100
+#define SIMLS_PWDB_SHIFT 8
+
+#define PRST_MODE_OFFSET CON0_OFFSET
+#define PRST_MODE_MASK 0x0004
+#define PRST_MODE_SHIFT 2
+
+#define ABIST_MODE_OFFSET CON0_OFFSET
+#define ABIST_MODE_MASK 0x0002
+#define ABIST_MODE_SHIFT 1
+
+#define ACD_MODE_OFFSET CON0_OFFSET
+#define ACD_MODE_MASK 0x0001
+#define ACD_MODE_SHIFT 0
+
+#define A_FUNC_DOE_OFFSET CON0_OFFSET
+#define A_FUNC_DOE_MASK 0xFFFF
+#define A_FUNC_DOE_SHIFT 0
+
+#define XOSC_LPDTB_OFFSET CON0_OFFSET
+#define XOSC_LPDTB_MASK 0x8000
+#define XOSC_LPDTB_SHIFT 15
+
+#define XOSC_CPDTB_OFFSET CON0_OFFSET
+#define XOSC_CPDTB_MASK 0x4000
+#define XOSC_CPDTB_SHIFT 14
+
+#define XOSC_LPDRST_OFFSET CON0_OFFSET
+#define XOSC_LPDRST_MASK 0x0200
+#define XOSC_LPDRST_SHIFT 9
+
+#define XOSC_LPDEN_OFFSET CON0_OFFSET
+#define XOSC_LPDEN_MASK 0x0100
+#define XOSC_LPDEN_SHIFT 8
+
+#define XOSC_PWDB_OFFSET CON0_OFFSET
+#define XOSC_PWDB_MASK 0x0080
+#define XOSC_PWDB_SHIFT 7
+
+#define XOSC_AMPSEL_OFFSET CON0_OFFSET
+#define XOSC_AMPSEL_MASK 0x0040
+#define XOSC_AMPSEL_SHIFT 6
+
+#define XOSC_AMPEN_OFFSET CON0_OFFSET
+#define XOSC_AMPEN_MASK 0x0020
+#define XOSC_AMPEN_SHIFT 5
+
+#define XOSC_CALI_OFFSET CON0_OFFSET
+#define XOSC_CALI_MASK 0x001F
+#define XOSC_CALI_SHIFT 0
+
+#define ABIST_FINISH_OFFSET CON0_OFFSET
+#define ABIST_FINISH_MASK 0x8000
+#define ABIST_FINISH_SHIFT 15
+
+#define ABIST_PASS_OFFSET CON0_OFFSET
+#define ABIST_PASS_MASK 0x4000
+#define ABIST_PASS_SHIFT 14
+
+#define ABIST_MON_CFG_OFFSET CON0_OFFSET
+#define ABIST_MON_CFG_MASK 0x0100
+#define ABIST_MON_CFG_SHIFT 8
+
+#define ABIST_HMON_SEL_OFFSET CON1_OFFSET
+#define ABIST_HMON_SEL_MASK 0xFF00
+#define ABIST_HMON_SEL_SHIFT 8
+
+#define ABIST_LMON_SEL_OFFSET CON1_OFFSET
+#define ABIST_LMON_SEL_MASK 0x00FF
+#define ABIST_LMON_SEL_SHIFT 0
+
+#define ABIST_HMON_OUT_OFFSET CON2_OFFSET
+#define ABIST_HMON_OUT_MASK 0x00F0
+#define ABIST_HMON_OUT_SHIFT 4
+
+#define ABIST_LMON_OUT_OFFSET CON2_OFFSET
+#define ABIST_LMON_OUT_MASK 0x000F
+#define ABIST_LMON_OUT_SHIFT 0
+
+#define ABIST_HMON_DATA_OFFSET CON3_OFFSET
+#define ABIST_HMON_DATA_MASK 0x00F0
+#define ABIST_HMON_DATA_SHIFT 4
+
+#define ABIST_LMON_DATA_OFFSET CON3_OFFSET
+#define ABIST_LMON_DATA_MASK 0x000F
+#define ABIST_LMON_DATA_SHIFT 0
+
+#define EOSC32_STP_CHOP_EN_OFFSET CON0_OFFSET
+#define EOSC32_STP_CHOP_EN_MASK 0x0002
+#define EOSC32_STP_CHOP_EN_SHIFT 1
+
+#define DCXO_STP_LVSH_EN_OFFSET CON0_OFFSET
+#define DCXO_STP_LVSH_EN_MASK 0x0001
+#define DCXO_STP_LVSH_EN_SHIFT 0
+
+#define EFUSE_CK_OFFSET CON0_OFFSET
+#define EFUSE_CK_MASK 0x0001
+#define EFUSE_CK_SHIFT 0
+
+#define EFUSE_A_OFFSET CON1_OFFSET
+#define EFUSE_A_MASK 0x3F00
+#define EFUSE_A_SHIFT 8
+
+#define EFUSE_DELSEL_OFFSET CON1_OFFSET
+#define EFUSE_DELSEL_MASK 0x0030
+#define EFUSE_DELSEL_SHIFT 4
+
+#define EFUSE_WE_OFFSET CON1_OFFSET
+#define EFUSE_WE_MASK 0x0004
+#define EFUSE_WE_SHIFT 2
+
+#define EFUSE_RD_OFFSET CON1_OFFSET
+#define EFUSE_RD_MASK 0x0002
+#define EFUSE_RD_SHIFT 1
+
+#define EFUSE_CKSEL_OFFSET CON1_OFFSET
+#define EFUSE_CKSEL_MASK 0x0001
+#define EFUSE_CKSEL_SHIFT 0
+
+#define EFUSE_OSC_OFFSET CON2_OFFSET
+#define EFUSE_OSC_MASK 0xFC00
+#define EFUSE_OSC_SHIFT 10
+
+#define SKIP_EFUSE_OUT_OFFSET CON2_OFFSET
+#define SKIP_EFUSE_OUT_MASK 0x0200
+#define SKIP_EFUSE_OUT_SHIFT 9
+
+#define EFUSE_FORCE_OFFSET CON2_OFFSET
+#define EFUSE_FORCE_MASK 0x0100
+#define EFUSE_FORCE_SHIFT 8
+
+#define EFUSE_MONSEL_OFFSET CON2_OFFSET
+#define EFUSE_MONSEL_MASK 0x000F
+#define EFUSE_MONSEL_SHIFT 0
+
+#define EFUSE_MONOUT_OFFSET CON3_OFFSET
+#define EFUSE_MONOUT_MASK 0x00FF
+#define EFUSE_MONOUT_SHIFT 0
+
+#define EFUSE_ICGR_OFFSET CON4_OFFSET
+#define EFUSE_ICGR_MASK 0x0F00
+#define EFUSE_ICGR_SHIFT 8
+
+#define EFUSE_BGR_OFFSET CON4_OFFSET
+#define EFUSE_BGR_MASK 0x001F
+#define EFUSE_BGR_SHIFT 0
+
+#define VRF_STATUS_OFFSET CON0_OFFSET
+#define VRF_STATUS_MASK 0x8000
+#define VRF_STATUS_SHIFT 15
+
+#define VRF_OC_FLAG_OFFSET CON0_OFFSET
+#define VRF_OC_FLAG_MASK 0x4000
+#define VRF_OC_FLAG_SHIFT 14
+
+#define VRF_OCFB_EN_OFFSET CON0_OFFSET
+#define VRF_OCFB_EN_MASK 0x2000
+#define VRF_OCFB_EN_SHIFT 13
+
+#define VRF_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VRF_OC_AUTOFF_MASK 0x1000
+#define VRF_OC_AUTOFF_SHIFT 12
+
+#define VRF_STB_EN_OFFSET CON0_OFFSET
+#define VRF_STB_EN_MASK 0x0800
+#define VRF_STB_EN_SHIFT 11
+
+#define VRF_NDIS_EN_OFFSET CON0_OFFSET
+#define VRF_NDIS_EN_MASK 0x0400
+#define VRF_NDIS_EN_SHIFT 10
+
+#define VRF_RS_OFFSET CON0_OFFSET
+#define VRF_RS_MASK 0x0004
+#define VRF_RS_SHIFT 2
+
+#define VRF_ON_SEL_OFFSET CON0_OFFSET
+#define VRF_ON_SEL_MASK 0x0002
+#define VRF_ON_SEL_SHIFT 1
+
+#define VRF_EN_OFFSET CON0_OFFSET
+#define VRF_EN_MASK 0x0001
+#define VRF_EN_SHIFT 0
+
+#define VRF_CAL_OFFSET CON1_OFFSET
+#define VRF_CAL_MASK 0x00F0
+#define VRF_CAL_SHIFT 4
+
+#define VRF_STB_TD_OFFSET CON2_OFFSET
+#define VRF_STB_TD_MASK 0x00C0
+#define VRF_STB_TD_SHIFT 6
+
+#define VRF_OC_TD_OFFSET CON2_OFFSET
+#define VRF_OC_TD_MASK 0x0030
+#define VRF_OC_TD_SHIFT 4
+
+#define VRF_EN_FORCE_OFFSET CON2_OFFSET
+#define VRF_EN_FORCE_MASK 0x0001
+#define VRF_EN_FORCE_SHIFT 0
+
+#define OCFB_CAL_OFFSET CON3_OFFSET
+#define OCFB_CAL_MASK 0x6000
+#define OCFB_CAL_SHIFT 13
+
+#define LDOS_TEST_EN_OFFSET CON3_OFFSET
+#define LDOS_TEST_EN_MASK 0x1000
+#define LDOS_TEST_EN_SHIFT 12
+
+#define VOSEL_TEST_OFFSET CON3_OFFSET
+#define VOSEL_TEST_MASK 0x0F00
+#define VOSEL_TEST_SHIFT 8
+
+#define LDOS_RSV_OFFSET CON3_OFFSET
+#define LDOS_RSV_MASK 0x00FF
+#define LDOS_RSV_SHIFT 0
+
+#define VTCXO_STATUS_OFFSET CON0_OFFSET
+#define VTCXO_STATUS_MASK 0x8000
+#define VTCXO_STATUS_SHIFT 15
+
+#define VTCXO_OC_FLAG_OFFSET CON0_OFFSET
+#define VTCXO_OC_FLAG_MASK 0x4000
+#define VTCXO_OC_FLAG_SHIFT 14
+
+#define VTCXO_OCFB_EN_OFFSET CON0_OFFSET
+#define VTCXO_OCFB_EN_MASK 0x2000
+#define VTCXO_OCFB_EN_SHIFT 13
+
+#define VTCXO_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VTCXO_OC_AUTOFF_MASK 0x1000
+#define VTCXO_OC_AUTOFF_SHIFT 12
+
+#define VTCXO_STB_EN_OFFSET CON0_OFFSET
+#define VTCXO_STB_EN_MASK 0x0800
+#define VTCXO_STB_EN_SHIFT 11
+
+#define VTCXO_NDIS_EN_OFFSET CON0_OFFSET
+#define VTCXO_NDIS_EN_MASK 0x0400
+#define VTCXO_NDIS_EN_SHIFT 10
+
+#define VTCXO_RS_OFFSET CON0_OFFSET
+#define VTCXO_RS_MASK 0x0004
+#define VTCXO_RS_SHIFT 2
+
+#define VTCXO_ON_SEL_OFFSET CON0_OFFSET
+#define VTCXO_ON_SEL_MASK 0x0002
+#define VTCXO_ON_SEL_SHIFT 1
+
+#define VTCXO_EN_OFFSET CON0_OFFSET
+#define VTCXO_EN_MASK 0x0001
+#define VTCXO_EN_SHIFT 0
+
+#define VTCXO_CAL_OFFSET CON1_OFFSET
+#define VTCXO_CAL_MASK 0x00F0
+#define VTCXO_CAL_SHIFT 4
+
+#define VTCXO_MODE_SEL_OFFSET CON1_OFFSET
+#define VTCXO_MODE_SEL_MASK 0x0002
+#define VTCXO_MODE_SEL_SHIFT 1
+
+#define VTCXO_LP_EN_OFFSET CON1_OFFSET
+#define VTCXO_LP_EN_MASK 0x0001
+#define VTCXO_LP_EN_SHIFT 0
+
+#define VTCXO_STB_TD_OFFSET CON2_OFFSET
+#define VTCXO_STB_TD_MASK 0x00C0
+#define VTCXO_STB_TD_SHIFT 6
+
+#define VTCXO_OC_TD_OFFSET CON2_OFFSET
+#define VTCXO_OC_TD_MASK 0x0030
+#define VTCXO_OC_TD_SHIFT 4
+
+#define CCI_SRCLKEN_OFFSET CON2_OFFSET
+#define CCI_SRCLKEN_MASK 0x0002
+#define CCI_SRCLKEN_SHIFT 1
+
+#define VTCXO_EN_FORCE_OFFSET CON2_OFFSET
+#define VTCXO_EN_FORCE_MASK 0x0001
+#define VTCXO_EN_FORCE_SHIFT 0
+
+#define VA_STATUS_OFFSET CON0_OFFSET
+#define VA_STATUS_MASK 0x8000
+#define VA_STATUS_SHIFT 15
+
+#define VA_OC_FLAG_OFFSET CON0_OFFSET
+#define VA_OC_FLAG_MASK 0x4000
+#define VA_OC_FLAG_SHIFT 14
+
+#define VA_OCFB_EN_OFFSET CON0_OFFSET
+#define VA_OCFB_EN_MASK 0x2000
+#define VA_OCFB_EN_SHIFT 13
+
+#define VA_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VA_OC_AUTOFF_MASK 0x1000
+#define VA_OC_AUTOFF_SHIFT 12
+
+#define VA_STB_EN_OFFSET CON0_OFFSET
+#define VA_STB_EN_MASK 0x0800
+#define VA_STB_EN_SHIFT 11
+
+#define VA_NDIS_EN_OFFSET CON0_OFFSET
+#define VA_NDIS_EN_MASK 0x0400
+#define VA_NDIS_EN_SHIFT 10
+
+#define VA_RS_OFFSET CON0_OFFSET
+#define VA_RS_MASK 0x0004
+#define VA_RS_SHIFT 2
+
+#define VA_ON_SEL_OFFSET CON0_OFFSET
+#define VA_ON_SEL_MASK 0x0002
+#define VA_ON_SEL_SHIFT 1
+
+#define VA_EN_OFFSET CON0_OFFSET
+#define VA_EN_MASK 0x0001
+#define VA_EN_SHIFT 0
+
+#define VA_CAL_OFFSET CON1_OFFSET
+#define VA_CAL_MASK 0x00F0
+#define VA_CAL_SHIFT 4
+
+#define VA_MODE_SEL_OFFSET CON1_OFFSET
+#define VA_MODE_SEL_MASK 0x0002
+#define VA_MODE_SEL_SHIFT 1
+
+#define VA_LP_EN_OFFSET CON1_OFFSET
+#define VA_LP_EN_MASK 0x0001
+#define VA_LP_EN_SHIFT 0
+
+#define VA_STB_TD_OFFSET CON2_OFFSET
+#define VA_STB_TD_MASK 0x00C0
+#define VA_STB_TD_SHIFT 6
+
+#define VA_OC_TD_OFFSET CON2_OFFSET
+#define VA_OC_TD_MASK 0x0030
+#define VA_OC_TD_SHIFT 4
+
+#define VA_EN_FORCE_OFFSET CON2_OFFSET
+#define VA_EN_FORCE_MASK 0x0001
+#define VA_EN_FORCE_SHIFT 0
+
+#define VCAMA_STATUS_OFFSET CON0_OFFSET
+#define VCAMA_STATUS_MASK 0x8000
+#define VCAMA_STATUS_SHIFT 15
+
+#define VCAMA_OC_FLAG_OFFSET CON0_OFFSET
+#define VCAMA_OC_FLAG_MASK 0x4000
+#define VCAMA_OC_FLAG_SHIFT 14
+
+#define VCAMA_OCFB_EN_OFFSET CON0_OFFSET
+#define VCAMA_OCFB_EN_MASK 0x2000
+#define VCAMA_OCFB_EN_SHIFT 13
+
+#define VCAMA_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VCAMA_OC_AUTOFF_MASK 0x1000
+#define VCAMA_OC_AUTOFF_SHIFT 12
+
+#define VCAMA_STB_EN_OFFSET CON0_OFFSET
+#define VCAMA_STB_EN_MASK 0x0800
+#define VCAMA_STB_EN_SHIFT 11
+
+#define VCAMA_NDIS_EN_OFFSET CON0_OFFSET
+#define VCAMA_NDIS_EN_MASK 0x0400
+#define VCAMA_NDIS_EN_SHIFT 10
+
+#define VCAMA_VOSEL_OFFSET CON0_OFFSET
+#define VCAMA_VOSEL_MASK 0x0030
+#define VCAMA_VOSEL_SHIFT 4
+
+#define VCAMA_RS_OFFSET CON0_OFFSET
+#define VCAMA_RS_MASK 0x0004
+#define VCAMA_RS_SHIFT 2
+
+#define VCAMA_ON_SEL_OFFSET CON0_OFFSET
+#define VCAMA_ON_SEL_MASK 0x0002
+#define VCAMA_ON_SEL_SHIFT 1
+
+#define VCAMA_EN_OFFSET CON0_OFFSET
+#define VCAMA_EN_MASK 0x0001
+#define VCAMA_EN_SHIFT 0
+
+#define VCAMA_CAL_OFFSET CON1_OFFSET
+#define VCAMA_CAL_MASK 0x00F0
+#define VCAMA_CAL_SHIFT 4
+
+#define VCAMA_STB_TD_OFFSET CON2_OFFSET
+#define VCAMA_STB_TD_MASK 0x00C0
+#define VCAMA_STB_TD_SHIFT 6
+
+#define VCAMA_OC_TD_OFFSET CON2_OFFSET
+#define VCAMA_OC_TD_MASK 0x0030
+#define VCAMA_OC_TD_SHIFT 4
+
+#define VCAMA_EN_FORCE_OFFSET CON2_OFFSET
+#define VCAMA_EN_FORCE_MASK 0x0001
+#define VCAMA_EN_FORCE_SHIFT 0
+
+#define VCAMD_STATUS_OFFSET CON0_OFFSET
+#define VCAMD_STATUS_MASK 0x8000
+#define VCAMD_STATUS_SHIFT 15
+
+#define VCAMD_OC_FLAG_OFFSET CON0_OFFSET
+#define VCAMD_OC_FLAG_MASK 0x4000
+#define VCAMD_OC_FLAG_SHIFT 14
+
+#define VCAMD_OCFB_EN_OFFSET CON0_OFFSET
+#define VCAMD_OCFB_EN_MASK 0x2000
+#define VCAMD_OCFB_EN_SHIFT 13
+
+#define VCAMD_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VCAMD_OC_AUTOFF_MASK 0x1000
+#define VCAMD_OC_AUTOFF_SHIFT 12
+
+#define VCAMD_STB_EN_OFFSET CON0_OFFSET
+#define VCAMD_STB_EN_MASK 0x0800
+#define VCAMD_STB_EN_SHIFT 11
+
+#define VCAMD_NDIS_EN_OFFSET CON0_OFFSET
+#define VCAMD_NDIS_EN_MASK 0x0400
+#define VCAMD_NDIS_EN_SHIFT 10
+
+#define VCAMD_VOSEL_OFFSET CON0_OFFSET
+#define VCAMD_VOSEL_MASK 0x0070
+#define VCAMD_VOSEL_SHIFT 4
+
+#define VCAMD_RS_OFFSET CON0_OFFSET
+#define VCAMD_RS_MASK 0x0004
+#define VCAMD_RS_SHIFT 2
+
+#define VCAMD_ON_SEL_OFFSET CON0_OFFSET
+#define VCAMD_ON_SEL_MASK 0x0002
+#define VCAMD_ON_SEL_SHIFT 1
+
+#define VCAMD_EN_OFFSET CON0_OFFSET
+#define VCAMD_EN_MASK 0x0001
+#define VCAMD_EN_SHIFT 0
+
+#define VCAMD_CAL_OFFSET CON1_OFFSET
+#define VCAMD_CAL_MASK 0x00F0
+#define VCAMD_CAL_SHIFT 4
+
+#define VCAMD_STB_TD_OFFSET CON2_OFFSET
+#define VCAMD_STB_TD_MASK 0x00C0
+#define VCAMD_STB_TD_SHIFT 6
+
+#define VCAMD_OC_TD_OFFSET CON2_OFFSET
+#define VCAMD_OC_TD_MASK 0x0030
+#define VCAMD_OC_TD_SHIFT 4
+
+#define VCAMD_EN_FORCE_OFFSET CON2_OFFSET
+#define VCAMD_EN_FORCE_MASK 0x0001
+#define VCAMD_EN_FORCE_SHIFT 0
+
+#define VIO28_STATUS_OFFSET CON0_OFFSET
+#define VIO28_STATUS_MASK 0x8000
+#define VIO28_STATUS_SHIFT 15
+
+#define VIO28_OC_FLAG_OFFSET CON0_OFFSET
+#define VIO28_OC_FLAG_MASK 0x4000
+#define VIO28_OC_FLAG_SHIFT 14
+
+#define VIO28_OCFB_EN_OFFSET CON0_OFFSET
+#define VIO28_OCFB_EN_MASK 0x2000
+#define VIO28_OCFB_EN_SHIFT 13
+
+#define VIO28_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VIO28_OC_AUTOFF_MASK 0x1000
+#define VIO28_OC_AUTOFF_SHIFT 12
+
+#define VIO28_STB_EN_OFFSET CON0_OFFSET
+#define VIO28_STB_EN_MASK 0x0800
+#define VIO28_STB_EN_SHIFT 11
+
+#define VIO28_NDIS_EN_OFFSET CON0_OFFSET
+#define VIO28_NDIS_EN_MASK 0x0400
+#define VIO28_NDIS_EN_SHIFT 10
+
+#define VIO28_RS_OFFSET CON0_OFFSET
+#define VIO28_RS_MASK 0x0004
+#define VIO28_RS_SHIFT 2
+
+#define VIO28_ON_SEL_OFFSET CON0_OFFSET
+#define VIO28_ON_SEL_MASK 0x0002
+#define VIO28_ON_SEL_SHIFT 1
+
+#define VIO28_EN_OFFSET CON0_OFFSET
+#define VIO28_EN_MASK 0x0001
+#define VIO28_EN_SHIFT 0
+
+#define VIO28_CAL_OFFSET CON1_OFFSET
+#define VIO28_CAL_MASK 0x00F0
+#define VIO28_CAL_SHIFT 4
+
+#define VIO28_STB_TD_OFFSET CON2_OFFSET
+#define VIO28_STB_TD_MASK 0x00C0
+#define VIO28_STB_TD_SHIFT 6
+
+#define VIO28_OC_TD_OFFSET CON2_OFFSET
+#define VIO28_OC_TD_MASK 0x0030
+#define VIO28_OC_TD_SHIFT 4
+
+#define VIO28_EN_FORCE_OFFSET CON2_OFFSET
+#define VIO28_EN_FORCE_MASK 0x0001
+#define VIO28_EN_FORCE_SHIFT 0
+
+#define VUSB_STATUS_OFFSET CON0_OFFSET
+#define VUSB_STATUS_MASK 0x8000
+#define VUSB_STATUS_SHIFT 15
+
+#define VUSB_OC_FLAG_OFFSET CON0_OFFSET
+#define VUSB_OC_FLAG_MASK 0x4000
+#define VUSB_OC_FLAG_SHIFT 14
+
+#define VUSB_OCFB_EN_OFFSET CON0_OFFSET
+#define VUSB_OCFB_EN_MASK 0x2000
+#define VUSB_OCFB_EN_SHIFT 13
+
+#define VUSB_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VUSB_OC_AUTOFF_MASK 0x1000
+#define VUSB_OC_AUTOFF_SHIFT 12
+
+#define VUSB_STB_EN_OFFSET CON0_OFFSET
+#define VUSB_STB_EN_MASK 0x0800
+#define VUSB_STB_EN_SHIFT 11
+
+#define VUSB_NDIS_EN_OFFSET CON0_OFFSET
+#define VUSB_NDIS_EN_MASK 0x0400
+#define VUSB_NDIS_EN_SHIFT 10
+
+#define VUSB_RS_OFFSET CON0_OFFSET
+#define VUSB_RS_MASK 0x0004
+#define VUSB_RS_SHIFT 2
+
+#define VUSB_ON_SEL_OFFSET CON0_OFFSET
+#define VUSB_ON_SEL_MASK 0x0002
+#define VUSB_ON_SEL_SHIFT 1
+
+#define VUSB_EN_OFFSET CON0_OFFSET
+#define VUSB_EN_MASK 0x0001
+#define VUSB_EN_SHIFT 0
+
+#define VUSB_CAL_OFFSET CON1_OFFSET
+#define VUSB_CAL_MASK 0x00F0
+#define VUSB_CAL_SHIFT 4
+
+#define VUSB_STB_TD_OFFSET CON2_OFFSET
+#define VUSB_STB_TD_MASK 0x00C0
+#define VUSB_STB_TD_SHIFT 6
+
+#define VUSB_OC_TD_OFFSET CON2_OFFSET
+#define VUSB_OC_TD_MASK 0x0030
+#define VUSB_OC_TD_SHIFT 4
+
+#define VUSB_EN_FORCE_OFFSET CON2_OFFSET
+#define VUSB_EN_FORCE_MASK 0x0001
+#define VUSB_EN_FORCE_SHIFT 0
+
+#define VBT_STATUS_OFFSET CON0_OFFSET
+#define VBT_STATUS_MASK 0x8000
+#define VBT_STATUS_SHIFT 15
+
+#define VBT_OC_FLAG_OFFSET CON0_OFFSET
+#define VBT_OC_FLAG_MASK 0x4000
+#define VBT_OC_FLAG_SHIFT 14
+
+#define VBT_OCFB_EN_OFFSET CON0_OFFSET
+#define VBT_OCFB_EN_MASK 0x2000
+#define VBT_OCFB_EN_SHIFT 13
+
+#define VBT_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VBT_OC_AUTOFF_MASK 0x1000
+#define VBT_OC_AUTOFF_SHIFT 12
+
+#define VBT_STB_EN_OFFSET CON0_OFFSET
+#define VBT_STB_EN_MASK 0x0800
+#define VBT_STB_EN_SHIFT 11
+
+#define VBT_NDIS_EN_OFFSET CON0_OFFSET
+#define VBT_NDIS_EN_MASK 0x0400
+#define VBT_NDIS_EN_SHIFT 10
+
+#define VBT_VOSEL_OFFSET CON0_OFFSET
+#define VBT_VOSEL_MASK 0x0070
+#define VBT_VOSEL_SHIFT 4
+
+#define VBT_RS_OFFSET CON0_OFFSET
+#define VBT_RS_MASK 0x0004
+#define VBT_RS_SHIFT 2
+
+#define VBT_ON_SEL_OFFSET CON0_OFFSET
+#define VBT_ON_SEL_MASK 0x0002
+#define VBT_ON_SEL_SHIFT 1
+
+#define VBT_EN_OFFSET CON0_OFFSET
+#define VBT_EN_MASK 0x0001
+#define VBT_EN_SHIFT 0
+
+#define VBT_CAL_OFFSET CON1_OFFSET
+#define VBT_CAL_MASK 0x00F0
+#define VBT_CAL_SHIFT 4
+
+#define VBT_STB_TD_OFFSET CON2_OFFSET
+#define VBT_STB_TD_MASK 0x00C0
+#define VBT_STB_TD_SHIFT 6
+
+#define VBT_OC_TD_OFFSET CON2_OFFSET
+#define VBT_OC_TD_MASK 0x0030
+#define VBT_OC_TD_SHIFT 4
+
+#define VBT_EN_FORCE_OFFSET CON2_OFFSET
+#define VBT_EN_FORCE_MASK 0x0001
+#define VBT_EN_FORCE_SHIFT 0
+
+#define VSIM_STATUS_OFFSET CON0_OFFSET
+#define VSIM_STATUS_MASK 0x8000
+#define VSIM_STATUS_SHIFT 15
+
+#define VSIM_OC_FLAG_OFFSET CON0_OFFSET
+#define VSIM_OC_FLAG_MASK 0x4000
+#define VSIM_OC_FLAG_SHIFT 14
+
+#define VSIM_OCFB_EN_OFFSET CON0_OFFSET
+#define VSIM_OCFB_EN_MASK 0x2000
+#define VSIM_OCFB_EN_SHIFT 13
+
+#define VSIM_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VSIM_OC_AUTOFF_MASK 0x1000
+#define VSIM_OC_AUTOFF_SHIFT 12
+
+#define VSIM_STB_EN_OFFSET CON0_OFFSET
+#define VSIM_STB_EN_MASK 0x0800
+#define VSIM_STB_EN_SHIFT 11
+
+#define VSIM_NDIS_EN_OFFSET CON0_OFFSET
+#define VSIM_NDIS_EN_MASK 0x0400
+#define VSIM_NDIS_EN_SHIFT 10
+
+#define VSIM_VOSEL_OFFSET CON0_OFFSET
+#define VSIM_VOSEL_MASK 0x0010
+#define VSIM_VOSEL_SHIFT 4
+
+#define VSIM_RS_OFFSET CON0_OFFSET
+#define VSIM_RS_MASK 0x0004
+#define VSIM_RS_SHIFT 2
+
+#define VSIM_ON_SEL_OFFSET CON0_OFFSET
+#define VSIM_ON_SEL_MASK 0x0002
+#define VSIM_ON_SEL_SHIFT 1
+
+#define VSIM_EN_OFFSET CON0_OFFSET
+#define VSIM_EN_MASK 0x0001
+#define VSIM_EN_SHIFT 0
+
+#define VSIM_CAL_OFFSET CON1_OFFSET
+#define VSIM_CAL_MASK 0x00F0
+#define VSIM_CAL_SHIFT 4
+
+#define VSIM_STB_TD_OFFSET CON2_OFFSET
+#define VSIM_STB_TD_MASK 0x00C0
+#define VSIM_STB_TD_SHIFT 6
+
+#define VSIM_OC_TD_OFFSET CON2_OFFSET
+#define VSIM_OC_TD_MASK 0x0030
+#define VSIM_OC_TD_SHIFT 4
+
+#define VSIM_GPLDO_EN_OFFSET CON2_OFFSET
+#define VSIM_GPLDO_EN_MASK 0x0002
+#define VSIM_GPLDO_EN_SHIFT 1
+
+#define VSIM_EN_FORCE_OFFSET CON2_OFFSET
+#define VSIM_EN_FORCE_MASK 0x0001
+#define VSIM_EN_FORCE_SHIFT 0
+
+#define VSIM_CSTOP_OFFSET CON3_OFFSET
+#define VSIM_CSTOP_MASK 0x0400
+#define VSIM_CSTOP_SHIFT 10
+
+#define VSIM_SRP_OFFSET CON3_OFFSET
+#define VSIM_SRP_MASK 0x0300
+#define VSIM_SRP_SHIFT 8
+
+#define VSIM_SRN_OFFSET CON3_OFFSET
+#define VSIM_SRN_MASK 0x00C0
+#define VSIM_SRN_SHIFT 6
+
+#define VSIM_BIAS_OFFSET CON3_OFFSET
+#define VSIM_BIAS_MASK 0x0030
+#define VSIM_BIAS_SHIFT 4
+
+#define SIMIO_DRV_OFFSET CON3_OFFSET
+#define SIMIO_DRV_MASK 0x000E
+#define SIMIO_DRV_SHIFT 1
+
+#define VSIM2_STATUS_OFFSET CON0_OFFSET
+#define VSIM2_STATUS_MASK 0x8000
+#define VSIM2_STATUS_SHIFT 15
+
+#define VSIM2_OC_FLAG_OFFSET CON0_OFFSET
+#define VSIM2_OC_FLAG_MASK 0x4000
+#define VSIM2_OC_FLAG_SHIFT 14
+
+#define VSIM2_OCFB_EN_OFFSET CON0_OFFSET
+#define VSIM2_OCFB_EN_MASK 0x2000
+#define VSIM2_OCFB_EN_SHIFT 13
+
+#define VSIM2_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VSIM2_OC_AUTOFF_MASK 0x1000
+#define VSIM2_OC_AUTOFF_SHIFT 12
+
+#define VSIM2_STB_EN_OFFSET CON0_OFFSET
+#define VSIM2_STB_EN_MASK 0x0800
+#define VSIM2_STB_EN_SHIFT 11
+
+#define VSIM2_NDIS_EN_OFFSET CON0_OFFSET
+#define VSIM2_NDIS_EN_MASK 0x0400
+#define VSIM2_NDIS_EN_SHIFT 10
+
+#define VSIM2_VOSEL_OFFSET CON0_OFFSET
+#define VSIM2_VOSEL_MASK 0x0070
+#define VSIM2_VOSEL_SHIFT 4
+
+#define VSIM2_RS_OFFSET CON0_OFFSET
+#define VSIM2_RS_MASK 0x0004
+#define VSIM2_RS_SHIFT 2
+
+#define VSIM2_ON_SEL_OFFSET CON0_OFFSET
+#define VSIM2_ON_SEL_MASK 0x0002
+#define VSIM2_ON_SEL_SHIFT 1
+
+#define VSIM2_EN_OFFSET CON0_OFFSET
+#define VSIM2_EN_MASK 0x0001
+#define VSIM2_EN_SHIFT 0
+
+#define VSIM2_CAL_OFFSET CON1_OFFSET
+#define VSIM2_CAL_MASK 0x00F0
+#define VSIM2_CAL_SHIFT 4
+
+#define VSIM2_STB_TD_OFFSET CON2_OFFSET
+#define VSIM2_STB_TD_MASK 0x00C0
+#define VSIM2_STB_TD_SHIFT 6
+
+#define VSIM2_OC_TD_OFFSET CON2_OFFSET
+#define VSIM2_OC_TD_MASK 0x0030
+#define VSIM2_OC_TD_SHIFT 4
+
+#define VSIM2_GPLDO_EN_OFFSET CON2_OFFSET
+#define VSIM2_GPLDO_EN_MASK 0x0002
+#define VSIM2_GPLDO_EN_SHIFT 1
+
+#define VSIM2_EN_FORCE_OFFSET CON2_OFFSET
+#define VSIM2_EN_FORCE_MASK 0x0001
+#define VSIM2_EN_FORCE_SHIFT 0
+
+#define GPIO_SIO2_OFFSET CON3_OFFSET
+#define GPIO_SIO2_MASK 0x8000
+#define GPIO_SIO2_SHIFT 15
+
+#define GPIO_SCLK2_OFFSET CON3_OFFSET
+#define GPIO_SCLK2_MASK 0x4000
+#define GPIO_SCLK2_SHIFT 14
+
+#define GPIO_SRST2_OFFSET CON3_OFFSET
+#define GPIO_SRST2_MASK 0x2000
+#define GPIO_SRST2_SHIFT 13
+
+#define SIM2_CSTOP_OFFSET CON3_OFFSET
+#define SIM2_CSTOP_MASK 0x0400
+#define SIM2_CSTOP_SHIFT 10
+
+#define SIM2_SRP_OFFSET CON3_OFFSET
+#define SIM2_SRP_MASK 0x0300
+#define SIM2_SRP_SHIFT 8
+
+#define SIM2_SRN_OFFSET CON3_OFFSET
+#define SIM2_SRN_MASK 0x00C0
+#define SIM2_SRN_SHIFT 6
+
+#define SIM2_BIAS_OFFSET CON3_OFFSET
+#define SIM2_BIAS_MASK 0x0030
+#define SIM2_BIAS_SHIFT 4
+
+#define SIMIO2_DRV_OFFSET CON3_OFFSET
+#define SIMIO2_DRV_MASK 0x000E
+#define SIMIO2_DRV_SHIFT 1
+
+#define SIM2_GPIO_EN_OFFSET CON3_OFFSET
+#define SIM2_GPIO_EN_MASK 0x0001
+#define SIM2_GPIO_EN_SHIFT 0
+
+#define VRTC_STATUS_OFFSET CON0_OFFSET
+#define VRTC_STATUS_MASK 0x8000
+#define VRTC_STATUS_SHIFT 15
+
+#define VRTC_OC_FLAG_OFFSET CON0_OFFSET
+#define VRTC_OC_FLAG_MASK 0x4000
+#define VRTC_OC_FLAG_SHIFT 14
+
+#define VRTC_OCFB_EN_OFFSET CON0_OFFSET
+#define VRTC_OCFB_EN_MASK 0x2000
+#define VRTC_OCFB_EN_SHIFT 13
+
+#define VRTC_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VRTC_OC_AUTOFF_MASK 0x1000
+#define VRTC_OC_AUTOFF_SHIFT 12
+
+#define VRTC_STB_EN_OFFSET CON0_OFFSET
+#define VRTC_STB_EN_MASK 0x0800
+#define VRTC_STB_EN_SHIFT 11
+
+#define VRTC_NDIS_EN_OFFSET CON0_OFFSET
+#define VRTC_NDIS_EN_MASK 0x0400
+#define VRTC_NDIS_EN_SHIFT 10
+
+#define VRTC_RS_OFFSET CON0_OFFSET
+#define VRTC_RS_MASK 0x0004
+#define VRTC_RS_SHIFT 2
+
+#define VRTC_ON_SEL_OFFSET CON0_OFFSET
+#define VRTC_ON_SEL_MASK 0x0002
+#define VRTC_ON_SEL_SHIFT 1
+
+#define VRTC_EN_OFFSET CON0_OFFSET
+#define VRTC_EN_MASK 0x0001
+#define VRTC_EN_SHIFT 0
+
+#define VRTC_CAL_OFFSET CON1_OFFSET
+#define VRTC_CAL_MASK 0x00F0
+#define VRTC_CAL_SHIFT 4
+
+#define VRTC_STB_TD_OFFSET CON2_OFFSET
+#define VRTC_STB_TD_MASK 0x00C0
+#define VRTC_STB_TD_SHIFT 6
+
+#define VRTC_OC_TD_OFFSET CON2_OFFSET
+#define VRTC_OC_TD_MASK 0x0030
+#define VRTC_OC_TD_SHIFT 4
+
+#define VRTC_EN_FORCE_OFFSET CON2_OFFSET
+#define VRTC_EN_FORCE_MASK 0x0001
+#define VRTC_EN_FORCE_SHIFT 0
+
+#define VIBR_STATUS_OFFSET CON0_OFFSET
+#define VIBR_STATUS_MASK 0x8000
+#define VIBR_STATUS_SHIFT 15
+
+#define VIBR_OC_FLAG_OFFSET CON0_OFFSET
+#define VIBR_OC_FLAG_MASK 0x4000
+#define VIBR_OC_FLAG_SHIFT 14
+
+#define VIBR_OCFB_EN_OFFSET CON0_OFFSET
+#define VIBR_OCFB_EN_MASK 0x2000
+#define VIBR_OCFB_EN_SHIFT 13
+
+#define VIBR_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VIBR_OC_AUTOFF_MASK 0x1000
+#define VIBR_OC_AUTOFF_SHIFT 12
+
+#define VIBR_STB_EN_OFFSET CON0_OFFSET
+#define VIBR_STB_EN_MASK 0x0800
+#define VIBR_STB_EN_SHIFT 11
+
+#define VIBR_NDIS_EN_OFFSET CON0_OFFSET
+#define VIBR_NDIS_EN_MASK 0x0400
+#define VIBR_NDIS_EN_SHIFT 10
+
+#define VIBR_VOSEL_OFFSET CON0_OFFSET
+#define VIBR_VOSEL_MASK 0x0070
+#define VIBR_VOSEL_SHIFT 4
+
+#define VIBR_RS_OFFSET CON0_OFFSET
+#define VIBR_RS_MASK 0x0004
+#define VIBR_RS_SHIFT 2
+
+#define VIBR_ON_SEL_OFFSET CON0_OFFSET
+#define VIBR_ON_SEL_MASK 0x0002
+#define VIBR_ON_SEL_SHIFT 1
+
+#define VIBR_EN_OFFSET CON0_OFFSET
+#define VIBR_EN_MASK 0x0001
+#define VIBR_EN_SHIFT 0
+
+#define VIBR_STB_SEL_OFFSET CON1_OFFSET
+#define VIBR_STB_SEL_MASK 0x1000
+#define VIBR_STB_SEL_SHIFT 12
+
+#define VIBR_CAL_OFFSET CON1_OFFSET
+#define VIBR_CAL_MASK 0x00F0
+#define VIBR_CAL_SHIFT 4
+
+#define VIBR_STB_TD_OFFSET CON2_OFFSET
+#define VIBR_STB_TD_MASK 0x00C0
+#define VIBR_STB_TD_SHIFT 6
+
+#define VIBR_OC_TD_OFFSET CON2_OFFSET
+#define VIBR_OC_TD_MASK 0x0030
+#define VIBR_OC_TD_SHIFT 4
+
+#define VIBR_EN_FORCE_OFFSET CON2_OFFSET
+#define VIBR_EN_FORCE_MASK 0x0001
+#define VIBR_EN_FORCE_SHIFT 0
+
+#define VMC_STATUS_OFFSET CON0_OFFSET
+#define VMC_STATUS_MASK 0x8000
+#define VMC_STATUS_SHIFT 15
+
+#define VMC_OC_FLAG_OFFSET CON0_OFFSET
+#define VMC_OC_FLAG_MASK 0x4000
+#define VMC_OC_FLAG_SHIFT 14
+
+#define VMC_OCFB_EN_OFFSET CON0_OFFSET
+#define VMC_OCFB_EN_MASK 0x2000
+#define VMC_OCFB_EN_SHIFT 13
+
+#define VMC_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VMC_OC_AUTOFF_MASK 0x1000
+#define VMC_OC_AUTOFF_SHIFT 12
+
+#define VMC_STB_EN_OFFSET CON0_OFFSET
+#define VMC_STB_EN_MASK 0x0800
+#define VMC_STB_EN_SHIFT 11
+
+#define VMC_NDIS_EN_OFFSET CON0_OFFSET
+#define VMC_NDIS_EN_MASK 0x0400
+#define VMC_NDIS_EN_SHIFT 10
+
+#define VMC_VOSEL_OFFSET CON0_OFFSET
+#define VMC_VOSEL_MASK 0x0070
+#define VMC_VOSEL_SHIFT 4
+
+#define VMC_RS_OFFSET CON0_OFFSET
+#define VMC_RS_MASK 0x0004
+#define VMC_RS_SHIFT 2
+
+#define VMC_ON_SEL_OFFSET CON0_OFFSET
+#define VMC_ON_SEL_MASK 0x0002
+#define VMC_ON_SEL_SHIFT 1
+
+#define VMC_EN_OFFSET CON0_OFFSET
+#define VMC_EN_MASK 0x0001
+#define VMC_EN_SHIFT 0
+
+#define VMC_STB_SEL_OFFSET CON1_OFFSET
+#define VMC_STB_SEL_MASK 0x1000
+#define VMC_STB_SEL_SHIFT 12
+
+#define VMC_CAL_OFFSET CON1_OFFSET
+#define VMC_CAL_MASK 0x00F0
+#define VMC_CAL_SHIFT 4
+
+#define VMC_STB_TD_OFFSET CON2_OFFSET
+#define VMC_STB_TD_MASK 0x00C0
+#define VMC_STB_TD_SHIFT 6
+
+#define VMC_OC_TD_OFFSET CON2_OFFSET
+#define VMC_OC_TD_MASK 0x0030
+#define VMC_OC_TD_SHIFT 4
+
+#define VMC_EN_FORCE_OFFSET CON2_OFFSET
+#define VMC_EN_FORCE_MASK 0x0001
+#define VMC_EN_FORCE_SHIFT 0
+
+#define VIO18_STATUS_OFFSET CON0_OFFSET
+#define VIO18_STATUS_MASK 0x8000
+#define VIO18_STATUS_SHIFT 15
+
+#define VIO18_OC_FLAG_OFFSET CON0_OFFSET
+#define VIO18_OC_FLAG_MASK 0x4000
+#define VIO18_OC_FLAG_SHIFT 14
+
+#define VIO18_OCFB_EN_OFFSET CON0_OFFSET
+#define VIO18_OCFB_EN_MASK 0x2000
+#define VIO18_OCFB_EN_SHIFT 13
+
+#define VIO18_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VIO18_OC_AUTOFF_MASK 0x1000
+#define VIO18_OC_AUTOFF_SHIFT 12
+
+#define VIO18_NDIS_EN_OFFSET CON0_OFFSET
+#define VIO18_NDIS_EN_MASK 0x0400
+#define VIO18_NDIS_EN_SHIFT 10
+
+#define VIO18_RS_OFFSET CON0_OFFSET
+#define VIO18_RS_MASK 0x0004
+#define VIO18_RS_SHIFT 2
+
+#define VIO18_ON_SEL_OFFSET CON0_OFFSET
+#define VIO18_ON_SEL_MASK 0x0002
+#define VIO18_ON_SEL_SHIFT 1
+
+#define VIO18_EN_OFFSET CON0_OFFSET
+#define VIO18_EN_MASK 0x0001
+#define VIO18_EN_SHIFT 0
+
+#define VIO18_CAL_OFFSET CON1_OFFSET
+#define VIO18_CAL_MASK 0x00F0
+#define VIO18_CAL_SHIFT 4
+
+#define VIO18_STB_TD_OFFSET CON2_OFFSET
+#define VIO18_STB_TD_MASK 0x00C0
+#define VIO18_STB_TD_SHIFT 6
+
+#define VIO18_OC_TD_OFFSET CON2_OFFSET
+#define VIO18_OC_TD_MASK 0x0030
+#define VIO18_OC_TD_SHIFT 4
+
+#define VIO18_EN_FORCE_OFFSET CON2_OFFSET
+#define VIO18_EN_FORCE_MASK 0x0001
+#define VIO18_EN_FORCE_SHIFT 0
+
+#define VSF_STATUS_OFFSET CON0_OFFSET
+#define VSF_STATUS_MASK 0x8000
+#define VSF_STATUS_SHIFT 15
+
+#define VSF_OC_FLAG_OFFSET CON0_OFFSET
+#define VSF_OC_FLAG_MASK 0x4000
+#define VSF_OC_FLAG_SHIFT 14
+
+#define VSF_OCFB_EN_OFFSET CON0_OFFSET
+#define VSF_OCFB_EN_MASK 0x2000
+#define VSF_OCFB_EN_SHIFT 13
+
+#define VSF_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VSF_OC_AUTOFF_MASK 0x1000
+#define VSF_OC_AUTOFF_SHIFT 12
+
+#define VSF_STB_EN_OFFSET CON0_OFFSET
+#define VSF_STB_EN_MASK 0x0800
+#define VSF_STB_EN_SHIFT 11
+
+#define VSF_NDIS_EN_OFFSET CON0_OFFSET
+#define VSF_NDIS_EN_MASK 0x0400
+#define VSF_NDIS_EN_SHIFT 10
+
+#define VSF_VOSEL_OFFSET CON0_OFFSET
+#define VSF_VOSEL_MASK 0x0070
+#define VSF_VOSEL_SHIFT 4
+
+#define VSF_RS_OFFSET CON0_OFFSET
+#define VSF_RS_MASK 0x0004
+#define VSF_RS_SHIFT 2
+
+#define VSF_EN_OFFSET CON0_OFFSET
+#define VSF_EN_MASK 0x0001
+#define VSF_EN_SHIFT 0
+
+#define VSF_CAL_OFFSET CON1_OFFSET
+#define VSF_CAL_MASK 0x00F0
+#define VSF_CAL_SHIFT 4
+
+#define VSF_STB_TD_OFFSET CON2_OFFSET
+#define VSF_STB_TD_MASK 0x00C0
+#define VSF_STB_TD_SHIFT 6
+
+#define VSF_OC_TD_OFFSET CON2_OFFSET
+#define VSF_OC_TD_MASK 0x0030
+#define VSF_OC_TD_SHIFT 4
+
+#define VSF_EN_FORCE_OFFSET CON2_OFFSET
+#define VSF_EN_FORCE_MASK 0x0001
+#define VSF_EN_FORCE_SHIFT 0
+
+#define VSF_AUTOFF_DLY_SEL_OFFSET CON3_OFFSET
+#define VSF_AUTOFF_DLY_SEL_MASK 0x00F0
+#define VSF_AUTOFF_DLY_SEL_SHIFT 4
+
+#define VSF_AUTOFF_EN_OFFSET CON3_OFFSET
+#define VSF_AUTOFF_EN_MASK 0x0001
+#define VSF_AUTOFF_EN_SHIFT 0
+
+#define VCORE_STATUS_OFFSET CON0_OFFSET
+#define VCORE_STATUS_MASK 0x8000
+#define VCORE_STATUS_SHIFT 15
+
+#define VCORE_OC_FLAG_OFFSET CON0_OFFSET
+#define VCORE_OC_FLAG_MASK 0x4000
+#define VCORE_OC_FLAG_SHIFT 14
+
+#define VCORE_OCFB_EN_OFFSET CON0_OFFSET
+#define VCORE_OCFB_EN_MASK 0x2000
+#define VCORE_OCFB_EN_SHIFT 13
+
+#define VCORE_OC_AUTOFF_OFFSET CON0_OFFSET
+#define VCORE_OC_AUTOFF_MASK 0x1000
+#define VCORE_OC_AUTOFF_SHIFT 12
+
+#define VCORE_STB_EN_OFFSET CON0_OFFSET
+#define VCORE_STB_EN_MASK 0x0800
+#define VCORE_STB_EN_SHIFT 11
+
+#define VCORE_ANTIUNSH_DN_OFFSET CON0_OFFSET
+#define VCORE_ANTIUNSH_DN_MASK 0x0400
+#define VCORE_ANTIUNSH_DN_SHIFT 10
+
+#define VCORE_VFBADJ_OFFSET CON0_OFFSET
+#define VCORE_VFBADJ_MASK 0x01F0
+#define VCORE_VFBADJ_SHIFT 4
+
+#define VCORE_SFSTREN_OFFSET CON0_OFFSET
+#define VCORE_SFSTREN_MASK 0x0008
+#define VCORE_SFSTREN_SHIFT 3
+
+#define VCORE_RS_OFFSET CON0_OFFSET
+#define VCORE_RS_MASK 0x0004
+#define VCORE_RS_SHIFT 2
+
+#define VCORE_ON_SEL_OFFSET CON0_OFFSET
+#define VCORE_ON_SEL_MASK 0x0002
+#define VCORE_ON_SEL_SHIFT 1
+
+#define VCORE_EN_OFFSET CON0_OFFSET
+#define VCORE_EN_MASK 0x0001
+#define VCORE_EN_SHIFT 0
+
+#define VCORE_BUCK_STATUS_OFFSET CON1_OFFSET
+#define VCORE_BUCK_STATUS_MASK 0x8000
+#define VCORE_BUCK_STATUS_SHIFT 15
+
+#define VCORE_CPMCKSEL_OFFSET CON1_OFFSET
+#define VCORE_CPMCKSEL_MASK 0x0400
+#define VCORE_CPMCKSEL_SHIFT 10
+
+#define VCORE_VFBADJ_SLEEP_OFFSET CON1_OFFSET
+#define VCORE_VFBADJ_SLEEP_MASK 0x01F0
+#define VCORE_VFBADJ_SLEEP_SHIFT 4
+
+#define VCORE_CPMCKSEL_MODE_OFFSET CON1_OFFSET
+#define VCORE_CPMCKSEL_MODE_MASK 0x0002
+#define VCORE_CPMCKSEL_MODE_SHIFT 1
+
+#define VCORE_MODESET_OFFSET CON1_OFFSET
+#define VCORE_MODESET_MASK 0x0001
+#define VCORE_MODESET_SHIFT 0
+
+#define VCORE_VOSEL_OFFSET CON2_OFFSET
+#define VCORE_VOSEL_MASK 0x0007
+#define VCORE_VOSEL_SHIFT 0
+
+#define VCORE_ICAL_LDO_OFFSET CON3_OFFSET
+#define VCORE_ICAL_LDO_MASK 0x3000
+#define VCORE_ICAL_LDO_SHIFT 12
+
+#define VCORE_OC_WND_OFFSET CON3_OFFSET
+#define VCORE_OC_WND_MASK 0x0C00
+#define VCORE_OC_WND_SHIFT 10
+
+#define VCORE_OC_THD_OFFSET CON3_OFFSET
+#define VCORE_OC_THD_MASK 0x0300
+#define VCORE_OC_THD_SHIFT 8
+
+#define VCORE_STB_TD_OFFSET CON3_OFFSET
+#define VCORE_STB_TD_MASK 0x00C0
+#define VCORE_STB_TD_SHIFT 6
+
+#define VCORE_OC_TD_OFFSET CON3_OFFSET
+#define VCORE_OC_TD_MASK 0x0030
+#define VCORE_OC_TD_SHIFT 4
+
+#define VCORE_EN_FORCE_OFFSET CON3_OFFSET
+#define VCORE_EN_FORCE_MASK 0x0001
+#define VCORE_EN_FORCE_SHIFT 0
+
+#define VCORE_RSV_OFFSET CON4_OFFSET
+#define VCORE_RSV_MASK 0xFF00
+#define VCORE_RSV_SHIFT 8
+
+#define VCORE_ADJCKSEL_OFFSET CON4_OFFSET
+#define VCORE_ADJCKSEL_MASK 0x0070
+#define VCORE_ADJCKSEL_SHIFT 4
+
+#define VCORE_SLEW_OFFSET CON4_OFFSET
+#define VCORE_SLEW_MASK 0x000C
+#define VCORE_SLEW_SHIFT 2
+
+#define VCORE_SLEW_NMOS_OFFSET CON4_OFFSET
+#define VCORE_SLEW_NMOS_MASK 0x0003
+#define VCORE_SLEW_NMOS_SHIFT 0
+
+#define VCORE_ZX_PDN_OFFSET CON5_OFFSET
+#define VCORE_ZX_PDN_MASK 0x8000
+#define VCORE_ZX_PDN_SHIFT 15
+
+#define VCORE_GMSEL_OFFSET CON5_OFFSET
+#define VCORE_GMSEL_MASK 0x4000
+#define VCORE_GMSEL_SHIFT 14
+
+#define VCORE_BURST_OFFSET CON5_OFFSET
+#define VCORE_BURST_MASK 0x3000
+#define VCORE_BURST_SHIFT 12
+
+#define VCORE_CSL_OFFSET CON5_OFFSET
+#define VCORE_CSL_MASK 0x0700
+#define VCORE_CSL_SHIFT 8
+
+#define VCORE_RZSEL_OFFSET CON5_OFFSET
+#define VCORE_RZSEL_MASK 0x0070
+#define VCORE_RZSEL_SHIFT 4
+
+#define VCORE_CSR_OFFSET CON5_OFFSET
+#define VCORE_CSR_MASK 0x000F
+#define VCORE_CSR_SHIFT 0
+
+#define BUCK_CKS_CHG_OFFSET CON6_OFFSET
+#define BUCK_CKS_CHG_MASK 0x8000
+#define BUCK_CKS_CHG_SHIFT 15
+
+#define BUCK_CKS_PRG_OFFSET CON6_OFFSET
+#define BUCK_CKS_PRG_MASK 0x003F
+#define BUCK_CKS_PRG_SHIFT 0
+
+#define VCDT_HV_VTH_OFFSET CON0_OFFSET
+#define VCDT_HV_VTH_MASK 0xF000
+#define VCDT_HV_VTH_SHIFT 12
+
+#define VCDT_LV_VTH_OFFSET CON0_OFFSET
+#define VCDT_LV_VTH_MASK 0x0F00
+#define VCDT_LV_VTH_SHIFT 8
+
+#define VCDT_HV_DET_OFFSET CON0_OFFSET
+#define VCDT_HV_DET_MASK 0x0080
+#define VCDT_HV_DET_SHIFT 7
+
+#define VCDT_LV_DET_OFFSET CON0_OFFSET
+#define VCDT_LV_DET_MASK 0x0040
+#define VCDT_LV_DET_SHIFT 6
+
+#define CHRDET_OFFSET CON0_OFFSET
+#define CHRDET_MASK 0x0020
+#define CHRDET_SHIFT 5
+
+#define CHR_EN_OFFSET CON0_OFFSET
+#define CHR_EN_MASK 0x0010
+#define CHR_EN_SHIFT 4
+
+#define CSDAC_EN_OFFSET CON0_OFFSET
+#define CSDAC_EN_MASK 0x0008
+#define CSDAC_EN_SHIFT 3
+
+#define PCHR_AUTOMODE_OFFSET CON0_OFFSET
+#define PCHR_AUTOMODE_MASK 0x0004
+#define PCHR_AUTOMODE_SHIFT 2
+
+#define CHR_LDO_DET_OFFSET CON0_OFFSET
+#define CHR_LDO_DET_MASK 0x0002
+#define CHR_LDO_DET_SHIFT 1
+
+#define VCDT_HV_EN_OFFSET CON0_OFFSET
+#define VCDT_HV_EN_MASK 0x0001
+#define VCDT_HV_EN_SHIFT 0
+
+#define VBAT_CV_VTH_OFFSET CON1_OFFSET
+#define VBAT_CV_VTH_MASK 0x1F00
+#define VBAT_CV_VTH_SHIFT 8
+
+#define VBAT_CC_VTH_OFFSET CON1_OFFSET
+#define VBAT_CC_VTH_MASK 0x0030
+#define VBAT_CC_VTH_SHIFT 4
+
+#define VBAT_CC_DET_OFFSET CON1_OFFSET
+#define VBAT_CC_DET_MASK 0x0008
+#define VBAT_CC_DET_SHIFT 3
+
+#define VBAT_CV_DET_OFFSET CON1_OFFSET
+#define VBAT_CV_DET_MASK 0x0004
+#define VBAT_CV_DET_SHIFT 2
+
+#define VBAT_CC_EN_OFFSET CON1_OFFSET
+#define VBAT_CC_EN_MASK 0x0002
+#define VBAT_CC_EN_SHIFT 1
+
+#define VBAT_CV_EN_OFFSET CON1_OFFSET
+#define VBAT_CV_EN_MASK 0x0001
+#define VBAT_CV_EN_SHIFT 0
+
+#define CS_DET_OFFSET CON2_OFFSET
+#define CS_DET_MASK 0x8000
+#define CS_DET_SHIFT 15
+
+#define CS_EN_OFFSET CON2_OFFSET
+#define CS_EN_MASK 0x0100
+#define CS_EN_SHIFT 8
+
+#define CS_VTH_OFFSET CON2_OFFSET
+#define CS_VTH_MASK 0x000F
+#define CS_VTH_SHIFT 0
+
+#define TOLTC_OFFSET CON3_OFFSET
+#define TOLTC_MASK 0x0700
+#define TOLTC_SHIFT 8
+
+#define TOHTC_OFFSET CON3_OFFSET
+#define TOHTC_MASK 0x0007
+#define TOHTC_SHIFT 0
+
+#define CSDAC_DLY_OFFSET CON4_OFFSET
+#define CSDAC_DLY_MASK 0x7000
+#define CSDAC_DLY_SHIFT 12
+
+#define CSDAC_STP_OFFSET CON4_OFFSET
+#define CSDAC_STP_MASK 0x0700
+#define CSDAC_STP_SHIFT 8
+
+#define CSDAC_STP_DEC_OFFSET CON4_OFFSET
+#define CSDAC_STP_DEC_MASK 0x0070
+#define CSDAC_STP_DEC_SHIFT 4
+
+#define CSDAC_STP_INC_OFFSET CON4_OFFSET
+#define CSDAC_STP_INC_MASK 0x0007
+#define CSDAC_STP_INC_SHIFT 0
+
+#define BATON_UNDET_OFFSET CON5_OFFSET
+#define BATON_UNDET_MASK 0x0400
+#define BATON_UNDET_SHIFT 10
+
+#define BATON_HT_EN_OFFSET CON5_OFFSET
+#define BATON_HT_EN_MASK 0x0200
+#define BATON_HT_EN_SHIFT 9
+
+#define BATON_EN_OFFSET CON5_OFFSET
+#define BATON_EN_MASK 0x0100
+#define BATON_EN_SHIFT 8
+
+#define VBAT_OV_VTH_OFFSET CON5_OFFSET
+#define VBAT_OV_VTH_MASK 0x0030
+#define VBAT_OV_VTH_SHIFT 4
+
+#define VBAT_OV_DET_OFFSET CON5_OFFSET
+#define VBAT_OV_DET_MASK 0x0008
+#define VBAT_OV_DET_SHIFT 3
+
+#define VBAT_OV_DEG_OFFSET CON5_OFFSET
+#define VBAT_OV_DEG_MASK 0x0002
+#define VBAT_OV_DEG_SHIFT 1
+
+#define VBAT_OV_EN_OFFSET CON5_OFFSET
+#define VBAT_OV_EN_MASK 0x0001
+#define VBAT_OV_EN_SHIFT 0
+
+#define CSDAC_DATA_OFFSET CON6_OFFSET
+#define CSDAC_DATA_MASK 0x03FF
+#define CSDAC_DATA_SHIFT 0
+
+#define PCHR_FT_CTRL_OFFSET CON7_OFFSET
+#define PCHR_FT_CTRL_MASK 0x0700
+#define PCHR_FT_CTRL_SHIFT 8
+
+#define PCHR_RST_OFFSET CON7_OFFSET
+#define PCHR_RST_MASK 0x0040
+#define PCHR_RST_SHIFT 6
+
+#define CSDAC_TESTMODE_OFFSET CON7_OFFSET
+#define CSDAC_TESTMODE_MASK 0x0020
+#define CSDAC_TESTMODE_SHIFT 5
+
+#define PCHR_TESTMODE_OFFSET CON7_OFFSET
+#define PCHR_TESTMODE_MASK 0x0010
+#define PCHR_TESTMODE_SHIFT 4
+
+#define OTG_BVALID_OFFSET CON7_OFFSET
+#define OTG_BVALID_MASK 0x0008
+#define OTG_BVALID_SHIFT 3
+
+#define OTG_BVALID_EN_OFFSET CON7_OFFSET
+#define OTG_BVALID_EN_MASK 0x0001
+#define OTG_BVALID_EN_SHIFT 0
+
+#define PCHR_FLAG_SEL_OFFSET CON8_OFFSET
+#define PCHR_FLAG_SEL_MASK 0x1F00
+#define PCHR_FLAG_SEL_SHIFT 8
+
+#define PCHR_FLAG_EN_OFFSET CON8_OFFSET
+#define PCHR_FLAG_EN_MASK 0x0080
+#define PCHR_FLAG_EN_SHIFT 7
+
+#define PCHR_FLAG_OUT_OFFSET CON8_OFFSET
+#define PCHR_FLAG_OUT_MASK 0x000F
+#define PCHR_FLAG_OUT_SHIFT 0
+
+#define CHRWDT_OUT_OFFSET CON9_OFFSET
+#define CHRWDT_OUT_MASK 0x8000
+#define CHRWDT_OUT_SHIFT 15
+
+#define CHRWDT_FLAG_OFFSET CON9_OFFSET
+#define CHRWDT_FLAG_MASK 0x0200
+#define CHRWDT_FLAG_SHIFT 9
+
+#define CHRWDT_INT_EN_OFFSET CON9_OFFSET
+#define CHRWDT_INT_EN_MASK 0x0100
+#define CHRWDT_INT_EN_SHIFT 8
+
+#define CHRWDT_EN_OFFSET CON9_OFFSET
+#define CHRWDT_EN_MASK 0x0010
+#define CHRWDT_EN_SHIFT 4
+
+#define CHRWDT_TD_OFFSET CON9_OFFSET
+#define CHRWDT_TD_MASK 0x000F
+#define CHRWDT_TD_SHIFT 0
+
+#define USBDL_SET_OFFSET CON10_OFFSET
+#define USBDL_SET_MASK 0x8000
+#define USBDL_SET_SHIFT 15
+
+#define USBDL_RST_OFFSET CON10_OFFSET
+#define USBDL_RST_MASK 0x4000
+#define USBDL_RST_SHIFT 14
+
+#define BGR_UNCHOP_OFFSET CON10_OFFSET
+#define BGR_UNCHOP_MASK 0x2000
+#define BGR_UNCHOP_SHIFT 13
+
+#define BGR_UNCHOP_PH_OFFSET CON10_OFFSET
+#define BGR_UNCHOP_PH_MASK 0x1000
+#define BGR_UNCHOP_PH_SHIFT 12
+
+#define BGR_RSEL_OFFSET CON10_OFFSET
+#define BGR_RSEL_MASK 0x0700
+#define BGR_RSEL_SHIFT 8
+
+#define ADCIN_CHR_EN_OFFSET CON10_OFFSET
+#define ADCIN_CHR_EN_MASK 0x0040
+#define ADCIN_CHR_EN_SHIFT 6
+
+#define ADCIN_VSEN_EN_OFFSET CON10_OFFSET
+#define ADCIN_VSEN_EN_MASK 0x0020
+#define ADCIN_VSEN_EN_SHIFT 5
+
+#define ADCIN_VBAT_EN_OFFSET CON10_OFFSET
+#define ADCIN_VBAT_EN_MASK 0x0010
+#define ADCIN_VBAT_EN_SHIFT 4
+
+#define UVLO_VTHL_OFFSET CON10_OFFSET
+#define UVLO_VTHL_MASK 0x0003
+#define UVLO_VTHL_SHIFT 0
+
+#define BC11_CMP_OUT_OFFSET CON11_OFFSET
+#define BC11_CMP_OUT_MASK 0x8000
+#define BC11_CMP_OUT_SHIFT 15
+
+#define BC11_RST_OFFSET CON11_OFFSET
+#define BC11_RST_MASK 0x0800
+#define BC11_RST_SHIFT 11
+
+#define BC11_BB_CTRL_OFFSET CON11_OFFSET
+#define BC11_BB_CTRL_MASK 0x0400
+#define BC11_BB_CTRL_SHIFT 10
+
+#define BC11_BIAS_EN_OFFSET CON11_OFFSET
+#define BC11_BIAS_EN_MASK 0x0200
+#define BC11_BIAS_EN_SHIFT 9
+
+#define BC11_VREF_VTH_OFFSET CON11_OFFSET
+#define BC11_VREF_VTH_MASK 0x0100
+#define BC11_VREF_VTH_SHIFT 8
+
+#define BC11_IPU_EN_OFFSET CON11_OFFSET
+#define BC11_IPU_EN_MASK 0x00C0
+#define BC11_IPU_EN_SHIFT 6
+
+#define BC11_IPD_EN_OFFSET CON11_OFFSET
+#define BC11_IPD_EN_MASK 0x0030
+#define BC11_IPD_EN_SHIFT 4
+
+#define BC11_VSRC_EN_OFFSET CON11_OFFSET
+#define BC11_VSRC_EN_MASK 0x000C
+#define BC11_VSRC_EN_SHIFT 2
+
+#define BC11_CMP_EN_OFFSET CON11_OFFSET
+#define BC11_CMP_EN_MASK 0x0003
+#define BC11_CMP_EN_SHIFT 0
+
+#define LOW_ICH_DB_OFFSET CON12_OFFSET
+#define LOW_ICH_DB_MASK 0x3F00
+#define LOW_ICH_DB_SHIFT 8
+
+#define ULC_DET_EN_OFFSET CON12_OFFSET
+#define ULC_DET_EN_MASK 0x0080
+#define ULC_DET_EN_SHIFT 7
+
+#define HWCV_EN_OFFSET CON12_OFFSET
+#define HWCV_EN_MASK 0x0040
+#define HWCV_EN_SHIFT 6
+
+#define TRACKING_EN_OFFSET CON12_OFFSET
+#define TRACKING_EN_MASK 0x0010
+#define TRACKING_EN_SHIFT 4
+
+#define CSDAC_MODE_OFFSET CON12_OFFSET
+#define CSDAC_MODE_MASK 0x0004
+#define CSDAC_MODE_SHIFT 2
+
+#define VCDT_MODE_OFFSET CON12_OFFSET
+#define VCDT_MODE_MASK 0x0002
+#define VCDT_MODE_SHIFT 1
+
+#define CV_MODE_OFFSET CON12_OFFSET
+#define CV_MODE_MASK 0x0001
+#define CV_MODE_SHIFT 0
+
+#define DRV_ITUNE_OFFSET CON13_OFFSET
+#define DRV_ITUNE_MASK 0x0300
+#define DRV_ITUNE_SHIFT 8
+
+#define OVP_TRIM_OFFSET CON13_OFFSET
+#define OVP_TRIM_MASK 0x000F
+#define OVP_TRIM_SHIFT 0
+
+#define PCHR_RV_OFFSET CON14_OFFSET
+#define PCHR_RV_MASK 0xFFFF
+#define PCHR_RV_SHIFT 0
+
+#define PWRKEY_DEB_OFFSET CON0_OFFSET
+#define PWRKEY_DEB_MASK 0x8000
+#define PWRKEY_DEB_SHIFT 15
+
+#define PWRKEY_VCORE_OFFSET CON0_OFFSET
+#define PWRKEY_VCORE_MASK 0x4000
+#define PWRKEY_VCORE_SHIFT 14
+
+#define TEST_MODE_POR_OFFSET CON0_OFFSET
+#define TEST_MODE_POR_MASK 0x2000
+#define TEST_MODE_POR_SHIFT 13
+
+#define USBDL_MDOE_OFFSET CON0_OFFSET
+#define USBDL_MDOE_MASK 0x1000
+#define USBDL_MDOE_SHIFT 12
+
+#define PMU_THR_PWROFF_OFFSET CON0_OFFSET
+#define PMU_THR_PWROFF_MASK 0x0800
+#define PMU_THR_PWROFF_SHIFT 11
+
+#define PMU_THR_STATUS_OFFSET CON0_OFFSET
+#define PMU_THR_STATUS_MASK 0x0700
+#define PMU_THR_STATUS_SHIFT 8
+
+#define USBDL_EN_OFFSET CON0_OFFSET
+#define USBDL_EN_MASK 0x0010
+#define USBDL_EN_SHIFT 4
+
+#define THR_HWPDN_EN_OFFSET CON0_OFFSET
+#define THR_HWPDN_EN_MASK 0x0008
+#define THR_HWPDN_EN_SHIFT 3
+
+#define THERMAL_DIS_OFFSET CON0_OFFSET
+#define THERMAL_DIS_MASK 0x0004
+#define THERMAL_DIS_SHIFT 2
+
+#define THR_SEL_OFFSET CON0_OFFSET
+#define THR_SEL_MASK 0x0003
+#define THR_SEL_SHIFT 0
+
+#define BIAS_GEN_FORCE_OFFSET CON1_OFFSET
+#define BIAS_GEN_FORCE_MASK 0x4000
+#define BIAS_GEN_FORCE_SHIFT 14
+
+#define PMU_LEV_UNGATE_OFFSET CON1_OFFSET
+#define PMU_LEV_UNGATE_MASK 0x0100
+#define PMU_LEV_UNGATE_SHIFT 8
+
+#define RST_DRVSEL_OFFSET CON1_OFFSET
+#define RST_DRVSEL_MASK 0x0020
+#define RST_DRVSEL_SHIFT 5
+
+#define STRUP_TEST_OFFSET CON1_OFFSET
+#define STRUP_TEST_MASK 0x0010
+#define STRUP_TEST_SHIFT 4
+
+#define PMU_PGDET_DIS_OFFSET CON1_OFFSET
+#define PMU_PGDET_DIS_MASK 0x0008
+#define PMU_PGDET_DIS_SHIFT 3
+
+#define VREF_BG_OFFSET CON1_OFFSET
+#define VREF_BG_MASK 0x0007
+#define VREF_BG_SHIFT 0
+
+#define STRUP_FLAG_OUT_OFFSET CON2_OFFSET
+#define STRUP_FLAG_OUT_MASK 0x0F00
+#define STRUP_FLAG_OUT_SHIFT 8
+
+#define STRUP_FLAG_EN_OFFSET CON2_OFFSET
+#define STRUP_FLAG_EN_MASK 0x0080
+#define STRUP_FLAG_EN_SHIFT 7
+
+#define STRUP_FLAG_SEL_OFFSET CON2_OFFSET
+#define STRUP_FLAG_SEL_MASK 0x000F
+#define STRUP_FLAG_SEL_SHIFT 0
+
+#define ESDDEG_DLYSEL_OFFSET CON3_OFFSET
+#define ESDDEG_DLYSEL_MASK 0x000E
+#define ESDDEG_DLYSEL_SHIFT 1
+
+#define ESDDEG_EN_OFFSET CON3_OFFSET
+#define ESDDEG_EN_MASK 0x0001
+#define ESDDEG_EN_SHIFT 0
+
+#define BOOST_CKS_CHG_OFFSET CON3_OFFSET
+#define BOOST_CKS_CHG_MASK 0x8000
+#define BOOST_CKS_CHG_SHIFT 15
+
+#define BOOST_CKS_PRG_OFFSET CON3_OFFSET
+#define BOOST_CKS_PRG_MASK 0x003F
+#define BOOST_CKS_PRG_SHIFT 0
+
+#define ISINK0_STATUS_OFFSET CON0_OFFSET
+#define ISINK0_STATUS_MASK 0x8000
+#define ISINK0_STATUS_SHIFT 15
+
+#define ISINK0_STEP_OFFSET CON0_OFFSET
+#define ISINK0_STEP_MASK 0x0070
+#define ISINK0_STEP_SHIFT 4
+
+#define ISINK0_MODE_OFFSET CON0_OFFSET
+#define ISINK0_MODE_MASK 0x0002
+#define ISINK0_MODE_SHIFT 1
+
+#define ISINK0_EN_OFFSET CON0_OFFSET
+#define ISINK0_EN_MASK 0x0001
+#define ISINK0_EN_SHIFT 0
+
+#define ISINKS_VREF_CAL_OFFSET CON1_OFFSET
+#define ISINKS_VREF_CAL_MASK 0x1F00
+#define ISINKS_VREF_CAL_SHIFT 8
+
+#define ISINKS_FORCE_OFF_OFFSET CON1_OFFSET
+#define ISINKS_FORCE_OFF_MASK 0x0001
+#define ISINKS_FORCE_OFF_SHIFT 0
+
+#define ISINKS_TEST_SEL_OFFSET CON2_OFFSET
+#define ISINKS_TEST_SEL_MASK 0x0700
+#define ISINKS_TEST_SEL_SHIFT 8
+
+#define ISINKS_RSV_OFFSET CON2_OFFSET
+#define ISINKS_RSV_MASK 0x00FF
+#define ISINKS_RSV_SHIFT 0
+
+#define ISINK1_STATUS_OFFSET CON0_OFFSET
+#define ISINK1_STATUS_MASK 0x8000
+#define ISINK1_STATUS_SHIFT 15
+
+#define ISINK1_STEP_OFFSET CON0_OFFSET
+#define ISINK1_STEP_MASK 0x0070
+#define ISINK1_STEP_SHIFT 4
+
+#define ISINK1_MODE_OFFSET CON0_OFFSET
+#define ISINK1_MODE_MASK 0x0002
+#define ISINK1_MODE_SHIFT 1
+
+#define ISINK1_EN_OFFSET CON0_OFFSET
+#define ISINK1_EN_MASK 0x0001
+#define ISINK1_EN_SHIFT 0
+
+#define ISINK2_STATUS_OFFSET CON0_OFFSET
+#define ISINK2_STATUS_MASK 0x8000
+#define ISINK2_STATUS_SHIFT 15
+
+#define ISINK2_STEP_OFFSET CON0_OFFSET
+#define ISINK2_STEP_MASK 0x0070
+#define ISINK2_STEP_SHIFT 4
+
+#define ISINK2_MODE_OFFSET CON0_OFFSET
+#define ISINK2_MODE_MASK 0x0002
+#define ISINK2_MODE_SHIFT 1
+
+#define ISINK2_EN_OFFSET CON0_OFFSET
+#define ISINK2_EN_MASK 0x0001
+#define ISINK2_EN_SHIFT 0
+
+#define ISINK3_STATUS_OFFSET CON0_OFFSET
+#define ISINK3_STATUS_MASK 0x8000
+#define ISINK3_STATUS_SHIFT 15
+
+#define ISINK3_STEP_OFFSET CON0_OFFSET
+#define ISINK3_STEP_MASK 0x0070
+#define ISINK3_STEP_SHIFT 4
+
+#define ISINK3_MODE_OFFSET CON0_OFFSET
+#define ISINK3_MODE_MASK 0x0002
+#define ISINK3_MODE_SHIFT 1
+
+#define ISINK3_EN_OFFSET CON0_OFFSET
+#define ISINK3_EN_MASK 0x0001
+#define ISINK3_EN_SHIFT 0
+
+#define ISINK4_STATUS_OFFSET CON0_OFFSET
+#define ISINK4_STATUS_MASK 0x8000
+#define ISINK4_STATUS_SHIFT 15
+
+#define ISINK4_STEP_OFFSET CON0_OFFSET
+#define ISINK4_STEP_MASK 0x0070
+#define ISINK4_STEP_SHIFT 4
+
+#define ISINK4_MODE_OFFSET CON0_OFFSET
+#define ISINK4_MODE_MASK 0x0002
+#define ISINK4_MODE_SHIFT 1
+
+#define ISINK4_EN_OFFSET CON0_OFFSET
+#define ISINK4_EN_MASK 0x0001
+#define ISINK4_EN_SHIFT 0
+
+#define ISINK5_STATUS_OFFSET CON0_OFFSET
+#define ISINK5_STATUS_MASK 0x8000
+#define ISINK5_STATUS_SHIFT 15
+
+#define ISINK5_STEP_OFFSET CON0_OFFSET
+#define ISINK5_STEP_MASK 0x0070
+#define ISINK5_STEP_SHIFT 4
+
+#define ISINK5_MODE_OFFSET CON0_OFFSET
+#define ISINK5_MODE_MASK 0x0002
+#define ISINK5_MODE_SHIFT 1
+
+#define ISINK5_EN_OFFSET CON0_OFFSET
+#define ISINK5_EN_MASK 0x0001
+#define ISINK5_EN_SHIFT 0
+
+#define KPLED_STATUS_OFFSET CON0_OFFSET
+#define KPLED_STATUS_MASK 0x8000
+#define KPLED_STATUS_SHIFT 15
+
+#define KPLED_SFSTREN_OFFSET CON0_OFFSET
+#define KPLED_SFSTREN_MASK 0x0400
+#define KPLED_SFSTREN_SHIFT 10
+
+#define KPLED_SFSTRTC_OFFSET CON0_OFFSET
+#define KPLED_SFSTRTC_MASK 0x0300
+#define KPLED_SFSTRTC_SHIFT 8
+
+#define KPLED_SEL_OFFSET CON0_OFFSET
+#define KPLED_SEL_MASK 0x0070
+#define KPLED_SEL_SHIFT 4
+
+#define KPLED_MODE_OFFSET CON0_OFFSET
+#define KPLED_MODE_MASK 0x0002
+#define KPLED_MODE_SHIFT 1
+
+#define KPLED_EN_OFFSET CON0_OFFSET
+#define KPLED_EN_MASK 0x0001
+#define KPLED_EN_SHIFT 0
+
+#define KPLED_FORCE_OFF_OFFSET CON1_OFFSET
+#define KPLED_FORCE_OFF_MASK 0x0001
+#define KPLED_FORCE_OFF_SHIFT 0
+
+#define SPK_OC_FLAG_OFFSET CON0_OFFSET
+#define SPK_OC_FLAG_MASK 0x4000
+#define SPK_OC_FLAG_SHIFT 14
+
+#define SPK_OC_AUTOFF_OFFSET CON0_OFFSET
+#define SPK_OC_AUTOFF_MASK 0x1000
+#define SPK_OC_AUTOFF_SHIFT 12
+
+#define SPK_VOL_OFFSET CON0_OFFSET
+#define SPK_VOL_MASK 0x0030
+#define SPK_VOL_SHIFT 4
+
+#define SPK_EN_OFFSET CON0_OFFSET
+#define SPK_EN_MASK 0x0001
+#define SPK_EN_SHIFT 0
+
+#define SPK_EN_VIEW_CLK_OFFSET CON3_OFFSET
+#define SPK_EN_VIEW_CLK_MASK 0x4000
+#define SPK_EN_VIEW_CLK_SHIFT 14
+
+#define SPK_OC_CTRL_OFFSET CON3_OFFSET
+#define SPK_OC_CTRL_MASK 0x000C
+#define SPK_OC_CTRL_SHIFT 2
+
+#define SPK_BIAS_OFFSET CON7_OFFSET
+#define SPK_BIAS_MASK 0x6000
+#define SPK_BIAS_SHIFT 13
+
+#define SPK_2IN1_OFFSET CON7_OFFSET
+#define SPK_2IN1_MASK 0x1000
+#define SPK_2IN1_SHIFT 12
+
+#define SPK_PBIAS_OFFSET CON7_OFFSET
+#define SPK_PBIAS_MASK 0x0400
+#define SPK_PBIAS_SHIFT 10
+
+#define SPKAB_OC_EN_OFFSET CON7_OFFSET
+#define SPKAB_OC_EN_MASK 0x0100
+#define SPKAB_OC_EN_SHIFT 8
+
+#define SPKAB_VCM_SEL_OFFSET CON7_OFFSET
+#define SPKAB_VCM_SEL_MASK 0x0080
+#define SPKAB_VCM_SEL_SHIFT 7
+
+#define VCM_IBSEL_OFFSET CON7_OFFSET
+#define VCM_IBSEL_MASK 0x0040
+#define VCM_IBSEL_SHIFT 6
+
+#define SPKAB_OBIAS_OFFSET CON7_OFFSET
+#define SPKAB_OBIAS_MASK 0x0030
+#define SPKAB_OBIAS_SHIFT 4
+
+#define SPK_RSV_OFFSET CON8_OFFSET
+#define SPK_RSV_MASK 0xF000
+#define SPK_RSV_SHIFT 12
+
+#define SPK_CALIBR_SEL_OFFSET CON8_OFFSET
+#define SPK_CALIBR_SEL_MASK 0x0200
+#define SPK_CALIBR_SEL_SHIFT 9
+
+#define SPK_CALIBR_EN_OFFSET CON8_OFFSET
+#define SPK_CALIBR_EN_MASK 0x0040
+#define SPK_CALIBR_EN_SHIFT 6
+
+#define VSF_OC_INT_EN_OFFSET CON0_OFFSET
+#define VSF_OC_INT_EN_MASK 0x2000
+#define VSF_OC_INT_EN_SHIFT 13
+
+#define VMC_OC_INT_EN_OFFSET CON0_OFFSET
+#define VMC_OC_INT_EN_MASK 0x1000
+#define VMC_OC_INT_EN_SHIFT 12
+
+#define VIBR_OC_INT_EN_OFFSET CON0_OFFSET
+#define VIBR_OC_INT_EN_MASK 0x0800
+#define VIBR_OC_INT_EN_SHIFT 11
+
+#define VRTC_OC_INT_EN_OFFSET CON0_OFFSET
+#define VRTC_OC_INT_EN_MASK 0x0400
+#define VRTC_OC_INT_EN_SHIFT 10
+
+#define VSIM2_OC_INT_EN_OFFSET CON0_OFFSET
+#define VSIM2_OC_INT_EN_MASK 0x0200
+#define VSIM2_OC_INT_EN_SHIFT 9
+
+#define VSIM_OC_INT_EN_OFFSET CON0_OFFSET
+#define VSIM_OC_INT_EN_MASK 0x0100
+#define VSIM_OC_INT_EN_SHIFT 8
+
+#define VBT_OC_INT_EN_OFFSET CON0_OFFSET
+#define VBT_OC_INT_EN_MASK 0x0080
+#define VBT_OC_INT_EN_SHIFT 7
+
+#define VUSB_OC_INT_EN_OFFSET CON0_OFFSET
+#define VUSB_OC_INT_EN_MASK 0x0040
+#define VUSB_OC_INT_EN_SHIFT 6
+
+#define VIO28_OC_INT_EN_OFFSET CON0_OFFSET
+#define VIO28_OC_INT_EN_MASK 0x0020
+#define VIO28_OC_INT_EN_SHIFT 5
+
+#define VCAMD_OC_INT_EN_OFFSET CON0_OFFSET
+#define VCAMD_OC_INT_EN_MASK 0x0010
+#define VCAMD_OC_INT_EN_SHIFT 4
+
+#define VCAMA_OC_INT_EN_OFFSET CON0_OFFSET
+#define VCAMA_OC_INT_EN_MASK 0x0008
+#define VCAMA_OC_INT_EN_SHIFT 3
+
+#define VA_OC_INT_EN_OFFSET CON0_OFFSET
+#define VA_OC_INT_EN_MASK 0x0004
+#define VA_OC_INT_EN_SHIFT 2
+
+#define VTCXO_OC_INT_EN_OFFSET CON0_OFFSET
+#define VTCXO_OC_INT_EN_MASK 0x0002
+#define VTCXO_OC_INT_EN_SHIFT 1
+
+#define VRF_OC_INT_EN_OFFSET CON0_OFFSET
+#define VRF_OC_INT_EN_MASK 0x0001
+#define VRF_OC_INT_EN_SHIFT 0
+
+#define VIO18_OC_INT_EN_OFFSET CON1_OFFSET
+#define VIO18_OC_INT_EN_MASK 0x0002
+#define VIO18_OC_INT_EN_SHIFT 1
+
+#define VCORE_OC_INT_EN_OFFSET CON1_OFFSET
+#define VCORE_OC_INT_EN_MASK 0x0001
+#define VCORE_OC_INT_EN_SHIFT 0
+
+#define SPK_OC_INT_EN_OFFSET CON3_OFFSET
+#define SPK_OC_INT_EN_MASK 0x0001
+#define SPK_OC_INT_EN_SHIFT 0
+/*
+#define VSF_OC_FLAG_OFFSET CON4_OFFSET
+#define VSF_OC_FLAG_MASK 0x2000
+#define VSF_OC_FLAG_SHIFT 13
+
+#define VMC_OC_FLAG_OFFSET CON4_OFFSET
+#define VMC_OC_FLAG_MASK 0x1000
+#define VMC_OC_FLAG_SHIFT 12
+
+#define VIBR_OC_FLAG_OFFSET CON4_OFFSET
+#define VIBR_OC_FLAG_MASK 0x0800
+#define VIBR_OC_FLAG_SHIFT 11
+
+#define VRTC_OC_FLAG_OFFSET CON4_OFFSET
+#define VRTC_OC_FLAG_MASK 0x0400
+#define VRTC_OC_FLAG_SHIFT 10
+
+#define VSIM2_OC_FLAG_OFFSET CON4_OFFSET
+#define VSIM2_OC_FLAG_MASK 0x0200
+#define VSIM2_OC_FLAG_SHIFT 9
+
+#define VSIM_OC_FLAG_OFFSET CON4_OFFSET
+#define VSIM_OC_FLAG_MASK 0x0100
+#define VSIM_OC_FLAG_SHIFT 8
+
+#define VBT_OC_FLAG_OFFSET CON4_OFFSET
+#define VBT_OC_FLAG_MASK 0x0080
+#define VBT_OC_FLAG_SHIFT 7
+
+#define VUSB_OC_FLAG_OFFSET CON4_OFFSET
+#define VUSB_OC_FLAG_MASK 0x0040
+#define VUSB_OC_FLAG_SHIFT 6
+
+#define VIO28_OC_FLAG_OFFSET CON4_OFFSET
+#define VIO28_OC_FLAG_MASK 0x0020
+#define VIO28_OC_FLAG_SHIFT 5
+
+#define VCAMD_OC_FLAG_OFFSET CON4_OFFSET
+#define VCAMD_OC_FLAG_MASK 0x0010
+#define VCAMD_OC_FLAG_SHIFT 4
+
+#define VCAMA_OC_FLAG_OFFSET CON4_OFFSET
+#define VCAMA_OC_FLAG_MASK 0x0008
+#define VCAMA_OC_FLAG_SHIFT 3
+
+#define VA_OC_FLAG_OFFSET CON4_OFFSET
+#define VA_OC_FLAG_MASK 0x0004
+#define VA_OC_FLAG_SHIFT 2
+
+#define VTCXO_OC_FLAG_OFFSET CON4_OFFSET
+#define VTCXO_OC_FLAG_MASK 0x0002
+#define VTCXO_OC_FLAG_SHIFT 1
+
+#define VRF_OC_FLAG_OFFSET CON4_OFFSET
+#define VRF_OC_FLAG_MASK 0x0001
+#define VRF_OC_FLAG_SHIFT 0
+
+#define VIO18_OC_FLAG_OFFSET CON5_OFFSET
+#define VIO18_OC_FLAG_MASK 0x0002
+#define VIO18_OC_FLAG_SHIFT 1
+
+#define VCORE_OC_FLAG_OFFSET CON5_OFFSET
+#define VCORE_OC_FLAG_MASK 0x0001
+#define VCORE_OC_FLAG_SHIFT 0
+
+#define SPK_OC_FLAG_OFFSET CON7_OFFSET
+#define SPK_OC_FLAG_MASK 0x0001
+#define SPK_OC_FLAG_SHIFT 0
+*/
+#define VSF_OC_STATUS_OFFSET CON8_OFFSET
+#define VSF_OC_STATUS_MASK 0x2000
+#define VSF_OC_STATUS_SHIFT 13
+
+#define VMC_OC_STATUS_OFFSET CON8_OFFSET
+#define VMC_OC_STATUS_MASK 0x1000
+#define VMC_OC_STATUS_SHIFT 12
+
+#define VIBR_OC_STATUS_OFFSET CON8_OFFSET
+#define VIBR_OC_STATUS_MASK 0x0800
+#define VIBR_OC_STATUS_SHIFT 11
+
+#define VRTC_OC_STATUS_OFFSET CON8_OFFSET
+#define VRTC_OC_STATUS_MASK 0x0400
+#define VRTC_OC_STATUS_SHIFT 10
+
+#define VSIM2_OC_STATUS_OFFSET CON8_OFFSET
+#define VSIM2_OC_STATUS_MASK 0x0200
+#define VSIM2_OC_STATUS_SHIFT 9
+
+#define VSIM_OC_STATUS_OFFSET CON8_OFFSET
+#define VSIM_OC_STATUS_MASK 0x0100
+#define VSIM_OC_STATUS_SHIFT 8
+
+#define VBT_OC_STATUS_OFFSET CON8_OFFSET
+#define VBT_OC_STATUS_MASK 0x0080
+#define VBT_OC_STATUS_SHIFT 7
+
+#define VUSB_OC_STATUS_OFFSET CON8_OFFSET
+#define VUSB_OC_STATUS_MASK 0x0040
+#define VUSB_OC_STATUS_SHIFT 6
+
+#define VIO28_OC_STATUS_OFFSET CON8_OFFSET
+#define VIO28_OC_STATUS_MASK 0x0020
+#define VIO28_OC_STATUS_SHIFT 5
+
+#define VCAMD_OC_STATUS_OFFSET CON8_OFFSET
+#define VCAMD_OC_STATUS_MASK 0x0010
+#define VCAMD_OC_STATUS_SHIFT 4
+
+#define VCAMA_OC_STATUS_OFFSET CON8_OFFSET
+#define VCAMA_OC_STATUS_MASK 0x0008
+#define VCAMA_OC_STATUS_SHIFT 3
+
+#define VA_OC_STATUS_OFFSET CON8_OFFSET
+#define VA_OC_STATUS_MASK 0x0004
+#define VA_OC_STATUS_SHIFT 2
+
+#define VTCXO_OC_STATUS_OFFSET CON8_OFFSET
+#define VTCXO_OC_STATUS_MASK 0x0002
+#define VTCXO_OC_STATUS_SHIFT 1
+
+#define VRF_OC_STATUS_OFFSET CON8_OFFSET
+#define VRF_OC_STATUS_MASK 0x0001
+#define VRF_OC_STATUS_SHIFT 0
+
+#define VIO18_OC_STATUS_OFFSET CON9_OFFSET
+#define VIO18_OC_STATUS_MASK 0x0002
+#define VIO18_OC_STATUS_SHIFT 1
+
+#define VCORE_OC_STATUS_OFFSET CON9_OFFSET
+#define VCORE_OC_STATUS_MASK 0x0001
+#define VCORE_OC_STATUS_SHIFT 0
+
+#define SPK_OC_STATUS_OFFSET CONB_OFFSET
+#define SPK_OC_STATUS_MASK 0x0001
+#define SPK_OC_STATUS_SHIFT 0
+
+#define INT_NODE_MUX_OFFSET CON0_OFFSET
+#define INT_NODE_MUX_MASK 0x0007
+#define INT_NODE_MUX_SHIFT 0
+
+#define IBIAS_TRIM_OFFSET CON1_OFFSET
+#define IBIAS_TRIM_MASK 0xF000
+#define IBIAS_TRIM_SHIFT 12
+
+#define TPSEL_OFFSET CON1_OFFSET
+#define TPSEL_MASK 0x0F00
+#define TPSEL_SHIFT 8
+
+#define TP_BUCK_OFFSET CON1_OFFSET
+#define TP_BUCK_MASK 0x0030
+#define TP_BUCK_SHIFT 4
+
+#define TP_LED_OFFSET CON1_OFFSET
+#define TP_LED_MASK 0x000F
+#define TP_LED_SHIFT 0
+
+#define TESTMODE_RSV_OFFSET CON2_OFFSET
+#define TESTMODE_RSV_MASK 0xFC00
+#define TESTMODE_RSV_SHIFT 10
+
+#define PMU_SV12_TMODE_OFFSET CON2_OFFSET
+#define PMU_SV12_TMODE_MASK 0x0200
+#define PMU_SV12_TMODE_SHIFT 9
+
+#define PMU_THR_TMODE_OFFSET CON2_OFFSET
+#define PMU_THR_TMODE_MASK 0x0100
+#define PMU_THR_TMODE_SHIFT 8
+
+#define IBIAS_TRIM_EN_OFFSET CON2_OFFSET
+#define IBIAS_TRIM_EN_MASK 0x0020
+#define IBIAS_TRIM_EN_SHIFT 5
+
+#define PMU_TMSEL_OFFSET CON2_OFFSET
+#define PMU_TMSEL_MASK 0x001F
+#define PMU_TMSEL_SHIFT 0
+
+#define PMIC_RSV0_OFFSET CON0_OFFSET
+#define PMIC_RSV0_MASK 0x00FF
+#define PMIC_RSV0_SHIFT 0
+
+#define PMIC_RSV1_OFFSET CON1_OFFSET
+#define PMIC_RSV1_MASK 0x00FF
+#define PMIC_RSV1_SHIFT 0
+
+#define PMIC_RSV2_OFFSET CON2_OFFSET
+#define PMIC_RSV2_MASK 0x00FF
+#define PMIC_RSV2_SHIFT 0
+
+#define PMIC_RSV3_OFFSET CON3_OFFSET
+#define PMIC_RSV3_MASK 0x00FF
+#define PMIC_RSV3_SHIFT 0
+
+
+///////////////////////////////////////////////////////////
+/* Special Command */
+
+// LDO cmds
+// LDO_CON0
+#define LDO_BUCK_EN_OFFSET CON0_OFFSET
+#define LDO_BUCK_EN_MASK 0x0001
+#define LDO_BUCK_EN_SHIFT 0
+
+#define LDO_BUCK_ON_SEL_OFFSET CON0_OFFSET
+#define LDO_BUCK_ON_SEL_MASK 0x0002
+#define LDO_BUCK_ON_SEL_SHIFT 1
+
+#define LDO_BUCK_RS_OFFSET CON0_OFFSET
+#define LDO_BUCK_RS_MASK 0x0004
+#define LDO_BUCK_RS_SHIFT 2
+
+#define LDO_BUCK_VOL_SEL_OFFSET CON0_OFFSET // For VCAMA, VCAMD, VBT, VSIM, VSIM2, VIBR, VMC, VCORE
+#define LDO_BUCK_VOL_SEL_MASK 0x01F0
+#define LDO_BUCK_VOL_SEL_SHIFT 4
+
+#define LDO_BUCK_NDIS_EN_OFFSET CON0_OFFSET // BUCK: ANTIUNSH_DN
+#define LDO_BUCK_NDIS_EN_MASK 0x0400
+#define LDO_BUCK_NDIS_EN_SHIFT 10
+
+#define LDO_BUCK_STB_EN_OFFSET CON0_OFFSET
+#define LDO_BUCK_STB_EN_MASK 0x0800
+#define LDO_BUCK_STB_EN_SHIFT 11
+
+#define LDO_BUCK_OC_AUTO_OFF_OFFSET CON0_OFFSET
+#define LDO_BUCK_OC_AUTO_OFF_MASK 0x1000
+#define LDO_BUCK_OC_AUTO_OFF_SHIFT 12
+
+#define LDO_BUCK_OCFB_EN_OFFSET CON0_OFFSET
+#define LDO_BUCK_OCFB_EN_MASK 0x2000
+#define LDO_BUCK_OCFB_EN_SHIFT 13
+
+#define LDO_BUCK_OC_FLAG_OFFSET CON0_OFFSET
+#define LDO_BUCK_OC_FLAG_MASK 0x4000
+#define LDO_BUCK_OC_FLAG_SHIFT 14
+
+#define LDO_BUCK_STATUS_OFFSET CON0_OFFSET
+#define LDO_BUCK_STATUS_MASK 0x8000
+#define LDO_BUCK_STATUS_SHIFT 15
+
+// LDO_CON1
+#define LDO_CAL_OFFSET CON1_OFFSET
+#define LDO_CAL_MASK 0x01F0
+#define LDO_CAL_SHIFT 4
+
+#define LDO_STB_SEL_OFFSET CON1_OFFSET // For VIBR & VMC
+#define LDO_STB_SEL_MASK 0x1000
+#define LDO_STB_SEL_SHIFT 12
+
+// LDO_CON2
+#define LDO_EN_FORCE_OFFSET CON2_OFFSET
+#define LDO_EN_FORCE_MASK 0x0001
+#define LDO_EN_FORCE_SHIFT 0
+
+#define LDO_OC_TD_OFFSET CON2_OFFSET
+#define LDO_OC_TD_MASK 0x0030
+#define LDO_OC_TD_SHIFT 4
+
+#define LDO_STB_TD_OFFSET CON2_OFFSET
+#define LDO_STB_TD_MASK 0x00C0
+#define LDO_STB_TD_SHIFT 6
+
+// BUCK cmds
+#define BUCK_VFBADJ_SLEEP_OFFSET CON1_OFFSET
+#define BUCK_VFBADJ_SLEEP_MASK 0x01F0
+#define BUCK_VFBADJ_SLEEP_SHIFT 4
+
+#define BUCK_EN_FORCE_OFFSET CON3_OFFSET
+#define BUCK_EN_FORCE_MASK 0x0001
+#define BUCK_EN_FORCE_SHIFT 0
+
+#define BUCK_OC_TD_OFFSET CON3_OFFSET
+#define BUCK_OC_TD_MASK 0x0030
+#define BUCK_OC_TD_SHIFT 4
+
+#define BUCK_STB_TD_OFFSET CON3_OFFSET
+#define BUCK_STB_TD_MASK 0x00C0
+#define BUCK_STB_TD_SHIFT 6
+
+#define BUCK_OC_THD_OFFSET CON3_OFFSET
+#define BUCK_OC_THD_MASK 0x0300
+#define BUCK_OC_THD_SHIFT 8
+
+#define BUCK_OC_WND_OFFSET CON3_OFFSET
+#define BUCK_OC_WND_MASK 0x0C00
+#define BUCK_OC_WND_SHIFT 10
+
+#define BUCK_ICAL_EN_OFFSET CON3_OFFSET
+#define BUCK_ICAL_EN_MASK 0x3000
+#define BUCK_ICAL_EN_SHIFT 12
+
+#define BUCK_CSL_OFFSET CON5_OFFSET
+#define BUCK_CSL_MASK 0x0700
+#define BUCK_CSL_SHIFT 8
+
+#define BUCK_BURST_OFFSET CON5_OFFSET
+#define BUCK_BURST_MASK 0x3000
+#define BUCK_BURST_SHIFT 12
+
+// CHR CMDS
+#define ADC_EN_OFFSET CON10_OFFSET
+#define ADC_EN_MASK 0x0070 // All ADC channels are enabled at same time
+#define ADC_EN_SHIFT 4
+
+// ISINK cmds
+// ISINK_CON0
+#define ISINK_EN_OFFSET CON0_OFFSET
+#define ISINK_EN_MASK 0x0001
+#define ISINK_EN_SHIFT 0
+
+#define ISINK_MODE_OFFSET CON0_OFFSET
+#define ISINK_MODE_MASK 0x0002
+#define ISINK_MODE_SHIFT 1
+
+#define ISINK_STEP_OFFSET CON0_OFFSET
+#define ISINK_STEP_MASK 0x0070
+#define ISINK_STEP_SHIFT 4
+
+#define ISINK_STATUS_OFFSET CON0_OFFSET
+#define ISINK_STATUS_MASK 0x8000
+#define ISINK_STATUS_SHIFT 15
+
+// ISINK_CON1
+#define ISINK_FORCE_OFF_OFFSET CON1_OFFSET
+#define ISINK_FORCE_OFF_MASK 0x0001
+#define ISINK_FORCE_OFF_SHIFT 0
+
+#define ISINK_VREF_CAL_OFFSET CON1_OFFSET
+#define ISINK_VREF_CAL_MASK 0x1F00
+#define ISINK_VREF_CAL_SHIFT 8
+
+#endif // #if defined(PMIC_6255_REG_API)
+
+#endif // #ifndef __PMU6255_HW_H__
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6255_sw.h b/mcu/driver/peripheral/inc/dcl_pmu6255_sw.h
new file mode 100644
index 0000000..c911dab
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6255_sw.h
@@ -0,0 +1,249 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2011
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6255_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMU6255 s/w setting.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef __DCL_PMU6255_SW_H_STRUCT__
+#define __DCL_PMU6255_SW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6255_REG_API)
+
+/* Charger external interrupt is fixed. */
+#define PMU_CHR_EINT_PIN 15
+#define PMU_OC_EINT_PIN 16
+#define PMU_CHR_OVP_EINT_PIN 17
+#define PMU_CHR_LDO_EINT_PIN 19
+
+/* adc number for measuring VBAT/VISENSE/VCHARGER is fixed internally. */
+#define PMU_ADC_VBAT_CH_NUM 0
+#define PMU_ADC_VISENSE_CH_NUM 1
+#define PMU_ADC_VCHARGER_CH_NUM 2
+#define PMU_ADC_VBATTEMP_CH_NUM 3
+
+/* adc factor for VBAT/VISENSE/VCHARGER */
+#define PMU_ADC_FACTOR_VBAT 100
+#define PMU_ADC_FACTOR_VISENSE 100
+
+#define PMU_ADC_FACTOR_VCHARGER 473 // (369/39 * 50)
+
+#define PMU_ADC_FACTOR_VBATTEMP 100
+
+typedef enum
+{
+ LDO_BUCK_EN,
+ LDO_BUCK_ON_SEL,
+ LDO_BUCK_RS,
+ LDO_BUCK_VOL_SEL,
+ LDO_BUCK_NDIS_EN,
+ LDO_BUCK_STB_EN,
+ LDO_BUCK_OC_AUTO_OFF,
+ LDO_BUCK_OCFB_EN,
+ LDO_BUCK_OC_FLAG,
+ LDO_BUCK_STATUS,
+ LDO_CAL,
+ LDO_STB_SEL,
+ LDO_EN_FORCE,
+ LDO_OC_TD,
+ LDO_STB_TD,
+ CCI_SRCLKEN,
+ VA_LP_EN,
+ VSIM_GPLDO_EN,
+ VSIM2_GPLDO_EN,
+ SIM2_GPIO_EN,
+ BUCK_VFBADJ_SLEEP,
+ BUCK_EN_FORCE,
+ BUCK_STB_TD,
+ BUCK_OC_THD,
+ BUCK_OC_WND,
+ BUCK_ICAL_EN,
+ BUCK_CSL,
+ BUCK_BURST,
+ VCDT_HV_EN,
+// CHR_LDO_DET,
+ CSDAC_EN,
+ CHR_EN,
+ CHRDET,
+ VCDT_HV_VTH,
+ VBAT_CV_EN,
+ VBAT_CV_DET,
+ VBAT_CV_VTH,
+ CS_VTH,
+ CSDAC_STP_INC,
+ CSDAC_STP_DEC,
+ CSDAC_STP,
+ CSDAC_DLY,
+ VBAT_OV_VTH,
+ BATON_EN,
+ BATON_HT_EN,
+ BATON_UNDET,
+ OTG_BVALID_EN,
+ OTG_BVALID,
+ CHRWDT_TD,
+ CHRWDT_EN,
+ CHRWDT_INT_EN,
+ CHRWDT_FLAG,
+ ADC_EN,
+ USBDL_RST,
+ USBDL_SET,
+ BC11_CMP_EN,
+ BC11_VSRC_EN,
+ BC11_IPD_EN,
+ BC11_IPU_EN,
+ BC11_VREF_VTH,
+ BC11_BIAS_EN,
+ BC11_BB_CTRL,
+ BC11_RST,
+ BC11_CMP_OUT,
+ CV_MODE,
+ VCDT_MODE,
+ CSDAC_MODE,
+ TRACKING_EN,
+ HWCV_EN,
+ ULC_DET_EN,
+ LOW_ICH_DB,
+ USBDL_EN,
+ VBAT_CC_DET,
+ ISINK_EN,
+ ISINK_MODE,
+ ISINK_STEP,
+ KPLED_EN,
+ KPLED_MODE,
+ KPLED_SEL,
+ SPK_EN,
+ SPK_VOL,
+ SPKAB_OC_EN,
+ SPKAB_OBIAS,
+ SPK_CALIBR_EN,
+ SPK_CALIBR_SEL,
+ ABIST_LMON_SEL,
+ ABIST_HMON_SEL,
+ ABIST_LMON_DATA,
+ ABIST_HMON_DATA,
+ VRF_OC_INT_EN,
+ VTCXO_OC_INT_EN,
+ VA_OC_INT_EN,
+ VCAMA_OC_INT_EN,
+ VCAMD_OC_INT_EN,
+ VIO28_OC_INT_EN,
+ VUSB_OC_INT_EN,
+ VBT_OC_INT_EN,
+ VSIM_OC_INT_EN,
+ VSIM2_OC_INT_EN,
+ VRTC_OC_INT_EN,
+ VIBR_OC_INT_EN,
+ VMC_OC_INT_EN,
+ VCORE_OC_INT_EN,
+ VIO18_OC_INT_EN,
+ SPK_OC_INT_EN,
+ VRF_OC_FLAG,
+ VTCXO_OC_FLAG,
+ VA_OC_FLAG,
+ VCAMA_OC_FLAG,
+ VCAMD_OC_FLAG,
+ VIO28_OC_FLAG,
+ VUSB_OC_FLAG,
+ VBT_OC_FLAG,
+ VSIM_OC_FLAG,
+ VSIM2_OC_FLAG,
+ VRTC_OC_FLAG,
+ VIBR_OC_FLAG,
+ VMC_OC_FLAG,
+ VCORE_OC_FLAG,
+ VIO18_OC_FLAG,
+ SPK_OC_FLAG,
+ VRF_OC_STATUS,
+ VTCXO_OC_STATUS,
+ VA_OC_STATUS,
+ VCAMA_OC_STATUS,
+ VCAMD_OC_STATUS,
+ VIO28_OC_STATUS,
+ VUSB_OC_STATUS,
+ VBT_OC_STATUS,
+ VSIM_OC_STATUS,
+ VSIM2_OC_STATUS,
+ VRTC_OC_STATUS,
+ VIBR_OC_STATUS,
+ VMC_OC_STATUS,
+ VCORE_OC_STATUS,
+ VIO18_OC_STATUS,
+ SPK_OC_STATUS,
+ PMU_FLAGS_MAX
+}PMU_FLAGS_LIST_ENUM;
+
+#define LDO_GROUP (OFFSEL(BUCK_GROUP))
+#define BUCK_GROUP (M(VCORE))
+
+#endif //#if defined(PMIC_6255_REG_API)
+
+#endif //#ifndef __DCL_PMU6255_SW_H_STRUCT__
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6256_hw.h b/mcu/driver/peripheral/inc/dcl_pmu6256_hw.h
new file mode 100644
index 0000000..c16cb67
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6256_hw.h
@@ -0,0 +1,996 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2011
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6256_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for PMU 6256 driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __PMU6256_HW_H__
+#define __PMU6256_HW_H__
+
+
+#if defined(PMIC_6256_REG_API)
+
+#define PMU_BASE MIXED_base
+
+#define PMU_END (PMU_BASE+0x1000)
+
+///////////////////////////////////////////////////////////////////////////////
+// ABIST Group
+#define ABIST_CON0 (PMU_BASE + 0x0010)
+#define ABIST_CON1 (PMU_BASE + 0x0014)
+#define ABIST_CON2 (PMU_BASE + 0x0018)
+#define ABIST_CON3 (PMU_BASE + 0x001C)
+
+// EFUSE Group
+#define EFUSE_CON0 (PMU_BASE + 0x0100) // Only for 6256 E2
+#define EFUSE_CON1 (PMU_BASE + 0x0104) // Only for 6256 E2
+#define EFUSE_CON2 (PMU_BASE + 0x0108) // Only for 6256 E2
+#define EFUSE_CON3 (PMU_BASE + 0x010C) // Only for 6256 E2
+
+// LDO group
+#define VRF_CON0 (PMU_BASE + 0x0800)
+#define VTCXO_CON0 (PMU_BASE + 0x0810)
+#define VA_CON0 (PMU_BASE + 0x0820)
+#define VCAMA_CON0 (PMU_BASE + 0x0830)
+#define VCAMD_CON0 (PMU_BASE + 0x0840)
+#define VIO28_CON0 (PMU_BASE + 0x0850)
+#define VUSB_CON0 (PMU_BASE + 0x0860)
+#define VBT_CON0 (PMU_BASE + 0x0870)
+#define VSIM_CON0 (PMU_BASE + 0x0880)
+#define VSIM2_CON0 (PMU_BASE + 0x0890)
+#define VRTC_CON0 (PMU_BASE + 0x08A0)
+#define VIBR_CON0 (PMU_BASE + 0x08B0)
+#define VMC_CON0 (PMU_BASE + 0x08C0)
+#define VFM_CON0 (PMU_BASE + 0x08D0) // Only for 6256 E1
+#define VM12_CON0 (PMU_BASE + 0x08E0) // Only for 6256 E1
+#if !defined(MT6256_S00)
+#define VIO18_CON0 (PMU_BASE + 0x08F0) // Only for 6256 E2
+#endif // End of #if !defined(MT6256_S00)
+
+// BUCK group
+#define VCORE_CON0 (PMU_BASE + 0x0900)
+#if defined(MT6256_S00)
+#define VIO18_CON0 (PMU_BASE + 0x0920) // Only for 6256 E1
+#endif // End of #if defined(MT6256_S00)
+
+// BOOST group
+#define BOOST_CON0 (PMU_BASE + 0x0B00) // Only for 6256 E1
+
+// CHR
+#define CHR_CON0 (PMU_BASE + 0x0A00)
+
+// STARTUP
+#define STRUP_CON0 (PMU_BASE + 0x0A80)
+
+// iSINK group
+#define ISINK0_CON0 (PMU_BASE + 0x0C00)
+#define ISINK1_CON0 (PMU_BASE + 0x0C10)
+#define ISINK2_CON0 (PMU_BASE + 0x0C20)
+#define ISINK3_CON0 (PMU_BASE + 0x0C30)
+#define ISINK4_CON0 (PMU_BASE + 0x0C40) // Only for 6256 E2
+#define ISINK5_CON0 (PMU_BASE + 0x0C50) // Only for 6256 E2
+
+// KPLED group
+#define KPLED_CON0 (PMU_BASE + 0x0C80)
+
+// SPK
+#define SPK_CON0 (PMU_BASE + 0x0D00)
+
+// PMIC_OC
+#define PMIC_OC_CON0 (PMU_BASE + 0x0E00)
+#define PMIC_OC_CON1 (PMU_BASE + 0x0E04)
+#define PMIC_OC_CON2 (PMU_BASE + 0x0E08)
+#define PMIC_OC_CON3 (PMU_BASE + 0x0E0C)
+#define PMIC_OC_CON4 (PMU_BASE + 0x0E10)
+#define PMIC_OC_CON5 (PMU_BASE + 0x0E14)
+#define PMIC_OC_CON6 (PMU_BASE + 0x0E18)
+#define PMIC_OC_CON7 (PMU_BASE + 0x0E1C)
+
+///////////////////////////////////////////////////////////////////////////////
+
+#define CON0_OFFSET 0x00
+#define CON1_OFFSET 0x04
+#define CON2_OFFSET 0x08
+#define CON3_OFFSET 0x0C
+#define CON4_OFFSET 0x10
+#define CON5_OFFSET 0x14
+#define CON6_OFFSET 0x18
+#define CON7_OFFSET 0x1C
+#define CON8_OFFSET 0x20
+#define CON9_OFFSET 0x24
+#define CON10_OFFSET 0x28
+#define CONA_OFFSET 0x28
+#define CON11_OFFSET 0x2C
+#define CONB_OFFSET 0x2C
+#define CON12_OFFSET 0x30
+#define CON13_OFFSET 0x34
+#define CON14_OFFSET 0x38
+
+// ABIST
+#define ABIST_LMON_SEL_OFFSET CON1_OFFSET
+#define ABIST_LMON_SEL_MASK 0x00FF
+#define ABIST_LMON_SEL_SHIFT 0
+
+#define ABIST_HMON_SEL_OFFSET CON1_OFFSET
+#define ABIST_HMON_SEL_MASK 0xFF00
+#define ABIST_HMON_SEL_SHIFT 8
+
+#define ABIST_LMON_DATA_OFFSET CON3_OFFSET
+#define ABIST_LMON_DATA_MASK 0x000F
+#define ABIST_LMON_DATA_SHIFT 0
+
+#define ABIST_HMON_DATA_OFFSET CON3_OFFSET
+#define ABIST_HMON_DATA_MASK 0x00F0
+#define ABIST_HMON_DATA_SHIFT 4
+
+// LDO cmds
+// LDO_CON0
+#define LDO_BUCK_EN_OFFSET CON0_OFFSET
+#define LDO_BUCK_EN_MASK 0x0001
+#define LDO_BUCK_EN_SHIFT 0
+
+#define LDO_BUCK_ON_SEL_OFFSET CON0_OFFSET
+#define LDO_BUCK_ON_SEL_MASK 0x0002
+#define LDO_BUCK_ON_SEL_SHIFT 1
+
+#define LDO_BUCK_RS_OFFSET CON0_OFFSET
+#define LDO_BUCK_RS_MASK 0x0004
+#define LDO_BUCK_RS_SHIFT 2
+
+#define LDO_BUCK_VOL_SEL_OFFSET CON0_OFFSET // For VCAMA, VCAMD, VBT, VSIM, VSIM2, VIBR, VMC, VCORE
+#define LDO_BUCK_VOL_SEL_MASK 0x01F0
+#define LDO_BUCK_VOL_SEL_SHIFT 4
+
+#define LDO_BUCK_NDIS_EN_OFFSET CON0_OFFSET // BUCK: ANTIUNSH_DN
+#define LDO_BUCK_NDIS_EN_MASK 0x0400
+#define LDO_BUCK_NDIS_EN_SHIFT 10
+
+#define LDO_BUCK_STB_EN_OFFSET CON0_OFFSET
+#define LDO_BUCK_STB_EN_MASK 0x0800
+#define LDO_BUCK_STB_EN_SHIFT 11
+
+#define LDO_BUCK_OC_AUTO_OFF_OFFSET CON0_OFFSET
+#define LDO_BUCK_OC_AUTO_OFF_MASK 0x1000
+#define LDO_BUCK_OC_AUTO_OFF_SHIFT 12
+
+#define LDO_BUCK_OCFB_EN_OFFSET CON0_OFFSET
+#define LDO_BUCK_OCFB_EN_MASK 0x2000
+#define LDO_BUCK_OCFB_EN_SHIFT 13
+
+#define LDO_BUCK_OC_FLAG_OFFSET CON0_OFFSET
+#define LDO_BUCK_OC_FLAG_MASK 0x4000
+#define LDO_BUCK_OC_FLAG_SHIFT 14
+
+#define LDO_BUCK_STATUS_OFFSET CON0_OFFSET
+#define LDO_BUCK_STATUS_MASK 0x8000
+#define LDO_BUCK_STATUS_SHIFT 15
+
+// LDO_CON1
+#define LDO_CAL_OFFSET CON1_OFFSET
+#define LDO_CAL_MASK 0x01F0
+#define LDO_CAL_SHIFT 4
+
+#define LDO_STB_SEL_OFFSET CON1_OFFSET // For VIBR & VMC
+#define LDO_STB_SEL_MASK 0x1000
+#define LDO_STB_SEL_SHIFT 12
+
+// LDO_CON2
+#define LDO_EN_FORCE_OFFSET CON2_OFFSET
+#define LDO_EN_FORCE_MASK 0x0001
+#define LDO_EN_FORCE_SHIFT 0
+
+#define LDO_OC_TD_OFFSET CON2_OFFSET
+#define LDO_OC_TD_MASK 0x0030
+#define LDO_OC_TD_SHIFT 4
+
+#define LDO_STB_TD_OFFSET CON2_OFFSET
+#define LDO_STB_TD_MASK 0x00C0
+#define LDO_STB_TD_SHIFT 6
+
+// LDO_CON2 MISC
+#define CCI_SRCLKEN_OFFSET CON2_OFFSET
+#define CCI_SRCLKEN_MASK 0x0002
+#define CCI_SRCLKEN_SHIFT 1
+
+#define VA_LP_EN_OFFSET CON2_OFFSET
+#define VA_LP_EN_MASK 0x0002
+#define VA_LP_EN_SHIFT 1
+
+#define VSIM_GPLDO_EN_OFFSET CON2_OFFSET
+#define VSIM_GPLDO_EN_MASK 0x0002
+#define VSIM_GPLDO_EN_SHIFT 1
+
+#define VSIM2_GPLDO_EN_OFFSET CON2_OFFSET
+#define VSIM2_GPLDO_EN_MASK 0x0002
+#define VSIM2_GPLDO_EN_SHIFT 1
+
+#define SIM2_GPIO_EN_OFFSET CON3_OFFSET
+#define SIM2_GPIO_EN_MASK 0x0001
+#define SIM2_GPIO_EN_SHIFT 0
+
+// BUCK cmds
+#define BUCK_VFBADJ_SLEEP_OFFSET CON1_OFFSET
+#define BUCK_VFBADJ_SLEEP_MASK 0x01F0
+#define BUCK_VFBADJ_SLEEP_SHIFT 4
+
+#define BUCK_EN_FORCE_OFFSET CON3_OFFSET
+#define BUCK_EN_FORCE_MASK 0x0001
+#define BUCK_EN_FORCE_SHIFT 0
+
+#define BUCK_OC_TD_OFFSET CON3_OFFSET
+#define BUCK_OC_TD_MASK 0x0030
+#define BUCK_OC_TD_SHIFT 4
+
+#define BUCK_STB_TD_OFFSET CON3_OFFSET
+#define BUCK_STB_TD_MASK 0x00C0
+#define BUCK_STB_TD_SHIFT 6
+
+#define BUCK_OC_THD_OFFSET CON3_OFFSET
+#define BUCK_OC_THD_MASK 0x0300
+#define BUCK_OC_THD_SHIFT 8
+
+#define BUCK_OC_WND_OFFSET CON3_OFFSET
+#define BUCK_OC_WND_MASK 0x0C00
+#define BUCK_OC_WND_SHIFT 10
+
+#define BUCK_ICAL_EN_OFFSET CON3_OFFSET
+#define BUCK_ICAL_EN_MASK 0x3000
+#define BUCK_ICAL_EN_SHIFT 12
+
+#define BUCK_CSL_OFFSET CON5_OFFSET
+#define BUCK_CSL_MASK 0x0700
+#define BUCK_CSL_SHIFT 8
+
+#define BUCK_BURST_OFFSET CON5_OFFSET
+#define BUCK_BURST_MASK 0x3000
+#define BUCK_BURST_SHIFT 12
+
+// CHR cmds
+// CHR_CON0
+#define VCDT_HV_EN_OFFSET CON0_OFFSET
+#define VCDT_HV_EN_MASK 0x0001
+#define VCDT_HV_EN_SHIFT 0
+
+#define CHR_LDO_DET_OFFSET CON0_OFFSET
+#define CHR_LDO_DET_MASK 0x0002
+#define CHR_LDO_DET_SHIFT 1
+
+#define PCHR_AUTOMODE_OFFSET CON0_OFFSET
+#define PCHR_AUTOMODE_MASK 0x0004
+#define PCHR_AUTOMODE_SHIFT 2
+
+#define CSDAC_EN_OFFSET CON0_OFFSET
+#define CSDAC_EN_MASK 0x0008
+#define CSDAC_EN_SHIFT 3
+
+#define CHR_EN_OFFSET CON0_OFFSET
+#define CHR_EN_MASK 0x0010
+#define CHR_EN_SHIFT 4
+
+#define CHRDET_OFFSET CON0_OFFSET
+#define CHRDET_MASK 0x0020
+#define CHRDET_SHIFT 5
+
+#define VCDT_LV_DET_OFFSET CON0_OFFSET
+#define VCDT_LV_DET_MASK 0x0040
+#define VCDT_LV_DET_SHIFT 6
+
+#define VCDT_HV_DET_OFFSET CON0_OFFSET
+#define VCDT_HV_DET_MASK 0x0080
+#define VCDT_HV_DET_SHIFT 7
+
+#define VCDT_LV_VTH_OFFSET CON0_OFFSET
+#define VCDT_LV_VTH_MASK 0x0F00
+#define VCDT_LV_VTH_SHIFT 8
+
+#define VCDT_HV_VTH_OFFSET CON0_OFFSET
+#define VCDT_HV_VTH_MASK 0xF000
+#define VCDT_HV_VTH_SHIFT 12
+
+// CHR_CON1
+#define VBAT_CV_EN_OFFSET CON1_OFFSET
+#define VBAT_CV_EN_MASK 0x0001
+#define VBAT_CV_EN_SHIFT 0
+
+#define VBAT_CC_EN_OFFSET CON1_OFFSET
+#define VBAT_CC_EN_MASK 0x0002
+#define VBAT_CC_EN_SHIFT 1
+
+#define VBAT_CV_DET_OFFSET CON1_OFFSET
+#define VBAT_CV_DET_MASK 0x0004
+#define VBAT_CV_DET_SHIFT 2
+
+#define VBAT_CC_DET_OFFSET CON1_OFFSET
+#define VBAT_CC_DET_MASK 0x0008
+#define VBAT_CC_DET_SHIFT 3
+
+#define VBAT_CC_VTH_OFFSET CON1_OFFSET
+#define VBAT_CC_VTH_MASK 0x0030
+#define VBAT_CC_VTH_SHIFT 4
+
+#define VBAT_CV_VTH_OFFSET CON1_OFFSET
+#define VBAT_CV_VTH_MASK 0x1F00
+#define VBAT_CV_VTH_SHIFT 8
+
+// CHR_CON2
+#define CS_VTH_OFFSET CON2_OFFSET
+#define CS_VTH_MASK 0x000F
+#define CS_VTH_SHIFT 0
+
+#define CS_EN_OFFSET CON2_OFFSET
+#define CS_EN_MASK 0x0100
+#define CS_EN_SHIFT 8
+
+#define CS_DET_OFFSET CON2_OFFSET
+#define CS_DET_MASK 0x8000
+#define CS_DET_SHIFT 15
+
+// CHR_CON3
+#define TOHTC_OFFSET CON3_OFFSET
+#define TOHTC_MASK 0x0007
+#define TOHTC_SHIFT 0
+
+#define TOLTC_OFFSET CON3_OFFSET
+#define TOLTC_MASK 0x0700
+#define TOLTC_SHIFT 8
+
+// CHR_CON4
+#define CSDAC_STP_INC_OFFSET CON4_OFFSET
+#define CSDAC_STP_INC_MASK 0x0007
+#define CSDAC_STP_INC_SHIFT 0
+
+#define CSDAC_STP_DEC_OFFSET CON4_OFFSET
+#define CSDAC_STP_DEC_MASK 0x0070
+#define CSDAC_STP_DEC_SHIFT 4
+
+#define CSDAC_STP_OFFSET CON4_OFFSET
+#define CSDAC_STP_MASK 0x0700
+#define CSDAC_STP_SHIFT 8
+
+#define CSDAC_DLY_OFFSET CON4_OFFSET
+#define CSDAC_DLY_MASK 0x7000
+#define CSDAC_DLY_SHIFT 12
+
+// CHR_CON5
+#define VBAT_OV_EN_OFFSET CON5_OFFSET
+#define VBAT_OV_EN_MASK 0x0001
+#define VBAT_OV_EN_SHIFT 0
+
+#define VBAT_OV_DEG_OFFSET CON5_OFFSET
+#define VBAT_OV_DEG_MASK 0x0002
+#define VBAT_OV_DEG_SHIFT 1
+
+#define VBAT_OV_DET_OFFSET CON5_OFFSET
+#define VBAT_OV_DET_MASK 0x0008
+#define VBAT_OV_DET_SHIFT 3
+
+#define VBAT_OV_VTH_OFFSET CON5_OFFSET
+#define VBAT_OV_VTH_MASK 0x0030
+#define VBAT_OV_VTH_SHIFT 4
+
+#define BATON_EN_OFFSET CON5_OFFSET
+#define BATON_EN_MASK 0x0100
+#define BATON_EN_SHIFT 8
+
+#define BATON_HT_EN_OFFSET CON5_OFFSET
+#define BATON_HT_EN_MASK 0x0200
+#define BATON_HT_EN_SHIFT 9
+
+#define BATON_UNDET_OFFSET CON5_OFFSET
+#define BATON_UNDET_MASK 0x0400
+#define BATON_UNDET_SHIFT 10
+
+// CHR_CON6
+#define CSDAC_DATA_OFFSET CON6_OFFSET
+#define CSDAC_DATA_MASK 0x03FF
+#define CSDAC_DATA_SHIFT 0
+
+// CHR_CON7
+#define OTG_BVALID_EN_OFFSET CON7_OFFSET
+#define OTG_BVALID_EN_MASK 0x0001
+#define OTG_BVALID_EN_SHIFT 0
+
+#define OTG_BVALID_OFFSET CON7_OFFSET
+#define OTG_BVALID_MASK 0x0008
+#define OTG_BVALID_SHIFT 3
+
+#define PCHR_TESTMODE_OFFSET CON7_OFFSET
+#define PCHR_TESTMODE_MASK 0x0010
+#define PCHR_TESTMODE_SHIFT 4
+
+#define CSDAC_TESTMODE_OFFSET CON7_OFFSET
+#define CSDAC_TESTMODE_MASK 0x0020
+#define CSDAC_TESTMODE_SHIFT 5
+
+#define PCHR_RST_OFFSET CON7_OFFSET
+#define PCHR_RST_MASK 0x0040
+#define PCHR_RST_SHIFT 6
+
+#define PCHR_FT_CTRL_OFFSET CON7_OFFSET
+#define PCHR_FT_CTRL_MASK 0x0700
+#define PCHR_FT_CTRL_SHIFT 8
+
+// CHR_CON8
+#define PCHR_FLAG_OUT_OFFSET CON8_OFFSET
+#define PCHR_FLAG_OUT_MASK 0x000F
+#define PCHR_FLAG_OUT_SHIFT 0
+
+#define PCHR_FLAG_EN_OFFSET CON8_OFFSET
+#define PCHR_FLAG_EN_MASK 0x0080
+#define PCHR_FLAG_EN_SHIFT 7
+
+#define PCHR_FLAG_SEL_OFFSET CON8_OFFSET
+#define PCHR_FLAG_SEL_MASK 0x1F00
+#define PCHR_FLAG_SEL_SHIFT 8
+
+// CHR_CON9
+#define CHRWDT_TD_OFFSET CON9_OFFSET
+#define CHRWDT_TD_MASK 0x000F
+#define CHRWDT_TD_SHIFT 0
+
+#define CHRWDT_EN_OFFSET CON9_OFFSET
+#define CHRWDT_EN_MASK 0x0010
+#define CHRWDT_EN_SHIFT 4
+
+#define CHRWDT_INT_EN_OFFSET CON9_OFFSET
+#define CHRWDT_INT_EN_MASK 0x0100
+#define CHRWDT_INT_EN_SHIFT 8
+
+#define CHRWDT_FLAG_OFFSET CON9_OFFSET
+#define CHRWDT_FLAG_MASK 0x0200
+#define CHRWDT_FLAG_SHIFT 9
+
+#define CHRWDT_OUT_OFFSET CON9_OFFSET
+#define CHRWDT_OUT_MASK 0x8000
+#define CHRWDT_OUT_SHIFT 15
+
+// CHR_CON10
+#define UVLO_VTHL_OFFSET CON10_OFFSET
+#define UVLO_VTHL_MASK 0x0003
+#define UVLO_VTHL_SHIFT 0
+
+#define ADC_EN_OFFSET CON10_OFFSET
+#define ADC_EN_MASK 0x0070 // All ADC channels are enabled at same time
+#define ADC_EN_SHIFT 4
+
+#define ADCIN_VBAT_EN_OFFSET CON10_OFFSET
+#define ADCIN_VBAT_EN_MASK 0x0010
+#define ADCIN_VBAT_EN_SHIFT 4
+
+#define ADCIN_VSEN_EN_OFFSET CON10_OFFSET
+#define ADCIN_VSEN_EN_MASK 0x0020
+#define ADCIN_VSEN_EN_SHIFT 5
+
+#define ADCIN_CHR_EN_OFFSET CON10_OFFSET
+#define ADCIN_CHR_EN_MASK 0x0040
+#define ADCIN_CHR_EN_SHIFT 6
+
+#define BGR_RSEL_OFFSET CON10_OFFSET
+#define BGR_RSEL_MASK 0x0700
+#define BGR_RSEL_SHIFT 8
+
+#define BGR_UNCHOP_PH_OFFSET CON10_OFFSET
+#define BGR_UNCHOP_PH_MASK 0x1000
+#define BGR_UNCHOP_PH_SHIFT 12
+
+#define BGR_UNCHOP_OFFSET CON10_OFFSET
+#define BGR_UNCHOP_MASK 0x2000
+#define BGR_UNCHOP_SHIFT 13
+
+#define USBDL_RST_OFFSET CON10_OFFSET
+#define USBDL_RST_MASK 0x4000
+#define USBDL_RST_SHIFT 14
+
+#define USBDL_SET_OFFSET CON10_OFFSET
+#define USBDL_SET_MASK 0x8000
+#define USBDL_SET_SHIFT 15
+
+// CHR_CON11
+#define BC11_CMP_EN_OFFSET CON11_OFFSET
+#define BC11_CMP_EN_MASK 0x0003
+#define BC11_CMP_EN_SHIFT 0
+
+#define BC11_VSRC_EN_OFFSET CON11_OFFSET
+#define BC11_VSRC_EN_MASK 0x000C
+#define BC11_VSRC_EN_SHIFT 2
+
+#define BC11_IPD_EN_OFFSET CON11_OFFSET
+#define BC11_IPD_EN_MASK 0x0030
+#define BC11_IPD_EN_SHIFT 4
+
+#define BC11_IPU_EN_OFFSET CON11_OFFSET
+#define BC11_IPU_EN_MASK 0x00C0
+#define BC11_IPU_EN_SHIFT 6
+
+#define BC11_VREF_VTH_OFFSET CON11_OFFSET
+#define BC11_VREF_VTH_MASK 0x0100
+#define BC11_VREF_VTH_SHIFT 8
+
+#define BC11_BIAS_EN_OFFSET CON11_OFFSET
+#define BC11_BIAS_EN_MASK 0x0200
+#define BC11_BIAS_EN_SHIFT 9
+
+#define BC11_BB_CTRL_OFFSET CON11_OFFSET
+#define BC11_BB_CTRL_MASK 0x0400
+#define BC11_BB_CTRL_SHIFT 10
+
+#define BC11_RST_OFFSET CON11_OFFSET
+#define BC11_RST_MASK 0x0800
+#define BC11_RST_SHIFT 11
+
+#define BC11_CMP_OUT_OFFSET CON11_OFFSET
+#define BC11_CMP_OUT_MASK 0x8000
+#define BC11_CMP_OUT_SHIFT 15
+
+// CHR_CON12
+#define CV_MODE_OFFSET CON12_OFFSET
+#define CV_MODE_MASK 0x0001
+#define CV_MODE_SHIFT 0
+
+#define VCDT_MODE_OFFSET CON12_OFFSET
+#define VCDT_MODE_MASK 0x0002
+#define VCDT_MODE_SHIFT 1
+
+#define CSDAC_MODE_OFFSET CON12_OFFSET
+#define CSDAC_MODE_MASK 0x0004
+#define CSDAC_MODE_SHIFT 2
+
+#define TRACKING_EN_OFFSET CON12_OFFSET
+#define TRACKING_EN_MASK 0x0010
+#define TRACKING_EN_SHIFT 4
+
+#define HWCV_EN_OFFSET CON12_OFFSET
+#define HWCV_EN_MASK 0x0040
+#define HWCV_EN_SHIFT 6
+
+#define ULC_DET_EN_OFFSET CON12_OFFSET
+#define ULC_DET_EN_MASK 0x0080
+#define ULC_DET_EN_SHIFT 7
+
+#define LOW_ICH_DB_OFFSET CON12_OFFSET
+#define LOW_ICH_DB_MASK 0x3F00
+#define LOW_ICH_DB_SHIFT 8
+
+// CHR_CON13
+#define OVP_TRIM_OFFSET CON13_OFFSET
+#define OVP_TRIM_MASK 0x000F
+#define OVP_TRIM_SHIFT 0
+
+#define DRV_ITUNE_OFFSET CON14_OFFSET
+#define DRV_ITUNE_MASK 0x0300
+#define DRV_ITUNE_SHIFT 8
+
+// STRUP cmds
+// STRUP_CON0
+#define USBDL_EN_OFFSET CON0_OFFSET
+#define USBDL_EN_MASK 0x0010
+#define USBDL_EN_SHIFT 4
+
+// ISINK cmds
+// ISINK_CON0
+#define ISINK_EN_OFFSET CON0_OFFSET
+#define ISINK_EN_MASK 0x0001
+#define ISINK_EN_SHIFT 0
+
+#define ISINK_MODE_OFFSET CON0_OFFSET
+#define ISINK_MODE_MASK 0x0002
+#define ISINK_MODE_SHIFT 1
+
+#define ISINK_STEP_OFFSET CON0_OFFSET
+#define ISINK_STEP_MASK 0x0070
+#define ISINK_STEP_SHIFT 4
+
+#define ISINK_STATUS_OFFSET CON0_OFFSET
+#define ISINK_STATUS_MASK 0x8000
+#define ISINK_STATUS_SHIFT 15
+
+// ISINK_CON1
+#define ISINK_FORCE_OFF_OFFSET CON1_OFFSET
+#define ISINK_FORCE_OFF_MASK 0x0001
+#define ISINK_FORCE_OFF_SHIFT 0
+
+#define ISINK_VREF_CAL_OFFSET CON1_OFFSET
+#define ISINK_VREF_CAL_MASK 0x1F00
+#define ISINK_VREF_CAL_SHIFT 8
+
+// KPLED
+// KPLED_CON0
+#define KPLED_EN_OFFSET CON0_OFFSET
+#define KPLED_EN_MASK 0x0001
+#define KPLED_EN_SHIFT 0
+
+#define KPLED_MODE_OFFSET CON0_OFFSET
+#define KPLED_MODE_MASK 0x0002
+#define KPLED_MODE_SHIFT 1
+
+#define KPLED_SEL_OFFSET CON0_OFFSET
+#define KPLED_SEL_MASK 0x0070
+#define KPLED_SEL_SHIFT 4
+
+#define KPLED_SFSTRTC_OFFSET CON0_OFFSET
+#define KPLED_SFSTRTC_MASK 0x0300
+#define KPLED_SFSTRTC_SHIFT 8
+
+#define KPLED_SFSTREN_OFFSET CON0_OFFSET
+#define KPLED_SFSTREN_MASK 0x0400
+#define KPLED_SFSTREN_SHIFT 10
+
+#define KPLED_STATUS_OFFSET CON0_OFFSET
+#define KPLED_STATUS_MASK 0x8000
+#define KPLED_STATUS_SHIFT 15
+
+// KPLED_CON1
+#define KPLED_FORCE_OFF_OFFSET CON1_OFFSET
+#define KPLED_FORCE_OFF_MASK 0x0001
+#define KPLED_FORCE_OFF_SHIFT 0
+
+// SPK
+// SPK_CON0
+#define SPK_EN_OFFSET CON0_OFFSET
+#define SPK_EN_MASK 0x0001
+#define SPK_EN_SHIFT 0
+
+#define SPK_RST_OFFSET CON0_OFFSET
+#define SPK_RST_MASK 0x0002
+#define SPK_RST_SHIFT 1
+
+#define SPK_DTCAL_OFFSET CON0_OFFSET
+#define SPK_DTCAL_MASK 0x0008
+#define SPK_DTCAL_SHIFT 3
+
+#define SPK_VOL_OFFSET CON0_OFFSET
+#define SPK_VOL_MASK 0x0010
+#define SPK_VOL_SHIFT 4
+
+#define SPK_OC_AUTOFF_OFFSET CON0_OFFSET
+#define SPK_OC_AUTOFF_MASK 0x1000
+#define SPK_OC_AUTOFF_SHIFT 12
+
+#define SPK_OC_FLAG_EN_OFFSET CON0_OFFSET
+#define SPK_OC_FLAG_EN_MASK 0x4000
+#define SPK_OC_FLAG_EN_SHIFT 14
+
+// SPK_CON1
+#define SPK_PFD_MODE_OFFSET CON1_OFFSET
+#define SPK_PFD_MODE_MASK 0x0001
+#define SPK_PFD_MODE_SHIFT 0
+
+#define SPK_CMODE_OFFSET CON1_OFFSET
+#define SPK_CMODE_MASK 0x000C
+#define SPK_CMODE_SHIFT 2
+
+#define SPK_CCODE_OFFSET CON1_OFFSET
+#define SPK_CCODE_MASK 0x00F0
+#define SPK_CCODE_SHIFT 4
+
+// SPK_CON2
+#define SPK_OC_THD_OFFSET CON2_OFFSET
+#define SPK_OC_THD_MASK 0x0030
+#define SPK_OC_THD_SHIFT 4
+
+#define SPK_OC_WND_OFFSET CON2_OFFSET
+#define SPK_OC_WND_MASK 0x00C0
+#define SPK_OC_WND_SHIFT 6
+
+// SPK_CON3
+#define SPK_OC_EN_OFFSET CON3_OFFSET
+#define SPK_OC_EN_MASK 0x0400
+#define SPK_OC_EN_SHIFT 10
+
+
+// SPK_CON5
+#define SPK_PG_SLEW_I_OFFSET CON5_OFFSET
+#define SPK_PG_SLEW_I_MASK 0x3000
+#define SPK_PG_SLEW_I_SHIFT 12
+
+// SPK_CON7
+#define SPKMODE_OFFSET CON7_OFFSET
+#define SPKMODE_MASK 0x0001
+#define SPKMODE_SHIFT 0
+
+#define SPKAB_OBIAS_OFFSET CON7_OFFSET
+#define SPKAB_OBIAS_MASK 0x0030
+#define SPKAB_OBIAS_SHIFT 4
+
+#define SPKAB_OC_EN_OFFSET CON7_OFFSET
+#define SPKAB_OC_EN_MASK 0x0010
+#define SPKAB_OC_EN_SHIFT 8
+
+// SPK_CON8
+#define SPK_CALIBR_EN_OFFSET CON8_OFFSET
+#define SPK_CALIBR_EN_MASK 0x0040
+#define SPK_CALIBR_EN_SHIFT 6
+
+#define SPK_CALIBR_SEL_OFFSET CON8_OFFSET
+#define SPK_CALIBR_SEL_MASK 0x0200
+#define SPK_CALIBR_SEL_SHIFT 9
+
+// PMIC_OC
+// PMIC_OC_CON0
+#define VRF_OC_INT_EN_OFFSET CON0_OFFSET
+#define VRF_OC_INT_EN_MASK 0x0001
+#define VRF_OC_INT_EN_SHIFT 0
+
+#define VTCXO_OC_INT_EN_OFFSET CON0_OFFSET
+#define VTCXO_OC_INT_EN_MASK 0x0002
+#define VTCXO_OC_INT_EN_SHIFT 1
+
+#define VA_OC_INT_EN_OFFSET CON0_OFFSET
+#define VA_OC_INT_EN_MASK 0x0004
+#define VA_OC_INT_EN_SHIFT 2
+
+#define VCAMA_OC_INT_EN_OFFSET CON0_OFFSET
+#define VCAMA_OC_INT_EN_MASK 0x0008
+#define VCAMA_OC_INT_EN_SHIFT 3
+
+#define VCAMD_OC_INT_EN_OFFSET CON0_OFFSET
+#define VCAMD_OC_INT_EN_MASK 0x0010
+#define VCAMD_OC_INT_EN_SHIFT 4
+
+#define VIO28_OC_INT_EN_OFFSET CON0_OFFSET
+#define VIO28_OC_INT_EN_MASK 0x0020
+#define VIO28_OC_INT_EN_SHIFT 5
+
+#define VUSB_OC_INT_EN_OFFSET CON0_OFFSET
+#define VUSB_OC_INT_EN_MASK 0x0040
+#define VUSB_OC_INT_EN_SHIFT 6
+
+#define VBT_OC_INT_EN_OFFSET CON0_OFFSET
+#define VBT_OC_INT_EN_MASK 0x0080
+#define VBT_OC_INT_EN_SHIFT 7
+
+#define VSIM_OC_INT_EN_OFFSET CON0_OFFSET
+#define VSIM_OC_INT_EN_MASK 0x0100
+#define VSIM_OC_INT_EN_SHIFT 8
+
+#define VSIM2_OC_INT_EN_OFFSET CON0_OFFSET
+#define VSIM2_OC_INT_EN_MASK 0x0200
+#define VSIM2_OC_INT_EN_SHIFT 9
+
+#define VRTC_OC_INT_EN_OFFSET CON0_OFFSET
+#define VRTC_OC_INT_EN_MASK 0x0400
+#define VRTC_OC_INT_EN_SHIFT 10
+
+#define VIBR_OC_INT_EN_OFFSET CON0_OFFSET
+#define VIBR_OC_INT_EN_MASK 0x0800
+#define VIBR_OC_INT_EN_SHIFT 11
+
+#define VMC_OC_INT_EN_OFFSET CON0_OFFSET
+#define VMC_OC_INT_EN_MASK 0x1000
+#define VMC_OC_INT_EN_SHIFT 12
+
+// PMIC_OC_CON1
+#define VCORE_OC_INT_EN_OFFSET CON1_OFFSET
+#define VCORE_OC_INT_EN_MASK 0x0001
+#define VCORE_OC_INT_EN_SHIFT 0
+
+#define VIO18_OC_INT_EN_OFFSET CON1_OFFSET
+#define VIO18_OC_INT_EN_MASK 0x0002
+#define VIO18_OC_INT_EN_SHIFT 1
+
+// PMIC_OC_CON3
+#define SPK_OC_INT_EN_OFFSET CON3_OFFSET
+#define SPK_OC_INT_EN_MASK 0x0001
+#define SPK_OC_INT_EN_SHIFT 0
+
+// PMIC_OC_CON4
+#define VRF_OC_FLAG_OFFSET CON4_OFFSET
+#define VRF_OC_FLAG_MASK 0x0001
+#define VRF_OC_FLAG_SHIFT 0
+
+#define VTCXO_OC_FLAG_OFFSET CON4_OFFSET
+#define VTCXO_OC_FLAG_MASK 0x0002
+#define VTCXO_OC_FLAG_SHIFT 1
+
+#define VA_OC_FLAG_OFFSET CON4_OFFSET
+#define VA_OC_FLAG_MASK 0x0004
+#define VA_OC_FLAG_SHIFT 2
+
+#define VCAMA_OC_FLAG_OFFSET CON4_OFFSET
+#define VCAMA_OC_FLAG_MASK 0x0008
+#define VCAMA_OC_FLAG_SHIFT 3
+
+#define VCAMD_OC_FLAG_OFFSET CON4_OFFSET
+#define VCAMD_OC_FLAG_MASK 0x0010
+#define VCAMD_OC_FLAG_SHIFT 4
+
+#define VIO28_OC_FLAG_OFFSET CON4_OFFSET
+#define VIO28_OC_FLAG_MASK 0x0020
+#define VIO28_OC_FLAG_SHIFT 5
+
+#define VUSB_OC_FLAG_OFFSET CON4_OFFSET
+#define VUSB_OC_FLAG_MASK 0x0040
+#define VUSB_OC_FLAG_SHIFT 6
+
+#define VBT_OC_FLAG_OFFSET CON4_OFFSET
+#define VBT_OC_FLAG_MASK 0x0080
+#define VBT_OC_FLAG_SHIFT 7
+
+#define VSIM_OC_FLAG_OFFSET CON4_OFFSET
+#define VSIM_OC_FLAG_MASK 0x0100
+#define VSIM_OC_FLAG_SHIFT 8
+
+#define VSIM2_OC_FLAG_OFFSET CON4_OFFSET
+#define VSIM2_OC_FLAG_MASK 0x0200
+#define VSIM2_OC_FLAG_SHIFT 9
+
+#define VRTC_OC_FLAG_OFFSET CON4_OFFSET
+#define VRTC_OC_FLAG_MASK 0x0400
+#define VRTC_OC_FLAG_SHIFT 10
+
+#define VIBR_OC_FLAG_OFFSET CON4_OFFSET
+#define VIBR_OC_FLAG_MASK 0x0800
+#define VIBR_OC_FLAG_SHIFT 11
+
+#define VMC_OC_FLAG_OFFSET CON4_OFFSET
+#define VMC_OC_FLAG_MASK 0x1000
+#define VMC_OC_FLAG_SHIFT 12
+
+// PMIC_OC_CON5
+#define VCORE_OC_FLAG_OFFSET CON5_OFFSET
+#define VCORE_OC_FLAG_MASK 0x0001
+#define VCORE_OC_FLAG_SHIFT 0
+
+#define VIO18_OC_FLAG_OFFSET CON5_OFFSET
+#define VIO18_OC_FLAG_MASK 0x0002
+#define VIO18_OC_FLAG_SHIFT 1
+
+// PMIC_OC_CON7
+#define SPK_OC_FLAG_OFFSET CON7_OFFSET
+#define SPK_OC_FLAG_MASK 0x0001
+#define SPK_OC_FLAG_SHIFT 0
+
+// PMIC_OC_CON8
+#define VRF_OC_STATUS_OFFSET CON8_OFFSET
+#define VRF_OC_STATUS_MASK 0x0001
+#define VRF_OC_STATUS_SHIFT 0
+
+#define VTCXO_OC_STATUS_OFFSET CON8_OFFSET
+#define VTCXO_OC_STATUS_MASK 0x0002
+#define VTCXO_OC_STATUS_SHIFT 1
+
+#define VA_OC_STATUS_OFFSET CON8_OFFSET
+#define VA_OC_STATUS_MASK 0x0004
+#define VA_OC_STATUS_SHIFT 2
+
+#define VCAMA_OC_STATUS_OFFSET CON8_OFFSET
+#define VCAMA_OC_STATUS_MASK 0x0008
+#define VCAMA_OC_STATUS_SHIFT 3
+
+#define VCAMD_OC_STATUS_OFFSET CON8_OFFSET
+#define VCAMD_OC_STATUS_MASK 0x0010
+#define VCAMD_OC_STATUS_SHIFT 4
+
+#define VIO28_OC_STATUS_OFFSET CON8_OFFSET
+#define VIO28_OC_STATUS_MASK 0x0020
+#define VIO28_OC_STATUS_SHIFT 5
+
+#define VUSB_OC_STATUS_OFFSET CON8_OFFSET
+#define VUSB_OC_STATUS_MASK 0x0040
+#define VUSB_OC_STATUS_SHIFT 6
+
+#define VBT_OC_STATUS_OFFSET CON8_OFFSET
+#define VBT_OC_STATUS_MASK 0x0080
+#define VBT_OC_STATUS_SHIFT 7
+
+#define VSIM_OC_STATUS_OFFSET CON8_OFFSET
+#define VSIM_OC_STATUS_MASK 0x0100
+#define VSIM_OC_STATUS_SHIFT 8
+
+#define VSIM2_OC_STATUS_OFFSET CON8_OFFSET
+#define VSIM2_OC_STATUS_MASK 0x0200
+#define VSIM2_OC_STATUS_SHIFT 9
+
+#define VRTC_OC_STATUS_OFFSET CON8_OFFSET
+#define VRTC_OC_STATUS_MASK 0x0400
+#define VRTC_OC_STATUS_SHIFT 10
+
+#define VIBR_OC_STATUS_OFFSET CON8_OFFSET
+#define VIBR_OC_STATUS_MASK 0x0800
+#define VIBR_OC_STATUS_SHIFT 11
+
+#define VMC_OC_STATUS_OFFSET CON8_OFFSET
+#define VMC_OC_STATUS_MASK 0x1000
+#define VMC_OC_STATUS_SHIFT 12
+
+// PMIC_OC_CON9
+#define VCORE_OC_STATUS_OFFSET CON9_OFFSET
+#define VCORE_OC_STATUS_MASK 0x0001
+#define VCORE_OC_STATUS_SHIFT 0
+
+#define VIO18_OC_STATUS_OFFSET CON9_OFFSET
+#define VIO18_OC_STATUS_MASK 0x0002
+#define VIO18_OC_STATUS_SHIFT 1
+
+// PMIC_OC_CONB
+#define SPK_OC_STATUS_OFFSET CONB_OFFSET
+#define SPK_OC_STATUS_MASK 0x0001
+#define SPK_OC_STATUS_SHIFT 0
+
+#endif // #if defined(PMIC_6256_REG_API)
+
+#endif // #ifndef __PMU6256_HW_H__
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6256_sw.h b/mcu/driver/peripheral/inc/dcl_pmu6256_sw.h
new file mode 100644
index 0000000..76fb5e7
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6256_sw.h
@@ -0,0 +1,294 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2011
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6256_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMU6256 s/w setting.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef __DCL_PMU6256_SW_H_STRUCT__
+#define __DCL_PMU6256_SW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6256_REG_API)
+
+/* Charger external interrupt is fixed. */
+#define PMU_CHR_EINT_PIN 15
+#define PMU_OC_EINT_PIN 16
+#define PMU_CHR_OVP_EINT_PIN 17
+#define PMU_CHR_LDO_EINT_PIN 19
+
+/* adc number for measuring VBAT/VISENSE/VCHARGER is fixed internally. */
+#define PMU_ADC_VBAT_CH_NUM 0
+#define PMU_ADC_VISENSE_CH_NUM 1
+#define PMU_ADC_VCHARGER_CH_NUM 2
+#define PMU_ADC_VBATTEMP_CH_NUM 3
+
+/* adc factor for VBAT/VISENSE/VCHARGER */
+#define PMU_ADC_FACTOR_VBAT 100
+#define PMU_ADC_FACTOR_VISENSE 100
+#if defined(MT6256_S00)
+#define PMU_ADC_FACTOR_VCHARGER 344 // (351/51 * 50)
+#else
+#define PMU_ADC_FACTOR_VCHARGER 473 // (369/39 * 50)
+#endif // End of #if defined(MT6256_S00)
+#define PMU_ADC_FACTOR_VBATTEMP 100
+
+typedef enum
+{
+ LDO_BUCK_EN,
+ LDO_BUCK_ON_SEL,
+ LDO_BUCK_RS,
+ LDO_BUCK_VOL_SEL,
+ LDO_BUCK_NDIS_EN,
+ LDO_BUCK_STB_EN,
+ LDO_BUCK_OC_AUTO_OFF,
+ LDO_BUCK_OCFB_EN,
+ LDO_BUCK_OC_FLAG,
+ LDO_BUCK_STATUS,
+ LDO_CAL,
+ LDO_STB_SEL,
+ LDO_EN_FORCE,
+ LDO_OC_TD,
+ LDO_STB_TD,
+ CCI_SRCLKEN,
+ VA_LP_EN,
+ VSIM_GPLDO_EN,
+ VSIM2_GPLDO_EN,
+ SIM2_GPIO_EN,
+ BUCK_VFBADJ_SLEEP,
+ BUCK_EN_FORCE,
+ BUCK_STB_TD,
+ BUCK_OC_THD,
+ BUCK_OC_WND,
+ BUCK_ICAL_EN,
+ BUCK_CSL,
+ BUCK_BURST,
+ VCDT_HV_EN,
+// CHR_LDO_DET,
+ CSDAC_EN,
+ CHR_EN,
+ CHRDET,
+ VCDT_HV_VTH,
+ VBAT_CV_EN,
+ VBAT_CV_DET,
+ VBAT_CV_VTH,
+ CS_VTH,
+ CSDAC_STP_INC,
+ CSDAC_STP_DEC,
+ CSDAC_STP,
+ CSDAC_DLY,
+ VBAT_OV_VTH,
+ BATON_EN,
+ BATON_HT_EN,
+ BATON_UNDET,
+ OTG_BVALID_EN,
+ OTG_BVALID,
+ CHRWDT_TD,
+ CHRWDT_EN,
+ CHRWDT_INT_EN,
+ CHRWDT_FLAG,
+ ADC_EN,
+ USBDL_RST,
+ USBDL_SET,
+ BC11_CMP_EN,
+ BC11_VSRC_EN,
+ BC11_IPD_EN,
+ BC11_IPU_EN,
+ BC11_VREF_VTH,
+ BC11_BIAS_EN,
+ BC11_BB_CTRL,
+ BC11_RST,
+ BC11_CMP_OUT,
+ CV_MODE,
+ VCDT_MODE,
+ CSDAC_MODE,
+ TRACKING_EN,
+ HWCV_EN,
+ ULC_DET_EN,
+ LOW_ICH_DB,
+ USBDL_EN,
+ VBAT_CC_DET,
+ ISINK_EN,
+ ISINK_MODE,
+ ISINK_STEP,
+ KPLED_EN,
+ KPLED_MODE,
+ KPLED_SEL,
+ SPK_EN,
+ SPK_VOL,
+ SPK_CCODE,
+ SPK_OC_EN,
+ SPK_PG_SLEW_I,
+ SPKAB_OC_EN,
+ SPKAB_OBIAS,
+ SPKMODE,
+ SPK_CALIBR_EN,
+ SPK_CALIBR_SEL,
+ ABIST_LMON_SEL,
+ ABIST_HMON_SEL,
+ ABIST_LMON_DATA,
+ ABIST_HMON_DATA,
+ VRF_OC_INT_EN,
+ VTCXO_OC_INT_EN,
+ VA_OC_INT_EN,
+ VCAMA_OC_INT_EN,
+ VCAMD_OC_INT_EN,
+ VIO28_OC_INT_EN,
+ VUSB_OC_INT_EN,
+ VBT_OC_INT_EN,
+ VSIM_OC_INT_EN,
+ VSIM2_OC_INT_EN,
+ VRTC_OC_INT_EN,
+ VIBR_OC_INT_EN,
+ VMC_OC_INT_EN,
+ VCORE_OC_INT_EN,
+ VIO18_OC_INT_EN,
+ SPK_OC_INT_EN,
+ VRF_OC_FLAG,
+ VTCXO_OC_FLAG,
+ VA_OC_FLAG,
+ VCAMA_OC_FLAG,
+ VCAMD_OC_FLAG,
+ VIO28_OC_FLAG,
+ VUSB_OC_FLAG,
+ VBT_OC_FLAG,
+ VSIM_OC_FLAG,
+ VSIM2_OC_FLAG,
+ VRTC_OC_FLAG,
+ VIBR_OC_FLAG,
+ VMC_OC_FLAG,
+ VCORE_OC_FLAG,
+ VIO18_OC_FLAG,
+ SPK_OC_FLAG,
+ VRF_OC_STATUS,
+ VTCXO_OC_STATUS,
+ VA_OC_STATUS,
+ VCAMA_OC_STATUS,
+ VCAMD_OC_STATUS,
+ VIO28_OC_STATUS,
+ VUSB_OC_STATUS,
+ VBT_OC_STATUS,
+ VSIM_OC_STATUS,
+ VSIM2_OC_STATUS,
+ VRTC_OC_STATUS,
+ VIBR_OC_STATUS,
+ VMC_OC_STATUS,
+ VCORE_OC_STATUS,
+ VIO18_OC_STATUS,
+ SPK_OC_STATUS,
+ PMU_FLAGS_MAX
+}PMU_FLAGS_LIST_ENUM;
+
+#define LDO_GROUP (OFFSEL(BUCK_GROUP))
+#if defined(MT6256_S00)
+#define BUCK_GROUP (M(VCORE)|M(VIO18))
+#else
+#define BUCK_GROUP (M(VCORE))
+#endif // End of #if defined(MT6256_S00)
+
+#endif //#if defined(PMIC_6256_REG_API)
+
+#endif //#ifndef __DCL_PMU6256_SW_H_STRUCT__
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6276_hw.h b/mcu/driver/peripheral/inc/dcl_pmu6276_hw.h
new file mode 100644
index 0000000..7386124
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6276_hw.h
@@ -0,0 +1,58 @@
+
+
+#ifndef __DCL_PMU6276_HW_H_STRUCT__
+#define __DCL_PMU6276_HW_H_STRUCT__
+
+#if defined(PMIC_6276_REG_API)
+
+
+#define PMU_BASE MIX_PMU_base
+#define PMU_END (PMU_BASE+0x1000)
+
+///////////////////////////////////////////////////////////////////////////////
+// LDO group
+#define VA12_CON0 (PMU_BASE+0x0620)
+#define VRTC_CON0 (PMU_BASE+0x0628)
+#define VMIC_CON0 (PMU_BASE+0x0630)
+#define VAUDN_CON0 (PMU_BASE+0x0640)
+#define VAUDP_CON0 (PMU_BASE+0x0650)
+#define VRF_CON0 (PMU_BASE+0x0700)
+#define VTCXO_CON0 (PMU_BASE+0x0710)
+#define VA25_CON0 (PMU_BASE+0x0720)
+#define VCAMA_CON0 (PMU_BASE+0x0730)
+#define VCAMD_CON0 (PMU_BASE+0x0740)
+#define VIO_CON0 (PMU_BASE+0x0750)
+#define VUSB_CON0 (PMU_BASE+0x0760)
+#define VBT_CON0 (PMU_BASE+0x0770)
+#define VSIM_CON0 (PMU_BASE+0x0780)
+#define VSIM2_CON0 (PMU_BASE+0x0790)
+#define VIBR_CON0 (PMU_BASE+0x07b0)
+#define VMC_CON0 (PMU_BASE+0x07c0)
+#define VCAMA2_CON0 (PMU_BASE+0x07d0)
+#define VCAMD2_CON0 (PMU_BASE+0x07e0)
+#define VFM_CON0 (PMU_BASE+0x07f0)
+#define VM12_CON0 (PMU_BASE+0x0800)
+
+//BUCK group
+#define VCORE_CON0 (PMU_BASE+0x0900)
+#define VIO18_CON0 (PMU_BASE+0x0920)
+#define VPROC_CON0 (PMU_BASE+0x0940)
+#define VRF18_CON0 (PMU_BASE+0x0960)
+#define VPA_CON0 (PMU_BASE+0x0b00)
+
+//KPLED
+#define KPLED_CON0 (PMU_BASE+0x0c80)
+
+//CHR
+#define CHR_CON0 (PMU_BASE+0x0a00)
+
+#define PMUA_CON0 (PMU_BASE+0x0680)
+#define OC_CON0 (PMU_BASE+0x0e00)
+#define LPOSC_CON0 (PMU_BASE+0x0100)
+#define STRUP_CON0 (PMU_BASE+0x0200)
+
+
+#endif //#if defined(PMIC_6276_REG_API)
+
+#endif //#ifndef __DCL_PMU6276_HW_H_STRUCT__
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6276_sw.h b/mcu/driver/peripheral/inc/dcl_pmu6276_sw.h
new file mode 100644
index 0000000..6f59ddf
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6276_sw.h
@@ -0,0 +1,251 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6276_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMU6276
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef __DCL_PMU6276_SW_H_STRUCT__
+#define __DCL_PMU6276_SW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6276_REG_API)
+
+/* Charger external interrupt is fixed. */
+#define PMU_CHR_EINT_PIN 29
+
+
+/* adc number for measuring VBAT/VISENSE/VCHARGER is fixed internally. */
+
+#define PMU_ADC_VBAT_CH_NUM 0
+#define PMU_ADC_VISENSE_CH_NUM 1
+#define PMU_ADC_VCHARGER_CH_NUM 2
+
+
+/* adc factor for VBAT/VISENSE/VCHARGER */
+#define PMU_ADC_FACTOR_VBAT 100
+#define PMU_ADC_FACTOR_VISENSE 100
+#if defined(MT6276_S00)
+#define PMU_ADC_FACTOR_VCHARGER 344 // (351/51 * 50)
+#endif //#if defined(MT6276_S00)
+#if defined(MT6276_S01)
+#define PMU_ADC_FACTOR_VCHARGER 473 // (369/39 * 50)
+#endif //#if defined(MT6276_S01)
+
+typedef enum
+{
+ PMU_VA12,
+ PMU_VRTC,
+ PMU_VMIC,
+ PMU_VAUDN,
+ PMU_VAUDP,
+ PMU_VRF28,
+ PMU_VTCXO,
+ PMU_VA25,
+ PMU_VCAMA,
+ PMU_VCAMD,
+ PMU_VIO28,
+ PMU_VUSB,
+ PMU_VBT,
+ PMU_VSIM,
+ PMU_VSIM2,
+ PMU_VIBR,
+ PMU_VMC,
+ PMU_VCAMA2,
+ PMU_VCAMD2,
+ PMU_VFM,
+ PMU_VM12,
+ PMU_VCORE,
+ PMU_VIO18,
+ PMU_VPROC,
+ PMU_VRF18,
+ PMU_LDO_BUCK_INTERNAL_MAX
+}PMU_LDO_BUCK_INTERNAL_LIST_ENUM;
+
+/*
+typedef enum
+{
+ VA12,
+ VRTC,
+ VMIC,
+ VAUDN,
+ VAUDP,
+ VRF,
+ VTCXO,
+ VA25,
+ VCAMA,
+ VCAMD,
+ VIO,
+ VUSB,
+ VBT,
+ VSIM,
+ VSIM2,
+ VIBR,
+ VMC,
+ VCAMA2,
+ VCAMD2,
+ VFM,
+ VM12,
+ VCORE,
+ VIO18,
+ VPROC,
+ VRF18,
+ PMU_LDO_BUCK_MAX
+}PMU_LDO_BUCK_LIST_ENUM;
+
+typedef enum
+{
+ VPA,
+ VPA1=VPA,
+ PMU_VPA_MAX
+}PMU_VPA_LIST_ENUM;
+
+
+typedef enum
+{
+ KPLED,
+ PMU_KPLED_MAX
+}PMU_KPLED_LIST_ENUM;
+
+typedef enum
+{
+ CHR,
+ PMU_CHR_MAX
+}PMU_CHR_LIST_ENUM;
+
+typedef enum
+{
+ PMU_ISINK_MAX
+}PMU_ISINK_LIST_ENUM;
+
+typedef enum
+{
+ PMU_BOOST_MAX
+}PMU_BOOST_LIST_ENUM;
+
+typedef enum
+{
+ PMU_SPK_MAX
+}PMU_SPK_LIST_ENUM;
+
+typedef enum
+{
+ LPOSC,
+ PMU_LPOSC_MAX
+}PMU_LPOSC_LIST_ENUM;
+
+*/
+
+#define LDO_GROUP (OFFSEL(BUCK_GROUP))
+#define BUCK_GROUP (M(VCORE)|M(VIO18)|M(VPROC)|M(VRF18))
+
+
+#if defined(__DRV_UPMU_SHARE_LDO__)
+//function ¬ÛÃö³]©w
+//multi users share the same LDO , enable multi user capability
+#define LDO_SHARE_EN_BITMAP (M(VCAMA))
+#define PMU_MULTIUSERS_HANDLE_NO 6 //vcama ctp fm
+#endif //#if defined(__DRV_UPMU_SHARE_LDO__)
+
+
+#define LDO_SET_VOLTAGE_BITMAP (M(VCAMA)|M(VCAMD)|M(VBT)|M(VSIM)|M(VSIM2)|M(VIBR)|M(VMC)|M(VCAMA2)|M(VCAMD2))
+
+
+#endif //#if defined(PMIC_6276_REG_API)
+
+#endif //#ifndef __DCL_PMU6276_SW_H_STRUCT__
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6573_hw.h b/mcu/driver/peripheral/inc/dcl_pmu6573_hw.h
new file mode 100644
index 0000000..20793f3
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6573_hw.h
@@ -0,0 +1,31 @@
+
+
+
+#ifndef __DCL_PMU6573_HW_H_STRUCT__
+#define __DCL_PMU6573_HW_H_STRUCT__
+
+#if defined(PMIC_6573_REG_API)
+
+
+#define PMU_BASE MIX_PMU_base
+#define PMU_END (PMU_BASE+0x1000)
+
+///////////////////////////////////////////////////////////////////////////////
+// LDO group
+#define VRF_CON0 (PMU_BASE+0x0700)
+#define VTCXO_CON0 (PMU_BASE+0x0710)
+#define VSIM_CON0 (PMU_BASE+0x0780)
+#define VSIM2_CON0 (PMU_BASE+0x0790)
+
+//BUCK group
+#define VRF18_CON0 (PMU_BASE+0x0960)
+#define VPA_CON0 (PMU_BASE+0x0b00)
+
+
+
+#endif //#if defined(PMIC_6573_REG_API)
+
+#endif //#ifndef __DCL_PMU6573_HW_H_STRUCT__
+
+
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu6573_sw.h b/mcu/driver/peripheral/inc/dcl_pmu6573_sw.h
new file mode 100644
index 0000000..3c5bcba
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu6573_sw.h
@@ -0,0 +1,171 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu6573_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMU 6573
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef __DCL_PMU6573_SW_H_STRUCT__
+#define __DCL_PMU6573_SW_H_STRUCT__
+
+#include "dcl_pmic_features.h"
+
+#if defined(PMIC_6573_REG_API)
+
+/* Charger external interrupt is fixed. */
+#define PMU_CHR_EINT_PIN 29
+
+
+/* adc number for measuring VBAT/VISENSE/VCHARGER is fixed internally. */
+
+#define PMU_ADC_VBAT_CH_NUM 0
+#define PMU_ADC_VISENSE_CH_NUM 1
+#define PMU_ADC_VCHARGER_CH_NUM 2
+
+
+/* adc factor for VBAT/VISENSE/VCHARGER */
+#define PMU_ADC_FACTOR_VBAT 100
+#define PMU_ADC_FACTOR_VISENSE 100
+#define PMU_ADC_FACTOR_VCHARGER 294 // 300/51 * 50
+
+/*
+typedef enum
+{
+ VTCXO,
+ VRF,
+ VSIM,
+ VSIM2,
+ VRF18,
+ PMU_LDO_BUCK_MAX,
+ CHR,
+ VMC,
+ VFM,
+ VCAMA,
+ VCAMD,
+ VIBR
+}PMU_LDO_BUCK_LIST_ENUM;
+
+typedef enum
+{
+ VPA1,
+ PMU_VPA_MAX
+}PMU_VPA_LIST_ENUM;
+
+
+typedef enum
+{
+ PMU_KPLED_MAX
+}PMU_KPLED_LIST_ENUM;
+
+typedef enum
+{
+ PMU_CHR_MAX
+}PMU_CHR_LIST_ENUM;
+
+typedef enum
+{
+ PMU_ISINK_MAX
+}PMU_ISINK_LIST_ENUM;
+
+typedef enum
+{
+ PMU_BOOST_MAX
+}PMU_BOOST_LIST_ENUM;
+
+typedef enum
+{
+ PMU_SPK_MAX
+}PMU_SPK_LIST_ENUM;
+
+*/
+
+#endif //#if defined(PMIC_6573_REG_API)
+
+#endif //#ifndef __DCL_PMU6573_SW_H_STRUCT__
+
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu_common_sw.h b/mcu/driver/peripheral/inc/dcl_pmu_common_sw.h
new file mode 100644
index 0000000..6f166bf
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu_common_sw.h
@@ -0,0 +1,533 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu_common_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is for PMU common function
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifndef __DCL_PMU_COMMON_SW_H__
+#define __DCL_PMU_COMMON_SW_H__
+
+#include "dcl.h"
+
+#ifndef __DRV_DEBUG_PMU_REG_READ_WRITE__
+#define PMU_DRV_ClearBits16(addr, data) DRV_ClearBits(addr,data)
+#define PMU_DRV_SetBits16(addr, data) DRV_SetBits(addr,data)
+#define PMU_DRV_WriteReg16(addr, data) DRV_WriteReg(addr, data)
+#define PMU_DRV_ReadReg16(addr) DRV_Reg(addr)
+#define PMU_DRV_ReadReg32(addr) DRV_Reg32(addr)
+#define PMU_DRV_SetData16(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#else // #ifndef __DRV_DEBUG_PMU_REG_READ_WRITE__
+#define PMU_DRV_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
+#define PMU_DRV_SetBits16(addr, data) DRV_DBG_SetBits(addr, data)
+#define PMU_DRV_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
+#define PMU_DRV_ReadReg16(addr) DRV_DBG_Reg(addr)
+#define PMU_DRV_ReadReg32(addr) DRV_DBG_Reg32(addr)
+#define PMU_DRV_SetData16(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#endif // #ifndef __DRV_DEBUG_PMU_REG_READ_WRITE__
+
+#define PMU_SaveAndSetIRQMask() SaveAndSetIRQMask()
+#define PMU_RestoreIRQMask(n) RestoreIRQMask(n)
+
+#define M(mod) (((DCL_UINT64)1)<<mod)
+#define NM(mod) (~(((DCL_UINT64)1)<<mod))
+#define ONSEL(modlist) (modlist)
+#define OFFSEL(modlist) (~(modlist))
+
+
+#define ISLDO(mod) ((M(mod)&LDO_GROUP)>0)
+
+// module control
+#define PMU_UNSUPPORT_MOD 0x00
+
+// PARAMETER control
+#define PARAMETERVAL_UNKNOWN 0xffffffff
+#define PARAMETER_UNKNOWN 0xffff
+
+#define ALLMOD 0xff
+#define MODMASK ALLMOD
+#define CMDMASK 0xffff00
+#define ENC(cmd,mod) (((cmd<<8)+mod))
+#define GETARRNUM(array) (sizeof(array)/sizeof(array[0]))
+#define GENFUN(fun) fun,GETARRNUM(fun)
+
+#define GETLDOIDX(mod) (pmuModtoIdx[mod])
+#define GETBUCKIDX(mod) (pmuModtoIdx[mod])
+
+#define PMU_SaveAndSetIRQMask() SaveAndSetIRQMask()
+#define PMU_RestoreIRQMask(n) RestoreIRQMask(n)
+
+typedef void DCL_VOID;
+
+typedef struct
+{
+ DCL_UINT32 cmd;
+ const DCL_VOID *pVals;
+ const DCL_VOID *pRegVals;
+ DCL_UINT8 size;
+}PMU_PARAMETER_TABLE_ENTRY;
+
+typedef struct
+{
+ DCL_UINT32 modidx;
+ DCL_UINT32 addr;
+ DCL_UINT32 usageBitMap;
+}PMU_MOD_BASEADDR_ENTRY;
+
+
+typedef struct
+{
+ DCL_UINT8 flagname;
+ DCL_UINT8 offset;
+ DCL_UINT16 mask;
+ DCL_UINT8 shift;
+}PMU_FLAG_TABLE_ENTRY;
+
+
+#if defined(__DRV_UPMU_BOOST_V1__)
+typedef enum
+{
+ BOOST_TYPE_VOLTAGE_CONTROLLER = 0,
+ BOOST_TYPE_CURRENT_CONVERTER
+}upmu_boost_type_enum;
+
+typedef enum
+{
+ BOOST_PWM_MODE = 0,
+ BOOST_REGISTER_CTRL_MODE = 1
+}upmu_boost_mode_enum;
+
+typedef enum
+{
+ BOOST_OC_THD_4_DIVIDED_BY_8 = 0,
+ BOOST_OC_THD_3_DIVIDED_BY_8 = 1,
+ BOOST_OC_THD_2_DIVIDED_BY_8 = 2,
+ BOOST_OC_THD_1_DIVIDED_BY_8 = 3
+}upmu_boost_oc_thd_enum;
+
+typedef enum
+{
+ BOOST_OC_WND_8_US = 0,
+ BOOST_OC_WND_16_US = 1,
+ BOOST_OC_WND_32_US = 2,
+ BOOST_OC_WND_64_US = 3
+}upmu_boost_oc_wnd_enum;
+
+typedef enum
+{
+ BOOST_HW_SEL_ISINK = 0,
+ BOOST_HW_SEL_BOOST
+}upmu_boost_hw_sel_enum;
+
+
+#endif // #if defined(__DRV_UPMU_BOOST_V1__)
+
+
+#if defined(__DRV_UPMU_BC11_V1__)
+typedef enum
+{
+ COMP_VTH_00_325000 = 0,
+ COMP_VTH_01_200000 = 1
+}PMU_CTRL_BC11_COMP_VTH_ENUM;
+
+typedef enum
+{
+ COMP_DISABLE = 0,
+ COMP_EN_ON_DM = 1,
+ COMP_EN_ON_DP = 2
+}PMU_CTRL_BC11_COMP_EN_ENUM;
+
+typedef enum
+{
+ IPD_DISABLE = 0,
+ IPD_EN_ON_DM = 1,
+ IPD_EN_ON_DP = 2
+}PMU_CTRL_BC11_IPD_EN_ENUM;
+
+typedef enum
+{
+ VSRC_DISABLE = 0,
+ VSRC_EN_ON_DM = 1,
+ VSRC_EN_ON_DP = 2,
+ VSRC_EN_ON_DPDM = 3
+}PMU_CTRL_BC11_VSRC_EN_ENUM;
+
+
+typedef enum
+{
+ IPU_DISABLE = 0,
+ IPU_EN_ON_DM = 1,
+ IPU_EN_ON_DP = 2
+}PMU_CTRL_BC11_IPU_EN_ENUM;
+#endif //#if defined(__DRV_UPMU_BC11_V1__)
+
+
+
+DCL_UINT16 PMU_get_Parameter_Idx(DCL_CTRL_CMD cmd);
+DCL_UINT16 PMU_Parameter_to_Value(DCL_CTRL_CMD cmd,DCL_UINT32 val);
+DCL_UINT32 PMU_Value_to_Parameter(DCL_CTRL_CMD cmd,DCL_UINT32 val);
+void PMU_SetData16(DCL_UINT32 Addr,DCL_UINT16 mask,DCL_UINT16 val);
+
+#if defined(PMIC_SLIM_V3)
+DCL_STATUS pmu_set_register_value(DCL_UINT32 address,PMU_FLAGS_LIST_ENUM flagname,DCL_UINT32 val);
+DCL_UINT16 pmu_get_register_value(DCL_UINT32 address,PMU_FLAGS_LIST_ENUM flagname);
+#endif //#if defined(PMIC_SLIM_V3)
+
+#if defined(__DRV_UPMU_SHARE_LDO__)
+DCL_BOOL ldoShare_free_idx(DCL_HANDLE handle);
+DCL_UINT16 ldoShare_get_idx(DCL_HANDLE handle);
+void ldoShare_set_bitmap(DCL_UINT16 idx,DCL_HANDLE handle,PMU_LDO_BUCK_LIST_ENUM ldo,DCL_BOOL enable);
+DCL_STATUS ldoShare_set_enable(DCL_HANDLE handle,PMU_LDO_BUCK_LIST_ENUM ldo, DCL_BOOL enable);
+#endif //#if defined(__DRV_UPMU_SHARE_LDO__)
+
+
+#if defined(__DRV_UPMU_LPOSC_V1__)
+// LPOSC
+void lposc_set_enable(PMU_LPOSC_LIST_ENUM lposc,DCL_BOOL enable);
+void lposc_set_buckboost_enable(PMU_LPOSC_LIST_ENUM lposc,DCL_BOOL enable);
+void lposc_set_acali_enable(PMU_LPOSC_LIST_ENUM lposc,DCL_BOOL enable);
+void lposc_set_freq_set(PMU_LPOSC_LIST_ENUM lposc,DCL_UINT8 val);
+void lposc_set_freq(PMU_LPOSC_LIST_ENUM lposc,DCL_UINT16 val);
+void lposc_set_buck_freq(PMU_LPOSC_LIST_ENUM lposc,DCL_UINT16 val);
+// LPOSC CON2
+void lposc_set_fd_res(PMU_LPOSC_LIST_ENUM lposc,DCL_UINT8 val);
+void lposc_set_ssc_enable(PMU_LPOSC_LIST_ENUM lposc,DCL_BOOL enable);
+void lposc_set_ssc_mod_amp(PMU_LPOSC_LIST_ENUM lposc,DCL_UINT8 val);
+void lposc_set_ssc_code_dur(PMU_LPOSC_LIST_ENUM lposc,DCL_UINT8 val);
+void lposc_set_pg_enable(PMU_LPOSC_LIST_ENUM lposc,DCL_BOOL enable);
+void lposc_set_sw_mode_enable(PMU_LPOSC_LIST_ENUM lposc,DCL_BOOL enable);
+#endif //#if defined(__DRV_UPMU_LPOSC_V1__)
+
+
+#if defined(__DRV_UPMU_LDO_V1__)
+
+void initLdoBuckMapping(void);
+// LDO CON0
+DCL_STATUS ldo_set_enable(PMU_LDO_BUCK_LIST_ENUM ldo, DCL_BOOL enable);
+DCL_STATUS ldo_set_voltage(PMU_LDO_BUCK_LIST_ENUM ldo, DCL_UINT32 vol);
+void ldo_set_oc_auto_off(PMU_LDO_BUCK_LIST_ENUM ldo, DCL_BOOL auto_off);
+void ldo_set_stb_enable(PMU_LDO_BUCK_LIST_ENUM ldo, DCL_BOOL enable);
+void ldo_set_on_sel(PMU_LDO_BUCK_LIST_ENUM ldo, PMU_ON_SEL_ENUM sel);
+void ldo_set_ocfb_enable(PMU_LDO_BUCK_LIST_ENUM ldo, DCL_BOOL enable);
+void ldo_set_ndis_enable(PMU_LDO_BUCK_LIST_ENUM ldo, DCL_BOOL enable);
+//LDO CON1
+void ldo_set_voltage_calibration_code(PMU_LDO_BUCK_LIST_ENUM ldo, DCL_UINT32 val);
+void ldo_set_current_limit(PMU_LDO_BUCK_LIST_ENUM ldo, DCL_UINT32 val);
+// LDO CON2
+void ldo_set_oc_td(PMU_LDO_BUCK_LIST_ENUM ldo, DCL_UINT32 sel);
+void ldo_set_stb_td(PMU_LDO_BUCK_LIST_ENUM ldo, DCL_UINT32 sel);
+void ldo_set_ctrl_sel(PMU_LDO_BUCK_LIST_ENUM ldo, PMU_CTRL_LDO_CTRL_MODE_ENUM sel);
+void ldo_set_sim_gpio_en(PMU_LDO_BUCK_LIST_ENUM ldo, DCL_BOOL enable);
+void ldo_set_simio_drv(PMU_LDO_BUCK_LIST_ENUM ldo, DCL_UINT8 val);
+void ldo_set_bias(PMU_LDO_BUCK_LIST_ENUM ldo, DCL_UINT8 val);
+void ldo_set_srn(PMU_LDO_BUCK_LIST_ENUM ldo, DCL_UINT8 val);
+void ldo_set_srp(PMU_LDO_BUCK_LIST_ENUM ldo, DCL_UINT8 val);
+
+#endif //#if defined(__DRV_UPMU_LDO_V1__)
+
+
+
+#if defined(__DRV_UPMU_BUCK_V1__)
+// BUCK CON0
+DCL_STATUS buck_set_enable(PMU_LDO_BUCK_LIST_ENUM buck, DCL_BOOL enable);
+DCL_STATUS buck_set_voltage(PMU_LDO_BUCK_LIST_ENUM buck, DCL_UINT32 vol);
+void buck_set_on_sel(PMU_LDO_BUCK_LIST_ENUM buck, PMU_ON_SEL_ENUM sel);
+void buck_set_rs(PMU_LDO_BUCK_LIST_ENUM buck, DCL_UINT32 sel);
+void buck_set_oc_auto_off(PMU_LDO_BUCK_LIST_ENUM buck, DCL_BOOL auto_off);
+void buck_set_dis_antiunsh(PMU_LDO_BUCK_LIST_ENUM buck, DCL_BOOL off);
+//BUCK CON3
+void buck_set_ical(PMU_LDO_BUCK_LIST_ENUM buck, DCL_UINT32 val);
+void buck_set_oc_td(PMU_LDO_BUCK_LIST_ENUM buck, DCL_UINT32 val);
+void buck_set_stb_td(PMU_LDO_BUCK_LIST_ENUM buck, DCL_UINT32 val);
+//BUCK CON5
+DCL_STATUS buck_set_sleep_voltage(PMU_LDO_BUCK_LIST_ENUM buck, DCL_UINT32 vol);
+void buck_set_burst_threshold(PMU_LDO_BUCK_LIST_ENUM buck, DCL_UINT32 threshold);
+void buck_set_current_limit(PMU_LDO_BUCK_LIST_ENUM buck, DCL_UINT32 val);
+void buck_set_ocfb_enable(PMU_LDO_BUCK_LIST_ENUM buck, DCL_UINT32 val);
+void buck_set_adjcksel(PMU_LDO_BUCK_LIST_ENUM buck, DCL_UINT8 val);
+void buck_set_rzsel(PMU_LDO_BUCK_LIST_ENUM buck, DCL_UINT8 val);
+void buck_set_csr(PMU_LDO_BUCK_LIST_ENUM buck, DCL_UINT8 val);
+void buck_set_cks_prg(PMU_LDO_BUCK_LIST_ENUM buck, DCL_UINT8 val);
+void buck_set_gmsel(PMU_LDO_BUCK_LIST_ENUM buck, DCL_UINT8 val);
+void buck_set_zx_pdn(PMU_LDO_BUCK_LIST_ENUM buck, DCL_UINT8 val);
+#endif //#if defined(__DRV_UPMU_BUCK__)
+
+#if defined(__DRV_UPMU_VPA_V1__)
+void vpa_set_enable(PMU_VPA_LIST_ENUM vpa,DCL_BOOL enable);
+void vpa_set_antiring_enable(PMU_VPA_LIST_ENUM vpa,DCL_BOOL enable);
+void vpa_set_rc(PMU_VPA_LIST_ENUM vpa,DCL_BOOL val);
+//VPA CON2
+void vpa_set_votune0(PMU_VPA_LIST_ENUM vpa, DCL_UINT32 voltage);
+void vpa_set_votune1(PMU_VPA_LIST_ENUM vpa, DCL_UINT32 voltage);
+//VPA CON3
+void vpa_set_votune2(PMU_VPA_LIST_ENUM vpa, DCL_UINT32 voltage);
+void vpa_set_votune3(PMU_VPA_LIST_ENUM vpa, DCL_UINT32 voltage);
+//VPA CON4
+void vpa_set_votune4(PMU_VPA_LIST_ENUM vpa, DCL_UINT32 voltage);
+void vpa_set_votune5(PMU_VPA_LIST_ENUM vpa, DCL_UINT32 voltage);
+//VPA CON5
+void vpa_set_votune6(PMU_VPA_LIST_ENUM vpa, DCL_UINT32 voltage);
+void vpa_set_votune7(PMU_VPA_LIST_ENUM vpa, DCL_UINT32 voltage);
+DCL_STATUS vpa_set_votune(PMU_VPA_LIST_ENUM vpa, DCL_UINT32 idx,DCL_UINT32 val);
+#endif //#if defined(__DRV_UPMU_VPA_V1__)
+
+#if defined(__DRV_UPMU_KPLED_V1__)
+// KPLED CON0
+void kpled_set_enable(PMU_KPLED_LIST_ENUM kpled, DCL_BOOL enable);
+void kpled_set_mode(PMU_KPLED_LIST_ENUM kpled, PMU_CTRL_KPLED_MODE_ENUM val);
+void kpled_set_sel(PMU_KPLED_LIST_ENUM kpled, DCL_UINT8 val);
+DCL_BOOL kpled_get_status(PMU_KPLED_LIST_ENUM kpled);
+#endif // #if defined(__DRV_UPMU_KPLED_V1__)
+
+
+#if defined(__DRV_UPMU_CHARGER_V1__)
+// CHR_CON0
+void chr_set_csdac_enable(PMU_CHR_LIST_ENUM chr, DCL_BOOL enable);
+DCL_BOOL chr_get_is_chr_det(PMU_CHR_LIST_ENUM chr);
+void chr_wdt_clear_internal(PMU_CHR_LIST_ENUM chr);
+void chr_set_enable(PMU_CHR_LIST_ENUM chr, DCL_BOOL enable);
+// CHR_CON1
+DCL_BOOL chr_get_is_vbat_cv_det(PMU_CHR_LIST_ENUM chr);
+DCL_STATUS chr_set_vbat_cv_vth(PMU_CHR_LIST_ENUM chr, DCL_UINT32 voltage);
+DCL_STATUS chr_set_vbat_cv_vth_value(PMU_CHR_LIST_ENUM chr, DCL_UINT16 val);
+void chr_set_vbat_cv_det_enable(PMU_CHR_LIST_ENUM chr, DCL_BOOL enable);
+// CHR_CON2
+DCL_UINT32 chr_get_cs_vth(PMU_CHR_LIST_ENUM chr);
+DCL_STATUS chr_set_cs_vth(PMU_CHR_LIST_ENUM chr, DCL_UINT32 current);
+// CHR_CON3
+void chr_set_csdac_stp(PMU_CHR_LIST_ENUM chr, DCL_UINT16 val);
+void chr_set_csdac_dly(PMU_CHR_LIST_ENUM chr, DCL_UINT16 val);
+DCL_BOOL chr_get_is_bat_on(PMU_CHR_LIST_ENUM chr);
+// CHR_CON6
+void chr_wdt_clear_internal(PMU_CHR_LIST_ENUM chr);
+void chr_set_wdt_td(PMU_CHR_LIST_ENUM chr,DCL_UINT32 sec);
+void chr_set_wdt_clear(PMU_CHR_LIST_ENUM chr);
+void chr_set_wdt_enable(PMU_CHR_LIST_ENUM chr, DCL_UINT8 enable);
+// CHR_CON7
+void chr_set_wdt_int_enable(PMU_CHR_LIST_ENUM chr, DCL_UINT8 enable);
+// CHR_CON8
+void chr_set_adc_measure_enable(PMU_CHR_LIST_ENUM chr, DCL_BOOL enable);
+
+DCL_STATUS chr_set_vbat_hv_vth(PMU_CHR_LIST_ENUM chr, DCL_UINT32 voltage);
+DCL_STATUS chr_set_vbat_ov_vth(PMU_CHR_LIST_ENUM chr, DCL_UINT32 voltage);
+void chr_set_baton_ht_en(PMU_CHR_LIST_ENUM chr, DCL_UINT16 enable);
+void chr_set_otg_bvalid_en(PMU_CHR_LIST_ENUM chr, DCL_UINT16 enable);
+
+#if defined(__DRV_UPMU_BC11_V1__)
+void chr_bc11_comp_vth(PMU_CHR_LIST_ENUM chr,PMU_CTRL_BC11_COMP_VTH_ENUM sel);
+void chr_bc11_comp_en_ctrl(PMU_CHR_LIST_ENUM chr,PMU_CTRL_BC11_COMP_EN_ENUM sel);
+void chr_bc11_ipd_en_ctrl(PMU_CHR_LIST_ENUM chr,PMU_CTRL_BC11_IPD_EN_ENUM sel);
+void chr_bc11_ipu_en_ctrl(PMU_CHR_LIST_ENUM chr,PMU_CTRL_BC11_IPU_EN_ENUM sel);
+void chr_bc11_bias_enable(PMU_CHR_LIST_ENUM chr, DCL_BOOL enable);
+void chr_bc11_bb_ctrl(PMU_CHR_LIST_ENUM chr);
+void chr_bc11_reset(PMU_CHR_LIST_ENUM chr);
+void chr_bc11_vsrc_en_ctrl(PMU_CHR_LIST_ENUM chr,PMU_CTRL_BC11_VSRC_EN_ENUM sel);
+DCL_BOOL chr_bc11_get_cmp_out(PMU_CHR_LIST_ENUM chr);
+#endif // #if defined(__DRV_UPMU_BC11_V1__)
+#endif //#if defined(__DRV_UPMU_CHARGER_V1__)
+
+#if defined(__DRV_UPMU_STRUP_V1__)
+void strup_usbdl_mode_enable(PMU_STRUP_LIST_ENUM strup,DCL_BOOL enable);
+#endif // #if defined(__DRV_UPMU_STRUP_V1__)
+
+
+#if defined(__DRV_UPMU_BOOST_V1__)
+// BOOST CON0
+void boost_set_enable(PMU_BOOST_LIST_ENUM boost, DCL_BOOL enable);
+void boost_set_type(PMU_BOOST_LIST_ENUM boost, upmu_boost_type_enum val);
+void boost_set_mode(PMU_BOOST_LIST_ENUM boost, upmu_boost_mode_enum val);
+void boost_set_vrsel(PMU_BOOST_LIST_ENUM boost, DCL_UINT8 val);
+void boost_set_oc_auto_off(PMU_BOOST_LIST_ENUM boost, DCL_BOOL auto_off);
+DCL_BOOL boost_get_oc_status(PMU_BOOST_LIST_ENUM boost);
+// BOOST CON1
+void boost_set_cl(PMU_BOOST_LIST_ENUM boost, DCL_UINT8 val);
+void boost_set_cs(PMU_BOOST_LIST_ENUM boost, DCL_UINT8 val);
+void boost_set_rc(PMU_BOOST_LIST_ENUM boost, DCL_UINT8 val);
+void boost_set_ss(PMU_BOOST_LIST_ENUM boost, DCL_UINT8 val);
+// BOOST CON2
+void boost_set_cksel(PMU_BOOST_LIST_ENUM boost, DCL_UINT8 val);
+void boost_set_sr_pmos(PMU_BOOST_LIST_ENUM boost, DCL_UINT8 val);
+void boost_set_sr_nmos(PMU_BOOST_LIST_ENUM boost, DCL_UINT8 val);
+void boost_set_slp(PMU_BOOST_LIST_ENUM boost, DCL_UINT8 val);
+// BOOST CON3
+void boost_set_cks_prg(PMU_BOOST_LIST_ENUM boost, DCL_UINT8 val);
+// BOOST CON4
+void boost_set_oc_thd(PMU_BOOST_LIST_ENUM boost, upmu_boost_oc_thd_enum val);
+void boost_set_oc_wnd(PMU_BOOST_LIST_ENUM boost, upmu_boost_oc_wnd_enum val);
+void boost_set_clk_cal(PMU_BOOST_LIST_ENUM boost, DCL_UINT8 val);
+// BOOST CON6
+void boost_set_hw_sel(PMU_BOOST_LIST_ENUM boost, upmu_boost_hw_sel_enum val);
+void boost_set_cc(PMU_BOOST_LIST_ENUM boost, DCL_UINT8 val);
+#endif //#if defined(__DRV_UPMU_BOOST_V1__)
+
+#if defined(__DRV_UPMU_ISINK_V1__)
+// ISINK CON0
+void isink_set_enable(PMU_ISINK_LIST_ENUM isink, DCL_BOOL enable);
+void isinks_set_vref_cal(PMU_ISINK_LIST_ENUM isink, kal_uint8 val);
+void isink_set_mode(PMU_ISINK_LIST_ENUM isink, PMU_CTRL_ISINK_MODE_ENUM val);
+void isink_set_step(PMU_ISINK_LIST_ENUM isink, DCL_UINT8 val);
+#endif //#if defined(__DRV_UPMU_ISINK_V1__)
+
+#if defined(__DRV_UPMU_SPK_V1__)
+// SPK CON0
+void spk_set_enable(PMU_SPK_LIST_ENUM spk, DCL_BOOL enable);
+void spk_set_reset(PMU_SPK_LIST_ENUM spk, DCL_BOOL reset);
+DCL_STATUS spk_set_vol(PMU_SPK_LIST_ENUM spk, PMU_SPK_VOL_ENUM vol);
+void spk_set_oc_auto_off(PMU_SPK_LIST_ENUM spk, DCL_BOOL auto_off);
+void spk_set_ocfb_enable(PMU_SPK_LIST_ENUM spk, DCL_BOOL enable);
+DCL_BOOL spk_set_get_oc_status(PMU_SPK_LIST_ENUM spk);
+// SPK CON1
+void spk_set_pfd_mode_enable(PMU_SPK_LIST_ENUM spk, DCL_BOOL enable);
+void spk_set_cmode(PMU_SPK_LIST_ENUM spk, DCL_UINT8 val);
+void spk_set_ccode(PMU_SPK_LIST_ENUM spk, DCL_UINT8 val);
+// SPK CON2
+void spk_set_oc_thd(PMU_SPK_LIST_ENUM spk, DCL_UINT8 val);
+void spk_set_oc_wnd(PMU_SPK_LIST_ENUM spk, DCL_UINT8 val);
+// SPK CON3
+void spk_set_osc_isel(PMU_SPK_LIST_ENUM spk, DCL_UINT8 val);
+void spk_set_oc_enable(PMU_SPK_LIST_ENUM spk, DCL_BOOL enable);
+// SPK CON4
+void spk_set_ocn_bias(PMU_SPK_LIST_ENUM spk, DCL_UINT8 val);
+void spk_set_ocp_bias(PMU_SPK_LIST_ENUM spk, DCL_UINT8 val);
+// SPK CON5
+void spk_set_pg_slew_dly(PMU_SPK_LIST_ENUM spk,DCL_UINT8 val);
+void spk_set_pg_slew_l(PMU_SPK_LIST_ENUM spk,DCL_UINT8 val);
+// SPK CON7
+void spk_set_mode(PMU_SPK_LIST_ENUM spk, PMU_CTRL_SPK_MODE_ENUM val);
+void spk_set_ab_obias(PMU_SPK_LIST_ENUM spk, DCL_UINT8 val);
+void spk_set_ab_oc_enable(PMU_SPK_LIST_ENUM spk, DCL_BOOL enable);
+#endif // #if defined(__DRV_UPMU_SPK_V1__)
+
+#if defined(__DRV_UPMU_SPK_V2__)
+// SPK CON0
+void spk_set_enable(PMU_SPK_LIST_ENUM spk, kal_bool enable);
+DCL_STATUS spk_set_vol(PMU_SPK_LIST_ENUM spk, PMU_SPK_VOL_ENUM vol);
+void spk_set_oc_enable(PMU_SPK_LIST_ENUM spk, kal_bool enable);
+void spk_set_obias(PMU_SPK_LIST_ENUM spk, kal_uint8 val);
+void spk_set_oc_thd(PMU_SPK_LIST_ENUM spk, kal_uint8 val);
+void spk_set_oc_wnd(PMU_SPK_LIST_ENUM spk, kal_uint8 val);
+#endif // #if defined(__DRV_UPMU_SPK_V2__)
+#endif //#define __DCL_PMU_COMMON_SW_H__
+
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu_hw.h b/mcu/driver/peripheral/inc/dcl_pmu_hw.h
new file mode 100644
index 0000000..f49e24a
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu_hw.h
@@ -0,0 +1,919 @@
+
+
+#ifndef __DCL_PMU_COMMON_HW_STRUCT__
+#define __DCL_PMU_COMMON_HW_STRUCT__
+
+#define CON0_OFFSET 0x00
+#define CON1_OFFSET 0x04
+#define CON2_OFFSET 0x08
+#define CON3_OFFSET 0x0C
+#define CON4_OFFSET 0x10
+#define CON5_OFFSET 0x14
+#define CON6_OFFSET 0x18
+#define CON7_OFFSET 0x1C
+#define CON8_OFFSET 0x20
+#define CON9_OFFSET 0x24
+
+#if defined(__DRV_UPMU_VPA_V1__)
+
+//VPA CON0
+#define VPA_EN_OFFSET CON0_OFFSET
+#define VPA_EN_MASK 0x1000
+#define VPA_EN_SHIFT 12
+
+#define VPA_ANTI_RING_OFFSET CON0_OFFSET
+#define VPA_ANTI_RING_MASK 0x0800
+#define VPA_ANTI_RING_SHIFT 11
+
+#define VPA_RC_OFFSET CON0_OFFSET
+#define VPA_RC_MASK 0x000c
+#define VPA_RC_SHIFT 2
+
+
+//VPA CON2
+#define VPA_VOTUNE0_OFFSET CON2_OFFSET
+#define VPA_VOTUNE0_MASK 0x001F
+#define VPA_VOTUNE0_SHIFT 0
+
+#define VPA_VOTUNE1_OFFSET CON2_OFFSET
+#define VPA_VOTUNE1_MASK 0x1F00
+#define VPA_VOTUNE1_SHIFT 8
+
+//VPA CON3
+#define VPA_VOTUNE2_OFFSET CON3_OFFSET
+#define VPA_VOTUNE2_MASK 0x001F
+#define VPA_VOTUNE2_SHIFT 0
+
+#define VPA_VOTUNE3_OFFSET CON3_OFFSET
+#define VPA_VOTUNE3_MASK 0x1F00
+#define VPA_VOTUNE3_SHIFT 8
+
+//VPA CON4
+#define VPA_VOTUNE4_OFFSET CON4_OFFSET
+#define VPA_VOTUNE4_MASK 0x001F
+#define VPA_VOTUNE4_SHIFT 0
+
+#define VPA_VOTUNE5_OFFSET CON4_OFFSET
+#define VPA_VOTUNE5_MASK 0x1F00
+#define VPA_VOTUNE5_SHIFT 8
+
+//VPA CON5
+#define VPA_VOTUNE6_OFFSET CON5_OFFSET
+#define VPA_VOTUNE6_MASK 0x001F
+#define VPA_VOTUNE6_SHIFT 0
+
+#define VPA_VOTUNE7_OFFSET CON5_OFFSET
+#define VPA_VOTUNE7_MASK 0x1F00
+#define VPA_VOTUNE7_SHIFT 8
+
+#endif //#if defined(__DRV_UPMU_VPA_V1__)
+
+#if defined(__DRV_UPMU_LPOSC_V1__)
+#define LPOSC_CON0_OFFSET 0x00
+#define LPOSC_CON1_OFFSET 0x04
+#define LPOSC_CON2_OFFSET 0x08
+#define LPOSC_CON3_OFFSET 0x0C
+#define LPOSC_CON4_OFFSET 0x10
+
+// LPOSC CON0
+#define LPOSC_EN_MASK 0x1000
+#define LPOSC_EN_SHIFT 12
+
+//LPOSC CON1
+#define LPOSC_FREQ_SET_MASK 0x00ff
+#define LPOSC_FREQ_SET_SHIFT 0
+
+#define LPOSC_BUCK_FREQ_SET_MASK 0x0700
+#define LPOSC_BUCK_FREQ_SET_SHIFT 8
+
+#define LPOSC_ACALI_EN_MASK 0x4000
+#define LPOSC_ACALI_EN_SHIFT 14
+
+#define LPOSC_FREQ_SET_MASK 0x00ff
+#define LPOSC_FREQ_SET_SHIFT 0
+
+// LPOSC CON2
+#define LPOSC_FD_RES_MASK 0x0007
+#define LPOSC_FD_RES_SHIFT 0
+
+#define LPOSC_SSC_EN_MASK 0x0008
+#define LPOSC_SSC_EN_SHIFT 3
+
+#define LPOSC_SSC_MOD_AMP_MASK 0x0700
+#define LPOSC_SSC_MOD_AMP_SHIFT 8
+
+#define LPOSC_RG_BUCK_BOOST_EN_MASK 0x0800
+#define LPOSC_RG_BUCK_BOOST_EN_SHIFT 11
+
+#define LPOSC_SSC_CODE_DUR_MASK 0x7000
+#define LPOSC_SSC_CODE_DUR_SHIFT 12
+
+#define LPOSC_LPOSC_PG_EN_MASK 0x8000
+#define LPOSC_LPOSC_PG_EN_SHIFT 15
+
+//LPOSC CON4
+#define LPOSC_SW_MODE_EN_MASK 0x1000
+#define LPOSC_SW_MODE_EN_SHIFT 12
+
+#endif //#if defined(__DRV_UPMU_BUCK_V1__)
+
+#if defined(__DRV_UPMU_LDO_V1__)
+#define LDO_CON0_OFFSET 0x00
+#define LDO_CON1_OFFSET 0x04
+#define LDO_CON2_OFFSET 0x08
+#define LDO_CON3_OFFSET 0x0C
+// LDO H/W register bitmap definition
+ // LDO_XXX CON0
+ #define LDO_EN_OFFSET CON0_OFFSET
+#define LDO_EN_MASK 0x0001
+#define LDO_EN_SHIFT 0
+
+#define LDO_ON_SEL_OFFSET CON0_OFFSET
+#define LDO_ON_SEL_MASK 0x0002
+#define LDO_ON_SEL_SHIFT 1
+
+#define LDO_RS_MASK 0x0004
+#define LDO_RS_SHIFT 2
+
+#define LDO_VOL_SEL_OFFSET CON0_OFFSET
+#define LDO_VOL_SEL_MASK 0x01F0
+#define LDO_VOL_SEL_SHIFT 4
+
+#define LDO_NDIS_EN_OFFSET CON0_OFFSET
+#define LDO_NDIS_EN_MASK 0x0400
+#define LDO_NDIS_EN_SHIFT 10
+
+#define LDO_STB_EN_OFFSET CON0_OFFSET
+#define LDO_STB_EN_MASK 0x0800
+#define LDO_STB_EN_SHIFT 11
+
+#define LDO_OC_AUTO_OFF_OFFSET CON0_OFFSET
+#define LDO_OC_AUTO_OFF_MASK 0x1000
+#define LDO_OC_AUTO_OFF_SHIFT 12
+
+#define LDO_OCFB_EN_OFFSET CON0_OFFSET
+#define LDO_OCFB_EN_MASK 0x2000
+#define LDO_OCFB_EN_SHIFT 13
+
+#define LDO_OC_STATUS_MASK 0x4000
+#define LDO_OC_STATUS_SHIFT 14
+
+#define LDO_STATUS_MASK 0x8000
+#define LDO_STATUS_SHIFT 15
+
+ // LDO_XXX CON1
+#if defined(__DRV_UPMU_LDO_V1_STB_TD_AT_CON1_BIT0__)
+#define LDO_STB_TD_OFFSET CON1_OFFSET
+#define LDO_STB_TD_MASK 0x0003
+#define LDO_STB_TD_SHIFT 0
+#else
+#define LDO_STB_TD_OFFSET CON2_OFFSET
+#define LDO_STB_TD_MASK 0x00c0
+#define LDO_STB_TD_SHIFT 6
+#endif // #if defined(__DRV_UPMU_LDO_V1_STB_TD_AT_CON1_BIT0__)
+
+#define LDO_FORCE_LOW_MASK 0x0004
+#define LDO_FORCE_LOW_SHIFT 2
+
+#define LDO_CAL_OFFSET CON1_OFFSET
+#define LDO_CAL_MASK 0x01F0
+#define LDO_CAL_SHIFT 4
+#if defined(__DRV_UPMU_LDO_CAL_AS_SLEEP_VOLTAGE__)
+#define LDO_VOL_SEL_SLEEP_MASK 0x01F0
+#define LDO_VOL_SEL_SLEEP_SHIFT 4
+#endif // #if defined(__DRV_UPMU_LDO_CAL_AS_SLEEP_VOLTAGE__)
+
+ // LDO_XXX CON2
+#define LDO_GP_LDOEN_MASK 0x0002
+#define LDO_GP_LDOEN_SHIFT 1
+
+#define LDO_OC_TD_OFFSET CON2_OFFSET
+#define LDO_OC_TD_MASK 0x0030
+#define LDO_OC_TD_SHIFT 4
+/*
+#if defined(__DRV_UPMU_LDO_V1_STB_TD_AT_CON2_BIT6__)
+#define LDO_STB_TD_OFFSET CON2_OFFSET
+#define LDO_STB_TD_MASK 0x00C0
+#define LDO_STB_TD_SHIFT 6
+#endif // #if defined(__DRV_UPMU_LDO_V1_STB_TD_AT_CON2_BIT6__)
+*/
+
+#define LDO_ICAL_EN_MASK 0x3000
+#define LDO_ICAL_EN_SHIFT 12
+
+ // LDO_XXX CON3
+ // Only for VSIM/VSIM2 LDO
+#define SIMIO_DRV_MASK 0x000E
+#define SIMIO_DRV_SHIFT 1
+#define SIM_BIAS_MASK 0x0030
+#define SIM_BIAS_SHIFT 4
+#define SIM_SRN_MASK 0x00C0
+#define SIM_SRN_SHIFT 6
+#define SIM_SRP_MASK 0x0300
+#define SIM_SRP_SHIFT 8
+#define SIM_CSTOP_MASK 0x0400 // Only for 6256 E2
+#define SIM_CSTOP_SHIFT 10 // Only for 6256 E2
+
+//////////////////// SIM control
+#if defined(__DRV_UPMU_LDO_SIM_SPECIFIC_CONFIG_FIELD_AT_CON2__)
+#define LDO_SIM_GPIO_EN_OFFSET CON2_OFFSET
+#define LDO_SIM_SIMIO_DRV_OFFSET CON2_OFFSET
+#define LDO_SIM_BIAS_OFFSET CON2_OFFSET
+#define LDO_SIM_SRN_OFFSET CON2_OFFSET
+#define LDO_SIM_SRP_OFFSET CON2_OFFSET
+#else
+#define LDO_SIM_GPIO_EN_OFFSET CON3_OFFSET
+#define LDO_SIM_SIMIO_DRV_OFFSET CON3_OFFSET
+#define LDO_SIM_BIAS_OFFSET CON3_OFFSET
+#define LDO_SIM_SRN_OFFSET CON3_OFFSET
+#define LDO_SIM_SRP_OFFSET CON3_OFFSET
+#define LDO_SIM_CSTOP_OFFSET CON3_OFFSET // Only for 6256 E2
+#endif //#if defined(__DRV_UPMU_LDO_SIM_SPECIFIC_CONFIG_FIELD_AT_CON2__)
+#define LDO_SIM_GPIO_EN_MASK 0x0001
+#define LDO_SIM_GPIO_EN_SHIFT 0
+
+#define LDO_SIM_SIMIO_DRV_MASK 0x000E
+#define LDO_SIM_SIMIO_DRV_SHIFT 1
+
+#define LDO_SIM_BIAS_MASK 0x0030
+#define LDO_SIM_BIAS_SHIFT 4
+
+#define LDO_SIM_SRN_MASK 0x00C0
+#define LDO_SIM_SRN_SHIFT 6
+
+#define LDO_SIM_SRP_MASK 0x0300
+#define LDO_SIM_SRP_SHIFT 8
+
+#define LDO_SIM_CSTOP_MASK 0x0400 // Only for 6256 E2
+#define LDO_SIM_CSTOP_SHIFT 10 // Only for 6256 E2
+///////////////////// SIM control end
+
+
+#endif // #if defined(__DRV_UPMU_LDO_V1__)
+
+#if defined(__DRV_UPMU_BUCK_V1__)
+#define BUCK_CON0_OFFSET 0x00
+#define BUCK_CON1_OFFSET 0x04
+#define BUCK_CON2_OFFSET 0x08
+#define BUCK_CON3_OFFSET 0x0C
+#define BUCK_CON4_OFFSET 0x10
+#define BUCK_CON5_OFFSET 0x14
+#define BUCK_CON6_OFFSET 0x18
+// BUCK H/W register bitmap definition
+ // BUCK_XXX CON0
+#define BUCK_EN_OFFSET CON0_OFFSET
+#define BUCK_EN_MASK 0x0001
+#define BUCK_EN_SHIFT 0
+
+#define BUCK_ON_SEL_OFFSET CON0_OFFSET
+#define BUCK_ON_SEL_MASK 0x0002
+#define BUCK_ON_SEL_SHIFT 1
+
+#define BUCK_RS_OFFSET CON0_OFFSET
+#define BUCK_RS_MASK 0x0004
+#define BUCK_RS_SHIFT 2
+
+#define BUCK_ST_STR_MASK 0x0008
+#define BUCK_ST_STR_SHIFT 3
+
+#define BUCK_VFBADJ_OFFSET CON0_OFFSET
+#define BUCK_VFBADJ_MASK 0x01F0
+#define BUCK_VFBADJ_SHIFT 4
+
+#define BUCK_DIS_ANTIUNSH_MASK 0x0400
+#define BUCK_DIS_ANTIUNSH_SHIFT 10
+
+#define BUCK_STB_EN_MASK 0x0800
+#define BUCK_STB_EN_SHIFT 11
+
+#define BUCK_OC_AUTO_OFF_MASK 0x1000
+#define BUCK_OC_AUTO_OFF_SHIFT 12
+
+#define BUCK_OCFB_EN_OFFSET CON0_OFFSET
+#define BUCK_OCFB_EN_MASK 0x2000
+#define BUCK_OCFB_EN_SHIFT 13
+
+ // BUCK_XXX CON1
+#define BUCK_MODESET_MASK 0x0001
+#define BUCK_MODESET_SHIFT 0
+
+#define BUCK_VFBADJ_SLEEP_OFFSET CON1_OFFSET
+#define BUCK_VFBADJ_SLEEP_MASK 0x01F0
+#define BUCK_VFBADJ_SLEEP_SHIFT 4
+
+#define BUCK_CLK_SRC_MASK 0x0400
+#define BUCK_CLK_SRC_SHIFT 10
+
+ // BUCK_XXX CON2
+#define BUCK_CAL_MASK 0x01F0
+#define BUCK_CAL_SHIFT 4
+
+ // BUCK_XXX CON3
+#define BUCK_OC_TD_OFFSET CON3_OFFSET
+#define BUCK_OC_TD_MASK 0x0030
+#define BUCK_OC_TD_SHIFT 4
+
+#define BUCK_STB_TD_OFFSET CON3_OFFSET
+#define BUCK_STB_TD_MASK 0x00C0
+#define BUCK_STB_TD_SHIFT 6
+
+#define BUCK_OC_THD_MASK 0x0300
+#define BUCK_OC_THD_SHIFT 8
+
+#define BUCK_OC_WND_MASK 0x0C00
+#define BUCK_OC_WND_SHIFT 10
+
+#define BUCK_ICAL_EN_OFFSET CON3_OFFSET
+#define BUCK_ICAL_EN_MASK 0x3000
+#define BUCK_ICAL_EN_SHIFT 12
+
+ // BUCK XXX CON4
+#define BUCK_ADJCKSEL_OFFSET CON4_OFFSET
+#define BUCK_ADJCKSEL_MASK 0x0070
+#define BULK_ADJCKSEL_SHIFT 4
+
+ // BUCK XXX CON5
+#define BUCK_CSR_OFFSET CON5_OFFSET
+#define BUCK_CSR_MASK 0x000F
+#define BULK_CSR_SHIFT 0
+
+#define BUCK_RZSEL_OFFSET CON5_OFFSET
+#define BUCK_RZSEL_MASK 0x0070
+#define BULK_RZSEL_SHIFT 4
+
+#define BUCK_CSL_OFFSET CON5_OFFSET
+#define BUCK_CSL_MASK 0x0700
+#define BUCK_CSL_SHIFT 8
+
+#define BUCK_BURST_OFFSET CON5_OFFSET
+#define BUCK_BURST_MASK 0x3000
+#define BUCK_BURST_SHIFT 12
+
+#define BUCK_GMSEL_OFFSET CON5_OFFSET
+#define BUCK_GMSEL_MASK 0x4000
+#define BUCK_GMSEL_SHIFT 14
+
+#define BUCK_ZX_PDN_OFFSET CON5_OFFSET
+#define BUCK_ZX_PDN_MASK 0x8000
+#define BUCK_ZX_PDN_SHIFT 15
+
+ // BUCK XXX CON6
+#define BUCK_CKS_PRG_OFFSET CON6_OFFSET
+#define BUCK_CKS_PRG_MASK 0x001f
+#define BUCK_CKS_PRG_SHIFT 0
+
+
+#endif // #if defined(__DRV_UPMU_BUCK_V1__)
+
+#if defined(__DRV_UPMU_BOOST_V1__)
+#define BOOST_CON0_OFFSET 0x00
+#define BOOST_CON1_OFFSET 0x04
+#define BOOST_CON2_OFFSET 0x08
+#define BOOST_CON3_OFFSET 0x0C
+#define BOOST_CON4_OFFSET 0x10
+#define BOOST_CON5_OFFSET 0x14
+#define BOOST_CON6_OFFSET 0x18
+// BOOST H/W register bitmap definition
+ // BOOST_XXX CON0
+#define BOOST_EN_OFFSET CON0_OFFSET
+#define BOOST_EN_MASK 0x0001
+#define BOOST_EN_SHIFT 0
+
+#define BOOST_TYPE_MASK 0x0002
+#define BOOST_TYPE_SHIFT 1
+
+#define BOOST_MODE_MASK 0x0004
+#define BOOST_MODE_SHIFT 2
+
+#define BOOST_VRSEL_MASK 0x01F0
+#define BOOST_VRSEL_SHIFT 4
+
+#define BOOST_OC_AUTO_OFF_MASK 0x1000
+#define BOOST_OC_AUTO_OFF_SHIFT 12
+
+#define BOOST_OC_FLAG_MASK 0x4000
+#define BOOST_OC_FLAG_SHIFT 14
+
+ // BOOST_XXX CON1
+#define BOOST_CL_OFFSET CON1_OFFSET
+#define BOOST_CL_MASK 0x0007
+#define BOOST_CL_SHIFT 0
+
+#define BOOST_CS_MASK 0x0070
+#define BOOST_CS_SHIFT 4
+
+#define BOOST_RC_MASK 0x0700
+#define BOOST_RC_SHIFT 8
+
+#define BOOST_SS_MASK 0x7000
+#define BOOST_SS_SHIFT 12
+
+ // BOOST_XXX CON2
+#define BOOST_CKSEL_MASK 0x0002
+#define BOOST_CKSEL_SHIFT 1
+
+#define BOOST_SR_PMOS_MASK 0x0070
+#define BOOST_SR_PMOS_SHIFT 4
+
+#define BOOST_SR_NMOS_MASK 0x0700
+#define BOOST_SR_NMOS_SHIFT 8
+
+#define BOOST_SLP_MASK 0xC000
+#define BOOST_SLP_SHIFT 14
+
+ // BOOST_XXX CON3
+#define BOOST_CKS_PRG_MASK 0x003F
+#define BOOST_CKS_PRG_SHIFT 0
+
+ // BOOST_XXX CON4
+#define BOOST_OC_THD_MASK 0x0030
+#define BOOST_OC_THD_SHIFT 4
+
+#define BOOST_OC_WND_MASK 0x00C0
+#define BOOST_OC_WND_SHIFT 6
+
+#define BOOST_CLK_CAL_OFFSET CON4_OFFSET
+#define BOOST_CLK_CAL_MASK 0x7000
+#define BOOST_CLK_CAL_SHIFT 12
+
+ // BOOST_XXX CON6
+#define BOOST_HW_SEL_MASK 0x0001
+#define BOOST_HW_SEL_SHIFT 0
+
+#define BOOST_CC_MASK 0x0070
+#define BOOST_CC_SHIFT 4
+
+#endif // #if defined(__DRV_UPMU_BOOST_V1__)
+
+
+#if defined(__DRV_UPMU_ISINK_V1__)
+#define ISINK_CON0_OFFSET 0x00
+#define ISINK_CON1_OFFSET 0x04
+#define ISINK_CON2_OFFSET 0x08
+// iSINK H/W register bitmap definition
+ // ISINK_XXX CON0
+#define ISINK_EN_OFFSET CON0_OFFSET
+#define ISINK_EN_MASK 0x0001
+#define ISINK_EN_SHIFT 0
+
+#define ISINK_MODE_OFFSET CON0_OFFSET
+#define ISINK_MODE_MASK 0x0002
+#define ISINK_MODE_SHIFT 1
+
+#define ISINK_STEP_OFFSET CON0_OFFSET
+#define ISINK_STEP_MASK 0x01F0
+#define ISINK_STEP_SHIFT 4
+
+#define ISINK_STATUS_MASK 0x8000
+#define ISINK_STATUS_SHIFT 15
+
+ // ISINK_XXX CON1
+#define ISINK_VREF_CAL_MASK 0x1F00
+#define ISINK_VREF_CAL_SHIFT 8
+
+#endif // #if defined(__DRV_UPMU_ISINK_V1__)
+
+
+#if defined(__DRV_UPMU_KPLED_V1__)
+#define KPLED_CON0_OFFSET 0x00
+#define KPLED_CON1_OFFSET 0x04
+// KPLED H/W register bitmap definition
+ // KPLED_XXX CON0
+#define KPLED_EN_OFFSET CON0_OFFSET
+#define KPLED_EN_MASK 0x0001
+#define KPLED_EN_SHIFT 0
+
+#define KPLED_MODE_OFFSET CON0_OFFSET
+#define KPLED_MODE_MASK 0x0002
+#define KPLED_MODE_SHIFT 1
+
+#define KPLED_SEL_OFFSET CON0_OFFSET
+#define KPLED_SEL_MASK 0x0070
+#define KPLED_SEL_SHIFT 4
+
+#define KPLED_SFSTRT_C_OFFSET CON0_OFFSET
+#define KPLED_SFSTRT_C_MASK 0x0300
+#define KPLED_SFSTRT_C_SHIFT 8
+
+#define KPLED_SFSTRT_EN_OFFSET CON0_OFFSET
+#define KPLED_SFSTRT_EN_MASK 0x0400
+#define KPLED_SFSTRT_EN_SHIFT 10
+
+#define KPLED_STATUS_OFFSET CON0_OFFSET
+#define KPLED_STATUS_MASK 0x8000
+#define KPLED_STATUS_SHIFT 15
+
+#endif // #if defined(__DRV_UPMU_KPLED_V1__)
+
+
+#if defined(__DRV_UPMU_SPK_V1__)
+#define SPK_CON0_OFFSET 0x00
+#define SPK_CON1_OFFSET 0x04
+#define SPK_CON2_OFFSET 0x08
+#define SPK_CON3_OFFSET 0x0C
+#define SPK_CON4_OFFSET 0x10
+#define SPK_CON5_OFFSET 0x14
+#define SPK_CON6_OFFSET 0x18
+#define SPK_CON7_OFFSET 0x1C
+// SPK H/W register bitmap definition
+ // SPK_XXX CON0
+#define SPK_EN_MASK 0x0001
+#define SPK_EN_SHIFT 0
+
+#define SPK_RST_MASK 0x0002
+#define SPK_RST_SHIFT 1
+
+#define SPK_VOL_OFFSET CON0_OFFSET
+#define SPK_VOL_MASK 0x01F0
+#define SPK_VOL_SHIFT 4
+
+#define SPK_OC_AUTO_OFF_MASK 0x1000
+#define SPK_OC_AUTO_OFF_SHIFT 12
+
+#define SPK_OCFB_EN_MASK 0x2000
+#define SPK_OCFB_EN_SHIFT 13
+
+#define SPK_OC_FLAG_MASK 0x4000
+#define SPK_OC_FLAG_SHIFT 14
+
+ // SPK_XXX CON1
+#define SPK_PFD_MODE_MASK 0x0001
+#define SPK_PFD_MODE_SHIFT 0
+
+#define SPK_CMODE_MASK 0x000C
+#define SPK_CMODE_SHIFT 2
+
+#define SPK_CCODE_MASK 0x00F0
+#define SPK_CCODE_SHIFT 4
+
+ // SPK_XXX CON2
+#define SPK_OC_THD_MASK 0x0030
+#define SPK_OC_THD_SHIFT 4
+
+#define SPK_OC_WND_MASK 0x00C0
+#define SPK_OC_WND_SHIFT 6
+
+ // SPK_XXX CON3
+#define SPK_OC_EN_OFFSET CON3_OFFSET
+#define SPK_OC_EN_MASK 0x0400
+#define SPK_OC_EN_SHIFT 10
+
+#define SPK_OSC_ISEL_MASK 0x00C0
+#define SPK_OSC_ISEL_SHIFT 6
+
+ // SPK_XXX CON4
+#define SPK_NG_DT_DLY_MASK 0x000f
+#define SPK_NG_DT_DLY_SHIFT 0
+#define SPK_OCN_BIAS_MASK 0x0700
+#define SPK_OCN_BIAS_SHIFT 8
+#define SPK_OCP_BIAS_MASK 0x7000
+#define SPK_OCP_BIAS_SHIFT 12
+
+ // SPK_XXX CON5
+#define SPK_NG_SLEW_DLY_MASK 0x0007
+#define SPK_NG_SLEW_DLY_SHIFT 0
+#define SPK_PG_SLEW_DLY_MASK 0x0700
+#define SPK_PG_SLEW_DLY_SHIFT 8
+#define SPK_PG_SLEW_I_MASK 0x3000
+#define SPK_PG_SLEW_I_SHIFT 12
+
+
+ // SPK_XXX CON7
+#define SPK_AB_OBIAS_MASK 0x0030
+#define SPK_AB_OBIAS_SHIFT 4
+#define SPK_AB_OC_EN_MASK 0x0100
+#define SPK_AB_OC_EN_SHIFT 8
+#define SPK_MODE_MASK 0x0001
+#define SPK_MODE_SHIFT 0
+
+
+#endif // #if defined(__DRV_UPMU_SPK_V1__)
+
+
+#if defined(__DRV_UPMU_SPK_V2__)
+#define SPK_CON0_OFFSET 0x00
+#define SPK_CON1_OFFSET 0x04
+// SPK H/W register bitmap definition
+ // SPK_XXX CON0
+#define SPK_EN_MASK 0x0001
+#define SPK_EN_SHIFT 0
+
+#define SPK_VOL_OFFSET CON0_OFFSET
+#define SPK_VOL_MASK 0x001E
+#define SPK_VOL_SHIFT 1
+
+#define SPK_OUT_FLOAT_B_MASK 0x0020
+#define SPK_OUT_FLOAT_B_SHIFT 5
+
+#define SPK_OC_EN_OFFSET CON0_OFFSET
+#define SPK_OC_EN_MASK 0x0040
+#define SPK_OC_EN_SHIFT 6
+
+#define SPK_OBIAS_MASK 0x00C0
+#define SPK_OBIAS_SHIFT 7
+
+#define SPK_IN_TIE_HIGH_MASK 0x0400
+#define SPK_IN_TIE_HIGH_SHIFT 10
+
+#define SPK_IN_FLOAT_B_MASK 0x0800
+#define SPK_IN_FLOAT_B_SHIFT 11
+
+#define SPK_MINUS_GAIN_MASK 0x3000
+#define SPK_MINUS_GAIN_SHIFT 12
+
+ // SPK_XXX CON1
+#define SPK_OC_THD_MASK 0x0003 // OC_TRG
+#define SPK_OC_THD_SHIFT 0
+
+#define SPK_OC_WND_MASK 0x000C
+#define SPK_OC_WND_SHIFT 2
+
+#define SPK_OC_AUTO_OFF_MASK 0x0040
+#define SPK_OC_AUTO_OFF_SHIFT 6
+
+#define SPK_OC_FLAG_MASK 0x8000
+#define SPK_OC_FLAG_SHIFT 15
+
+#endif // #if defined(__DRV_UPMU_SPK_V2__)
+
+
+#if defined(__DRV_UPMU_CHARGER_V1__)
+#define CHR_CON0_OFFSET 0x00
+#define CHR_CON1_OFFSET 0x04
+#define CHR_CON2_OFFSET 0x08
+#define CHR_CON3_OFFSET 0x0C
+#define CHR_CON4_OFFSET 0x10
+#define CHR_CON5_OFFSET 0x14
+#define CHR_CON6_OFFSET 0x18
+#define CHR_CON7_OFFSET 0x1C
+#define CHR_CON8_OFFSET 0x20
+#define CHR_CON9_OFFSET 0x24
+#define CHR_BC11_CON0_OFFSET CHR_CON9_OFFSET
+#define CHR_CON10_OFFSET 0x28
+#define CHR_BC11_CON1_OFFSET CHR_CON10_OFFSET
+// CHARGER H/W register bitmap definition
+ // CHR_XXX CON0
+#define VCDT_LV_VTH_MASK 0x001F
+#define VCDT_LV_VTH_SHIFT 0
+#define VCDT_HV_VTH_MASK 0x00F0
+#define VCDT_HV_VTH_SHIFT 4
+#define VCDT_HV_EN_MASK 0x0100
+#define VCDT_HV_EN_SHIFT 8
+#define PCHR_AUTO_MASK 0x0400
+#define PCHR_AUTO_SHIFT 10
+
+#define CSDAC_EN_OFFSET CON0_OFFSET
+#define CSDAC_EN_MASK 0x0800
+#define CSDAC_EN_SHIFT 11
+
+#define CHR_EN_OFFSET CON0_OFFSET
+#define CHR_EN_MASK 0x1000
+#define CHR_EN_SHIFT 12
+
+#define CHRDET_OFFSET CON0_OFFSET
+#define CHRDET_MASK 0x2000
+#define CHRDET_SHIFT 13
+
+#define VCDT_LV_DET_MASK 0x4000
+#define VCDT_LV_DET_SHIFT 14
+#define VCDT_HV_DET_MASK 0x8000
+#define VCDT_HV_DET_SHIFT 15
+ // CHR_XXX CON1
+#define VBAT_CV_VTH_OFFSET CON1_OFFSET
+#define VBAT_CV_VTH_MASK 0x001F
+#define VBAT_CV_VTH_SHIFT 0
+
+#define VBAT_CC_VTH_MASK 0x00C0
+#define VBAT_CC_VTH_SHIFT 6
+
+#define VBAT_CV_EN_OFFSET CON1_OFFSET
+#define VBAT_CV_EN_MASK 0x0100
+#define VBAT_CV_EN_SHIFT 8
+
+#define VBAT_CC_EN_MASK 0x0200
+#define VBAT_CC_EN_SHIFT 9
+
+#define VBAT_CV_DET_OFFSET CON1_OFFSET
+#define VBAT_CV_DET_MASK 0x4000
+#define VBAT_CV_DET_SHIFT 14
+
+#define VBAT_CC_DET_MASK 0x8000
+#define VBAT_CC_DET_SHIFT 15
+ // CHR_XXX CON2
+#define PCHR_TOHTC_MASK 0x0007
+#define PCHR_TOHTC_SHIFT 0
+#define PCHR_TOLTC_MASK 0x0070
+#define PCHR_TOLTC_SHIFT 4
+
+#define CS_VTH_OFFSET CON2_OFFSET
+#define CS_VTH_MASK 0x0700
+#define CS_VTH_SHIFT 8
+
+#define CS_EN_MASK 0x1000
+#define CS_EN_SHIFT 12
+#if defined(__DRV_OTG_BVALID_DET_AT_CON2_BIT14__)
+#define OTG_BVALID_DET_MASK 0x4000
+#define OTG_BVALID_DET_SHIFT 14
+#endif // #if defined(__DRV_OTG_BVALID_DET_AT_CON2_BIT14__)
+#define CS_DET_MASK 0x8000
+#define CS_DET_SHIFT 15
+ // CHR_XXX CON3
+#define CSDAC_STP_MASK 0x0003
+#define CSDAC_STP_SHIFT 0
+#if defined(__DRV_VBAT_OV_EN_AT_CON3_BIT3__)
+#define VBAT_OV_EN_MASK 0x0008
+#define VBAT_OV_EN_SHIFT 3
+#endif // #if defined(__DRV_VBAT_OV_EN_AT_CON3_BIT3__)
+#define CSDAC_DLY_MASK 0x0030
+#define CSDAC_DLY_SHIFT 4
+#define VBAT_OV_VTH_MASK 0x00C0
+#define VBAT_OV_VTH_SHIFT 6
+#if defined(__DRV_VBAT_OV_EN_AT_CON3_BIT8__)
+#define VBAT_OV_EN_MASK 0x0100
+#define VBAT_OV_EN_SHIFT 8
+#endif // #if defined(__DRV_VBAT_OV_EN_AT_CON3_BIT8__)
+#if defined(__DRV_BATON_EN_AT_CON3_BIT9__)
+#define BATON_EN_MASK 0x0200
+#define BATON_EN_SHIFT 9
+#endif // #if defined(__DRV_BATON_EN_AT_CON3_BIT9__)
+
+#define BATON_HT_EN_MASK 0x0400
+#define BATON_HT_EN_SHIFT 10
+
+#if defined(__DRV_BATON_EN_AT_CON3_BIT12__)
+#define BATON_EN_MASK 0x1000
+#define BATON_EN_SHIFT 12
+#endif // #if defined(__DRV_BATON_EN_AT_CON3_BIT12__)
+#if defined(__DRV_OTG_BVALID_EN_AT_CON3_BIT13__)
+#define OTG_BVALID_EN_OFFSET CON3_OFFSET
+#define OTG_BVALID_EN_MASK 0x2000
+#define OTG_BVALID_EN_SHIFT 13
+#endif // #if defined(__DRV_OTG_BVALID_EN_AT_CON3_BIT13__)
+#define VBAT_OV_DET_MASK 0x4000
+#define VBAT_OV_DET_SHIFT 14
+#define BATON_UNDET_MASK 0x8000
+#define BATON_UNDET_SHIFT 15
+ // CHR_XXX CON4
+#define PCHR_TEST_MASK 0x0001
+#define PCHR_TEST_SHIFT 0
+#define PCHR_CSDAC_TEST_MASK 0x0002
+#define PCHR_CSDAC_TEST_SHIFT 1
+#define PCHR_RST_MASK 0x0004
+#define PCHR_RST_SHIFT 2
+#define CSDAC_DAT_MASK 0xFF00
+#define CSDAC_DAT_SHIFT 8
+ // CHR_XXX CON5
+#define PCHR_FLAG_SEL_MASK 0x000F
+#define PCHR_FLAG_SEL_SHIFT 0
+#define PCHR_FLAG_EN_MASK 0x0080
+#define PCHR_FLAG_EN_SHIFT 7
+#define PCHR_FLAG_OUT_MASK 0x0F00
+#define PCHR_FLAG_OUT_SHIFT 8
+#if defined(__DRV_OTG_BVALID_EN_AT_CON5_BIT12__)
+#define OTG_BVALID_EN_OFFSET CON5_OFFSET
+#define OTG_BVALID_EN_MASK 0x1000
+#define OTG_BVALID_EN_SHIFT 12
+#endif // #if defined(__DRV_OTG_BVALID_EN_AT_CON5_BIT12__)
+#if defined(__DRV_OTG_BVALID_DET_AT_CON5_BIT15__)
+#define OTG_BVALID_DET_MASK 0x8000
+#define OTG_BVALID_DET_SHIFT 15
+#endif // #if defined(__DRV_OTG_BVALID_DET_AT_CON5_BIT15__)
+
+ // CHR_XXX CON6
+
+#define CHRWDT_TD_OFFSET CON6_OFFSET
+#define CHRWDT_TD_MASK 0x000F // TTTTTTTTT
+#define CHRWDT_TD_SHIFT 0
+
+#define CHRWDT_EN_OFFSET CON6_OFFSET
+#define CHRWDT_EN_MASK 0x0010
+#define CHRWDT_EN_SHIFT 4
+
+ // CHR_XXX CON7
+#define CHRWDT_INT_EN_OFFSET CON7_OFFSET
+#define CHRWDT_INT_EN_MASK 0x0001
+#define CHRWDT_INT_EN_SHIFT 0
+
+#define CHRWDT_FLAG_WR_MASK 0x0002
+#define CHRWDT_FLAG_WR_SHIFT 1
+#define CHRWDT_OUT_MASK 0x8000
+#define CHRWDT_OTU_SHIFT 15
+ // CHR_XXX CON8
+#define BGR_RSEL_MASK 0x0007
+#define BGR_RSEL_SHIFT 0
+#define BGR_UNCHOP_PH_MASK 0x0010
+#define BGR_UNCHOP_PH_SHIFT 4
+#define BGR_UNCHOP_MASK 0x0020
+#define BGR_UNCHOP_SHIFT 5
+#define UVLO_VTHL_MASK 0x0300
+#define UVLO_VTHL_SHIFT 8
+
+#define ADC_EN_OFFSET CON8_OFFSET
+#define ADC_EN_MASK 0x7000 // All ADC channels are enabled at same time
+#define ADC_EN_SHIFT 12
+ // CHR_XXX CON9 (CHR_BC11_CON0)
+
+#if defined(__DRV_UPMU_BC11_V1__)
+
+#if defined(__DRV_UPMU_BC11_MAPPING_V1__)
+#define BC11_VREF_VTH_OFFSET CON9_OFFSET
+#define BC11_VREF_VTH_MASK 0x0001
+#define BC11_VREF_VTH_SHIFT 0
+
+#define BC11_CMP_EN_OFFSET CON9_OFFSET
+#define BC11_CMP_EN_MASK 0x0006
+#define BC11_CMP_EN_SHIFT 1
+
+#define BC11_IPD_EN_OFFSET CON9_OFFSET
+#define BC11_IPD_EN_MASK 0x0018
+#define BC11_IPD_EN_SHIFT 3
+
+#define BC11_IPU_EN_OFFSET CON9_OFFSET
+#define BC11_IPU_EN_MASK 0x0060
+#define BC11_IPU_EN_SHIFT 5
+
+#define BC11_BIAS_EN_OFFSET CON9_OFFSET
+#define BC11_BIAS_EN_MASK 0x0080
+#define BC11_BIAS_EN_SHIFT 7
+
+#define BC11_BB_CTRL_OFFSET CON9_OFFSET
+#define BC11_BB_CTRL_MASK 0x0100
+#define BC11_BB_CTRL_SHIFT 8
+
+#define BC11_RST_OFFSET CON9_OFFSET
+#define BC11_RST_MASK 0x0200
+#define BC11_RST_SHIFT 9
+
+#if defined(__MT6251PMU_E1_BC11_VSRC_EN_AT_TEST_CON1_BIT4__)
+#define BC11_VSRC_EN_OFFSET 0x0504 //CHR_CON0+0x0504=TEST_CON1
+#define BC11_VSRC_EN_MASK 0x0030
+#define BC11_VSRC_EN_SHIFT 4
+#else
+#define BC11_VSRC_EN_OFFSET CON9_OFFSET
+#define BC11_VSRC_EN_MASK 0x0C00
+#define BC11_VSRC_EN_SHIFT 10
+#endif //#if defined(__MT6251PMU_E1_BC11_VSRC_EN_AT_TEST_CON1_BIT4__)
+
+#define BC11_CMP_OUT_OFFSET CON9_OFFSET
+#define BC11_CMP_OUT_MASK 0x8000
+#define BC11_CMP_OUT_SHIFT 15
+#endif //#if defined(__DRV_UPMU_BC11_MAPPING_V1)
+
+#if defined(__DRV_UPMU_BC11_MAPPING_V2__)
+#define BC11_VREF_VTH_OFFSET CHR_CON10_OFFSET
+#define BC11_VREF_VTH_MASK 0x0040
+#define BC11_VREF_VTH_SHIFT 6
+
+#define BC11_CMP_EN_OFFSET CHR_CON10_OFFSET
+#define BC11_CMP_EN_MASK 0x0003
+#define BC11_CMP_EN_SHIFT 0
+
+#define BC11_IPD_EN_OFFSET CHR_CON10_OFFSET
+#define BC11_IPD_EN_MASK 0x000c
+#define BC11_IPD_EN_SHIFT 2
+
+#define BC11_IPU_EN_OFFSET CHR_CON10_OFFSET
+#define BC11_IPU_EN_MASK 0x0030
+#define BC11_IPU_EN_SHIFT 4
+
+#define BC11_BIAS_EN_OFFSET CHR_CON10_OFFSET
+#define BC11_BIAS_EN_MASK 0x0080
+#define BC11_BIAS_EN_SHIFT 7
+
+#define BC11_BB_CTRL_OFFSET CHR_CON10_OFFSET
+#define BC11_BB_CTRL_MASK 0x0100
+#define BC11_BB_CTRL_SHIFT 8
+
+#define BC11_RST_OFFSET CHR_CON9_OFFSET
+#define BC11_RST_MASK 0x0100
+#define BC11_RST_SHIFT 8
+
+#define BC11_VSRC_EN_OFFSET CHR_CON9_OFFSET
+#define BC11_VSRC_EN_MASK 0x0003
+#define BC11_VSRC_EN_SHIFT 0
+
+#define BC11_CMP_OUT_OFFSET CHR_CON10_OFFSET
+#define BC11_CMP_OUT_MASK 0x0200
+#define BC11_CMP_OUT_SHIFT 9
+
+#endif //#if defined(__DRV_UPMU_BC11_MAPPING_V2__)
+#endif // #if defined(__DRV_UPMU_BC11_V1__)
+
+
+#endif // #if defined(__DRV_UPMU_CHARGER_V1__)
+
+#if defined(__DRV_UPMU_STRUP_V1__)
+#define STRUP_CON0_OFFSET 0x00
+
+ // STRUP_XXX CON0
+#define USBDL_EN_OFFSET CON0_OFFSET
+#define USBDL_EN_MASK 0x0010
+#define USBDL_EN_SHIFT 4
+#endif // #if defined(__DRV_UPMU_STRUP_V1__)
+
+
+
+
+
+#endif //#define __DCL_PMU_COMMON_HW_STRUCT__
+
diff --git a/mcu/driver/peripheral/inc/dcl_pmu_sw.h b/mcu/driver/peripheral/inc/dcl_pmu_sw.h
new file mode 100644
index 0000000..e4c52bf
--- /dev/null
+++ b/mcu/driver/peripheral/inc/dcl_pmu_sw.h
@@ -0,0 +1,111 @@
+
+
+#include "dcl_pmic_features.h"
+
+
+#if defined(MT6276PMU)
+#include "dcl_pmu6276_sw.h"
+#include "dcl_pmu6276_hw.h"
+#include "dcl_pmu_hw.h"
+
+
+#elif defined(MT6238PMU) || defined(MT6235PMU)
+#include "dcl_pmu6235_sw.h"
+#include "dcl_pmu6235_hw.h"
+
+#elif defined(MT6236PMU)
+#include "dcl_pmu6236_sw.h"
+#include "dcl_pmu6236_hw.h"
+
+#elif defined(MT6251PMU)
+#include "dcl_pmu6251_sw.h"
+#include "dcl_pmu6251_hw.h"
+#include "dcl_pmu_hw.h"
+
+#elif defined(MT6253PMU)
+#include "dcl_pmu6253_sw.h"
+#include "dcl_pmu6253_hw.h"
+
+#elif defined(MT6253ELPMU) || defined(MT6252PMU)
+#include "dcl_pmu6252_sw.h"
+#include "dcl_pmu6252_hw.h"
+#include "dcl_pmu_hw.h"
+
+#elif defined(MT6255PMU)
+#include "dcl_pmu6255_sw.h"
+#include "dcl_pmu6255_hw.h"
+#include "dcl_pmu_hw.h"
+
+#elif defined(MT6256PMU)
+#include "dcl_pmu6256_sw.h"
+#include "dcl_pmu6256_hw.h"
+#include "dcl_pmu_hw.h"
+
+#elif defined(MT6573PMU)
+#include "dcl_pmu6573_sw.h"
+#include "dcl_pmu6573_hw.h"
+#include "dcl_pmu_hw.h"
+
+
+#elif defined(MT6326)
+#include "dcl_pmic6326_sw.h"
+#include "dcl_pmic6326_hw.h"
+
+#elif defined(MT6326_CCCI)
+#include "dcl_pmic6326_ccci_sw.h"
+
+#elif defined(MT6329)
+#include "dcl_pmic6329_sw.h"
+#include "dcl_pmic6329_hw.h"
+
+#elif defined(MT6327)
+#include "dcl_pmic6327_sw.h"
+#include "dcl_pmic6327_hw.h"
+
+#endif //#if defined(MT6276PMU)
+
+#include "dcl_pmu_common_sw.h"
+
+#if defined(PMIC_FIXED_3_ADC_CH)
+/* adc number for measuring VBAT/VISENSE/VCHARGER is fixed internally. */
+#define PMIC_ADC_VCHARGER_CH_NUM PMU_ADC_VCHARGER_CH_NUM
+#define PMIC_ADC_VISENSE_CH_NUM PMU_ADC_VISENSE_CH_NUM
+#define PMIC_ADC_VBAT_CH_NUM PMU_ADC_VBAT_CH_NUM
+#if defined(PMIC_FIXED_4_ADC_CH)
+#define PMIC_ADC_VBATTEMP_CH_NUM PMU_ADC_VBATTEMP_CH_NUM
+#endif // #if defined(PMIC_FIXED_4_ADC_CH)
+
+/* adc factor for VBAT/VISENSE/VCHARGER */
+#define PMIC_ADC_FACTOR_VBAT PMU_ADC_FACTOR_VBAT
+#define PMIC_ADC_FACTOR_VISENSE PMU_ADC_FACTOR_VISENSE
+#define PMIC_ADC_FACTOR_VCHARGER PMU_ADC_FACTOR_VCHARGER
+#if defined(PMIC_FIXED_4_ADC_CH)
+#define PMIC_ADC_FACTOR_VBATTEMP PMU_ADC_FACTOR_VBATTEMP
+#endif // #if defined(PMIC_FIXED_4_ADC_CH)
+
+#endif // #if defined(PMIC_FIXED_3_ADC_CH)
+
+#if defined(PMIC_FIXED_CHR_EINT)
+#define PMIC_CHR_EINT_PIN PMU_CHR_EINT_PIN
+#endif // #if defined(PMIC_FIXED_CHR_EINT)
+
+#define DCL_PMU_DEV_MAGIC_NUM (0x80000000)
+#define DCL_PMU_IS_HANDLE_MAGIC(handl_) ((handl_)& DCL_PMU_DEV_MAGIC_NUM)
+
+
+#ifndef __DRV_DEBUG_PWIC_REG_READ_WRITE__
+#define PWIC_DRV_ClearBits16(addr, data) DRV_ClearBits(addr,data)
+#define PWIC_DRV_SetBits16(addr, data) DRV_SetBits(addr,data)
+#define PWIC_DRV_WriteReg16(addr, data) DRV_WriteReg(addr, data)
+#define PWIC_DRV_WriteReg32(addr, data) DRV_WriteReg32(addr, data)
+#define PWIC_DRV_ReadReg16(addr) DRV_Reg(addr)
+#define PWIC_DRV_ReadReg32(addr) DRV_Reg32(addr)
+#else // #ifndef __DRV_DEBUG_PWIC_REG_READ_WRITE__
+#define PWIC_DRV_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
+#define PWIC_DRV_SetBits16(addr) DRV_DBG_SetBits(addr)
+#define PWIC_DRV_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
+#define PWIC_DRV_WriteReg32(addr, data) DRV_DBG_WriteReg32(addr, data)
+#define PWIC_DRV_ReadReg16(addr) DRV_DBG_Reg(addr)
+#define PWIC_DRV_ReadReg32(addr) DRV_DBG_Reg32(addr)
+#endif // #ifndef __DRV_DEBUG_PWIC_REG_READ_WRITE__
+
diff --git a/mcu/driver/peripheral/inc/f32k_clk_hw.h b/mcu/driver/peripheral/inc/f32k_clk_hw.h
new file mode 100644
index 0000000..0debeff
--- /dev/null
+++ b/mcu/driver/peripheral/inc/f32k_clk_hw.h
@@ -0,0 +1,202 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * f32k_clk_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for F32K_CLK driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef F32K_CLK_HW_H
+#define F32K_CLK_HW_H
+
+#include "drv_features_f32k.h"
+#include "reg_base.h"
+
+#if !defined(DRV_F32K_CLK_OFF)
+#if defined(DRV_F32K_FQMTR_AS_6255)
+#define FQMTR_BASE (PLL_base+0x0000)
+#define FQMTR_CON0 (PLL_base+0x1080)
+#define FQMTR_CON1 (PLL_base+0x1084)
+#define FQMTR_CON2 (PLL_base+0x1088)
+#define FQMTR_CON3 (PLL_base+0x108c)
+#define FQMTR_CON4 (PLL_base+0x1090)
+#elif defined(DRV_F32K_FQMTR_AS_6250)
+#define FQMTR_CON0 (PMU_base+0x0ff0)
+#define FQMTR_CON1 (PMU_base+0x0ff4)
+#define FQMTR_CON2 (PMU_base+0x0ff8)
+#define FQMTR_CON3 (PMU_base+0x0ffc)
+#elif defined(DRV_F32K_FQMTR_AS_6280)
+#define FQMTR_CON0 (MIX_ABB_base+0x0400)
+#define FQMTR_CON1 (MIX_ABB_base+0x0404)
+#define FQMTR_CON2 (MIX_ABB_base+0x0408)
+#define FQMTR_CON3 (MIX_ABB_base+0x040C)
+#endif
+
+#if defined(DRV_F32K_SWITCH_32K)
+#define F32K_MD_CHIP_STATUS (CONFIG_base+0x0018)
+#define F32K_AP_F32K_SEL (AP_CONFIG_base+0x000c)
+
+#define F32K_SYS_PAD32K_BOND_EN (0x200) //(((*(volatile kal_uint16 *)(F32K_MD_CHIP_STATUS))&0x200)>>9)
+
+#define F32K_AP_DCXO32K_CK_EN (0x0)
+#define F32K_AP_PAD32K_CK_EN (0x2)
+
+#endif
+
+#if defined(DRV_F32K_FQMTR_AS_6255)
+
+#define FQMTR_EN (0x8000)
+#define FQMTR_RST (0x4000)
+
+#define FQMTR_TCKSEL_CLKSQ13M (0x1)
+#define FQMTR_TCKSEL_EOSC32K (0xe)
+
+#define FQMTR_FCKSEL_CLKSQ13M (0x00)
+#define FQMTR_FCKSEL_DCXO32K (0x10)
+#define FQMTR_FCKSEL_EOSC32K (0x20)
+
+#define FQMTR_COND_ON (0x0)
+#define FQMTR_BUSY (0x8000)
+
+#define FQMTR_WINSET_LV1 (0x1)
+#define FQMTR_WINSET_LV2 (0x10)
+
+#elif defined(DRV_F32K_FQMTR_AS_6250)
+
+#define FQMTR_BUSY (0x8000)
+#define FQMTR_EN (0x4000)
+#define FQMTR_RST (0x2000)
+
+#define FQMTR_TCKSEL_DCXO32K (0x3)
+#define FQMTR_TCKSEL_EOSC32K (0x4)
+
+#define FQMTR_WINSET_LV1 (0xFFFF)
+
+#elif defined(DRV_F32K_FQMTR_AS_6280)
+
+#define FQMTR_EN (0x8000)
+#define FQMTR_RST (0x4000)
+#define FQMTR_FCKSEL_CLK26M (0x000)
+#define FQMTR_FCKSEL_PAD32K (0x100)
+#define FQMTR_FCKSEL_DCXO32K (0x200)
+
+#define FQMTR_TCKSEL_CLKSSQ26M (0x1)
+#define FQMTR_BUSY (0x8000)
+#define FQMTR_CLKDIV_1_OVER_2 (0x0)
+#define F32K_FQMTR_WINSET (0x0)
+
+#define FQMTR_CON0_DEFAULT_VAL (0x0)
+#define FQMTR_CON1_DEFAULT_VAL (0x0)
+
+#endif
+
+#if defined(DRV_F32K_XOSC_CALI_DEF_9)
+#define F32K_XOSCCALI_DEF_VAL (0x9)
+#elif defined(DRV_F32K_XOSC_CALI_DEF_F)
+#define F32K_XOSCCALI_DEF_VAL (0xf)
+#endif
+
+#define F32K_EOSCCALI_DEF_VAL (0xF)
+
+#endif /*!defined(DRV_F32K_CLK_OFF)*/
+
+#endif //#ifndef F32K_CLK_HW_H
+
diff --git a/mcu/driver/peripheral/inc/f32k_clk_sw.h b/mcu/driver/peripheral/inc/f32k_clk_sw.h
new file mode 100644
index 0000000..bc7edcc
--- /dev/null
+++ b/mcu/driver/peripheral/inc/f32k_clk_sw.h
@@ -0,0 +1,199 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * f32k_clk_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for F32K_CLK driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef F32K_CLK_SW_H
+#define F32K_CLK_SW_H
+
+#include "kal_general_types.h"
+#include "drv_comm.h"
+
+#if defined(DRV_F32K_FQMTR_AS_6255)
+#define IDLE_VAL_WITH_WINSET_LV1 (0x319) //13M meter 32K with winset=1
+#define IDLE_VAL_WITH_WINSET_LV2 (0x1a59) //13M meter 32K with winset=16
+#elif defined(DRV_F32K_FQMTR_AS_6250)
+#define IDLE_VAL_WITH_WINSET_LV1 (0x52) //26M meter 32K with winset=0xffff
+#endif
+
+#if defined(DRV_F32K_FQMTR_AS_6280)
+// 26MHZ = PAD_32K clock*(1+-2.5%) * FQMTR_data/(0x1)
+#define FQMTR_PAD32K_LOWER_BOUND (774)
+#define FQMTR_PAD32K_UPPER_BOUND (814)
+#endif
+
+#define F32K_EOSCCALI_MAX (0x1f)
+#define F32K_EOSCCALI_MIN (0x0)
+// =================================================================
+// Exported APIs, used by modules other than driver level functions
+#if defined(DRV_F32K_INTERNAL_32K)
+extern void F32K_XOSC32_EMB_setting(void);
+#endif //#if defined(DRV_F32K_INTERNAL_32K)
+
+
+#if !defined(__MINI_BOOTLOADER__)
+#if defined(DRV_F32K_INTERNAL_32K) || defined(DRV_F32K_SWITCH_32K)
+extern kal_bool F32K_Query_Is_XOSC32(void);
+#endif //#if defined(DRV_F32K_INTERNAL_32K) || defined(DRV_F32K_SWITCH_32K)
+
+
+#if defined(DRV_F32K_INTERNAL_32K)
+extern kal_uint16 F32K_EOSC32_trimming(void);
+#endif //#if defined(DRV_F32K_INTERNAL_32K)
+
+#if defined(DRV_F32K_SWITCH_32K)
+extern void F32K_Switch_32K_setting(void);
+#endif //#if defined(DRV_F32K_SWITCH_32K)
+
+#endif //#if !defined(__MINI_BOOTLOADER__)
+
+#if !defined(DRV_F32K_CLK_OFF)
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_F32K_CLK_REG_DBG__)
+#define DRV_F32K_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+#define DRV_F32K_Reg(addr) DRV_DBG_Reg(addr)
+#define DRV_F32K_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define DRV_F32K_Reg32(addr) DRV_DBG_Reg32(addr)
+#define DRV_F32K_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+#define DRV_F32K_Reg8(addr) DRV_DBG_Reg8(addr)
+#define DRV_F32K_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+#define DRV_F32K_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+#define DRV_F32K_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#define DRV_F32K_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+#define DRV_F32K_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+#define DRV_F32K_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+#define DRV_F32K_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+#define DRV_F32K_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+#define DRV_F32K_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+#else
+#define DRV_F32K_WriteReg(addr,data) DRV_WriteReg(addr,data)
+#define DRV_F32K_Reg(addr) DRV_Reg(addr)
+#define DRV_F32K_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define DRV_F32K_Reg32(addr) DRV_Reg32(addr)
+#define DRV_F32K_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+#define DRV_F32K_Reg8(addr) DRV_Reg8(addr)
+#define DRV_F32K_ClearBits(addr,data) DRV_ClearBits(addr,data)
+#define DRV_F32K_SetBits(addr,data) DRV_SetBits(addr,data)
+#define DRV_F32K_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define DRV_F32K_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+#define DRV_F32K_SetBits32(addr,data) DRV_SetBits32(addr,data)
+#define DRV_F32K_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+#define DRV_F32K_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+#define DRV_F32K_SetBits8(addr,data) DRV_SetBits8(addr,data)
+#define DRV_F32K_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_F32K_CLK_REG_DBG__)
+
+#else //!defined(DRV_F32K_CLK_OFF)
+
+#define DRV_F32K_WriteReg(addr,data)
+#define DRV_F32K_Reg(addr) drv_dummy_return()
+#define DRV_F32K_WriteReg32(addr,data)
+#define DRV_F32K_Reg32(addr) drv_dummy_return()
+#define DRV_F32K_WriteReg8(addr,data)
+#define DRV_F32K_Reg8(addr) drv_dummy_return()
+#define DRV_F32K_ClearBits(addr,data)
+#define DRV_F32K_SetBits(addr,data)
+#define DRV_F32K_SetData(addr, bitmask, value)
+#define DRV_F32K_ClearBits32(addr,data)
+#define DRV_F32K_SetBits32(addr,data)
+#define DRV_F32K_SetData32(addr, bitmask, value)
+#define DRV_F32K_ClearBits8(addr,data)
+#define DRV_F32K_SetBits8(addr,data)
+#define DRV_F32K_SetData8(addr, bitmask, value)
+
+#endif //!defined(DRV_F32K_CLK_OFF)
+
+
+#endif //#ifndef F32K_CLK_SW_H
+
diff --git a/mcu/driver/peripheral/inc/gpio_common_hw.h b/mcu/driver/peripheral/inc/gpio_common_hw.h
new file mode 100644
index 0000000..249263a
--- /dev/null
+++ b/mcu/driver/peripheral/inc/gpio_common_hw.h
@@ -0,0 +1,13 @@
+#ifndef __GPIO_COMMON_HW_H__
+#define __GPIO_COMMON_HW_H__
+#if defined(DRV_GPIO_NEW_INIT_ARCHI)
+
+#if defined(DRV_GPIO_REG_AS_6280)
+#include "gpio6280_hw.h"
+#endif//defined(DRV_GPIO_REG_AS_6280)
+
+#else //defined(DRV_GPIO_NEW_INIT_ARCHI)
+#include "gpio_hw.h"
+#endif//defined(DRV_GPIO_NEW_INIT_ARCHI)
+
+#endif//__GPIO_COMMON_HW_H__
\ No newline at end of file
diff --git a/mcu/driver/peripheral/inc/gpio_hw.h b/mcu/driver/peripheral/inc/gpio_hw.h
new file mode 100644
index 0000000..9c8b7ef
--- /dev/null
+++ b/mcu/driver/peripheral/inc/gpio_hw.h
@@ -0,0 +1,2280 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * gpio_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for GPIO driver.
+ *
+ * Author:
+ * -------
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _GPIO_HW_H
+#define _GPIO_HW_H
+
+#include "drv_features_gpio.h"
+#include "reg_base.h"
+
+#if !defined(DRV_GPIO_OFF)
+ //MMP address
+#if defined(DRV_GPIO_REG_AS_6205) || defined(DRV_GPIO_REG_AS_6205B)
+ #define GPIO_DIR (GPIO_base+0x0000)
+ #define GPIO_DIR2 (GPIO_base+0x0004)
+ #define GPIO_PULLEN (GPIO_base+0x0008)
+ #define GPIO_PULLEN2 (GPIO_base+0x000c)
+ #define GPIO_DOUT (GPIO_base+0x0010)
+ #define GPIO_DOUT2 (GPIO_base+0x0014)
+ #define GPIO_DIN (GPIO_base+0x0018)
+ #define GPIO_DIN2 (GPIO_base+0x001c)
+ #define GPO_DOUT (GPIO_base+0x0020)
+ #define GPIO_MODE1 (GPIO_base+0x0024)
+ #define GPIO_MODE2 (GPIO_base+0x0028)
+ #define GPIO_MODE3 (GPIO_base+0x002c)
+ #define GPIO_MODE4 (GPIO_base+0x0030)
+
+
+ #if defined(DRV_GPIO_REG_AS_6205B)
+ #define GPIO_DIR_SET (GPIO_base+0x0040+0x0000)
+ #define GPIO_DIR2_SET (GPIO_base+0x0040+0x0004)
+ #define GPIO_PULLEN_SET (GPIO_base+0x0040+0x0008)
+ #define GPIO_PULLEN2_SET (GPIO_base+0x0040+0x000c)
+ #define GPIO_DOUT_SET (GPIO_base+0x0040+0x0010)
+ #define GPIO_DOUT2_SET (GPIO_base+0x0040+0x0014)
+ #define GPIO_DIN_SET (GPIO_base+0x0040+0x0018)
+ #define GPIO_DIN2_SET (GPIO_base+0x0040+0x001c)
+ #define GPO_DOUT_SET (GPIO_base+0x0040+0x0020)
+ #define GPIO_MODE1_SET (GPIO_base+0x0040+0x0024)
+ #define GPIO_MODE2_SET (GPIO_base+0x0040+0x0028)
+ #define GPIO_MODE3_SET (GPIO_base+0x0040+0x002c)
+ #define GPIO_MODE4_SET (GPIO_base+0x0040+0x0030)
+ #define GPIO_MODE_SET(_no) (GPIO_MODE1_SET+(0x04*(_no)))
+
+ #define GPIO_DIR_CLR (GPIO_base+0x0080+0x0000)
+ #define GPIO_DIR2_CLR (GPIO_base+0x0080+0x0004)
+ #define GPIO_PULLEN_CLR (GPIO_base+0x0080+0x0008)
+ #define GPIO_PULLEN2_CLR (GPIO_base+0x0080+0x000c)
+ #define GPIO_DOUT_CLR (GPIO_base+0x0080+0x0010)
+ #define GPIO_DOUT2_CLR (GPIO_base+0x0080+0x0014)
+ #define GPIO_DIN_CLR (GPIO_base+0x0080+0x0018)
+ #define GPIO_DIN2_CLR (GPIO_base+0x0080+0x001c)
+ #define GPO_DOUT_CLR (GPIO_base+0x0080+0x0020)
+ #define GPIO_MODE1_CLR (GPIO_base+0x0080+0x0024)
+ #define GPIO_MODE2_CLR (GPIO_base+0x0080+0x0028)
+ #define GPIO_MODE3_CLR (GPIO_base+0x0080+0x002c)
+ #define GPIO_MODE4_CLR (GPIO_base+0x0080+0x0030)
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE1_CLR+(0x04*(_no)))
+
+
+ #endif /*DRV_GPIO_REG_AS_6205B*/
+
+ #define GPIO_MODE(_no) (GPIO_MODE1+(0x4*(_no)))
+
+#endif /*DRV_GPIO_REG_AS_6205,DRV_GPIO_REG_AS_6205B*/
+
+#if defined(DRV_GPIO_REG_AS_6208) || defined(FPGA)
+ #define GPIO_DIR (GPIO_base+0x0000)
+ #define GPIO_DOUT (GPIO_base+0x0004)
+ #define GPIO_DIN (GPIO_base+0x0008)
+ #define GPIO_MODE1 (GPIO_base+0x000C)
+ #define GPIO_MODE2 (GPIO_base+0x0010)
+ #define GPI_O_DIO (GPIO_base+0x0018)
+ #define GPI_O_MODE (GPIO_base+0x001c)
+
+ #define GPIO_MODE(_no) (GPIO_MODE1+(0x4*(_no)))
+
+#endif /*DRV_GPIO_REG_AS_6208,FPGA*/
+
+#if defined(DRV_GPIO_REG_AS_6218)
+ #define GPIO_DIR1 (GPIO_base+0x0000)
+ #define GPIO_DIR2 (GPIO_base+0x0010)
+ #define GPIO_DIR3 (GPIO_base+0x0020)
+ #define GPIO_PULLEN1 (GPIO_base+0x0030)
+ #define GPIO_PULLEN2 (GPIO_base+0x0040)
+ #define GPIO_PULLEN3 (GPIO_base+0x0050)
+ #define GPIO_DOUT1 (GPIO_base+0x0060)
+ #define GPIO_DOUT2 (GPIO_base+0x0070)
+ #define GPIO_DOUT3 (GPIO_base+0x0080)
+ #define GPIO_DIN1 (GPIO_base+0x0090)
+ #define GPIO_DIN2 (GPIO_base+0x0094)
+ #define GPIO_DIN3 (GPIO_base+0x0098)
+ #define GPO_DOUT (GPIO_base+0x00a0)
+ #define GPIO_MODE1 (GPIO_base+0x00b0)
+ #define GPIO_MODE2 (GPIO_base+0x00c0)
+ #define GPIO_MODE3 (GPIO_base+0x00d0)
+ #define GPIO_MODE4 (GPIO_base+0x00e0)
+ #define GPIO_MODE5 (GPIO_base+0x00f0)
+ #define GPIO_MODE6 (GPIO_base+0x0100)
+ #define GPO_MODE (GPIO_base+0x0110)
+
+ #define GPIO_DIR1_SET (GPIO_base+0x0000+0x04)
+ #define GPIO_DIR2_SET (GPIO_base+0x0010+0x04)
+ #define GPIO_DIR3_SET (GPIO_base+0x0020+0x04)
+ #define GPIO_PULLEN1_SET (GPIO_base+0x0030+0x04)
+ #define GPIO_PULLEN2_SET (GPIO_base+0x0040+0x04)
+ #define GPIO_PULLEN3_SET (GPIO_base+0x0050+0x04)
+ #define GPIO_DOUT1_SET (GPIO_base+0x0060+0x04)
+ #define GPIO_DOUT2_SET (GPIO_base+0x0070+0x04)
+ #define GPIO_DOUT3_SET (GPIO_base+0x0080+0x04)
+ #define GPO_DOUT_SET (GPIO_base+0x00a0+0x04)
+ #define GPIO_MODE1_SET (GPIO_base+0x00b0+0x04)
+ #define GPIO_MODE2_SET (GPIO_base+0x00c0+0x04)
+ #define GPIO_MODE3_SET (GPIO_base+0x00d0+0x04)
+ #define GPIO_MODE4_SET (GPIO_base+0x00e0+0x04)
+ #define GPIO_MODE5_SET (GPIO_base+0x00f0+0x04)
+ #define GPIO_MODE6_SET (GPIO_base+0x0100+0x04)
+ #define GPO_MODE_SET (GPIO_base+0x0110+0x04)
+ #define GPIO_MODE_SET(_no) (GPIO_MODE1_SET+(0x10*(_no)))
+ #define GPIO_DIR_SET(_no) (GPIO_DIR1_SET+(0x10*(_no)))
+ #define GPIO_DOUT_SET(_no) (GPIO_DOUT1_SET+(0x10*(_no)))
+
+ #define GPIO_DIR1_CLR (GPIO_base+0x0000+0x08)
+ #define GPIO_DIR2_CLR (GPIO_base+0x0010+0x08)
+ #define GPIO_DIR3_CLR (GPIO_base+0x0020+0x08)
+ #define GPIO_PULLEN1_CLR (GPIO_base+0x0030+0x08)
+ #define GPIO_PULLEN2_CLR (GPIO_base+0x0040+0x08)
+ #define GPIO_PULLEN3_CLR (GPIO_base+0x0050+0x08)
+ #define GPIO_DOUT1_CLR (GPIO_base+0x0060+0x08)
+ #define GPIO_DOUT2_CLR (GPIO_base+0x0070+0x08)
+ #define GPIO_DOUT3_CLR (GPIO_base+0x0080+0x08)
+ #define GPO_DOUT_CLR (GPIO_base+0x00a0+0x08)
+ #define GPIO_MODE1_CLR (GPIO_base+0x00b0+0x08)
+ #define GPIO_MODE2_CLR (GPIO_base+0x00c0+0x08)
+ #define GPIO_MODE3_CLR (GPIO_base+0x00d0+0x08)
+ #define GPIO_MODE4_CLR (GPIO_base+0x00e0+0x08)
+ #define GPIO_MODE5_CLR (GPIO_base+0x00f0+0x08)
+ #define GPIO_MODE6_CLR (GPIO_base+0x0100+0x08)
+ #define GPO_MODE_CLR (GPIO_base+0x0110+0x08)
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE1_CLR+(0x10*(_no)))
+ #define GPIO_DIR_CLR(_no) (GPIO_DIR1_CLR+(0x10*(_no)))
+ #define GPIO_DOUT_CLR(_no) (GPIO_DOUT1_CLR+(0x10*(_no)))
+
+ #define GPIO_MODE(_no) (GPIO_MODE1+(0x10*(_no)))
+ #define GPIO_DOUT(_no) (GPIO_DOUT1+(0x10*(_no)))
+ #define GPIO_DIR(_no) (GPIO_DIR1+(0x10*(_no)))
+#endif /*DRV_GPIO_REG_AS_6218*/
+
+#if defined(DRV_GPIO_REG_AS_6218B)
+ #define GPIO_DIR1 (GPIO_base+0x0000)
+ #define GPIO_DIR2 (GPIO_base+0x0010)
+ #define GPIO_DIR3 (GPIO_base+0x0020)
+ #define GPIO_PULLEN1 (GPIO_base+0x0030)
+ #define GPIO_PULLEN2 (GPIO_base+0x0040)
+ #define GPIO_PULLEN3 (GPIO_base+0x0050)
+ #define GPIO_DINV1 (GPIO_base+0x0060)
+ #define GPIO_DINV2 (GPIO_base+0x0070)
+ #define GPIO_DINV3 (GPIO_base+0x0080)
+ #define GPIO_DOUT1 (GPIO_base+0x0090)
+ #define GPIO_DOUT2 (GPIO_base+0x00a0)
+ #define GPIO_DOUT3 (GPIO_base+0x00b0)
+ #define GPIO_DIN1 (GPIO_base+0x00c0)
+ #define GPIO_DIN2 (GPIO_base+0x00d0)
+ #define GPIO_DIN3 (GPIO_base+0x00e0)
+ #define GPO_DOUT (GPIO_base+0x00f0)
+ #define GPIO_MODE1 (GPIO_base+0x0100)
+ #define GPIO_MODE2 (GPIO_base+0x0110)
+ #define GPIO_MODE3 (GPIO_base+0x0120)
+ #define GPIO_MODE4 (GPIO_base+0x0130)
+ #define GPIO_MODE5 (GPIO_base+0x0140)
+ #define GPIO_MODE6 (GPIO_base+0x0150)
+ #define GPO_MODE (GPIO_base+0x0160)
+
+ #define GPIO_DIR1_SET (GPIO_base+0x0000+0x04)
+ #define GPIO_DIR2_SET (GPIO_base+0x0010+0x04)
+ #define GPIO_DIR3_SET (GPIO_base+0x0020+0x04)
+ #define GPIO_PULLEN1_SET (GPIO_base+0x0030+0x04)
+ #define GPIO_PULLEN2_SET (GPIO_base+0x0040+0x04)
+ #define GPIO_PULLEN3_SET (GPIO_base+0x0050+0x04)
+ #define GPIO_DOUT1_SET (GPIO_base+0x0090+0x04)
+ #define GPIO_DOUT2_SET (GPIO_base+0x00a0+0x04)
+ #define GPIO_DOUT3_SET (GPIO_base+0x00b0+0x04)
+ #define GPO_DOUT_SET (GPIO_base+0x00f0+0x04)
+ #define GPIO_MODE1_SET (GPIO_base+0x0100+0x04)
+ #define GPIO_MODE2_SET (GPIO_base+0x0110+0x04)
+ #define GPIO_MODE3_SET (GPIO_base+0x0120+0x04)
+ #define GPIO_MODE4_SET (GPIO_base+0x0130+0x04)
+ #define GPIO_MODE5_SET (GPIO_base+0x0140+0x04)
+ #define GPIO_MODE6_SET (GPIO_base+0x0150+0x04)
+ #define GPO_MODE_SET (GPIO_base+0x0160+0x04)
+ #define GPIO_DINV_ADRS(n) (GPIO_DINV1+0x10*(n))
+ #define GPIO_MODE_SET(_no) (GPIO_MODE1_SET+(0x10*(_no)))
+ #define GPIO_DIR_SET(_no) (GPIO_DIR1_SET+(0x10*(_no)))
+ #define GPIO_DOUT_SET(_no) (GPIO_DOUT1_SET+(0x10*(_no)))
+ #define GPIO_PULLEN_SET(_no) (GPIO_PULLEN1_SET+(0x10*(_no)))
+
+ #define GPIO_DIR1_CLR (GPIO_base+0x0000+0x08)
+ #define GPIO_DIR2_CLR (GPIO_base+0x0010+0x08)
+ #define GPIO_DIR3_CLR (GPIO_base+0x0020+0x08)
+ #define GPIO_PULLEN1_CLR (GPIO_base+0x0030+0x08)
+ #define GPIO_PULLEN2_CLR (GPIO_base+0x0040+0x08)
+ #define GPIO_PULLEN3_CLR (GPIO_base+0x0050+0x08)
+ #define GPIO_DOUT1_CLR (GPIO_base+0x0090+0x08)
+ #define GPIO_DOUT2_CLR (GPIO_base+0x00a0+0x08)
+ #define GPIO_DOUT3_CLR (GPIO_base+0x00b0+0x08)
+ #define GPO_DOUT_CLR (GPIO_base+0x00f0+0x08)
+ #define GPIO_MODE1_CLR (GPIO_base+0x0100+0x08)
+ #define GPIO_MODE2_CLR (GPIO_base+0x0110+0x08)
+ #define GPIO_MODE3_CLR (GPIO_base+0x0120+0x08)
+ #define GPIO_MODE4_CLR (GPIO_base+0x0130+0x08)
+ #define GPIO_MODE5_CLR (GPIO_base+0x0140+0x08)
+ #define GPIO_MODE6_CLR (GPIO_base+0x0150+0x08)
+ #define GPO_MODE_CLR (GPIO_base+0x0160+0x08)
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE1_CLR+(0x10*(_no)))
+ #define GPIO_DIR_CLR(_no) (GPIO_DIR1_CLR+(0x10*(_no)))
+ #define GPIO_DOUT_CLR(_no) (GPIO_DOUT1_CLR+(0x10*(_no)))
+ #define GPIO_PULLEN_CLR(_no) (GPIO_PULLEN1_CLR+(0x10*(_no)))
+
+ #define GPIO_MODE(_no) (GPIO_MODE1+(0x10*(_no)))
+ #define GPIO_DOUT(_no) (GPIO_DOUT1+(0x10*(_no)))
+ #define GPIO_DIR(_no) (GPIO_DIR1+(0x10*(_no)))
+#endif /*DRV_GPIO_REG_AS_6218B*/
+
+#if defined(DRV_GPIO_REG_AS_6219) || defined(DRV_GPIO_REG_AS_6225) || defined(DRV_GPIO_REG_AS_6223)
+ #define GPIO_DIR1 (GPIO_base+0x0000)
+ #define GPIO_DIR2 (GPIO_base+0x0010)
+ #define GPIO_DIR3 (GPIO_base+0x0020)
+ #define GPIO_DIR4 (GPIO_base+0x0030)
+ #define GPIO_PULLEN1 (GPIO_base+0x0040)
+ #define GPIO_PULLEN2 (GPIO_base+0x0050)
+ #define GPIO_PULLEN3 (GPIO_base+0x0060)
+ #define GPIO_PULLEN4 (GPIO_base+0x0070)
+ #define GPIO_DINV1 (GPIO_base+0x0080)
+ #define GPIO_DINV2 (GPIO_base+0x0090)
+ #define GPIO_DINV3 (GPIO_base+0x00a0)
+ #define GPIO_DINV4 (GPIO_base+0x00b0)
+ #define GPIO_DOUT1 (GPIO_base+0x00c0)
+ #define GPIO_DOUT2 (GPIO_base+0x00d0)
+ #define GPIO_DOUT3 (GPIO_base+0x00e0)
+ #define GPIO_DOUT4 (GPIO_base+0x00f0)
+ #define GPIO_DIN1 (GPIO_base+0x0100)
+ #define GPIO_DIN2 (GPIO_base+0x0110)
+ #define GPIO_DIN3 (GPIO_base+0x0120)
+ #define GPIO_DIN4 (GPIO_base+0x0130)
+ #if !defined(DRV_GPIO_REG_AS_6223)
+ #define GPO_DOUT (GPIO_base+0x0140)
+ #endif /* DRV_GPIO_REG_AS_6223 */
+ #define GPIO_MODE1 (GPIO_base+0x0150)
+ #define GPIO_MODE2 (GPIO_base+0x0160)
+ #define GPIO_MODE3 (GPIO_base+0x0170)
+ #define GPIO_MODE4 (GPIO_base+0x0180)
+ #define GPIO_MODE5 (GPIO_base+0x0190)
+ #define GPIO_MODE6 (GPIO_base+0x01a0)
+ #define GPIO_MODE7 (GPIO_base+0x01b0)
+ #if defined(DRV_GPIO_REG_AS_6223)
+ #define GPIO_BANK (GPIO_base+0x01c0)
+ #define CLKO_MODE1 (GPIO_base+0x0200)
+ #define CLKO_MODE2 (GPIO_base+0x0210)
+ #define CLKO_MODE3 (GPIO_base+0x0220)
+ #define CLKO_MODE4 (GPIO_base+0x0230)
+ #define CLKO_MODE5 (GPIO_base+0x0240)
+ #define CLKO_MODE6 (GPIO_base+0x0250)
+ #else /* DRV_GPIO_REG_AS_6223 */
+ #define GPO_MODE (GPIO_base+0x01c0)
+ #endif /* DRV_GPIO_REG_AS_6223 */
+ #define GPIO_DINV_ADRS(n) (GPIO_DINV1+0x10*(n))
+
+ #define GPIO_DIR1_SET (GPIO_base+0x0000+0x04)
+ #define GPIO_DIR2_SET (GPIO_base+0x0010+0x04)
+ #define GPIO_DIR3_SET (GPIO_base+0x0020+0x04)
+ #define GPIO_DIR4_SET (GPIO_base+0x0030+0x04)
+ #define GPIO_PULLEN1_SET (GPIO_base+0x0040+0x04)
+ #define GPIO_PULLEN2_SET (GPIO_base+0x0050+0x04)
+ #define GPIO_PULLEN3_SET (GPIO_base+0x0060+0x04)
+ #define GPIO_PULLEN4_SET (GPIO_base+0x0070+0x04)
+ #define GPIO_DOUT1_SET (GPIO_base+0x00c0+0x04)
+ #define GPIO_DOUT2_SET (GPIO_base+0x00d0+0x04)
+ #define GPIO_DOUT3_SET (GPIO_base+0x00e0+0x04)
+ #define GPIO_DOUT4_SET (GPIO_base+0x00f0+0x04)
+ #if !defined(DRV_GPIO_REG_AS_6223)
+ #define GPO_DOUT_SET (GPIO_base+0x0140+0x04)
+ #endif /* DRV_GPIO_REG_AS_6223 */
+ #define GPIO_MODE1_SET (GPIO_base+0x0150+0x04)
+ #define GPIO_MODE2_SET (GPIO_base+0x0160+0x04)
+ #define GPIO_MODE3_SET (GPIO_base+0x0170+0x04)
+ #define GPIO_MODE4_SET (GPIO_base+0x0180+0x04)
+ #define GPIO_MODE5_SET (GPIO_base+0x0190+0x04)
+ #define GPIO_MODE6_SET (GPIO_base+0x01a0+0x04)
+ #define GPIO_MODE7_SET (GPIO_base+0x01b0+0x04)
+ #if defined(DRV_GPIO_REG_AS_6223)
+ #define GPIO_BANK_SET (GPIO_base+0x01c0+0x04)
+ #define CLKO_MODE1_SET (GPIO_base+0x0200+0x04)
+ #define CLKO_MODE2_SET (GPIO_base+0x0210+0x04)
+ #define CLKO_MODE3_SET (GPIO_base+0x0220+0x04)
+ #define CLKO_MODE4_SET (GPIO_base+0x0230+0x04)
+ #define CLKO_MODE5_SET (GPIO_base+0x0240+0x04)
+ #define CLKO_MODE6_SET (GPIO_base+0x0250+0x04)
+ #else /* DRV_GPIO_REG_AS_6223 */
+ #define GPO_MODE_SET (GPIO_base+0x01c0+0x04)
+ #endif /* DRV_GPIO_REG_AS_6223 */
+ #define GPIO_MODE_SET(_no) (GPIO_MODE1_SET+(0x10*(_no)))
+ #define GPIO_DIR_SET(_no) (GPIO_DIR1_SET+(0x10*(_no)))
+ #define GPIO_DOUT_SET(_no) (GPIO_DOUT1_SET+(0x10*(_no)))
+ #define GPIO_PULLEN_SET(_no) (GPIO_PULLEN1_SET+(0x10*(_no)))
+ #if defined(DRV_GPIO_REG_AS_6223)
+ #define CLKO_MODE_SET(_no) (CLKO_MODE1_SET+(0x10*(_no)))
+ #endif /* DRV_GPIO_REG_AS_6223 */
+ #define GPIO_DIR1_CLR (GPIO_base+0x0000+0x08)
+ #define GPIO_DIR2_CLR (GPIO_base+0x0010+0x08)
+ #define GPIO_DIR3_CLR (GPIO_base+0x0020+0x08)
+ #define GPIO_DIR4_CLR (GPIO_base+0x0030+0x08)
+ #define GPIO_PULLEN1_CLR (GPIO_base+0x0040+0x08)
+ #define GPIO_PULLEN2_CLR (GPIO_base+0x0050+0x08)
+ #define GPIO_PULLEN3_CLR (GPIO_base+0x0060+0x08)
+ #define GPIO_PULLEN4_CLR (GPIO_base+0x0070+0x08)
+ #define GPIO_DOUT1_CLR (GPIO_base+0x00c0+0x08)
+ #define GPIO_DOUT2_CLR (GPIO_base+0x00d0+0x08)
+ #define GPIO_DOUT3_CLR (GPIO_base+0x00e0+0x08)
+ #define GPIO_DOUT4_CLR (GPIO_base+0x00f0+0x08)
+ #if !defined(DRV_GPIO_REG_AS_6223)
+ #define GPO_DOUT_CLR (GPIO_base+0x0140+0x08)
+ #endif /* DRV_GPIO_REG_AS_6223 */
+ #define GPIO_MODE1_CLR (GPIO_base+0x0150+0x08)
+ #define GPIO_MODE2_CLR (GPIO_base+0x0160+0x08)
+ #define GPIO_MODE3_CLR (GPIO_base+0x0170+0x08)
+ #define GPIO_MODE4_CLR (GPIO_base+0x0180+0x08)
+ #define GPIO_MODE5_CLR (GPIO_base+0x0190+0x08)
+ #define GPIO_MODE6_CLR (GPIO_base+0x01a0+0x08)
+ #define GPIO_MODE7_CLR (GPIO_base+0x01b0+0x08)
+ #if defined(DRV_GPIO_REG_AS_6223)
+ #define GPIO_BANK_CLR (GPIO_base+0x01c0+0x08)
+ #define CLKO_MODE1_CLR (GPIO_base+0x0200+0x08)
+ #define CLKO_MODE2_CLR (GPIO_base+0x0210+0x08)
+ #define CLKO_MODE3_CLR (GPIO_base+0x0220+0x08)
+ #define CLKO_MODE4_CLR (GPIO_base+0x0230+0x08)
+ #define CLKO_MODE5_CLR (GPIO_base+0x0240+0x08)
+ #define CLKO_MODE6_CLR (GPIO_base+0x0250+0x08)
+ #else /* DRV_GPIO_REG_AS_6223 */
+ #define GPO_MODE_CLR (GPIO_base+0x01c0+0x08)
+ #endif /* DRV_GPIO_REG_AS_6223 */
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE1_CLR+(0x10*(_no)))
+ #define GPIO_DIR_CLR(_no) (GPIO_DIR1_CLR+(0x10*(_no)))
+ #define GPIO_DOUT_CLR(_no) (GPIO_DOUT1_CLR+(0x10*(_no)))
+ #define GPIO_PULLEN_CLR(_no) (GPIO_PULLEN1_CLR+(0x10*(_no)))
+ #if defined(DRV_GPIO_REG_AS_6223)
+ #define CLKO_MODE_CLR(_no) (CLKO_MODE1_CLR+(0x10*(_no)))
+ #endif /* DRV_GPIO_REG_AS_6223 */
+
+ #define GPIO_MODE(_no) (GPIO_MODE1+(0x10*(_no)))
+ #define GPIO_DOUT(_no) (GPIO_DOUT1+(0x10*(_no)))
+ #define GPIO_DIR(_no) (GPIO_DIR1+(0x10*(_no)))
+ #if defined(DRV_GPIO_REG_AS_6223)
+ #define CLKO_MODE(_no) (CLKO_MODE1+(0x10*(_no)))
+ #define CLKO_NUM 6
+ #endif /* DRV_GPIO_REG_AS_6223 */
+#endif /*DRV_GPIO_REG_AS_6219, DRV_GPIO_REG_AS_6225*/
+
+#if defined(DRV_GPIO_REG_AS_6227)
+ #define GPIO_DIR1 (GPIO_base+0x0000)
+ #define GPIO_DIR2 (GPIO_base+0x0010)
+ #define GPIO_DIR3 (GPIO_base+0x0020)
+ #define GPIO_DIR4 (GPIO_base+0x0030)
+ #define GPIO_PULLEN1 (GPIO_base+0x0040)
+ #define GPIO_PULLEN2 (GPIO_base+0x0050)
+ #define GPIO_PULLEN3 (GPIO_base+0x0060)
+ #define GPIO_PULLEN4 (GPIO_base+0x0070)
+ #define GPIO_DINV1 (GPIO_base+0x0080)
+ #define GPIO_DINV2 (GPIO_base+0x0090)
+ #define GPIO_DINV3 (GPIO_base+0x00a0)
+ #define GPIO_DINV4 (GPIO_base+0x00b0)
+ #define GPIO_DOUT1 (GPIO_base+0x00c0)
+ #define GPIO_DOUT2 (GPIO_base+0x00d0)
+ #define GPIO_DOUT3 (GPIO_base+0x00e0)
+ #define GPIO_DOUT4 (GPIO_base+0x00f0)
+ #define GPIO_DIN1 (GPIO_base+0x0100)
+ #define GPIO_DIN2 (GPIO_base+0x0110)
+ #define GPIO_DIN3 (GPIO_base+0x0120)
+ #define GPIO_DIN4 (GPIO_base+0x0130)
+ #define GPO_DOUT (GPIO_base+0x0140)
+ #define GPIO_MODE1 (GPIO_base+0x0150)
+ #define GPIO_MODE2 (GPIO_base+0x0160)
+ #define GPIO_MODE3 (GPIO_base+0x0170)
+ #define GPIO_MODE4 (GPIO_base+0x0180)
+ #define GPIO_MODE5 (GPIO_base+0x0190)
+ #define GPIO_MODE6 (GPIO_base+0x01a0)
+ #define GPIO_MODE7 (GPIO_base+0x01b0)
+ #define GPIO_MODE8 (GPIO_base+0x01d0)
+ #define GPO_MODE (GPIO_base+0x01c0)
+ #define GPIO_DINV_ADRS(n) (GPIO_DINV1+0x10*(n))
+
+ #define GPIO_DIR1_SET (GPIO_base+0x0000+0x04)
+ #define GPIO_DIR2_SET (GPIO_base+0x0010+0x04)
+ #define GPIO_DIR3_SET (GPIO_base+0x0020+0x04)
+ #define GPIO_DIR4_SET (GPIO_base+0x0030+0x04)
+ #define GPIO_PULLEN1_SET (GPIO_base+0x0040+0x04)
+ #define GPIO_PULLEN2_SET (GPIO_base+0x0050+0x04)
+ #define GPIO_PULLEN3_SET (GPIO_base+0x0060+0x04)
+ #define GPIO_PULLEN4_SET (GPIO_base+0x0070+0x04)
+ #define GPIO_DOUT1_SET (GPIO_base+0x00c0+0x04)
+ #define GPIO_DOUT2_SET (GPIO_base+0x00d0+0x04)
+ #define GPIO_DOUT3_SET (GPIO_base+0x00e0+0x04)
+ #define GPIO_DOUT4_SET (GPIO_base+0x00f0+0x04)
+ #define GPO_DOUT_SET (GPIO_base+0x0140+0x04)
+ #define GPIO_MODE1_SET (GPIO_base+0x0150+0x04)
+ #define GPIO_MODE2_SET (GPIO_base+0x0160+0x04)
+ #define GPIO_MODE3_SET (GPIO_base+0x0170+0x04)
+ #define GPIO_MODE4_SET (GPIO_base+0x0180+0x04)
+ #define GPIO_MODE5_SET (GPIO_base+0x0190+0x04)
+ #define GPIO_MODE6_SET (GPIO_base+0x01a0+0x04)
+ #define GPIO_MODE7_SET (GPIO_base+0x01b0+0x04)
+ #define GPIO_MODE8_SET (GPIO_base+0x01d0+0x04)
+ #define GPO_MODE_SET (GPIO_base+0x01c0+0x04)
+ #define GPIO_MODE_SET(_no) (GPIO_MODE1_SET+(0x10*(_no)))
+ #define GPIO_DIR_SET(_no) (GPIO_DIR1_SET+(0x10*(_no)))
+ #define GPIO_DOUT_SET(_no) (GPIO_DOUT1_SET+(0x10*(_no)))
+ #define GPIO_PULLEN_SET(_no) (GPIO_PULLEN1_SET+(0x10*(_no)))
+
+ #define GPIO_DIR1_CLR (GPIO_base+0x0000+0x08)
+ #define GPIO_DIR2_CLR (GPIO_base+0x0010+0x08)
+ #define GPIO_DIR3_CLR (GPIO_base+0x0020+0x08)
+ #define GPIO_DIR4_CLR (GPIO_base+0x0030+0x08)
+ #define GPIO_PULLEN1_CLR (GPIO_base+0x0040+0x08)
+ #define GPIO_PULLEN2_CLR (GPIO_base+0x0050+0x08)
+ #define GPIO_PULLEN3_CLR (GPIO_base+0x0060+0x08)
+ #define GPIO_PULLEN4_CLR (GPIO_base+0x0070+0x08)
+ #define GPIO_DOUT1_CLR (GPIO_base+0x00c0+0x08)
+ #define GPIO_DOUT2_CLR (GPIO_base+0x00d0+0x08)
+ #define GPIO_DOUT3_CLR (GPIO_base+0x00e0+0x08)
+ #define GPIO_DOUT4_CLR (GPIO_base+0x00f0+0x08)
+ #define GPO_DOUT_CLR (GPIO_base+0x0140+0x08)
+ #define GPIO_MODE1_CLR (GPIO_base+0x0150+0x08)
+ #define GPIO_MODE2_CLR (GPIO_base+0x0160+0x08)
+ #define GPIO_MODE3_CLR (GPIO_base+0x0170+0x08)
+ #define GPIO_MODE4_CLR (GPIO_base+0x0180+0x08)
+ #define GPIO_MODE5_CLR (GPIO_base+0x0190+0x08)
+ #define GPIO_MODE6_CLR (GPIO_base+0x01a0+0x08)
+ #define GPIO_MODE7_CLR (GPIO_base+0x01b0+0x08)
+ #define GPIO_MODE8_CLR (GPIO_base+0x01d0+0x08)
+ #define GPO_MODE_CLR (GPIO_base+0x01c0+0x08)
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE1_CLR+(0x10*(_no)))
+ #define GPIO_DIR_CLR(_no) (GPIO_DIR1_CLR+(0x10*(_no)))
+ #define GPIO_DOUT_CLR(_no) (GPIO_DOUT1_CLR+(0x10*(_no)))
+ #define GPIO_PULLEN_CLR(_no) (GPIO_PULLEN1_CLR+(0x10*(_no)))
+
+ #define GPIO_MODE(_no) (GPIO_MODE1+(0x10*(_no)))
+ #define GPIO_DOUT(_no) (GPIO_DOUT1+(0x10*(_no)))
+ #define GPIO_DIR(_no) (GPIO_DIR1+(0x10*(_no)))
+ #define GPIO_DIN(_no) (GPIO_DIN1+(0x10*(_no)))
+
+#endif /*DRV_GPIO_REG_AS_6227*/
+
+
+#if defined(DRV_GPIO_REG_AS_6228)
+ #define GPIO_DIR1 (GPIO_base+0x0000)
+ #define GPIO_DIR2 (GPIO_base+0x0010)
+ #define GPIO_DIR3 (GPIO_base+0x0020)
+ #define GPIO_DIR4 (GPIO_base+0x0030)
+ #define GPIO_DIR5 (GPIO_base+0x0040)
+ #define GPIO_PULLEN1 (GPIO_base+0x0050)
+ #define GPIO_PULLEN2 (GPIO_base+0x0060)
+ #define GPIO_PULLEN3 (GPIO_base+0x0070)
+ #define GPIO_PULLEN4 (GPIO_base+0x0080)
+ #define GPIO_PULLEN5 (GPIO_base+0x0090)
+ #define GPIO_DINV1 (GPIO_base+0x00a0)
+ #define GPIO_DINV2 (GPIO_base+0x00b0)
+ #define GPIO_DINV3 (GPIO_base+0x00c0)
+ #define GPIO_DINV4 (GPIO_base+0x00d0)
+ #define GPIO_DINV5 (GPIO_base+0x00e0)
+ #define GPIO_DOUT1 (GPIO_base+0x00f0)
+ #define GPIO_DOUT2 (GPIO_base+0x0100)
+ #define GPIO_DOUT3 (GPIO_base+0x0110)
+ #define GPIO_DOUT4 (GPIO_base+0x0120)
+ #define GPIO_DOUT5 (GPIO_base+0x0130)
+ #define GPIO_DIN1 (GPIO_base+0x0140)
+ #define GPIO_DIN2 (GPIO_base+0x0150)
+ #define GPIO_DIN3 (GPIO_base+0x0160)
+ #define GPIO_DIN4 (GPIO_base+0x0170)
+ #define GPIO_DIN5 (GPIO_base+0x0180)
+ #define GPO_DOUT (GPIO_base+0x0190)
+ #define GPIO_MODE1 (GPIO_base+0x01a0)
+ #define GPIO_MODE2 (GPIO_base+0x01b0)
+ #define GPIO_MODE3 (GPIO_base+0x01c0)
+ #define GPIO_MODE4 (GPIO_base+0x01d0)
+ #define GPIO_MODE5 (GPIO_base+0x01e0)
+ #define GPIO_MODE6 (GPIO_base+0x01f0)
+ #define GPIO_MODE7 (GPIO_base+0x0200)
+ #define GPIO_MODE8 (GPIO_base+0x0210)
+ #define GPIO_MODE9 (GPIO_base+0x0220)
+ #define GPIO_MODE10 (GPIO_base+0x0230)
+ #define GPO_MODE (GPIO_base+0x0240)
+ #define GPIO_DINV_ADRS(n) (GPIO_DINV1+0x10*(n))
+
+ #define GPIO_DIR1_SET (GPIO_base+0x0000+0x04)
+ #define GPIO_DIR2_SET (GPIO_base+0x0010+0x04)
+ #define GPIO_DIR3_SET (GPIO_base+0x0020+0x04)
+ #define GPIO_DIR4_SET (GPIO_base+0x0030+0x04)
+ #define GPIO_DIR5_SET (GPIO_base+0x0040+0x04)
+ #define GPIO_PULLEN1_SET (GPIO_base+0x0050+0x04)
+ #define GPIO_PULLEN2_SET (GPIO_base+0x0060+0x04)
+ #define GPIO_PULLEN3_SET (GPIO_base+0x0070+0x04)
+ #define GPIO_PULLEN4_SET (GPIO_base+0x0080+0x04)
+ #define GPIO_PULLEN5_SET (GPIO_base+0x0090+0x04)
+ #define GPIO_DOUT1_SET (GPIO_base+0x00f0+0x04)
+ #define GPIO_DOUT2_SET (GPIO_base+0x0100+0x04)
+ #define GPIO_DOUT3_SET (GPIO_base+0x0110+0x04)
+ #define GPIO_DOUT4_SET (GPIO_base+0x0120+0x04)
+ #define GPIO_DOUT5_SET (GPIO_base+0x0130+0x04)
+ #define GPO_DOUT_SET (GPIO_base+0x0190+0x04)
+ #define GPIO_MODE1_SET (GPIO_base+0x01a0+0x04)
+ #define GPIO_MODE2_SET (GPIO_base+0x01b0+0x04)
+ #define GPIO_MODE3_SET (GPIO_base+0x01c0+0x04)
+ #define GPIO_MODE4_SET (GPIO_base+0x01d0+0x04)
+ #define GPIO_MODE5_SET (GPIO_base+0x01e0+0x04)
+ #define GPIO_MODE6_SET (GPIO_base+0x01f0+0x04)
+ #define GPIO_MODE7_SET (GPIO_base+0x0200+0x04)
+ #define GPIO_MODE8_SET (GPIO_base+0x0210+0x04)
+ #define GPIO_MODE9_SET (GPIO_base+0x0220+0x04)
+ #define GPIO_MODE10_SET (GPIO_base+0x0230+0x04)
+ #define GPO_MODE_SET (GPIO_base+0x0240+0x04)
+ #define GPIO_MODE_SET(_no) (GPIO_MODE1_SET+(0x10*(_no)))
+ #define GPIO_DIR_SET(_no) (GPIO_DIR1_SET+(0x10*(_no)))
+ #define GPIO_DOUT_SET(_no) (GPIO_DOUT1_SET+(0x10*(_no)))
+ #define GPIO_PULLEN_SET(_no) (GPIO_PULLEN1_SET+(0x10*(_no)))
+
+ #define GPIO_DIR1_CLR (GPIO_base+0x0000+0x08)
+ #define GPIO_DIR2_CLR (GPIO_base+0x0010+0x08)
+ #define GPIO_DIR3_CLR (GPIO_base+0x0020+0x08)
+ #define GPIO_DIR4_CLR (GPIO_base+0x0030+0x08)
+ #define GPIO_DIR5_CLR (GPIO_base+0x0040+0x08)
+ #define GPIO_PULLEN1_CLR (GPIO_base+0x0050+0x08)
+ #define GPIO_PULLEN2_CLR (GPIO_base+0x0060+0x08)
+ #define GPIO_PULLEN3_CLR (GPIO_base+0x0070+0x08)
+ #define GPIO_PULLEN4_CLR (GPIO_base+0x0080+0x08)
+ #define GPIO_PULLEN5_CLR (GPIO_base+0x0090+0x08)
+ #define GPIO_DOUT1_CLR (GPIO_base+0x00f0+0x08)
+ #define GPIO_DOUT2_CLR (GPIO_base+0x0100+0x08)
+ #define GPIO_DOUT3_CLR (GPIO_base+0x0110+0x08)
+ #define GPIO_DOUT4_CLR (GPIO_base+0x0120+0x08)
+ #define GPIO_DOUT5_CLR (GPIO_base+0x0130+0x08)
+ #define GPO_DOUT_CLR (GPIO_base+0x0190+0x08)
+ #define GPIO_MODE1_CLR (GPIO_base+0x01a0+0x08)
+ #define GPIO_MODE2_CLR (GPIO_base+0x01b0+0x08)
+ #define GPIO_MODE3_CLR (GPIO_base+0x01c0+0x08)
+ #define GPIO_MODE4_CLR (GPIO_base+0x01d0+0x08)
+ #define GPIO_MODE5_CLR (GPIO_base+0x01e0+0x08)
+ #define GPIO_MODE6_CLR (GPIO_base+0x01f0+0x08)
+ #define GPIO_MODE7_CLR (GPIO_base+0x0200+0x08)
+ #define GPIO_MODE8_CLR (GPIO_base+0x0210+0x08)
+ #define GPIO_MODE9_CLR (GPIO_base+0x0220+0x08)
+ #define GPIO_MODE10_CLR (GPIO_base+0x0230+0x08)
+ #define GPO_MODE_CLR (GPIO_base+0x0240+0x08)
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE1_CLR+(0x10*(_no)))
+ #define GPIO_DIR_CLR(_no) (GPIO_DIR1_CLR+(0x10*(_no)))
+ #define GPIO_DOUT_CLR(_no) (GPIO_DOUT1_CLR+(0x10*(_no)))
+ #define GPIO_PULLEN_CLR(_no) (GPIO_PULLEN1_CLR+(0x10*(_no)))
+
+ #define GPIO_MODE(_no) (GPIO_MODE1+(0x10*(_no)))
+ #define GPIO_DOUT(_no) (GPIO_DOUT1+(0x10*(_no)))
+ #define GPIO_DIR(_no) (GPIO_DIR1+(0x10*(_no)))
+ #define GPIO_DIN(_no) (GPIO_DIN1+(0x10*(_no)))
+#endif /*DRV_GPIO_REG_AS_6228*/
+
+#if defined(DRV_GPIO_REG_AS_6268T)
+ #define GPIO_DIR1 (GPIO_base+0x0000)
+ #define GPIO_DIR2 (GPIO_base+0x0010)
+ #define GPIO_PULLEN1 (GPIO_base+0x0050)
+ #define GPIO_PULLEN2 (GPIO_base+0x0060)
+ #define GPIO_DINV1 (GPIO_base+0x00a0)
+ #define GPIO_DINV2 (GPIO_base+0x00b0)
+ #define GPIO_DOUT1 (GPIO_base+0x00f0)
+ #define GPIO_DOUT2 (GPIO_base+0x0100)
+ #define GPIO_DIN1 (GPIO_base+0x0140)
+ #define GPIO_DIN2 (GPIO_base+0x0150)
+ #define GPIO_MODE1 (GPIO_base+0x01a0)
+ #define GPIO_MODE2 (GPIO_base+0x01b0)
+ #define GPIO_MODE3 (GPIO_base+0x01c0)
+ #define GPIO_MODE4 (GPIO_base+0x01d0)
+ #define GPIO_DINV_ADRS(n) (GPIO_DINV1+0x10*(n))
+
+ #define GPIO_DIR1_SET (GPIO_base+0x0000+0x04)
+ #define GPIO_DIR2_SET (GPIO_base+0x0010+0x04)
+ #define GPIO_PULLEN1_SET (GPIO_base+0x0050+0x04)
+ #define GPIO_PULLEN2_SET (GPIO_base+0x0060+0x04)
+ #define GPIO_DOUT1_SET (GPIO_base+0x00f0+0x04)
+ #define GPIO_DOUT2_SET (GPIO_base+0x0100+0x04)
+ #define GPIO_MODE1_SET (GPIO_base+0x01a0+0x04)
+ #define GPIO_MODE2_SET (GPIO_base+0x01b0+0x04)
+ #define GPIO_MODE3_SET (GPIO_base+0x01c0+0x04)
+ #define GPIO_MODE4_SET (GPIO_base+0x01d0+0x04)
+ #define GPIO_MODE_SET(_no) (GPIO_MODE1_SET+(0x10*(_no)))
+ #define GPIO_DIR_SET(_no) (GPIO_DIR1_SET+(0x10*(_no)))
+ #define GPIO_DOUT_SET(_no) (GPIO_DOUT1_SET+(0x10*(_no)))
+ #define GPIO_PULLEN_SET(_no) (GPIO_PULLEN1_SET+(0x10*(_no)))
+
+ #define GPIO_DIR1_CLR (GPIO_base+0x0000+0x08)
+ #define GPIO_DIR2_CLR (GPIO_base+0x0010+0x08)
+ #define GPIO_PULLEN1_CLR (GPIO_base+0x0050+0x08)
+ #define GPIO_PULLEN2_CLR (GPIO_base+0x0060+0x08)
+ #define GPIO_DOUT1_CLR (GPIO_base+0x00f0+0x08)
+ #define GPIO_DOUT2_CLR (GPIO_base+0x0100+0x08)
+ #define GPIO_MODE1_CLR (GPIO_base+0x01a0+0x08)
+ #define GPIO_MODE2_CLR (GPIO_base+0x01b0+0x08)
+ #define GPIO_MODE3_CLR (GPIO_base+0x01c0+0x08)
+ #define GPIO_MODE4_CLR (GPIO_base+0x01d0+0x08)
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE1_CLR+(0x10*(_no)))
+ #define GPIO_DIR_CLR(_no) (GPIO_DIR1_CLR+(0x10*(_no)))
+ #define GPIO_DOUT_CLR(_no) (GPIO_DOUT1_CLR+(0x10*(_no)))
+ #define GPIO_PULLEN_CLR(_no) (GPIO_PULLEN1_CLR+(0x10*(_no)))
+
+ #define GPIO_MODE(_no) (GPIO_MODE1+(0x10*(_no)))
+ #define GPIO_DOUT(_no) (GPIO_DOUT1+(0x10*(_no)))
+ #define GPIO_DIR(_no) (GPIO_DIR1+(0x10*(_no)))
+ #define GPIO_DIN(_no) (GPIO_DIN1+(0x10*(_no)))
+#endif /*DRV_GPIO_REG_AS_6268T*/
+
+#if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6270A) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DIR1 (GPIO_base+0x0000)
+ #define GPIO_DIR2 (GPIO_base+0x0040)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_DIR3 (GPIO_base+0x0080)
+ #define GPIO_DIR4 (GPIO_base+0x00c0)
+ #define GPIO_DIR5 (GPIO_base+0x0100)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DIR6 (GPIO_base+0x0140)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DIR7 (GPIO_base+0x0180)
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_PULLEN1 (GPIO_base+0x0200)
+ #define GPIO_PULLEN2 (GPIO_base+0x0240)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_PULLEN3 (GPIO_base+0x0280)
+ #define GPIO_PULLEN4 (GPIO_base+0x02c0)
+ #define GPIO_PULLEN5 (GPIO_base+0x0300)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_PULLEN6 (GPIO_base+0x0340)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_PULLEN7 (GPIO_base+0x0380)
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_PULLSEL1 (GPIO_base+0x0400)
+ #define GPIO_PULLSEL2 (GPIO_base+0x0440)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_PULLSEL3 (GPIO_base+0x0480)
+ #define GPIO_PULLSEL4 (GPIO_base+0x04c0)
+ #define GPIO_PULLSEL5 (GPIO_base+0x0500)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_PULLSEL6 (GPIO_base+0x0540)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_PULLSEL7 (GPIO_base+0x0580)
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_DINV1 (GPIO_base+0x0600)
+ #define GPIO_DINV2 (GPIO_base+0x0640)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_DINV3 (GPIO_base+0x0680)
+ #define GPIO_DINV4 (GPIO_base+0x06c0)
+ #define GPIO_DINV5 (GPIO_base+0x0700)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DINV6 (GPIO_base+0x0740)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DINV7 (GPIO_base+0x0780)
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_DOUT1 (GPIO_base+0x0800)
+ #define GPIO_DOUT2 (GPIO_base+0x0840)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_DOUT3 (GPIO_base+0x0880)
+ #define GPIO_DOUT4 (GPIO_base+0x08c0)
+ #define GPIO_DOUT5 (GPIO_base+0x0900)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DOUT6 (GPIO_base+0x0940)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DOUT7 (GPIO_base+0x0980)
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_DIN1 (GPIO_base+0x0a00)
+ #define GPIO_DIN2 (GPIO_base+0x0a40)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_DIN3 (GPIO_base+0x0a80)
+ #define GPIO_DIN4 (GPIO_base+0x0ac0)
+ #define GPIO_DIN5 (GPIO_base+0x0b00)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DIN6 (GPIO_base+0x0b40)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DIN7 (GPIO_base+0x0b80)
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #if defined(MT6276_S01)
+ #define GPIO_MODE0 (GPIO_base+0x1000)
+ #define GPIO_MODE1 (GPIO_base+0x1100)
+ #define GPIO_MODE2 (GPIO_base+0x1200)
+ #define GPIO_MODE3 (GPIO_base+0x1300)
+ #define GPIO_MODE4 (GPIO_base+0x1400)
+ #define GPIO_MODE5 (GPIO_base+0x1500)
+ #define GPIO_MODE6 (GPIO_base+0x1600)
+ #define GPIO_MODE7 (GPIO_base+0x1700)
+ #define GPIO_MODE8 (GPIO_base+0x1800)
+ #define GPIO_MODE9 (GPIO_base+0x1900)
+ #define GPIO_MODEA (GPIO_base+0x1A00)
+ #define GPIO_MODEB (GPIO_base+0x1B00)
+ #define GPIO_MODEC (GPIO_base+0x1C00)
+ #define GPIO_MODED (GPIO_base+0x1D00)
+ #define GPIO_MODEE (GPIO_base+0x1E00)
+ #define GPIO_MODEF (GPIO_base+0x1F00)
+ #define GPIO_MODE10 (GPIO_base+0x2000)
+ #define GPIO_MODE11 (GPIO_base+0x2100)
+ #define GPIO_MODE12 (GPIO_base+0x2200)
+ #define GPIO_MODE13 (GPIO_base+0x2300)
+ #define GPIO_MODE14 (GPIO_base+0x2400)
+ #define GPIO_MODE15 (GPIO_base+0x2500)
+ #define GPIO_MODE16 (GPIO_base+0x2600)
+ #else //define(MT6276_S01)
+ #define GPIO_MODE1 (GPIO_base+0x1000)
+ #define GPIO_MODE2 (GPIO_base+0x1100)
+ #define GPIO_MODE3 (GPIO_base+0x1200)
+ #define GPIO_MODE4 (GPIO_base+0x1300)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_MODE5 (GPIO_base+0x1400)
+ #define GPIO_MODE6 (GPIO_base+0x1500)
+ #define GPIO_MODE7 (GPIO_base+0x1600)
+ #define GPIO_MODE8 (GPIO_base+0x1700)
+ #define GPIO_MODE9 (GPIO_base+0x1800)
+ #define GPIO_MODEA (GPIO_base+0x1900)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_MODEB (GPIO_base+0x1a00)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_MODEC (GPIO_base+0x1b00)
+ #define GPIO_MODED (GPIO_base+0x1c00)
+ #if defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_MODEE (GPIO_base+0x1d00)
+ #endif //defined(DRV_GPIO_REG_AS_6276)
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #endif //define(MT6276_S01)
+ #define CLKO_MODE1 (GPIO_base+0x3000)
+ #define CLKO_MODE2 (GPIO_base+0x3100)
+ #define CLKO_MODE3 (GPIO_base+0x3200)
+ #define CLKO_MODE4 (GPIO_base+0x3300)
+ #define CLKO_MODE5 (GPIO_base+0x3400)
+#if !defined(DRV_GPIO_REG_AS_6270A)
+ #define CLKO_MODE6 (GPIO_base+0x3500)
+#if !defined(DRV_GPIO_REG_AS_6268A) && !defined(DRV_GPIO_REG_AS_6268) && !defined(DRV_GPIO_REG_AS_6276)
+ #define CLKO_MODE7 (GPIO_base+0x3600)
+ #define CLKO_MODE8 (GPIO_base+0x3700)
+ #if defined(DRV_GPIO_REG_AS_6235)
+ #define CLKO_MODE9 (GPIO_base+0x3800)
+ #define CLKO_MODEA (GPIO_base+0x3900)
+ #endif /* DRV_GPIO_REG_AS_6235 */
+ #if defined(DRV_GPIO_REG_AS_6238)
+ #define GPIO_TM (GPIO_base+0x4000)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+#endif /* !defined(DRV_GPIO_REG_AS_6268A) */
+#endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_DINV_ADRS(n) (GPIO_DINV1+0x40*(n))
+
+ #define GPIO_DIR1_SET (GPIO_base+0x0000+0x04)
+ #define GPIO_DIR2_SET (GPIO_base+0x0040+0x04)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_DIR3_SET (GPIO_base+0x0080+0x04)
+ #define GPIO_DIR4_SET (GPIO_base+0x00c0+0x04)
+ #define GPIO_DIR5_SET (GPIO_base+0x0100+0x04)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DIR6_SET (GPIO_base+0x0140+0x04)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DIR7_SET (GPIO_base+0x0180+0x04)
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_PULLEN1_SET (GPIO_base+0x0200+0x04)
+ #define GPIO_PULLEN2_SET (GPIO_base+0x0240+0x04)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_PULLEN3_SET (GPIO_base+0x0280+0x04)
+ #define GPIO_PULLEN4_SET (GPIO_base+0x02c0+0x04)
+ #define GPIO_PULLEN5_SET (GPIO_base+0x0300+0x04)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_PULLEN6_SET (GPIO_base+0x0340+0x04)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_PULLEN7_SET (GPIO_base+0x0380+0x04)
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_PULLSEL1_SET (GPIO_base+0x0400+0x04)
+ #define GPIO_PULLSEL2_SET (GPIO_base+0x0440+0x04)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_PULLSEL3_SET (GPIO_base+0x0480+0x04)
+ #define GPIO_PULLSEL4_SET (GPIO_base+0x04c0+0x04)
+ #define GPIO_PULLSEL5_SET (GPIO_base+0x0500+0x04)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_PULLSEL6_SET (GPIO_base+0x0540+0x04)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_PULLSEL7_SET (GPIO_base+0x0580+0x04)
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_DOUT1_SET (GPIO_base+0x0800+0x04)
+ #define GPIO_DOUT2_SET (GPIO_base+0x0840+0x04)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_DOUT3_SET (GPIO_base+0x0880+0x04)
+ #define GPIO_DOUT4_SET (GPIO_base+0x08c0+0x04)
+ #define GPIO_DOUT5_SET (GPIO_base+0x0900+0x04)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DOUT6_SET (GPIO_base+0x0940+0x04)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DOUT7_SET (GPIO_base+0x0980+0x04)
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #if defined(MT6276_S01)
+ #define GPIO_MODE0_SET (GPIO_base+0x1000+0x04)
+ #define GPIO_MODE1_SET (GPIO_base+0x1100+0x04)
+ #define GPIO_MODE2_SET (GPIO_base+0x1200+0x04)
+ #define GPIO_MODE3_SET (GPIO_base+0x1300+0x04)
+ #define GPIO_MODE4_SET (GPIO_base+0x1400+0x04)
+ #define GPIO_MODE5_SET (GPIO_base+0x1500+0x04)
+ #define GPIO_MODE6_SET (GPIO_base+0x1600+0x04)
+ #define GPIO_MODE7_SET (GPIO_base+0x1700+0x04)
+ #define GPIO_MODE8_SET (GPIO_base+0x1800+0x04)
+ #define GPIO_MODE9_SET (GPIO_base+0x1900+0x04)
+ #define GPIO_MODEA_SET (GPIO_base+0x1A00+0x04)
+ #define GPIO_MODEB_SET (GPIO_base+0x1B00+0x04)
+ #define GPIO_MODEC_SET (GPIO_base+0x1C00+0x04)
+ #define GPIO_MODED_SET (GPIO_base+0x1D00+0x04)
+ #define GPIO_MODEE_SET (GPIO_base+0x1E00+0x04)
+ #define GPIO_MODEF_SET (GPIO_base+0x1F00+0x04)
+ #define GPIO_MODE10_SET (GPIO_base+0x2000+0x04)
+ #define GPIO_MODE11_SET (GPIO_base+0x2100+0x04)
+ #define GPIO_MODE12_SET (GPIO_base+0x2200+0x04)
+ #define GPIO_MODE13_SET (GPIO_base+0x2300+0x04)
+ #define GPIO_MODE14_SET (GPIO_base+0x2400+0x04)
+ #define GPIO_MODE15_SET (GPIO_base+0x2500+0x04)
+ #define GPIO_MODE16_SET (GPIO_base+0x2600+0x04)
+ #else
+ #define GPIO_MODE1_SET (GPIO_base+0x1000+0x04)
+ #define GPIO_MODE2_SET (GPIO_base+0x1100+0x04)
+ #define GPIO_MODE3_SET (GPIO_base+0x1200+0x04)
+ #define GPIO_MODE4_SET (GPIO_base+0x1300+0x04)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_MODE5_SET (GPIO_base+0x1400+0x04)
+ #define GPIO_MODE6_SET (GPIO_base+0x1500+0x04)
+ #define GPIO_MODE7_SET (GPIO_base+0x1600+0x04)
+ #define GPIO_MODE8_SET (GPIO_base+0x1700+0x04)
+ #define GPIO_MODE9_SET (GPIO_base+0x1800+0x04)
+ #define GPIO_MODEA_SET (GPIO_base+0x1900+0x04)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_MODEB_SET (GPIO_base+0x1a00+0x04)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_MODEC_SET (GPIO_base+0x1b00+0x04)
+ #define GPIO_MODED_SET (GPIO_base+0x1c00+0x04)
+ #if defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_MODEE_SET (GPIO_base+0x1d00+0x04)
+ #endif
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #endif //define(MT6276_S01)
+
+ #if defined(MT6276_S01)
+ #define GPIO_MODE_SET(_no) (GPIO_MODE0_SET+(0x100*(_no)))
+ #else
+ #define GPIO_MODE_SET(_no) (GPIO_MODE1_SET+(0x100*(_no)))
+ #endif
+ #define GPIO_DIR_SET(_no) (GPIO_DIR1_SET+(0x40*(_no)))
+ #define GPIO_DOUT_SET(_no) (GPIO_DOUT1_SET+(0x40*(_no)))
+ #define GPIO_PULLEN_SET(_no) (GPIO_PULLEN1_SET+(0x40*(_no)))
+ #define GPIO_PULLSEL_SET(_no) (GPIO_PULLSEL1_SET+(0x40*(_no)))
+
+ #define GPIO_DIR1_CLR (GPIO_base+0x0000+0x08)
+ #define GPIO_DIR2_CLR (GPIO_base+0x0040+0x08)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_DIR3_CLR (GPIO_base+0x0080+0x08)
+ #define GPIO_DIR4_CLR (GPIO_base+0x00c0+0x08)
+ #define GPIO_DIR5_CLR (GPIO_base+0x0100+0x08)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DIR6_CLR (GPIO_base+0x0140+0x08)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DIR7_CLR (GPIO_base+0x0180+0x08)
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_PULLEN1_CLR (GPIO_base+0x0200+0x08)
+ #define GPIO_PULLEN2_CLR (GPIO_base+0x0240+0x08)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_PULLEN3_CLR (GPIO_base+0x0280+0x08)
+ #define GPIO_PULLEN4_CLR (GPIO_base+0x02c0+0x08)
+ #define GPIO_PULLEN5_CLR (GPIO_base+0x0300+0x08)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_PULLEN6_CLR (GPIO_base+0x0340+0x08)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_PULLEN7_CLR (GPIO_base+0x0380+0x08)
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_PULLSEL1_CLR (GPIO_base+0x0400+0x08)
+ #define GPIO_PULLSEL2_CLR (GPIO_base+0x0440+0x08)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_PULLSEL3_CLR (GPIO_base+0x0480+0x08)
+ #define GPIO_PULLSEL4_CLR (GPIO_base+0x04c0+0x08)
+ #define GPIO_PULLSEL5_CLR (GPIO_base+0x0500+0x08)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_PULLSEL6_CLR (GPIO_base+0x0540+0x08)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_PULLSEL7_CLR (GPIO_base+0x0580+0x08)
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_DOUT1_CLR (GPIO_base+0x0800+0x08)
+ #define GPIO_DOUT2_CLR (GPIO_base+0x0840+0x08)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_DOUT3_CLR (GPIO_base+0x0880+0x08)
+ #define GPIO_DOUT4_CLR (GPIO_base+0x08c0+0x08)
+ #define GPIO_DOUT5_CLR (GPIO_base+0x0900+0x08)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DOUT6_CLR (GPIO_base+0x0940+0x08)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_DOUT7_CLR (GPIO_base+0x0980+0x08)
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #if defined(MT6276_S01)
+ #define GPIO_MODE0_CLR (GPIO_base+0x1000+0x08)
+ #define GPIO_MODE1_CLR (GPIO_base+0x1100+0x08)
+ #define GPIO_MODE2_CLR (GPIO_base+0x1200+0x08)
+ #define GPIO_MODE3_CLR (GPIO_base+0x1300+0x08)
+ #define GPIO_MODE4_CLR (GPIO_base+0x1400+0x08)
+ #define GPIO_MODE5_CLR (GPIO_base+0x1500+0x08)
+ #define GPIO_MODE6_CLR (GPIO_base+0x1600+0x08)
+ #define GPIO_MODE7_CLR (GPIO_base+0x1700+0x08)
+ #define GPIO_MODE8_CLR (GPIO_base+0x1800+0x08)
+ #define GPIO_MODE9_CLR (GPIO_base+0x1900+0x08)
+ #define GPIO_MODEA_CLR (GPIO_base+0x1A00+0x08)
+ #define GPIO_MODEB_CLR (GPIO_base+0x1B00+0x08)
+ #define GPIO_MODEC_CLR (GPIO_base+0x1C00+0x08)
+ #define GPIO_MODED_CLR (GPIO_base+0x1D00+0x08)
+ #define GPIO_MODEE_CLR (GPIO_base+0x1E00+0x08)
+ #define GPIO_MODEF_CLR (GPIO_base+0x1F00+0x08)
+ #define GPIO_MODE10_CLR (GPIO_base+0x2000+0x08)
+ #define GPIO_MODE11_CLR (GPIO_base+0x2100+0x08)
+ #define GPIO_MODE12_CLR (GPIO_base+0x2200+0x08)
+ #define GPIO_MODE13_CLR (GPIO_base+0x2300+0x08)
+ #define GPIO_MODE14_CLR (GPIO_base+0x2400+0x08)
+ #define GPIO_MODE15_CLR (GPIO_base+0x2500+0x08)
+ #define GPIO_MODE16_CLR (GPIO_base+0x2600+0x08)
+ #else
+ #define GPIO_MODE1_CLR (GPIO_base+0x1000+0x08)
+ #define GPIO_MODE2_CLR (GPIO_base+0x1100+0x08)
+ #define GPIO_MODE3_CLR (GPIO_base+0x1200+0x08)
+ #define GPIO_MODE4_CLR (GPIO_base+0x1300+0x08)
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+ #define GPIO_MODE5_CLR (GPIO_base+0x1400+0x08)
+ #define GPIO_MODE6_CLR (GPIO_base+0x1500+0x08)
+ #define GPIO_MODE7_CLR (GPIO_base+0x1600+0x08)
+ #define GPIO_MODE8_CLR (GPIO_base+0x1700+0x08)
+ #define GPIO_MODE9_CLR (GPIO_base+0x1800+0x08)
+ #define GPIO_MODEA_CLR (GPIO_base+0x1900+0x08)
+ #if defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_MODEB_CLR (GPIO_base+0x1a00+0x08)
+ #endif /* DRV_GPIO_REG_AS_6238 */
+ #if defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_MODEC_CLR (GPIO_base+0x1b00+0x08)
+ #define GPIO_MODED_CLR (GPIO_base+0x1c00+0x08)
+ #if defined(DRV_GPIO_REG_AS_6276)
+ #define GPIO_MODEE_CLR (GPIO_base+0x1d00+0x08)
+ #endif
+ #endif /* DRV_GPIO_REG_AS_6268A */
+ #endif //!defined(DRV_GPIO_REG_AS_6270A)
+ #endif //define(MT6276_S01)
+
+ #if defined(MT6276_S01)
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE0_CLR+(0x100*(_no)))
+ #define GPIO_MODE(_no) (GPIO_MODE0+(0x100*(_no)))
+ #else
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE1_CLR+(0x100*(_no)))
+ #define GPIO_MODE(_no) (GPIO_MODE1+(0x100*(_no)))
+ #endif
+ #define GPIO_DIR_CLR(_no) (GPIO_DIR1_CLR+(0x40*(_no)))
+ #define GPIO_DOUT_CLR(_no) (GPIO_DOUT1_CLR+(0x40*(_no)))
+ #define GPIO_PULLEN_CLR(_no) (GPIO_PULLEN1_CLR+(0x40*(_no)))
+ #define GPIO_PULLSEL_CLR(_no) (GPIO_PULLSEL1_CLR+(0x40*(_no)))
+
+
+ #define GPIO_DOUT(_no) (GPIO_DOUT1+(0x40*(_no)))
+ #define GPIO_DIR(_no) (GPIO_DIR1+(0x40*(_no)))
+ #define GPIO_DIN(_no) (GPIO_DIN1+(0x40*(_no)))
+ #define GPIO_PULLEN(_no) (GPIO_PULLEN1+(0x40*(_no)))
+ #define GPIO_PULLSEL(_no) (GPIO_PULLSEL1+(0x40*(_no)))
+ #define CLKO_MODE(_no) (CLKO_MODE1+(0x100*(_no)))
+ #if defined(DRV_GPIO_REG_AS_6238)
+ #define CLKO_NUM 8
+ #elif defined(DRV_GPIO_REG_AS_6235)
+ #define CLKO_NUM 10
+ #elif defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6270A) || defined(DRV_GPIO_REG_AS_6276)
+ #define CLKO_NUM 6
+ #endif
+#endif /*defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235) || defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6270A) || defined(DRV_GPIO_REG_AS_6276)*/
+
+#if defined(DRV_GPIO_REG_AS_TK6516)
+ #define GPIO_DIR1 (GPIO_base+0x0000)
+ #define GPIO_PULLEN1 (GPIO_base+0x0100)
+ #define GPIO_PULLSEL1 (GPIO_base+0x0200)
+ #define GPIO_DINV1 (GPIO_base+0x0300)
+ #define GPIO_DOUT1 (GPIO_base+0x0400)
+ #define GPIO_DIN1 (GPIO_base+0x0500)
+ #define GPIO_MODE1 (GPIO_base+0x0600)
+ #define GPIO_DINV_ADRS(n) (GPIO_DINV1+0x10*(n))
+
+ #define GPIO_DIR1_SET (GPIO_base+0x0000+0x04)
+ #define GPIO_PULLEN1_SET (GPIO_base+0x0100+0x04)
+ #define GPIO_PULLSEL1_SET (GPIO_base+0x0200+0x04)
+ #define GPIO_DOUT1_SET (GPIO_base+0x0400+0x04)
+ #define GPIO_MODE1_SET (GPIO_base+0x0600+0x04)
+ #define GPIO_MODE_SET(_no) (GPIO_MODE1_SET+(0x10*(_no)))
+ #define GPIO_DIR_SET(_no) (GPIO_DIR1_SET+(0x10*(_no)))
+ #define GPIO_DOUT_SET(_no) (GPIO_DOUT1_SET+(0x10*(_no)))
+ #define GPIO_PULLEN_SET(_no) (GPIO_PULLEN1_SET+(0x10*(_no)))
+ #define GPIO_PULLSEL_SET(_no) (GPIO_PULLSEL1_SET+(0x40*(_no)))
+
+ #define GPIO_DIR1_CLR (GPIO_base+0x0000+0x08)
+ #define GPIO_PULLEN1_CLR (GPIO_base+0x0100+0x08)
+ #define GPIO_PULLSEL1_CLR (GPIO_base+0x0200+0x08)
+ #define GPIO_DOUT1_CLR (GPIO_base+0x0400+0x08)
+ #define GPIO_MODE1_CLR (GPIO_base+0x0600+0x08)
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE1_CLR+(0x10*(_no)))
+ #define GPIO_DIR_CLR(_no) (GPIO_DIR1_CLR+(0x10*(_no)))
+ #define GPIO_DOUT_CLR(_no) (GPIO_DOUT1_CLR+(0x10*(_no)))
+ #define GPIO_PULLEN_CLR(_no) (GPIO_PULLEN1_CLR+(0x10*(_no)))
+ #define GPIO_PULLSEL_CLR(_no) (GPIO_PULLSEL1_CLR+(0x40*(_no)))
+
+ #define GPIO_MODE(_no) (GPIO_MODE1+(0x10*(_no)))
+ #define GPIO_DOUT(_no) (GPIO_DOUT1+(0x10*(_no)))
+ #define GPIO_DIR(_no) (GPIO_DIR1+(0x10*(_no)))
+ #define GPIO_DIN(_no) (GPIO_DIN1+(0x10*(_no)))
+ #define GPIO_PULLEN(_no) (GPIO_PULLEN1+(0x40*(_no)))
+ #define GPIO_PULLSEL(_no) (GPIO_PULLSEL1+(0x40*(_no)))
+#endif /*DRV_GPIO_REG_AS_TK6516*/
+
+#if defined(DRV_GPIO_REG_AS_6253T)
+ #define GPIO_DIR1 (GPIO_base+0x0000)
+ #define GPIO_DIR2 (GPIO_base+0x0010)
+ #define GPIO_DIR3 (GPIO_base+0x0020)
+ #define GPIO_DIR4 (GPIO_base+0x0030)
+ #define GPIO_DIR5 (GPIO_base+0x0040)
+ #define GPIO_DIR6 (GPIO_base+0x0380)
+ #define GPIO_PULLEN1 (GPIO_base+0x0050)
+ #define GPIO_PULLEN2 (GPIO_base+0x0060)
+ #define GPIO_PULLEN3 (GPIO_base+0x0070)
+ #define GPIO_PULLEN4 (GPIO_base+0x0080)
+ #define GPIO_PULLEN5 (GPIO_base+0x0090)
+ #define GPIO_PULLEN6 (GPIO_base+0x0390)
+ #define GPIO_DINV1 (GPIO_base+0x00a0)
+ #define GPIO_DINV2 (GPIO_base+0x00b0)
+ #define GPIO_DINV3 (GPIO_base+0x00c0)
+ #define GPIO_DINV4 (GPIO_base+0x00d0)
+ #define GPIO_DINV5 (GPIO_base+0x00e0)
+ #define GPIO_DINV6 (GPIO_base+0x03a0)
+ #define GPIO_DOUT1 (GPIO_base+0x00f0)
+ #define GPIO_DOUT2 (GPIO_base+0x0100)
+ #define GPIO_DOUT3 (GPIO_base+0x0110)
+ #define GPIO_DOUT4 (GPIO_base+0x0120)
+ #define GPIO_DOUT5 (GPIO_base+0x0130)
+ #define GPIO_DOUT6 (GPIO_base+0x03b0)
+ #define GPIO_DIN1 (GPIO_base+0x0140)
+ #define GPIO_DIN2 (GPIO_base+0x0150)
+ #define GPIO_DIN3 (GPIO_base+0x0160)
+ #define GPIO_DIN4 (GPIO_base+0x0170)
+ #define GPIO_DIN5 (GPIO_base+0x0180)
+ #define GPIO_DIN6 (GPIO_base+0x03c0)
+ #define GPIO_MODE1 (GPIO_base+0x0190)
+ #define GPIO_MODE2 (GPIO_base+0x01a0)
+ #define GPIO_MODE3 (GPIO_base+0x01b0)
+ #define GPIO_MODE4 (GPIO_base+0x01c0)
+ #define GPIO_MODE5 (GPIO_base+0x01d0)
+ #define GPIO_MODE6 (GPIO_base+0x01e0)
+ #define GPIO_MODE7 (GPIO_base+0x01f0)
+ #define GPIO_MODE8 (GPIO_base+0x0200)
+ #define GPIO_MODE9 (GPIO_base+0x0210)
+ #define GPIO_MODEA (GPIO_base+0x0220)
+ #define GPIO_MODEB (GPIO_base+0x03d0)
+ #define GPIO_BANK (GPIO_base+0x0230)
+ #define CLKO_MODE1 (GPIO_base+0x0300)
+ #define CLKO_MODE2 (GPIO_base+0x0310)
+ #define CLKO_MODE3 (GPIO_base+0x0320)
+ #define CLKO_MODE4 (GPIO_base+0x0330)
+ #define CLKO_MODE5 (GPIO_base+0x0340)
+ #define CLKO_MODE6 (GPIO_base+0x0350)
+ #define CLKO_MODE7 (GPIO_base+0x0360)
+ #define GPIO_DINV_ADRS(n) (((n)<5)?(GPIO_DINV1+0x10*(n)):GPIO_DINV6)
+
+ #define GPIO_PULLSEL1 (GPIO_base+0x0240)
+ #define GPIO_PULLSEL2 (GPIO_base+0x0250)
+ #define GPIO_PULLSEL3 (GPIO_base+0x0260)
+ #define GPIO_PULLSEL4 (GPIO_base+0x0270)
+ #define GPIO_PULLSEL5 (GPIO_base+0x0280)
+ #define GPIO_PULLSEL6 (GPIO_base+0x03e0)
+ #define GPIO_TM (GPIO_base+0x0370)
+
+ #define GPIO_DIR1_SET (GPIO_base+0x0000+0x04)
+ #define GPIO_DIR2_SET (GPIO_base+0x0010+0x04)
+ #define GPIO_DIR3_SET (GPIO_base+0x0020+0x04)
+ #define GPIO_DIR4_SET (GPIO_base+0x0030+0x04)
+ #define GPIO_DIR5_SET (GPIO_base+0x0040+0x04)
+ #define GPIO_DIR6_SET (GPIO_base+0x0380+0x04)
+ #define GPIO_PULLEN1_SET (GPIO_base+0x0050+0x04)
+ #define GPIO_PULLEN2_SET (GPIO_base+0x0060+0x04)
+ #define GPIO_PULLEN3_SET (GPIO_base+0x0070+0x04)
+ #define GPIO_PULLEN4_SET (GPIO_base+0x0080+0x04)
+ #define GPIO_PULLEN5_SET (GPIO_base+0x0090+0x04)
+ #define GPIO_PULLEN6_SET (GPIO_base+0x0390+0x04)
+ #define GPIO_DINV1_SET (GPIO_base+0x00a0+0x04)
+ #define GPIO_DINV2_SET (GPIO_base+0x00b0+0x04)
+ #define GPIO_DINV3_SET (GPIO_base+0x00c0+0x04)
+ #define GPIO_DINV4_SET (GPIO_base+0x00d0+0x04)
+ #define GPIO_DINV5_SET (GPIO_base+0x00e0+0x04)
+ #define GPIO_DINV6_SET (GPIO_base+0x03a0+0x04)
+ #define GPIO_DOUT1_SET (GPIO_base+0x00f0+0x04)
+ #define GPIO_DOUT2_SET (GPIO_base+0x0100+0x04)
+ #define GPIO_DOUT3_SET (GPIO_base+0x0110+0x04)
+ #define GPIO_DOUT4_SET (GPIO_base+0x0120+0x04)
+ #define GPIO_DOUT5_SET (GPIO_base+0x0130+0x04)
+ #define GPIO_DOUT6_SET (GPIO_base+0x03b0+0x04)
+ #define GPIO_DIN1_SET (GPIO_base+0x0140+0x04)
+ #define GPIO_DIN2_SET (GPIO_base+0x0150+0x04)
+ #define GPIO_DIN3_SET (GPIO_base+0x0160+0x04)
+ #define GPIO_DIN4_SET (GPIO_base+0x0170+0x04)
+ #define GPIO_DIN5_SET (GPIO_base+0x0180+0x04)
+ #define GPIO_DIN6_SET (GPIO_base+0x03c0+0x04)
+ #define GPIO_MODE1_SET (GPIO_base+0x0190+0x04)
+ #define GPIO_MODE2_SET (GPIO_base+0x01a0+0x04)
+ #define GPIO_MODE3_SET (GPIO_base+0x01b0+0x04)
+ #define GPIO_MODE4_SET (GPIO_base+0x01c0+0x04)
+ #define GPIO_MODE5_SET (GPIO_base+0x01d0+0x04)
+ #define GPIO_MODE6_SET (GPIO_base+0x01e0+0x04)
+ #define GPIO_MODE7_SET (GPIO_base+0x01f0+0x04)
+ #define GPIO_MODE8_SET (GPIO_base+0x0200+0x04)
+ #define GPIO_MODE9_SET (GPIO_base+0x0210+0x04)
+ #define GPIO_MODEA_SET (GPIO_base+0x0220+0x04)
+ #define GPIO_MODEB_SET (GPIO_base+0x03d0+0x04)
+ #define GPIO_BANK_SET (GPIO_base+0x0230+0x04)
+ #define CLKO_MODE1_SET (GPIO_base+0x0300+0x04)
+ #define CLKO_MODE2_SET (GPIO_base+0x0310+0x04)
+ #define CLKO_MODE3_SET (GPIO_base+0x0320+0x04)
+ #define CLKO_MODE4_SET (GPIO_base+0x0330+0x04)
+ #define CLKO_MODE5_SET (GPIO_base+0x0340+0x04)
+ #define CLKO_MODE6_SET (GPIO_base+0x0350+0x04)
+ #define CLKO_MODE7_SET (GPIO_base+0x0360+0x04)
+
+ #define GPIO_PULLSEL1_SET (GPIO_base+0x0240+0x04)
+ #define GPIO_PULLSEL2_SET (GPIO_base+0x0250+0x04)
+ #define GPIO_PULLSEL3_SET (GPIO_base+0x0260+0x04)
+ #define GPIO_PULLSEL4_SET (GPIO_base+0x0270+0x04)
+ #define GPIO_PULLSEL5_SET (GPIO_base+0x0280+0x04)
+ #define GPIO_PULLSEL6_SET (GPIO_base+0x03e0+0x04)
+ #define GPIO_TM_SET (GPIO_base+0x0370+0x04)
+
+ #define GPIO_MODE_SET(_no) (((_no)<10)?(GPIO_MODE1_SET+(0x10*(_no))):(GPIO_MODEB_SET))
+ #define GPIO_DIR_SET(_no) (((_no)<5)?(GPIO_DIR1_SET+(0x10*(_no))):(GPIO_DIR6_SET))
+ #define GPIO_DOUT_SET(_no) (((_no)<5)?(GPIO_DOUT1_SET+(0x10*(_no))):(GPIO_DOUT6_SET))
+ #define GPIO_PULLEN_SET(_no) (((_no)<5)?(GPIO_PULLEN1_SET+(0x10*(_no))):(GPIO_PULLEN6_SET))
+ #define GPIO_PULLSEL_SET(_no) (((_no)<5)?(GPIO_PULLSEL1_SET+(0x10*(_no))):(GPIO_PULLSEL6_SET))
+
+ #define GPIO_DIR1_CLR (GPIO_base+0x0000+0x08)
+ #define GPIO_DIR2_CLR (GPIO_base+0x0010+0x08)
+ #define GPIO_DIR3_CLR (GPIO_base+0x0020+0x08)
+ #define GPIO_DIR4_CLR (GPIO_base+0x0030+0x08)
+ #define GPIO_DIR5_CLR (GPIO_base+0x0040+0x08)
+ #define GPIO_DIR6_CLR (GPIO_base+0x0380+0x08)
+ #define GPIO_PULLEN1_CLR (GPIO_base+0x0050+0x08)
+ #define GPIO_PULLEN2_CLR (GPIO_base+0x0060+0x08)
+ #define GPIO_PULLEN3_CLR (GPIO_base+0x0070+0x08)
+ #define GPIO_PULLEN4_CLR (GPIO_base+0x0080+0x08)
+ #define GPIO_PULLEN5_CLR (GPIO_base+0x0090+0x08)
+ #define GPIO_PULLEN6_CLR (GPIO_base+0x0390+0x08)
+ #define GPIO_DINV1_CLR (GPIO_base+0x00a0+0x08)
+ #define GPIO_DINV2_CLR (GPIO_base+0x00b0+0x08)
+ #define GPIO_DINV3_CLR (GPIO_base+0x00c0+0x08)
+ #define GPIO_DINV4_CLR (GPIO_base+0x00d0+0x08)
+ #define GPIO_DINV5_CLR (GPIO_base+0x00e0+0x08)
+ #define GPIO_DINV6_CLR (GPIO_base+0x03a0+0x08)
+ #define GPIO_DOUT1_CLR (GPIO_base+0x00f0+0x08)
+ #define GPIO_DOUT2_CLR (GPIO_base+0x0100+0x08)
+ #define GPIO_DOUT3_CLR (GPIO_base+0x0110+0x08)
+ #define GPIO_DOUT4_CLR (GPIO_base+0x0120+0x08)
+ #define GPIO_DOUT5_CLR (GPIO_base+0x0130+0x08)
+ #define GPIO_DOUT6_CLR (GPIO_base+0x03b0+0x08)
+ #define GPIO_DIN1_CLR (GPIO_base+0x0140+0x08)
+ #define GPIO_DIN2_CLR (GPIO_base+0x0150+0x08)
+ #define GPIO_DIN3_CLR (GPIO_base+0x0160+0x08)
+ #define GPIO_DIN4_CLR (GPIO_base+0x0170+0x08)
+ #define GPIO_DIN5_CLR (GPIO_base+0x0180+0x08)
+ #define GPIO_DIN6_CLR (GPIO_base+0x03c0+0x08)
+ #define GPIO_MODE1_CLR (GPIO_base+0x0190+0x08)
+ #define GPIO_MODE2_CLR (GPIO_base+0x01a0+0x08)
+ #define GPIO_MODE3_CLR (GPIO_base+0x01b0+0x08)
+ #define GPIO_MODE4_CLR (GPIO_base+0x01c0+0x08)
+ #define GPIO_MODE5_CLR (GPIO_base+0x01d0+0x08)
+ #define GPIO_MODE6_CLR (GPIO_base+0x01e0+0x08)
+ #define GPIO_MODE7_CLR (GPIO_base+0x01f0+0x08)
+ #define GPIO_MODE8_CLR (GPIO_base+0x0200+0x08)
+ #define GPIO_MODE9_CLR (GPIO_base+0x0210+0x08)
+ #define GPIO_MODEA_CLR (GPIO_base+0x0220+0x08)
+ #define GPIO_MODEB_CLR (GPIO_base+0x03d0+0x08)
+ #define GPIO_BANK_CLR (GPIO_base+0x0230+0x08)
+ #define CLKO_MODE1_CLR (GPIO_base+0x0300+0x08)
+ #define CLKO_MODE2_CLR (GPIO_base+0x0310+0x08)
+ #define CLKO_MODE3_CLR (GPIO_base+0x0320+0x08)
+ #define CLKO_MODE4_CLR (GPIO_base+0x0330+0x08)
+ #define CLKO_MODE5_CLR (GPIO_base+0x0340+0x08)
+ #define CLKO_MODE6_CLR (GPIO_base+0x0350+0x08)
+ #define CLKO_MODE7_CLR (GPIO_base+0x0360+0x08)
+
+ #define GPIO_PULLSEL1_CLR (GPIO_base+0x0240+0x08)
+ #define GPIO_PULLSEL2_CLR (GPIO_base+0x0250+0x08)
+ #define GPIO_PULLSEL3_CLR (GPIO_base+0x0260+0x08)
+ #define GPIO_PULLSEL4_CLR (GPIO_base+0x0270+0x08)
+ #define GPIO_PULLSEL5_CLR (GPIO_base+0x0280+0x08)
+ #define GPIO_PULLSEL6_CLR (GPIO_base+0x03e0+0x08)
+ #define GPIO_TM_CLR (GPIO_base+0x0370+0x08)
+
+ #define GPIO_MODE_CLR(_no) (((_no)<10)?(GPIO_MODE1_CLR+(0x10*(_no))):(GPIO_MODEB_CLR))
+ #define GPIO_DIR_CLR(_no) (((_no)<5)?(GPIO_DIR1_CLR+(0x10*(_no))):(GPIO_DIR6_CLR))
+ #define GPIO_DOUT_CLR(_no) (((_no)<5)?(GPIO_DOUT1_CLR+(0x10*(_no))):(GPIO_DOUT6_CLR))
+ #define GPIO_PULLEN_CLR(_no) (((_no)<5)?(GPIO_PULLEN1_CLR+(0x10*(_no))):(GPIO_PULLEN6_CLR))
+ #define GPIO_PULLSEL_CLR(_no) (((_no)<5)?(GPIO_PULLSEL1_CLR+(0x10*(_no))):(GPIO_PULLSEL6_CLR))
+
+ #define GPIO_MODE(_no) (((_no)<10)?(GPIO_MODE1+(0x10*(_no))):(GPIO_MODEB))
+ #define GPIO_DOUT(_no) (((_no)<5)?(GPIO_DOUT1+(0x10*(_no))):(GPIO_DOUT6))
+ #define GPIO_DIR(_no) (((_no)<5)?(GPIO_DIR1+(0x10*(_no))):(GPIO_DIR6))
+ #define GPIO_DIN(_no) (((_no)<5)?(GPIO_DIN1+(0x10*(_no))):(GPIO_DIN6))
+ #define GPIO_PULLEN(_no) (((_no)<5)?(GPIO_PULLEN1+(0x10*(_no))):(GPIO_PULLEN6))
+ #define GPIO_PULLSEL(_no) (((_no)<5)?(GPIO_PULLSEL1+(0x10*(_no))):(GPIO_PULLSEL6))
+ #define CLKO_MODE(_no) (CLKO_MODE1+(0x10*(_no)))
+
+ #define CLKO_NUM 7
+#endif /*DRV_GPIO_REG_AS_6253T*/
+
+#if defined(DRV_GPIO_REG_AS_6253E)
+ #define GPIO_DIR1 (GPIO_base+0x0000)
+ #define GPIO_DIR2 (GPIO_base+0x0010)
+ #define GPIO_DIR3 (GPIO_base+0x0020)
+ #define GPIO_DIR4 (GPIO_base+0x0030)
+ #define GPIO_PULLEN1 (GPIO_base+0x0050)
+ #define GPIO_PULLEN2 (GPIO_base+0x0060)
+ #define GPIO_PULLEN3 (GPIO_base+0x0070)
+ #define GPIO_PULLEN4 (GPIO_base+0x0080)
+ #define GPIO_DINV1 (GPIO_base+0x00a0)
+ #define GPIO_DINV2 (GPIO_base+0x00b0)
+ #define GPIO_DINV3 (GPIO_base+0x00c0)
+ #define GPIO_DINV4 (GPIO_base+0x00d0)
+ #define GPIO_DOUT1 (GPIO_base+0x00f0)
+ #define GPIO_DOUT2 (GPIO_base+0x0100)
+ #define GPIO_DOUT3 (GPIO_base+0x0110)
+ #define GPIO_DOUT4 (GPIO_base+0x0120)
+ #define GPIO_DIN1 (GPIO_base+0x0140)
+ #define GPIO_DIN2 (GPIO_base+0x0150)
+ #define GPIO_DIN3 (GPIO_base+0x0160)
+ #define GPIO_DIN4 (GPIO_base+0x0170)
+
+ #define GPIO_SPMODE (GPIO_base+0x0220)
+
+ #define GPIO_MODE1 (GPIO_base+0x0190)
+ #define GPIO_MODE2 (GPIO_base+0x01a0)
+ #define GPIO_MODE3 (GPIO_base+0x01b0)
+ #define GPIO_MODE4 (GPIO_base+0x01c0)
+ #define GPIO_MODE5 (GPIO_base+0x01d0)
+ #define GPIO_MODE6 (GPIO_base+0x01e0)
+ #define GPIO_MODE7 (GPIO_base+0x01f0)
+ #define GPIO_MODE8 (GPIO_base+0x0200)
+
+ #define GPIO_BANK (GPIO_base+0x0230)
+
+ #define CLKO_MODE1 (GPIO_base+0x0300)
+ #define CLKO_MODE2 (GPIO_base+0x0310)
+ #define CLKO_MODE3 (GPIO_base+0x0320)
+ #define CLKO_MODE4 (GPIO_base+0x0330)
+ #define CLKO_MODE5 (GPIO_base+0x0340)
+ #define CLKO_MODE6 (GPIO_base+0x0350)
+ #define CLKO_MODE7 (GPIO_base+0x0360)
+ #define GPIO_DINV_ADRS(n) (GPIO_DINV1+0x10*(n))
+
+ #define GPIO_PULLSEL1 (GPIO_base+0x0240)
+ #define GPIO_PULLSEL2 (GPIO_base+0x0250)
+ #define GPIO_PULLSEL3 (GPIO_base+0x0260)
+ #define GPIO_PULLSEL4 (GPIO_base+0x0270)
+
+ #define GPIO_TM (GPIO_base+0x0370)
+
+ #define GPIO_DIR1_SET (GPIO_DIR1+0x04)
+ #define GPIO_PULLEN1_SET (GPIO_PULLEN1+0x04)
+ #define GPIO_DOUT1_SET (GPIO_DOUT1+0x04)
+ #define GPIO_MODE1_SET (GPIO_MODE1+0x04)
+
+ #define GPIO_PULLSEL1_SET (GPIO_PULLSEL1+0x04)
+ #define GPIO_MODE_SET(_no) (GPIO_MODE1_SET+(0x10*(_no)))
+ #define GPIO_DIR_SET(_no) (GPIO_DIR1_SET+(0x10*(_no)))
+ #define GPIO_DOUT_SET(_no) (GPIO_DOUT1_SET+(0x10*(_no)))
+ #define GPIO_PULLEN_SET(_no) (GPIO_PULLEN1_SET+(0x10*(_no)))
+ #define GPIO_PULLSEL_SET(_no) (GPIO_PULLSEL1_SET+(0x10*(_no)))
+
+ #define GPIO_DIR1_CLR (GPIO_DIR1+0x08)
+ #define GPIO_PULLEN1_CLR (GPIO_PULLEN1+0x08)
+ #define GPIO_DOUT1_CLR (GPIO_DOUT1+0x08)
+ #define GPIO_MODE1_CLR (GPIO_MODE1+0x08)
+ #define GPIO_PULLSEL1_CLR (GPIO_PULLSEL1+0x08)
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE1_CLR+(0x10*(_no)))
+ #define GPIO_DIR_CLR(_no) (GPIO_DIR1_CLR+(0x10*(_no)))
+ #define GPIO_DOUT_CLR(_no) (GPIO_DOUT1_CLR+(0x10*(_no)))
+ #define GPIO_PULLEN_CLR(_no) (GPIO_PULLEN1_CLR+(0x10*(_no)))
+ #define GPIO_PULLSEL_CLR(_no) (GPIO_PULLSEL1_CLR+(0x10*(_no)))
+
+ #define GPIO_MODE(_no) (GPIO_MODE1+(0x10*(_no)))
+ #define GPIO_DOUT(_no) (GPIO_DOUT1+(0x10*(_no)))
+ #define GPIO_DIR(_no) (GPIO_DIR1+(0x10*(_no)))
+ #define GPIO_DIN(_no) (GPIO_DIN1+(0x10*(_no)))
+ #define GPIO_PULLEN(_no) (GPIO_PULLEN1+(0x10*(_no)))
+ #define GPIO_PULLSEL(_no) (GPIO_PULLSEL1+(0x10*(_no)))
+ #define CLKO_MODE(_no) (CLKO_MODE1+(0x10*(_no)))
+ #define CLKO_NUM 7
+
+#endif /*DRV_GPIO_REG_AS_6253E*/
+
+#if defined(DRV_GPIO_REG_AS_6253E_1)
+ #define GPIO_DIR1 (GPIO_base+0x0000)
+ #define GPIO_DIR2 (GPIO_base+0x0010)
+ #define GPIO_DIR3 (GPIO_base+0x0020)
+ #define GPIO_DIR4 (GPIO_base+0x0030)
+ #define GPIO_DIR5 (GPIO_base+0x0040)
+
+ #define GPIO_PULLEN1 (GPIO_base+0x0050)
+ #define GPIO_PULLEN2 (GPIO_base+0x0060)
+ #define GPIO_PULLEN3 (GPIO_base+0x0070)
+ #define GPIO_PULLEN4 (GPIO_base+0x0080)
+ #define GPIO_PULLEN5 (GPIO_base+0x0090)
+
+ #define GPIO_DINV1 (GPIO_base+0x00a0)
+ #define GPIO_DINV2 (GPIO_base+0x00b0)
+ #define GPIO_DINV3 (GPIO_base+0x00c0)
+ #define GPIO_DINV4 (GPIO_base+0x00d0)
+ #define GPIO_DINV5 (GPIO_base+0x00e0)
+
+ #define GPIO_DOUT1 (GPIO_base+0x00f0)
+ #define GPIO_DOUT2 (GPIO_base+0x0100)
+ #define GPIO_DOUT3 (GPIO_base+0x0110)
+ #define GPIO_DOUT4 (GPIO_base+0x0120)
+ #define GPIO_DOUT5 (GPIO_base+0x0130)
+
+ #define GPIO_DIN1 (GPIO_base+0x0140)
+ #define GPIO_DIN2 (GPIO_base+0x0150)
+ #define GPIO_DIN3 (GPIO_base+0x0160)
+ #define GPIO_DIN4 (GPIO_base+0x0170)
+ #define GPIO_DIN5 (GPIO_base+0x0180)
+
+ #define GPIO_SPMODE0 (GPIO_base+0x0210)
+ #define GPIO_SPMODE1 (GPIO_base+0x0220)
+
+ #define GPIO_MODE1 (GPIO_base+0x0190)
+ #define GPIO_MODE2 (GPIO_base+0x01a0)
+ #define GPIO_MODE3 (GPIO_base+0x01b0)
+ #define GPIO_MODE4 (GPIO_base+0x01c0)
+ #define GPIO_MODE5 (GPIO_base+0x01d0)
+ #define GPIO_MODE6 (GPIO_base+0x01e0)
+ #define GPIO_MODE7 (GPIO_base+0x01f0)
+ #define GPIO_MODE8 (GPIO_base+0x0200)
+ #define GPIO_MODE9 (GPIO_base+0x0230)
+
+ // #define GPIO_BANK (GPIO_base+0x0230)
+
+ #define CLKO_MODE1 (GPIO_base+0x0300)
+ #define CLKO_MODE2 (GPIO_base+0x0310)
+ #define CLKO_MODE3 (GPIO_base+0x0320)
+ #define CLKO_MODE4 (GPIO_base+0x0330)
+ #define CLKO_MODE5 (GPIO_base+0x0340)
+ #define CLKO_MODE6 (GPIO_base+0x0350)
+ #define CLKO_MODE7 (GPIO_base+0x0360)
+
+ #define GPIO_DINV_ADRS(n) (GPIO_DINV1+0x10*(n))
+
+ #define GPIO_PULLSEL1 (GPIO_base+0x0240)
+ #define GPIO_PULLSEL2 (GPIO_base+0x0250)
+ #define GPIO_PULLSEL3 (GPIO_base+0x0260)
+ #define GPIO_PULLSEL4 (GPIO_base+0x0270)
+ #define GPIO_PULLSEL5 (GPIO_base+0x0280)
+
+ #define GPIO_TM (GPIO_base+0x0370)
+
+ #define GPIO_DIR1_SET (GPIO_DIR1+0x04)
+ #define GPIO_PULLEN1_SET (GPIO_PULLEN1+0x04)
+ #define GPIO_DOUT1_SET (GPIO_DOUT1+0x04)
+ #define GPIO_MODE1_SET (GPIO_MODE1+0x04)
+ #define GPIO_PULLSEL1_SET (GPIO_PULLSEL1+0x04)
+
+ #define GPIO_MODE_SET(_no) (((_no)==8)?(GPIO_MODE9+0x04):(GPIO_MODE1_SET+(0x10*(_no))))
+ #define GPIO_DIR_SET(_no) (GPIO_DIR1_SET+(0x10*(_no)))
+ #define GPIO_DOUT_SET(_no) (GPIO_DOUT1_SET+(0x10*(_no)))
+ #define GPIO_PULLEN_SET(_no) (GPIO_PULLEN1_SET+(0x10*(_no)))
+ #define GPIO_PULLSEL_SET(_no) (GPIO_PULLSEL1_SET+(0x10*(_no)))
+
+ #define GPIO_DIR1_CLR (GPIO_DIR1+0x08)
+ #define GPIO_PULLEN1_CLR (GPIO_PULLEN1+0x08)
+ #define GPIO_DOUT1_CLR (GPIO_DOUT1+0x08)
+ #define GPIO_MODE1_CLR (GPIO_MODE1+0x08)
+ #define GPIO_PULLSEL1_CLR (GPIO_PULLSEL1+0x08)
+
+ #define GPIO_MODE_CLR(_no) (((_no)==8)?(GPIO_MODE9+0x08):(GPIO_MODE1_CLR+(0x10*(_no))))
+ #define GPIO_DIR_CLR(_no) (GPIO_DIR1_CLR+(0x10*(_no)))
+ #define GPIO_DOUT_CLR(_no) (GPIO_DOUT1_CLR+(0x10*(_no)))
+ #define GPIO_PULLEN_CLR(_no) (GPIO_PULLEN1_CLR+(0x10*(_no)))
+ #define GPIO_PULLSEL_CLR(_no) (GPIO_PULLSEL1_CLR+(0x10*(_no)))
+
+ #define GPIO_MODE(_no) (((_no)==8)?(GPIO_MODE9):(GPIO_MODE1+(0x10*(_no))))
+ #define GPIO_DOUT(_no) (GPIO_DOUT1+(0x10*(_no)))
+ #define GPIO_DIR(_no) (GPIO_DIR1+(0x10*(_no)))
+ #define GPIO_DIN(_no) (GPIO_DIN1+(0x10*(_no)))
+ #define GPIO_PULLEN(_no) (GPIO_PULLEN1+(0x10*(_no)))
+ #define GPIO_PULLSEL(_no) (GPIO_PULLSEL1+(0x10*(_no)))
+ #define CLKO_MODE(_no) (CLKO_MODE1+(0x10*(_no)))
+ #define CLKO_NUM 7
+
+#endif /*DRV_GPIO_REG_AS_6253E_1*/
+
+#if defined(DRV_GPIO_REG_AS_6236)
+ #define GPIO_DIR1 (GPIO_base+0x0000)
+ #define GPIO_DIR2 (GPIO_base+0x0010)
+ #define GPIO_DIR3 (GPIO_base+0x0020)
+ #define GPIO_DIR4 (GPIO_base+0x0030)
+ #define GPIO_DIR5 (GPIO_base+0x0040)
+ #define GPIO_PULLEN1 (GPIO_base+0x0100)
+ #define GPIO_PULLEN2 (GPIO_base+0x0110)
+ #define GPIO_PULLEN3 (GPIO_base+0x0120)
+ #define GPIO_PULLEN4 (GPIO_base+0x0130)
+ #define GPIO_PULLEN5 (GPIO_base+0x0140)
+ #define GPIO_PULLSEL1 (GPIO_base+0x0200)
+ #define GPIO_PULLSEL2 (GPIO_base+0x0210)
+ #define GPIO_PULLSEL3 (GPIO_base+0x0220)
+ #define GPIO_PULLSEL4 (GPIO_base+0x0230)
+ #define GPIO_PULLSEL5 (GPIO_base+0x0240)
+ #define GPIO_DINV1 (GPIO_base+0x0300)
+ #define GPIO_DINV2 (GPIO_base+0x0310)
+ #define GPIO_DINV3 (GPIO_base+0x0320)
+ #define GPIO_DINV4 (GPIO_base+0x0330)
+ #define GPIO_DINV5 (GPIO_base+0x0340)
+ #define GPIO_DOUT1 (GPIO_base+0x0400)
+ #define GPIO_DOUT2 (GPIO_base+0x0410)
+ #define GPIO_DOUT3 (GPIO_base+0x0420)
+ #define GPIO_DOUT4 (GPIO_base+0x0430)
+ #define GPIO_DOUT5 (GPIO_base+0x0440)
+ #define GPIO_DIN1 (GPIO_base+0x0500)
+ #define GPIO_DIN2 (GPIO_base+0x0510)
+ #define GPIO_DIN3 (GPIO_base+0x0520)
+ #define GPIO_DIN4 (GPIO_base+0x0530)
+ #define GPIO_DIN5 (GPIO_base+0x0540)
+ #define GPIO_MODE1 (GPIO_base+0x0600)
+ #define GPIO_MODE2 (GPIO_base+0x0610)
+ #define GPIO_MODE3 (GPIO_base+0x0620)
+ #define GPIO_MODE4 (GPIO_base+0x0630)
+ #define GPIO_MODE5 (GPIO_base+0x0640)
+ #define GPIO_MODE6 (GPIO_base+0x0650)
+ #define GPIO_MODE7 (GPIO_base+0x0660)
+ #define GPIO_MODE8 (GPIO_base+0x0670)
+ #define GPIO_MODE9 (GPIO_base+0x0680)
+ #define CLKO_MODE0 (GPIO_base+0x0900)
+ #define CLKO_MODE1 (GPIO_base+0x0910)
+ #define CLKO_MODE2 (GPIO_base+0x0920)
+ #define CLKO_MODE3 (GPIO_base+0x0930)
+ #define CLKO_MODE4 (GPIO_base+0x0940)
+ #define CLKO_MODE5 (GPIO_base+0x0950)
+ #define GPIO_DINV_ADRS(n) (GPIO_DINV1+0x10*(n))
+
+ #define GPIO_DIR1_SET (GPIO_base+0x0000+0x04)
+ #define GPIO_DIR2_SET (GPIO_base+0x0010+0x04)
+ #define GPIO_DIR3_SET (GPIO_base+0x0020+0x04)
+ #define GPIO_DIR4_SET (GPIO_base+0x0030+0x04)
+ #define GPIO_DIR5_SET (GPIO_base+0x0040+0x04)
+ #define GPIO_PULLEN1_SET (GPIO_base+0x0100+0x04)
+ #define GPIO_PULLEN2_SET (GPIO_base+0x0110+0x04)
+ #define GPIO_PULLEN3_SET (GPIO_base+0x0120+0x04)
+ #define GPIO_PULLEN4_SET (GPIO_base+0x0130+0x04)
+ #define GPIO_PULLEN5_SET (GPIO_base+0x0140+0x04)
+ #define GPIO_PULLSEL1_SET (GPIO_base+0x0200+0x04)
+ #define GPIO_PULLSEL2_SET (GPIO_base+0x0210+0x04)
+ #define GPIO_PULLSEL3_SET (GPIO_base+0x0220+0x04)
+ #define GPIO_PULLSEL4_SET (GPIO_base+0x0230+0x04)
+ #define GPIO_PULLSEL5_SET (GPIO_base+0x0240+0x04)
+ #define GPIO_DOUT1_SET (GPIO_base+0x0400+0x04)
+ #define GPIO_DOUT2_SET (GPIO_base+0x0410+0x04)
+ #define GPIO_DOUT3_SET (GPIO_base+0x0420+0x04)
+ #define GPIO_DOUT4_SET (GPIO_base+0x0430+0x04)
+ #define GPIO_DOUT5_SET (GPIO_base+0x0440+0x04)
+ #define GPIO_MODE1_SET (GPIO_base+0x0600+0x04)
+ #define GPIO_MODE2_SET (GPIO_base+0x0610+0x04)
+ #define GPIO_MODE3_SET (GPIO_base+0x0620+0x04)
+ #define GPIO_MODE4_SET (GPIO_base+0x0630+0x04)
+ #define GPIO_MODE5_SET (GPIO_base+0x0640+0x04)
+ #define GPIO_MODE6_SET (GPIO_base+0x0650+0x04)
+ #define GPIO_MODE7_SET (GPIO_base+0x0660+0x04)
+ #define GPIO_MODE8_SET (GPIO_base+0x0670+0x04)
+ #define GPIO_MODE9_SET (GPIO_base+0x0680+0x04)
+ #define GPIO_MODE_SET(_no) (GPIO_MODE1_SET+(0x10*(_no)))
+ #define GPIO_DIR_SET(_no) (GPIO_DIR1_SET+(0x10*(_no)))
+ #define GPIO_DOUT_SET(_no) (GPIO_DOUT1_SET+(0x10*(_no)))
+ #define GPIO_PULLEN_SET(_no) (GPIO_PULLEN1_SET+(0x10*(_no)))
+ #define GPIO_PULLSEL_SET(_no) (GPIO_PULLSEL1_SET+(0x10*(_no)))
+
+ #define GPIO_DIR1_CLR (GPIO_base+0x0000+0x08)
+ #define GPIO_DIR2_CLR (GPIO_base+0x0010+0x08)
+ #define GPIO_DIR3_CLR (GPIO_base+0x0020+0x08)
+ #define GPIO_DIR4_CLR (GPIO_base+0x0030+0x08)
+ #define GPIO_DIR5_CLR (GPIO_base+0x0040+0x08)
+ #define GPIO_PULLEN1_CLR (GPIO_base+0x0100+0x08)
+ #define GPIO_PULLEN2_CLR (GPIO_base+0x0110+0x08)
+ #define GPIO_PULLEN3_CLR (GPIO_base+0x0120+0x08)
+ #define GPIO_PULLEN4_CLR (GPIO_base+0x0130+0x08)
+ #define GPIO_PULLEN5_CLR (GPIO_base+0x0140+0x08)
+ #define GPIO_PULLSEL1_CLR (GPIO_base+0x0200+0x08)
+ #define GPIO_PULLSEL2_CLR (GPIO_base+0x0210+0x08)
+ #define GPIO_PULLSEL3_CLR (GPIO_base+0x0220+0x08)
+ #define GPIO_PULLSEL4_CLR (GPIO_base+0x0230+0x08)
+ #define GPIO_PULLSEL5_CLR (GPIO_base+0x0240+0x08)
+ #define GPIO_DOUT1_CLR (GPIO_base+0x0400+0x08)
+ #define GPIO_DOUT2_CLR (GPIO_base+0x0410+0x08)
+ #define GPIO_DOUT3_CLR (GPIO_base+0x0420+0x08)
+ #define GPIO_DOUT4_CLR (GPIO_base+0x0430+0x08)
+ #define GPIO_DOUT5_CLR (GPIO_base+0x0440+0x08)
+ #define GPIO_MODE1_CLR (GPIO_base+0x0600+0x08)
+ #define GPIO_MODE2_CLR (GPIO_base+0x0610+0x08)
+ #define GPIO_MODE3_CLR (GPIO_base+0x0620+0x08)
+ #define GPIO_MODE4_CLR (GPIO_base+0x0630+0x08)
+ #define GPIO_MODE5_CLR (GPIO_base+0x0640+0x08)
+ #define GPIO_MODE6_CLR (GPIO_base+0x0650+0x08)
+ #define GPIO_MODE7_CLR (GPIO_base+0x0660+0x08)
+ #define GPIO_MODE8_CLR (GPIO_base+0x0670+0x08)
+ #define GPIO_MODE9_CLR (GPIO_base+0x0680+0x08)
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE1_CLR+(0x10*(_no)))
+ #define GPIO_DIR_CLR(_no) (GPIO_DIR1_CLR+(0x10*(_no)))
+ #define GPIO_DOUT_CLR(_no) (GPIO_DOUT1_CLR+(0x10*(_no)))
+ #define GPIO_PULLEN_CLR(_no) (GPIO_PULLEN1_CLR+(0x10*(_no)))
+ #define GPIO_PULLSEL_CLR(_no) (GPIO_PULLSEL1_CLR+(0x10*(_no)))
+
+ #define GPIO_MODE(_no) (GPIO_MODE1+(0x10*(_no)))
+ #define GPIO_DOUT(_no) (GPIO_DOUT1+(0x10*(_no)))
+ #define GPIO_DIR(_no) (GPIO_DIR1+(0x10*(_no)))
+ #define GPIO_DIN(_no) (GPIO_DIN1+(0x10*(_no)))
+ #define GPIO_PULLEN(_no) (GPIO_PULLEN1+(0x10*(_no)))
+ #define GPIO_PULLSEL(_no) (GPIO_PULLSEL1+(0x10*(_no)))
+ #define CLKO_MODE(_no) (CLKO_MODE0+(0x10*(_no)))
+ #define CLKO_NUM 6
+#endif /*defined(DRV_GPIO_REG_AS_6236)*/
+
+#if defined(DRV_GPIO_REG_AS_6255)
+ #define GPIO_DIR1 (GPIO_base+0x0000)
+ #define GPIO_DIR2 (GPIO_base+0x0010)
+ #define GPIO_DIR3 (GPIO_base+0x0020)
+ #define GPIO_DIR4 (GPIO_base+0x0030)
+ #define GPIO_DIR5 (GPIO_base+0x0040)
+ #define GPIO_DIR6 (GPIO_base+0x0050)
+ #define GPIO_DIR7 (GPIO_base+0x0060)
+ #define GPIO_PULLEN1 (GPIO_base+0x0100)
+ #define GPIO_PULLEN2 (GPIO_base+0x0110)
+ #define GPIO_PULLEN3 (GPIO_base+0x0120)
+ #define GPIO_PULLEN4 (GPIO_base+0x0130)
+ #define GPIO_PULLEN5 (GPIO_base+0x0140)
+ #define GPIO_PULLEN6 (GPIO_base+0x0150)
+ #define GPIO_PULLEN7 (GPIO_base+0x0160)
+ #define GPIO_PULLSEL1 (GPIO_base+0x0200)
+ #define GPIO_PULLSEL2 (GPIO_base+0x0210)
+ #define GPIO_PULLSEL3 (GPIO_base+0x0220)
+ #define GPIO_PULLSEL4 (GPIO_base+0x0230)
+ #define GPIO_PULLSEL5 (GPIO_base+0x0240)
+ #define GPIO_PULLSEL6 (GPIO_base+0x0250)
+ #define GPIO_PULLSEL7 (GPIO_base+0x0260)
+ #define GPIO_DINV1 (GPIO_base+0x0300)
+ #define GPIO_DINV2 (GPIO_base+0x0310)
+ #define GPIO_DINV3 (GPIO_base+0x0320)
+ #define GPIO_DINV4 (GPIO_base+0x0330)
+ #define GPIO_DINV5 (GPIO_base+0x0340)
+ #define GPIO_DINV6 (GPIO_base+0x0350)
+ #define GPIO_DINV7 (GPIO_base+0x0360)
+ #define GPIO_DOUT1 (GPIO_base+0x0400)
+ #define GPIO_DOUT2 (GPIO_base+0x0410)
+ #define GPIO_DOUT3 (GPIO_base+0x0420)
+ #define GPIO_DOUT4 (GPIO_base+0x0430)
+ #define GPIO_DOUT5 (GPIO_base+0x0440)
+ #define GPIO_DOUT6 (GPIO_base+0x0450)
+ #define GPIO_DOUT7 (GPIO_base+0x0460)
+ #define GPIO_DIN1 (GPIO_base+0x0500)
+ #define GPIO_DIN2 (GPIO_base+0x0510)
+ #define GPIO_DIN3 (GPIO_base+0x0520)
+ #define GPIO_DIN4 (GPIO_base+0x0530)
+ #define GPIO_DIN5 (GPIO_base+0x0540)
+ #define GPIO_DIN6 (GPIO_base+0x0550)
+ #define GPIO_DIN7 (GPIO_base+0x0560)
+ #define GPIO_MODE1 (GPIO_base+0x0600)
+ #define GPIO_MODE2 (GPIO_base+0x0610)
+ #define GPIO_MODE3 (GPIO_base+0x0620)
+ #define GPIO_MODE4 (GPIO_base+0x0630)
+ #define GPIO_MODE5 (GPIO_base+0x0640)
+ #define GPIO_MODE6 (GPIO_base+0x0650)
+ #define GPIO_MODE7 (GPIO_base+0x0660)
+ #define GPIO_MODE8 (GPIO_base+0x0670)
+ #define GPIO_MODE9 (GPIO_base+0x0680)
+ #define GPIO_MODE10 (GPIO_base+0x0690)
+ #define GPIO_MODE11 (GPIO_base+0x06A0)
+ #define GPIO_MODE12 (GPIO_base+0x06B0)
+ #define GPIO_MODE13 (GPIO_base+0x06C0)
+ #define GPIO_MODE14 (GPIO_base+0x06D0)
+ #define GPIO_MODE15 (GPIO_base+0x06E0)
+ #define GPIO_MODE16 (GPIO_base+0x06F0)
+ #define GPIO_MODE17 (GPIO_base+0x0700)
+ #define GPIO_MODE18 (GPIO_base+0x0710)
+ #define GPIO_MODE19 (GPIO_base+0x0720)
+ #define GPIO_MODE20 (GPIO_base+0x0730)
+ #define GPIO_MODE21 (GPIO_base+0x0740)
+ #define GPIO_MODE22 (GPIO_base+0x0750)
+ #define GPIO_MODE23 (GPIO_base+0x0760)
+ #define GPIO_MODE24 (GPIO_base+0x0770)
+ #define GPIO_MODE25 (GPIO_base+0x0780)
+#define GPIO_MODE26 (GPIO_base+0x0790)
+#define GPIO_MODE27 (GPIO_base+0x07A0)
+ #define CLKO_MODE0 (GPIO_base+0x0900)
+ #define CLKO_MODE1 (GPIO_base+0x0910)
+ #define CLKO_MODE2 (GPIO_base+0x0920)
+ #define CLKO_MODE3 (GPIO_base+0x0930)
+ #define CLKO_MODE4 (GPIO_base+0x0940)
+ #define CLKO_MODE5 (GPIO_base+0x0950)
+ #define CLKO_MODE6 (GPIO_base+0x0960)
+ #define CLKO_MODE7 (GPIO_base+0x0970)
+ #define CLKO_MODE8 (GPIO_base+0x0980)
+
+ #define GPIO_DINV_ADRS(n) (GPIO_DINV1+0x10*(n))
+
+ #define GPIO_DIR1_SET (GPIO_DIR1+0x04)
+ #define GPIO_PULLEN1_SET (GPIO_PULLEN1+0x04)
+ #define GPIO_PULLSEL1_SET (GPIO_PULLSEL1+0x04)
+ #define GPIO_DOUT1_SET (GPIO_DOUT1+0x04)
+ #define GPIO_MODE1_SET (GPIO_MODE1+0x04)
+ #define GPIO_MODE_SET(_no) (GPIO_MODE1_SET+(0x10*(_no)))
+ #define GPIO_DIR_SET(_no) (GPIO_DIR1_SET+(0x10*(_no)))
+ #define GPIO_DOUT_SET(_no) (GPIO_DOUT1_SET+(0x10*(_no)))
+ #define GPIO_PULLEN_SET(_no) (GPIO_PULLEN1_SET+(0x10*(_no)))
+ #define GPIO_PULLSEL_SET(_no) (GPIO_PULLSEL1_SET+(0x10*(_no)))
+
+ #define GPIO_DIR1_CLR (GPIO_DIR1+0x08)
+ #define GPIO_PULLEN1_CLR (GPIO_PULLEN1+0x08)
+ #define GPIO_PULLSEL1_CLR (GPIO_PULLSEL1+0x08)
+ #define GPIO_DOUT1_CLR (GPIO_DOUT1+0x08)
+ #define GPIO_MODE1_CLR (GPIO_MODE1+0x08)
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE1_CLR+(0x10*(_no)))
+ #define GPIO_DIR_CLR(_no) (GPIO_DIR1_CLR+(0x10*(_no)))
+ #define GPIO_DOUT_CLR(_no) (GPIO_DOUT1_CLR+(0x10*(_no)))
+ #define GPIO_PULLEN_CLR(_no) (GPIO_PULLEN1_CLR+(0x10*(_no)))
+ #define GPIO_PULLSEL_CLR(_no) (GPIO_PULLSEL1_CLR+(0x10*(_no)))
+
+ #define GPIO_MODE(_no) (GPIO_MODE1+(0x10*(_no)))
+ #define GPIO_DOUT(_no) (GPIO_DOUT1+(0x10*(_no)))
+ #define GPIO_DIR(_no) (GPIO_DIR1+(0x10*(_no)))
+ #define GPIO_DIN(_no) (GPIO_DIN1+(0x10*(_no)))
+ #define GPIO_PULLEN(_no) (GPIO_PULLEN1+(0x10*(_no)))
+ #define GPIO_PULLSEL(_no) (GPIO_PULLSEL1+(0x10*(_no)))
+ #define CLKO_MODE(_no) (CLKO_MODE0+(0x10*(_no)))
+ #define CLKO_NUM 9
+#endif /*defined(DRV_GPIO_REG_AS_6255)*/
+
+#if defined(DRV_GPIO_REG_AS_6251)
+ #define GPIO_DIR1 (GPIO_base+0x0000)
+ #define GPIO_DIR2 (GPIO_base+0x0010)
+ #define GPIO_DIR3 (GPIO_base+0x0020)
+ #define GPIO_PULLEN1 (GPIO_base+0x0050)
+ #define GPIO_PULLEN2 (GPIO_base+0x0060)
+ #define GPIO_PULLEN3 (GPIO_base+0x0070)
+ #define GPIO_PULLSEL1 (GPIO_base+0x0240)
+ #define GPIO_PULLSEL2 (GPIO_base+0x0250)
+ #define GPIO_PULLSEL3 (GPIO_base+0x0260)
+ #define GPIO_DINV1 (GPIO_base+0x00A0)
+ #define GPIO_DINV2 (GPIO_base+0x00B0)
+ //#define GPIO_DINV3 (GPIO_base+0x00C0)
+ #define GPIO_DOUT1 (GPIO_base+0x00F0)
+ #define GPIO_DOUT2 (GPIO_base+0x0100)
+ #define GPIO_DOUT3 (GPIO_base+0x0110)
+ #define GPIO_DIN1 (GPIO_base+0x0140)
+ #define GPIO_DIN2 (GPIO_base+0x0150)
+ //#define GPIO_DIN3 (GPIO_base+0x0160)
+ #define GPIO_MODE1 (GPIO_base+0x0190)
+ #define GPIO_MODE2 (GPIO_base+0x01A0)
+ #define GPIO_MODE3 (GPIO_base+0x01B0)
+ #define GPIO_MODE4 (GPIO_base+0x01C0)
+ #define GPIO_MODE5 (GPIO_base+0x01D0)
+ #define GPIO_MODE6 (GPIO_base+0x01E0)
+ #define GPIO_MODE7 (GPIO_base+0x01F0)
+ #define GPIO_MODE8 (GPIO_base+0x0200)
+ #define CLKO_MODE0 (GPIO_base+0x0300)
+ #define CLKO_MODE1 (GPIO_base+0x0310)
+ #define CLKO_MODE2 (GPIO_base+0x0320)
+ #define CLKO_MODE3 (GPIO_base+0x0330)
+ #define GPIO_DINV_ADRS(n) (GPIO_DINV1+0x10*(n))
+
+ #define GPIO_DIR1_SET (GPIO_DIR1+0x04)
+ #define GPIO_PULLEN1_SET (GPIO_PULLEN1+0x04)
+ #define GPIO_PULLSEL1_SET (GPIO_PULLSEL1+0x04)
+ #define GPIO_DOUT1_SET (GPIO_DOUT1+0x04)
+ #define GPIO_MODE1_SET (GPIO_MODE1+0x04)
+ #define GPIO_MODE_SET(_no) (GPIO_MODE1_SET+(0x10*(_no)))
+ #define GPIO_DIR_SET(_no) (GPIO_DIR1_SET+(0x10*(_no)))
+ #define GPIO_DOUT_SET(_no) (GPIO_DOUT1_SET+(0x10*(_no)))
+ #define GPIO_PULLEN_SET(_no) (GPIO_PULLEN1_SET+(0x10*(_no)))
+ #define GPIO_PULLSEL_SET(_no) (GPIO_PULLSEL1_SET+(0x10*(_no)))
+
+ #define GPIO_DIR1_CLR (GPIO_DIR1+0x08)
+ #define GPIO_PULLEN1_CLR (GPIO_PULLEN1+0x08)
+ #define GPIO_PULLSEL1_CLR (GPIO_PULLSEL1+0x08)
+ #define GPIO_DOUT1_CLR (GPIO_DOUT1+0x08)
+ #define GPIO_MODE1_CLR (GPIO_MODE1+0x08)
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE1_CLR+(0x10*(_no)))
+ #define GPIO_DIR_CLR(_no) (GPIO_DIR1_CLR+(0x10*(_no)))
+ #define GPIO_DOUT_CLR(_no) (GPIO_DOUT1_CLR+(0x10*(_no)))
+ #define GPIO_PULLEN_CLR(_no) (GPIO_PULLEN1_CLR+(0x10*(_no)))
+ #define GPIO_PULLSEL_CLR(_no) (GPIO_PULLSEL1_CLR+(0x10*(_no)))
+
+ #define GPIO_MODE(_no) (GPIO_MODE1+(0x10*(_no)))
+ #define GPIO_DOUT(_no) (GPIO_DOUT1+(0x10*(_no)))
+ #define GPIO_DIR(_no) (GPIO_DIR1+(0x10*(_no)))
+ #define GPIO_DIN(_no) (GPIO_DIN1+(0x10*(_no)))
+ #define GPIO_PULLEN(_no) (GPIO_PULLEN1+(0x10*(_no)))
+ #define GPIO_PULLSEL(_no) (GPIO_PULLSEL1+(0x10*(_no)))
+ #define CLKO_MODE(_no) (CLKO_MODE0+(0x10*(_no)))
+ #define CLKO_NUM 4
+#endif /*defined(DRV_GPIO_REG_AS_6251)*/
+
+ #if defined(MT6276_S01)
+ #define CLK_MUX_SEL0 (CONFIG_base+0x0538)
+ #define CLK_MUX_SEL1 (CONFIG_base+0x053C)
+ #endif
+
+#if defined(DRV_GPIO_REG_AS_6256)
+ #define GPIO_DIR1 (GPIO_base+0x0000)
+ #define GPIO_DIR2 (GPIO_base+0x0010)
+ #define GPIO_DIR3 (GPIO_base+0x0020)
+ #define GPIO_DIR4 (GPIO_base+0x0030)
+ #define GPIO_DIR5 (GPIO_base+0x0040)
+ #define GPIO_DIR6 (GPIO_base+0x0050)
+ #define GPIO_DIR7 (GPIO_base+0x0060)
+
+ #define GPIO_PULLEN1 (GPIO_base+0x0100)
+ #define GPIO_PULLEN2 (GPIO_base+0x0110)
+ #define GPIO_PULLEN3 (GPIO_base+0x0120)
+ #define GPIO_PULLEN4 (GPIO_base+0x0130)
+ #define GPIO_PULLEN5 (GPIO_base+0x0140)
+ #define GPIO_PULLEN6 (GPIO_base+0x0150)
+ #define GPIO_PULLEN7 (GPIO_base+0x0160)
+
+ #define GPIO_PULLSEL1 (GPIO_base+0x0200)
+ #define GPIO_PULLSEL2 (GPIO_base+0x0210)
+ #define GPIO_PULLSEL3 (GPIO_base+0x0220)
+ #define GPIO_PULLSEL4 (GPIO_base+0x0230)
+ #define GPIO_PULLSEL5 (GPIO_base+0x0240)
+ #define GPIO_PULLSEL6 (GPIO_base+0x0250)
+ #define GPIO_PULLSEL7 (GPIO_base+0x0260)
+
+ #define GPIO_DINV1 (GPIO_base+0x0300)
+ #define GPIO_DINV2 (GPIO_base+0x0310)
+ #define GPIO_DINV3 (GPIO_base+0x0320)
+ #define GPIO_DINV4 (GPIO_base+0x0330)
+ #define GPIO_DINV5 (GPIO_base+0x0340)
+ #define GPIO_DINV6 (GPIO_base+0x0350)
+ #define GPIO_DINV7 (GPIO_base+0x0360)
+
+ #define GPIO_DOUT1 (GPIO_base+0x0400)
+ #define GPIO_DOUT2 (GPIO_base+0x0410)
+ #define GPIO_DOUT3 (GPIO_base+0x0420)
+ #define GPIO_DOUT4 (GPIO_base+0x0430)
+ #define GPIO_DOUT5 (GPIO_base+0x0440)
+ #define GPIO_DOUT6 (GPIO_base+0x0450)
+ #define GPIO_DOUT7 (GPIO_base+0x0460)
+
+ #define GPIO_DIN1 (GPIO_base+0x0500)
+ #define GPIO_DIN2 (GPIO_base+0x0510)
+ #define GPIO_DIN3 (GPIO_base+0x0520)
+ #define GPIO_DIN4 (GPIO_base+0x0530)
+ #define GPIO_DIN5 (GPIO_base+0x0540)
+ #define GPIO_DIN6 (GPIO_base+0x0550)
+ #define GPIO_DIN7 (GPIO_base+0x0560)
+
+ #define GPIO_MODE1 (GPIO_base+0x0600)
+ #define GPIO_MODE2 (GPIO_base+0x0610)
+ #define GPIO_MODE3 (GPIO_base+0x0620)
+ #define GPIO_MODE4 (GPIO_base+0x0630)
+ #define GPIO_MODE5 (GPIO_base+0x0640)
+ #define GPIO_MODE6 (GPIO_base+0x0650)
+ #define GPIO_MODE7 (GPIO_base+0x0660)
+ #define GPIO_MODE8 (GPIO_base+0x0670)
+ #define GPIO_MODE9 (GPIO_base+0x0680)
+ #define GPIO_MODE10 (GPIO_base+0x0690)
+ #define GPIO_MODE11 (GPIO_base+0x06A0)
+ #define GPIO_MODE12 (GPIO_base+0x06B0)
+ #define GPIO_MODE13 (GPIO_base+0x06C0)
+ #define GPIO_MODE14 (GPIO_base+0x06D0)
+ #define GPIO_MODE15 (GPIO_base+0x06E0)
+ #define GPIO_MODE16 (GPIO_base+0x06F0)
+ #define GPIO_MODE17 (GPIO_base+0x0700)
+ #define GPIO_MODE18 (GPIO_base+0x0710)
+ #define GPIO_MODE19 (GPIO_base+0x0720)
+ #define GPIO_MODE20 (GPIO_base+0x0730)
+ #define GPIO_MODE21 (GPIO_base+0x0740)
+ #define GPIO_MODE22 (GPIO_base+0x0750)
+ #define GPIO_MODE23 (GPIO_base+0x0760)
+ #define GPIO_MODE24 (GPIO_base+0x0770)
+ #define GPIO_MODE25 (GPIO_base+0x0780)
+ #define GPIO_MODE26 (GPIO_base+0x0790)
+ #define GPIO_MODE27 (GPIO_base+0x07A0)
+
+ #define CLKO_MODE0 (GPIO_base+0x0900)
+ #define CLKO_MODE1 (GPIO_base+0x0910)
+ #define CLKO_MODE2 (GPIO_base+0x0920)
+ #define CLKO_MODE3 (GPIO_base+0x0930)
+ #define CLKO_MODE4 (GPIO_base+0x0940)
+ #define CLKO_MODE5 (GPIO_base+0x0950)
+ #define CLKO_MODE6 (GPIO_base+0x0960)
+
+ #define GPIO_DIR1_SET (GPIO_DIR1+0x04)
+ #define GPIO_PULLEN1_SET (GPIO_PULLEN1+0x04)
+ #define GPIO_PULLSEL1_SET (GPIO_PULLSEL1+0x04)
+ #define GPIO_DOUT1_SET (GPIO_DOUT1+0x04)
+ #define GPIO_MODE1_SET (GPIO_MODE1+0x04)
+ #define GPIO_DINV_ADRS(n) (GPIO_DINV1+0x10*(n))
+ #define GPIO_MODE_SET(_no) (GPIO_MODE1_SET+(0x10*(_no)))
+ #define GPIO_DIR_SET(_no) (GPIO_DIR1_SET+(0x10*(_no)))
+ #define GPIO_DOUT_SET(_no) (GPIO_DOUT1_SET+(0x10*(_no)))
+ #define GPIO_PULLEN_SET(_no) (GPIO_PULLEN1_SET+(0x10*(_no)))
+ #define GPIO_PULLSEL_SET(_no) (GPIO_PULLSEL1_SET+(0x10*(_no)))
+
+ #define GPIO_DIR1_CLR (GPIO_DIR1+0x08)
+ #define GPIO_PULLEN1_CLR (GPIO_PULLEN1+0x08)
+ #define GPIO_PULLSEL1_CLR (GPIO_PULLSEL1+0x08)
+ #define GPIO_DOUT1_CLR (GPIO_DOUT1+0x08)
+ #define GPIO_MODE1_CLR (GPIO_MODE1+0x08)
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE1_CLR+(0x10*(_no)))
+ #define GPIO_DIR_CLR(_no) (GPIO_DIR1_CLR+(0x10*(_no)))
+ #define GPIO_DOUT_CLR(_no) (GPIO_DOUT1_CLR+(0x10*(_no)))
+ #define GPIO_PULLEN_CLR(_no) (GPIO_PULLEN1_CLR+(0x10*(_no)))
+ #define GPIO_PULLSEL_CLR(_no) (GPIO_PULLSEL1_CLR+(0x10*(_no)))
+
+ #define GPIO_MODE(_no) (GPIO_MODE1+(0x10*(_no)))
+ #define GPIO_DOUT(_no) (GPIO_DOUT1+(0x10*(_no)))
+ #define GPIO_DIR(_no) (GPIO_DIR1+(0x10*(_no)))
+ #define GPIO_DIN(_no) (GPIO_DIN1+(0x10*(_no)))
+ #define GPIO_PULLEN(_no) (GPIO_PULLEN1+(0x10*(_no)))
+ #define GPIO_PULLSEL(_no) (GPIO_PULLSEL1+(0x10*(_no)))
+ #define CLKO_MODE(_no) (CLKO_MODE0+(0x10*(_no)))
+ #define CLKO_NUM 6
+#endif /*defined(DRV_GPIO_REG_AS_6256)*/
+
+#if defined(DRV_GPIO_REG_AS_6280)
+
+#define GPIO_DIR1 (GPIO_base+0x0000)
+#define GPIO_DIR2 (GPIO_base+0x0040)
+#define GPIO_DIR3 (GPIO_base+0x0080)
+#define GPIO_DIR4 (GPIO_base+0x00c0)
+#define GPIO_DIR5 (GPIO_base+0x0100)
+#define GPIO_DIR6 (GPIO_base+0x0140)
+#define GPIO_DIR7 (GPIO_base+0x0180)
+
+/*********************************************************/
+
+#define GPIO_PULLEN1 (GPIO_base+0x0200)
+#define GPIO_PULLEN2 (GPIO_base+0x0240)
+#define GPIO_PULLEN3 (GPIO_base+0x0280)
+#define GPIO_PULLEN4 (GPIO_base+0x02c0)
+#define GPIO_PULLEN5 (GPIO_base+0x0300)
+#define GPIO_PULLEN6 (GPIO_base+0x0340)
+#define GPIO_PULLEN7 (GPIO_base+0x0380)
+
+/*********************************************************/
+
+#define GPIO_PULLSEL1 (GPIO_base+0x0400)
+#define GPIO_PULLSEL2 (GPIO_base+0x0440)
+#define GPIO_PULLSEL3 (GPIO_base+0x0480)
+#define GPIO_PULLSEL4 (GPIO_base+0x04c0)
+#define GPIO_PULLSEL5 (GPIO_base+0x0500)
+#define GPIO_PULLSEL6 (GPIO_base+0x0540)
+#define GPIO_PULLSEL7 (GPIO_base+0x0580)
+
+/*********************************************************/
+#define GPIO_DINV1 (GPIO_base+0x0600)
+#define GPIO_DINV2 (GPIO_base+0x0640)
+#define GPIO_DINV3 (GPIO_base+0x0680)
+#define GPIO_DINV4 (GPIO_base+0x06c0)
+#define GPIO_DINV5 (GPIO_base+0x0700)
+#define GPIO_DINV6 (GPIO_base+0x0740)
+#define GPIO_DINV7 (GPIO_base+0x0780)
+/*********************************************************/
+#define GPIO_DOUT1 (GPIO_base+0x0800)
+#define GPIO_DOUT2 (GPIO_base+0x0840)
+#define GPIO_DOUT3 (GPIO_base+0x0880)
+#define GPIO_DOUT4 (GPIO_base+0x08c0)
+#define GPIO_DOUT5 (GPIO_base+0x0900)
+#define GPIO_DOUT6 (GPIO_base+0x0940)
+#define GPIO_DOUT7 (GPIO_base+0x0980)
+/*********************************************************/
+#define GPIO_DIN1 (GPIO_base+0x0a00)
+#define GPIO_DIN2 (GPIO_base+0x0a40)
+#define GPIO_DIN3 (GPIO_base+0x0a80)
+#define GPIO_DIN4 (GPIO_base+0x0ac0)
+#define GPIO_DIN5 (GPIO_base+0x0b00)
+#define GPIO_DIN6 (GPIO_base+0x0b40)
+#define GPIO_DIN7 (GPIO_base+0x0b80)
+/*********************************************************/
+ #define GPIO_MODE0 (GPIO_base+0x1000)
+ #define GPIO_MODE1 (GPIO_base+0x1100)
+ #define GPIO_MODE2 (GPIO_base+0x1200)
+ #define GPIO_MODE3 (GPIO_base+0x1300)
+ #define GPIO_MODE4 (GPIO_base+0x1400)
+ #define GPIO_MODE5 (GPIO_base+0x1500)
+ #define GPIO_MODE6 (GPIO_base+0x1600)
+ #define GPIO_MODE7 (GPIO_base+0x1700)
+ #define GPIO_MODE8 (GPIO_base+0x1800)
+ #define GPIO_MODE9 (GPIO_base+0x1900)
+ #define GPIO_MODE10 (GPIO_base+0x1A00)
+ #define GPIO_MODE11 (GPIO_base+0x1B00)
+ #define GPIO_MODE12 (GPIO_base+0x1C00)
+ #define GPIO_MODE13 (GPIO_base+0x1D00)
+ #define GPIO_MODE14 (GPIO_base+0x1E00)
+ #define GPIO_MODE15 (GPIO_base+0x1F00)
+ #define GPIO_MODE16 (GPIO_base+0x2000)
+ #define GPIO_MODE17 (GPIO_base+0x2100)
+ #define GPIO_MODE18 (GPIO_base+0x2200)
+ #define GPIO_MODE19 (GPIO_base+0x2300)
+ #define GPIO_MODE20 (GPIO_base+0x2400)
+ #define GPIO_MODE21 (GPIO_base+0x2500)
+ #define GPIO_MODE22 (GPIO_base+0x2600)
+ #define GPIO_MODE23 (GPIO_base+0x2700)
+ #define GPIO_MODE24 (GPIO_base+0x2800)
+ /*********************************************************/
+#define GPIO_OTHER (GPIO_base+0x5c00)
+
+/*********************************************************/
+#define CLKO_MODE1 (GPIO_base+0x7000)
+#define CLKO_MODE2 (GPIO_base+0x7100)
+
+/*********************************************************/
+
+
+
+#define GPIO_DINV_ADRS(n) (GPIO_DINV1+0x40*(n))
+
+ #define GPIO_DIR1_SET (GPIO_DIR1+0x04)
+ #define GPIO_PULLEN1_SET (GPIO_PULLEN1+0x04)
+ #define GPIO_PULLSEL1_SET (GPIO_PULLSEL1+0x04)
+ #define GPIO_DOUT1_SET (GPIO_DOUT1+0x04)
+ #define GPIO_MODE1_SET (GPIO_MODE0+0x04)
+ #define GPIO_MODE_SET(_no) (GPIO_MODE1_SET+(0x100*(_no)))
+ #define GPIO_DIR_SET(_no) (GPIO_DIR1_SET+(0x40*(_no)))
+ #define GPIO_DOUT_SET(_no) (GPIO_DOUT1_SET+(0x40*(_no)))
+ #define GPIO_PULLEN_SET(_no) (GPIO_PULLEN1_SET+(0x40*(_no)))
+ #define GPIO_PULLSEL_SET(_no) (GPIO_PULLSEL1_SET+(0x40*(_no)))
+ #define GPIO_OTHER_SET (GPIO_OTHER+0x04)
+
+ #define GPIO_DIR1_CLR (GPIO_DIR1+0x08)
+ #define GPIO_PULLEN1_CLR (GPIO_PULLEN1+0x08)
+ #define GPIO_PULLSEL1_CLR (GPIO_PULLSEL1+0x08)
+ #define GPIO_DOUT1_CLR (GPIO_DOUT1+0x08)
+ #define GPIO_MODE1_CLR (GPIO_MODE0+0x08)
+ #define GPIO_MODE_CLR(_no) (GPIO_MODE1_CLR+(0x100*(_no)))
+ #define GPIO_DIR_CLR(_no) (GPIO_DIR1_CLR+(0x40*(_no)))
+ #define GPIO_DOUT_CLR(_no) (GPIO_DOUT1_CLR+(0x40*(_no)))
+ #define GPIO_PULLEN_CLR(_no) (GPIO_PULLEN1_CLR+(0x40*(_no)))
+ #define GPIO_PULLSEL_CLR(_no) (GPIO_PULLSEL1_CLR+(0x40*(_no)))
+ #define GPIO_OTHER_CLR (GPIO_OTHER+0x08)
+
+
+ #define GPIO_MODE(_no) (GPIO_MODE0+(0x100*(_no)))
+ #define GPIO_DOUT(_no) (GPIO_DOUT1+(0x40*(_no)))
+ #define GPIO_DIR(_no) (GPIO_DIR1+(0x40*(_no)))
+ #define GPIO_DIN(_no) (GPIO_DIN1+(0x40*(_no)))
+ #define GPIO_PULLEN(_no) (GPIO_PULLEN1+(0x40*(_no)))
+ #define GPIO_PULLSEL(_no) (GPIO_PULLSEL1+(0x40*(_no)))
+
+
+ #define CLKO_MODE(_no) (CLKO_MODE1+(0x100*(_no)))
+ #define CLKO_NUM 2
+
+#endif //defined(DRV_GPIO_REG_AS_6280)
+
+
+
+
+#endif /*!defined(DRV_GPIO_OFF)*/
+#endif /*_GPIO_HW_H*/
+
diff --git a/mcu/driver/peripheral/inc/gpt_hw.h b/mcu/driver/peripheral/inc/gpt_hw.h
new file mode 100644
index 0000000..17d859d
--- /dev/null
+++ b/mcu/driver/peripheral/inc/gpt_hw.h
@@ -0,0 +1,196 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * gpt_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for GPT driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef GPT_HW_H
+#define GPT_HW_H
+#include "drv_features_gpt.h"
+#include "reg_base.h"
+#if !defined(DRV_GPT_OFF)
+
+//MMP address
+//#define GPT_base 0x80100000
+#define GPT1_CTRL (GPT_base+0x00)
+#define GPT1_LEN (GPT_base+0x04)
+#define GPT2_CTRL (GPT_base+0x08)
+#define GPT2_LEN (GPT_base+0x0c)
+#define GPT_STS (GPT_base+0x10)
+#define GPT1_PRESCALER (GPT_base+0x14)
+#define GPT2_PRESCALER (GPT_base+0x18)
+#if defined(DRV_GPT_GPT3)
+#define GPT3_CTRL (GPT_base+0x1c)
+#define GPT3_LEN (GPT_base+0x20)
+#define GPT3_PRESCALER (GPT_base+0x24)
+#endif
+#if defined(DRV_GPT_GPT4)
+#define GPT4_CTRL (GPT_base+0x28)
+#define GPT4_LEN (GPT_base+0x2c)
+#endif
+#endif /*#if !defined(DRV_GPT_OFF)*/
+
+//GPT_CTRL
+#define GPT_CTRL_AUTOMODE 0x4000
+#define GPT_CTRL_Enable 0x8000
+#define GPT_CTRL_Disable 0x0000
+#define GPT3_ENABLE 0x1
+#define GPT4_ENABLE 0x1
+#define GPT4_LOCKED 0x02
+//GPT_STS
+#define GPT_STS_1 0x0001
+#define GPT_STS_2 0x0002
+
+
+//GPT_PRESCALER
+#define GPT_PRESCALER_div2 0x0000
+#define GPT_PRESCALER_div4 0x0001
+#define GPT_PRESCALER_div8 0x0002
+#define GPT_PRESCALER_div16 0x0003
+#define GPT_PRESCALER_div32 0x0004
+#define GPT_PRESCALER_div64 0x0005
+#define GPT_PRESCALER_div128 0x0006
+#define GPT_PRESCALER_div256 0x0007
+
+#endif /*GPT_HW_H*/
+
diff --git a/mcu/driver/peripheral/inc/gpt_sw.h b/mcu/driver/peripheral/inc/gpt_sw.h
new file mode 100644
index 0000000..fddb0e6
--- /dev/null
+++ b/mcu/driver/peripheral/inc/gpt_sw.h
@@ -0,0 +1,274 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * gpt_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for GPT driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef GPT_SW_H
+#define GPT_SW_H
+#include "kal_general_types.h"
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(DRV_GPT_GPT3)
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+#endif
+#if 0
+/* under construction !*/
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_GPT_REG_DBG__)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#else
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_GPT_REG_DBG__)
+/* under construction !*/
+#endif
+
+#endif
diff --git a/mcu/driver/peripheral/inc/hif_v2_internal.h b/mcu/driver/peripheral/inc/hif_v2_internal.h
new file mode 100644
index 0000000..938fb51
--- /dev/null
+++ b/mcu/driver/peripheral/inc/hif_v2_internal.h
@@ -0,0 +1,195 @@
+#ifndef __HIF_V2_INTERNAL_H__
+#define __HIF_V2_INTERNAL_H__
+
+//#include "drv_features.h"
+//#include "kal_release.h"
+#include "reg_base.h"
+#if defined(DRV_HIF_SUPPORT) && defined(DRV_HIF_V2)
+
+
+//#define HIF0_base 0x81180000
+
+// Default: HIF0 is connected to LPCE1. HIF1 is connected to LPCE2.
+#error
+
+//define ECO solution for MT6256E4,MT6575E2 or MTK later chips
+//#if (defined(MT6256_S03) || defined(MT6575_S01) || defined(MT6577)) && defined(__AST_TL1_TDD__)
+//#if (defined(MT6256_S03)) && defined(__AST_TL1_TDD__)
+//#define HIF_ECO_SOLUTION_SUPPORT
+//#endif
+/****************************************************************************
+** Define HIF registers and Macro
+*****************************************************************************/
+#define HIF_MAX_PORT_NUM 4
+#define HIF_ENGINE_COUNT 2
+
+#define HIF_PORT_MCU_A0_LOW_ADDR(n) (HIF0_base+0x0300+n*base_add_increase)
+#define HIF_PORT_MCU_A0_HIGH_ADDR(n) (HIF0_base+0x0310+n*base_add_increase)
+#define HIF_PORT_PDMA_ADDR(n) (HIF0_base+0x0200+n*base_add_increase)
+
+#define HIF_TIMING_CONFIG_WRITE_WAIT_STATE_MASK 0x3F
+#define HIF_TIMING_CONFIG_WRITE_SETUP_TIME_MASK 0xF00
+#define HIF_TIMING_CONFIG_WRITE_HOLD_TIME_MASK 0xF000
+#define HIF_TIMING_CONFIG_READ_LATENCY_TIME_MASK 0x3F0000
+#define HIF_TIMING_CONFIG_READ_SETUP_TIME_MASK 0xF000000
+#define HIF_TIMING_CONFIG_READ_HOLD_TIME_MASK 0xF0000000
+#define HIF_TIMING_CONFIG_CHW_MASK 0xF
+#define HIF_TIMING_CONFIG_WRITE_WAIT_STATE_OFFSET 0
+#define HIF_TIMING_CONFIG_WRITE_SETUP_TIME_OFFSET 8
+#define HIF_TIMING_CONFIG_WRITE_HOLD_TIME_OFFSET 12
+#define HIF_TIMING_CONFIG_READ_LATENCY_TIME_OFFSET 16
+#define HIF_TIMING_CONFIG_READ_SETUP_TIME_OFFSET 24
+#define HIF_TIMING_CONFIG_READ_HOLD_TIME_OFFSET 28
+#define HIF_TIMING_CONFIG_CHW_OFFSET 0
+
+
+#define HIF_STA_REG(n) (HIF0_base+n*base_add_increase+0x0)
+#define HIF_INTEN_REG(n) (HIF0_base+n*base_add_increase+0x4)
+#define HIF_INTSTA_REG(n) (HIF0_base+n*base_add_increase+0x8)
+#define HIF_START_REG(n) (HIF0_base+n*base_add_increase+0xC)
+#define HIF_SWRST_REG(n) (HIF0_base+n*base_add_increase+0x10)
+#define HIF_TIME0_REG(n) (HIF0_base+n*base_add_increase+0x14)
+#define HIF_TIME1_REG(n) (HIF0_base+n*base_add_increase+0x18)
+#define HIF_CON_REG(n) (HIF0_base+n*base_add_increase+0x20)
+#define HIF_DAMOUNT_REG(n) (HIF0_base+n*base_add_increase+0x24)
+//#if defined (HIF_ECO_SOLUTION_SUPPORT)
+#define HIF_ACS_ARB_REG(n) (HIF0_base+n*base_add_increase+0x30)
+
+#define PIF_BUSY_MASK 0x2
+
+#define MCU_ACS_REQ_OFFSET 0
+#define MCU_ACS_STR_OFFSET 2
+//#endif
+
+#define HIF_BUSY_MASK 0x00000001
+#define HIF_CPL_MASK 0x00000001
+#define HIF_START_MASK 0x00000001
+#define HIF_RST_MASK 0x00000001
+#define HIF_HIFW_MASK 0x00000003
+#define HIF_WRITE_MASK 0x00000004
+#define HIF_A0_MASK 0x00000008
+#define HIF_ULTRA_MASK 0x00000010
+
+#define HIF_HIFW_OFFSET 0
+#define HIF_WRITE_OFFSET 2
+#define HIF_A0_OFFSET 3
+#define HIF_ULTRA_OFFSET 4
+
+#define SET_HIF_CE2WR_SETUP_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_WRITE_SETUP_TIME_MASK;\
+ (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_WRITE_SETUP_TIME_OFFSET;
+#define SET_HIF_CE2WR_HOLD_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_WRITE_HOLD_TIME_MASK;\
+ (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_WRITE_HOLD_TIME_OFFSET;
+#define SET_HIF_CE2RD_SETUP_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_READ_SETUP_TIME_MASK;\
+ (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_READ_SETUP_TIME_OFFSET;
+#define SET_HIF_CE2RD_HOLD_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_READ_HOLD_TIME_MASK;\
+ (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_READ_HOLD_TIME_OFFSET;
+#define SET_HIF_WRITE_WAIT_STATE(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_WRITE_WAIT_STATE_MASK;\
+ (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_WRITE_WAIT_STATE_OFFSET;
+#define SET_HIF_READ_LATENCY_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME0_REG(n)) &= ~HIF_TIMING_CONFIG_READ_LATENCY_TIME_MASK;\
+ (*(volatile kal_uint32*)HIF_TIME0_REG(n)) |= (val)<<HIF_TIMING_CONFIG_READ_LATENCY_TIME_OFFSET;
+#define SET_HIF_CS_HIGH_WIDTH_TIME(n, val) (*(volatile kal_uint32*)HIF_TIME1_REG(n)) &= ~HIF_TIMING_CONFIG_CHW_MASK;\
+ (*(volatile kal_uint32*)HIF_TIME1_REG(n)) |= (val)<<HIF_TIMING_CONFIG_CHW_OFFSET;
+#define SET_HIF_BUS_WIDTH(n, val) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_HIFW_MASK;\
+ (*(volatile kal_uint32*)HIF_CON_REG(n)) |= (val/8-1)<<HIF_HIFW_OFFSET;
+#define SET_HIF_WRITE(n) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_WRITE_MASK;\
+ (*(volatile kal_uint32*)HIF_CON_REG(n)) |= 1<<HIF_WRITE_OFFSET;
+#define SET_HIF_READ(n) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_WRITE_MASK;\
+ (*(volatile kal_uint32*)HIF_CON_REG(n)) |= 0<<HIF_WRITE_OFFSET;
+#define SET_HIF_A0_HIGH(n) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_A0_MASK;\
+ (*(volatile kal_uint32*)HIF_CON_REG(n)) |= 1<<HIF_A0_OFFSET;
+#define SET_HIF_A0_LOW(n) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_A0_MASK;\
+ (*(volatile kal_uint32*)HIF_CON_REG(n)) |= 0<<HIF_A0_OFFSET;
+#define SET_HIF_ULTRA(n, val) (*(volatile kal_uint32*)HIF_CON_REG(n)) &= ~HIF_ULTRA_MASK;\
+ (*(volatile kal_uint32*)HIF_CON_REG(n)) |= (val)<<HIF_ULTRA_OFFSET;
+#define GET_HIF_ULTRA(n) (((*(volatile kal_uint32*)HIF_CON_REG(n))>> HIF_ULTRA_OFFSET) & 0x1);
+#define SET_HIF_DAMOUNT(n, val) (*(volatile kal_uint32*)HIF_DAMOUNT_REG(n)) = (val) - 1;
+
+#define ENABLE_HIF_INTR(n) (*(volatile kal_uint32*)HIF_INTEN_REG(n)) = 1;
+#define DISABLE_HIF_INTR(n) (*(volatile kal_uint32*)HIF_INTEN_REG(n)) = 0;
+
+#define START_HIF(n) (*(volatile kal_uint32*)HIF_START_REG(n)) = 0;\
+ (*(volatile kal_uint32*)HIF_START_REG(n)) = 1;
+#define HIF_BUSY(n) ((*(volatile kal_uint32*)HIF_STA_REG(n)) & HIF_BUSY_MASK)
+#define HIF_INT_CLEAR(n) do {volatile kal_uint32 hif_intsta = (*(volatile kal_uint32*)HIF_INTSTA_REG(n)));} while(0);
+//#if defined (HIF_ECO_SOLUTION_SUPPORT)
+#define SET_HIF_MCU_ACS_REQ(n) (*(volatile kal_uint32*)HIF_ACS_ARB_REG(n)) |= 1<<MCU_ACS_REQ_OFFSET
+#define SET_HIF_MCU_ACS_STA(n) (*(volatile kal_uint32*)HIF_ACS_ARB_REG(n)) |= 1<<MCU_ACS_STR_OFFSET
+#define CLEAR_HIF_MCU_ACS_REQ_STA(n) (*(volatile kal_uint32*)HIF_ACS_ARB_REG(n)) = 0
+#define PIF_BUSY(n) ((*(volatile kal_uint32*)HIF_ACS_ARB_REG(n)) & PIF_BUSY_MASK)
+//#endif
+
+// power gating definitions
+#error
+// End of power gating definitions
+/****************************************************************************
+** NLI arbiter definitions
+*****************************************************************************/
+#define REG_NLI_ARB_CS *((volatile unsigned int *) (NLI_ARB_base + 0x0014))
+#define REG_NLI_ARB_CONT_GRANT *((volatile unsigned int *) (NLI_ARB_base + 0x0018))
+#define REG_NLI_ARB_HANDOVER *((volatile unsigned int *) (NLI_ARB_base + 0x001C))
+
+
+#define NLI_ARB_CE0B_SEL_OFS 0
+#define NLI_ARB_CE1B_SEL_OFS 4
+#define NLI_ARB_CE2B_SEL_OFS 8
+#define NLI_ARB_CE3B_SEL_OFS 12
+#define NLI_ARB_CEB_SEL_OFS(n) (4 * n)
+
+#define NLI_ARB_CE0B_SEL_MASK 0x7
+#define NLI_ARB_CE1B_SEL_MASK 0x70
+#define NLI_ARB_CE2B_SEL_MASK 0x700
+#define NLI_ARB_CE3B_SEL_MASK 0x7000
+#define NLI_ARB_CEB_SEL_MASK(n) (0x7 << (NLI_ARB_CEB_SEL_OFS(n)))
+#define NLI_ARB_SET_LPCE_SEL(lpce_num, hif_id) \
+{ \
+ volatile unsigned int temp_REG_NLI_ARB_CS; \
+ temp_REG_NLI_ARB_CS = REG_NLI_ARB_CS; \
+ temp_REG_NLI_ARB_CS &= (~(NLI_ARB_CEB_SEL_MASK(lpce_num))); \
+ temp_REG_NLI_ARB_CS |= ((hif_id+3) << (NLI_ARB_CEB_SEL_OFS(lpce_num))); \
+ REG_NLI_ARB_CS = temp_REG_NLI_ARB_CS; \
+}
+/****************************************************************************
+** PDMA definitions
+*****************************************************************************/
+#define PDMA_OFS 0x80
+// PDMA definitions
+
+
+/****************************************************************************
+** PDMA Control Register Macros
+*****************************************************************************/
+
+#define PDMA_SET_BUF_ADDR(if_num, val) REG_PDMA_HIF_MEM_ADDR(if_num) = val;
+#define PDMA_RD_BIT 0x1
+#define PDMA_SET_RW_DIRECTION(if_num, R) REG_PDMA_HIF_CON(if_num) &= (~(PDMA_RD_BIT));\
+ REG_PDMA_HIF_CON(if_num) |= (R & 0x1);
+#define PDMA_BURST_LEN_MASK 0x70000
+#define PDMA_BURST_LEN_OFS 16
+#define PDMA_SET_BURST_LEN(if_num, len) REG_PDMA_HIF_CON(if_num) &= (~(PDMA_BURST_LEN_MASK));\
+ REG_PDMA_HIF_CON(if_num) |= ((len & 0x7) << PDMA_BURST_LEN_OFS);
+#define PDMA_SET_BUF_LEN(if_num, len) REG_PDMA_HIF_LEN(if_num) = len
+#define PDMA_START(if_num) REG_PDMA_HIF_EN(if_num) = 1;
+#define PDMA_SW_RST(if_num) REG_PDMA_HIF_RST(if_num) = 1;
+
+// End of PDMA definitions
+
+typedef struct
+{
+ kal_bool realtime_callback;
+ kal_uint32 port;
+ kal_uint32 engine_id;
+ kal_uint32 user;
+ HIF_CONFIG_T config;
+ kal_bool A0H_CPU_BUSY;
+ kal_bool A0L_CPU_BUSY;
+} HIF_INTERNAL_HANDLE_T;
+
+// HIF internal functions
+void hif0_lisr(void);
+void hif0_hisr(void);
+void hif1_lisr(void);
+void hif1_hisr(void);
+void hif_wait_for_idle(kal_uint32 engine_id);
+
+#endif
+#endif
diff --git a/mcu/driver/peripheral/inc/i2c.h b/mcu/driver/peripheral/inc/i2c.h
new file mode 100644
index 0000000..ad5e639
--- /dev/null
+++ b/mcu/driver/peripheral/inc/i2c.h
@@ -0,0 +1,653 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sccb_v2.h
+ *
+ *
+ * Description:
+ * ------------
+ * SCCB/I2C V2 Driver
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ *****************************************************************************/
+#ifndef __I2C_H__
+#define __I2C_H__
+
+#include "drv_features_i2c.h"
+#include "dcl_i2c_owner.h"
+
+#if (defined(DRV_I2C_25_SERIES))
+
+#include "drv_comm.h"
+
+#include "kal_general_types.h"
+#include "reg_base.h"
+
+#ifdef I2C_V2_DVT
+ #if !defined(DRV_I2C_DMA_ENABLED)
+ #define DRV_I2C_DMA_ENABLED
+ #endif // #if !defined(DRV_I2C_DMA_ENABLED)
+#endif // #ifdef I2C_V2_DVT
+
+
+#ifndef __DRV_DEBUG_I2C_REG_READ_WRITE__
+#define DRV_I2C_ClearBits16(addr, data) DRV_ClearBits(addr,data)
+#define DRV_I2C_SetBits16(addr, data) DRV_SetBits(addr,data)
+#define DRV_I2C_WriteReg16(addr, data) DRV_WriteReg(addr, data)
+#define DRV_I2C_ReadReg16(addr) DRV_Reg(addr)
+#define DRV_I2C_SetData16(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#else // #ifndef __DRV_DEBUG_PMU_REG_READ_WRITE__
+#define DRV_I2C_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
+#define DRV_I2C_SetBits16(addr) DRV_DBG_SetBits(addr)
+#define DRV_I2C_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
+#define DRV_I2C_ReadReg16(addr) DRV_DBG_Reg(addr)
+#define DRV_I2C_SetData16(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#endif // #ifndef __DRV_DEBUG_PMU_REG_READ_WRITE__
+
+#define SCCB_MAXIMUM_TRANSACTION_LENGTH 8 // SCCB backward compatible
+
+
+#if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
+#define I2C_CLOCK_RATE 15360 //15.36MHz
+#elif defined(DRV_I2C_CLOCK_RATE_3_000_MHZ)
+#define I2C_CLOCK_RATE 3000 //3.0MHz
+#else // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
+#define I2C_CLOCK_RATE 13000 //13MHz
+#endif // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
+
+
+#if (defined(DRV_I2C_DMA_ENABLED))
+#include "dma_hw.h"
+ #include "dma_sw.h"
+ #if (defined(__DMA_API_V2__))
+ #define DRV_I2C_USE_DMA_V2_API // 76 and later chips are all applied V2 DMA API
+ #else
+ #define DRV_I2C_USE_DMA_V1_API // 35, 38, 39, 53, 68, 36 chips are all applied V1 DMA API
+ #endif
+#endif // #if (defined(DRV_I2C_DMA_ENABLED))
+
+// Some common structures are defined in sccb.h
+
+typedef enum
+{
+ I2C_TRANSACTION_COMPLETE,
+ I2C_TRANSACTION_FAIL,
+ I2C_TRANSACTION_IS_BUSY,
+ I2C_TRANSACTION_ACKERR,
+ I2C_TRANSACTION_HS_NACKERR,
+ I2C_TRANSACTION_SUCCESS,
+ I2C_TRANSACTION_TIMEOUT
+}I2C_TRANSACTION_RESULT;
+
+
+typedef enum
+{
+ I2C_IDLE_STATE = 0,
+ I2C_READY_STATE,
+ I2C_BUSY_STATE
+}I2C_STATE;
+
+/* Transaction mode for new SCCB APIs */
+typedef enum
+{
+ I2C_TRANSACTION_FAST_MODE,
+ I2C_TRANSACTION_HIGH_SPEED_MODE
+}I2C_TRANSACTION_MODE;
+
+/* Transaction type for batch transaction */
+typedef enum
+{
+ I2C_TRANSACTION_WRITE,
+ I2C_TRANSACTION_READ,
+ I2C_TRANSACTION_CONT_WRITE,
+ I2C_TRANSACTION_CONT_READ,
+ I2C_TRANSACTION_WRITE_AND_READ
+}I2C_TRANSACTION_TYPE;
+
+typedef struct
+{
+ kal_uint8 *data;
+ kal_uint32 data_len;
+}i2c_single_write_struct, i2c_single_read_struct;
+/* For I2C_CMD_CONT_WRITE, I2C_CMD_CONT_READ command. */
+typedef struct
+{
+ kal_uint8 *data;
+ kal_uint32 data_len;
+ kal_uint32 transfer_num;
+}i2c_cont_write_struct, i2c_cont_read_struct;
+/* For I2C_CMD_WRITE_AND_READ command. */
+typedef struct
+{
+ kal_uint8 *indata;
+ kal_uint32 indata_len;
+ kal_uint8 *outdata;
+ kal_uint32 outdata_len;
+}i2c_write_and_read_struct;
+/* */
+typedef union
+{
+ i2c_single_write_struct single_write;
+ i2c_single_read_struct single_read;
+ i2c_cont_write_struct cont_write;
+ i2c_cont_write_struct cont_read;
+ i2c_write_and_read_struct write_and_read;
+}i2c_transaction_data_struct;
+/* For I2C_CMD_SINGLE_BATCH command. */
+typedef struct
+{
+ I2C_TRANSACTION_TYPE transaction_type;
+ i2c_transaction_data_struct transaction_data;
+}i2c_batch_data_struct;
+
+typedef enum
+{
+#if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
+ // Module source clock is 15.36Mhz
+ I2C_100KB, //99.74KB
+ I2C_200KB, //196.9KB
+ I2C_300KB, //295.4KB
+ I2C_400KB, //384.0KB
+ /* HS Mode */
+ I2C_960KB, //960.0KB
+ I2C_1280KB, //1280.0KB
+ I2C_1536KB, //1536.0KB
+ I2C_1920KB, //1920.0KB
+ I2C_2560KB, //2560.0KB
+ I2C_3840KB //3840.0KB
+#elif defined(DRV_I2C_CLOCK_RATE_3_000_MHZ)
+ // Module source clock is 3.0Mhz
+ I2C_100KB, //100.0KB
+ I2C_200KB, //196.9KB
+ I2C_400KB, //384.0KB
+ /* HS Mode */
+ I2C_750KB, //750.0KB
+ I2C_1500KB //1500.0KB
+#else // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
+ // Module source clock is 13Mhz
+ I2C_100KB, //101.5KB
+ I2C_200KB, //203.1KB
+ I2C_300KB, //295.5KB
+ I2C_400KB, //382.4KB
+ /* HS Mode */
+ I2C_460KB, //464.3KB
+ I2C_540KB, //541.7KB
+ I2C_650KB, //650.0KB
+ I2C_720KB, //722.0KB
+
+ I2C_810KB, //812.5KB
+ I2C_930KB, //928.6KB
+ I2C_1100KB, //1083.3KB
+ I2C_1300KB, //1300.0KB
+ I2C_1625KB, //1625.0KB
+ I2C_2150KB, //2166.6KB
+ I2C_3250KB //3250.6KB
+#endif // #if defined(DRV_I2C_CLOCK_RATE_15_360_MHZ)
+}I2C_SPEED_ENUM;
+
+typedef struct
+{
+ //kal_uint8 sccb_mode; // Transaction mode for existing SCCB APIs
+
+ kal_bool get_handle_wait; //When get handle wait until the I2C is avaliable
+
+ kal_uint8 slave_address; //the address of the slave device
+
+ kal_uint8 delay_len; //number of half pulse between transfers in a trasaction
+
+ I2C_TRANSACTION_MODE transaction_mode; //I2C_TRANSACTION_FAST_MODE or I2C_TRANSACTION_HIGH_SPEED_MODE
+
+ kal_uint16 Fast_Mode_Speed; //The speed of I2C fast mode(Kb)
+
+ kal_uint16 HS_Mode_Speed; //The speed of I2C high speed mode(Kb)
+
+ #if (defined(DRV_I2C_DMA_ENABLED))
+ kal_bool is_DMA_enabled; //Transaction via DMA instead of 8-byte FIFO
+ #endif // #if (defined(DRV_I2C_DMA_ENABLED))
+
+}i2c_config_struct;
+
+typedef struct
+{
+ i2c_config_struct i2c_config;
+
+ kal_uint8 fs_sample_cnt_div; //these two parameters are used to specify I2C clock rate
+ kal_uint8 fs_step_cnt_div; //half pulse width=step_cnt_div*sample_cnt_div*(1/13Mhz)
+
+ kal_uint8 hs_sample_cnt_div; //these two parameters are used to specify I2C clock rate
+ kal_uint8 hs_step_cnt_div; //half pulse width=step_cnt_div*sample_cnt_div*(1/13Mhz)
+
+ I2C_TRANSACTION_RESULT transaction_result; /* The result of the end of transaction
+ (I2C_TRANSACTION_COMPLETE|I2C_TRANSACTION_FAIL) */
+
+}i2c_handle_struct;
+
+typedef struct
+{
+ volatile I2C_STATE state;
+ DCL_I2C_OWNER owner;
+
+ kal_uint8 number_of_read;
+ kal_uint8* read_buffer;
+
+ #if (defined(DRV_I2C_DMA_ENABLED))
+ kal_bool is_DMA_enabled;
+ #endif // #if (defined(DRV_I2C_DMA_ENABLED))
+
+}i2c_status_struct;
+
+
+
+#ifndef DRV_I2C_OFF
+/* Register Definitions */
+#define REG_I2C_DATA_PORT (I2C_base + 0x00)
+#define REG_I2C_SLAVE_ADDR (I2C_base + 0x04)
+#define REG_I2C_INT_MASK (I2C_base + 0x08)
+#define REG_I2C_INT_STA (I2C_base + 0x0c)
+#define REG_I2C_CONTROL (I2C_base + 0x10)
+#define REG_I2C_TRANSFER_LEN (I2C_base + 0x14)
+#define REG_I2C_TRANSAC_LEN (I2C_base + 0x18)
+#define REG_I2C_DELAY_LEN (I2C_base + 0x1c)
+#define REG_I2C_TIMING (I2C_base + 0x20)
+#define REG_I2C_START (I2C_base + 0x24)
+#define REG_I2C_FIFO_STAT (I2C_base + 0x30)
+#define REG_I2C_FIFO_THRESH (I2C_base + 0x34)
+#define REG_I2C_FIFO_ADDR_CLR (I2C_base + 0x38)
+#define REG_I2C_IO_CONFIG (I2C_base + 0x40)
+#define REG_I2C_MULTI_MASTER (I2C_base + 0x44)
+#define REG_I2C_HS_MODE (I2C_base + 0x48)
+#define REG_I2C_SOFTRESET (I2C_base + 0x50)
+#define REG_I2C_TRANSFER_LEN_AUX (I2C_base + 0x6C) ///new from MT6256E2
+#define REG_I2C_HW_Version (I2C_base + 0x78)
+#define REG_I2C_DBG_STA (I2C_base + 0x64) //only for debug
+#define REG_I2C_TIMEOUT_TIMING (I2C_base + 0x74) //timeout timing reg
+#endif // DRV_I2C_OFF
+
+/* Register masks */
+#define I2C_1_BIT_MASK 0x01
+#define I2C_3_BIT_MASK 0x07
+#define I2C_4_BIT_MASK 0x0f
+#define I2C_6_BIT_MASK 0x3f
+#define I2C_8_BIT_MASK 0xff
+#define I2C_16_BIT_MASK 0xffff
+
+#define I2C_RX_FIFO_THRESH_MASK 0x0007
+#define I2C_RX_FIFO_THRESH_SHIFT 0
+#define I2C_TX_FIFO_THRESH_MASK 0x0700
+#define I2C_TX_FIFO_THRESH_SHIFT 8
+
+#define I2C_AUX_LEN_MASK 0x1f00
+#define I2C_AUX_LEN_SHIFT 8
+
+#define I2C_SAMPLE_CNT_DIV_MASK 0x0700
+#define I2C_SAMPLE_CNT_DIV_SHIFT 8
+#define I2C_DATA_READ_TIME_MASK 0x7000
+#define I2C_DATA_READ_TIME_SHIFT 12
+
+#define I2C_MASTER_READ 0x01
+#define I2C_MASTER_WRITE 0x00
+
+//#define I2C_CTL_MODE_BIT 0x01
+#define I2C_CTL_RS_STOP_BIT 0x02
+#define I2C_CTL_DMA_EN_BIT 0x04
+#define I2C_CTL_CLK_EXT_EN_BIT 0x08
+#define I2C_CTL_DIR_CHANGE_BIT 0x10
+#define I2C_CTL_ACK_ERR_DET_BIT 0x20
+#define I2C_CTL_TRANSFER_LEN_CHG_BIT 0x40
+
+#define I2C_DATA_READ_ADJ_BIT 0x8000
+
+#define I2C_SCL_MODE_BIT 0x01
+#define I2C_SDA_MODE_BIT 0x02
+#define I2C_BUS_DETECT_EN_BIT 0x04
+
+#define I2C_ARBITRATION_BIT 0x01
+#define I2C_CLOCK_SYNC_BIT 0x02
+#define I2C_BUS_BUSY_DET_BIT 0x04
+
+#define I2C_HS_EN_BIT 0x01
+#define I2C_HS_NACK_ERR_DET_EN_BIT 0x02
+#define I2C_HS_MASTER_CODE_MASK 0x0070
+#define I2C_HS_MASTER_CODE_SHIFT 4
+#define I2C_HS_STEP_CNT_DIV_MASK 0x0700
+#define I2C_HS_STEP_CNT_DIV_SHIFT 8
+#define I2C_HS_SAMPLE_CNT_DIV_MASK 0x7000
+#define I2C_HS_SAMPLE_CNT_DIV_SHIFT 12
+
+/* I2C Status */
+#define I2C_FIFO_FULL_STATUS 0x01
+#define I2C_FIFO_EMPTY_STATUS 0x02
+
+/* Register Settings */
+#define SET_I2C_SLAVE_ADDRESS(n,rw) do{DRV_I2C_SetData16(REG_I2C_SLAVE_ADDR, I2C_8_BIT_MASK, (((n>>1)<<1) + rw));} while(0);
+
+#define DISABLE_I2C_INT do{DRV_I2C_WriteReg16(REG_I2C_INT_MASK, 0);} while(0);
+#define ENABLE_I2C_INT do{DRV_I2C_WriteReg16(REG_I2C_INT_MASK,I2C_1_BIT_MASK);} while(0);
+
+#define CLEAR_I2C_STA do{DRV_I2C_WriteReg16(REG_I2C_INT_STA, I2C_4_BIT_MASK);} while(0);
+
+//#define SET_I2C_FAST_SPEED_MODE REG_I2C_CONTROL &= ~I2C_CTL_MODE_BIT;
+//#define SET_I2C_HIGH_SPEED_MODE REG_I2C_CONTROL |= I2C_CTL_MODE_BIT;
+
+#define SET_I2C_ST_BETWEEN_TRANSFER do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_RS_STOP_BIT);} while(0);
+#define SET_I2C_RS_BETWEEN_TRANSFER do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_RS_STOP_BIT);} while(0);
+#define ENABLE_I2C_DMA_TRANSFER do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_DMA_EN_BIT);} while(0);
+#define ENABLE_I2C_CLOCK_EXTENSION do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_CLK_EXT_EN_BIT);} while(0);
+#define ENABLE_I2C_DIR_CHANGE do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_DIR_CHANGE_BIT);} while(0);
+#define ENABLE_I2C_ACK_ERR_DET do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_ACK_ERR_DET_BIT);} while(0);
+#define ENABLE_I2C_TRANSFER_LEN_CHG do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_CTL_TRANSFER_LEN_CHG_BIT);} while(0);
+#define ENABLE_I2C_BUS_BUSY_RESET do{DRV_I2C_SetBits16(REG_I2C_CONTROL, 0x80);} while(0);
+#define ENABLE_I2C_TIMEOUT do{DRV_I2C_SetBits16(REG_I2C_CONTROL, I2C_TIMEOUT);} while(0);
+
+#define DISABLE_I2C_DMA_TRANSFER do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_DMA_EN_BIT);} while(0);
+#define DISABLE_I2C_CLOCK_EXTENSION do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_CLK_EXT_EN_BIT);} while(0);
+#define DISABLE_I2C_DIR_CHANGE do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_DIR_CHANGE_BIT);} while(0);
+#define DISABLE_I2C_ACK_ERR_DET do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_ACK_ERR_DET_BIT);} while(0);
+#define DISABLE_I2C_TRANSFER_LEN_CHG do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_CTL_TRANSFER_LEN_CHG_BIT);} while(0);
+#define DISABLE_I2C_BUS_BUSY_RESET do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, 0x80);} while(0);
+#define DISABLE_I2C_TIMEOUT do{DRV_I2C_ClearBits16(REG_I2C_CONTROL, I2C_TIMEOUT);} while(0);
+
+#ifdef DRV_I2C_MAX_65535_TRANSFER_LENGTH
+#define SET_I2C_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_16_BIT_MASK, (n));} while(0);
+#define SET_I2C_AUX_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN_AUX, I2C_16_BIT_MASK, (n));} while(0);
+#else
+#define SET_I2C_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_8_BIT_MASK, (n));} while(0);
+#define SET_I2C_AUX_TRANSFER_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSFER_LEN, I2C_AUX_LEN_MASK, ((n)<<I2C_AUX_LEN_SHIFT));} while(0);
+#endif
+
+#define SET_I2C_TRANSACTION_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_TRANSAC_LEN, I2C_8_BIT_MASK, (n));} while(0);
+#define SET_I2C_DELAY_LENGTH(n) do{DRV_I2C_SetData16(REG_I2C_DELAY_LEN, I2C_8_BIT_MASK, (n));} while(0);
+
+#define SET_I2C_STEP_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_6_BIT_MASK, (n));} while(0);
+#define SET_I2C_SAMPLE_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_SAMPLE_CNT_DIV_MASK, ((n)<<I2C_SAMPLE_CNT_DIV_SHIFT));} while(0);
+#define SET_I2C_DATA_READ_TIME(n) do{DRV_I2C_SetData16(REG_I2C_TIMING, I2C_DATA_READ_TIME_MASK, ((n)<<I2C_DATA_READ_TIME_SHIFT));} while(0);
+#define ENABLE_I2C_DATA_READ_ADJ do{DRV_I2C_SetBits16(REG_I2C_TIMING, I2C_DATA_READ_ADJ_BIT);} while(0);
+#define DISABLE_I2C_DATA_READ_ADJ do{DRV_I2C_ClearBits16(REG_I2C_TIMING, I2C_DATA_READ_ADJ_BIT);} while(0);
+
+#define START_I2C_TRANSACTION do{DRV_I2C_WriteReg16(REG_I2C_START, 0x01);} while(0);
+
+// #define I2C_FIFO_FULL ((REG_I2C_FIFO_STAT>>1)&0x01)
+// #define I2C_FIFO_EMPTY (REG_I2C_FIFO_STAT & 0x01)
+
+#define SET_I2C_RX_FIFO_THRESH(n) do{DRV_I2C_SetData16(REG_I2C_FIFO_THRESH, I2C_RX_FIFO_THRESH_MASK, ((n)<< I2C_RX_FIFO_THRESH_SHIFT));} while(0);
+#define SET_I2C_TX_FIFO_THRESH(n) do{DRV_I2C_SetData16(REG_I2C_FIFO_THRESH, I2C_TX_FIFO_THRESH_MASK, ((n)<< I2C_TX_FIFO_THRESH_SHIFT));} while(0);
+
+#define CLEAR_I2C_FIFO do{DRV_I2C_WriteReg16(REG_I2C_FIFO_ADDR_CLR, 0x01);} while(0);
+
+#define SET_I2C_SCL_NORMAL_MODE do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_SCL_MODE_BIT);} while(0);
+#define SET_I2C_SCL_WIRED_AND_MODE do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_SCL_MODE_BIT);} while(0);
+#define SET_I2C_SDA_NORMAL_MODE do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_SDA_MODE_BIT);} while(0);
+#define SET_I2C_SDA_WIRED_AND_MODE do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_SDA_MODE_BIT);} while(0);
+#define ENABLE_I2C_BUS_DETECT do{DRV_I2C_SetBits16(REG_I2C_IO_CONFIG, I2C_BUS_DETECT_EN_BIT);} while(0);
+#define DISABLE_I2C_BUS_DETECT do{DRV_I2C_ClearBits16(REG_I2C_IO_CONFIG, I2C_BUS_DETECT_EN_BIT);} while(0);
+
+#define ENABLE_I2C_CLOCK_SYNC do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_ARBITRATION_BIT);} while(0);
+#define ENABLE_DATA_ARBITION do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_CLOCK_SYNC_BIT);} while(0);
+#define ENABLE_I2C_BUS_BUSY_DET do{DRV_I2C_SetBits16(REG_I2C_MULTI_MASTER, I2C_BUS_BUSY_DET_BIT);} while(0);
+#define DISABLE_I2C_CLOCK_SYNC do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_ARBITRATION_BIT);} while(0);
+#define DISABLE_DATA_ARBITION do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_CLOCK_SYNC_BIT);} while(0);
+#define DISABLE_I2C_BUS_BUSY_DET do{DRV_I2C_ClearBits16(REG_I2C_MULTI_MASTER, I2C_BUS_BUSY_DET_BIT);} while(0);
+
+#define SET_I2C_HIGH_SPEED_MODE_800KB do{DRV_I2C_WriteReg16(REG_I2C_HS_MODE, 0x0703);} while(0);
+#define SET_I2C_HIGH_SPEED_MODE_1000KB do{DRV_I2C_WriteReg16(REG_I2C_HS_MODE, 0x0503);} while(0);
+
+#define SET_I2C_FAST_MODE do{DRV_I2C_ClearBits16(REG_I2C_HS_MODE, I2C_HS_EN_BIT);} while(0);
+#define SET_I2C_HS_MODE do{DRV_I2C_SetBits16(REG_I2C_HS_MODE, I2C_HS_EN_BIT);} while(0);
+#define ENABLE_I2C_NAKERR_DET do{DRV_I2C_SetBits16(REG_I2C_HS_MODE, I2C_HS_NACK_ERR_DET_EN_BIT);} while(0);
+#define DISABLE_I2C_NAKERR_DET do{DRV_I2C_ClearBits16(REG_I2C_HS_MODE, I2C_HS_NACK_ERR_DET_EN_BIT);} while(0);
+#define SET_I2C_HS_MASTER_CODE(n) do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_MASTER_CODE_MASK, ((n)<<I2C_HS_MASTER_CODE_SHIFT));} while(0);
+
+#define SET_I2C_HS_STEP_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_STEP_CNT_DIV_MASK, ((n)<<I2C_HS_STEP_CNT_DIV_SHIFT));} while(0);
+#define SET_I2C_HS_SAMPLE_CNT_DIV(n) do{DRV_I2C_SetData16(REG_I2C_HS_MODE, I2C_HS_SAMPLE_CNT_DIV_MASK, ((n)<<I2C_HS_SAMPLE_CNT_DIV_SHIFT));} while(0);
+
+#define RESET_I2C do{DRV_I2C_WriteReg16(REG_I2C_SOFTRESET, 0x01);} while(0);
+
+//---------------- DMA ----------------
+#if defined(DRV_I2C_DIRECT_CONFIG_DMA_REGISTER)
+
+//#define DMA_base 0x80030000 -->defined in /inc/reg_base.h
+
+/* Regidter Definitions */
+#define REG_DMA_CHANNEL_CONTROL(c) *((volatile unsigned int *) (DMA_base + 0x14+ (c<<8)))
+#define REG_DMA_CHANNEL_START(c) *((volatile unsigned int *) (DMA_base + 0x18+ (c<<8)))
+#define REG_DMA_PROG_ADDR(c) *((volatile unsigned int *) (DMA_base + 0x2c+ (c<<8)))
+#define REG_DMA_TRANSFER_COUNT(c) *((volatile unsigned int *) (DMA_base + 0x10+ (c<<8)))
+
+/* Master Definitions*/
+#define DMA_MASTER_I2C_TX DMA_CON_MASTER_I2CTX
+#define DMA_MASTER_I2C_RX DMA_CON_MASTER_I2CRX
+#define DMA_MASTER_IRDA_TX 0x02
+#define DMA_MASTER_IRDA_RX 0x03
+
+#define DMA_I2C_TX_CHANNEL 4
+#define DMA_I2C_RX_CHANNEL 5
+
+/* Register masks */
+#define DMA_CON_DIR_MASK 0x40000
+#define DMA_CON_MAS_MASK 0x01f00000
+
+#define I2C_SET_TX_DMA_CONTROL(c,m) REG_DMA_CHANNEL_CONTROL(c) = 0x00000014;\
+ REG_DMA_CHANNEL_CONTROL(c) |= (((m)<<20) & DMA_CON_MAS_MASK);
+
+#define I2C_SET_RX_DMA_CONTROL(c,m) REG_DMA_CHANNEL_CONTROL(c) = 0x00040018;\
+ REG_DMA_CHANNEL_CONTROL(c) |= (((m)<<20) & DMA_CON_MAS_MASK);
+
+#define I2C_SET_DMA_PROGRAMMABLE_ADDR(c,addr) REG_DMA_PROG_ADDR(c) = (addr);
+#define I2C_SET_DMA_TRANSFER_COUNT(c,size) REG_DMA_TRANSFER_COUNT(c)= size ;
+#define I2C_START_DMA_TRANSFER(c) REG_DMA_CHANNEL_START(c) = 0x8000;
+#define I2C_STOP_DMA_TRANSFER(c) REG_DMA_CHANNEL_START(c) = 0;
+
+#endif // #if defined(DRV_I2C_DIRECT_CONFIG_DMA_REGISTER)
+
+/****** SW definitions******/
+#define I2C_READ_BIT 0x01
+#define I2C_WRITE_BIT 0x00
+
+#define I2C_TRANSAC_COMPLETE 0x01
+#define I2C_TRANSAC_ACK_ERR 0x02
+#define I2C_HS_NACK_ERR 0x04
+#define I2C_TIMEOUT 0x10
+
+//extern kal_bool dcl_i2c_init_done_flag;
+//extern i2c_handle_struct i2c_handle[DCL_I2C_NUM_OF_OWNER];
+
+void dcl_i2c_init(void);
+extern void dcl_i2c_hw_cfg (DCL_I2C_OWNER owner, I2C_TRANSACTION_TYPE type, kal_uint8* write_buffer, kal_uint32 write_len, kal_uint8* read_buffer, kal_uint32 read_len, kal_uint32 transfer_num);
+void dcl_i2c_set_transaction_speed(DCL_I2C_OWNER owner,I2C_TRANSACTION_MODE mode,kal_uint16* Fast_Mode_Speed,kal_uint16* HS_Mode_Speed);
+extern kal_uint32 dcl_i2c_wait_transaction_complete_and_lock(DCL_I2C_OWNER owner);
+void dcl_i2c_wait_transaction_complete(kal_uint32 savedMask);
+#if defined(DRV_I2C_BATCH_TRANSACTION_SUPPORT)
+I2C_TRANSACTION_RESULT dcl_i2c_get_batch_transaction_result(DCL_I2C_OWNER owner,kal_uint32* batch_num);
+I2C_TRANSACTION_RESULT dcl_i2c_batch_transaction(DCL_I2C_OWNER owner, i2c_batch_data_struct *batch_data, kal_uint32 batch_num);
+#endif // #if (defined(DRV_I2C_DMA_ENABLED))
+
+#endif // #if (defined(DRV_I2C_25_SERIES))
+
+void CameraSccbPadEnable(kal_bool On);
+#endif // #ifndef __I2C_H__
+
diff --git a/mcu/driver/peripheral/inc/i2c_dual_hw.h b/mcu/driver/peripheral/inc/i2c_dual_hw.h
new file mode 100644
index 0000000..cc37d9b
--- /dev/null
+++ b/mcu/driver/peripheral/inc/i2c_dual_hw.h
@@ -0,0 +1,476 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * i2c_dual_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for I2C DUAL driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _I2C_DUAL_HW_H
+#define _I2C_DUAL_HW_H
+#include "drv_features.h"
+
+#include "drv_comm.h"
+#include "reg_base.h"
+
+#if defined(DRV_I2C_DUAL)
+
+#ifndef __DRV_DEBUG_I2C_DUAL_REG_READ_WRITE__
+#define I2C_DUAL_DRV_ClearBits16(addr, data) DRV_ClearBits(addr,data)
+#define I2C_DUAL_DRV_SetBits16(addr, data) DRV_SetBits(addr,data)
+#define I2C_DUAL_DRV_WriteReg16(addr, data) DRV_WriteReg(addr, data)
+#define I2C_DUAL_DRV_ReadReg16(addr) DRV_Reg(addr)
+#define I2C_DUAL_DRV_ClearBits32(addr, data) DRV_ClearBits32(addr, data)
+#else // #ifndef __DRV_DEBUG_I2C_DUAL_REG_READ_WRITE__
+#define I2C_DUAL_DRV_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
+#define I2C_DUAL_DRV_SetBits16(addr) DRV_DBG_SetBits(addr)
+#define I2C_DUAL_DRV_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
+#define I2C_DUAL_DRV_ReadReg16(addr) DRV_DBG_Reg(addr)
+#define I2C_DUAL_DRV_ClearBits32(addr, data) DRV_DBG_ClearBits32(addr, data)
+#endif // #ifndef __DRV_DEBUG_I2C_DUAL_REG_READ_WRITE__
+
+
+
+// I2CD means I2C DUAL
+
+#define I2CD_CH1_DATA_PORT (I2C_DUAL_base + 0x00)
+#define I2CD_CH1_SLAVE_ADDR (I2C_DUAL_base + 0x04)
+#define I2CD_INTR_MASK (I2C_DUAL_base + 0x08)
+#define I2CD_INTR_STAT (I2C_DUAL_base + 0x0C)
+#define I2CD_CH1_CTRL (I2C_DUAL_base + 0x10)
+#define I2CD_CH1_TRANSFER_LEN (I2C_DUAL_base + 0x14)
+#define I2CD_CH1_TRANSAC_LEN (I2C_DUAL_base + 0x18)
+#define I2CD_CH1_DELAY_LEN (I2C_DUAL_base + 0x1C)
+#define I2CD_CH1_TIMING (I2C_DUAL_base + 0x20)
+#define I2CD_CH1_START (I2C_DUAL_base + 0x24)
+#define I2CD_CH1_FIFO_STAT (I2C_DUAL_base + 0x30)
+#define I2CD_CH1_FIFO_THRESH (I2C_DUAL_base + 0x34)
+#define I2CD_CH1_FIFO_ADDR_CLR (I2C_DUAL_base + 0x38)
+#define I2CD_IO_CONFIG (I2C_DUAL_base + 0x40)
+#define I2CD_CH1_HS (I2C_DUAL_base + 0x48)
+#define I2CD_SOFTRESET (I2C_DUAL_base + 0x50)
+#if defined(MT6329)
+#define I2CD_IRQSEL (I2C_DUAL_base + 0x60)
+#endif // End of #if defined(MT6329)
+#define I2CD_CH2_DATA_PORT (I2C_DUAL_base + 0x80)
+#define I2CD_CH2_SLAVE_ADDR (I2C_DUAL_base + 0x84)
+#define I2CD_CH2_CTRL (I2C_DUAL_base + 0x90)
+#define I2CD_CH2_TRANSFER_LEN (I2C_DUAL_base + 0x94)
+#define I2CD_CH2_TRANSAC_LEN (I2C_DUAL_base + 0x98)
+#define I2CD_CH2_DELAY_LEN (I2C_DUAL_base + 0x9C)
+#define I2CD_CH2_TIMING (I2C_DUAL_base + 0xA0)
+#define I2CD_CH2_START (I2C_DUAL_base + 0xA4)
+#define I2CD_CH2_FIFO_STAT (I2C_DUAL_base + 0xB0)
+#define I2CD_CH2_FIFO_ADDR_CLR (I2C_DUAL_base + 0xB8)
+
+// 0x00
+#define I2CD_CH1_DATA_PORT_MASK 0x00FF
+#define I2CD_CH1_DATA_PORT_SHIFT 0
+
+// 0x04
+#define I2CD_CH1_SLAVE_ADDR_MASK 0x00FF
+#define I2CD_CH1_SLAVE_ADDR_SHIFT 0
+
+// 0x08
+#define I2CD_INTR_MASK_CH1_TRANS_COMP_MASK 0x0001
+#define I2CD_INTR_MASK_CH1_TRANS_COMP_SHIFT 0
+#define I2CD_INTR_MASK_CH1_ACK_ERR_MASK 0x0002
+#define I2CD_INTR_MASK_CH1_ACK_ERR_SHIFT 1
+#define I2CD_INTR_MASK_CH1_HSNAK_ERR_MASK 0x0004
+#define I2CD_INTR_MASK_CH1_HSNAK_ERR_SHIFT 2
+#define I2CD_INTR_MASK_CH2_TRANS_COMP_MASK 0x0010
+#define I2CD_INTR_MASK_CH2_TRANS_COMP_SHIFT 4
+#define I2CD_INTR_MASK_CH2_ACK_ERR_MASK 0x0020
+#define I2CD_INTR_MASK_CH2_ACK_ERR_SHIFT 5
+
+// 0x0C
+#define I2CD_INTR_STAT_CH1_TRANS_COMP_MASK 0x0001
+#define I2CD_INTR_STAT_CH1_TRANS_COMP_SHIFT 0
+#define I2CD_INTR_STAT_CH1_ACK_ERR_MASK 0x0002
+#define I2CD_INTR_STAT_CH1_ACK_ERR_SHIFT 1
+#define I2CD_INTR_STAT_CH1_HSNAK_ERR_MASK 0x0004
+#define I2CD_INTR_STAT_CH1_HSNAK_ERR_SHIFT 2
+#define I2CD_INTR_STAT_CH2_TRANS_COMP_MASK 0x0010
+#define I2CD_INTR_STAT_CH2_TRANS_COMP_SHIFT 4
+#define I2CD_INTR_STAT_CH2_ACK_ERR_MASK 0x0020
+#define I2CD_INTR_STAT_CH2_ACK_ERR_SHIFT 5
+
+// 0x10
+#define I2CD_CH1_CTRL_RESTART_MASK 0x0002
+#define I2CD_CH1_CTRL_RESTART_SHIFT 1
+#define I2CD_CH1_CTRL_DMAEN_MASK 0x0004
+#define I2CD_CH1_CTRL_DMAEN_SHIFT 2
+#define I2CD_CH1_CTRL_CLK_EXT_EN_MASK 0x0008
+#define I2CD_CH1_CTRL_CLK_EXT_EN_SHIFT 3
+#define I2CD_CH1_CTRL_DIR_CHANGE_MASK 0x0010
+#define I2CD_CH1_CTRL_DIR_CHANGE_SHIFT 4
+#define I2CD_CH1_CTRL_ACKERR_DET_EN_MASK 0x0020
+#define I2CD_CH1_CTRL_ACKERR_DET_EN_SHIFT 5
+#define I2CD_CH1_CTRL_TRANSFER_LEN_CHANGE_MASK 0x0040
+#define I2CD_CH1_CTRL_TRANSFER_LEN_CHANGE_SHIFT 6
+
+// 0x14
+#define I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_MASK 0x00FF
+#define I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_SHIFT 0
+#define I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_AUX_MASK 0x1F00
+#define I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_AUX_SHIFT 8
+
+// 0x18
+#define I2CD_CH1_TRANSAC_LEN_TRANSAC_LEN_MASK 0x00FF
+#define I2CD_CH1_TRANSAC_LEN_TRANSAC_LEN_SHIFT 0
+
+// 0x1C
+#define I2CD_CH1_DELAY_LEN_DELAY_LEN_MASK 0x00FF
+#define I2CD_CH1_DELAY_LEN_DELAY_LEN_SHIFT 0
+
+// 0x20
+#define I2CD_CH1_TIMING_STEP_CNT_DIV_MASK 0x003F
+#define I2CD_CH1_TIMING_STEP_CNT_DIV_SHIFT 0
+#define I2CD_CH1_TIMING_SAMPLE_CNT_DIV_MASK 0x0700
+#define I2CD_CH1_TIMING_SAMPLE_CNT_DIV_SHIFT 8
+#define I2CD_CH1_TIMING_DATA_READ_MASK 0x7000
+#define I2CD_CH1_TIMING_DATA_READ_SHIFT 12
+#define I2CD_CH1_TIMING_DATA_READ_ADJ_MASK 0x8000
+#define I2CD_CH1_TIMING_DATA_READ_ADJ_SHIFT 15
+
+// 0x24
+#define I2CD_CH1_START_START_MASK 0x0001
+#define I2CD_CH1_START_START_SHIFT 0
+
+// 0x30
+#define I2CD_CH1_FIFO_STAT_RD_EMPTY_MASK 0x0001
+#define I2CD_CH1_FIFO_STAT_RD_EMPTY_SHIFT 0
+#define I2CD_CH1_FIFO_STAT_WR_FULL_MASK 0x0002
+#define I2CD_CH1_FIFO_STAT_WR_FULL_SHIFT 1
+#define I2CD_CH1_FIFO_STAT_OFFSET_MASK 0x00F0
+#define I2CD_CH1_FIFO_STAT_OFFSET_SHIFT 4
+#define I2CD_CH1_FIFO_STAT_WR_ADDR_MASK 0x0F00
+#define I2CD_CH1_FIFO_STAT_WR_ADDR_SHIFT 8
+#define I2CD_CH1_FIFO_STAT_RD_ADDR_MASK 0xF000
+#define I2CD_CH1_FIFO_STAT_RD_ADDR_SHIFT 12
+
+// 0x34
+#define I2CD_CH1_FIFO_THRESH_RX_TRIG_MASK 0x0007
+#define I2CD_CH1_FIFO_THRESH_RX_TRIG_SHIFT 0
+#define I2CD_CH1_FIFO_THRESH_TX_TRIG_MASK 0x0700
+#define I2CD_CH1_FIFO_THRESH_TX_TRIG_SHIFT 8
+
+// 0x38
+#define I2CD_CH1_FIFO_ADDR_CLR_CR_MASK 0x0001
+#define I2CD_CH1_FIFO_ADDR_CLR_CR_SHIFT 0
+
+// 0x40
+#define I2CD_IO_CONFIG_SCL_IO_MASK 0x0001
+#define I2CD_IO_CONFIG_SCL_IO_SHIFT 0
+#define I2CD_IO_CONFIG_SDA_IO_MASK 0x0002
+#define I2CD_IO_CONFIG_SDA_IO_SHIFT 1
+#define I2CD_IO_CONFIG_SYNC_EN_MASK 0x0004
+#define I2CD_IO_CONFIG_SYNC_EN_SHIFT 2
+#define I2CD_IO_CONFIG_IDLE_OE_EN_MASK 0x0008 // MT6575
+#define I2CD_IO_CONFIG_IDLE_OE_SIFT 3 // MT6575
+
+// 0x48
+#define I2CD_CH1_HS_HS_EN_MASK 0x0001
+#define I2CD_CH1_HS_HS_EN_SHIFT 0
+#define I2CD_CH1_HS_HS_NAK_ERR_DET_EN_MASK 0x0002
+#define I2CD_CH1_HS_HS_NAK_ERR_DET_EN_SHIFT 1
+#define I2CD_CH1_HS_MASTER_CODE_MASK 0x0070
+#define I2CD_CH1_HS_MASTER_CODE_SHIFT 4
+#define I2CD_CH1_HS_HS_STEP_CNT_DIV_MASK 0x0700
+#define I2CD_CH1_HS_HS_STEP_CNT_DIV_SHIFT 8
+#define I2CD_CH1_HS_HS_SAMPLE_CNT_DIV_MASK 0x7000
+#define I2CD_CH1_HS_HS_SAMPLE_CNT_DIV_SHIFT 12
+
+// 0x50
+#define I2CD_SOFTRESET_SOFTRESET_MASK 0x0001
+#define I2CD_SOFTRESET_SOFTRESET_SHIFT 0
+
+// 0x60
+#define I2CD_IRQ_SEL_IRQ_SEL_MASK 0x0001 // MT6575
+#define I2CD_IRQ_SEL_IRQ_SEL_SHIFT 0 // MT6575
+
+// 0x80
+#define I2CD_CH2_DATA_PORT_MASK 0x00FF
+#define I2CD_CH2_DATA_PORT_SHIFT 0
+
+// 0x84
+#define I2CD_CH2_SLAVE_ADDR_MASK 0x00FF
+#define I2CD_CH2_SLAVE_ADDR_SHIFT 0
+
+// 0x90
+#define I2CD_CH2_CTRL_RESTART_MASK 0x0002
+#define I2CD_CH2_CTRL_RESTART_SHIFT 1
+#define I2CD_CH2_CTRL_CLK_EXT_EN_MASK 0x0008
+#define I2CD_CH2_CTRL_CLK_EXT_EN_SHIFT 3
+#define I2CD_CH2_CTRL_DIR_CHANGE_MASK 0x0010
+#define I2CD_CH2_CTRL_DIR_CHANGE_SHIFT 4
+#define I2CD_CH2_CTRL_ACKERR_DET_EN_MASK 0x0020
+#define I2CD_CH2_CTRL_ACKERR_DET_EN_SHIFT 5
+#define I2CD_CH2_CTRL_TRANSFER_LEN_CHANGE_MASK 0x0040
+#define I2CD_CH2_CTRL_TRANSFER_LEN_CHANGE_SHIFT 6
+#define I2CD_CH2_CTRL_CH_WAIT_EN_MASK 0x0080
+#define I2CD_CH2_CTRL_CH_WAIT_EN_SHIFT 7
+
+// 0x94
+#define I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_MASK 0x0007
+#define I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_SHIFT 0
+#define I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_AUX_MASK 0x0700
+#define I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_AUX_SHIFT 8
+
+// 0x98
+#define I2CD_CH2_TRANSAC_LEN_TRANSAC_LEN_MASK 0x0007
+#define I2CD_CH2_TRANSAC_LEN_TRANSAC_LEN_SHIFT 0
+
+// 0x9C
+#define I2CD_CH2_DELAY_LEN_DELAY_LEN_MASK 0x0003
+#define I2CD_CH2_DELAY_LEN_DELAY_LEN_SHIFT 0
+
+// 0xA0
+#define I2CD_CH2_TIMING_STEP_CNT_DIV_MASK 0x003F
+#define I2CD_CH2_TIMING_STEP_CNT_DIV_SHIFT 0
+#define I2CD_CH2_TIMING_SAMPLE_CNT_DIV_MASK 0x0700
+#define I2CD_CH2_TIMING_SAMPLE_CNT_DIV_SHIFT 8
+#define I2CD_CH2_TIMING_DATA_READ_MASK 0x7000
+#define I2CD_CH2_TIMING_DATA_READ_SHIFT 12
+#define I2CD_CH2_TIMING_DATA_READ_ADJ_MASK 0x8000
+#define I2CD_CH2_TIMING_DATA_READ_ADJ_SHIFT 15
+
+// 0xA4
+#define I2CD_CH2_START_START_MASK 0x0001
+#define I2CD_CH2_START_START_SHIFT 0
+
+// 0xB0
+#define I2CD_CH2_FIFO_STAT_RD_EMPTY_MASK 0x0001
+#define I2CD_CH2_FIFO_STAT_RD_EMPTY_SHIFT 0
+#define I2CD_CH2_FIFO_STAT_WR_FULL_MASK 0x0002
+#define I2CD_CH2_FIFO_STAT_WR_FULL_SHIFT 1
+#define I2CD_CH2_FIFO_STAT_OFFSET_MASK 0x00F0
+#define I2CD_CH2_FIFO_STAT_OFFSET_SHIFT 4
+#define I2CD_CH2_FIFO_STAT_WR_ADDR_MASK 0x0F00
+#define I2CD_CH2_FIFO_STAT_WR_ADDR_SHIFT 8
+#define I2CD_CH2_FIFO_STAT_RD_ADDR_MASK 0xF000
+#define I2CD_CH2_FIFO_STAT_RD_ADDR_SHIFT 12
+
+// 0xB8
+#define I2CD_CH2_FIFO_ADDR_CLR_CR_MASK 0x0001
+#define I2CD_CH2_FIFO_ADDR_CLR_CR_SHIFT 0
+
+///////////////////////////////////////////////////////////////////////////////
+// Ch1 macros
+#define I2C_DUAL_CH1_CLEAR_FIFO(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH1_FIFO_ADDR_CLR, (kal_uint16)1)
+#define I2C_DUAL_CH1_CLEAR_INTR_STAT(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_DUAL_DRV_ReadReg16(I2CD_INTR_STAT);\
+ tmp &= (I2CD_INTR_STAT_CH1_TRANS_COMP_MASK | I2CD_INTR_STAT_CH1_ACK_ERR_MASK | I2CD_INTR_STAT_CH1_HSNAK_ERR_MASK);\
+ tmp |= (val);\
+ I2C_DUAL_DRV_WriteReg16(I2CD_INTR_STAT, tmp);\
+}
+#define I2C_DUAL_CH1_SET_SLAVE_ADDR(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH1_SLAVE_ADDR, (kal_uint16)val)
+#define I2C_DUAL_CH1_SET_TRANSFER_LEN(len1, len2) {\
+ kal_uint16 tmp;\
+ tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH1_TRANSFER_LEN);\
+ tmp &= ~(I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_MASK | I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_AUX_MASK);\
+ tmp |= ((kal_uint16)len1 << I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_SHIFT);\
+ tmp |= ((kal_uint16)len2 << I2CD_CH1_TRANSFER_LEN_TRANSFER_LEN_AUX_SHIFT);\
+ I2C_DUAL_DRV_WriteReg16(I2CD_CH1_TRANSFER_LEN, tmp);\
+}
+#define I2C_DUAL_CH1_SET_TIMING(sample_cnt, step_cnt) {\
+ kal_uint16 tmp;\
+ tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH1_TIMING);\
+ tmp &= ~(I2CD_CH1_TIMING_STEP_CNT_DIV_MASK | I2CD_CH1_TIMING_SAMPLE_CNT_DIV_MASK);\
+ tmp |= ((kal_uint16)sample_cnt << I2CD_CH1_TIMING_SAMPLE_CNT_DIV_SHIFT);\
+ tmp |= ((kal_uint16)step_cnt << I2CD_CH1_TIMING_STEP_CNT_DIV_SHIFT);\
+ I2C_DUAL_DRV_WriteReg16(I2CD_CH1_TIMING, tmp);\
+}
+
+#define I2C_DUAL_CH1_SET_TRANSAC_LEN(len) I2C_DUAL_DRV_WriteReg16(I2CD_CH1_TRANSAC_LEN, (kal_uint16)len);
+#define I2C_DUAL_CH1_SET_DIR_CHANGE(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH1_CTRL);\
+ tmp &= ~I2CD_CH1_CTRL_DIR_CHANGE_MASK;\
+ tmp |= ((kal_uint16)val << I2CD_CH1_CTRL_DIR_CHANGE_SHIFT);\
+ I2C_DUAL_DRV_WriteReg16(I2CD_CH1_CTRL, tmp);\
+}
+
+#define I2C_DUAL_CH1_SET_RESTART(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH1_CTRL);\
+ tmp &= ~I2CD_CH1_CTRL_RESTART_MASK;\
+ tmp |= ((kal_uint16)val << I2CD_CH1_CTRL_RESTART_SHIFT);\
+ I2C_DUAL_DRV_WriteReg16(I2CD_CH1_CTRL, tmp);\
+}
+
+#define I2C_DUAL_CH1_SET_INTR(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_DUAL_DRV_ReadReg16(I2CD_INTR_MASK);\
+ tmp |= (val & (I2CD_INTR_MASK_CH1_TRANS_COMP_MASK | I2CD_INTR_MASK_CH1_ACK_ERR_MASK | I2CD_INTR_MASK_CH1_HSNAK_ERR_MASK));\
+ I2C_DUAL_DRV_WriteReg16(I2CD_INTR_MASK, (kal_uint16)tmp);\
+}
+
+#define I2C_DUAL_CH1_CLR_INTR(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_DUAL_DRV_ReadReg16(I2CD_INTR_MASK);\
+ tmp &= ~(val & (I2CD_INTR_MASK_CH1_TRANS_COMP_MASK | I2CD_INTR_MASK_CH1_ACK_ERR_MASK | I2CD_INTR_MASK_CH1_HSNAK_ERR_MASK) );\
+ I2C_DUAL_DRV_WriteReg16(I2CD_INTR_MASK, (kal_uint16)tmp);\
+}
+
+
+#define I2C_DUAL_CH1_SET_DATA_PORT(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH1_DATA_PORT, (kal_uint16)val)
+#define I2C_DUAL_CH1_SET_START(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH1_START, I2CD_CH1_START_START_MASK);
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Ch2 macros
+#define I2C_DUAL_CH2_CLEAR_FIFO(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH2_FIFO_ADDR_CLR, (kal_uint16)1)
+#define I2C_DUAL_CH2_CLEAR_INTR_STAT(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_DUAL_DRV_ReadReg16(I2CD_INTR_STAT);\
+ tmp &= (I2CD_INTR_STAT_CH2_TRANS_COMP_MASK | I2CD_INTR_STAT_CH2_ACK_ERR_MASK);\
+ tmp |= (val);\
+ I2C_DUAL_DRV_WriteReg16(I2CD_INTR_STAT, tmp);\
+}
+#define I2C_DUAL_CH2_SET_SLAVE_ADDR(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH2_SLAVE_ADDR, (kal_uint16)val)
+#define I2C_DUAL_CH2_SET_TRANSFER_LEN(len1, len2) {\
+ kal_uint16 tmp;\
+ tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH2_TRANSFER_LEN);\
+ tmp &= ~(I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_MASK | I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_AUX_MASK);\
+ tmp |= ((kal_uint16)len1 << I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_SHIFT);\
+ tmp |= ((kal_uint16)len2 << I2CD_CH2_TRANSFER_LEN_TRANSFER_LEN_AUX_SHIFT);\
+ I2C_DUAL_DRV_WriteReg16(I2CD_CH2_TRANSFER_LEN, tmp);\
+}
+#define I2C_DUAL_CH2_SET_TIMING(sample_cnt, step_cnt) {\
+ kal_uint16 tmp;\
+ tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH2_TIMING);\
+ tmp &= ~(I2CD_CH2_TIMING_STEP_CNT_DIV_MASK | I2CD_CH2_TIMING_SAMPLE_CNT_DIV_MASK);\
+ tmp |= ((kal_uint16)sample_cnt << I2CD_CH2_TIMING_SAMPLE_CNT_DIV_SHIFT);\
+ tmp |= ((kal_uint16)step_cnt << I2CD_CH2_TIMING_STEP_CNT_DIV_SHIFT);\
+ I2C_DUAL_DRV_WriteReg16(I2CD_CH2_TIMING, tmp);\
+}
+
+#define I2C_DUAL_CH2_SET_TRANSAC_LEN(len) I2C_DUAL_DRV_WriteReg16(I2CD_CH2_TRANSAC_LEN, (kal_uint16)len);
+#define I2C_DUAL_CH2_SET_DIR_CHANGE(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH2_CTRL);\
+ tmp &= ~I2CD_CH2_CTRL_DIR_CHANGE_MASK;\
+ tmp |= ((kal_uint16)val << I2CD_CH2_CTRL_DIR_CHANGE_SHIFT);\
+ I2C_DUAL_DRV_WriteReg16(I2CD_CH2_CTRL, tmp);\
+}
+
+#define I2C_DUAL_CH2_SET_RESTART(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_DUAL_DRV_ReadReg16(I2CD_CH2_CTRL);\
+ tmp &= ~I2CD_CH2_CTRL_RESTART_MASK;\
+ tmp |= ((kal_uint16)val << I2CD_CH2_CTRL_RESTART_SHIFT);\
+ I2C_DUAL_DRV_WriteReg16(I2CD_CH2_CTRL, tmp);\
+}
+
+#define I2C_DUAL_CH2_SET_INTR(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_DUAL_DRV_ReadReg16(I2CD_INTR_MASK);\
+ tmp |= (val & (I2CD_INTR_MASK_CH2_TRANS_COMP_MASK | I2CD_INTR_MASK_CH2_ACK_ERR_MASK));\
+ I2C_DUAL_DRV_WriteReg16(I2CD_INTR_MASK, (kal_uint16)tmp);\
+}
+
+#define I2C_DUAL_CH2_CLR_INTR(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_DUAL_DRV_ReadReg16(I2CD_INTR_MASK);\
+ tmp &= ~(val & (I2CD_INTR_MASK_CH2_TRANS_COMP_MASK | I2CD_INTR_MASK_CH2_ACK_ERR_MASK) );\
+ I2C_DUAL_DRV_WriteReg16(I2CD_INTR_MASK, (kal_uint16)tmp);\
+}
+
+#define I2C_DUAL_CH2_SET_DATA_PORT(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH2_DATA_PORT, (kal_uint16)val)
+#define I2C_DUAL_CH2_SET_START(val) I2C_DUAL_DRV_WriteReg16(I2CD_CH2_START, I2CD_CH2_START_START_MASK);
+
+#endif // #if defined(DRV_I2C_DUAL)
+
+#endif // #ifndef _I2C_DUAL_HW_H
+
diff --git a/mcu/driver/peripheral/inc/i2c_dual_sw.h b/mcu/driver/peripheral/inc/i2c_dual_sw.h
new file mode 100644
index 0000000..5d38e28
--- /dev/null
+++ b/mcu/driver/peripheral/inc/i2c_dual_sw.h
@@ -0,0 +1,213 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * i2c_dual_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for I2C DUAL driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __I2C_DUAL_SW_H__
+#define __I2C_DUAL_SW_H__
+
+
+// MoDIS parser skip start
+// The following are private APIs
+// I2C DUAL driver is only used by PMIC6326 for now, NOT exported for other owners
+
+// #define MEASURE_I2C_DUAL_PERIOD
+//#define I2C_DUAL_AP_MD_TEST
+
+#define I2C_DUAL_CHANNEL1 1
+#define I2C_DUAL_CHANNEL2 2
+#define I2C_DUAL_READ 0
+#define I2C_DUAL_WRITE 1
+
+#define I2C_CLK_RATE 16250//13000
+
+#define MAX_ST_MODE_SPEED 100 /* khz */
+#define MAX_FS_MODE_SPEED 1000 /* khz */
+#define MAX_HS_MODE_SPEED 3400 /* khz */
+
+#define MAX_SAMPLE_CNT_DIV 8
+#define MAX_STEP_CNT_DIV 64
+#define MAX_HS_STEP_CNT_DIV 8
+
+typedef enum {
+ ST_MODE,
+ FS_MODE,
+ HS_MODE,
+} I2C_SPD_MODE;
+
+#if defined(MT6326)
+kal_bool pmic6326_reg_write(kal_uint8 reg, kal_uint8 val);
+kal_bool pmic6326_reg_read(kal_uint8 reg, kal_uint8 *pval);
+
+kal_bool pmic6326_reg_write_intr(kal_uint8 reg, kal_uint8 val);
+kal_bool pmic6326_reg_read_intr(kal_uint8 reg, kal_uint8 *pval);
+
+kal_bool pmic6326_reg_write_polling(kal_uint8 reg, kal_uint8 val);
+kal_bool pmic6326_reg_read_polling(kal_uint8 reg, kal_uint8 *pval);
+
+kal_bool pmic6326_reg_write_fast(kal_uint8 reg, kal_uint8 val);
+kal_bool pmic6326_reg_read_fast(kal_uint8 reg, kal_uint8 *pval);
+
+kal_bool pmic6326_ch2_reg_write(kal_uint8 reg, kal_uint8 val);
+kal_bool pmic6326_ch2_reg_read(kal_uint8 reg, kal_uint8 *pval);
+
+kal_bool pmic6326_ch2_reg_write_intr(kal_uint8 reg, kal_uint8 val);
+kal_bool pmic6326_ch2_reg_read_intr(kal_uint8 reg, kal_uint8 *pval);
+
+kal_bool pmic6326_ch2_reg_write_polling(kal_uint8 reg, kal_uint8 val);
+kal_bool pmic6326_ch2_reg_read_polling(kal_uint8 reg, kal_uint8 *pval);
+
+kal_bool pmic6326_ch2_reg_write_fast(kal_uint8 reg, kal_uint8 val);
+kal_bool pmic6326_ch2_reg_read_fast(kal_uint8 reg, kal_uint8 *pval);
+
+#elif (defined(MT6329) || defined(MT6327))
+#define PMIC_BANK0 0
+#define PMIC_BANK1 1
+
+#if defined(MEASURE_I2C_DUAL_PERIOD)
+extern kal_uint32 i2c_dual_time1;
+extern kal_uint32 i2c_dual_time2;
+extern kal_uint32 i2c_dual_time3;
+#endif
+
+kal_bool pmic6329_reg_write(kal_uint8 reg, kal_uint8 val, kal_uint32 bank);
+kal_bool pmic6329_reg_read(kal_uint8 reg, kal_uint8 *pval, kal_uint32 bank);
+
+kal_bool pmic6329_reg_write_intr(kal_uint8 reg, kal_uint8 val, kal_uint32 bank);
+kal_bool pmic6329_reg_read_intr(kal_uint8 reg, kal_uint8 *pval, kal_uint32 bank);
+
+kal_bool pmic6329_reg_write_polling(kal_uint8 reg, kal_uint8 val, kal_uint32 bank);
+kal_bool pmic6329_reg_read_polling(kal_uint8 reg, kal_uint8 *pval, kal_uint32 bank);
+
+kal_bool pmic6329_reg_write_fast(kal_uint8 reg, kal_uint8 val, kal_uint32 bank);
+kal_bool pmic6329_reg_read_fast(kal_uint8 reg, kal_uint8 *pval, kal_uint32 bank);
+
+kal_bool pmic6329_ch2_reg_write(kal_uint8 reg, kal_uint8 val, kal_uint32 bank);
+kal_bool pmic6329_ch2_reg_read(kal_uint8 reg, kal_uint8 *pval, kal_uint32 bank);
+
+kal_bool pmic6329_ch2_reg_write_intr(kal_uint8 reg, kal_uint8 val, kal_uint32 bank);
+kal_bool pmic6329_ch2_reg_read_intr(kal_uint8 reg, kal_uint8 *pval, kal_uint32 bank);
+
+kal_bool pmic6329_ch2_reg_write_polling(kal_uint8 reg, kal_uint8 val, kal_uint32 bank);
+kal_bool pmic6329_ch2_reg_read_polling(kal_uint8 reg, kal_uint8 *pval, kal_uint32 bank);
+
+kal_bool pmic6329_ch2_reg_write_fast(kal_uint8 reg, kal_uint8 val, kal_uint32 bank);
+kal_bool pmic6329_ch2_reg_read_fast(kal_uint8 reg, kal_uint8 *pval, kal_uint32 bank);
+
+
+//==============================================================================
+// I2C Exported Function
+//==============================================================================
+extern void i2c_v1_set_speed (unsigned long clock, I2C_SPD_MODE mode, unsigned long khz);
+extern void i2c_dual_ap_md_test(void);
+extern kal_bool i2c_dual_polling_trans_comp(kal_uint32 channel);
+#endif // End of #if defined(MT6326)
+// MoDIS parser skip end
+
+#endif // #ifndef __I2C_DUAL_SW_H__
+
diff --git a/mcu/driver/peripheral/inc/i2c_pmic_hw.h b/mcu/driver/peripheral/inc/i2c_pmic_hw.h
new file mode 100644
index 0000000..1ae38c3
--- /dev/null
+++ b/mcu/driver/peripheral/inc/i2c_pmic_hw.h
@@ -0,0 +1,395 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * i2c_pmic_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for I2C DUAL driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _I2C_PMIC_HW_H
+#define _I2C_PMIC_HW_H
+#include "drv_features.h"
+
+#include "drv_comm.h"
+#include "reg_base.h"
+
+#if defined(DRV_I2C_PMIC)
+
+#ifndef __DRV_DEBUG_I2C_PMIC_REG_READ_WRITE__
+#define I2C_PMIC_DRV_ClearBits16(addr, data) DRV_ClearBits(addr,data)
+#define I2C_PMIC_DRV_SetBits16(addr, data) DRV_SetBits(addr,data)
+#define I2C_PMIC_DRV_WriteReg16(addr, data) DRV_WriteReg(addr, data)
+#define I2C_PMIC_DRV_ReadReg16(addr) DRV_Reg(addr)
+#define I2C_PMIC_DRV_ClearBits32(addr, data) DRV_ClearBits32(addr, data)
+#define I2C_PMIC_DRV_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#else // #ifndef __DRV_DEBUG_I2C_PMIC_REG_READ_WRITE__
+#define I2C_PMIC_DRV_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
+#define I2C_PMIC_DRV_SetBits16(addr) DRV_DBG_SetBits(addr)
+#define I2C_PMIC_DRV_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
+#define I2C_PMIC_DRV_ReadReg16(addr) DRV_DBG_Reg(addr)
+#define I2C_PMIC_DRV_ClearBits32(addr, data) DRV_DBG_ClearBits32(addr, data)
+#define I2C_PMIC_DRV_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#endif // #ifndef __DRV_DEBUG_I2C_PMIC_REG_READ_WRITE__
+
+
+//#define I2CP_base I2C_DUAL_base
+#define I2CP_base I2C_base
+#define PMIC6327_I2C_ID 0xC0
+
+
+// I2CP means I2C for PMIC
+#define I2CP_DATA_PORT (I2CP_base + 0x00)
+#define I2CP_SLAVE_ADDR (I2CP_base + 0x04)
+#define I2CP_INTR_MASK (I2CP_base + 0x08)
+#define I2CP_INTR_STAT (I2CP_base + 0x0C)
+#define I2CP_CTRL (I2CP_base + 0x10)
+#define I2CP_TRANSFER_LEN (I2CP_base + 0x14)
+#define I2CP_TRANSFER_LEN_AUX (I2CP_base + 0x6c)
+#define I2CP_TRANSAC_LEN (I2CP_base + 0x18)
+#define I2CP_DELAY_LEN (I2CP_base + 0x1C)
+#define I2CP_TIMING (I2CP_base + 0x20)
+#define I2CP_START (I2CP_base + 0x24)
+#define I2CP_FIFO_STAT (I2CP_base + 0x30)
+#define I2CP_FIFO_THRESH (I2CP_base + 0x34)
+#define I2CP_FIFO_ADDR_CLR (I2CP_base + 0x38)
+#define I2CP_IO_CONFIG (I2CP_base + 0x40)
+#define I2CP_HS (I2CP_base + 0x48)
+#define I2CP_SOFTRESET (I2CP_base + 0x50)
+#define I2CP_DEBUGSTAT (I2CP_base + 0x64)
+#define I2CP_DEBUGCTRL (I2CP_base + 0x68)
+#define I2CP_TIMEOUT (I2CP_base + 0x74)
+#define I2CP_VERSION (I2CP_base + 0x78)
+
+
+// 0x00
+#define I2CP_DATA_PORT_MASK 0x00FF
+#define I2CP_DATA_PORT_SHIFT 0
+
+// 0x04
+#define I2CP_SLAVE_ADDR_MASK 0x00FF
+#define I2CP_SLAVE_ADDR_SHIFT 0
+
+// 0x08
+#define I2CP_INTR_MASK_TRANS_COMP_MASK 0x0001
+#define I2CP_INTR_MASK_TRANS_COMP_SHIFT 0
+#define I2CP_INTR_MASK_ACK_ERR_MASK 0x0002
+#define I2CP_INTR_MASK_ACK_ERR_SHIFT 1
+#define I2CP_INTR_MASK_HSNAK_ERR_MASK 0x0004
+#define I2CP_INTR_MASK_HSNAK_ERR_SHIFT 2
+#define I2CP_INTR_MASK_TIMEOUT_MASK 0x0010
+#define I2CP_INTR_MASK_TIMEOUT_SHIFT 4
+
+// 0x0C
+#define I2CP_INTR_STAT_TRANS_COMP_MASK 0x0001
+#define I2CP_INTR_STAT_TRANS_COMP_SHIFT 0
+#define I2CP_INTR_STAT_ACK_ERR_MASK 0x0002
+#define I2CP_INTR_STAT_ACK_ERR_SHIFT 1
+#define I2CP_INTR_STAT_HSNAK_ERR_MASK 0x0004
+#define I2CP_INTR_STAT_HSNAK_ERR_SHIFT 2
+#define I2CP_INTR_STAT_TIMEOUT_MASK 0x0010
+#define I2CP_INTR_STAT_TIMEOUT_SHIFT 4
+
+
+// 0x10
+#define I2CP_CTRL_RESTART_MASK 0x0002
+#define I2CP_CTRL_RESTART_SHIFT 1
+#define I2CP_CTRL_DMA_EN_MASK 0x0004
+#define I2CP_CTRL_DMA_EN_SHIFT 2
+#define I2CP_CTRL_CLK_EXT_EN_MASK 0x0008
+#define I2CP_CTRL_CLK_EXT_EN_SHIFT 3
+#define I2CP_CTRL_DIR_CHANGE_MASK 0x0010
+#define I2CP_CTRL_DIR_CHANGE_SHIFT 4
+#define I2CP_CTRL_ACKERR_DET_EN_MASK 0x0020
+#define I2CP_CTRL_ACKERR_DET_EN_SHIFT 5
+#define I2CP_CTRL_TRANSFER_LEN_CHANGE_MASK 0x0040
+#define I2CP_CTRL_TRANSFER_LEN_CHANGE_SHIFT 6
+#define I2CP_CTRL_RESET_BUS_BUSY_EN_MASK 0x0080
+#define I2CP_CTRL_RESET_BUS_BUSY_EN_SHIFT 7
+#define I2CP_CTRL_TIMEOUT_EN_MASK 0x0100
+#define I2CP_CTRL_TIMEOUT_EN_SHIFT 8
+
+// 0x14
+#define I2CP_TRANSFER_LEN_TRANSFER_LEN_MASK 0x00FF
+#define I2CP_TRANSFER_LEN_TRANSFER_LEN_SHIFT 0
+
+// 0x6c
+#define I2CP_TRANSFER_LEN_AUX_TRANSFER_LEN_AUX_MASK 0x00FF
+#define I2CP_TRANSFER_LEN_AUX_TRANSFER_LEN_AUX_SHIFT 0
+
+// 0x18
+#define I2CP_TRANSAC_LEN_TRANSAC_LEN_MASK 0x00FF
+#define I2CP_TRANSAC_LEN_TRANSAC_LEN_SHIFT 0
+
+// 0x1C
+#define I2CP_DELAY_LEN_DELAY_LEN_MASK 0x00FF
+#define I2CP_DELAY_LEN_DELAY_LEN_SHIFT 0
+
+// 0x20
+#define I2CP_TIMING_STEP_CNT_DIV_MASK 0x003F
+#define I2CP_TIMING_STEP_CNT_DIV_SHIFT 0
+#define I2CP_TIMING_SAMPLE_CNT_DIV_MASK 0x0700
+#define I2CP_TIMING_SAMPLE_CNT_DIV_SHIFT 8
+#define I2CP_TIMING_DATA_READ_MASK 0x7000
+#define I2CP_TIMING_DATA_READ_SHIFT 12
+#define I2CP_TIMING_DATA_READ_ADJ_MASK 0x8000
+#define I2CP_TIMING_DATA_READ_ADJ_SHIFT 15
+
+// 0x24
+#define I2CP_START_START_MASK 0x0001
+#define I2CP_START_START_SHIFT 0
+
+// 0x30
+#define I2CP_FIFO_STAT_RD_EMPTY_MASK 0x0001
+#define I2CP_FIFO_STAT_RD_EMPTY_SHIFT 0
+#define I2CP_FIFO_STAT_WR_FULL_MASK 0x0002
+#define I2CP_FIFO_STAT_WR_FULL_SHIFT 1
+#define I2CP_FIFO_STAT_OFFSET_MASK 0x00F0
+#define I2CP_FIFO_STAT_OFFSET_SHIFT 4
+#define I2CP_FIFO_STAT_WR_ADDR_MASK 0x0F00
+#define I2CP_FIFO_STAT_WR_ADDR_SHIFT 8
+#define I2CP_FIFO_STAT_RD_ADDR_MASK 0xF000
+#define I2CP_FIFO_STAT_RD_ADDR_SHIFT 12
+
+// 0x34
+#define I2CP_FIFO_THRESH_RX_TRIG_MASK 0x0007
+#define I2CP_FIFO_THRESH_RX_TRIG_SHIFT 0
+#define I2CP_FIFO_THRESH_TX_TRIG_MASK 0x0700
+#define I2CP_FIFO_THRESH_TX_TRIG_SHIFT 8
+
+// 0x38
+#define I2CP_FIFO_ADDR_CLR_CR_MASK 0x0001
+#define I2CP_FIFO_ADDR_CLR_CR_SHIFT 0
+
+// 0x40
+#define I2CP_IO_CONFIG_SCL_IO_MASK 0x0001
+#define I2CP_IO_CONFIG_SCL_IO_SHIFT 0
+#define I2CP_IO_CONFIG_SDA_IO_MASK 0x0002
+#define I2CP_IO_CONFIG_SDA_IO_SHIFT 1
+#define I2CP_IO_CONFIG_SYNC_EN_MASK 0x0004
+#define I2CP_IO_CONFIG_SYNC_EN_SHIFT 2
+#define I2CP_IO_CONFIG_IDLE_OE_EN_MASK 0x0008
+#define I2CP_IO_CONFIG_IDLE_OE_SIFT 3
+
+// 0x48
+#define I2CP_HS_HS_EN_MASK 0x0001
+#define I2CP_HS_HS_EN_SHIFT 0
+#define I2CP_HS_HS_NAK_ERR_DET_EN_MASK 0x0002
+#define I2CP_HS_HS_NAK_ERR_DET_EN_SHIFT 1
+#define I2CP_HS_MASTER_CODE_MASK 0x0070
+#define I2CP_HS_MASTER_CODE_SHIFT 4
+#define I2CP_HS_HS_STEP_CNT_DIV_MASK 0x0700
+#define I2CP_HS_HS_STEP_CNT_DIV_SHIFT 8
+#define I2CP_HS_HS_SAMPLE_CNT_DIV_MASK 0x7000
+#define I2CP_HS_HS_SAMPLE_CNT_DIV_SHIFT 12
+
+// 0x50
+#define I2CP_SOFTRESET_SOFTRESET_MASK 0x0001
+#define I2CP_SOFTRESET_SOFTRESET_SHIFT 0
+
+//0x64
+#define I2CP_DEBUG_STAT_MASTER_STAT_MASK 0x001f
+#define I2CP_DEBUG_STAT_MASTER_STAT_SHIFT 0
+#define I2CP_DEBUG_STAT_MASTER_READ_MASK 0x0020
+#define I2CP_DEBUG_STAT_MASTER_READ_SHIFT 5
+#define I2CP_DEBUG_STAT_MASTER_WRITE_MASK 0x0040
+#define I2CP_DEBUG_STAT_MASTER_WRITE_SHIFT 6
+#define I2CP_DEBUG_STAT_BUS_BUSY_MASK 0x0080
+#define I2CP_DEBUG_STAT_BUS_BUSY_SHIFT 7
+
+
+
+///////////////////////////////////////////////////////////////////////////////
+// Ch1 macros
+#define I2C_PMIC_CLEAR_FIFO(val) I2C_PMIC_DRV_WriteReg16(I2CP_FIFO_ADDR_CLR, (kal_uint16)1)
+#define I2C_PMIC_CLEAR_INTR_STAT(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_PMIC_DRV_ReadReg16(I2CP_INTR_STAT);\
+ tmp &= (I2CP_INTR_STAT_TRANS_COMP_MASK | I2CP_INTR_STAT_ACK_ERR_MASK|I2CP_INTR_STAT_HSNAK_ERR_MASK|I2CP_INTR_STAT_TIMEOUT_MASK);\
+ tmp |= (val);\
+ I2C_PMIC_DRV_WriteReg16(I2CP_INTR_STAT, tmp);\
+}
+#define I2C_PMIC_SET_SLAVE_ADDR(val) I2C_PMIC_DRV_WriteReg16(I2CP_SLAVE_ADDR, (kal_uint16)val)
+#define I2C_PMIC_SET_TRANSFER_LEN(len1, len2) {\
+ kal_uint16 tmp;\
+ tmp = I2C_PMIC_DRV_ReadReg16(I2CP_TRANSFER_LEN);\
+ tmp &= ~(I2CP_TRANSFER_LEN_TRANSFER_LEN_MASK);\
+ tmp |= ((kal_uint16)len1 << I2CP_TRANSFER_LEN_TRANSFER_LEN_SHIFT);\
+ I2C_PMIC_DRV_WriteReg16(I2CP_TRANSFER_LEN, tmp);\
+ tmp = I2C_PMIC_DRV_ReadReg16(I2CP_TRANSFER_LEN_AUX);\
+ tmp &= ~(I2CP_TRANSFER_LEN_AUX_TRANSFER_LEN_AUX_MASK);\
+ tmp |= ((kal_uint16)len1 << I2CP_TRANSFER_LEN_AUX_TRANSFER_LEN_AUX_SHIFT);\
+ I2C_PMIC_DRV_WriteReg16(I2CP_TRANSFER_LEN_AUX, tmp);\
+}
+
+#define I2C_PMIC_SET_TIMING(sample_cnt, step_cnt) {\
+ kal_uint16 tmp;\
+ tmp = I2C_PMIC_DRV_ReadReg16(I2CP_TIMING);\
+ tmp &= ~(I2CP_TIMING_STEP_CNT_DIV_MASK | I2CP_TIMING_SAMPLE_CNT_DIV_MASK);\
+ tmp |= ((kal_uint16)sample_cnt << I2CP_TIMING_SAMPLE_CNT_DIV_SHIFT);\
+ tmp |= ((kal_uint16)step_cnt << I2CP_TIMING_STEP_CNT_DIV_SHIFT);\
+ I2C_PMIC_DRV_WriteReg16(I2CP_TIMING, tmp);\
+}
+
+#define I2C_PMIC_SET_TRANSAC_LEN(len) I2C_PMIC_DRV_WriteReg16(I2CP_TRANSAC_LEN, (kal_uint16)len);
+#define I2C_PMIC_SET_DIR_CHANGE(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_PMIC_DRV_ReadReg16(I2CP_CTRL);\
+ tmp &= ~I2CP_CTRL_DIR_CHANGE_MASK;\
+ tmp |= ((kal_uint16)val << I2CP_CTRL_DIR_CHANGE_SHIFT);\
+ I2C_PMIC_DRV_WriteReg16(I2CP_CTRL, tmp);\
+}
+
+
+#define I2C_PMIC_SET_ACKERR_DET_EN(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_PMIC_DRV_ReadReg16(I2CP_CTRL);\
+ tmp &= ~I2CP_CTRL_ACKERR_DET_EN_MASK;\
+ tmp |= ((kal_uint16)val << I2CP_CTRL_ACKERR_DET_EN_SHIFT);\
+ I2C_PMIC_DRV_WriteReg16(I2CP_CTRL, tmp);\
+}
+
+#define I2C_PMIC_SET_CLK_EXT_EN(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_PMIC_DRV_ReadReg16(I2CP_CTRL);\
+ tmp &= ~I2CP_CTRL_CLK_EXT_EN_MASK;\
+ tmp |= ((kal_uint16)val << I2CP_CTRL_CLK_EXT_EN_SHIFT);\
+ I2C_PMIC_DRV_WriteReg16(I2CP_CTRL, tmp);\
+}
+
+
+#define I2C_PMIC_SET_RESTART(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_PMIC_DRV_ReadReg16(I2CP_CTRL);\
+ tmp &= ~I2CP_CTRL_RESTART_MASK;\
+ tmp |= ((kal_uint16)val << I2CP_CTRL_RESTART_SHIFT);\
+ I2C_PMIC_DRV_WriteReg16(I2CP_CTRL, tmp);\
+}
+
+
+#define I2C_PMIC_SET_INTR(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_PMIC_DRV_ReadReg16(I2CP_INTR_MASK);\
+ tmp |= (val & (I2CP_INTR_MASK_TRANS_COMP_MASK | I2CP_INTR_MASK_ACK_ERR_MASK | I2CP_INTR_MASK_HSNAK_ERR_MASK));\
+ I2C_PMIC_DRV_WriteReg16(I2CP_INTR_MASK, (kal_uint16)tmp);\
+}
+
+#define I2C_PMIC_CLR_INTR(val) {\
+ kal_uint16 tmp;\
+ tmp = I2C_PMIC_DRV_ReadReg16(I2CP_INTR_MASK);\
+ tmp &= ~(val & (I2CP_INTR_MASK_TRANS_COMP_MASK | I2CP_INTR_MASK_ACK_ERR_MASK | I2CP_INTR_MASK_HSNAK_ERR_MASK) );\
+ I2C_PMIC_DRV_WriteReg16(I2CP_INTR_MASK, (kal_uint16)tmp);\
+}
+
+
+#define I2C_PMIC_SET_DATA_PORT(val) I2C_PMIC_DRV_WriteReg16(I2CP_DATA_PORT, (kal_uint16)val)
+#define I2C_PMIC_GET_START() ((I2C_PMIC_DRV_ReadReg16(I2CP_START)&I2CP_START_START_MASK)>>I2CP_START_START_SHIFT)
+#define I2C_PMIC_SET_START(val) I2C_PMIC_DRV_WriteReg16(I2CP_START, I2CP_START_START_MASK);
+
+
+
+#endif // #if defined(DRV_I2C_PMIC)
+
+#endif // #ifndef _I2C_PMIC_HW_H
+
diff --git a/mcu/driver/peripheral/inc/i2c_pmic_sw.h b/mcu/driver/peripheral/inc/i2c_pmic_sw.h
new file mode 100644
index 0000000..a959eb1
--- /dev/null
+++ b/mcu/driver/peripheral/inc/i2c_pmic_sw.h
@@ -0,0 +1,253 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * i2c_dual_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for I2C DUAL driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __I2C_PMIC_SW_H__
+#define __I2C_PMIC_SW_H__
+
+#define I2C_PMIC_DBG_LOG_ENABLE
+#define I2C_PMIC_DBG_PATTERN_ENABLE
+//#define I2C_PMIC_DISABLE_DCM
+
+#if defined(I2C_PMIC_DBG_LOG_ENABLE)
+#define I2C_PMIC_LOG i2c_pmic_log
+#else
+#define I2C_PMIC_LOG(...)
+#endif
+
+typedef enum
+{
+ I2C_PMIC_READY_STATE = 0,
+ I2C_PMIC_READ_STATE,
+ I2C_PMIC_WRITE_STATE
+}I2C_PMIC_STATE;
+
+typedef enum
+{
+ I2C_PMIC_QUERY = 0,
+ I2C_PMIC_READ,
+ I2C_PMIC_WRITE
+}I2C_PMIC_POLLING_TYPE;
+
+
+/* GCC porting related */
+#if defined(__UBL__) || defined(__FUE__)
+#ifdef __MTK_TARGET__
+
+#define __i2csection(S) __attribute__ ((section (#S)))
+/* Tag variables with this */
+#define __emiinitrw __i2csection(EMIINITRW)
+#define __emiinitzi __i2csection(EMIINITZI)
+/* Tag constants with this */
+#define __emiinitconst __i2csection(EMIINITCONST)
+/* Tag function with this */
+#define __emiinitcode __i2csection(EMIINITCODE)
+
+#endif /* __MTK_TARGET__ */
+#else //#if defined(__UBL__) || defined(__FUE__)
+
+#define __emiinitrw
+#define __emiinitzi
+#define __emiinitconst
+#define __emiinitcode
+
+#endif //#if defined(__UBL__) || defined(__FUE__)
+
+typedef enum
+{
+ I2C_byte_return,
+ I2C_byte_write,
+ I2C_field_write,
+ I2C_read_sw_end,
+ I2C_write_sw_end,
+ I2C_polling_finish_reading,
+ I2C_polling_finish_writing,
+ I2C_polling_finish_reading_error,
+ I2C_polling_finish_writing_error,
+ I2C_polling_other_reading,
+ I2C_polling_other_writing,
+ I2C_polling_finish_other_reading,
+ I2C_polling_finish_other_writing,
+ I2C_polling_finish_other_reading_error,
+ I2C_polling_finish_other_writing_error,
+ I2C_polling_rdy_query,
+ I2C_polling_rdy_read,
+ I2C_polling_rdy_write,
+ I2C_polling_other_finish_mine
+}I2C_PMIC_DBG_INFO;
+
+typedef struct
+{
+ I2C_PMIC_DBG_INFO type;
+ kal_uint32 qbit;
+ kal_uint32 time;
+ kal_uint32 irqmask;
+ kal_uint32 token;
+ kal_uint32 hwowner;
+ kal_uint32 PDNStatus;
+}I2C_PMIC_DBG_LOG;
+
+extern void i2c_pmic_log(I2C_PMIC_DBG_INFO type,kal_uint32 var);
+
+
+#endif // #ifndef __I2C_PMIC_SW_H__
+
diff --git a/mcu/driver/peripheral/inc/keypad.h b/mcu/driver/peripheral/inc/keypad.h
new file mode 100644
index 0000000..2193f7f
--- /dev/null
+++ b/mcu/driver/peripheral/inc/keypad.h
@@ -0,0 +1,665 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * keypad_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for keypad driver and adaption.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _KEYPAD_H
+#define _KEYPAD_H
+
+#include "drv_features.h"
+#include "intrCtrl.h"
+#include "drv_comm.h"
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "kal_public_api.h"
+#include "keypad_sw.h"
+#include "dcl.h"
+
+
+typedef enum {
+ kbd_1_key_det_mode = 0,
+ kbd_2_keys_det_mode,
+ kbd_3_keys_det_mode
+} kbd_key_det_mode;
+
+
+
+
+
+#define __DCL_KBD_SUPPORT__
+
+#if defined(__EXTEND_QWERTY_KEYPAD__)
+
+#define KBD_MASKIRQ SetINTMask(IRQ_KPAD_CODE)
+#define KBD_UNMASKIRQ RestoreINTMask(IRQ_KPAD_CODE)
+#else
+
+#define KBD_MASKIRQ IRQMask(IRQ_KPAD_CODE)
+#define KBD_UNMASKIRQ IRQUnmask(IRQ_KPAD_CODE)
+
+#endif //#if defined(__EXTEND_QWERTY_KEYPAD__)
+
+#ifdef __EXTRA_A_B_KEY_SUPPORT__
+#define KBD_EX_GPT_HDL_CNT 2
+#else
+#define KBD_EX_GPT_HDL_CNT 0
+#endif
+
+#if defined(__TWO_KEY_DETECTION_SWITCHABLE__)
+ #define KBD_KEY_DETECTION_CNT 2
+#elif defined(__THREE_KEY_DETECTION_SWITCHABLE__)
+ #define KBD_KEY_DETECTION_CNT 3
+#else
+ #define KBD_KEY_DETECTION_CNT 1
+#endif
+
+#define KBD_GPT_HDL_CNT (KBD_EX_GPT_HDL_CNT + KBD_KEY_DETECTION_CNT)
+
+#define EVENT_REQUESTED (KBD_STATUS_CHANGE_EVENT|KBD_SWITCH_DETCTION_MODE_EVENT |KEY_UP_EVENT| KEY_DOWN_EVENT| KEY_RIGHT_EVENT | KEY_LEFT_EVENT)
+
+#if defined(TWO_KEY_ENABLE)
+ #if defined(__TWO_KEY_DETECTION_SWITCHABLE__) || defined(__THREE_KEY_DETECTION_SWITCHABLE__)
+ #error " kbd config conflicts!!"
+ #endif
+#endif
+
+
+typedef struct
+{
+ kal_uint32 kbdmap_reg;
+ kal_uint32 kbdmap_reg1;
+ kal_uint32 kbdmap_reg2;
+}kbd_map_reg_struct;
+
+typedef enum
+{
+ KEY_DIRECTION_EVENT_NUll,
+ KBD_STATUS_CHANGE_EVENT = 0x01, /*keypad status changes event id */
+ KBD_SWITCH_DETCTION_MODE_EVENT = 0x02, /*keypad switch detection mode event id*/
+
+ KEY_UP_EVENT = 0x10,
+ KEY_DOWN_EVENT = 0x20,
+ KEY_LEFT_EVENT = 0x40,
+ KEY_RIGHT_EVENT = 0x80,
+ KEY_DIRECTION_EVENT_ALL = 0xF0
+}kbd_task_event;
+
+
+typedef struct
+{
+ kal_eventgrpid event;
+ DCL_HANDLE gpthandle[KBD_GPT_HDL_CNT];
+
+#ifdef __EXTRA_A_B_KEY_SUPPORT__
+ kal_bool ext_status[2];
+#endif/*__EXTRA_A_B_KEY_SUPPORT__*/
+
+#ifdef __KBD_2STEP_KEY_SUPPORT__
+DCL_HANDLE kbd_2key_handle;
+#endif
+#if defined(__EXTEND_QWERTY_KEYPAD__)
+ DCL_HANDLE kbd_extend_gpthandle;
+ kal_uint32 polling_timeout;
+#endif //#if defined(__EXTEND_QWERTY_KEYPAD__)
+ kal_uint32 longpress_timeout;
+ kal_uint32 repeat_time;
+} kbd_struct;
+
+
+#if defined(__EXTEND_QWERTY_KEYPAD__)
+
+typedef struct
+{
+ kal_bool key_column_all_low_GND[KBD_COLUMN]; //column all low cause by GND_ROW
+ kal_bool key_column_all_low_GPO[KBD_COLUMN]; //column all low cause by GPO_ROW
+}keypad_Ext_QwertyKey_Status;
+ typedef struct
+ {
+ kal_bool key_column_all_low_GND[KBD_COLUMN]; //column all low cause by GND_ROW
+ kal_bool key_column_all_low_GPO[KBD_COLUMN]; //column all low cause by GPO_ROW
+
+ kal_uint8 kbd_press_GND_column[KBD_KEY_DETECTION_CNT]; // which column pressed
+ kal_uint8 kbd_press_GPO_column[KBD_KEY_DETECTION_CNT]; // which column pressed
+ }keypad_Ext_QwertyKey_detect_info_struct;
+
+#endif
+
+ /*keypad detect keys result during one key event*/
+ typedef struct
+ {
+ #if defined(__EXTEND_QWERTY_KEYPAD__)
+ keypad_Ext_QwertyKey_detect_info_struct kbd_Ext_Qwerty_key_info;
+#endif
+ kal_uint8 key_presscount;
+ kal_uint8 key_releasecount;
+ kal_uint8 key_total_count;
+
+ kal_uint8 kbd_press_key[KBD_KEY_DETECTION_CNT];
+ kal_uint8 kbd_release_key[KBD_KEY_DETECTION_CNT];
+
+ } keypad_detect_info_struct;
+
+typedef enum
+{
+ Normal_ROW = 0,
+ Ext_GPO_ROW,
+ Ext_GND_ROW
+}Keypad_ROW_Type;
+
+/*every key information*/
+ typedef struct
+ {
+ kal_bool bKeyStatus; /*0: press; 1: release */
+ kal_uint16 key_index; /*key index defined during customization*/
+
+#if defined(__EXTEND_QWERTY_KEYPAD__)
+ kal_uint8 key_column; /*extend keys in which column*/
+ Keypad_ROW_Type Row_Type;
+#endif
+ }keypad_key_info;
+
+typedef struct
+{
+ kbd_map_reg_struct kbd_map_reg;
+#if defined(__EXTEND_QWERTY_KEYPAD__)
+ kal_bool key_column_all_low_GND[KBD_COLUMN]; //column all low cause by GND_ROW
+ kal_bool key_column_all_low_GPO[KBD_COLUMN]; //column all low cause by GPO_ROW
+ kal_bool extend_switch_mode_key;//when switch mode, the extend key is pressed
+ kal_uint8 extend_key_switch_pressed_num;
+ kal_uint8 kbd_switch_mode_extend_press_key[KBD_KEY_DETECTION_CNT];
+
+#endif
+
+}keypad_status_struct;
+
+#if !defined(KBD_DETECT_ONLY_ONE_KEY) && defined(__EXTRA_A_B_KEY_SUPPORT__)
+ extern const kal_uint8 EXTRA_A_KEY_EINT_NO;
+ extern const kal_uint8 EXTRA_B_KEY_EINT_NO;
+ #define EINT_A_KEY EXTRA_A_KEY_EINT_NO
+ #define EINT_B_KEY EXTRA_B_KEY_EINT_NO
+#endif
+
+#if defined(__TC01__)
+#define kbd_push_time_stamp() \
+{\
+ kal_get_time(&(kbd_buffer.kbd_data_buffer[kbd_buffer.kbd_data_buffer_windex].keytimestamp));\
+}
+
+#define kbd_pop_time_stamp(_key_data) \
+{\
+kbd_data* key_data = (kbd_data*)(_key_data);\
+key_data->keytimestamp = kbd_buffer.kbd_data_buffer[kbd_buffer.kbd_data_buffer_rindex].keytimestamp;\
+}
+
+#else
+#define kbd_push_time_stamp() ;
+#define kbd_pop_time_stamp(_key_data) ;
+#endif
+
+extern void kbdbuffer_get_roomleft_(kal_uint8* pleft);
+
+#define kbdbuffer_get_roomleft(_left) \
+{\
+ kbdbuffer_get_roomleft_(&(_left));\
+}
+
+
+extern void Kbd_Initiaze(void);
+extern kal_bool Kbd_GetDetectionMode(kal_uint8 *pmode);
+extern kal_bool kbd_SetDetectionMode(kbd_key_det_mode mode);
+extern kal_bool kbd_IsKeySupported(kal_uint8 key);
+extern kal_bool kbd_IsKeymutiple(kal_uint8 key);
+extern kal_uint32 Kbd_GetKeyCount(void);
+extern kal_bool Kbd_GetKeyDatas(kbd_data *keydata);
+extern kal_bool Kbd_PeekKeyDatas(kbd_data *keydata, kal_bool specify_read,
+ kal_uint32 read_pointer,kal_uint32* current_read_pointer);
+extern kal_uint32 kbd_SendKey(kal_uint8 key);
+extern void Kbd_SetLongPreTime(kal_uint32 ticks);
+extern void Kbd_SetRepeatPreTime(kal_uint32 ticks);
+
+
+//#include "us_timer.h"
+extern kal_uint32 L1I_GetTimeStamp(void);
+#define KBD_GetTimeStamp L1I_GetTimeStamp
+#if defined(__MTK_INTERNAL__) && !defined(__MAUI_BASIC__) && defined(__DRV_DBG_MEMORY_TRACE_SUPPORT__) && defined(__EXTEND_QWERTY_KEYPAD__)
+#define DRV_KBD_MEMORY_TRACE
+typedef struct{
+ kal_uint16 tag;
+ kal_uint32 time;
+ kal_uint32 data1;
+ kal_uint32 data2;
+}KBD_DRV_DBG_DATA;
+#define MAX_KBD_DRV_DBG_INFO_SIZE 512
+typedef struct{
+ KBD_DRV_DBG_DATA dbg_data[MAX_KBD_DRV_DBG_INFO_SIZE];
+ kal_uint16 dbg_data_idx;
+}KBD_DRV_DBG_STRUCT;
+extern void kbd_drv_dbg_trace(kal_uint16 index, kal_uint32 time, kal_uint32 data1, kal_uint32 data2);
+#define KBD_DBG(a,b,c,d) kbd_drv_dbg_trace(a,b,c,d);
+#else //#if defined(__MTK_INTERNAL__) && !defined(LOW_COST_SUPPORT)
+#define KBD_DBG(a,b,c,d) ;
+#endif //#if defined(__MTK_INTERNAL__) && !defined(LOW_COST_SUPPORT)
+
+
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_KBD_REG_DBG__)
+#define DRV_KBD_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+#define DRV_KBD_Reg(addr) DRV_DBG_Reg(addr)
+#define DRV_KBD_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define DRV_KBD_Reg32(addr) DRV_DBG_Reg32(addr)
+#define DRV_KBD_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+#define DRV_KBD_Reg8(addr) DRV_DBG_Reg8(addr)
+#define DRV_KBD_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+#define DRV_KBD_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+#define DRV_KBD_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#define DRV_KBD_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+#define DRV_KBD_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+#define DRV_KBD_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+#define DRV_KBD_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+#define DRV_KBD_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+#define DRV_KBD_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+#else
+#define DRV_KBD_WriteReg(addr,data) DRV_WriteReg(addr,data)
+#define DRV_KBD_Reg(addr) DRV_Reg(addr)
+#define DRV_KBD_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define DRV_KBD_Reg32(addr) DRV_Reg32(addr)
+#define DRV_KBD_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+#define DRV_KBD_Reg8(addr) DRV_Reg8(addr)
+#define DRV_KBD_ClearBits(addr,data) DRV_ClearBits(addr,data)
+#define DRV_KBD_SetBits(addr,data) DRV_SetBits(addr,data)
+#define DRV_KBD_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define DRV_KBD_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+#define DRV_KBD_SetBits32(addr,data) DRV_SetBits32(addr,data)
+#define DRV_KBD_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+#define DRV_KBD_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+#define DRV_KBD_SetBits8(addr,data) DRV_SetBits8(addr,data)
+#define DRV_KBD_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_KBD_REG_DBG__)
+
+#endif
+
+
+
+
+
diff --git a/mcu/driver/peripheral/inc/keypad_trc.h b/mcu/driver/peripheral/inc/keypad_trc.h
new file mode 100644
index 0000000..1e8120f
--- /dev/null
+++ b/mcu/driver/peripheral/inc/keypad_trc.h
@@ -0,0 +1,104 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * keypad_trc.h
+ *
+ * Project:
+ * --------
+ * MAUI
+ *
+ * Description:
+ * ------------
+ * This is trace map definition for keypad driver
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ ****************************************************************************/
+#ifndef _KEYPAD_TRC_H
+#define _KEYPAD_TRC_H
+
+
+#ifndef GEN_FOR_PC
+
+ #ifndef _STACK_CONFIG_H
+ #error "stack_config.h should be included before tst_config.h"
+ #endif
+
+#else
+ #include "kal_trace.h"
+#endif /* GEN_FOR_PC */
+
+
+#ifndef _KAL_TRACE_H
+ #error "kal_trace.h should be included before tst_trace.h"
+#endif
+
+#if !defined(GEN_FOR_PC)
+#if defined(__TST_MODULE__) || defined(__CUSTOM_RELEASE__)
+ #include "keypad_trc_gen.h"
+#endif /* TST Trace Defintion */
+#endif
+BEGIN_TRACE_MAP(MOD_DRVKBD)
+
+ TRC_MSG(KBD_REPEAT_HANDLER_NO_ROOM,"KBD repeat handler: no room for repeated event")
+ TRC_MSG(KBD_LONGPRESS_HANDLER_NO_ROOM,"KBD longpress handler: no room for longpress event")
+ TRC_MSG(KBD_2STEP_KEY_HANDLER_NO_ROOM,"KBD 2-step key handler: no room for 2-step key event")
+ TRC_MSG(KBD_PUT_DATA_TO_BUFFER,"KBD put data to ring buffer: event: %d, data: %d")
+ TRC_MSG(KBD_PUT_TWO_DATA_TO_BUFFER,"KBD put data to ring buffer: event: %d, data1: %d, data2: %d")
+ TRC_MSG(KBD_GET_TWO_KEY_DATA,"KBD get two key: event: %d, data1: %d, data2: %d")
+ TRC_MSG(KBD_GET_ONE_KEY_DATA,"KBD get one key: event: %d, data: %d")
+ TRC_MSG(KBD_DETECT_MODE_SWITCH,"KBD detect mode switch to %d")
+ TRC_MSG(KBD_DETECT_MODE_SWITCH_NOT_SUPPORT,"KBD detect mode switch not supported")
+ TRC_MSG(KBD_EXT_A_B_KEY_SUPPORT,"KBD extra A, B key support")
+ TRC_MSG(KBD_EXT_2STEP_KEY_SUPPORT,"KBD 2-step key support")
+ TRC_MSG(KBD_MULTIPLE_KEY,"KBD %d is a multiple key")
+ TRC_MSG(KBD_NOT_MULTIPLE_KEY,"KBD %d is NOT a multiple key")
+ TRC_MSG(KBD_2STEP_KEY_QUERY,"KBD 2-step key: %d")
+ TRC_MSG(KBD_KEY_QUERY_SUPPORTED,"KBD key: %d is supported")
+ TRC_MSG(KBD_KEY_QUERY_NOT_SUPPORTED,"KBD key: %d is NOT supported")
+
+
+
+
+END_TRACE_MAP(MOD_DRVKBD)
+
+#endif /* _TP_TRC_H */
+
+
diff --git a/mcu/driver/peripheral/inc/mt6571_pmic_wrap_hw.h b/mcu/driver/peripheral/inc/mt6571_pmic_wrap_hw.h
new file mode 100644
index 0000000..e20f3fa
--- /dev/null
+++ b/mcu/driver/peripheral/inc/mt6571_pmic_wrap_hw.h
@@ -0,0 +1,315 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mt6582_pmic_wrap_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This is mt6571 pmic wrapper h/w register
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __MT6571_PMIC_WRAP_HW_H__
+#define __MT6571_PMIC_WRAP_HW_H__
+
+#if !defined(FPGA_CTP)
+#include "reg_base.h"
+
+#define PMIC_WRAP_BASE (AP_PMIC_WRAP_BASE)
+#define TOP_CLOCK_CTRL_BASE (AP_TOP_CLOCK_CTRL_BASE)
+#define TOPRGU_BASE (AP_TOPRGU_BASE)
+
+#else
+#define PMIC_WRAP_BASE (0x1000F000)
+#define TOP_CLOCK_CTRL_BASE (0x10000000)
+#define TOPRGU_BASE (0x10007000)
+
+#endif
+
+#define CLK_SEL_0 (TOP_CLOCK_CTRL_BASE + 0x000)
+#define CLK_SWCG_1 (TOP_CLOCK_CTRL_BASE + 0x024)
+#define CLK_SETCG_1 (TOP_CLOCK_CTRL_BASE + 0x054)
+#define CLK_SETCG_3 (TOP_CLOCK_CTRL_BASE + 0x05C)
+#define CLK_CLRCG_1 (TOP_CLOCK_CTRL_BASE + 0x084)
+#define WDT_SWSYSRST (TOPRGU_BASE + 0x018)
+#define WDT_FAST_SWSYSRST (TOPRGU_BASE + 0x408)
+
+#define INFRA_GLOBALCON_RST0 (AP_INFRACFG_AO_base + 0x030)
+
+#define PMIC_WRAP_MUX_SEL (PMIC_WRAP_BASE+0x0)
+#define PMIC_WRAP_WRAP_EN (PMIC_WRAP_BASE+0x4)
+#define PMIC_WRAP_DIO_EN (PMIC_WRAP_BASE+0x8)
+#define PMIC_WRAP_SIDLY (PMIC_WRAP_BASE+0xC)
+#define PMIC_WRAP_OP_TYPE (PMIC_WRAP_BASE+0x10)
+#define PMIC_WRAP_MSB_FIRST (PMIC_WRAP_BASE+0x14)
+#define PMIC_WRAP_RDDMY (PMIC_WRAP_BASE+0x18)
+#define PMIC_WRAP_SI_CK_CON (PMIC_WRAP_BASE+0x1C)
+#define PMIC_WRAP_CSHEXT_WRITE (PMIC_WRAP_BASE+0x20)
+#define PMIC_WRAP_CSHEXT_READ (PMIC_WRAP_BASE+0x24)
+#define PMIC_WRAP_CSLEXT_START (PMIC_WRAP_BASE+0x28)
+#define PMIC_WRAP_CSLEXT_END (PMIC_WRAP_BASE+0x2C)
+#define PMIC_WRAP_STAUPD_PRD (PMIC_WRAP_BASE+0x30)
+#define PMIC_WRAP_STAUPD_GRPEN (PMIC_WRAP_BASE+0x34)
+#define PMIC_WRAP_STAUPD_MAN_TRIG (PMIC_WRAP_BASE+0x38)
+#define PMIC_WRAP_STAUPD_STA (PMIC_WRAP_BASE+0x3C)
+#define PMIC_WRAP_GPS_STA (PMIC_WRAP_BASE+0x40)
+#define PMIC_WRAP_WRAP_STA (PMIC_WRAP_BASE+0x44)
+#define PMIC_WRAP_HARB_INIT (PMIC_WRAP_BASE+0x48)
+#define PMIC_WRAP_HARB_HPRIO (PMIC_WRAP_BASE+0x4C)
+#define PMIC_WRAP_HIPRIO_ARB_EN (PMIC_WRAP_BASE+0x50)
+#define PMIC_WRAP_HARB_STA0 (PMIC_WRAP_BASE+0x54)
+#define PMIC_WRAP_HARB_STA1 (PMIC_WRAP_BASE+0x58)
+#define PMIC_WRAP_MAN_EN (PMIC_WRAP_BASE+0x5C)
+#define PMIC_WRAP_MAN_CMD (PMIC_WRAP_BASE+0x60)
+#define PMIC_WRAP_MAN_RDATA (PMIC_WRAP_BASE+0x64)
+#define PMIC_WRAP_MAN_VLDCLR (PMIC_WRAP_BASE+0x68)
+#define PMIC_WRAP_WACS0_EN (PMIC_WRAP_BASE+0x6C)
+#define PMIC_WRAP_INIT_DONE0 (PMIC_WRAP_BASE+0x70)
+#define PMIC_WRAP_WACS0_CMD (PMIC_WRAP_BASE+0x74)
+#define PMIC_WRAP_WACS0_RDATA (PMIC_WRAP_BASE+0x78)
+#define PMIC_WRAP_WACS0_VLDCLR (PMIC_WRAP_BASE+0x7C)
+#define PMIC_WRAP_WACS1_EN (PMIC_WRAP_BASE+0x80)
+#define PMIC_WRAP_INIT_DONE1 (PMIC_WRAP_BASE+0x84)
+#define PMIC_WRAP_WACS1_CMD (PMIC_WRAP_BASE+0x88)
+#define PMIC_WRAP_WACS1_RDATA (PMIC_WRAP_BASE+0x8C)
+#define PMIC_WRAP_WACS1_VLDCLR (PMIC_WRAP_BASE+0x90)
+#define PMIC_WRAP_WACS2_EN (PMIC_WRAP_BASE+0x94)
+#define PMIC_WRAP_INIT_DONE2 (PMIC_WRAP_BASE+0x98)
+#define PMIC_WRAP_WACS2_CMD (PMIC_WRAP_BASE+0x9C)
+#define PMIC_WRAP_WACS2_RDATA (PMIC_WRAP_BASE+0xA0)
+#define PMIC_WRAP_WACS2_VLDCLR (PMIC_WRAP_BASE+0xA4)
+#define PMIC_WRAP_INT_EN (PMIC_WRAP_BASE+0xA8)
+#define PMIC_WRAP_INT_FLG_RAW (PMIC_WRAP_BASE+0xAC)
+#define PMIC_WRAP_INT_FLG (PMIC_WRAP_BASE+0xB0)
+#define PMIC_WRAP_INT_CLR (PMIC_WRAP_BASE+0xB4)
+#define PMIC_WRAP_SIG_ADR (PMIC_WRAP_BASE+0xB8)
+#define PMIC_WRAP_SIG_MODE (PMIC_WRAP_BASE+0xBC)
+#define PMIC_WRAP_SIG_VALUE (PMIC_WRAP_BASE+0xC0)
+#define PMIC_WRAP_SIG_ERRVAL (PMIC_WRAP_BASE+0xC4)
+#define PMIC_WRAP_CRC_EN (PMIC_WRAP_BASE+0xC8)
+#define PMIC_WRAP_TIMER_EN (PMIC_WRAP_BASE+0xCC)
+#define PMIC_WRAP_TIMER_STA (PMIC_WRAP_BASE+0xD0)
+#define PMIC_WRAP_WDT_UNIT (PMIC_WRAP_BASE+0xD4)
+#define PMIC_WRAP_WDT_SRC_EN (PMIC_WRAP_BASE+0xD8)
+#define PMIC_WRAP_WDT_FLG (PMIC_WRAP_BASE+0xDC)
+#define PMIC_WRAP_DEBUG_INT_SEL (PMIC_WRAP_BASE+0xE0)
+#define PMIC_WRAP_DVFS_ADR0 (PMIC_WRAP_BASE+0xE4)
+#define PMIC_WRAP_DVFS_WDATA0 (PMIC_WRAP_BASE+0xE8)
+#define PMIC_WRAP_DVFS_ADR1 (PMIC_WRAP_BASE+0xEC)
+#define PMIC_WRAP_DVFS_WDATA1 (PMIC_WRAP_BASE+0xF0)
+#define PMIC_WRAP_DVFS_ADR2 (PMIC_WRAP_BASE+0xF4)
+#define PMIC_WRAP_DVFS_WDATA2 (PMIC_WRAP_BASE+0xF8)
+#define PMIC_WRAP_DVFS_ADR3 (PMIC_WRAP_BASE+0xFC)
+#define PMIC_WRAP_DVFS_WDATA3 (PMIC_WRAP_BASE+0x100)
+#define PMIC_WRAP_DVFS_ADR4 (PMIC_WRAP_BASE+0x104)
+#define PMIC_WRAP_DVFS_WDATA4 (PMIC_WRAP_BASE+0x108)
+#define PMIC_WRAP_DVFS_ADR5 (PMIC_WRAP_BASE+0x10C)
+#define PMIC_WRAP_DVFS_WDATA5 (PMIC_WRAP_BASE+0x110)
+#define PMIC_WRAP_DVFS_ADR6 (PMIC_WRAP_BASE+0x114)
+#define PMIC_WRAP_DVFS_WDATA6 (PMIC_WRAP_BASE+0x118)
+#define PMIC_WRAP_DVFS_ADR7 (PMIC_WRAP_BASE+0x11C)
+#define PMIC_WRAP_DVFS_WDATA7 (PMIC_WRAP_BASE+0x120)
+#define PMIC_WRAP_CIPHER_KEY_SEL (PMIC_WRAP_BASE+0x124)
+#define PMIC_WRAP_CIPHER_IV_SEL (PMIC_WRAP_BASE+0x128)
+#define PMIC_WRAP_CIPHER_EN (PMIC_WRAP_BASE+0x12C)
+#define PMIC_WRAP_CIPHER_RDY (PMIC_WRAP_BASE+0x130)
+#define PMIC_WRAP_CIPHER_MODE (PMIC_WRAP_BASE+0x134)
+#define PMIC_WRAP_CIPHER_SWRST (PMIC_WRAP_BASE+0x138)
+#define PMIC_WRAP_DCM_EN (PMIC_WRAP_BASE+0x13C)
+#define PMIC_WRAP_DCM_DBC_PRD (PMIC_WRAP_BASE+0x140)
+#define PMIC_WRAP_ADC_CMD_ADDR (PMIC_WRAP_BASE+0x144)
+#define PMIC_WRAP_PWRAP_ADC_CMD (PMIC_WRAP_BASE+0x148)
+#define PMIC_WRAP_ADC_RDY_ADDR (PMIC_WRAP_BASE+0x14C)
+#define PMIC_WRAP_ADC_RDATA_ADDR1 (PMIC_WRAP_BASE+0x150)
+#define PMIC_WRAP_ADC_RDATA_ADDR2 (PMIC_WRAP_BASE+0x154)
+#define PMIC_WRAP_SWRST (PMIC_WRAP_BASE+0x180)
+#define PMIC_WRAP_DEBUG_SEL (PMIC_WRAP_BASE+0x190)
+
+// Bit Control
+#define GET_STAUPD_DLE_CNT(x) ((x>>0) & 0x00000007)
+#define GET_STAUPD_ALE_CNT(x) ((x>>3) & 0x00000007)
+#define GET_STAUPD_FSM(x) ((x>>6) & 0x00000007)
+#define GET_PWRAP_GPS_ACK(x) ((x>>0) & 0x00000001)
+#define GET_GPS_PWRAP_REQ(x) ((x>>1) & 0x00000001)
+#define GET_GPSINF_DLE_CNT(x) ((x>>4) & 0x00000003)
+#define GET_GPSINF_ALE_CNT(x) ((x>>6) & 0x00000003)
+#define GET_GPS_INF_FSM(x) ((x>>8) & 0x00000007)
+#define GET_PWRAP_GPS_WDATA(x) ((x>>15) & 0x0001ffff)
+#define GET_WRAP_CH_DLE_RESTCNT(x) ((x>>0) & 0x00000007)
+#define GET_WRAP_CH_ALE_RESTCNT(x) ((x>>3) & 0x00000003)
+#define GET_WRAP_AG_DLE_RESTCNT(x) ((x>>5) & 0x00000003)
+#define GET_WRAP_CH_W(x) ((x>>7) & 0x00000001)
+#define GET_WRAP_CH_REQ(x) ((x>>8) & 0x00000001)
+#define GET_AG_WRAP_W(x) ((x>>9) & 0x00000001)
+#define GET_AG_WRAP_REQ(x) ((x>>10) & 0x00000001)
+#define GET_WRAP_FSM(x) ((x>>11) & 0x0000000f)
+#define GET_HARB_WRAP_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_HARB_WRAP_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_HARB_WRAP_REQ(x) ((x>>31) & 0x00000001)
+#define GET_HARB_DLE_EMPTY(x) ((x>>0) & 0x00000001)
+#define GET_HARB_DLE_FULL(x) ((x>>1) & 0x00000001)
+#define GET_HARB_VLD(x) ((x>>2) & 0x00000001)
+#define GET_HARB_DLE_OWN(x) ((x>>3) & 0x0000000f)
+#define GET_HARB_OWN(x) ((x>>7) & 0x0000000f)
+#define GET_HARB_DLE_RESTCNT(x) ((x>>11) & 0x0000000f)
+#define GET_AG_HARB_REQ(x) ((x>>15) & 0x0000007f)
+#define GET_HARB_WRAP_W(x) ((x>>22) & 0x00000001)
+#define GET_HARB_WRAP_REQ0(x) ((x>>23) & 0x00000001)
+#define GET_SPI_WDATA(x) ((x>>0) & 0x000000ff)
+#define GET_SPI_OP(x) ((x>>8) & 0x0000001f)
+#define GET_SPI_W(x) ((x>>13) & 0x00000001)
+#define GET_MAN_RDATA(x) ((x>>0) & 0x000000ff)
+#define GET_MAN_FSM(x) ((x>>8) & 0x00000007)
+#define GET_MAN_REQ(x) ((x>>11) & 0x00000001)
+#define GET_WACS0_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS0_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS0_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS0_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS0_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS0_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE0(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE0(x) ((x>>21) & 0x00000001)
+#define GET_WACS1_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS1_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS1_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS1_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS1_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS1_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE1(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE1(x) ((x>>21) & 0x00000001)
+#define GET_WACS2_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS2_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS2_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS2_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS2_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS2_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE2(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE2(x) ((x>>21) & 0x00000001)
+
+#define GET_WACS_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE(x) ((x>>21) & 0x00000001)
+
+#define SPI_AUTO_MODE 0
+#define SPI_MANUAL_MODE 1
+#define HARB_HPRIO_ALL 0x1FF
+#define HARB_HPRIO_RRAPB (1 << 8)
+#define HARB_HPRIO_PERI_PWRAP (1 << 7)
+#define HARB_HPRIO_STAUPD (1 << 6)
+#define HARB_HPRIO_ERC (1 << 5)
+#define HARB_HPRIO_DVFSINF (1 << 4)
+#define HARB_HPRIO_WACS2 (1 << 3)
+#define HARB_HPRIO_WACS1 (1 << 2)
+#define HARB_HPRIO_WACS0 (1 << 1)
+#define HARB_HPRIO_MDINF (1 << 0)
+
+
+// Current WRAP FSM states.
+#define WRAP_FSM_IDLE_STATE 0x0
+#define WRAP_FSM_CSL_ADR_START_STATE 0x2
+#define WRAP_FSM_ADR_STATE 0x4
+#define WRAP_FSM_CSL_ADR_END_STATE 0x6
+#define WRAP_FSM_CSH_ADR_STATE 0x8
+#define WRAP_FSM_CSL_DATA_START_STATE 0xA
+#define WRAP_FSM_DATA_STATE 0xC
+#define WRAP_FSM_CSL_DATA_END_STATE 0xE
+#define WRAP_FSM_CSH_DATA_STATE 0xF
+
+#define WACS_INIT_DONE_NOT_FINISHED 0
+#define WACS_INIT_DONE_FINISHED 1
+
+
+#define WACS_SYNC_MODULE_BUSY 0
+#define WACS_SYNC_MODULE_IDLE 1
+
+// Current WACS FSM states.
+#define WACS_FSM_IDLE_STATE 0x0
+#define WACS_FSM_REQ_STATE 0x2
+#define WACS_FSM_WFDLE_STATE 0x4
+#define WACS_FSM_WFVLDCLR_STATE 0x6
+
+// Current MAN FSM states.
+#define MAN_FSM_IDLE_STATE 0x0
+#define MAN_FSM_REQ_STATE 0x2
+#define MAN_FSM_WFDLE_STATE 0x4
+#define MAN_FSM_WFVLDCLR_STATE 0x6
+
+// Current STAUPD FSM states.
+#define STAUPD_FSM_IDLE_STATE 0x0
+#define STAUPD_FSM_REQ_STATE 0x2
+#define STAUPD_FSM_WFDLE_STATE 0x4
+
+#define DEW_READ_TEST_VALUE 0x5AA5
+
+//-----macro for manual commnd --------------------------------------------------------
+#define OP_WR (0x1)
+
+#define OP_CSH (0x0)
+#define OP_CSL (0x1)
+#define OP_OUTS (0x8)
+#define OP_OUTD (0x9)
+#define OP_INS (0xC)
+#define OP_IND (0xD)
+
+ #endif // __MT6571_PMIC_WRAP_HW_H__
+
diff --git a/mcu/driver/peripheral/inc/mt6571_pmic_wrap_sw.h b/mcu/driver/peripheral/inc/mt6571_pmic_wrap_sw.h
new file mode 100644
index 0000000..ef00c6c
--- /dev/null
+++ b/mcu/driver/peripheral/inc/mt6571_pmic_wrap_sw.h
@@ -0,0 +1,184 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mt6571_pmic_wrap_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This is for mt6571 pmic wrapper driver s/w usage
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __MT6571_PMIC_WRAP_SW_H__
+#define __MT6571_PMIC_WRAP_SW_H__
+
+#include "drv_comm.h"
+#define PMIC_WRAP_READ 0
+#define PMIC_WRAP_WRITE 1
+
+#define PMIC_WRAP_REG_CLOCK_SAFE_MODE 0
+
+#define PMIC_WRAP_REG_CLOCK_06MHZ 1
+#define PMIC_WRAP_REG_CLOCK_12MHZ 2
+
+#define PMIC_WRAP_REG_CLOCK_18MHZ 1
+#define PMIC_WRAP_REG_CLOCK_36MHZ 2
+
+#define DEW_WRITE_TEST_VALUE 0xA55A
+
+#define PMIC_WRAP_INVALID_RW 0x10
+#define PMIC_WRAP_INVALID_ADDR 0x11
+#define PMIC_WRAP_INVALID_WDATA 0x12
+#define PMIC_WRAP_INVALID_OP 0x13
+#define PMIC_WRAP_INVALID_ARGUMENT 0x14
+
+#define PMIC_WRAP_INIT_SIDLY_FAIL 0x20
+#define PMIC_WRAP_INIT_REG_CLK_FAIL 0x21
+#define PMIC_WRAP_INIT_DUAL_MODE_FAIL 0x22
+#define PMIC_WRAP_INIT_CIPHER_FAIL 0x23
+
+#define PMIC_WRAP_NOT_INIT_DONE 0x30
+#define PMIC_WRAP_NOT_INIT_DONE_READ 0x31
+#define PMIC_WRAP_READ_TEST_FAIL 0x32
+#define PMIC_WRAP_WRITE_TEST_FAIL 0x33
+#define PMIC_WRAP_SWITCH_DIO_FAIL 0x34
+#define PMIC_WRAP_READ_FAIL 0x35
+#define PMIC_WRAP_WRITE_FAIL 0x36
+#define PMIC_WRAP_DEW_EVENT_TEST_FAIL 0x37
+#define PMIC_WRAP_MANUAL_MODE_NOT_IDLE 0x38
+#define PMIC_WRAP_STAUPD_FSM_NOT_IDLE 0x39
+
+
+#define PMIC_WRAP_TIME_OUT_FAIL 0xFF
+
+#define OP_RD (0x0)
+#define OP_WR (0x1)
+
+#define OP_CSH (0x0)
+#define OP_CSL (0x1)
+#define OP_CK (0x2)
+#define OP_OUTS (0x8)
+#define OP_OUTD (0x9)
+#define OP_INS (0xC)
+#define OP_IND (0xD)
+
+#define DRV_WriteReg(addr,data) ((*(volatile kal_uint16 *)(addr)) = (kal_uint16)(data))
+#define DRV_Reg(addr) (*(volatile kal_uint16 *)(addr))
+#define DRV_WriteReg32(addr,data) ((*(volatile kal_uint32 *)(addr)) = (kal_uint32)(data))
+#define DRV_Reg32(addr) (*(volatile kal_uint32 *)(addr))
+#define DRV_WriteReg8(addr,data) ((*(volatile kal_uint8 *)(addr)) = (kal_uint8)(data))
+#define DRV_Reg8(addr) (*(volatile kal_uint8 *)(addr))
+
+#define DRV_ClearBits32(addr,data) {\
+ kal_uint32 temp;\
+ temp = DRV_Reg32(addr);\
+ temp &=~(data);\
+ DRV_WriteReg32(addr,temp);\
+}
+
+#define DRV_SetBits32(addr,data) {\
+ kal_uint32 temp;\
+ temp = DRV_Reg32(addr);\
+ temp |= (data);\
+ DRV_WriteReg32(addr,temp);\
+}
+
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_PMIC_WRAP_REG_DBG__)
+#define PMIC_WRAP_DRV_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
+#define PMIC_WRAP_DRV_SetBits16(addr) DRV_DBG_SetBits(addr)
+#define PMIC_WRAP_DRV_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
+#define PMIC_WRAP_DRV_ReadReg16(addr) DRV_DBG_Reg(addr)
+#define PMIC_WRAP_DRV_ClearBits32(addr, data) DRV_DBG_ClearBits32(addr, data)
+#define PMIC_WRAP_DRV_SetBits32(addr, data) DRV_DBG_SetBits32(addr, data)
+#define PMIC_WRAP_DRV_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define PMIC_WRAP_DRV_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define PMIC_WRAP_DRV_Reg32(addr) DRV_DBG_Reg32(addr)
+#else // #if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RTC_REG_DBG__)
+#define PMIC_WRAP_DRV_ClearBits16(addr, data) DRV_ClearBits(addr,data)
+#define PMIC_WRAP_DRV_SetBits16(addr, data) DRV_SetBits(addr,data)
+#define PMIC_WRAP_DRV_WriteReg16(addr, data) DRV_WriteReg(addr, data)
+#define PMIC_WRAP_DRV_ReadReg16(addr) DRV_Reg(addr)
+#define PMIC_WRAP_DRV_ClearBits32(addr, data) DRV_ClearBits32(addr, data)
+#define PMIC_WRAP_DRV_SetBits32(addr, data) DRV_SetBits32(addr, data)
+#define PMIC_WRAP_DRV_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define PMIC_WRAP_DRV_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define PMIC_WRAP_DRV_Reg32(addr) DRV_Reg32(addr)
+#endif // #if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RTC_REG_DBG__)
+
+kal_uint32 DrvPWRAP_Init(void);
+kal_uint32 DrvPWRAP_WACS2_NoChk(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+//kal_uint32 DrvPWRAP_WACS0(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_WACS0(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint16 *rdata);
+//kal_uint32 DrvPWRAP_WACS1(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_WACS1(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint16 *rdata);
+kal_uint32 DrvPWRAP_WACS2(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_Man(kal_uint32 write, kal_uint32 op, kal_uint32 wdata, kal_uint32 *rdata );
+kal_uint32 DrvPWRAP_ManAccess(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_InitDio(kal_bool dio_en);
+kal_uint32 DrvPWRAP_SwitchDio(kal_bool dio_en);
+kal_uint32 DrvPWRAP_InitCIPHER(void);
+kal_uint32 DrvPWRAP_EnableCIPHER(void);
+kal_uint32 DrvPWRAP_DisableCIPHER(void);
+void DrvPWRAP_ResetSPISLV(void);
+void DrvPWRAP_SwitchMux(kal_uint8 mux_sel_new);
+kal_uint32 DrvPWRAP_InitSiStrobe(void);
+kal_uint32 DrvPWRAP_StaUpdTrig(kal_uint32 mode);
+void DrvPWRAP_AlignCRC(void);
+kal_uint32 DrvPWRAP_InitRegClk(kal_uint32 regck_sel);
+
+typedef kal_uint32 (*loop_condition_fp)(kal_uint32); // Define a function pointer
+
+#endif // __MT6571_PMIC_WRAP_SW_H__
diff --git a/mcu/driver/peripheral/inc/mt6572_pmic_wrap_hw.h b/mcu/driver/peripheral/inc/mt6572_pmic_wrap_hw.h
new file mode 100644
index 0000000..3c0d725
--- /dev/null
+++ b/mcu/driver/peripheral/inc/mt6572_pmic_wrap_hw.h
@@ -0,0 +1,327 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mt6582_pmic_wrap_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This is mt6572 pmic wrapper h/w register
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __MT6572_PMIC_WRAP_HW_H__
+#define __MT6572_PMIC_WRAP_HW_H__
+
+#if !defined(FPGA_CTP)
+#include "reg_base.h"
+
+#define PMIC_WRAP_BASE (AP_PMIC_WRAP_BASE)
+#define TOP_CLOCK_CTRL_BASE (AP_TOP_CLOCK_CTRL_BASE)
+#define TOPRGU_BASE (AP_TOPRGU_BASE)
+
+#else
+#define PMIC_WRAP_BASE (0x1000F000)
+#define TOP_CLOCK_CTRL_BASE (0x10000000)
+#define TOPRGU_BASE (0x10007000)
+
+#endif
+
+#define CLK_SEL_0 (TOP_CLOCK_CTRL_BASE + 0x000)
+#define CLK_SWCG_1 (TOP_CLOCK_CTRL_BASE + 0x024)
+#define CLK_SETCG_1 (TOP_CLOCK_CTRL_BASE + 0x054)
+#define CLK_SETCG_3 (TOP_CLOCK_CTRL_BASE + 0x05C)
+#define CLK_CLRCG_1 (TOP_CLOCK_CTRL_BASE + 0x084)
+#define WDT_SWSYSRST (TOPRGU_BASE + 0x018)
+
+#define INFRA_GLOBALCON_RST0 (AP_INFRACFG_AO_base + 0x030)
+
+#define PMIC_WRAP_MUX_SEL (PMIC_WRAP_BASE+0x0)
+#define PMIC_WRAP_WRAP_EN (PMIC_WRAP_BASE+0x4)
+#define PMIC_WRAP_DIO_EN (PMIC_WRAP_BASE+0x8)
+#define PMIC_WRAP_SIDLY (PMIC_WRAP_BASE+0xC)
+#define PMIC_WRAP_OP_TYPE (PMIC_WRAP_BASE+0x10)
+#define PMIC_WRAP_MSB_FIRST (PMIC_WRAP_BASE+0x14)
+#define PMIC_WRAP_RDDMY (PMIC_WRAP_BASE+0x18)
+#define PMIC_WRAP_SI_CK_CON (PMIC_WRAP_BASE+0x1C)
+#define PMIC_WRAP_CSHEXT_WRITE (PMIC_WRAP_BASE+0x20)
+#define PMIC_WRAP_CSHEXT_READ (PMIC_WRAP_BASE+0x24)
+#define PMIC_WRAP_CSLEXT_START (PMIC_WRAP_BASE+0x28)
+#define PMIC_WRAP_CSLEXT_END (PMIC_WRAP_BASE+0x2C)
+#define PMIC_WRAP_STAUPD_PRD (PMIC_WRAP_BASE+0x30)
+#define PMIC_WRAP_STAUPD_GRPEN (PMIC_WRAP_BASE+0x34)
+#define PMIC_WRAP_STAUPD_MAN_TRIG (PMIC_WRAP_BASE+0x38)
+#define PMIC_WRAP_STAUPD_STA (PMIC_WRAP_BASE+0x3C)
+#define PMIC_WRAP_GPS_STA (PMIC_WRAP_BASE+0x40)
+#define PMIC_WRAP_WRAP_STA (PMIC_WRAP_BASE+0x44)
+#define PMIC_WRAP_HARB_INIT (PMIC_WRAP_BASE+0x48)
+#define PMIC_WRAP_HARB_HPRIO (PMIC_WRAP_BASE+0x4C)
+#define PMIC_WRAP_HIPRIO_ARB_EN (PMIC_WRAP_BASE+0x50)
+#define PMIC_WRAP_HARB_STA0 (PMIC_WRAP_BASE+0x54)
+#define PMIC_WRAP_HARB_STA1 (PMIC_WRAP_BASE+0x58)
+#define PMIC_WRAP_MAN_EN (PMIC_WRAP_BASE+0x5C)
+#define PMIC_WRAP_MAN_CMD (PMIC_WRAP_BASE+0x60)
+#define PMIC_WRAP_MAN_RDATA (PMIC_WRAP_BASE+0x64)
+#define PMIC_WRAP_MAN_VLDCLR (PMIC_WRAP_BASE+0x68)
+#define PMIC_WRAP_WACS0_EN (PMIC_WRAP_BASE+0x6C)
+#define PMIC_WRAP_INIT_DONE0 (PMIC_WRAP_BASE+0x70)
+#define PMIC_WRAP_WACS0_CMD (PMIC_WRAP_BASE+0x74)
+#define PMIC_WRAP_WACS0_RDATA (PMIC_WRAP_BASE+0x78)
+#define PMIC_WRAP_WACS0_VLDCLR (PMIC_WRAP_BASE+0x7C)
+#define PMIC_WRAP_WACS1_EN (PMIC_WRAP_BASE+0x80)
+#define PMIC_WRAP_INIT_DONE1 (PMIC_WRAP_BASE+0x84)
+#define PMIC_WRAP_WACS1_CMD (PMIC_WRAP_BASE+0x88)
+#define PMIC_WRAP_WACS1_RDATA (PMIC_WRAP_BASE+0x8C)
+#define PMIC_WRAP_WACS1_VLDCLR (PMIC_WRAP_BASE+0x90)
+#define PMIC_WRAP_WACS2_EN (PMIC_WRAP_BASE+0x94)
+#define PMIC_WRAP_INIT_DONE2 (PMIC_WRAP_BASE+0x98)
+#define PMIC_WRAP_WACS2_CMD (PMIC_WRAP_BASE+0x9C)
+#define PMIC_WRAP_WACS2_RDATA (PMIC_WRAP_BASE+0xA0)
+#define PMIC_WRAP_WACS2_VLDCLR (PMIC_WRAP_BASE+0xA4)
+#define PMIC_WRAP_INT_EN (PMIC_WRAP_BASE+0xA8)
+#define PMIC_WRAP_INT_FLG_RAW (PMIC_WRAP_BASE+0xAC)
+#define PMIC_WRAP_INT_FLG (PMIC_WRAP_BASE+0xB0)
+#define PMIC_WRAP_INT_CLR (PMIC_WRAP_BASE+0xB4)
+#define PMIC_WRAP_SIG_ADR (PMIC_WRAP_BASE+0xB8)
+#define PMIC_WRAP_SIG_MODE (PMIC_WRAP_BASE+0xBC)
+#define PMIC_WRAP_SIG_VALUE (PMIC_WRAP_BASE+0xC0)
+#define PMIC_WRAP_SIG_ERRVAL (PMIC_WRAP_BASE+0xC4)
+#define PMIC_WRAP_CRC_EN (PMIC_WRAP_BASE+0xC8)
+#define PMIC_WRAP_TIMER_EN (PMIC_WRAP_BASE+0xCC)
+#define PMIC_WRAP_TIMER_STA (PMIC_WRAP_BASE+0xD0)
+#define PMIC_WRAP_WDT_UNIT (PMIC_WRAP_BASE+0xD4)
+#define PMIC_WRAP_WDT_SRC_EN (PMIC_WRAP_BASE+0xD8)
+#define PMIC_WRAP_WDT_FLG (PMIC_WRAP_BASE+0xDC)
+#define PMIC_WRAP_DEBUG_INT_SEL (PMIC_WRAP_BASE+0xE0)
+#define PMIC_WRAP_DVFS_ADR0 (PMIC_WRAP_BASE+0xE4)
+#define PMIC_WRAP_DVFS_WDATA0 (PMIC_WRAP_BASE+0xE8)
+#define PMIC_WRAP_DVFS_ADR1 (PMIC_WRAP_BASE+0xEC)
+#define PMIC_WRAP_DVFS_WDATA1 (PMIC_WRAP_BASE+0xF0)
+#define PMIC_WRAP_DVFS_ADR2 (PMIC_WRAP_BASE+0xF4)
+#define PMIC_WRAP_DVFS_WDATA2 (PMIC_WRAP_BASE+0xF8)
+#define PMIC_WRAP_DVFS_ADR3 (PMIC_WRAP_BASE+0xFC)
+#define PMIC_WRAP_DVFS_WDATA3 (PMIC_WRAP_BASE+0x100)
+#define PMIC_WRAP_DVFS_ADR4 (PMIC_WRAP_BASE+0x104)
+#define PMIC_WRAP_DVFS_WDATA4 (PMIC_WRAP_BASE+0x108)
+#define PMIC_WRAP_DVFS_ADR5 (PMIC_WRAP_BASE+0x10C)
+#define PMIC_WRAP_DVFS_WDATA5 (PMIC_WRAP_BASE+0x110)
+#define PMIC_WRAP_DVFS_ADR6 (PMIC_WRAP_BASE+0x114)
+#define PMIC_WRAP_DVFS_WDATA6 (PMIC_WRAP_BASE+0x118)
+#define PMIC_WRAP_DVFS_ADR7 (PMIC_WRAP_BASE+0x11C)
+#define PMIC_WRAP_DVFS_WDATA7 (PMIC_WRAP_BASE+0x120)
+#define PMIC_WRAP_CIPHER_KEY_SEL (PMIC_WRAP_BASE+0x124)
+#define PMIC_WRAP_CIPHER_IV_SEL (PMIC_WRAP_BASE+0x128)
+#define PMIC_WRAP_CIPHER_EN (PMIC_WRAP_BASE+0x12C)
+#define PMIC_WRAP_CIPHER_RDY (PMIC_WRAP_BASE+0x130)
+#define PMIC_WRAP_CIPHER_MODE (PMIC_WRAP_BASE+0x134)
+#define PMIC_WRAP_CIPHER_SWRST (PMIC_WRAP_BASE+0x138)
+#define PMIC_WRAP_DCM_EN (PMIC_WRAP_BASE+0x13C)
+#define PMIC_WRAP_DCM_DBC_PRD (PMIC_WRAP_BASE+0x140)
+#define PMIC_WRAP_ADC_CMD_ADDR (PMIC_WRAP_BASE+0x144)
+#define PMIC_WRAP_PWRAP_ADC_CMD (PMIC_WRAP_BASE+0x148)
+#define PMIC_WRAP_ADC_RDY_ADDR (PMIC_WRAP_BASE+0x14C)
+#define PMIC_WRAP_ADC_RDATA_ADDR1 (PMIC_WRAP_BASE+0x150)
+#define PMIC_WRAP_ADC_RDATA_ADDR2 (PMIC_WRAP_BASE+0x154)
+#define PMIC_WRAP_SWRST (PMIC_WRAP_BASE+0x180)
+#define PMIC_WRAP_DEBUG_SEL (PMIC_WRAP_BASE+0x190)
+
+// Bit Control
+#define GET_STAUPD_DLE_CNT(x) ((x>>0) & 0x00000007)
+#define GET_STAUPD_ALE_CNT(x) ((x>>3) & 0x00000007)
+#define GET_STAUPD_FSM(x) ((x>>6) & 0x00000007)
+#define GET_PWRAP_GPS_ACK(x) ((x>>0) & 0x00000001)
+#define GET_GPS_PWRAP_REQ(x) ((x>>1) & 0x00000001)
+#define GET_GPSINF_DLE_CNT(x) ((x>>4) & 0x00000003)
+#define GET_GPSINF_ALE_CNT(x) ((x>>6) & 0x00000003)
+#define GET_GPS_INF_FSM(x) ((x>>8) & 0x00000007)
+#define GET_PWRAP_GPS_WDATA(x) ((x>>15) & 0x0001ffff)
+#define GET_WRAP_CH_DLE_RESTCNT(x) ((x>>0) & 0x00000007)
+#define GET_WRAP_CH_ALE_RESTCNT(x) ((x>>3) & 0x00000003)
+#define GET_WRAP_AG_DLE_RESTCNT(x) ((x>>5) & 0x00000003)
+#define GET_WRAP_CH_W(x) ((x>>7) & 0x00000001)
+#define GET_WRAP_CH_REQ(x) ((x>>8) & 0x00000001)
+#define GET_AG_WRAP_W(x) ((x>>9) & 0x00000001)
+#define GET_AG_WRAP_REQ(x) ((x>>10) & 0x00000001)
+#define GET_WRAP_FSM(x) ((x>>11) & 0x0000000f)
+#define GET_HARB_WRAP_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_HARB_WRAP_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_HARB_WRAP_REQ(x) ((x>>31) & 0x00000001)
+#define GET_HARB_DLE_EMPTY(x) ((x>>0) & 0x00000001)
+#define GET_HARB_DLE_FULL(x) ((x>>1) & 0x00000001)
+#define GET_HARB_VLD(x) ((x>>2) & 0x00000001)
+#define GET_HARB_DLE_OWN(x) ((x>>3) & 0x0000000f)
+#define GET_HARB_OWN(x) ((x>>7) & 0x0000000f)
+#define GET_HARB_DLE_RESTCNT(x) ((x>>11) & 0x0000000f)
+#define GET_AG_HARB_REQ(x) ((x>>15) & 0x0000007f)
+#define GET_HARB_WRAP_W(x) ((x>>22) & 0x00000001)
+#define GET_HARB_WRAP_REQ0(x) ((x>>23) & 0x00000001)
+#define GET_SPI_WDATA(x) ((x>>0) & 0x000000ff)
+#define GET_SPI_OP(x) ((x>>8) & 0x0000001f)
+#define GET_SPI_W(x) ((x>>13) & 0x00000001)
+#define GET_MAN_RDATA(x) ((x>>0) & 0x000000ff)
+#define GET_MAN_FSM(x) ((x>>8) & 0x00000007)
+#define GET_MAN_REQ(x) ((x>>11) & 0x00000001)
+#define GET_WACS0_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS0_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS0_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS0_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS0_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS0_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE0(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE0(x) ((x>>21) & 0x00000001)
+#define GET_WACS1_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS1_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS1_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS1_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS1_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS1_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE1(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE1(x) ((x>>21) & 0x00000001)
+#define GET_WACS2_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS2_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS2_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS2_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS2_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS2_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE2(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE2(x) ((x>>21) & 0x00000001)
+
+#define GET_WACS_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE(x) ((x>>21) & 0x00000001)
+
+#define SPI_AUTO_MODE 0
+#define SPI_MANUAL_MODE 1
+#define HARB_HPRIO_ALL 0x1FF
+#define HARB_HPRIO_RRAPB (1 << 8)
+#define HARB_HPRIO_PERI_PWRAP (1 << 7)
+#define HARB_HPRIO_STAUPD (1 << 6)
+#define HARB_HPRIO_ERC (1 << 5)
+#define HARB_HPRIO_DVFSINF (1 << 4)
+#define HARB_HPRIO_WACS2 (1 << 3)
+#define HARB_HPRIO_WACS1 (1 << 2)
+#define HARB_HPRIO_WACS0 (1 << 1)
+#define HARB_HPRIO_MDINF (1 << 0)
+
+
+// Current WRAP FSM states.
+#define WRAP_FSM_IDLE_STATE 0x0
+#define WRAP_FSM_CSL_ADR_START_STATE 0x2
+#define WRAP_FSM_ADR_STATE 0x4
+#define WRAP_FSM_CSL_ADR_END_STATE 0x6
+#define WRAP_FSM_CSH_ADR_STATE 0x8
+#define WRAP_FSM_CSL_DATA_START_STATE 0xA
+#define WRAP_FSM_DATA_STATE 0xC
+#define WRAP_FSM_CSL_DATA_END_STATE 0xE
+#define WRAP_FSM_CSH_DATA_STATE 0xF
+
+#define WACS_INIT_DONE_NOT_FINISHED 0
+#define WACS_INIT_DONE_FINISHED 1
+
+
+#define WACS_SYNC_MODULE_BUSY 0
+#define WACS_SYNC_MODULE_IDLE 1
+
+// Current WACS FSM states.
+#define WACS_FSM_IDLE_STATE 0x0
+#define WACS_FSM_REQ_STATE 0x2
+#define WACS_FSM_WFDLE_STATE 0x4
+#define WACS_FSM_WFVLDCLR_STATE 0x6
+
+// Current MAN FSM states.
+#define MAN_FSM_IDLE_STATE 0x0
+#define MAN_FSM_REQ_STATE 0x2
+#define MAN_FSM_WFDLE_STATE 0x4
+#define MAN_FSM_WFVLDCLR_STATE 0x6
+
+// Current STAUPD FSM states.
+#define STAUPD_FSM_IDLE_STATE 0x0
+#define STAUPD_FSM_REQ_STATE 0x2
+#define STAUPD_FSM_WFDLE_STATE 0x4
+
+#define DEW_READ_TEST_VALUE 0x5AA5
+
+//-----macro for manual commnd --------------------------------------------------------
+#define OP_WR (0x1)
+
+#define OP_CSH (0x0)
+#define OP_CSL (0x1)
+#define OP_OUTS (0x8)
+#define OP_OUTD (0x9)
+#define OP_INS (0xC)
+#define OP_IND (0xD)
+
+ #endif // __MT6572_PMIC_WRAP_HW_H__
+
diff --git a/mcu/driver/peripheral/inc/mt6572_pmic_wrap_sw.h b/mcu/driver/peripheral/inc/mt6572_pmic_wrap_sw.h
new file mode 100644
index 0000000..999efba
--- /dev/null
+++ b/mcu/driver/peripheral/inc/mt6572_pmic_wrap_sw.h
@@ -0,0 +1,193 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mt6572_pmic_wrap_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This is for mt6572 pmic wrapper driver s/w usage
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __MT6572_PMIC_WRAP_SW_H__
+#define __MT6572_PMIC_WRAP_SW_H__
+
+#include "drv_comm.h"
+#define PMIC_WRAP_READ 0
+#define PMIC_WRAP_WRITE 1
+
+#define PMIC_WRAP_REG_CLOCK_SAFE_MODE 0
+
+#define PMIC_WRAP_REG_CLOCK_06MHZ 1
+#define PMIC_WRAP_REG_CLOCK_12MHZ 2
+
+#define PMIC_WRAP_REG_CLOCK_18MHZ 1
+#define PMIC_WRAP_REG_CLOCK_36MHZ 2
+
+#define DEW_WRITE_TEST_VALUE 0xA55A
+
+#define PMIC_WRAP_INVALID_RW 0x10
+#define PMIC_WRAP_INVALID_ADDR 0x11
+#define PMIC_WRAP_INVALID_WDATA 0x12
+#define PMIC_WRAP_INVALID_OP 0x13
+#define PMIC_WRAP_INVALID_ARGUMENT 0x14
+
+#define PMIC_WRAP_INIT_SIDLY_FAIL 0x20
+#define PMIC_WRAP_INIT_REG_CLK_FAIL 0x21
+#define PMIC_WRAP_INIT_DUAL_MODE_FAIL 0x22
+#define PMIC_WRAP_INIT_CIPHER_FAIL 0x23
+
+#define PMIC_WRAP_NOT_INIT_DONE 0x30
+#define PMIC_WRAP_NOT_INIT_DONE_READ 0x31
+#define PMIC_WRAP_READ_TEST_FAIL 0x32
+#define PMIC_WRAP_WRITE_TEST_FAIL 0x33
+#define PMIC_WRAP_SWITCH_DIO_FAIL 0x34
+#define PMIC_WRAP_READ_FAIL 0x35
+#define PMIC_WRAP_WRITE_FAIL 0x36
+#define PMIC_WRAP_DEW_EVENT_TEST_FAIL 0x37
+#define PMIC_WRAP_MANUAL_MODE_NOT_IDLE 0x38
+#define PMIC_WRAP_STAUPD_FSM_NOT_IDLE 0x39
+
+
+#define PMIC_WRAP_TIME_OUT_FAIL 0xFF
+
+#define OP_RD (0x0)
+#define OP_WR (0x1)
+
+#define OP_CSH (0x0)
+#define OP_CSL (0x1)
+#define OP_CK (0x2)
+#define OP_OUTS (0x8)
+#define OP_OUTD (0x9)
+#define OP_INS (0xC)
+#define OP_IND (0xD)
+
+#define DRV_WriteReg(addr,data) ((*(volatile kal_uint16 *)(addr)) = (kal_uint16)(data))
+#define DRV_Reg(addr) (*(volatile kal_uint16 *)(addr))
+#define DRV_WriteReg32(addr,data) ((*(volatile kal_uint32 *)(addr)) = (kal_uint32)(data))
+#define DRV_Reg32(addr) (*(volatile kal_uint32 *)(addr))
+#define DRV_WriteReg8(addr,data) ((*(volatile kal_uint8 *)(addr)) = (kal_uint8)(data))
+#define DRV_Reg8(addr) (*(volatile kal_uint8 *)(addr))
+
+#define DRV_ClearBits32(addr,data) {\
+ kal_uint32 temp;\
+ temp = DRV_Reg32(addr);\
+ temp &=~(data);\
+ DRV_WriteReg32(addr,temp);\
+}
+
+#define DRV_SetBits32(addr,data) {\
+ kal_uint32 temp;\
+ temp = DRV_Reg32(addr);\
+ temp |= (data);\
+ DRV_WriteReg32(addr,temp);\
+}
+
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_PMIC_WRAP_REG_DBG__)
+#define PMIC_WRAP_DRV_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
+#define PMIC_WRAP_DRV_SetBits16(addr) DRV_DBG_SetBits(addr)
+#define PMIC_WRAP_DRV_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
+#define PMIC_WRAP_DRV_ReadReg16(addr) DRV_DBG_Reg(addr)
+#define PMIC_WRAP_DRV_ClearBits32(addr, data) DRV_DBG_ClearBits32(addr, data)
+#define PMIC_WRAP_DRV_SetBits32(addr, data) DRV_DBG_SetBits32(addr, data)
+#define PMIC_WRAP_DRV_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define PMIC_WRAP_DRV_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define PMIC_WRAP_DRV_Reg32(addr) DRV_DBG_Reg32(addr)
+#else // #if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RTC_REG_DBG__)
+#define PMIC_WRAP_DRV_ClearBits16(addr, data) DRV_ClearBits(addr,data)
+#define PMIC_WRAP_DRV_SetBits16(addr, data) DRV_SetBits(addr,data)
+#define PMIC_WRAP_DRV_WriteReg16(addr, data) DRV_WriteReg(addr, data)
+#define PMIC_WRAP_DRV_ReadReg16(addr) DRV_Reg(addr)
+#define PMIC_WRAP_DRV_ClearBits32(addr, data) DRV_ClearBits32(addr, data)
+#define PMIC_WRAP_DRV_SetBits32(addr, data) DRV_SetBits32(addr, data)
+#define PMIC_WRAP_DRV_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define PMIC_WRAP_DRV_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define PMIC_WRAP_DRV_Reg32(addr) DRV_Reg32(addr)
+#endif // #if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RTC_REG_DBG__)
+
+kal_uint32 DrvPWRAP_Init(void);
+kal_uint32 DrvPWRAP_WACS2_NoChk(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+//kal_uint32 DrvPWRAP_WACS0(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_WACS0(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint16 *rdata);
+//kal_uint32 DrvPWRAP_WACS1(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_WACS1(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint16 *rdata);
+kal_uint32 DrvPWRAP_WACS2(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_Man(kal_uint32 write, kal_uint32 op, kal_uint32 wdata, kal_uint32 *rdata );
+kal_uint32 DrvPWRAP_ManAccess(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_InitDio(kal_bool dio_en);
+kal_uint32 DrvPWRAP_SwitchDio(kal_bool dio_en);
+kal_uint32 DrvPWRAP_InitCIPHER(void);
+kal_uint32 DrvPWRAP_EnableCIPHER(void);
+kal_uint32 DrvPWRAP_DisableCIPHER(void);
+void DrvPWRAP_ResetSPISLV(void);
+void DrvPWRAP_SwitchMux(kal_uint8 mux_sel_new);
+kal_uint32 DrvPWRAP_InitSiStrobe(void);
+kal_uint32 DrvPWRAP_StaUpdTrig(kal_uint32 mode);
+void DrvPWRAP_AlignCRC(void);
+kal_uint32 DrvPWRAP_InitRegClk(kal_uint32 regck_sel);
+
+typedef kal_uint32 (*loop_condition_fp)(kal_uint32); // Define a function pointer
+
+#endif // __MT6572_PMIC_WRAP_SW_H__
diff --git a/mcu/driver/peripheral/inc/mt6582_pmic_wrap_hw.h b/mcu/driver/peripheral/inc/mt6582_pmic_wrap_hw.h
new file mode 100644
index 0000000..4f85724
--- /dev/null
+++ b/mcu/driver/peripheral/inc/mt6582_pmic_wrap_hw.h
@@ -0,0 +1,315 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mt6582_pmic_wrap_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This is mt6582 pmic wrapper h/w register
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __MT6582_PMIC_WRAP_HW_H__
+#define __MT6582_PMIC_WRAP_HW_H__
+
+#if !defined(FPGA_CTP)
+#include "reg_base.h"
+#define PMIC_WRAP_BASE (AP_PMIC_WRAP_BASE)
+#define CKSYS_BASE (AP_CKSYS_BASE)
+#define AP_INFRACFG_AO_base (AP_INFRACFG_AO_BASE)
+
+#else
+#define AP_PMIC_WRAP_base PMIC_WRAP_BASE
+#define AP_INFRACFG_AO_base INFRACFG_BASE
+#define CKSYS_BASE (0x10000000)
+
+#endif
+
+#define CLK_CFG_4_CLR (CKSYS_BASE + 0x088)
+
+#define INFRA_GLOBALCON_RST0 (AP_INFRACFG_AO_base + 0x030)
+
+#define PMIC_WRAP_MUX_SEL (PMIC_WRAP_BASE+0x0)
+#define PMIC_WRAP_WRAP_EN (PMIC_WRAP_BASE+0x4)
+#define PMIC_WRAP_DIO_EN (PMIC_WRAP_BASE+0x8)
+#define PMIC_WRAP_SIDLY (PMIC_WRAP_BASE+0xC)
+#define PMIC_WRAP_OP_TYPE (PMIC_WRAP_BASE+0x10)
+#define PMIC_WRAP_MSB_FIRST (PMIC_WRAP_BASE+0x14)
+#define PMIC_WRAP_RDDMY (PMIC_WRAP_BASE+0x18)
+#define PMIC_WRAP_SI_CK_CON (PMIC_WRAP_BASE+0x1C)
+#define PMIC_WRAP_CSHEXT_WRITE (PMIC_WRAP_BASE+0x20)
+#define PMIC_WRAP_CSHEXT_READ (PMIC_WRAP_BASE+0x24)
+#define PMIC_WRAP_CSLEXT_START (PMIC_WRAP_BASE+0x28)
+#define PMIC_WRAP_CSLEXT_END (PMIC_WRAP_BASE+0x2C)
+#define PMIC_WRAP_STAUPD_PRD (PMIC_WRAP_BASE+0x30)
+#define PMIC_WRAP_STAUPD_GRPEN (PMIC_WRAP_BASE+0x34)
+#define PMIC_WRAP_STAUPD_MAN_TRIG (PMIC_WRAP_BASE+0x38)
+#define PMIC_WRAP_STAUPD_STA (PMIC_WRAP_BASE+0x3C)
+#define PMIC_WRAP_GPS_STA (PMIC_WRAP_BASE+0x40)
+#define PMIC_WRAP_WRAP_STA (PMIC_WRAP_BASE+0x44)
+#define PMIC_WRAP_HARB_INIT (PMIC_WRAP_BASE+0x48)
+#define PMIC_WRAP_HARB_HPRIO (PMIC_WRAP_BASE+0x4C)
+#define PMIC_WRAP_HIPRIO_ARB_EN (PMIC_WRAP_BASE+0x50)
+#define PMIC_WRAP_HARB_STA0 (PMIC_WRAP_BASE+0x54)
+#define PMIC_WRAP_HARB_STA1 (PMIC_WRAP_BASE+0x58)
+#define PMIC_WRAP_MAN_EN (PMIC_WRAP_BASE+0x5C)
+#define PMIC_WRAP_MAN_CMD (PMIC_WRAP_BASE+0x60)
+#define PMIC_WRAP_MAN_RDATA (PMIC_WRAP_BASE+0x64)
+#define PMIC_WRAP_MAN_VLDCLR (PMIC_WRAP_BASE+0x68)
+#define PMIC_WRAP_WACS0_EN (PMIC_WRAP_BASE+0x6C)
+#define PMIC_WRAP_INIT_DONE0 (PMIC_WRAP_BASE+0x70)
+#define PMIC_WRAP_WACS0_CMD (PMIC_WRAP_BASE+0x74)
+#define PMIC_WRAP_WACS0_RDATA (PMIC_WRAP_BASE+0x78)
+#define PMIC_WRAP_WACS0_VLDCLR (PMIC_WRAP_BASE+0x7C)
+#define PMIC_WRAP_WACS1_EN (PMIC_WRAP_BASE+0x80)
+#define PMIC_WRAP_INIT_DONE1 (PMIC_WRAP_BASE+0x84)
+#define PMIC_WRAP_WACS1_CMD (PMIC_WRAP_BASE+0x88)
+#define PMIC_WRAP_WACS1_RDATA (PMIC_WRAP_BASE+0x8C)
+#define PMIC_WRAP_WACS1_VLDCLR (PMIC_WRAP_BASE+0x90)
+#define PMIC_WRAP_WACS2_EN (PMIC_WRAP_BASE+0x94)
+#define PMIC_WRAP_INIT_DONE2 (PMIC_WRAP_BASE+0x98)
+#define PMIC_WRAP_WACS2_CMD (PMIC_WRAP_BASE+0x9C)
+#define PMIC_WRAP_WACS2_RDATA (PMIC_WRAP_BASE+0xA0)
+#define PMIC_WRAP_WACS2_VLDCLR (PMIC_WRAP_BASE+0xA4)
+#define PMIC_WRAP_INT_EN (PMIC_WRAP_BASE+0xA8)
+#define PMIC_WRAP_INT_FLG_RAW (PMIC_WRAP_BASE+0xAC)
+#define PMIC_WRAP_INT_FLG (PMIC_WRAP_BASE+0xB0)
+#define PMIC_WRAP_INT_CLR (PMIC_WRAP_BASE+0xB4)
+#define PMIC_WRAP_SIG_ADR (PMIC_WRAP_BASE+0xB8)
+#define PMIC_WRAP_SIG_MODE (PMIC_WRAP_BASE+0xBC)
+#define PMIC_WRAP_SIG_VALUE (PMIC_WRAP_BASE+0xC0)
+#define PMIC_WRAP_SIG_ERRVAL (PMIC_WRAP_BASE+0xC4)
+#define PMIC_WRAP_CRC_EN (PMIC_WRAP_BASE+0xC8)
+#define PMIC_WRAP_TIMER_EN (PMIC_WRAP_BASE+0xCC)
+#define PMIC_WRAP_TIMER_STA (PMIC_WRAP_BASE+0xD0)
+#define PMIC_WRAP_WDT_UNIT (PMIC_WRAP_BASE+0xD4)
+#define PMIC_WRAP_WDT_SRC_EN (PMIC_WRAP_BASE+0xD8)
+#define PMIC_WRAP_WDT_FLG (PMIC_WRAP_BASE+0xDC)
+#define PMIC_WRAP_DEBUG_INT_SEL (PMIC_WRAP_BASE+0xE0)
+#define PMIC_WRAP_DVFS_ADR0 (PMIC_WRAP_BASE+0xE4)
+#define PMIC_WRAP_DVFS_WDATA0 (PMIC_WRAP_BASE+0xE8)
+#define PMIC_WRAP_DVFS_ADR1 (PMIC_WRAP_BASE+0xEC)
+#define PMIC_WRAP_DVFS_WDATA1 (PMIC_WRAP_BASE+0xF0)
+#define PMIC_WRAP_DVFS_ADR2 (PMIC_WRAP_BASE+0xF4)
+#define PMIC_WRAP_DVFS_WDATA2 (PMIC_WRAP_BASE+0xF8)
+#define PMIC_WRAP_DVFS_ADR3 (PMIC_WRAP_BASE+0xFC)
+#define PMIC_WRAP_DVFS_WDATA3 (PMIC_WRAP_BASE+0x100)
+#define PMIC_WRAP_DVFS_ADR4 (PMIC_WRAP_BASE+0x104)
+#define PMIC_WRAP_DVFS_WDATA4 (PMIC_WRAP_BASE+0x108)
+#define PMIC_WRAP_DVFS_ADR5 (PMIC_WRAP_BASE+0x10C)
+#define PMIC_WRAP_DVFS_WDATA5 (PMIC_WRAP_BASE+0x110)
+#define PMIC_WRAP_DVFS_ADR6 (PMIC_WRAP_BASE+0x114)
+#define PMIC_WRAP_DVFS_WDATA6 (PMIC_WRAP_BASE+0x118)
+#define PMIC_WRAP_DVFS_ADR7 (PMIC_WRAP_BASE+0x11C)
+#define PMIC_WRAP_DVFS_WDATA7 (PMIC_WRAP_BASE+0x120)
+#define PMIC_WRAP_CIPHER_KEY_SEL (PMIC_WRAP_BASE+0x124)
+#define PMIC_WRAP_CIPHER_IV_SEL (PMIC_WRAP_BASE+0x128)
+#define PMIC_WRAP_CIPHER_EN (PMIC_WRAP_BASE+0x12C)
+#define PMIC_WRAP_CIPHER_RDY (PMIC_WRAP_BASE+0x130)
+#define PMIC_WRAP_CIPHER_MODE (PMIC_WRAP_BASE+0x134)
+#define PMIC_WRAP_CIPHER_SWRST (PMIC_WRAP_BASE+0x138)
+#define PMIC_WRAP_DCM_EN (PMIC_WRAP_BASE+0x13C)
+#define PMIC_WRAP_DCM_DBC_PRD (PMIC_WRAP_BASE+0x140)
+#define PMIC_WRAP_ADC_CMD_ADDR (PMIC_WRAP_BASE+0x144)
+#define PMIC_WRAP_PWRAP_ADC_CMD (PMIC_WRAP_BASE+0x148)
+#define PMIC_WRAP_ADC_RDY_ADDR (PMIC_WRAP_BASE+0x14C)
+#define PMIC_WRAP_ADC_RDATA_ADDR1 (PMIC_WRAP_BASE+0x150)
+#define PMIC_WRAP_ADC_RDATA_ADDR2 (PMIC_WRAP_BASE+0x154)
+
+// Bit Control
+#define GET_STAUPD_DLE_CNT(x) ((x>>0) & 0x00000007)
+#define GET_STAUPD_ALE_CNT(x) ((x>>3) & 0x00000007)
+#define GET_STAUPD_FSM(x) ((x>>6) & 0x00000007)
+#define GET_PWRAP_GPS_ACK(x) ((x>>0) & 0x00000001)
+#define GET_GPS_PWRAP_REQ(x) ((x>>1) & 0x00000001)
+#define GET_GPSINF_DLE_CNT(x) ((x>>4) & 0x00000003)
+#define GET_GPSINF_ALE_CNT(x) ((x>>6) & 0x00000003)
+#define GET_GPS_INF_FSM(x) ((x>>8) & 0x00000007)
+#define GET_PWRAP_GPS_WDATA(x) ((x>>15) & 0x0001ffff)
+#define GET_WRAP_CH_DLE_RESTCNT(x) ((x>>0) & 0x00000007)
+#define GET_WRAP_CH_ALE_RESTCNT(x) ((x>>3) & 0x00000003)
+#define GET_WRAP_AG_DLE_RESTCNT(x) ((x>>5) & 0x00000003)
+#define GET_WRAP_CH_W(x) ((x>>7) & 0x00000001)
+#define GET_WRAP_CH_REQ(x) ((x>>8) & 0x00000001)
+#define GET_AG_WRAP_W(x) ((x>>9) & 0x00000001)
+#define GET_AG_WRAP_REQ(x) ((x>>10) & 0x00000001)
+#define GET_WRAP_FSM(x) ((x>>11) & 0x0000000f)
+#define GET_HARB_WRAP_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_HARB_WRAP_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_HARB_WRAP_REQ(x) ((x>>31) & 0x00000001)
+#define GET_HARB_DLE_EMPTY(x) ((x>>0) & 0x00000001)
+#define GET_HARB_DLE_FULL(x) ((x>>1) & 0x00000001)
+#define GET_HARB_VLD(x) ((x>>2) & 0x00000001)
+#define GET_HARB_DLE_OWN(x) ((x>>3) & 0x0000000f)
+#define GET_HARB_OWN(x) ((x>>7) & 0x0000000f)
+#define GET_HARB_DLE_RESTCNT(x) ((x>>11) & 0x0000000f)
+#define GET_AG_HARB_REQ(x) ((x>>15) & 0x0000007f)
+#define GET_HARB_WRAP_W(x) ((x>>22) & 0x00000001)
+#define GET_HARB_WRAP_REQ0(x) ((x>>23) & 0x00000001)
+#define GET_SPI_WDATA(x) ((x>>0) & 0x000000ff)
+#define GET_SPI_OP(x) ((x>>8) & 0x0000001f)
+#define GET_SPI_W(x) ((x>>13) & 0x00000001)
+#define GET_MAN_RDATA(x) ((x>>0) & 0x000000ff)
+#define GET_MAN_FSM(x) ((x>>8) & 0x00000007)
+#define GET_MAN_REQ(x) ((x>>11) & 0x00000001)
+#define GET_WACS0_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS0_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS0_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS0_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS0_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS0_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE0(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE0(x) ((x>>21) & 0x00000001)
+#define GET_WACS1_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS1_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS1_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS1_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS1_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS1_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE1(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE1(x) ((x>>21) & 0x00000001)
+#define GET_WACS2_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS2_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS2_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS2_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS2_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS2_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE2(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE2(x) ((x>>21) & 0x00000001)
+
+#define GET_WACS_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE(x) ((x>>21) & 0x00000001)
+
+#define SPI_AUTO_MODE 0
+#define SPI_MANUAL_MODE 1
+#define HARB_HPRIO_ALL 0x1FF
+#define HARB_HPRIO_RRAPB (1 << 8)
+#define HARB_HPRIO_PERI_PWRAP (1 << 7)
+#define HARB_HPRIO_STAUPD (1 << 6)
+#define HARB_HPRIO_ERC (1 << 5)
+#define HARB_HPRIO_DVFSINF (1 << 4)
+#define HARB_HPRIO_WACS2 (1 << 3)
+#define HARB_HPRIO_WACS1 (1 << 2)
+#define HARB_HPRIO_WACS0 (1 << 1)
+#define HARB_HPRIO_MDINF (1 << 0)
+
+
+// Current WRAP FSM states.
+#define WRAP_FSM_IDLE_STATE 0x0
+#define WRAP_FSM_CSL_ADR_START_STATE 0x2
+#define WRAP_FSM_ADR_STATE 0x4
+#define WRAP_FSM_CSL_ADR_END_STATE 0x6
+#define WRAP_FSM_CSH_ADR_STATE 0x8
+#define WRAP_FSM_CSL_DATA_START_STATE 0xA
+#define WRAP_FSM_DATA_STATE 0xC
+#define WRAP_FSM_CSL_DATA_END_STATE 0xE
+#define WRAP_FSM_CSH_DATA_STATE 0xF
+
+#define WACS_INIT_DONE_NOT_FINISHED 0
+#define WACS_INIT_DONE_FINISHED 1
+
+
+#define WACS_SYNC_MODULE_BUSY 0
+#define WACS_SYNC_MODULE_IDLE 1
+
+// Current WACS FSM states.
+#define WACS_FSM_IDLE_STATE 0x0
+#define WACS_FSM_REQ_STATE 0x2
+#define WACS_FSM_WFDLE_STATE 0x4
+#define WACS_FSM_WFVLDCLR_STATE 0x6
+
+// Current MAN FSM states.
+#define MAN_FSM_IDLE_STATE 0x0
+#define MAN_FSM_REQ_STATE 0x2
+#define MAN_FSM_WFDLE_STATE 0x4
+#define MAN_FSM_WFVLDCLR_STATE 0x6
+
+// Current STAUPD FSM states.
+#define STAUPD_FSM_IDLE_STATE 0x0
+#define STAUPD_FSM_REQ_STATE 0x2
+#define STAUPD_FSM_WFDLE_STATE 0x4
+
+#define DEW_READ_TEST_VALUE 0x5AA5
+
+//-----macro for manual commnd --------------------------------------------------------
+#define OP_WR (0x1)
+
+#define OP_CSH (0x0)
+#define OP_CSL (0x1)
+#define OP_OUTS (0x8)
+#define OP_OUTD (0x9)
+#define OP_INS (0xC)
+#define OP_IND (0xD)
+
+ #endif // __MT6582_PMIC_WRAP_HW_H__
+
diff --git a/mcu/driver/peripheral/inc/mt6582_pmic_wrap_sw.h b/mcu/driver/peripheral/inc/mt6582_pmic_wrap_sw.h
new file mode 100644
index 0000000..6536d46
--- /dev/null
+++ b/mcu/driver/peripheral/inc/mt6582_pmic_wrap_sw.h
@@ -0,0 +1,193 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mt6582_pmic_wrap_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This is for mt6582 pmic wrapper driver s/w usage
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __MT6582_PMIC_WRAP_SW_H__
+#define __MT6582_PMIC_WRAP_SW_H__
+
+#include "drv_comm.h"
+#define PMIC_WRAP_READ 0
+#define PMIC_WRAP_WRITE 1
+
+#define PMIC_WRAP_REG_CLOCK_SAFE_MODE 0
+
+#define PMIC_WRAP_REG_CLOCK_06MHZ 1
+#define PMIC_WRAP_REG_CLOCK_12MHZ 2
+
+#define PMIC_WRAP_REG_CLOCK_18MHZ 1
+#define PMIC_WRAP_REG_CLOCK_36MHZ 2
+
+#define DEW_WRITE_TEST_VALUE 0xA55A
+
+#define PMIC_WRAP_INVALID_RW 0x10
+#define PMIC_WRAP_INVALID_ADDR 0x11
+#define PMIC_WRAP_INVALID_WDATA 0x12
+#define PMIC_WRAP_INVALID_OP 0x13
+#define PMIC_WRAP_INVALID_ARGUMENT 0x14
+
+#define PMIC_WRAP_INIT_SIDLY_FAIL 0x20
+#define PMIC_WRAP_INIT_REG_CLK_FAIL 0x21
+#define PMIC_WRAP_INIT_DUAL_MODE_FAIL 0x22
+#define PMIC_WRAP_INIT_CIPHER_FAIL 0x23
+
+#define PMIC_WRAP_NOT_INIT_DONE 0x30
+#define PMIC_WRAP_NOT_INIT_DONE_READ 0x31
+#define PMIC_WRAP_READ_TEST_FAIL 0x32
+#define PMIC_WRAP_WRITE_TEST_FAIL 0x33
+#define PMIC_WRAP_SWITCH_DIO_FAIL 0x34
+#define PMIC_WRAP_READ_FAIL 0x35
+#define PMIC_WRAP_WRITE_FAIL 0x36
+#define PMIC_WRAP_DEW_EVENT_TEST_FAIL 0x37
+#define PMIC_WRAP_MANUAL_MODE_NOT_IDLE 0x38
+#define PMIC_WRAP_STAUPD_FSM_NOT_IDLE 0x39
+
+
+#define PMIC_WRAP_TIME_OUT_FAIL 0xFF
+
+#define OP_RD (0x0)
+#define OP_WR (0x1)
+
+#define OP_CSH (0x0)
+#define OP_CSL (0x1)
+#define OP_CK (0x2)
+#define OP_OUTS (0x8)
+#define OP_OUTD (0x9)
+#define OP_INS (0xC)
+#define OP_IND (0xD)
+
+#define DRV_WriteReg(addr,data) ((*(volatile kal_uint16 *)(addr)) = (kal_uint16)(data))
+#define DRV_Reg(addr) (*(volatile kal_uint16 *)(addr))
+#define DRV_WriteReg32(addr,data) ((*(volatile kal_uint32 *)(addr)) = (kal_uint32)(data))
+#define DRV_Reg32(addr) (*(volatile kal_uint32 *)(addr))
+#define DRV_WriteReg8(addr,data) ((*(volatile kal_uint8 *)(addr)) = (kal_uint8)(data))
+#define DRV_Reg8(addr) (*(volatile kal_uint8 *)(addr))
+
+#define DRV_ClearBits32(addr,data) {\
+ kal_uint32 temp;\
+ temp = DRV_Reg32(addr);\
+ temp &=~(data);\
+ DRV_WriteReg32(addr,temp);\
+}
+
+#define DRV_SetBits32(addr,data) {\
+ kal_uint32 temp;\
+ temp = DRV_Reg32(addr);\
+ temp |= (data);\
+ DRV_WriteReg32(addr,temp);\
+}
+
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_PMIC_WRAP_REG_DBG__)
+#define PMIC_WRAP_DRV_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
+#define PMIC_WRAP_DRV_SetBits16(addr) DRV_DBG_SetBits(addr)
+#define PMIC_WRAP_DRV_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
+#define PMIC_WRAP_DRV_ReadReg16(addr) DRV_DBG_Reg(addr)
+#define PMIC_WRAP_DRV_ClearBits32(addr, data) DRV_DBG_ClearBits32(addr, data)
+#define PMIC_WRAP_DRV_SetBits32(addr, data) DRV_DBG_SetBits32(addr, data)
+#define PMIC_WRAP_DRV_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define PMIC_WRAP_DRV_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define PMIC_WRAP_DRV_Reg32(addr) DRV_DBG_Reg32(addr)
+#else // #if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RTC_REG_DBG__)
+#define PMIC_WRAP_DRV_ClearBits16(addr, data) DRV_ClearBits(addr,data)
+#define PMIC_WRAP_DRV_SetBits16(addr, data) DRV_SetBits(addr,data)
+#define PMIC_WRAP_DRV_WriteReg16(addr, data) DRV_WriteReg(addr, data)
+#define PMIC_WRAP_DRV_ReadReg16(addr) DRV_Reg(addr)
+#define PMIC_WRAP_DRV_ClearBits32(addr, data) DRV_ClearBits32(addr, data)
+#define PMIC_WRAP_DRV_SetBits32(addr, data) DRV_SetBits32(addr, data)
+#define PMIC_WRAP_DRV_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define PMIC_WRAP_DRV_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define PMIC_WRAP_DRV_Reg32(addr) DRV_Reg32(addr)
+#endif // #if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RTC_REG_DBG__)
+
+kal_uint32 DrvPWRAP_Init(void);
+kal_uint32 DrvPWRAP_WACS2_NoChk(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+//kal_uint32 DrvPWRAP_WACS0(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_WACS0(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint16 *rdata);
+//kal_uint32 DrvPWRAP_WACS1(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_WACS1(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint16 *rdata);
+kal_uint32 DrvPWRAP_WACS2(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_Man(kal_uint32 write, kal_uint32 op, kal_uint32 wdata, kal_uint32 *rdata );
+kal_uint32 DrvPWRAP_ManAccess(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_InitDio(kal_bool dio_en);
+kal_uint32 DrvPWRAP_SwitchDio(kal_bool dio_en);
+kal_uint32 DrvPWRAP_InitCIPHER(void);
+kal_uint32 DrvPWRAP_EnableCIPHER(void);
+kal_uint32 DrvPWRAP_DisableCIPHER(void);
+void DrvPWRAP_ResetSPISLV(void);
+void DrvPWRAP_SwitchMux(kal_uint8 mux_sel_new);
+kal_uint32 DrvPWRAP_InitSiStrobe(void);
+kal_uint32 DrvPWRAP_StaUpdTrig(kal_uint32 mode);
+void DrvPWRAP_AlignCRC(void);
+kal_uint32 DrvPWRAP_InitRegClk(kal_uint32 regck_sel);
+
+typedef kal_uint32 (*loop_condition_fp)(kal_uint32); // Define a function pointer
+
+#endif // __MT6582_PMIC_WRAP_SW_H__
diff --git a/mcu/driver/peripheral/inc/mt6589_pmic_wrap_hw.h b/mcu/driver/peripheral/inc/mt6589_pmic_wrap_hw.h
new file mode 100644
index 0000000..5bce139
--- /dev/null
+++ b/mcu/driver/peripheral/inc/mt6589_pmic_wrap_hw.h
@@ -0,0 +1,309 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mt6589_pmic_wrap_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This is mt6589 pmic wrapper h/w register
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __MT6752_PMIC_WRAP_HW_H__
+#define __MT6589_PMIC_WRAP_HW_H__
+
+#include "reg_base.h"
+
+#define PMIC_WRAP_BASE (AP_PMIC_WRAP_base)
+
+#define WDT_SWSYSRST (AP_TOPRGU_base + 0x18)
+#define CLK_CFG_8 (AP_TOPRGU_base + 0x164)
+
+#define INFRA_GLOBALCON_RST0 (AP_INFRACFG_AO_base + 0x030)
+
+#define PERI_GLOBALCON_RST1 (AP_PERICFG_base + 0x004)
+
+#define PMIC_WRAP_MUX_SEL (PMIC_WRAP_BASE+0x0)
+#define PMIC_WRAP_WRAP_EN (PMIC_WRAP_BASE+0x4)
+#define PMIC_WRAP_DIO_EN (PMIC_WRAP_BASE+0x8)
+#define PMIC_WRAP_SIDLY (PMIC_WRAP_BASE+0xC)
+#define PMIC_WRAP_CSHEXT (PMIC_WRAP_BASE+0x10)
+#define PMIC_WRAP_CSHEXT_WRITE (PMIC_WRAP_BASE+0x14)
+#define PMIC_WRAP_CSHEXT_READ (PMIC_WRAP_BASE+0x18)
+#define PMIC_WRAP_CSLEXT_START (PMIC_WRAP_BASE+0x1C)
+#define PMIC_WRAP_CSLEXT_END (PMIC_WRAP_BASE+0x20)
+#define PMIC_WRAP_STAUPD_PRD (PMIC_WRAP_BASE+0x24)
+#define PMIC_WRAP_STAUPD_GRPEN (PMIC_WRAP_BASE+0x28)
+#define PMIC_WRAP_STAUPD_MAN_TRIG (PMIC_WRAP_BASE+0x2C)
+#define PMIC_WRAP_STAUPD_STA (PMIC_WRAP_BASE+0x30)
+#define PMIC_WRAP_EVENT_IN_EN (PMIC_WRAP_BASE+0x34)
+#define PMIC_WRAP_EVENT_DST_EN (PMIC_WRAP_BASE+0x38)
+#define PMIC_WRAP_WRAP_STA (PMIC_WRAP_BASE+0x3C)
+#define PMIC_WRAP_RRARB_INIT (PMIC_WRAP_BASE+0x40)
+#define PMIC_WRAP_RRARB_EN (PMIC_WRAP_BASE+0x44)
+#define PMIC_WRAP_RRARB_STA0 (PMIC_WRAP_BASE+0x48)
+#define PMIC_WRAP_RRARB_STA1 (PMIC_WRAP_BASE+0x4C)
+#define PMIC_WRAP_HARB_INIT (PMIC_WRAP_BASE+0x50)
+#define PMIC_WRAP_HARB_HPRIO (PMIC_WRAP_BASE+0x54)
+#define PMIC_WRAP_HIPRIO_ARB_EN (PMIC_WRAP_BASE+0x58)
+#define PMIC_WRAP_HARB_STA0 (PMIC_WRAP_BASE+0x5C)
+#define PMIC_WRAP_HARB_STA1 (PMIC_WRAP_BASE+0x60)
+#define PMIC_WRAP_MAN_EN (PMIC_WRAP_BASE+0x64)
+#define PMIC_WRAP_MAN_CMD (PMIC_WRAP_BASE+0x68)
+#define PMIC_WRAP_MAN_RDATA (PMIC_WRAP_BASE+0x6C)
+#define PMIC_WRAP_MAN_VLDCLR (PMIC_WRAP_BASE+0x70)
+#define PMIC_WRAP_WACS0_EN (PMIC_WRAP_BASE+0x74)
+#define PMIC_WRAP_INIT_DONE0 (PMIC_WRAP_BASE+0x78)
+#define PMIC_WRAP_WACS0_CMD (PMIC_WRAP_BASE+0x7C)
+#define PMIC_WRAP_WACS0_RDATA (PMIC_WRAP_BASE+0x80)
+#define PMIC_WRAP_WACS0_VLDCLR (PMIC_WRAP_BASE+0x84)
+#define PMIC_WRAP_WACS1_EN (PMIC_WRAP_BASE+0x88)
+#define PMIC_WRAP_INIT_DONE1 (PMIC_WRAP_BASE+0x8C)
+#define PMIC_WRAP_WACS1_CMD (PMIC_WRAP_BASE+0x90)
+#define PMIC_WRAP_WACS1_RDATA (PMIC_WRAP_BASE+0x94)
+#define PMIC_WRAP_WACS1_VLDCLR (PMIC_WRAP_BASE+0x98)
+#define PMIC_WRAP_WACS2_EN (PMIC_WRAP_BASE+0x9C)
+#define PMIC_WRAP_INIT_DONE2 (PMIC_WRAP_BASE+0xA0)
+#define PMIC_WRAP_WACS2_CMD (PMIC_WRAP_BASE+0xA4)
+#define PMIC_WRAP_WACS2_RDATA (PMIC_WRAP_BASE+0xA8)
+#define PMIC_WRAP_WACS2_VLDCLR (PMIC_WRAP_BASE+0xAC)
+#define PMIC_WRAP_INT_EN (PMIC_WRAP_BASE+0xB0)
+#define PMIC_WRAP_INT_FLG_RAW (PMIC_WRAP_BASE+0xB4)
+#define PMIC_WRAP_INT_FLG (PMIC_WRAP_BASE+0xB8)
+#define PMIC_WRAP_INT_CLR (PMIC_WRAP_BASE+0xBC)
+#define PMIC_WRAP_SIG_ADR (PMIC_WRAP_BASE+0xC0)
+#define PMIC_WRAP_SIG_MODE (PMIC_WRAP_BASE+0xC4)
+#define PMIC_WRAP_SIG_VALUE (PMIC_WRAP_BASE+0xC8)
+#define PMIC_WRAP_SIG_ERRVAL (PMIC_WRAP_BASE+0xCC)
+#define PMIC_WRAP_CRC_EN (PMIC_WRAP_BASE+0xD0)
+#define PMIC_WRAP_EVENT_STA (PMIC_WRAP_BASE+0xD4)
+#define PMIC_WRAP_EVENT_STACLR (PMIC_WRAP_BASE+0xD8)
+#define PMIC_WRAP_TIMER_EN (PMIC_WRAP_BASE+0xDC)
+#define PMIC_WRAP_TIMER_STA (PMIC_WRAP_BASE+0xE0)
+#define PMIC_WRAP_WDT_UNIT (PMIC_WRAP_BASE+0xE4)
+#define PMIC_WRAP_WDT_SRC_EN (PMIC_WRAP_BASE+0xE8)
+#define PMIC_WRAP_WDT_FLG (PMIC_WRAP_BASE+0xEC)
+#define PMIC_WRAP_DEBUG_INT_SEL (PMIC_WRAP_BASE+0xF0)
+#define PMIC_WRAP_DVFS_ADR0 (PMIC_WRAP_BASE+0xF4)
+#define PMIC_WRAP_DVFS_WDATA0 (PMIC_WRAP_BASE+0xF8)
+#define PMIC_WRAP_DVFS_ADR1 (PMIC_WRAP_BASE+0xFC)
+#define PMIC_WRAP_DVFS_WDATA1 (PMIC_WRAP_BASE+0x100)
+#define PMIC_WRAP_DVFS_ADR2 (PMIC_WRAP_BASE+0x104)
+#define PMIC_WRAP_DVFS_WDATA2 (PMIC_WRAP_BASE+0x108)
+#define PMIC_WRAP_DVFS_ADR3 (PMIC_WRAP_BASE+0x10C)
+#define PMIC_WRAP_DVFS_WDATA3 (PMIC_WRAP_BASE+0x110)
+#define PMIC_WRAP_DVFS_ADR4 (PMIC_WRAP_BASE+0x114)
+#define PMIC_WRAP_DVFS_WDATA4 (PMIC_WRAP_BASE+0x118)
+#define PMIC_WRAP_DVFS_ADR5 (PMIC_WRAP_BASE+0x11C)
+#define PMIC_WRAP_DVFS_WDATA5 (PMIC_WRAP_BASE+0x120)
+#define PMIC_WRAP_DVFS_ADR6 (PMIC_WRAP_BASE+0x124)
+#define PMIC_WRAP_DVFS_WDATA6 (PMIC_WRAP_BASE+0x128)
+#define PMIC_WRAP_DVFS_ADR7 (PMIC_WRAP_BASE+0x12C)
+#define PMIC_WRAP_DVFS_WDATA7 (PMIC_WRAP_BASE+0x130)
+#define PMIC_WRAP_CIPHER_KEY_SEL (PMIC_WRAP_BASE+0x134)
+#define PMIC_WRAP_CIPHER_IV_SEL (PMIC_WRAP_BASE+0x138)
+#define PMIC_WRAP_CIPHER_LOAD (PMIC_WRAP_BASE+0x13C)
+#define PMIC_WRAP_CIPHER_START (PMIC_WRAP_BASE+0x140)
+#define PMIC_WRAP_CIPHER_RDY (PMIC_WRAP_BASE+0x144)
+#define PMIC_WRAP_CIPHER_MODE (PMIC_WRAP_BASE+0x148)
+#define PMIC_WRAP_CIPHER_SWRST (PMIC_WRAP_BASE+0x14C)
+#define PMIC_WRAP_CIPHER_IV0 (PMIC_WRAP_BASE+0x150)
+#define PMIC_WRAP_CIPHER_IV1 (PMIC_WRAP_BASE+0x154)
+#define PMIC_WRAP_CIPHER_IV2 (PMIC_WRAP_BASE+0x158)
+#define PMIC_WRAP_DCM_EN (PMIC_WRAP_BASE+0x15C)
+#define PMIC_WRAP_DCM_DBC_PRD (PMIC_WRAP_BASE+0x160)
+
+// Bit Control
+#define GET_STAUPD_DLE_CNT(x) ((x>>0) & 0x00000007)
+#define GET_STAUPD_ALE_CNT(x) ((x>>3) & 0x00000007)
+#define GET_STAUPD_FSM(x) ((x>>6) & 0x00000007)
+#define GET_WRAP_CH_DLE_RESTCNT(x) ((x>>0) & 0x00000007)
+#define GET_WRAP_CH_ALE_RESTCNT(x) ((x>>3) & 0x00000003)
+#define GET_WRAP_AG_DLE_RESTCNT(x) ((x>>5) & 0x00000003)
+#define GET_WRAP_CH_W(x) ((x>>7) & 0x00000001)
+#define GET_WRAP_CH_REQ(x) ((x>>8) & 0x00000001)
+#define GET_AG_WRAP_W(x) ((x>>9) & 0x00000001)
+#define GET_AG_WRAP_REQ(x) ((x>>10) & 0x00000001)
+#define GET_WRAP_FSM(x) ((x>>11) & 0x0000000f)
+#define GET_HARB_WRAP_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_HARB_WRAP_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_HARB_WRAP_REQ(x) ((x>>31) & 0x00000001)
+#define GET_HARB_DLE_EMPTY(x) ((x>>0) & 0x00000001)
+#define GET_HARB_DLE_FULL(x) ((x>>1) & 0x00000001)
+#define GET_HARB_VLD(x) ((x>>2) & 0x00000001)
+#define GET_HARB_DLE_OWN(x) ((x>>3) & 0x0000000f)
+#define GET_HARB_OWN(x) ((x>>7) & 0x0000000f)
+#define GET_HARB_DLE_RESTCNT(x) ((x>>11) & 0x0000000f)
+#define GET_AG_HARB_REQ(x) ((x>>15) & 0x000001ff)
+#define GET_HARB_WRAP_W(x) ((x>>24) & 0x00000001)
+#define GET_HARB_WRAP_REQ0(x) ((x>>25) & 0x00000001)
+#define GET_SPI_WDATA(x) ((x>>0) & 0x000000ff)
+#define GET_SPI_OP(x) ((x>>8) & 0x0000001f)
+#define GET_SPI_W(x) ((x>>13) & 0x00000001)
+#define GET_MAN_RDATA(x) ((x>>0) & 0x000000ff)
+#define GET_MAN_FSM(x) ((x>>8) & 0x00000007)
+#define GET_MAN_REQ(x) ((x>>11) & 0x00000001)
+#define GET_WACS0_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS0_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS0_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS0_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS0_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS0_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE0(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE0(x) ((x>>21) & 0x00000001)
+#define GET_WACS1_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS1_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS1_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS1_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS1_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS1_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE1(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE1(x) ((x>>21) & 0x00000001)
+#define GET_WACS2_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS2_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS2_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS2_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS2_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS2_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE2(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE2(x) ((x>>21) & 0x00000001)
+
+#define GET_WACS_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE(x) ((x>>21) & 0x00000001)
+
+#define SPI_AUTO_MODE 0
+#define SPI_MANUAL_MODE 1
+#define HARB_HPRIO_ALL 0x1FF
+#define HARB_HPRIO_RRAPB (1 << 8)
+#define HARB_HPRIO_PERI_PWRAP (1 << 7)
+#define HARB_HPRIO_STAUPD (1 << 6)
+#define HARB_HPRIO_ERC (1 << 5)
+#define HARB_HPRIO_DVFSINF (1 << 4)
+#define HARB_HPRIO_WACS2 (1 << 3)
+#define HARB_HPRIO_WACS1 (1 << 2)
+#define HARB_HPRIO_WACS0 (1 << 1)
+#define HARB_HPRIO_MDINF (1 << 0)
+
+
+// Current WRAP FSM states.
+#define WRAP_FSM_IDLE_STATE 0x0
+#define WRAP_FSM_CSL_ADR_START_STATE 0x2
+#define WRAP_FSM_ADR_STATE 0x4
+#define WRAP_FSM_CSL_ADR_END_STATE 0x6
+#define WRAP_FSM_CSH_ADR_STATE 0x8
+#define WRAP_FSM_CSL_DATA_START_STATE 0xA
+#define WRAP_FSM_DATA_STATE 0xC
+#define WRAP_FSM_CSL_DATA_END_STATE 0xE
+#define WRAP_FSM_CSH_DATA_STATE 0xF
+
+#define WACS_INIT_DONE_NOT_FINISHED 0
+#define WACS_INIT_DONE_FINISHED 1
+
+
+#define WACS_SYNC_MODULE_BUSY 0
+#define WACS_SYNC_MODULE_IDLE 1
+
+// Current WACS FSM states.
+#define WACS_FSM_IDLE_STATE 0x0
+#define WACS_FSM_REQ_STATE 0x2
+#define WACS_FSM_WFDLE_STATE 0x4
+#define WACS_FSM_WFVLDCLR_STATE 0x6
+
+// Current MAN FSM states.
+#define MAN_FSM_IDLE_STATE 0x0
+#define MAN_FSM_REQ_STATE 0x2
+#define MAN_FSM_WFDLE_STATE 0x4
+#define MAN_FSM_WFVLDCLR_STATE 0x6
+
+// Current STAUPD FSM states.
+#define STAUPD_FSM_IDLE_STATE 0x0
+#define STAUPD_FSM_REQ_STATE 0x2
+#define STAUPD_FSM_WFDLE_STATE 0x4
+
+#define DEW_READ_TEST_VALUE 0x5AA5
+
+//-----macro for manual commnd --------------------------------------------------------
+#define OP_WR (0x1)
+
+#define OP_CSH (0x0)
+#define OP_CSL (0x1)
+#define OP_OUTS (0x8)
+#define OP_OUTD (0x9)
+#define OP_INS (0xC)
+#define OP_IND (0xD)
+
+ #endif // __MT6752_PMIC_WRAP_HW_H__
+
diff --git a/mcu/driver/peripheral/inc/mt6589_pmic_wrap_sw.h b/mcu/driver/peripheral/inc/mt6589_pmic_wrap_sw.h
new file mode 100644
index 0000000..03f1433
--- /dev/null
+++ b/mcu/driver/peripheral/inc/mt6589_pmic_wrap_sw.h
@@ -0,0 +1,190 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mt6589_pmic_wrap_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This is for mt6589 pmic wrapper driver s/w usage
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __MT6752_PMIC_WRAP_SW_H__
+#define __MT6589_PMIC_WRAP_SW_H__
+
+#include "drv_comm.h"
+#define PMIC_WRAP_READ 0
+#define PMIC_WRAP_WRITE 1
+
+#define PMIC_WRAP_REG_CLOCK_SAFE_MODE 0
+#define PMIC_WRAP_REG_CLOCK_18MHZ 1
+#define PMIC_WRAP_REG_CLOCK_36MHZ 2
+
+#define DEW_WRITE_TEST_VALUE 0xA55A
+
+#define PMIC_WRAP_INVALID_RW 0x10
+#define PMIC_WRAP_INVALID_ADDR 0x11
+#define PMIC_WRAP_INVALID_WDATA 0x12
+#define PMIC_WRAP_INVALID_OP 0x13
+#define PMIC_WRAP_INVALID_ARGUMENT 0x14
+
+#define PMIC_WRAP_INIT_SIDLY_FAIL 0x20
+#define PMIC_WRAP_INIT_REG_CLK_FAIL 0x21
+#define PMIC_WRAP_INIT_DUAL_MODE_FAIL 0x22
+#define PMIC_WRAP_INIT_CIPHER_FAIL 0x23
+
+#define PMIC_WRAP_NOT_INIT_DONE 0x30
+#define PMIC_WRAP_NOT_INIT_DONE_READ 0x31
+#define PMIC_WRAP_READ_TEST_FAIL 0x32
+#define PMIC_WRAP_WRITE_TEST_FAIL 0x33
+#define PMIC_WRAP_SWITCH_DIO_FAIL 0x34
+#define PMIC_WRAP_READ_FAIL 0x35
+#define PMIC_WRAP_WRITE_FAIL 0x36
+#define PMIC_WRAP_DEW_EVENT_TEST_FAIL 0x37
+#define PMIC_WRAP_MANUAL_MODE_NOT_IDLE 0x38
+#define PMIC_WRAP_STAUPD_FSM_NOT_IDLE 0x39
+
+
+#define PMIC_WRAP_TIME_OUT_FAIL 0xFF
+
+#define OP_RD (0x0)
+#define OP_WR (0x1)
+
+#define OP_CSH (0x0)
+#define OP_CSL (0x1)
+#define OP_OUTS (0x8)
+#define OP_OUTD (0x9)
+#define OP_INS (0xC)
+#define OP_IND (0xD)
+
+#define DRV_WriteReg(addr,data) ((*(volatile kal_uint16 *)(addr)) = (kal_uint16)(data))
+#define DRV_Reg(addr) (*(volatile kal_uint16 *)(addr))
+#define DRV_WriteReg32(addr,data) ((*(volatile kal_uint32 *)(addr)) = (kal_uint32)(data))
+#define DRV_Reg32(addr) (*(volatile kal_uint32 *)(addr))
+#define DRV_WriteReg8(addr,data) ((*(volatile kal_uint8 *)(addr)) = (kal_uint8)(data))
+#define DRV_Reg8(addr) (*(volatile kal_uint8 *)(addr))
+
+#define DRV_ClearBits32(addr,data) {\
+ kal_uint32 temp;\
+ temp = DRV_Reg32(addr);\
+ temp &=~(data);\
+ DRV_WriteReg32(addr,temp);\
+}
+
+#define DRV_SetBits32(addr,data) {\
+ kal_uint32 temp;\
+ temp = DRV_Reg32(addr);\
+ temp |= (data);\
+ DRV_WriteReg32(addr,temp);\
+}
+
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_PMIC_WRAP_REG_DBG__)
+#define PMIC_WRAP_DRV_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
+#define PMIC_WRAP_DRV_SetBits16(addr) DRV_DBG_SetBits(addr)
+#define PMIC_WRAP_DRV_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
+#define PMIC_WRAP_DRV_ReadReg16(addr) DRV_DBG_Reg(addr)
+#define PMIC_WRAP_DRV_ClearBits32(addr, data) DRV_DBG_ClearBits32(addr, data)
+#define PMIC_WRAP_DRV_SetBits32(addr, data) DRV_DBG_SetBits32(addr, data)
+#define PMIC_WRAP_DRV_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define PMIC_WRAP_DRV_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define PMIC_WRAP_DRV_Reg32(addr) DRV_DBG_Reg32(addr)
+#else // #if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RTC_REG_DBG__)
+#define PMIC_WRAP_DRV_ClearBits16(addr, data) DRV_ClearBits(addr,data)
+#define PMIC_WRAP_DRV_SetBits16(addr, data) DRV_SetBits(addr,data)
+#define PMIC_WRAP_DRV_WriteReg16(addr, data) DRV_WriteReg(addr, data)
+#define PMIC_WRAP_DRV_ReadReg16(addr) DRV_Reg(addr)
+#define PMIC_WRAP_DRV_ClearBits32(addr, data) DRV_ClearBits32(addr, data)
+#define PMIC_WRAP_DRV_SetBits32(addr, data) DRV_SetBits32(addr, data)
+#define PMIC_WRAP_DRV_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define PMIC_WRAP_DRV_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define PMIC_WRAP_DRV_Reg32(addr) DRV_Reg32(addr)
+#endif // #if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RTC_REG_DBG__)
+
+kal_uint32 DrvPWRAP_Init(void);
+kal_uint32 DrvPWRAP_WACS2_NoChk(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+//kal_uint32 DrvPWRAP_WACS0(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_WACS0(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint16 *rdata);
+//kal_uint32 DrvPWRAP_WACS1(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_WACS1(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint16 *rdata);
+kal_uint32 DrvPWRAP_WACS2(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_WACS3(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_WACS4(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_Man(kal_uint32 write, kal_uint32 op, kal_uint32 wdata, kal_uint32 *rdata );
+kal_uint32 DrvPWRAP_ManAccess(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_InitDio(kal_bool dio_en);
+kal_uint32 DrvPWRAP_SwitchDio(kal_bool dio_en);
+kal_uint32 DrvPWRAP_InitCIPHER(void);
+kal_uint32 DrvPWRAP_EnableCIPHER(void);
+kal_uint32 DrvPWRAP_DisableCIPHER(void);
+void DrvPWRAP_ResetSPISLV(void);
+kal_uint32 DrvPWRAP_EventTest( void );
+void DrvPWRAP_SwitchMux(kal_uint8 mux_sel_new);
+kal_uint32 DrvPWRAP_InitSIDLY(void);
+kal_uint32 DrvPWRAP_StaUpdTrig(kal_uint32 mode);
+void DrvPWRAP_AlignCRC(void);
+kal_uint32 DrvPWRAP_InitRegClk(kal_uint32 regck_sel);
+
+typedef kal_uint32 (*loop_condition_fp)(kal_uint32); // Define a function pointer
+
+#endif // __MT6752_PMIC_WRAP_SW_H__
diff --git a/mcu/driver/peripheral/inc/mt6752_pmic_wrap_hw.h b/mcu/driver/peripheral/inc/mt6752_pmic_wrap_hw.h
new file mode 100644
index 0000000..b589d9b
--- /dev/null
+++ b/mcu/driver/peripheral/inc/mt6752_pmic_wrap_hw.h
@@ -0,0 +1,375 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mt6752_pmic_wrap_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This is mt6752 pmic wrapper h/w register
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __MT6752_PMIC_WRAP_HW_H__
+#define __MT6752_PMIC_WRAP_HW_H__
+
+#if !defined(FPGA_CTP)
+#include "reg_base.h"
+
+/*
+#define TOP_CLOCK_CTRL_BASE (AP_TOP_CLOCK_CTRL_BASE)
+#define TOPRGU_BASE (AP_TOPRGU_BASE)
+*/
+#define PMIC_WRAP_BASE (PWRAP_BASE)
+#define PMIC_WRAP_P2P_BASE (0xA005E000)
+#else
+#define PMIC_WRAP_BASE (0x1000D000)
+#define CKSYS_BASE (0x10000000)
+#define INFRACFG_AO_BASE (0x10001000)
+#define PMIC_WRAP_P2P_BASE (0x1005E000)
+#endif
+
+#define CLK_CFG_5_CLR (CKSYS_BASE + 0x098)
+
+#define INFRA_GLOBALCON_RST0_SET (INFRACFG_AO_BASE+0x120)
+#define INFRA_GLOBALCON_RST0_CLR (INFRACFG_AO_BASE+0x124)
+
+#define PERI_BUS_DCM_CTRL (INFRACFG_AO_BASE+0x074)
+#define MODULE_SW_CG_0_SET (INFRACFG_AO_BASE+0x080)
+#define MODULE_SW_CG_0_CLR (INFRACFG_AO_BASE+0x084)
+#define MODULE_SW_CG_0_STA (INFRACFG_AO_BASE+0x090)
+
+#define PMIC_WRAP_MUX_SEL (PMIC_WRAP_BASE+0x0)
+#define PMIC_WRAP_WRAP_EN (PMIC_WRAP_BASE+0x4)
+#define PMIC_WRAP_DIO_EN (PMIC_WRAP_BASE+0x8)
+#define PMIC_WRAP_SIDLY (PMIC_WRAP_BASE+0xC)
+#define PMIC_WRAP_RDDMY (PMIC_WRAP_BASE+0x10)
+#define PMIC_WRAP_SI_CK_CON (PMIC_WRAP_BASE+0x14)
+#define PMIC_WRAP_CSHEXT_WRITE (PMIC_WRAP_BASE+0x18)
+#define PMIC_WRAP_CSHEXT_READ (PMIC_WRAP_BASE+0x1C)
+#define PMIC_WRAP_CSLEXT_START (PMIC_WRAP_BASE+0x20)
+#define PMIC_WRAP_CSLEXT_END (PMIC_WRAP_BASE+0x24)
+#define PMIC_WRAP_STAUPD_PRD (PMIC_WRAP_BASE+0x28)
+#define PMIC_WRAP_STAUPD_GRPEN (PMIC_WRAP_BASE+0x2C)
+#define PMIC_WRAP_EINT_STA0_ADR (PMIC_WRAP_BASE+0x30)
+#define PMIC_WRAP_EINT_STA1_ADR (PMIC_WRAP_BASE+0x34)
+#define PMIC_WRAP_EINT_STA (PMIC_WRAP_BASE+0x38)
+#define PMIC_WRAP_EINT_CLR (PMIC_WRAP_BASE+0x3C)
+#define PMIC_WRAP_STAUPD_MAN_TRIG (PMIC_WRAP_BASE+0x40)
+#define PMIC_WRAP_STAUPD_STA (PMIC_WRAP_BASE+0x44)
+#define PMIC_WRAP_WRAP_STA (PMIC_WRAP_BASE+0x48)
+#define PMIC_WRAP_HARB_INIT (PMIC_WRAP_BASE+0x4C)
+#define PMIC_WRAP_HARB_HPRIO (PMIC_WRAP_BASE+0x50)
+#define PMIC_WRAP_HIPRIO_ARB_EN (PMIC_WRAP_BASE+0x54)
+#define PMIC_WRAP_HARB_STA0 (PMIC_WRAP_BASE+0x58)
+#define PMIC_WRAP_HARB_STA1 (PMIC_WRAP_BASE+0x5C)
+#define PMIC_WRAP_MAN_EN (PMIC_WRAP_BASE+0x60)
+#define PMIC_WRAP_MAN_CMD (PMIC_WRAP_BASE+0x64)
+#define PMIC_WRAP_MAN_RDATA (PMIC_WRAP_BASE+0x68)
+#define PMIC_WRAP_MAN_VLDCLR (PMIC_WRAP_BASE+0x6C)
+#define PMIC_WRAP_WACS0_EN (PMIC_WRAP_BASE+0x70)
+#define PMIC_WRAP_INIT_DONE0 (PMIC_WRAP_BASE+0x74)
+#define PMIC_WRAP_WACS0_CMD (PMIC_WRAP_BASE+0x78)
+#define PMIC_WRAP_WACS0_RDATA (PMIC_WRAP_BASE+0x7C)
+#define PMIC_WRAP_WACS0_VLDCLR (PMIC_WRAP_BASE+0x80)
+#define PMIC_WRAP_WACS1_EN (PMIC_WRAP_BASE+0x84)
+#define PMIC_WRAP_INIT_DONE1 (PMIC_WRAP_BASE+0x88)
+#define PMIC_WRAP_WACS1_CMD (PMIC_WRAP_BASE+0x8C)
+#define PMIC_WRAP_WACS1_RDATA (PMIC_WRAP_BASE+0x90)
+#define PMIC_WRAP_WACS1_VLDCLR (PMIC_WRAP_BASE+0x94)
+#define PMIC_WRAP_WACS2_EN (PMIC_WRAP_BASE+0x98)
+#define PMIC_WRAP_INIT_DONE2 (PMIC_WRAP_BASE+0x9C)
+#define PMIC_WRAP_WACS2_CMD (PMIC_WRAP_BASE+0xA0)
+#define PMIC_WRAP_WACS2_RDATA (PMIC_WRAP_BASE+0xA4)
+#define PMIC_WRAP_WACS2_VLDCLR (PMIC_WRAP_BASE+0xA8)
+#define PMIC_WRAP_INT_EN (PMIC_WRAP_BASE+0xAC)
+#define PMIC_WRAP_INT_FLG_RAW (PMIC_WRAP_BASE+0xB0)
+#define PMIC_WRAP_INT_FLG (PMIC_WRAP_BASE+0xB4)
+#define PMIC_WRAP_INT_CLR (PMIC_WRAP_BASE+0xB8)
+#define PMIC_WRAP_SIG_ADR (PMIC_WRAP_BASE+0xBC)
+#define PMIC_WRAP_SIG_MODE (PMIC_WRAP_BASE+0xC0)
+#define PMIC_WRAP_SIG_VALUE (PMIC_WRAP_BASE+0xC4)
+#define PMIC_WRAP_SIG_ERRVAL (PMIC_WRAP_BASE+0xC8)
+#define PMIC_WRAP_CRC_EN (PMIC_WRAP_BASE+0xCC)
+#define PMIC_WRAP_TIMER_EN (PMIC_WRAP_BASE+0xD0)
+#define PMIC_WRAP_TIMER_STA (PMIC_WRAP_BASE+0xD4)
+#define PMIC_WRAP_WDT_UNIT (PMIC_WRAP_BASE+0xD8)
+#define PMIC_WRAP_WDT_SRC_EN (PMIC_WRAP_BASE+0xDC)
+#define PMIC_WRAP_WDT_FLG (PMIC_WRAP_BASE+0xE0)
+#define PMIC_WRAP_DEBUG_INT_SEL (PMIC_WRAP_BASE+0xE4)
+#define PMIC_WRAP_DVFS_ADR0 (PMIC_WRAP_BASE+0xE8)
+#define PMIC_WRAP_DVFS_WDATA0 (PMIC_WRAP_BASE+0xEC)
+#define PMIC_WRAP_DVFS_ADR1 (PMIC_WRAP_BASE+0xF0)
+#define PMIC_WRAP_DVFS_WDATA1 (PMIC_WRAP_BASE+0xF4)
+#define PMIC_WRAP_DVFS_ADR2 (PMIC_WRAP_BASE+0xF8)
+#define PMIC_WRAP_DVFS_WDATA2 (PMIC_WRAP_BASE+0xFC)
+#define PMIC_WRAP_DVFS_ADR3 (PMIC_WRAP_BASE+0x100)
+#define PMIC_WRAP_DVFS_WDATA3 (PMIC_WRAP_BASE+0x104)
+#define PMIC_WRAP_DVFS_ADR4 (PMIC_WRAP_BASE+0x108)
+#define PMIC_WRAP_DVFS_WDATA4 (PMIC_WRAP_BASE+0x10C)
+#define PMIC_WRAP_DVFS_ADR5 (PMIC_WRAP_BASE+0x110)
+#define PMIC_WRAP_DVFS_WDATA5 (PMIC_WRAP_BASE+0x114)
+#define PMIC_WRAP_DVFS_ADR6 (PMIC_WRAP_BASE+0x118)
+#define PMIC_WRAP_DVFS_WDATA6 (PMIC_WRAP_BASE+0x11C)
+#define PMIC_WRAP_DVFS_ADR7 (PMIC_WRAP_BASE+0x120)
+#define PMIC_WRAP_DVFS_WDATA7 (PMIC_WRAP_BASE+0x124)
+#define PMIC_WRAP_SPMINF_STA (PMIC_WRAP_BASE+0x128)
+#define PMIC_WRAP_CIPHER_KEY_SEL (PMIC_WRAP_BASE+0x12C)
+#define PMIC_WRAP_CIPHER_IV_SEL (PMIC_WRAP_BASE+0x130)
+#define PMIC_WRAP_CIPHER_EN (PMIC_WRAP_BASE+0x134)
+#define PMIC_WRAP_CIPHER_RDY (PMIC_WRAP_BASE+0x138)
+#define PMIC_WRAP_CIPHER_MODE (PMIC_WRAP_BASE+0x13C)
+#define PMIC_WRAP_CIPHER_SWRST (PMIC_WRAP_BASE+0x140)
+#define PMIC_WRAP_DCM_EN (PMIC_WRAP_BASE+0x144)
+#define PMIC_WRAP_DCM_DBC_PRD (PMIC_WRAP_BASE+0x148)
+#define PMIC_WRAP_EXT_CK (PMIC_WRAP_BASE+0x14C)
+#define PMIC_WRAP_ADC_CMD_ADDR (PMIC_WRAP_BASE+0x150)
+#define PMIC_WRAP_PWRAP_ADC_CMD (PMIC_WRAP_BASE+0x154)
+#define PMIC_WRAP_ADC_RDY_ADDR (PMIC_WRAP_BASE+0x158)
+#define PMIC_WRAP_ADC_RDATA_ADDR1 (PMIC_WRAP_BASE+0x15C)
+#define PMIC_WRAP_ADC_RDATA_ADDR2 (PMIC_WRAP_BASE+0x160)
+#define PMIC_WRAP_GPS_STA (PMIC_WRAP_BASE+0x164)
+#define PMIC_WRAP_SWRST (PMIC_WRAP_BASE+0x168)
+
+// Bit Control
+#define GET_STAUPD_DLE_CNT(x) ((x>>0) & 0x00000007)
+#define GET_STAUPD_ALE_CNT(x) ((x>>3) & 0x00000007)
+#define GET_STAUPD_FSM(x) ((x>>6) & 0x00000007)
+#define GET_WRAP_CH_DLE_RESTCNT(x) ((x>>0) & 0x00000007)
+#define GET_WRAP_CH_ALE_RESTCNT(x) ((x>>3) & 0x00000003)
+#define GET_WRAP_AG_DLE_RESTCNT(x) ((x>>5) & 0x00000003)
+#define GET_WRAP_CH_W(x) ((x>>7) & 0x00000001)
+#define GET_WRAP_CH_REQ(x) ((x>>8) & 0x00000001)
+#define GET_AG_WRAP_W(x) ((x>>9) & 0x00000001)
+#define GET_AG_WRAP_REQ(x) ((x>>10) & 0x00000001)
+#define GET_WRAP_FSM(x) ((x>>11) & 0x0000000f)
+#define GET_HARB_WRAP_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_HARB_WRAP_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_HARB_WRAP_REQ(x) ((x>>31) & 0x00000001)
+#define GET_HARB_DLE_EMPTY(x) ((x>>0) & 0x00000001)
+#define GET_HARB_DLE_FULL(x) ((x>>1) & 0x00000001)
+#define GET_HARB_VLD(x) ((x>>2) & 0x00000001)
+#define GET_HARB_DLE_OWN(x) ((x>>3) & 0x00000007)
+#define GET_HARB_OWN(x) ((x>>6) & 0x00000007)
+#define GET_HARB_DLE_RESTCNT(x) ((x>>9) & 0x00000007)
+#define GET_AG_HARB_REQ(x) ((x>>12) & 0x000000ff)
+#define GET_HARB_WRAP_W(x) ((x>>20) & 0x00000001)
+#define GET_HARB_WRAP_REQ0(x) ((x>>21) & 0x00000001)
+#define GET_SPI_WDATA(x) ((x>>0) & 0x000000ff)
+#define GET_SPI_OP(x) ((x>>8) & 0x0000001f)
+#define GET_SPI_W(x) ((x>>13) & 0x00000001)
+#define GET_MAN_RDATA(x) ((x>>0) & 0x000000ff)
+#define GET_MAN_FSM(x) ((x>>8) & 0x00000007)
+#define GET_MAN_REQ(x) ((x>>11) & 0x00000001)
+#define GET_WACS0_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS0_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS0_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS0_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS0_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS0_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE0(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE0(x) ((x>>21) & 0x00000001)
+#define GET_SYS_IDLE0(x) ((x>>22) & 0x00000001)
+#define GET_WACS0_FIFO_FILLCNT(x) ((x>>24) & 0x0000000f)
+#define GET_WACS0_FIFO_FREECNT(x) ((x>>28) & 0x0000000f)
+#define GET_WACS1_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS1_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS1_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS1_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS1_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS1_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE1(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE1(x) ((x>>21) & 0x00000001)
+#define GET_SYS_IDLE1(x) ((x>>22) & 0x00000001)
+#define GET_WACS1_FIFO_FILLCNT(x) ((x>>24) & 0x0000000f)
+#define GET_WACS1_FIFO_FREECNT(x) ((x>>28) & 0x0000000f)
+#define GET_WACS2_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS2_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS2_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS2_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS2_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS2_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE2(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE2(x) ((x>>21) & 0x00000001)
+#define GET_SYS_IDLE2(x) ((x>>22) & 0x00000001)
+#define GET_WACS2_FIFO_FILLCNT(x) ((x>>24) & 0x0000000f)
+#define GET_WACS2_FIFO_FREECNT(x) ((x>>28) & 0x0000000f)
+#define GET_PWRAP_GPS_ACK(x) ((x>>0) & 0x00000001)
+#define GET_GPS_PWRAP_REQ(x) ((x>>1) & 0x00000001)
+#define GET_GPSINF_DLE_CNT(x) ((x>>4) & 0x00000003)
+#define GET_GPSINF_ALE_CNT(x) ((x>>6) & 0x00000003)
+#define GET_GPS_INF_FSM(x) ((x>>8) & 0x00000007)
+#define GET_PWRAP_GPS_WDATA(x) ((x>>15) & 0x0001ffff)
+
+#define GET_WACS_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE(x) ((x>>21) & 0x00000001)
+
+////////////////////////////////////////////////////////////
+// For P2P
+#define PMIC_WRAP_P2P_WACS_P2P_EN (PMIC_WRAP_P2P_BASE+0x200)
+#define PMIC_WRAP_P2P_INIT_DONE_P2P (PMIC_WRAP_P2P_BASE+0x204)
+#define PMIC_WRAP_P2P_WACS_P2P_CMD (PMIC_WRAP_P2P_BASE+0x208)
+#define PMIC_WRAP_P2P_WACS_P2P_RDATA (PMIC_WRAP_P2P_BASE+0x20C)
+#define PMIC_WRAP_P2P_WACS_P2P_VLDCLR (PMIC_WRAP_P2P_BASE+0x210)
+
+#define GET_WACS_P2P_WDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS_P2P_ADR(x) ((x>>16) & 0x00007fff)
+#define GET_WACS_P2P_WRITE(x) ((x>>31) & 0x00000001)
+#define GET_WACS_P2P_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS_P2P_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS_P2P_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE_P2P(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE_P2P(x) ((x>>21) & 0x00000001)
+#define GET_SYS_IDLE_P2P(x) ((x>>22) & 0x00000001)
+#define GET_WACS_P2P_FIFO_FILLCNT(x) ((x>>24) & 0x0000000f)
+#define GET_WACS_P2P_FIFO_FREECNT(x) ((x>>28) & 0x0000000f)
+////////////////////////////////////////////////////////////
+
+#define SPI_AUTO_MODE 0
+#define SPI_MANUAL_MODE 1
+
+#define HARB_HPRIO_ALL 0xFF
+/*
+[7]: WACS_P2P (MD32 SW)
+[6]: GPSINF
+[5]: STAUPD
+[4]: WACS2 (AP SW)
+[3]: WACS1 (MD2 SW)
+[2]: DVFSINF
+[1]: WACS0 (MD1 SW)
+[0]: MDINF
+*/
+#define HARB_HPRIO_WACSP2P (1 << 7)
+#define HARB_HPRIO_GPSINF (1 << 6)
+#define HARB_HPRIO_STAUPD (1 << 5)
+#define HARB_HPRIO_WACS2 (1 << 4)
+#define HARB_HPRIO_WACS1 (1 << 3)
+#define HARB_HPRIO_DVFSINF (1 << 2)
+#define HARB_HPRIO_WACS0 (1 << 1)
+#define HARB_HPRIO_MDINF (1 << 0)
+
+// Current WRAP FSM states.
+#define WRAP_FSM_IDLE_STATE 0x0
+#define WRAP_FSM_CSL_ADR_START_STATE 0x2
+#define WRAP_FSM_ADR_STATE 0x4
+#define WRAP_FSM_CSL_ADR_END_STATE 0x6
+#define WRAP_FSM_CSH_ADR_STATE 0x8
+#define WRAP_FSM_CSL_DATA_START_STATE 0xA
+#define WRAP_FSM_DATA_STATE 0xC
+#define WRAP_FSM_CSL_DATA_END_STATE 0xE
+#define WRAP_FSM_CSH_DATA_STATE 0xF
+
+#define WACS_INIT_DONE_NOT_FINISHED 0
+#define WACS_INIT_DONE_FINISHED 1
+
+#define WACS_SYNC_MODULE_BUSY 0
+#define WACS_SYNC_MODULE_IDLE 1
+
+// Current WACS FSM states.
+#define WACS_FSM_IDLE_STATE 0x0
+#define WACS_FSM_REQ_STATE 0x2
+#define WACS_FSM_WFDLE_STATE 0x4
+#define WACS_FSM_WFVLDCLR_STATE 0x6
+
+// Current MAN FSM states.
+#define MAN_FSM_IDLE_STATE 0x0
+#define MAN_FSM_REQ_STATE 0x2
+#define MAN_FSM_WFDLE_STATE 0x4
+#define MAN_FSM_WFVLDCLR_STATE 0x6
+
+// Current STAUPD FSM states.
+#define STAUPD_FSM_IDLE_STATE 0x0
+#define STAUPD_FSM_REQ_STATE 0x2
+#define STAUPD_FSM_WFDLE_STATE 0x4
+
+#define MT6331_DEW_READ_TEST_VALUE 0x5AA5
+#define MT6332_DEW_READ_TEST_VALUE 0xA55A
+
+//-----macro for manual commnd --------------------------------------------------------
+// From par_spi_man.h
+#define OP_WR (0x1)
+#define OP_RD (0x0)
+
+#define OP_CSH (0x0)
+#define OP_CSL (0x1)
+#define OP_CK (0x2)
+
+#define OP_OUTS (0x8)
+#define OP_OUTD (0x9)
+#define OP_OUTQ (0xA)
+
+#define OP_INS (0xC)
+#define OP_IND (0xD)
+#define OP_INQ (0xE)
+
+#define OP_OS2IS (0x10)
+#define OP_OS2ID (0x11)
+#define OP_OS2IQ (0x12)
+#define OP_OD2IS (0x13)
+#define OP_OD2ID (0x14)
+#define OP_OD2IQ (0x15)
+#define OP_OQ2IS (0x16)
+#define OP_OQ2ID (0x17)
+#define OP_OQ2IQ (0x18)
+
+#define OP_OSNIS (0x19)
+#define OP_ODNID (0x1A)
+
+ #endif // __MT6752_PMIC_WRAP_HW_H__
+
diff --git a/mcu/driver/peripheral/inc/mt6752_pmic_wrap_sw.h b/mcu/driver/peripheral/inc/mt6752_pmic_wrap_sw.h
new file mode 100644
index 0000000..6a98e70
--- /dev/null
+++ b/mcu/driver/peripheral/inc/mt6752_pmic_wrap_sw.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2014
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * mt6752_pmic_wrap_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This is for mt6752 pmic wrapper driver s/w usage
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __MT6752_PMIC_WRAP_SW_H__
+#define __MT6752_PMIC_WRAP_SW_H__
+
+#include "drv_comm.h"
+#define PMIC_WRAP_READ 0
+#define PMIC_WRAP_WRITE 1
+
+#define PMIC_WRAP_REG_CLOCK_SAFE_MODE 0
+
+#define PMIC_WRAP_REG_CLOCK_18MHZ 1
+
+#define MT6325_DEW_WRITE_TEST_VALUE 0xA55A
+#define MT6325_DEW_READ_TEST_VALUE 0x5AA5
+
+#define PMIC_WRAP_INVALID_RW 0x10
+#define PMIC_WRAP_INVALID_ADDR 0x11
+#define PMIC_WRAP_INVALID_WDATA 0x12
+#define PMIC_WRAP_INVALID_OP 0x13
+#define PMIC_WRAP_INVALID_ARGUMENT 0x14
+#define PMIC_WRAP_NOT_SUPPORT_MANUAL_ACCESS_TO_PMIC_2 0x15
+
+#define PMIC_WRAP_INIT_SIDLY_FAIL 0x20
+#define PMIC_WRAP_INIT_REG_CLK_FAIL 0x21
+#define PMIC_WRAP_INIT_DUAL_MODE_FAIL 0x22
+#define PMIC_WRAP_INIT_CIPHER_FAIL 0x23
+
+#define PMIC_WRAP_NOT_INIT_DONE 0x30
+#define PMIC_WRAP_NOT_INIT_DONE_READ 0x31
+#define PMIC_WRAP_READ_TEST_FAIL 0x32
+#define PMIC_WRAP_WRITE_TEST_FAIL 0x33
+#define PMIC_WRAP_SWITCH_DIO_FAIL 0x34
+#define PMIC_WRAP_READ_FAIL 0x35
+#define PMIC_WRAP_WRITE_FAIL 0x36
+#define PMIC_WRAP_DEW_EVENT_TEST_FAIL 0x37
+#define PMIC_WRAP_MANUAL_MODE_NOT_IDLE 0x38
+#define PMIC_WRAP_STAUPD_FSM_NOT_IDLE 0x39
+
+
+#define PMIC_WRAP_TIME_OUT_FAIL 0xFF
+
+#define OP_RD (0x0)
+#define OP_WR (0x1)
+
+#define OP_CSH (0x0)
+#define OP_CSL (0x1)
+#define OP_CK (0x2)
+#define OP_OUTS (0x8)
+#define OP_OUTD (0x9)
+#define OP_INS (0xC)
+#define OP_IND (0xD)
+
+#define DRV_WriteReg(addr,data) ((*(volatile kal_uint16 *)(addr)) = (kal_uint16)(data))
+#define DRV_Reg(addr) (*(volatile kal_uint16 *)(addr))
+#define DRV_WriteReg32(addr,data) ((*(volatile kal_uint32 *)(addr)) = (kal_uint32)(data))
+#define DRV_Reg32(addr) (*(volatile kal_uint32 *)(addr))
+#define DRV_WriteReg8(addr,data) ((*(volatile kal_uint8 *)(addr)) = (kal_uint8)(data))
+#define DRV_Reg8(addr) (*(volatile kal_uint8 *)(addr))
+
+#define DRV_ClearBits32(addr,data) {\
+ kal_uint32 temp;\
+ temp = DRV_Reg32(addr);\
+ temp &=~(data);\
+ DRV_WriteReg32(addr,temp);\
+}
+
+#define DRV_SetBits32(addr,data) {\
+ kal_uint32 temp;\
+ temp = DRV_Reg32(addr);\
+ temp |= (data);\
+ DRV_WriteReg32(addr,temp);\
+}
+
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_PMIC_WRAP_REG_DBG__)
+#define PMIC_WRAP_DRV_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
+#define PMIC_WRAP_DRV_SetBits16(addr) DRV_DBG_SetBits(addr)
+#define PMIC_WRAP_DRV_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
+#define PMIC_WRAP_DRV_ReadReg16(addr) DRV_DBG_Reg(addr)
+#define PMIC_WRAP_DRV_ClearBits32(addr, data) DRV_DBG_ClearBits32(addr, data)
+#define PMIC_WRAP_DRV_SetBits32(addr, data) DRV_DBG_SetBits32(addr, data)
+#define PMIC_WRAP_DRV_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define PMIC_WRAP_DRV_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define PMIC_WRAP_DRV_Reg32(addr) DRV_DBG_Reg32(addr)
+#else // #if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RTC_REG_DBG__)
+#define PMIC_WRAP_DRV_ClearBits16(addr, data) DRV_ClearBits(addr,data)
+#define PMIC_WRAP_DRV_SetBits16(addr, data) DRV_SetBits(addr,data)
+#define PMIC_WRAP_DRV_WriteReg16(addr, data) DRV_WriteReg(addr, data)
+#define PMIC_WRAP_DRV_ReadReg16(addr) DRV_Reg(addr)
+#define PMIC_WRAP_DRV_ClearBits32(addr, data) DRV_ClearBits32(addr, data)
+#define PMIC_WRAP_DRV_SetBits32(addr, data) DRV_SetBits32(addr, data)
+#define PMIC_WRAP_DRV_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define PMIC_WRAP_DRV_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define PMIC_WRAP_DRV_Reg32(addr) DRV_Reg32(addr)
+#endif // #if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RTC_REG_DBG__)
+
+kal_uint32 DrvPWRAP_Init(void);
+kal_uint32 DrvPWRAP_WACS2_NoChk(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+//kal_uint32 DrvPWRAP_WACS0(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_WACS0(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint16 *rdata);
+//kal_uint32 DrvPWRAP_WACS1(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_WACS1(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint16 *rdata);
+kal_uint32 DrvPWRAP_WACS2(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_Man(kal_uint32 write, kal_uint32 op, kal_uint32 wdata, kal_uint32 *rdata );
+kal_uint32 DrvPWRAP_ManAccess(kal_uint32 write, kal_uint32 adr, kal_uint32 wdata, kal_uint32 *rdata);
+kal_uint32 DrvPWRAP_InitDio(kal_uint32 dio_en);
+kal_uint32 DrvPWRAP_SwitchDio(kal_uint32 dio_en);
+kal_uint32 DrvPWRAP_InitCIPHER(void);
+kal_uint32 DrvPWRAP_EnableCIPHER(void);
+kal_uint32 DrvPWRAP_DisableCIPHER(void);
+void DrvPWRAP_ResetSPISLV(void);
+void DrvPWRAP_SwitchMux(kal_uint8 mux_sel_new);
+kal_uint32 DrvPWRAP_InitSiStrobe(void);
+kal_uint32 DrvPWRAP_StaUpdTrig(kal_uint32 mode);
+void DrvPWRAP_AlignCRC(void);
+kal_uint32 DrvPWRAP_InitRegClk(kal_uint32 regck_sel);
+kal_uint32 DrvPWRAP_Read_Test(kal_bool NoChk);
+typedef kal_uint32 (*loop_condition_fp)(kal_uint32); // Define a function pointer
+
+#endif // __MT6752_PMIC_WRAP_SW_H__
diff --git a/mcu/driver/peripheral/inc/nli_arb.h b/mcu/driver/peripheral/inc/nli_arb.h
new file mode 100644
index 0000000..6af78ed
--- /dev/null
+++ b/mcu/driver/peripheral/inc/nli_arb.h
@@ -0,0 +1,184 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001-2007
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * nli_arb.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * This file is to define NLI Arbiter reigter and operation macro for MT6276, MT6256 and etc..
+ *
+ * Author:
+ * -------
+ *
+ * Bin Han (mtk80391)
+ *
+ *------------------------------------------------------------------------------
+ * $Log$
+ *
+ * 07 19 2011 bin.han
+ * removed!
+ * .
+ *
+ *
+ *******************************************************************************/
+#ifndef __NLI_ARB_H__
+#define __NLI_ARB_H__
+
+#include "reg_base.h"
+
+
+////////////////////////// Reigster Operation Macro Define ////////////////////////////
+#ifdef NLI_ARB_base
+
+#define REG_NLI_ARB_STATUS *((volatile unsigned int *)(NLI_ARB_base+0x000))
+#define REG_NLI_ARB_SWRST *((volatile unsigned int *)(NLI_ARB_base+0x010))
+#define REG_NLI_ARB_CS *((volatile unsigned int *)(NLI_ARB_base+0x014))
+#define REG_NLI_ARB_CONT_GRANT *((volatile unsigned int *)(NLI_ARB_base+0x018))
+#define REG_NLI_ARB_HANDOVER *((volatile unsigned int *)(NLI_ARB_base+0x01C))
+#define REG_NLI_ARB_MON_SRC *((volatile unsigned int *)(NLI_ARB_base+0x040))
+#define REG_NLI_ARB_MON_CLR *((volatile unsigned int *)(NLI_ARB_base+0x044))
+#define REG_NLI_ARB_MON_START *((volatile unsigned int *)(NLI_ARB_base+0x048))
+#define REG_NLI_ARB_MON_RD *((volatile unsigned int *)(NLI_ARB_base+0x050))
+#define REG_NLI_ARB_MON_WR *((volatile unsigned int *)(NLI_ARB_base+0x054))
+#define REG_NLI_ARB_MON_CYC *((volatile unsigned int *)(NLI_ARB_base+0x058))
+
+
+#define NLI_ARB_CS_FAVOR_NORMAL_BIT (0x10000)
+#define NLI_ARB_CS_FAVOR_ULTRA_BIT (0x20000)
+#define ENABLE_NLI_ARB_FAVOR_NORMAL() REG_NLI_ARB_CS |= NLI_ARB_CS_FAVOR_NORMAL_BIT;
+#define DISABLE_NLI_ARB_FAVOR_NORMAL() REG_NLI_ARB_CS &= (~NLI_ARB_CS_FAVOR_NORMAL_BIT);
+#define ENABLE_NLI_ARB_FAVOR_ULTRA() REG_NLI_ARB_CS |= NLI_ARB_CS_FAVOR_ULTRA_BIT;
+#define DISABLE_NLI_ARB_FAVOR_ULTRA() REG_NLI_ARB_CS &= (~NLI_ARB_CS_FAVOR_ULTRA_BIT);
+#define GET_NLI_ARB_FAVOR_NORMAL_ENABLE() (REG_NLI_ARB_CS & NLI_ARB_CS_FAVOR_NORMAL_BIT)
+#define GET_NLI_ARB_FAVOR_ULTRA_ENABLE() (REG_NLI_ARB_CS & NLI_ARB_CS_FAVOR_ULTRA_BIT)
+
+
+#define SET_NLI_ARB_CS_SOURCE_SELECTION(src,dest) do{REG_NLI_ARB_CS &= ~(0x7<<(dest)); REG_NLI_ARB_CS |= ((src)<<(dest));} while(0)
+#define GET_NLI_ARB_CS_SOURCE_SELECTION(dest) ((REG_NLI_ARB_CS >> (dest)) & 0x7)
+#else
+
+// Dummy MACRO to avoid build error
+#define ENABLE_NLI_ARB_FAVOR_NORMAL()
+#define DISABLE_NLI_ARB_FAVOR_NORMAL()
+#define ENABLE_NLI_ARB_FAVOR_ULTRA()
+#define DISABLE_NLI_ARB_FAVOR_ULTRA()
+
+#define SET_NLI_ARB_CS_SOURCE_SELECTION_LPCE0B(x)
+#define SET_NLI_ARB_CS_SOURCE_SELECTION_LPCE1B(x)
+#define SET_NLI_ARB_CS_SOURCE_SELECTION_LPCE2B(x)
+#define SET_NLI_ARB_CS_SOURCE_SELECTION_LPCE3B(x)
+
+#endif //NLI_ARB_base
+
+
+////////////////////////// User Interface ////////////////////////////
+typedef enum
+{
+ NLI_ARB_USER_LCD = 0,
+ NLI_ARB_USER_NAND,
+ NLI_ARB_USER_HIF0,
+ NLI_ARB_USER_HIF1,
+
+ NLI_ARB_USER_NUM
+}NLI_ARB_USER_ENUM;
+
+///Notice: the following enum define is chip depedent
+typedef enum
+{
+ NLI_ARB_CS_SOURCE_LCD0 = 0,
+ NLI_ARB_CS_SOURCE_LCD1 = 1,
+ NLI_ARB_CS_SOURCE_LCD2 = 2,
+ NLI_ARB_CS_SOURCE_HIF0 = 3,
+ NLI_ARB_CS_SOURCE_HIF1 = 4,
+
+ NLI_ARB_CS_SOURCE_NUMBER
+}NLI_ARB_CS_SOURCE_ENUM;
+
+
+///Notice: the following enum define is chip depedent
+typedef enum
+{
+ NLI_ARB_CS_DEST_LPCE0B = 0,
+ NLI_ARB_CS_DEST_LPCE1B = 1,
+ NLI_ARB_CS_DEST_LPCE2B = 2,
+ NLI_ARB_CS_DEST_LPCE3B = 3,
+
+ NLI_ARB_CS_DEST_NUMBER
+}NLI_ARB_CS_DEST_ENUM;
+
+
+typedef enum
+{
+ // Set operation
+ NLI_ARB_SET_FAVOR_NORMAL = 0,
+ NLI_ARB_SET_FAVOR_ULTRA,
+ NLI_ARB_SET_CS_MAPPING,
+
+ // Query operation
+ NLI_ARB_QUERY_FAVOR_NORMAL,
+ NLI_ARB_QUERY_FAVOR_ULTRA,
+ NLI_ARB_QUERY_CS_MAPPING,
+
+ NLI_ARB_CONTROL_CODE_NUM
+}NLI_ARB_CONTROL_CODE_ENUM;
+
+
+typedef struct
+{
+ kal_bool enable;
+}NLI_ARB_SET_QUERY_FAVOR_STRUCT;
+
+
+typedef struct
+{
+ NLI_ARB_CS_SOURCE_ENUM cs_source; /// LCD0, LCD1, LCD2, HIF0, HIF1
+ NLI_ARB_CS_DEST_ENUM cs_dest; /// LPCE0B,LPCE1B, LPCE2B, LPCE3B
+}NLI_ARB_SET_QUERY_CS_MAPPING_STRUCT;
+
+
+//The drv init function
+void NLI_ARB_init(void);
+//The drv IO control function , return KAL_FALSE means set or query is fail
+kal_bool NLI_ARB_IOCtrl(NLI_ARB_USER_ENUM user, NLI_ARB_CONTROL_CODE_ENUM ctrlCode, void *ctrlStruct);
+
+#endif // __NLI_ARB_H__
diff --git a/mcu/driver/peripheral/inc/pfc_hw.h b/mcu/driver/peripheral/inc/pfc_hw.h
new file mode 100644
index 0000000..baf47f6
--- /dev/null
+++ b/mcu/driver/peripheral/inc/pfc_hw.h
@@ -0,0 +1 @@
+/* This file should be deleted */
\ No newline at end of file
diff --git a/mcu/driver/peripheral/inc/pfc_sw.h b/mcu/driver/peripheral/inc/pfc_sw.h
new file mode 100644
index 0000000..baf47f6
--- /dev/null
+++ b/mcu/driver/peripheral/inc/pfc_sw.h
@@ -0,0 +1 @@
+/* This file should be deleted */
\ No newline at end of file
diff --git a/mcu/driver/peripheral/inc/pmic_wrap.h b/mcu/driver/peripheral/inc/pmic_wrap.h
new file mode 100644
index 0000000..21b6c6c
--- /dev/null
+++ b/mcu/driver/peripheral/inc/pmic_wrap.h
@@ -0,0 +1,127 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * pmic_wrap.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is used to configure correspond header files of pmic wrapper.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "drv_features.h"
+
+#if defined(MT6325)
+#define DRV_PMIC_WRAP_V2
+#define DRV_PMIC_WRAP_6752_REG
+#endif
+#if defined(DRV_PMIC_WRAP_6752_REG)
+
+#include "mt6752_pmic_wrap_hw.h"
+#include "mt6752_pmic_wrap_sw.h"
+
+#elif defined(DRV_PMIC_WRAP_6595_REG)
+
+#include "mt6595_pmic_wrap_hw.h"
+#include "mt6595_pmic_wrap_sw.h"
+
+#elif defined(DRV_PMIC_WRAP_6589_REG)
+
+#include "mt6589_pmic_wrap_hw.h"
+#include "mt6589_pmic_wrap_sw.h"
+#include "reg_peri_pwrap_bridge.h"
+
+#elif defined(DRV_PMIC_WRAP_6582_REG)
+
+#include "mt6582_pmic_wrap_hw.h"
+#include "mt6582_pmic_wrap_sw.h"
+
+#elif defined(DRV_PMIC_WRAP_6572_REG)
+
+#include "mt6572_pmic_wrap_hw.h"
+#include "mt6572_pmic_wrap_sw.h"
+
+#elif defined(DRV_PMIC_WRAP_6571_REG)
+
+#include "mt6571_pmic_wrap_hw.h"
+#include "mt6571_pmic_wrap_sw.h"
+
+#endif
diff --git a/mcu/driver/peripheral/inc/pwm_hw.h b/mcu/driver/peripheral/inc/pwm_hw.h
new file mode 100644
index 0000000..4c04210
--- /dev/null
+++ b/mcu/driver/peripheral/inc/pwm_hw.h
@@ -0,0 +1,228 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * pwm_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for PWM driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef PWM_HW_H
+#define PWM_HW_H
+#include "drv_features_pwm.h"
+#include "reg_base.h"
+#ifndef DRV_PWM_OFF
+#if !defined(DRV_PWM_RWG)
+#define PWM1_CTRL (PWM_base+0x0000) /* PWM Control */
+#define PWM1_COUNT (PWM_base+0x0004) /* PWM max counter value */
+#define PWM1_THRESHOLD (PWM_base+0x0008) /* PWM threshold value */
+#if 0
+/* under construction !*/
+#endif
+#define PWM1_PWR_OFF 0x0020
+#if defined(DRV_PWM_PWM2)
+ #define PWM2_CTRL (PWM_base+0x000C) /* PWM Control */
+ #define PWM2_COUNT (PWM_base+0x0010) /* PWM max counter value */
+ #define PWM2_THRESHOLD (PWM_base+0x0014) /* PWM threshold value */
+#if 0
+/* under construction !*/
+#endif
+ #define PWM2_PWR_OFF 0x0400
+#if defined(DRV_PWM_PWM3)
+ #define PWM3_CTRL (PWM_base+0x0018) /* PWM Control */
+ #define PWM3_COUNT (PWM_base+0x001C) /* PWM max counter value */
+ #define PWM3_THRESHOLD (PWM_base+0x0020) /* PWM threshold value */
+#if defined(DRV_PWM_PWM4)
+ #define PWM4_CTRL (PWM_base+0x0024) /* PWM Control */
+ #define PWM4_COUNT (PWM_base+0x0028) /* PWM max counter value */
+ #define PWM4_THRESHOLD (PWM_base+0x002C) /* PWM threshold value */
+#endif /*DRV_PWM_PWM4*/
+
+#endif /*DRV_PWM_PWM3*/
+#endif /*DRV_PWM_PWM2*/
+#endif // DRV_PWM_OFF
+
+#define PWM_CTRL_EN 0x8000
+#define PWM_CTRL_CLK_1 0x0000
+#define PWM_CTRL_CLK_2 0x0001
+#define PWM_CTRL_CLK_4 0x0002
+#define PWM_CTRL_CLK_8 0x0003
+
+#if defined(DRV_PWM_CLK_SEL)
+ #define PWM_CTRL_CLKSEL 0x0004
+#endif /*DRV_PWM_CLK_SEL*/
+
+/*==================Macro====================*/
+#define PWM_SetCountValue(count) *(volatile kal_uint16 *)PWM1_COUNT = count
+#define PWM_SetThres(thres) *(volatile kal_uint16 *)PWM1_THRESHOLD = thres
+#if defined(DRV_PWM_PWM2)
+ #define PWM2_SetCountValue(count) *(volatile kal_uint16 *)PWM2_COUNT = count
+ #define PWM2_SetThres(thres) *(volatile kal_uint16 *)PWM2_THRESHOLD = thres
+#if defined(DRV_PWM_PWM3)
+ #define PWM3_SetCountValue(count) *(volatile kal_uint16 *)PWM3_COUNT = count
+ #define PWM3_SetThres(thres) *(volatile kal_uint16 *)PWM3_THRESHOLD = thres
+#if defined(DRV_PWM_PWM4)
+ #define PWM4_SetCountValue(count) *(volatile kal_uint16 *)PWM4_COUNT = count
+ #define PWM4_SetThres(thres) *(volatile kal_uint16 *)PWM4_THRESHOLD = thres
+#endif /*DRV_PWM_PWM4*/
+#endif /*DRV_PWM_PWM3*/
+#endif /*DRV_PWM_PWM2*/
+
+#endif /* !defined(DRV_PWM_RWG) */
+
+
+#endif
+
diff --git a/mcu/driver/peripheral/inc/pwm_sw.h b/mcu/driver/peripheral/inc/pwm_sw.h
new file mode 100644
index 0000000..7c2024c
--- /dev/null
+++ b/mcu/driver/peripheral/inc/pwm_sw.h
@@ -0,0 +1,353 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * pwm_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for PWM driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
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+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef PWM_SW_H
+#define PWM_SW_H
+
+#include "drv_features_pwm.h"
+#include "rwg_sw.h"
+#include "kal_general_types.h"
+#include "dcl.h"
+#include "drv_comm.h"
+
+#if !defined(DRV_PWM_RWG)
+
+//this should move to pwm_sw.h
+#if defined(DRV_PWM_PWM2)
+#if defined(DRV_PWM_PWM3)
+#if defined(DRV_PWM_PWM4)
+#define PWM_COUNT 4
+#else //defined(DRV_PWM_PWM4)
+#define PWM_COUNT 3
+#endif//defined(DRV_PWM_PWM4)
+#else //defined(DRV_PWM_PWM3)
+#define PWM_COUNT 2
+#endif //defined(DRV_PWM_PWM3)
+#else //defined(DRV_PWM_PWM2)
+#define PWM_COUNT 1
+#endif//defined(DRV_PWM_PWM2)
+
+typedef enum
+{
+ pwmclk_1MHZ=0,
+ pwmclk_2MHZ,
+ pwmclk_4MHZ,
+ pwmclk_8MHZ
+}PWMClock_DIV;
+
+typedef enum
+{
+ pwmclk_13M=0,
+ pwmclk_32k
+}PWMClock_SEL;
+
+typedef enum
+{
+ PWM1=0,
+ PWM2,
+ PWM3,
+ PWM4
+}PWM_TYPE;
+
+typedef void (*DCL_PWM_INIT)(void);
+typedef void (*DCL_PWM_CLK_INIT)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 clk_sel, kal_uint32 clk_div);
+typedef void (*DCL_PWM_START)(DCL_UINT8 owner, DCL_UINT32 pwm_num);
+typedef void (*DCL_PWM_STOP)(DCL_UINT8 owner, DCL_UINT32 pwm_num);
+typedef void (*DCL_PWM_CONFIG_OLD)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 freq, kal_uint8 duty);
+typedef DCL_UINT8 (*DCL_PWM_GETCURRENT_LEVEL)(DCL_UINT8 pwm_num);
+typedef DCL_UINT32(*DCL_PWM_GETCURRENT_FREQ)(DCL_UINT8 pwm_num);
+typedef DCL_UINT8 (*DCL_PWM_GETCURRENT_DUTY)(DCL_UINT8 pwm_num);
+
+typedef struct
+{
+ DCL_PWM_INIT pwmInit;
+ DCL_PWM_CLK_INIT pwmClkInit;
+ DCL_PWM_START pwmStart;
+ DCL_PWM_STOP pwmStop;
+ DCL_PWM_GETCURRENT_LEVEL pwmGetCurrent_level;
+ DCL_PWM_GETCURRENT_FREQ pwmGetCurrent_Freq;
+ DCL_PWM_GETCURRENT_DUTY pwmGetCurrent_Duty;
+ DCL_PWM_CONFIG_OLD pwmConfigOld;
+}PWMDriver_t;
+
+extern void DCL_PWM_Init(void);
+extern void DCL_PWM_SetClock(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 clk_sel, kal_uint32 clk_div);
+extern void DCL_PWM_Start(kal_uint8 owner, kal_uint32 pwm_num);
+extern void DCL_PWM_Stop(kal_uint8 owner, kal_uint32 pwm_num);
+extern void DCL_PWM_ConfigOld(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 freq, kal_uint8 duty);
+extern kal_uint8 DCL_PWM_GetCurrent_Level(kal_uint8 pwm_num);
+extern kal_uint8 DCL_PWM_GetCurrentDuty(kal_uint8 pwm_num);
+extern kal_uint32 DCL_PWM_GetCurrentFreq(kal_uint8 pwm_num);
+
+
+extern void PWM_Init(PWMClock_SEL clk_sel,PWMClock_DIV Clock_div);
+extern void PWM1_Configure(kal_uint32 freq, kal_uint8 duty);
+extern void PWM1_Start(void);
+extern void PWM1_Stop(void);
+extern kal_uint8 PWM1_GetCurrentLevel(void);
+extern kal_uint8 PMW1_GetCurrentDuty(void);
+extern kal_uint32 PMW1_GetCurrentFreq(void);
+#if defined(DRV_PWM_PWM2)
+ extern void PWM2_Init(PWMClock_SEL clk_sel,PWMClock_DIV Clock_div);
+ extern void PWM2_Configure(kal_uint32 freq, kal_uint8 duty);
+ extern void PWM2_Start(void);
+ extern void PWM2_Stop(void);
+ extern kal_uint8 PWM2_GetCurrentLevel(void);
+ extern kal_uint8 PMW2_GetCurrentDuty(void);
+ extern kal_uint32 PMW2_GetCurrentFreq(void);
+#if defined(DRV_PWM_PWM3)
+ extern void PWM3_Init(PWMClock_SEL clk_sel,PWMClock_DIV Clock_div);
+ extern void PWM3_Configure(kal_uint32 freq, kal_uint8 duty);
+ extern void PWM3_Start(void);
+ extern void PWM3_Stop(void);
+ extern kal_uint8 PWM3_GetCurrentLevel(void);
+ extern kal_uint8 PMW3_GetCurrentDuty(void);
+ extern kal_uint32 PMW3_GetCurrentFreq(void);
+#if defined(__DRV_PMU53_SPEC_V2__)
+extern void PWM3_Output_High(void);
+#endif //#if defined(__DRV_PMU53_SPEC_V2__)
+#if defined(DRV_PWM_PWM4)
+ extern void PWM4_Init(PWMClock_SEL clk_sel,PWMClock_DIV Clock_div);
+ extern void PWM4_Configure(kal_uint32 freq, kal_uint8 duty);
+ extern void PWM4_Start(void);
+ extern void PWM4_Stop(void);
+ extern kal_uint8 PWM4_GetCurrentLevel(void);
+ extern kal_uint8 PMW4_GetCurrentDuty(void);
+ extern kal_uint32 PMW4_GetCurrentFreq(void);
+#endif /* DRV_PWM_PWM4 */
+
+#endif /* DRV_PWM_PWM3 */
+#endif /* DRV_PWM_PWM2 */
+
+#endif /* !defined(DRV_PWM_RWG) */
+
+
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_PWM_REG_DBG__)
+#define DRV_PWM_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+#define DRV_PWM_Reg(addr) DRV_DBG_Reg(addr)
+#define DRV_PWM_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define DRV_PWM_Reg32(addr) DRV_DBG_Reg32(addr)
+#define DRV_PWM_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+#define DRV_PWM_Reg8(addr) DRV_DBG_Reg8(addr)
+#define DRV_PWM_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+#define DRV_PWM_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+#define DRV_PWM_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#define DRV_PWM_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+#define DRV_PWM_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+#define DRV_PWM_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+#define DRV_PWM_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+#define DRV_PWM_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+#define DRV_PWM_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+#else
+#define DRV_PWM_WriteReg(addr,data) DRV_WriteReg(addr,data)
+#define DRV_PWM_Reg(addr) DRV_Reg(addr)
+#define DRV_PWM_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define DRV_PWM_Reg32(addr) DRV_Reg32(addr)
+#define DRV_PWM_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+#define DRV_PWM_Reg8(addr) DRV_Reg8(addr)
+#define DRV_PWM_ClearBits(addr,data) DRV_ClearBits(addr,data)
+#define DRV_PWM_SetBits(addr,data) DRV_SetBits(addr,data)
+#define DRV_PWM_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define DRV_PWM_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+#define DRV_PWM_SetBits32(addr,data) DRV_SetBits32(addr,data)
+#define DRV_PWM_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+#define DRV_PWM_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+#define DRV_PWM_SetBits8(addr,data) DRV_SetBits8(addr,data)
+#define DRV_PWM_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_PWM_REG_DBG__)
+#endif
+
diff --git a/mcu/driver/peripheral/inc/readme.txt b/mcu/driver/peripheral/inc/readme.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/driver/peripheral/inc/readme.txt
diff --git a/mcu/driver/peripheral/inc/reg_peri_pwrap_bridge.h b/mcu/driver/peripheral/inc/reg_peri_pwrap_bridge.h
new file mode 100644
index 0000000..9263050
--- /dev/null
+++ b/mcu/driver/peripheral/inc/reg_peri_pwrap_bridge.h
@@ -0,0 +1,46 @@
+#ifndef __PERI_PWRAP_BRIDGE_REGS_H__
+#define __PERI_PWRAP_BRIDGE_REGS_H__
+
+#include "reg_base.h"
+
+#define PERI_PWRAP_BRIDGE_BASE (AP_PERI_PWRAP_BRIDGE_base)
+
+#define PERI_PWRAP_BRIDGE_IARB_INIT (PERI_PWRAP_BRIDGE_BASE+0x0)
+#define PERI_PWRAP_BRIDGE_IORD_ARB_EN (PERI_PWRAP_BRIDGE_BASE+0x4)
+#define PERI_PWRAP_BRIDGE_IARB_STA0 (PERI_PWRAP_BRIDGE_BASE+0x8)
+#define PERI_PWRAP_BRIDGE_IARB_STA1 (PERI_PWRAP_BRIDGE_BASE+0xC)
+#define PERI_PWRAP_BRIDGE_WACS3_EN (PERI_PWRAP_BRIDGE_BASE+0x10)
+#define PERI_PWRAP_BRIDGE_INIT_DONE3 (PERI_PWRAP_BRIDGE_BASE+0x14)
+#define PERI_PWRAP_BRIDGE_WACS3_CMD (PERI_PWRAP_BRIDGE_BASE+0x18)
+#define PERI_PWRAP_BRIDGE_WACS3_RDATA (PERI_PWRAP_BRIDGE_BASE+0x1C)
+#define PERI_PWRAP_BRIDGE_WACS3_VLDCLR (PERI_PWRAP_BRIDGE_BASE+0x20)
+#define PERI_PWRAP_BRIDGE_WACS4_EN (PERI_PWRAP_BRIDGE_BASE+0x24)
+#define PERI_PWRAP_BRIDGE_INIT_DONE4 (PERI_PWRAP_BRIDGE_BASE+0x28)
+#define PERI_PWRAP_BRIDGE_WACS4_CMD (PERI_PWRAP_BRIDGE_BASE+0x2C)
+#define PERI_PWRAP_BRIDGE_WACS4_RDATA (PERI_PWRAP_BRIDGE_BASE+0x30)
+#define PERI_PWRAP_BRIDGE_WACS4_VLDCLR (PERI_PWRAP_BRIDGE_BASE+0x34)
+#define PERI_PWRAP_BRIDGE_INT_EN (PERI_PWRAP_BRIDGE_BASE+0x38)
+#define PERI_PWRAP_BRIDGE_INT_FLG_RAW (PERI_PWRAP_BRIDGE_BASE+0x3C)
+#define PERI_PWRAP_BRIDGE_INT_FLG (PERI_PWRAP_BRIDGE_BASE+0x40)
+#define PERI_PWRAP_BRIDGE_INT_CLR (PERI_PWRAP_BRIDGE_BASE+0x44)
+#define PERI_PWRAP_BRIDGE_TIMER_EN (PERI_PWRAP_BRIDGE_BASE+0x48)
+#define PERI_PWRAP_BRIDGE_TIMER_STA (PERI_PWRAP_BRIDGE_BASE+0x4C)
+#define PERI_PWRAP_BRIDGE_WDT_UNIT (PERI_PWRAP_BRIDGE_BASE+0x50)
+#define PERI_PWRAP_BRIDGE_WDT_SRC_EN (PERI_PWRAP_BRIDGE_BASE+0x54)
+#define PERI_PWRAP_BRIDGE_WDT_FLG (PERI_PWRAP_BRIDGE_BASE+0x58)
+#define PERI_PWRAP_BRIDGE_DEBUG_INT_SEL (PERI_PWRAP_BRIDGE_BASE+0x5C)
+
+
+#define GET_WACS3_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS3_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS3_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE3(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE3(x) ((x>>21) & 0x00000001)
+#define GET_WACS4_RDATA(x) ((x>>0) & 0x0000ffff)
+#define GET_WACS4_FSM(x) ((x>>16) & 0x00000007)
+#define GET_WACS4_REQ(x) ((x>>19) & 0x00000001)
+#define GET_SYNC_IDLE4(x) ((x>>20) & 0x00000001)
+#define GET_INIT_DONE4(x) ((x>>21) & 0x00000001)
+
+#endif //__PERI_PWRAP_BRIDGE_REGS_H__
+
diff --git a/mcu/driver/peripheral/inc/rtc_hw.h b/mcu/driver/peripheral/inc/rtc_hw.h
new file mode 100644
index 0000000..37aeb82
--- /dev/null
+++ b/mcu/driver/peripheral/inc/rtc_hw.h
@@ -0,0 +1,349 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * rtc_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for RTC driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _RTC_HW_H
+#define _RTC_HW_H
+#include "reg_base.h"
+
+#if !defined(DRV_RTC_OFF)
+/*****************
+ * RTC Registers *
+ *****************/
+#define RTC_BBPU (RTC_base+0x0000) /*Baseband Power-up ctrl */
+#define RTC_IRQ_STATUS (RTC_base+0x0004) /*IRQ Status */
+#define RTC_IRQ_EN (RTC_base+0x0008) /*IRQ Enable */
+#define RTC_CII_EN (RTC_base+0x000C) /*Counter increment IRQ */
+#define RTC_AL_MASK (RTC_base+0x0010)/*Alarm mask control */
+#define RTC_TC_SEC (RTC_base+0x0014)/*Second time counter */
+#define RTC_TC_MIN (RTC_base+0x0018)/*Minute time counter */
+#define RTC_TC_HOU (RTC_base+0x001C)/*Hour time counter */
+#define RTC_TC_DOM (RTC_base+0x0020)/*Day of Mth time counter */
+#define RTC_TC_DOW (RTC_base+0x0024)/*Day of Wk time counter */
+#define RTC_TC_MTH (RTC_base+0x0028)/*Month time counter */
+#define RTC_TC_YEA (RTC_base+0x002C)/*Year time counter */
+#define RTC_AL_SEC (RTC_base+0x0030)/*Second alarm */
+#define RTC_AL_MIN (RTC_base+0x0034)/*Minute alarm */
+#define RTC_AL_HOU (RTC_base+0x0038)/*Hour alarm */
+#define RTC_AL_DOM (RTC_base+0x003C)/*Day of Month alarm */
+#define RTC_AL_DOW (RTC_base+0x0040)/*Day of Week alarm */
+#define RTC_AL_MTH (RTC_base+0x0044)/*Month alarm */
+#define RTC_AL_YEA (RTC_base+0x0048)/*Year alarm */
+#define RTC_XOSCCAL (RTC_base+0x004C)
+#define RTC_POWERKEY1 (RTC_base+0x0050)
+#define RTC_POWERKEY2 (RTC_base+0x0054)
+#if defined(DRV_RTC_REG_COMM)
+ #define RTC_INFO1 (RTC_base+0x0058)
+ #define RTC_INFO2 (RTC_base+0x005c)
+#if defined(DRV_RTC_W_FLAG)
+ #define RTC_W_FLAG (RTC_base+0x0060)
+#endif
+#endif /*DRV_RTC_REG_COMM*/
+
+#if defined(DRV_RTC_HW_CALI)
+#define RTC_SPAR0 (RTC_base+0x0060)
+#define RTC_SPAR1 (RTC_base+0x0064)
+#define RTC_PROT (RTC_base+0x0068)
+#define RTC_DIFF (RTC_base+0x006C)
+#define RTC_CALI (RTC_base+0x0070)
+#define RTC_WRTGR (RTC_base+0x0074)
+#endif /* DRV_RTC_HW_CALI */
+
+#if defined(DRV_RTC_GPIO)
+#define RTC_GPIO (RTC_base+0x0078)
+#endif /* DRV_RTC_GPIO */
+
+//RTC_IRQ_STATUS
+#define RTC_IRQ_STATUS_AL_STAT 0x0001
+#define RTC_IRQ_STATUS_TC_STAT 0x0002
+#if defined(DRV_RTC_LOW_POWER_DETECT)
+#define RTC_IRQ_STATUS_LP_STAT 0x0008
+#endif /* DRV_RTC_GPIO */
+
+//RTC_IRQ_EN
+#define RTC_IRQ_EN_AL 0x0001
+#define RTC_IRQ_EN_TC 0x0002
+#define RTC_IRQ_EN_ONESHOT 0x0004
+
+#define RTC_IRQ_EN_ALLOFF 0x0000
+
+//RTC_CII_EN
+#define RTC_CII_EN_SEC 0x0001
+#define RTC_CII_EN_MIN 0x0002
+#define RTC_CII_EN_HOU 0x0004
+#define RTC_CII_EN_DOM 0x0008
+#define RTC_CII_EN_DOW 0x0010
+#define RTC_CII_EN_MTH 0x0020
+#define RTC_CII_EN_YEA 0x0040
+#define RTC_CII_EN_ALLOFF 0x0000
+#if defined(DRV_RTC_CII_HALF_SEC)
+ #define RTC_CII_EN_1_2S 0x0080
+ #define RTC_CII_EN_1_4S 0x0100
+ #define RTC_CII_EN_1_8S 0x0200
+#endif /*DRV_RTC_CII_HALF_SEC*/
+
+//RTC_AL_MASK, mask ==> 1 close intr, 0 open intr.
+#define RTC_AL_MASK_SEC 0x0001
+#define RTC_AL_MASK_MIN 0x0003
+#define RTC_AL_MASK_HOU 0x0007
+#define RTC_AL_MASK_DOM 0x000f
+#define RTC_AL_MASK_DOW 0x0017
+#define RTC_AL_MASK_MTH 0x002f
+#define RTC_AL_MASK_YEA 0x006f
+#define RTC_AL_MASK_ALLOFF 0x0000
+#define RTC_AL_MASK_NORMAL (RTC_AL_MASK_HOU | RTC_AL_MASK_MIN)
+
+//RTC_POWERKEY
+#define RTC_POWERKEY1_KEY 0xa357
+#define RTC_POWERKEY2_KEY 0x67d2
+
+#define RTC_PROTECT1 0x586a
+#define RTC_PROTECT2 0x9136
+
+#if defined(DRV_RTC_INFO_MASK)
+ #define RTC_INFO1_RESETDTIME 0x000f
+ #define RTC_INFO1_INFO_MASK 0x00f0
+ #define RTC_INFO2_INFO_MASK 0x00ff
+#endif /*DRV_RTC_INFO_MASK*/
+
+#if defined(DRV_RTC_REG_COMM)
+#if !defined(DRV_RTC_PDN_EXTEND)
+#define RTC_PDN1_MASK 0x00f1
+#endif /*!defined(DRV_RTC_PDN_EXTEND)*/
+#endif /*DRV_RTC_REG_COMM*/
+
+
+#if defined(DRV_RTC_W_FLAG)
+
+#define RTC_POWERKEY_BUSY 0x3
+#define RTC_BBPU_BUSY 0x4
+#define RTC_TIME_BUSY 0x8000
+
+#endif
+
+#if defined(DRV_RTC_HW_CALI)
+#define RTC_DIFF_MASK 0x0fff
+#define RTC_CALI_MASK 0x007f
+#define RTC_WRTGR_WRTGR 0x0001
+#endif
+
+
+#define RTC_OSC32_AMP_EN 0x100
+
+#if defined(DRV_RTC_INTERNAL_32K_AS_6255)
+#define RTC_OSC32_XOSC32_ENB 0x020
+#define RTC_OSC32_EMBCK_SEL_MODE 0x040
+#define RTC_OSC32_EMBCK_SEL 0x080
+#define RTC_OSC32_EOSC_CHOP_EN 0x400
+
+#define RTC_GPIO_VBAT_LPSTA_RAW 0x0001
+#define RTC_GPIO_EMBCK_SWITCH_FAIL 0x0002
+#endif
+
+#if defined(DRV_RTC_GPIO)
+#define RTC_GPIO_LPEN 0x0004
+#define RTC_GPIO_LPRST 0x0008
+#define RTC_GPIO_CDBO 0x0010
+#define RTC_GPIO_F32KOB 0x0020
+#define RTC_GPIO_GPO 0x0040
+#define RTC_GPIO_GOE 0x0080
+#define RTC_GPIO_GSR 0x0100
+#define RTC_GPIO_GSMT 0x0200
+#define RTC_GPIO_GPEN 0x0400
+#define RTC_GPIO_GPU 0x0800
+#define RTC_GPIO_GE4 0x1000
+#define RTC_GPIO_GE8 0x2000
+#define RTC_GPIO_GPI 0x4000
+#define RTC_GPIO_LPSTA_RAW 0x8000
+#endif
+
+#endif /*!defined(DRV_RTC_OFF)*/
+
+#endif /*_RTC_HW_H*/
+
diff --git a/mcu/driver/peripheral/inc/rtc_sw.h b/mcu/driver/peripheral/inc/rtc_sw.h
new file mode 100644
index 0000000..c94e373
--- /dev/null
+++ b/mcu/driver/peripheral/inc/rtc_sw.h
@@ -0,0 +1 @@
+/* Empty */
\ No newline at end of file
diff --git a/mcu/driver/peripheral/inc/rtc_sw_new.h b/mcu/driver/peripheral/inc/rtc_sw_new.h
new file mode 100644
index 0000000..9fa811e
--- /dev/null
+++ b/mcu/driver/peripheral/inc/rtc_sw_new.h
@@ -0,0 +1,544 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * rtc_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for RTC driver and adaption.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _RTC_SW_H
+#define _RTC_SW_H
+
+#include "drv_comm.h"
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+
+#define ONE_SHOT_DIS 0
+#define ONE_SHOT_EN 1
+
+#define RTC_BBPU_KEY 0x4300
+
+#define RTC_BBPU_ALARM_SW 0x0001
+#if defined(DRV_RTC_BBPU_AS_6205) || defined(DRV_RTC_BBPU_AS_6208) || defined(FPGA)
+ #define RTC_BBPU_PWR_POLARITY 0x0002
+#endif /*DRV_RTC_BBPU_AS_6205,DRV_RTC_BBPU_AS_6208,FPGA*/
+
+#if defined(DRV_RTC_BBPU_AS_6205B) || defined(DRV_RTC_BBPU_AS_6238)
+ #define RTC_BBPU_WRITE_EN 0x0002
+ #define RTC_BBPU_PWR_SW 0x0004
+ #define RTC_BBPU_AUTOPDN 0x0008
+ #if defined(DRV_RTC_BBPU_AS_6238)
+ #define RTC_BBPU_CLRPKY 0x0010
+ #define RTC_BBPU_RELOAD 0x0020
+ #define RTC_BBPU_CBUSY 0x0040
+ #define RTC_BBPU_DBING 0x0080
+ #endif
+#endif /*DRV_RTC_BBPU_AS_6205B*/
+
+#if defined(DRV_RTC_BBPU_AS_6218)
+ #define RTC_BBPU_PWR_POLARITY 0x0002
+ #define RTC_BBPU_PWR_SW 0x0004
+ #define RTC_BBPU_AUTOPDN 0x0008
+#endif /*DRV_RTC_BBPU_AS_6218*/
+
+#if defined(DRV_RTC_BBPU_AS_6205)
+ #define RTC_BBPU_PWR_SW 0x0004
+ #define RTC_BBPU_PDN_XOSC32K 0x0010
+#endif /*(DRV_RTC_BBPU_AS_6205)*/
+#if defined(DRV_RTC_BBPU_AS_6208) || defined(FPGA)
+ #define RTC_BBPU_PDN_XOSC32K 0x0004
+ #define RTC_BBPU_PWR_SW 0x0010
+#endif /*(DRV_RTC_BBPU_AS_6208,FPGA)*/
+
+#if defined(DRV_RTC_BBPU_AS_6276)
+ #define RTC_BBPU_PWR_SW 0x0004
+ #define RTC_BBPU_AUTOPDN 0x0008
+ #define RTC_BBPU_CLRPKY 0x0010
+ #define RTC_BBPU_RELOAD 0x0020
+ #define RTC_BBPU_CBUSY 0x0040
+#endif /*DRV_RTC_BBPU_AS_6205B*/
+
+
+#if defined(DRV_RTC_BBPU_AS_6205) || defined(DRV_RTC_BBPU_AS_6208) || defined(FPGA)
+ #define RTC_BBPU_POWERON (RTC_BBPU_PDN_XOSC32K|RTC_BBPU_PWR_SW|RTC_BBPU_PWR_POLARITY|RTC_BBPU_ALARM_SW|RTC_BBPU_KEY)
+ #define RTC_BBPU_POWEROFF (RTC_BBPU_PDN_XOSC32K|RTC_BBPU_PWR_POLARITY|RTC_BBPU_ALARM_SW|RTC_BBPU_KEY)
+#endif /*DRV_RTC_BBPU_AS_6205,DRV_RTC_BBPU_AS_6208,FPGA*/
+
+#if defined(DRV_RTC_BBPU_AS_6205B) || defined(DRV_RTC_BBPU_AS_6238)
+ #define RTC_BBPU_POWERON (RTC_BBPU_PWR_SW|RTC_BBPU_WRITE_EN|RTC_BBPU_ALARM_SW|RTC_BBPU_AUTOPDN|RTC_BBPU_KEY)
+ #define RTC_BBPU_POWEROFF (RTC_BBPU_WRITE_EN|RTC_BBPU_ALARM_SW|RTC_BBPU_AUTOPDN|RTC_BBPU_KEY)
+#endif /*DRV_RTC_BBPU_AS_6205B*/
+/*0227 TY removes RTC_BBPU_ALARM_SW*/
+#if defined(DRV_RTC_BBPU_AS_6218)
+ #define RTC_BBPU_POWERON (RTC_BBPU_PWR_SW|RTC_BBPU_PWR_POLARITY|RTC_BBPU_ALARM_SW|RTC_BBPU_AUTOPDN|RTC_BBPU_KEY)
+ #define RTC_BBPU_POWEROFF (RTC_BBPU_PWR_POLARITY|RTC_BBPU_ALARM_SW|RTC_BBPU_AUTOPDN|RTC_BBPU_KEY)
+#endif /*DRV_RTC_BBPU_AS_6218*/
+
+#if defined(DRV_RTC_BBPU_AS_6276)
+ #define RTC_BBPU_POWERON (RTC_BBPU_PWR_SW|RTC_BBPU_ALARM_SW|RTC_BBPU_AUTOPDN|RTC_BBPU_KEY)
+ #define RTC_BBPU_POWEROFF (RTC_BBPU_ALARM_SW|RTC_BBPU_AUTOPDN|RTC_BBPU_KEY)
+#endif /*DRV_RTC_BBPU_AS_6205B*/
+
+typedef struct __rtc
+{
+ kal_uint8 rtc_sec; /* seconds after the minute - [0,59] */
+ kal_uint8 rtc_min; /* minutes after the hour - [0,59] */
+ kal_uint8 rtc_hour; /* hours after the midnight - [0,23] */
+ kal_uint8 rtc_day; /* day of the month - [1,31] */
+ kal_uint8 rtc_mon; /* months - [1,12] */
+ kal_uint8 rtc_wday; /* days in a week - [1,7] */
+ kal_uint8 rtc_year; /* years - [0,127] */
+} t_rtc;
+
+typedef struct
+{
+ void (*rtc_tcfunc)(void);
+ void (*rtc_alfunc)(void);
+}rtc_callbac;
+
+typedef struct
+{
+ kal_hisrid hisr;
+}rtc_module;
+
+typedef struct
+{
+kal_bool time_valid;
+t_rtc rtc_time;
+kal_bool ticks_diff_valid;
+kal_int32 ticks_diff_per_hour;
+} rtc_nvram_data;
+
+typedef struct{
+ module_type dest_mod_id;
+ sap_type sap_id;
+ msg_type msg_id;
+}RTC_REG_MODULE_ILM_INFO_T;
+
+typedef enum
+{
+ rtc_pdn1 = 0,
+ rtc_pdn2,
+ rtc_max_index
+} RTC_PDN_INDEX;
+
+#if defined(DRV_RTC_REG_SPAR)
+typedef enum
+{
+ rtc_spar0 = 0,
+ rtc_spar1,
+ rtc_spar_max_index
+}RTC_SPAR_INDEX;
+#endif
+
+#if defined(DRV_RTC_GPIO)
+typedef enum {
+ RTC_GPIO_DISABLE = 0,
+ RTC_GPIO_EXPORT_32K,
+ RTC_GPIO_EXPORT_COREDETB,
+}RTC_GPIO_MODE_enum;
+
+typedef enum {
+ RTC_GPIO_NO_PULL = 0,
+ RTC_GPIO_PULL_DOWN,
+ RTC_GPIO_PULL_UP
+}RTC_GPIO_PULL_TYPE_enum;
+
+typedef enum {
+ RTC_GPIO_DS_4mA = 0,
+ RTC_GPIO_DS_8mA,
+ RTC_GPIO_DS_12mA,
+ RTC_GPIO_DS_16mA
+}RTC_GPIO_DRIVING_STRENGTH_enum;
+#endif //defined(DRV_RTC_GPIO)
+
+#if defined(DRV_RTC_REG_COMM)
+
+kal_uint16 RTC_Read_PDN(RTC_PDN_INDEX PDNIndex);
+void RTC_Set_PDN_bits(RTC_PDN_INDEX PDNIndex,kal_uint16 flag);
+void RTC_Clear_PDN_bits(RTC_PDN_INDEX PDNIndex,kal_uint16 flag);
+void RTC_Write_PDN_bits(RTC_PDN_INDEX PDNIndex,kal_uint16 flag);
+
+#endif //#if defined(DRV_RTC_REG_COMM)
+
+#if defined(DRV_RTC_REG_SPAR)
+kal_uint16 RTC_Read_SPAR(RTC_SPAR_INDEX SPARIndex);
+void RTC_Write_SPAR(RTC_SPAR_INDEX SPARIndex, kal_uint16 flag);
+#endif // End of #if defined(DRV_RTC_REG_SPAR)
+// ============================================================
+// Exported APIs, used by modules other than driver level functions
+extern void RTC_Config_(kal_uint8 AL_EN,kal_uint8 TC_EN);
+extern void RTC_InitTC_Time(t_rtc *rtctime);
+extern void RTC_GetTime_(t_rtc *rtctime);
+extern void RTC_SetAlarm(t_rtc *rtctime);
+extern kal_bool RTC_GetALTime(t_rtc *rtctime);
+extern kal_bool RTC_isFisrtOn(void);
+extern void RTC_setPWRKey(void);
+extern void RTC_setXOSC_(void);
+extern void RTC_unlockPROT(void);
+#if defined(DRV_RTC_LOW_POWER_DETECT)
+extern void RTC_Clear_LPSTA_RAW(void);
+extern void RTC_Set_GPIO_Output_Mode(kal_bool value,kal_bool is_SlewRateOn);
+extern kal_bool RTC_Get_GPIO_Input(void);
+extern void RTC_Set_GPIO_Input_Mode(RTC_GPIO_PULL_TYPE_enum PullType,RTC_GPIO_DRIVING_STRENGTH_enum PullDs,kal_bool is_SmithTrigger);
+extern void RTC_Set_GPIO_Mode(RTC_GPIO_MODE_enum Mode);
+#endif //#if defined(DRV_RTC_LOW_POWER_DETECT)
+
+// ============================================================
+// MoDIS parser skip start
+// Exported functions, used by driver level functions
+extern kal_bool isPWROnByRTC(void);
+extern void RTC_IRQOneShotEnable(kal_uint8 oneShotEN);
+extern void RTC_LISR(void);
+extern void RTC_init_(void (*RTC_TCCallback)(void),void (*RTC_ALCallback)(void));
+extern kal_bool RTC_is_MS_FirstPowerOn_(void);
+extern kal_bool RTC_is_config_valid(void);
+extern kal_bool RTC_is_Time_Valid(t_rtc *time);
+extern void RTC_GetTimeOnly(t_rtc *rtctime );
+extern kal_uint8 RTC_read_xosc_reg(void);
+extern void RTC_write_xosc_reg(kal_uint16 reg_value);
+extern void RTC_SaveTC_Time(t_rtc *rtctime);
+extern void RTC_set_First_PowerOn(kal_bool isFirstPowerOn);
+extern kal_bool RTC_Bootloader_PowerOn_(void);
+
+#if defined(DRV_RTC_HW_CALI)
+extern void RTC_wait_busy(void);
+extern void RTC_write_trigger(void);
+extern void RTC_write_trigger_wait(void);
+#endif /* defined(DRV_RTC_HW_CALI) */
+// MoDIS parser skip end
+
+// ============================================================
+// MoDIS parser skip start
+// Unknown functions, maybe previous owner forgot to delete
+extern void RTC_BBPUOpen(kal_bool open);
+extern void RTC_BBPWRUP_init(void);
+// MoDIS parser skip end
+
+#if defined(DRV_RTC_REG_COMM)
+//pwic may change pdn value during booting, save the original value of pdn1.
+extern kal_uint16 originalPDN1;
+extern kal_uint16 RTC_original_pnd1(void);
+#endif
+
+#if !defined(__FUE__) && !defined(__UBL__)
+extern kal_bool RTC_Set_Module_ILM_Info(RTC_REG_MODULE_ILM_INFO_T *Module_ilm_info);
+#endif
+
+#if !defined(DRV_RTC_OFF)
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RTC_REG_DBG__)
+#define DRV_RTC_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+#define DRV_RTC_Reg(addr) DRV_DBG_Reg(addr)
+#define DRV_RTC_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define DRV_RTC_Reg32(addr) DRV_DBG_Reg32(addr)
+#define DRV_RTC_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+#define DRV_RTC_Reg8(addr) DRV_DBG_Reg8(addr)
+#define DRV_RTC_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+#define DRV_RTC_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+#define DRV_RTC_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#define DRV_RTC_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+#define DRV_RTC_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+#define DRV_RTC_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+#define DRV_RTC_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+#define DRV_RTC_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+#define DRV_RTC_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+#else
+#define DRV_RTC_WriteReg(addr,data) DRV_WriteReg(addr,data)
+#define DRV_RTC_Reg(addr) DRV_Reg(addr)
+#define DRV_RTC_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define DRV_RTC_Reg32(addr) DRV_Reg32(addr)
+#define DRV_RTC_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+#define DRV_RTC_Reg8(addr) DRV_Reg8(addr)
+#define DRV_RTC_ClearBits(addr,data) DRV_ClearBits(addr,data)
+#define DRV_RTC_SetBits(addr,data) DRV_SetBits(addr,data)
+#define DRV_RTC_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define DRV_RTC_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+#define DRV_RTC_SetBits32(addr,data) DRV_SetBits32(addr,data)
+#define DRV_RTC_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+#define DRV_RTC_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+#define DRV_RTC_SetBits8(addr,data) DRV_SetBits8(addr,data)
+#define DRV_RTC_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RTC_REG_DBG__)
+
+#else //!defined(DRV_RTC_OFF)
+
+#define DRV_RTC_WriteReg(addr,data)
+#define DRV_RTC_Reg(addr) drv_dummy_return()
+#define DRV_RTC_WriteReg32(addr,data)
+#define DRV_RTC_Reg32(addr) drv_dummy_return()
+#define DRV_RTC_WriteReg8(addr,data)
+#define DRV_RTC_Reg8(addr) drv_dummy_return()
+#define DRV_RTC_ClearBits(addr,data)
+#define DRV_RTC_SetBits(addr,data)
+#define DRV_RTC_SetData(addr, bitmask, value)
+#define DRV_RTC_ClearBits32(addr,data)
+#define DRV_RTC_SetBits32(addr,data)
+#define DRV_RTC_SetData32(addr, bitmask, value)
+#define DRV_RTC_ClearBits8(addr,data)
+#define DRV_RTC_SetBits8(addr,data)
+#define DRV_RTC_SetData8(addr, bitmask, value)
+
+#endif //!defined(DRV_RTC_OFF)
+
+#endif
+
diff --git a/mcu/driver/peripheral/inc/rtc_trc.h b/mcu/driver/peripheral/inc/rtc_trc.h
new file mode 100644
index 0000000..e8a39d8
--- /dev/null
+++ b/mcu/driver/peripheral/inc/rtc_trc.h
@@ -0,0 +1,141 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * rtc_trc.h
+ *
+ * Project:
+ * --------
+ * MAUI
+ *
+ * Description:
+ * ------------
+ * This is trace map definition for RTC driver
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ ****************************************************************************/
+#ifndef _RTC_TRC_H
+#define _RTC_TRC_H
+
+
+#ifndef GEN_FOR_PC
+
+ #ifndef _STACK_CONFIG_H
+ #error "stack_config.h should be included before tst_config.h"
+ #endif
+
+#else
+ #include "kal_trace.h"
+#endif /* GEN_FOR_PC */
+
+
+#ifndef _KAL_TRACE_H
+ #error "kal_trace.h should be included before tst_trace.h"
+#endif
+
+#if !defined(GEN_FOR_PC)
+#if defined(__TST_MODULE__) || defined(__CUSTOM_RELEASE__)
+ #include "rtc_trc_gen.h"
+#endif /* TST Trace Defintion */
+#endif
+BEGIN_TRACE_MAP(MOD_RTC_HISR)
+
+ TRC_MSG(RTC_REPEAT_CALI_ADJUST_COUNT,"RTC adjust %d count for repeat calibration register")
+ TRC_MSG(RTC_REPEAT_CALI_VALUE,"RTC repeat calibration register value: %x")
+ TRC_MSG(RTC_REPEAT_CALI_VALUE_EXCEED_MAX,"RTC repeat calibration value %d exceed max")
+ TRC_MSG(RTC_REPEAT_CALI_VALUE_EXCEED_MIN,"RTC repeat calibration value %d exceed min")
+ TRC_MSG(RTC_REPEAT_CALI_PERFORM_CALI,"RTC repeat calibration perform for %d counts")
+
+ TRC_MSG(RTC_ONESHOT_CALI_PERFORM_COUNT,"RTC one shot calibration for %d counts, remains %d counts")
+ TRC_MSG(RTC_ONESHOT_CALI_VALUE,"RTC oneshot calibration register value: %x")
+ TRC_MSG(RTC_ONESHOT_CALI_FINISH,"RTC oneshot calibration finish")
+
+ TRC_MSG(RTC_HW_CALI_START_MEASURE_INACCURATE,"RTC HW cali, start to measure rtc inaccurate: (%d:%d:%d)")
+ TRC_MSG(RTC_HW_CALI_INIT_MEASURE_ACCURATE_L1_TICK,"RTC HW cali, init L1 tick: %d")
+ TRC_MSG(RTC_HW_CALI_FINISH_MEASURE_INACCURATE,"RTC HW cali, finish measuring rtc inaccurate: (%d:%d:%d)")
+ TRC_MSG(RTC_HW_CALI_FINISH_MEASURE_ACCURATE_L1_TICK,"RTC HW cali, finish L1 tick: %d, inaccurate ticks: %d")
+ TRC_MSG(RTC_HW_CALI_NO_NEED_TO_CALI,"RTC HW cali, no need to perform calibration, no diff count: %d")
+ TRC_MSG(RTC_HW_CALI_IN_PROGRESS,"RTC HW cali, in progress: (%d:%d:%d)")
+ TRC_MSG(RTC_HW_CALI_INIT_REPEAT_CALI_COUNT,"RTC HW cali, init repeat cali count: %d")
+
+ TRC_MSG(RTC_SW_CALI_START_POWEROFF_CALI,"RTC SW cali, start to do power off cali")
+ TRC_MSG(RTC_SW_CALI_START_POWEROFF_CALI_TIME,"RTC SW cali, current time before power off cali: (%d:%d:%d)")
+ TRC_MSG(RTC_SW_CALI_FINISH_POWEROFF_CALI_TIME,"RTC SW cali, current time after power off cali: (%d:%d:%d)")
+ TRC_MSG(RTC_SW_CALI_FINISH_2ND_POWEROFF_CALI,"RTC SW cali, wait %d ticks to perform 2nd power off cali")
+ TRC_MSG(RTC_SW_CALI_AFTER_2ND_POWEROFF_CALI,"RTC SW cali, current time after 2nd power off cali: (%d:%d:%d)")
+ TRC_MSG(RTC_SW_CALI_START_POWERON_CALI_TIME,"RTC SW cali, start power on cali: (%d:%d:%d), init tick: %d")
+ TRC_MSG(RTC_SW_CALI_POWERON_CALI_START_INACCURACY_MEASURE,"RTC SW cali, start accuracy measure")
+ TRC_MSG(RTC_SW_CALI_POWERON_CALI_FINISH_INACCURACY_MEASURE,"RTC SW cali, accuracy for one hour: %d ticks")
+ TRC_MSG(RTC_SW_CALI_POWERON_CALI_START,"RTC SW cali, start power on cali: (%d:%d:%d), init tick: %d")
+ TRC_MSG(RTC_SW_CALI_WRITE_NVRAM,"RTC SW cali, write to NVRAM")
+ TRC_MSG(RTC_SW_CALI_KAL_EXPIRE_EARLY,"RTC SW cali, KAL_timer expired early, expected: %d (tick), now: %d")
+ TRC_MSG(RTC_SW_CALI_TIMOUE_NOT_IN_SEC_BOUNDARY,"RTC SW cali, timeout not in second boundary: %d (tick)")
+ TRC_MSG(RTC_SW_CALI_TIMOUE_OUT,"RTC SW cali timeout (%d:%d:%d), current frame tick: %d")
+ TRC_MSG(RTC_SW_CALI_UPDATE_TIME,"RTC SW cali, update time (%d:%d:%d), current frame tick: %d")
+ TRC_MSG(RTC_SW_CALI_POWEROFF_CALI_INIT1,"RTC SW cali, NVRAM time valid: %d")
+ TRC_MSG(RTC_SW_CALI_POWEROFF_CALI_INIT2,"RTC SW cali, NVRAM time: %d-%d-%d (%d:%d:%d)")
+ TRC_MSG(RTC_SW_CALI_POWEROFF_CALI_INIT3,"RTC SW cali, NVRAM tick diff valud: %d")
+ TRC_MSG(RTC_SW_CALI_POWEROFF_CALI_INIT4,"RTC SW cali, NVRAM ticks_diff_per_hour: %d")
+ TRC_MSG(RTC_SW_CALI_CURR_POWER_TIME,"RTC SW cali, curr power on time: %d-%d-%d (%d:%d:%d)")
+ TRC_MSG(RTC_SW_CALI_RTC_TIME_IN_MINUTE_BOUNDARY,"RTC SW cali, rtc time in minute boundary: %d, delay 6 sec")
+ TRC_MSG(RTC_SW_CALI_RTC_TIME_IN_ALARM_BOUNDARY,"RTC SW cali, rtc time in alarm boundary: %d, delay 6 sec")
+ TRC_MSG(RTC_SW_CALI_INACCURATE_TICK_DURING_POWEROFF,"RTC cali, inaccurate ticks during power off: %d")
+ TRC_MSG(RTC_SW_CALI_ALARM_POWERON_AND_NEED_BACKWARD_TIME,"RTC cali, alarm power on, but we need to backward time")
+ TRC_MSG(RTC_SW_CALI_ALARM_POWERON_AND_POWEROFF,"RTC cali, alarm power on but we backward time so power off")
+
+
+
+ TRC_MSG(RTC_TC_INTR_FOR_USER,"RTC TC intr for user")
+ TRC_MSG(RTC_AL_INTR,"RTC AL intr")
+
+ TRC_MSG(RTC_FORWARD_TIME_1,"RTC forward time: (%d:%d:%d) forward %d hour, %d min, %d sec")
+ TRC_MSG(RTC_FORWARD_TIME_2,"RTC forward time done: (%d:%d:%d)")
+ TRC_MSG(RTC_BACKWARD_TIME_1,"RTC backward time: (%d:%d:%d) backward %d hour, %d min, %d sec")
+ TRC_MSG(RTC_BACKWARD_TIME_2,"RTC backward time done: (%d:%d:%d)")
+
+
+
+
+
+END_TRACE_MAP(MOD_RTC_HISR)
+
+#endif /* _RTC_TRC_H */
+
+
diff --git a/mcu/driver/peripheral/inc/rwg_hw.h b/mcu/driver/peripheral/inc/rwg_hw.h
new file mode 100644
index 0000000..9044b98
--- /dev/null
+++ b/mcu/driver/peripheral/inc/rwg_hw.h
@@ -0,0 +1,376 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * rwg_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for Random Waveform Generator (Enhaced PWM) driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef RWG_HW_H
+#define RWG_HW_H
+#include "drv_features_pwm.h"
+
+/*add by RHR suggest Add*/
+#include "reg_base.h"
+/*add by RHR suggest Add*/
+
+#if defined(DRV_PWM_RWG)
+#ifndef DRV_PWM_OFF
+
+#define PWM_ENABLE (PWM_base+0x0000) /* PWM Enable */
+#define PWM4_DELAY (PWM_base+0x0004) /* PWM4 Delay Duration */
+#define PWM5_DELAY (PWM_base+0x0008) /* PWM5 Delay Duration */
+#define PWM6_DELAY (PWM_base+0x000C) /* PWM6 Delay Duration */
+
+#define PWM1_CON (PWM_base+0x0010) /* PWM1 Control */
+#define PWM1_HDURATION (PWM_base+0x0014) /* PWM1 High Duration */
+#define PWM1_LDURATION (PWM_base+0x0018) /* PWM1 Low Duration */
+#define PWM1_GDURATION (PWM_base+0x001C) /* PWM1 Guard Duration */
+#define PWM1_BUF0_BASE_ADDR (PWM_base+0x0020) /* PWM1 Buffer0 Base Address */
+#define PWM1_BUF0_SIZE (PWM_base+0x0024) /* PWM1 Buffer0 Size */
+#define PWM1_BUF1_BASE_ADDR (PWM_base+0x0028) /* PWM1 Buffer1 Base Address */
+#define PWM1_BUF1_SIZE (PWM_base+0x002C) /* PWM1 Buffer1 Size */
+#define PWM1_SEND_DATA0 (PWM_base+0x0030) /* PWM1 Send Data0 */
+#define PWM1_SEND_DATA1 (PWM_base+0x0034) /* PWM1 Send Data1 */
+#define PWM1_WAVE_NUM (PWM_base+0x0038) /* PWM1 Wave Number */
+#define PWM1_DATA_WIDTH (PWM_base+0x003C) /* PWM1 Data Width */
+#define PWM1_THRESH (PWM_base+0x0040) /* PWM1 Threshold */
+#define PWM1_SEND_WAVENUM (PWM_base+0x0044) /* PWM1 Send Wave Number */
+#define PWM1_VALID (PWM_base+0x0048) /* PWM1 Valid */
+
+#define PWM2_CON (PWM_base+0x0050) /* PWM2 Control */
+#define PWM2_HDURATION (PWM_base+0x0054) /* PWM2 High Duration */
+#define PWM2_LDURATION (PWM_base+0x0058) /* PWM2 Low Duration */
+#define PWM2_GDURATION (PWM_base+0x005C) /* PWM2 Guard Duration */
+#define PWM2_BUF0_BASE_ADDR (PWM_base+0x0060) /* PWM2 Buffer0 Base Address */
+#define PWM2_BUF0_SIZE (PWM_base+0x0064) /* PWM2 Buffer0 Size */
+#define PWM2_BUF1_BASE_ADDR (PWM_base+0x0068) /* PWM2 Buffer1 Base Address */
+#define PWM2_BUF1_SIZE (PWM_base+0x006C) /* PWM2 Buffer1 Size */
+#define PWM2_SEND_DATA0 (PWM_base+0x0070) /* PWM2 Send Data0 */
+#define PWM2_SEND_DATA1 (PWM_base+0x0074) /* PWM2 Send Data1 */
+#define PWM2_WAVE_NUM (PWM_base+0x0078) /* PWM2 Wave Number */
+#define PWM2_DATA_WIDTH (PWM_base+0x007C) /* PWM2 Data Width */
+#define PWM2_THRESH (PWM_base+0x0080) /* PWM2 Threshold */
+#define PWM2_SEND_WAVENUM (PWM_base+0x0084) /* PWM2 Send Wave Number */
+#define PWM2_VALID (PWM_base+0x0088) /* PWM2 Valid */
+
+#define PWM3_CON (PWM_base+0x0090) /* PWM3 Control */
+#define PWM3_HDURATION (PWM_base+0x0094) /* PWM3 High Duration */
+#define PWM3_LDURATION (PWM_base+0x0098) /* PWM3 Low Duration */
+#define PWM3_GDURATION (PWM_base+0x009C) /* PWM3 Guard Duration */
+#define PWM3_BUF0_BASE_ADDR (PWM_base+0x00A0) /* PWM3 Buffer0 Base Address */
+#define PWM3_BUF0_SIZE (PWM_base+0x00A4) /* PWM3 Buffer0 Size */
+#define PWM3_BUF1_BASE_ADDR (PWM_base+0x00A8) /* PWM3 Buffer1 Base Address */
+#define PWM3_BUF1_SIZE (PWM_base+0x00AC) /* PWM3 Buffer1 Size */
+#define PWM3_SEND_DATA0 (PWM_base+0x00B0) /* PWM3 Send Data0 */
+#define PWM3_SEND_DATA1 (PWM_base+0x00B4) /* PWM3 Send Data1 */
+#define PWM3_WAVE_NUM (PWM_base+0x00B8) /* PWM3 Wave Number */
+#define PWM3_DATA_WIDTH (PWM_base+0x00BC) /* PWM3 Data Width */
+#define PWM3_THRESH (PWM_base+0x00C0) /* PWM3 Threshold */
+#define PWM3_SEND_WAVENUM (PWM_base+0x00C4) /* PWM3 Send Wave Number */
+#define PWM3_VALID (PWM_base+0x00C8) /* PWM3 Valid */
+
+#define PWM4_CON (PWM_base+0x00D0) /* PWM4 Control */
+#define PWM4_HDURATION (PWM_base+0x00D4) /* PWM4 High Duration */
+#define PWM4_LDURATION (PWM_base+0x00D8) /* PWM4 Low Duration */
+#define PWM4_GDURATION (PWM_base+0x00DC) /* PWM4 Guard Duration */
+#define PWM4_BUF0_BASE_ADDR (PWM_base+0x00E0) /* PWM4 Buffer0 Base Address */
+#define PWM4_BUF0_SIZE (PWM_base+0x00E4) /* PWM4 Buffer0 Size */
+#define PWM4_BUF1_BASE_ADDR (PWM_base+0x00E8) /* PWM4 Buffer1 Base Address */
+#define PWM4_BUF1_SIZE (PWM_base+0x00EC) /* PWM4 Buffer1 Size */
+#define PWM4_SEND_DATA0 (PWM_base+0x00F0) /* PWM4 Send Data0 */
+#define PWM4_SEND_DATA1 (PWM_base+0x00F4) /* PWM4 Send Data1 */
+#define PWM4_WAVE_NUM (PWM_base+0x00F8) /* PWM4 Wave Number */
+#define PWM4_SEND_WAVENUM (PWM_base+0x00FC) /* PWM4 Send Wave Number */
+#define PWM4_VALID (PWM_base+0x0100) /* PWM4 Valid */
+
+#define PWM5_CON (PWM_base+0x0110) /* PWM5 Control */
+#define PWM5_HDURATION (PWM_base+0x0114) /* PWM5 High Duration */
+#define PWM5_LDURATION (PWM_base+0x0118) /* PWM5 Low Duration */
+#define PWM5_GDURATION (PWM_base+0x011C) /* PWM5 Guard Duration */
+#define PWM5_BUF0_BASE_ADDR (PWM_base+0x0120) /* PWM5 Buffer0 Base Address */
+#define PWM5_BUF0_SIZE (PWM_base+0x0124) /* PWM5 Buffer0 Size */
+#define PWM5_BUF1_BASE_ADDR (PWM_base+0x0128) /* PWM5 Buffer1 Base Address */
+#define PWM5_BUF1_SIZE (PWM_base+0x012C) /* PWM5 Buffer1 Size */
+#define PWM5_SEND_DATA0 (PWM_base+0x0130) /* PWM5 Send Data0 */
+#define PWM5_SEND_DATA1 (PWM_base+0x0134) /* PWM5 Send Data1 */
+#define PWM5_WAVE_NUM (PWM_base+0x0138) /* PWM5 Wave Number */
+#define PWM5_SEND_WAVENUM (PWM_base+0x013C) /* PWM5 Send Wave Number */
+#define PWM5_VALID (PWM_base+0x0140) /* PWM5 Valid */
+
+#define PWM6_CON (PWM_base+0x0150) /* PWM6 Control */
+#define PWM6_HDURATION (PWM_base+0x0154) /* PWM6 High Duration */
+#define PWM6_LDURATION (PWM_base+0x0158) /* PWM6 Low Duration */
+#define PWM6_GDURATION (PWM_base+0x015C) /* PWM6 Guard Duration */
+#define PWM6_BUF0_BASE_ADDR (PWM_base+0x0160) /* PWM6 Buffer0 Base Address */
+#define PWM6_BUF0_SIZE (PWM_base+0x0164) /* PWM6 Buffer0 Size */
+#define PWM6_BUF1_BASE_ADDR (PWM_base+0x0168) /* PWM6 Buffer1 Base Address */
+#define PWM6_BUF1_SIZE (PWM_base+0x016C) /* PWM6 Buffer1 Size */
+#define PWM6_SEND_DATA0 (PWM_base+0x0170) /* PWM6 Send Data0 */
+#define PWM6_SEND_DATA1 (PWM_base+0x0174) /* PWM6 Send Data1 */
+#define PWM6_WAVE_NUM (PWM_base+0x0178) /* PWM6 Wave Number */
+#define PWM6_SEND_WAVENUM (PWM_base+0x017C) /* PWM6 Send Wave Number */
+#define PWM6_VALID (PWM_base+0x0180) /* PWM6 Valid */
+
+#define PWM_INT_ENABLE (PWM_base+0x0190) /* PWM Interrupt Enable */
+#define PWM_INT_STATUS (PWM_base+0x0194) /* PWM Interrupt Status */
+#define PWM_INT_ACK (PWM_base+0x0198) /* PWM Interrupt Acknowledge */
+
+/* PWM_ENABLE register */
+#define PWM_ENABLE_MASK 0x0000003F
+#define PWM1_ENABLE_MASK 0x00000001
+ #define PWM1_ENABLE 0x00000001
+ #define PWM1_DISABLE 0x00000000
+#define PWM2_ENABLE_MASK 0x00000002
+ #define PWM2_ENABLE 0x00000002
+ #define PWM2_DISABLE 0x00000000
+#define PWM3_ENABLE_MASK 0x00000004
+ #define PWM3_ENABLE 0x00000004
+ #define PWM3_DISABLE 0x00000000
+#define PWM4_ENABLE_MASK 0x00000008
+ #define PWM4_ENABLE 0x00000008
+ #define PWM4_DISABLE 0x00000000
+#define PWM5_ENABLE_MASK 0x00000010
+ #define PWM5_ENABLE 0x00000010
+ #define PWM5_DISABLE 0x00000000
+#define PWM6_ENABLE_MASK 0x00000020
+ #define PWM6_ENABLE 0x00000020
+ #define PWM6_DISABLE 0x00000000
+#define PWM_SEQ_MODE_MASK 0x00000040
+ #define PWM_SEQ_MODE_ON 0x00000040
+ #define PWM_SEQ_MODE_OFF 0x00000000
+
+/* PWM4, PWM5, PWM6 Delay Duration register */
+#define PWM_DELAY_DURATON_MASK 0x0000FFFF
+#define PWM_DELAY_CLKSEL_MASK 0x00010000
+ #define PWM_DELAY_CLKSEL_52M 0x00000000
+ #define PWM_DELAY_CLKSEL_32K 0x00010000
+
+/* PWM1~PWM6 Control registers */
+#define PWM_CON_CLKDIV_SHIFT 0
+#define PWM_CON_CLKDIV_MASK 0x00000007
+ #define PWM_CON_CLKDIV_1 0x00000000
+ #define PWM_CON_CLKDIV_2 0x00000001
+ #define PWM_CON_CLKDIV_4 0x00000010
+ #define PWM_CON_CLKDIV_8 0x00000011
+ #define PWM_CON_CLKDIV_16 0x00000100
+ #define PWM_CON_CLKDIV_32 0x00000101
+ #define PWM_CON_CLKDIV_64 0x00000110
+ #define PWM_CON_CLKDIV_128 0x00000111
+#define PWM_CON_CLKSEL_SHIFT 3
+#define PWM_CON_CLKSEL_MASK 0x00000008
+ #define PWM_CON_CLKSEL_52M 0x00000000
+ #define PWM_CON_CLKSEL_32K 0x00000008
+#define PWM_CON_FIXED_CLKMODE_SHIFT 4
+#define PWM_CON_FIXED_CLKMODE_MASK 0x00000010
+ #define PWM_CON_FIXED_CLKMODE_0 0x00000000
+ #define PWM_CON_FIXED_CLKMODE_1 0x00000010
+#define PWM_CON_SRCSEL_SHIFT 5
+#define PWM_CON_SRCSEL_MASK 0x00000020
+ #define PWM_CON_SRCSEL_FIFO 0x00000000
+ #define PWM_CON_SRCSEL_MEM 0x00000020
+#define PWM_CON_MODE_SHIFT 6
+#define PWM_CON_MODE_MASK 0x00000040
+ #define PWM_CON_MODE_PERIODIC 0x00000000
+ #define PWM_CON_MODE_RANDOM 0x00000040
+#define PWM_CON_IDLE_VALUE_SHIFT 7
+#define PWM_CON_IDLE_VALUE_MASK 0x00000080
+ #define PWM_CON_IDLE_VALUE_0 0x00000000
+ #define PWM_CON_IDLE_VALUE_1 0x00000080
+#define PWM_CON_GUARD_VALUE_SHIFT 8
+#define PWM_CON_GUARD_VALUE_MASK 0x00000100
+ #define PWM_CON_GUARD_VALUE_0 0x00000000
+ #define PWM_CON_GUARD_VALUE_1 0x00000100
+#define PWM_CON_STOP_BITPOS_SHIFT 9
+#define PWM_CON_STOP_BITPOS_MASK 0x00007E00
+#define PWM_CON_OLD_PWM_MODE_SHIFT 15
+#define PWM_CON_OLD_PWM_MODE_MASK 0x00008000
+ #define PWM_CON_NEW_PWM_MODE 0x00000000
+ #define PWM_CON_OLD_PWM_MODE 0x00008000
+
+/* PWM1~PWM3 Data Width registers */
+#define PWM_DATA_WIDTH_MASK 0x00003FFF
+
+/* PWM1~PWM3 Threshold registers */
+#define PWM_THRESH_MASK 0x00003FFF
+
+/* PWM1~PWM6 Data Valid registers */
+#define PWM_DATA_VALID_MASK 0x0000000F
+#define PWM_BUF0_VALID_MASK 0x00000001
+ #define PWM_BUF0_INVALID 0x00000000
+ #define PWM_BUF0_VALID 0x00000001
+#define PWM_BUF0_VALID_WEN_MASK 0x00000002
+ #define PWM_BUF0_VALID_WDISABLE 0x00000000
+ #define PWM_BUF0_VALID_WENABLE 0x00000002
+#define PWM_BUF1_VALID_MASK 0x00000004
+ #define PWM_BUF1_INVALID 0x00000000
+ #define PWM_BUF1_VALID 0x00000004
+#define PWM_BUF1_VALID_WEN_MASK 0x00000008
+ #define PWM_BUF1_VALID_WDISABLE 0x00000000
+ #define PWM_BUF1_VALID_WENABLE 0x00000008
+
+/* PWM Interrupt Enable registers */
+#define PWM_INT_ENABLE_MASK 0x00000FFF
+#define PWM1_INT_FINISH_EN_MASK 0x00000001
+ #define PWM1_INT_FINISH_DISABLE 0x00000000
+ #define PWM1_INT_FINISH_ENABLE 0x00000001
+#define PWM1_INT_UNDERFLOW_EN_MASK 0x00000002
+ #define PWM1_INT_UNDERFLOW_DISABLE 0x00000000
+ #define PWM1_INT_UNDERFLOW_ENABLE 0x00000002
+#define PWM2_INT_FINISH_EN_MASK 0x00000004
+ #define PWM2_INT_FINISH_DISABLE 0x00000000
+ #define PWM2_INT_FINISH_ENABLE 0x00000004
+#define PWM2_INT_UNDERFLOW_EN_MASK 0x00000008
+ #define PWM2_INT_UNDERFLOW_DISABLE 0x00000000
+ #define PWM2_INT_UNDERFLOW_ENABLE 0x00000008
+#define PWM3_INT_FINISH_EN_MASK 0x00000010
+ #define PWM3_INT_FINISH_DISABLE 0x00000000
+ #define PWM3_INT_FINISH_ENABLE 0x00000010
+#define PWM3_INT_UNDERFLOW_EN_MASK 0x00000020
+ #define PWM3_INT_UNDERFLOW_DISABLE 0x00000000
+ #define PWM3_INT_UNDERFLOW_ENABLE 0x00000020
+#define PWM4_INT_FINISH_EN_MASK 0x00000040
+ #define PWM4_INT_FINISH_DISABLE 0x00000000
+ #define PWM4_INT_FINISH_ENABLE 0x00000040
+#define PWM4_INT_UNDERFLOW_EN_MASK 0x00000080
+ #define PWM4_INT_UNDERFLOW_DISABLE 0x00000000
+ #define PWM4_INT_UNDERFLOW_ENABLE 0x00000080
+#define PWM5_INT_FINISH_EN_MASK 0x00000100
+ #define PWM5_INT_FINISH_DISABLE 0x00000000
+ #define PWM5_INT_FINISH_ENABLE 0x00000100
+#define PWM5_INT_UNDERFLOW_EN_MASK 0x00000200
+ #define PWM5_INT_UNDERFLOW_DISABLE 0x00000000
+ #define PWM5_INT_UNDERFLOW_ENABLE 0x00000200
+#define PWM6_INT_FINISH_EN_MASK 0x00000400
+ #define PWM6_INT_FINISH_DISABLE 0x00000000
+ #define PWM6_INT_FINISH_ENABLE 0x00000400
+#define PWM6_INT_UNDERFLOW_EN_MASK 0x00000800
+ #define PWM6_INT_UNDERFLOW_DISABLE 0x00000000
+ #define PWM6_INT_UNDERFLOW_ENABLE 0x00000800
+
+/* PWM Interrupt Status registers */
+#define PWM_INT_STATUS_MASK 0x00000FFF
+#define PWM1_INT_FINISH_EN_ST 0x00000001
+#define PWM1_INT_UNDERFLOW_EN_ST 0x00000002
+#define PWM2_INT_FINISH_EN_ST 0x00000004
+#define PWM2_INT_UNDERFLOW_EN_ST 0x00000008
+#define PWM3_INT_FINISH_EN_ST 0x00000010
+#define PWM3_INT_UNDERFLOW_EN_ST 0x00000020
+#define PWM4_INT_FINISH_EN_ST 0x00000040
+#define PWM4_INT_UNDERFLOW_EN_ST 0x00000080
+#define PWM5_INT_FINISH_EN_ST 0x00000100
+#define PWM5_INT_UNDERFLOW_EN_ST 0x00000200
+#define PWM6_INT_FINISH_EN_ST 0x00000400
+#define PWM6_INT_UNDERFLOW_EN_ST 0x00000800
+
+/* PWM Interrupt ACK registers */
+#define PWM_INT_ACK_MASK 0x00000FFF
+#define PWM1_INT_FINISH_ACK 0x00000001
+#define PWM1_INT_UNDERFLOW_ACK 0x00000002
+#define PWM2_INT_FINISH_ACK 0x00000004
+#define PWM2_INT_UNDERFLOW_ACK 0x00000008
+#define PWM3_INT_FINISH_ACK 0x00000010
+#define PWM3_INT_UNDERFLOW_ACK 0x00000020
+#define PWM4_INT_FINISH_ACK 0x00000040
+#define PWM4_INT_UNDERFLOW_ACK 0x00000080
+#define PWM5_INT_FINISH_ACK 0x00000100
+#define PWM5_INT_UNDERFLOW_ACK 0x00000200
+#define PWM6_INT_FINISH_ACK 0x00000400
+#define PWM6_INT_UNDERFLOW_ACK 0x00000800
+
+#define PWM_TEST_SEL 0x100
+#endif // DRV_PWM_OFF
+#endif /* defined(DRV_PWM_RWG) */
+
+
+#endif
+
diff --git a/mcu/driver/peripheral/inc/rwg_sw.h b/mcu/driver/peripheral/inc/rwg_sw.h
new file mode 100644
index 0000000..a880571
--- /dev/null
+++ b/mcu/driver/peripheral/inc/rwg_sw.h
@@ -0,0 +1,348 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * rwg_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for Random Waveform Generator (Enhaced PWM) driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef RWG_SW_H
+#define RWG_SW_H
+#include "kal_general_types.h"
+#include "drv_comm.h"
+#include "drv_features_pwm.h"
+#include "dcl.h"
+#if defined(DRV_PWM_RWG)
+/*PWM user mode ID*/
+typedef enum
+{
+ PWM_OWNER_UEM=0,
+ PWM_OWNER_AF,
+ PWM_OWNER_NONE=0xff
+}pwm_owner_e;
+
+/*Select PWM1 clock scale*/
+typedef enum
+{
+ PWM_CLK_DIV_NONE=0,
+ PWM_CLK_DIV_2=1,
+ PWM_CLK_DIV_4=2,
+ PWM_CLK_DIV_8=3,
+ PWM_CLK_DIV_16=4,
+ PWM_CLK_DIV_32=5,
+ PWM_CLK_DIV_64=6,
+ PWM_CLK_DIV_128=7
+}pwm_clk_div_e;
+
+/*Select PWMn clock*/
+typedef enum
+{
+ PWM_CLK_SEL_52M=0,
+ PWM_CLK_SEL_32K=1
+}pwm_clk_sel_e;
+
+/*PWM channel enumerate*/
+typedef enum
+{
+ PWM1=0,
+ PWM2,
+ PWM3,
+ PWM4,
+ PWM5,
+ PWM6,
+ PWM_COUNT
+}pwm_num_e;
+
+typedef enum
+{
+ PWM_SEQ_EN_PWM3=0x1,
+ PWM_SEQ_EN_PWM34=0x03,
+ PWM_SEQ_EN_PWM35=0x05,
+ PWM_SEQ_EN_PWM345=0x07,
+ PWM_SEQ_EN_PWM36=0x09,
+ PWM_SEQ_EN_PWM346=0x0b,
+ PWM_SEQ_EN_PWM356=0x0d,
+ PWM_SEQ_EN_PWM3456=0x0f
+} pwm_seq_en_cnt_e;
+
+typedef enum
+{
+ PWM_BUF_INVALID_NONE=0,
+ PWM_BUF_0_INVALID,
+ PWM_BUF_1_INVALID,
+ PWM_BUF_0_1_INVALID
+} pwm_buf_invalid_e;
+typedef void (*DCL_PWM_INIT)(void);
+typedef void (*DCL_PWM_CLK_INIT)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 clk_sel, kal_uint32 clk_div);
+typedef void (*DCL_PWM_START)(DCL_UINT8 owner, DCL_UINT32 pwm_num);
+typedef void (*DCL_PWM_STOP)(DCL_UINT8 owner, DCL_UINT32 pwm_num);
+typedef DCL_BOOL (*DCL_PWM_CONFIGURE)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 mode, void *para);
+typedef void (*DCL_PWM_SET_BUF_VALID)(kal_uint8 owner, kal_uint32 pwm_num,kal_uint32 *buf_addr, kal_uint16 buf_size, kal_bool is_buf0);
+typedef void (*DCL_PWM_SET_DELAY)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 clk_sel, kal_uint16 delay_cnt);
+typedef DCL_BOOL (*DCL_PWM_SEQ_OPEN)(kal_uint8 owner);
+typedef void (*DCL_PWM_SEQ_START)(kal_uint8 owner, kal_uint8 en_cnt);
+typedef void (*DCL_PWM_SEQ_STOP)(kal_uint8 owner);
+typedef DCL_BOOL (*DCL_PWM_SEQ_CLOSE)(kal_uint8 owner);
+typedef void (*DCL_PWM_CONFIG_OLD)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 freq, kal_uint8 duty);
+typedef DCL_UINT8 (*DCL_PWM_GETCURRENT_LEVEL)(DCL_UINT8 pwm_num);
+typedef DCL_UINT32(*DCL_PWM_GETCURRENT_FREQ)(DCL_UINT8 pwm_num);
+typedef DCL_UINT8 (*DCL_PWM_GETCURRENT_DUTY)(DCL_UINT8 pwm_num);
+typedef void (*DCL_PWM_TEST_SELECT)(DCL_BOOL sel);
+typedef kal_bool (*DCL_PWM_OPEN)(kal_uint8 owner, kal_uint32 pwm_num);
+typedef kal_bool (*DCL_PWM_CLOSE)(kal_uint8 owner, kal_uint32 pwm_num);
+typedef void (*DCL_PWM_CONFIG_FREQ_STEPS)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 freq, kal_uint16 steps);
+typedef void (*DCL_PWM_SET_DUTY)(kal_uint8 owner, kal_uint32 pwm_num, kal_uint16 duty);
+typedef struct
+{
+ DCL_PWM_INIT pwmInit;
+ DCL_PWM_CLK_INIT pwmClkInit;
+ DCL_PWM_START pwmStart;
+ DCL_PWM_STOP pwmStop;
+ DCL_PWM_GETCURRENT_LEVEL pwmGetCurrent_level;
+ DCL_PWM_GETCURRENT_FREQ pwmGetCurrent_Freq;
+ DCL_PWM_GETCURRENT_DUTY pwmGetCurrent_Duty;
+ DCL_PWM_CONFIG_OLD pwmConfigOld;
+ DCL_PWM_TEST_SELECT pwmTestSelect;
+ DCL_PWM_CONFIGURE pwmConfigure;
+ DCL_PWM_OPEN pwmOpen;
+ DCL_PWM_CLOSE pwmClose;
+ DCL_PWM_SET_BUF_VALID pwmSetBufValid;
+ DCL_PWM_SET_DELAY pwmSetDelay;
+ DCL_PWM_SEQ_OPEN pwmSeqOpen;
+ DCL_PWM_SEQ_START pwmSeqStart;
+ DCL_PWM_SEQ_STOP pwmSeqStop;
+ DCL_PWM_SEQ_CLOSE pwmSeqClose;
+ DCL_PWM_CONFIG_FREQ_STEPS pwm_config_freq_steps;
+ DCL_PWM_SET_DUTY pwmSetDuty;
+}PWMDriver_t;
+
+extern void DCL_PWM_Start(kal_uint8 owner, kal_uint32 pwm_num);
+extern void DCL_PWM_Stop(kal_uint8 owner, kal_uint32 pwm_num);
+extern kal_uint8 DCL_PWM_GetCurrent_Level(kal_uint8 pwm_num);
+extern kal_uint8 DCL_PWM_GetCurrentDuty(kal_uint8 pwm_num);
+extern kal_uint32 DCL_PWM_GetCurrentFreq(kal_uint8 pwm_num);
+extern void DCL_PWM_ConfigOld(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 freq, kal_uint8 duty);
+
+extern void PWM_Init(void);
+extern kal_bool PWM_Open(kal_uint8 owner, kal_uint32 pwm_num);
+extern kal_bool PWM_Seq_Open(kal_uint8 owner);
+extern kal_bool PWM_Close(kal_uint8 owner, kal_uint32 pwm_num);
+extern kal_bool PWM_Seq_Close(kal_uint8 owner);
+extern void PWM_CLK_Init(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 clk_sel, kal_uint32 clk_div);
+extern kal_bool PWM_Configure(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 mode, void *para);
+extern void PWM_Start(kal_uint8 owner, kal_uint32 pwm_num);
+extern void PWM_Stop(kal_uint8 owner, kal_uint32 pwm_num);
+
+/* Below are for Sequence mode */
+extern void PMW_Set_Delay(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 clk_sel, kal_uint16 delay_cnt);
+extern void PWM_Seq_Start(kal_uint8 owner, kal_uint8 en_cnt);
+extern void PWM_Seq_Stop(kal_uint8 owner);
+//extern kal_uint32 PWM_Check_Buf_Valid(kal_uint32 pwm_num);
+extern void PWM_Set_Buf_Valid(kal_uint8 owner, kal_uint32 pwm_num, kal_uint32 *buf_addr, kal_uint16 buf_size, kal_bool is_buf0);
+
+/* Below are for OLD PWM backward compatibility. */
+// MoDIS parser skip start
+// The following APIs are implemented in other dummy API files
+extern void PWM1_Configure(kal_uint32 freq, kal_uint8 duty);
+extern void PWM2_Configure(kal_uint32 freq, kal_uint8 duty);
+// MoDIS parser skip end
+extern void PWM3_Configure(kal_uint32 freq, kal_uint8 duty);
+// MoDIS parser skip start
+// The following APIs are implemented in other dummy API files
+extern void PWM1_Start(void);
+extern void PWM2_Start(void);
+// MoDIS parser skip end
+extern void PWM3_Start(void);
+// MoDIS parser skip start
+// The following APIs are implemented in other dummy API files
+extern void PWM1_Stop(void);
+extern void PWM2_Stop(void);
+// MoDIS parser skip end
+extern void PWM3_Stop(void);
+
+// OLD PWM support for PWM port 4, 5, 6 begin
+extern void PWM4_Configure(kal_uint32 freq, kal_uint8 duty);
+extern void PWM5_Configure(kal_uint32 freq, kal_uint8 duty);
+extern void PWM6_Configure(kal_uint32 freq, kal_uint8 duty);
+extern void PWM4_Start(void);
+extern void PWM5_Start(void);
+extern void PWM6_Start(void);
+extern void PWM4_Stop(void);
+extern void PWM5_Stop(void);
+extern void PWM6_Stop(void);
+extern kal_uint8 PWM4_GetCurrentLevel(void);
+extern kal_uint8 PMW4_GetCurrentDuty(void);
+extern kal_uint32 PMW4_GetCurrentFreq(void);
+extern kal_uint8 PWM5_GetCurrentLevel(void);
+extern kal_uint8 PMW5_GetCurrentDuty(void);
+extern kal_uint32 PMW5_GetCurrentFreq(void);
+extern kal_uint8 PWM6_GetCurrentLevel(void);
+extern kal_uint8 PMW6_GetCurrentDuty(void);
+extern kal_uint32 PMW6_GetCurrentFreq(void);
+// OLD PWM support for PWM port 4, 5, 6 begin
+
+extern kal_uint8 PWM1_GetCurrentLevel(void);
+extern kal_uint8 PMW1_GetCurrentDuty(void);
+extern kal_uint32 PMW1_GetCurrentFreq(void);
+extern kal_uint8 PWM2_GetCurrentLevel(void);
+extern kal_uint8 PMW2_GetCurrentDuty(void);
+extern kal_uint32 PMW2_GetCurrentFreq(void);
+extern kal_uint8 PWM3_GetCurrentLevel(void);
+extern kal_uint32 PMW3_GetCurrentFreq(void);
+extern kal_uint8 PMW3_GetCurrentDuty(void);
+extern void PWM_Test_Select(kal_bool sel);
+#endif /* defined(DRV_PWM_RWG) */
+
+
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RWG_REG_DBG__)
+#define DRV_RWG_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+#define DRV_RWG_Reg(addr) DRV_DBG_Reg(addr)
+#define DRV_RWG_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define DRV_RWG_Reg32(addr) DRV_DBG_Reg32(addr)
+#define DRV_RWG_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+#define DRV_RWG_Reg8(addr) DRV_DBG_Reg8(addr)
+#define DRV_RWG_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+#define DRV_RWG_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+#define DRV_RWG_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#define DRV_RWG_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+#define DRV_RWG_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+#define DRV_RWG_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+#define DRV_RWG_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+#define DRV_RWG_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+#define DRV_RWG_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+#else
+#define DRV_RWG_WriteReg(addr,data) DRV_WriteReg(addr,data)
+#define DRV_RWG_Reg(addr) DRV_Reg(addr)
+#define DRV_RWG_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define DRV_RWG_Reg32(addr) DRV_Reg32(addr)
+#define DRV_RWG_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+#define DRV_RWG_Reg8(addr) DRV_Reg8(addr)
+#define DRV_RWG_ClearBits(addr,data) DRV_ClearBits(addr,data)
+#define DRV_RWG_SetBits(addr,data) DRV_SetBits(addr,data)
+#define DRV_RWG_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define DRV_RWG_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+#define DRV_RWG_SetBits32(addr,data) DRV_SetBits32(addr,data)
+#define DRV_RWG_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+#define DRV_RWG_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+#define DRV_RWG_SetBits8(addr,data) DRV_SetBits8(addr,data)
+#define DRV_RWG_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_RWG_REG_DBG__)
+#endif
+
diff --git a/mcu/driver/peripheral/inc/spi.h b/mcu/driver/peripheral/inc/spi.h
new file mode 100644
index 0000000..b0b64fc
--- /dev/null
+++ b/mcu/driver/peripheral/inc/spi.h
@@ -0,0 +1,609 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * spi.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for SPI driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __spi_h__
+#define __spi_h__
+
+//////////////////RHR-ADD//////////////////////
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+//////////////////RHR-ADD//////////////////////
+
+//////////////////RHR-REMOVE//////////////////////
+//#include <spi_define.h>
+//////////////////////////////////////////////////
+
+#include "drv_features.h"
+
+#if defined(DRV_SPI_SUPPORT)
+
+/** \brief Open the SPI interface
+ *
+ * Before using the SPI interface, users have to call this
+ * function to get one unique number to be used in later SPI
+ * API functions.
+ *
+ * \param id Points to a kal_int32. When this function is
+ * finished, and if it succeed, this variable is represented
+ * as an unique identification number which is used as a
+ * parameter in the other SPI API functions if needed.
+ * \return
+ * - KAL_TRUE if the SPI interface is available.
+ * - KAL_FALSE if the SPI interface is unavailable.
+ */
+#ifdef DRV_SPI_HAL
+#define SPI_OPEN(id) spi_open_old((id), __FILE__, __LINE__);
+#else
+#define SPI_OPEN(id) spi_open((id), __FILE__, __LINE__);
+#endif
+
+/** \brief Release the ownership of the SPI interface, so
+ * that others can use it.
+ *
+ * spi_open() will get the ownership of the SPI interface,
+ * you have to call this function to release the ownership.
+ *
+ * \param id The return value of spi_open().
+ * \return
+ * - KAL_TRUE if success.
+ * - KAL_FALSE if failure, caller can use spi_get_error_code()
+ * to examine what was wrong.
+ */
+#ifdef DRV_SPI_HAL
+#define SPI_CLOSE(id) spi_close_old((id))
+#else
+#define SPI_CLOSE(id) spi_close((id))
+#endif
+
+
+#define SPI_INTERFACE_MAX_PKT_LENGTH_PER_TIMES (0x400)
+#define SPI_INTERFACE_MAX_PKT_COUNT_PER_TIMES (0x100)
+
+/**
+ * \def SPI_FIFO_SIZE
+ * \ingroup spi
+ * Defines the internal TX/RX FIFO size of the SPI controller.
+ */
+#define SPI_FIFO_SIZE (32)
+
+/** \enum SPI_TIME_TYPE
+ * \ingroup spi
+ *
+ * @brief
+ * Specify the time intervals used by the SPI interface.
+ */
+enum SPI_TIME_TYPE {
+ SPI_TIME_SETUP,
+ /**<
+ * \ingroup spi
+ * Setup time.
+ */
+ SPI_TIME_HOLD,
+ /**<
+ * \ingroup spi
+ * Hold time.
+ */
+ SPI_TIME_LOW,
+ /**<
+ * \ingroup spi
+ * Low voltage time of the SPI clock.
+ */
+ SPI_TIME_HIGH,
+ /**<
+ * \ingroup spi
+ * High voltage time of the SPI clock.
+ */
+ SPI_TIME_IDLE
+ /**<
+ * \ingroup spi
+ * Idle time.
+ */
+};
+typedef enum SPI_TIME_TYPE SPI_TIME_TYPE;
+
+/** \enum SPI_INT_TYPE
+ * \ingroup spi
+ *
+ * @brief
+ * SPI interrupt category enum.
+ *
+ * This enumeration defines the two interrupts which SPI devices can generate.
+ */
+enum SPI_INT_TYPE {
+ SPI_INT_PAUSE,
+ /**<
+ * \ingroup spi
+ * Pause interrupt.
+ */
+ SPI_INT_FINISH
+ /**<
+ * \ingroup spi
+ * Finish interrupt.
+ */
+};
+typedef enum SPI_INT_TYPE SPI_INT_TYPE;
+
+/** \enum SPI_DIRECTION_TYPE
+ * \ingroup spi
+ *
+ * @brief
+ * SPI direction enum.
+ *
+ * This enumeration defines whether this SPI operation is
+ * transmission of reception.
+ */
+enum SPI_DIRECTION_TYPE {
+ SPI_TX,
+ /**<
+ * \ingroup spi
+ * Means transmission
+ */
+ SPI_RX
+ /**<
+ * \ingroup spi
+ * Means reception
+ */
+};
+typedef enum SPI_DIRECTION_TYPE SPI_DIRECTION_TYPE;
+
+/** \enum SPI_MLSB
+ * \ingroup spi
+ *
+ * @brief
+ * Specify the MSB or LSB used by the SPI TX/RX operation.
+ */
+enum SPI_MLSB {
+ SPI_LSB = 0,
+ /**<
+ * \ingroup spi
+ * LSB.
+ */
+ SPI_MSB
+ /**<
+ * \ingroup spi
+ * MSB.
+ */
+};
+typedef enum SPI_MLSB SPI_MLSB;
+
+/** \enum SPI_CPOL
+ * \ingroup spi
+ *
+ * @brief
+ * Choose the desired clock polarities supported by the SPI interface.
+ */
+enum SPI_CPOL {
+ SPI_CPOL_0 = 0,
+ /**<
+ * \ingroup spi
+ * SPI clock polarity 0.
+ */
+ SPI_CPOL_1
+ /**<
+ * \ingroup spi
+ * SPI clock polarity 1.
+ */
+};
+typedef enum SPI_CPOL SPI_CPOL;
+
+/** \enum SPI_CPHA
+ * \ingroup spi
+ *
+ * @brief
+ * Choose the desired clock formats supported by the SPI interface.
+ */
+enum SPI_CPHA {
+ SPI_CPHA_0 = 0,
+ /**<
+ * \ingroup spi
+ * SPI clock format 0.
+ */
+ SPI_CPHA_1
+ /**<
+ * \ingroup spi
+ * SPI clock format 1.
+ */
+};
+typedef enum SPI_CPHA SPI_CPHA;
+
+/** \enum SPI_MODE
+ * \ingroup spi
+ *
+ * @brief
+ * Choose the SPI FIFO mode or the SPI DMA mode.
+ */
+enum SPI_MODE {
+ SPI_MODE_FIFO = 0,
+ /**<
+ * \ingroup spi
+ * SPI FIFO mode.
+ */
+ SPI_MODE_DMA
+ /**<
+ * \ingroup spi
+ * SPI DMA mode.
+ */
+};
+typedef enum SPI_MODE SPI_MODE;
+
+/** \enum SPI_ERROR_CODE
+ * \ingroup spi
+ *
+ * @brief
+ * The possible result values of each SPI operations.
+ */
+enum SPI_ERROR_CODE {
+ SPI_NO_ERROR = 0,
+ /**<
+ * \ingroup spi
+ * No errors.
+ */
+
+ SPI_ERROR_CODE_UNAVAILABLE,
+ /**<
+ * \ingroup spi
+ * If ownership of the SPI interface is owned by another
+ * task.
+ */
+
+ SPI_ERROR_CODE_UNKNOWN_TIME_TYPE,
+ /**<
+ * \ingroup spi
+ * Unknown spi time type.
+ */
+
+ SPI_ERROR_CODE_UNKNOWN_BIT_STATUS,
+ /**<
+ * \ingroup spi
+ * Unknown spi bit status.
+ */
+
+ SPI_ERROR_CODE_UNKNOWN_INT_TYPE,
+ /**<
+ * \ingroup spi
+ * Unknown spi interrupt type.
+ */
+
+ SPI_ERROR_CODE_UNKNOWN_MSB_LSB_TYPE,
+ /**<
+ * \ingroup spi
+ * Unknown spi MSB/LSB.
+ */
+
+ SPI_ERROR_CODE_UNKNOWN_TRANSFER_DIRECTION,
+ /**<
+ * \ingroup spi
+ * Unknown spi TX/RX.
+ */
+
+ SPI_ERROR_CODE_UNKNOWN_TRANSFER_TYPE,
+ /**<
+ * \ingroup spi
+ * Unknown spi DMA/FIFO.
+ */
+
+ SPI_ERROR_CODE_UNKNOWN_CLK_POLARITY,
+ /**<
+ * \ingroup spi
+ * Unknown spi clock polarity.
+ */
+
+ SPI_ERROR_CODE_UNKNOWN_CLK_FORMAT,
+ /**<
+ * \ingroup spi
+ * Unknown spi clock format.
+ */
+
+ SPI_ERROR_CODE_ID_PTR_CAN_NOT_BE_ZERO,
+ /**<
+ * \ingroup spi
+ * In spi_open(), the specified ID address can not
+ * be 0.
+ */
+
+ SPI_ERROR_CODE_FILENAME_PTR_CAN_NOT_BE_ZERO,
+ /**<
+ * \ingroup spi
+ * In spi_open(), the specified filename address can not
+ * be 0.
+ */
+
+ SPI_ERROR_CODE_DMA_BUF_ADDR_CAT_NOT_BE_ZERO,
+ /**<
+ * \ingroup spi
+ * In SPI DMA mode, the specified buffer address can not
+ * be 0.
+ */
+
+ SPI_ERROR_CODE_CONFIG_ATTR_CAN_NOT_BE_ZERO,
+ /**<
+ * \ingroup spi
+ * In spi_config(), the specified spi_attr_t can not
+ * be 0.
+ */
+
+ SPI_ERROR_CODE_PKT_LENGTH_CAN_NOT_BE_ZERO,
+ /**<
+ * \ingroup spi
+ * In SPI DMA mode, the specified packet length can not be
+ * 0.
+ */
+
+ SPI_ERROR_CODE_PKT_COUNT_CAN_NOT_BE_ZERO,
+ /**<
+ * \ingroup spi
+ * In SPI DMA mode, the specified packet count can not be
+ * 0.
+ */
+
+ SPI_ERROR_CODE_PKT_LENGTH_TOO_LARGE,
+ /**<
+ * \ingroup spi
+ * In SPI DMA mode, the specified packet length is too
+ * large to operate.
+ */
+
+ SPI_ERROR_CODE_PKT_COUNT_TOO_LARGE,
+ /**<
+ * \ingroup spi
+ * In SPI DMA mode, the specified packet count is too
+ * large to operate.
+ */
+
+ SPI_ERROR_CODE_ADDR_NOT_4_ALIGN
+ /**<
+ * \ingroup spi
+ * The buffer addresses for TX and RX should be 4-byte
+ * alignment.
+ */
+};
+typedef enum SPI_ERROR_CODE SPI_ERROR_CODE;
+
+enum SPI_BIT_STATUS
+{
+ SPI_DISABLE,
+ SPI_ENABLE
+};
+typedef enum SPI_BIT_STATUS SPI_BIT_STATUS;
+
+/**
+ * \typedef spi_cb_func
+ * \ingroup spi
+ * The callback function type.
+ */
+typedef void (*spi_cb_func)(void);
+
+enum SPI_GET_TICK_MODE {
+ SPI_NO_GET_TICK_MODE,
+ SPI_GET_TICK_MODE_DELAY_1,
+ SPI_GET_TICK_MODE_DELAY_2
+};
+typedef enum SPI_GET_TICK_MODE SPI_GET_TICK_MODE;
+
+struct spi_attr_t {
+ kal_uint8 setup_time;
+ kal_uint8 hold_time;
+ kal_uint8 clk_low;
+ kal_uint8 clk_high;
+ kal_uint8 idle_time;
+ kal_bool enable_pause_int;
+ kal_bool enable_finish_int;
+ kal_bool enable_pause_mode;
+ kal_bool enable_deassert_mode;
+ SPI_MLSB tx_mlsb;
+ SPI_MLSB rx_mlsb;
+ SPI_MODE tx_mode;
+ SPI_MODE rx_mode;
+ SPI_CPOL clk_polarity;
+ SPI_CPHA clk_fmt;
+ SPI_GET_TICK_MODE get_tick;
+ kal_bool enable_ultra_high;
+ kal_uint16 ultra_high_thresh;
+ kal_bool enable_gmc_slow_down;
+ kal_bool enable_gmc_split_burst;
+ kal_uint16 gmc_slow_down_thresh;
+};
+typedef struct spi_attr_t spi_attr_t;
+
+typedef enum
+{ SPI_EVENT_INVALID = 0x0,
+ SPI_EVENT_TRANSFER_COMPLETE = 0x1
+} SPIEventType;
+
+extern volatile kal_eventgrpid spi_event_id;
+
+/* Export function prototype. */
+extern void SPI_LISR(void);
+
+#ifdef DRV_SPI_HAL
+extern kal_bool spi_open_old(
+#else
+extern kal_bool spi_open(
+#endif
+ kal_int32 * const id,
+ char const * const filename,
+ kal_uint32 const lineno);
+
+#ifdef DRV_SPI_HAL
+extern kal_bool spi_close_old(
+#else
+extern kal_bool spi_close(
+#endif
+ kal_int32 const id);
+
+extern kal_bool spi_set_time_interval(
+ kal_int32 const id,
+ SPI_TIME_TYPE const type,
+ kal_uint8 const value);
+
+extern kal_bool spi_set_interrupt(
+ kal_int32 const id,
+ SPI_INT_TYPE const type,
+ SPI_BIT_STATUS const status);
+
+extern kal_bool spi_set_msb(
+ kal_int32 const id,
+ SPI_DIRECTION_TYPE const type,
+ SPI_MLSB const msb);
+
+extern kal_bool spi_select_mode(
+ kal_int32 const id,
+ SPI_DIRECTION_TYPE const type,
+ SPI_MODE const mode);
+
+extern kal_bool spi_set_clock_polarity(
+ kal_int32 const id,
+ SPI_CPOL const cpol);
+
+extern kal_bool spi_set_clock_format(
+ kal_int32 const id,
+ SPI_CPHA const cpha);
+
+extern kal_bool spi_set_pause_mode(
+ kal_int32 const id,
+ kal_bool const status);
+
+extern kal_bool spi_set_deassert_mode(
+ kal_int32 const id,
+ kal_bool const status);
+
+extern kal_bool spi_set_desired_size(
+ kal_int32 const id,
+ kal_uint32 const length,
+ kal_uint16 const loop);
+
+extern kal_bool spi_set_get_tick_mode(
+ kal_int32 const id,
+ SPI_GET_TICK_MODE const get_tick);
+
+extern kal_bool spi_slow_down_gmc(
+ kal_int32 const id,
+ kal_bool const slow_down_enable,
+ kal_bool const split_burst_enable,
+ kal_uint16 const slow_down_thresh);
+
+extern kal_bool spi_set_ultra_high(
+ kal_int32 const id,
+ kal_bool const ultra_high_enable,
+ kal_uint16 const ultra_high_thresh);
+
+extern kal_bool spi_set_rwaddr(
+ kal_int32 const id,
+ SPI_DIRECTION_TYPE const type,
+ void * const addr);
+
+extern kal_bool spi_set_cb(
+ kal_int32 const id,
+ SPI_INT_TYPE const type,
+ spi_cb_func func,
+ spi_cb_func * const old);
+
+extern kal_bool spi_set_endian_reverse(
+ kal_int32 const id,
+ SPI_DIRECTION_TYPE const type,
+ kal_bool const reverse);
+
+extern kal_bool spi_config(
+ kal_int32 const id,
+ spi_attr_t * const attr);
+
+extern kal_bool spi_clear_fifo(
+ kal_int32 const id,
+ SPI_DIRECTION_TYPE const direction);
+
+extern kal_bool spi_reset(
+ kal_int32 const id);
+
+extern kal_bool spi_resume(
+ kal_int32 const id);
+
+extern kal_bool spi_activate(
+ kal_int32 const id);
+
+extern kal_bool spi_is_in_pause_mode(void);
+extern kal_bool spi_is_busy(void);
+
+extern kal_bool spi_wait_not_busy(
+ kal_int32 const id);
+
+extern kal_bool spi_fifo_push(
+ kal_int32 const id,
+ kal_uint32 const data);
+
+extern kal_bool spi_fifo_pop(
+ kal_int32 const id,
+ kal_uint32 * const data);
+
+extern void spi_init(void);
+
+extern int rand(void);
+
+#ifdef DRV_SPI_HAL
+extern kal_bool spi_get_driving_current(kal_bool* bEnableSlewRate, kal_uint32* current);
+extern kal_bool spi_set_driving_current(kal_bool bEnableSlewRate, kal_uint32 current);
+extern void spi_select_port(kal_uint32 port);
+#endif
+
+#endif
+
+#endif
diff --git a/mcu/driver/peripheral/inc/spi_define.h b/mcu/driver/peripheral/inc/spi_define.h
new file mode 100644
index 0000000..942b8e0
--- /dev/null
+++ b/mcu/driver/peripheral/inc/spi_define.h
@@ -0,0 +1,84 @@
+#ifndef __spi_define_h__
+#define __spi_define_h__
+
+//#define SPI_DVT_LOAD
+#define SPI_MAUI_LOAD
+
+#if defined(SPI_DVT_LOAD)
+
+/* DVT load */
+#include <typedefs.h>
+
+#define SPI_FAKE_KAL_SUPPORT
+#define SPI_FAKE_DRV_SUPPORT
+
+#define SPI_FULL_ISR_SUPPORT
+
+#define ENABLE_UT 1
+
+#include <spi_fake_reg_base.h>
+#include <spi_fake_intrCtrl.h>
+
+#elif defined(SPI_MAUI_LOAD)
+
+/* MAUI load */
+#define SPI_DRVPDN_SUPPORT
+
+#define SPI_FULL_KAL_SUPPORT
+#define SPI_FULL_DRV_SUPPORT
+#define SPI_FULL_ISR_SUPPORT
+
+#define SPI_HISR_SUPPORT
+
+
+//////////////////RHR ADD//////////////////////////
+#include "kal_public_defs.h"
+///////////////////////////////////////////////////
+
+//////////////////RHR-REMOVE//////////////////////
+//#include <reg_base.h>
+//#include <intrCtrl.h>
+//#include <drv_comm.h>
+//#include <drv_hisr.h>
+//#include <spi.h>
+//#include <spi_internal.h>
+//#include <gpio_hw.h>
+//#include <Stack_utils.h>
+//#if defined(__MTK_TARGET__)
+//#include <cache_sw.h>
+//#include <init.h>
+//#endif
+//#include <kal_non_specific_general_types.h>
+//#include <kal_release.h>
+//#if defined(SPI_DRVPDN_SUPPORT)
+//#include <drvpdn.h>
+//#endif
+//////////////////////////////////////////////////
+
+/* for kal_get_current_thread_ID() */
+//#include <rtfiles.h>
+//#include <Fs_kal.h>
+//extern kal_taskid kal_get_current_thread_ID(void);
+
+
+#else
+#error
+#endif
+
+#if defined(SPI_FULL_KAL_SUPPORT)
+#elif defined(SPI_FAKE_KAL_SUPPORT)
+#include <spi_fake_kal.h>
+#else
+#error
+#endif
+
+#if defined(SPI_FULL_DRV_SUPPORT)
+#include <drv_features.h>
+#elif defined(SPI_FAKE_DRV_SUPPORT)
+#include <spi_fake_drv.h>
+#else
+#error
+#endif
+
+
+#endif
diff --git a/mcu/driver/peripheral/inc/spi_internal.h b/mcu/driver/peripheral/inc/spi_internal.h
new file mode 100644
index 0000000..61df662
--- /dev/null
+++ b/mcu/driver/peripheral/inc/spi_internal.h
@@ -0,0 +1,340 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * spi_internal.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines the SPI driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __spi_internal_h__
+#define __spi_internal_h__
+
+//////////////////RHR-ADD//////////////////////
+#include "reg_base.h"
+//////////////////RHR-ADD//////////////////////
+
+//////////////////RHR-REMOVE//////////////////////
+//#include <spi_define.h>
+//////////////////////////////////////////////////
+
+
+/**
+ * \def SPI_CONF0_REG
+ * \ingroup spi
+ * Defines the SPI configuration 0 register.
+ */
+#define SPI_CONF0_REG (*((kal_uint32 volatile *)((SPI_base) + 0x0)))
+
+/**
+ * \def SPI_CONF1_REG
+ * \ingroup spi
+ * Defines the SPI configuration 1 register.
+ */
+#define SPI_CONF1_REG (*((kal_uint32 volatile *)((SPI_base) + 0x4)))
+
+/**
+ * \def SPI_TX_ADDR_REG
+ * \ingroup spi
+ * Defines the SPI TX source address register.
+ */
+#define SPI_TX_ADDR_REG (*((kal_uint32 volatile *)((SPI_base) + 0x8)))
+
+/**
+ * \def SPI_RX_ADDR_REG
+ * \ingroup spi
+ * Defines the SPI RX destination address register.
+ */
+#define SPI_RX_ADDR_REG (*((kal_uint32 volatile *)((SPI_base) + 0xC)))
+
+#define SPI_TX_FIFO_REG_ADDR ((kal_uint32 volatile *)((SPI_base) + 0x10))
+/**
+ * \def SPI_TX_FIFO_REG
+ * \ingroup spi
+ * Defines the SPI TX data FIFO register.
+ */
+#define SPI_TX_FIFO_REG (*SPI_TX_FIFO_REG_ADDR)
+
+#define SPI_RX_FIFO_REG_ADDR ((kal_uint32 volatile *)((SPI_base) + 0x14))
+/**
+ * \def SPI_RX_FIFO_REG
+ * \ingroup spi
+ * Defines the SPI RX data FIFO register.
+ */
+#define SPI_RX_FIFO_REG (*SPI_RX_FIFO_REG_ADDR)
+
+/**
+ * \def SPI_COMM_REG
+ * \ingroup spi
+ * Defines the SPI command register.
+ */
+#define SPI_COMM_REG (*((kal_uint32 volatile *)((SPI_base) + 0x18)))
+
+/**
+ * \def SPI_STATUS1_REG
+ * \ingroup spi
+ * Defines the SPI status register 1.
+ */
+#define SPI_STATUS1_REG (*((kal_uint32 volatile *)((SPI_base) + 0x1C)))
+
+/**
+ * \def SPI_STATUS2_REG
+ * \ingroup spi
+ * Defines the SPI status register 2.
+ */
+#define SPI_STATUS2_REG (*((kal_uint32 volatile *)((SPI_base) + 0x20)))
+
+#if defined (DRV_SPI_GMC_ARBITRATE )
+#define SPI_GMC_SLOW_DOWN_REG (*((kal_uint32 volatile *)((SPI_base) + 0x24)))
+#define SPI_ULTRA_HIGH_PRIORITY_REG (*((kal_uint32 volatile *)((SPI_base) + 0x28)))
+#endif
+#if defined (DRV_SPI_PAD_MACRO_SELECT )
+#define SPI_PAD_MACRO_SELECT_REG (*((kal_uint32 volatile *)((SPI_base) + 0x2C)))
+#endif
+
+/** \enum SPI_COMM_REG_BIT_POS
+ * \ingroup spi
+ *
+ * @brief
+ * Specify the bit position in the SPI command register.
+ */
+enum SPI_COMM_REG_BIT_POS
+{
+ SPI_COMM_BIT_ACT = 0,
+ /**<
+ * \ingroup spi
+ * The activate bit.
+ */
+ SPI_COMM_BIT_RESUME = 1,
+ /**<
+ * \ingroup spi
+ * The resume bit.
+ */
+ SPI_COMM_BIT_RESET = 2,
+ /**<
+ * \ingroup spi
+ * The reset bit.
+ */
+ SPI_COMM_BIT_PAUSE_EN = 4,
+ /**<
+ * \ingroup spi
+ * The pause enable bit.
+ */
+ SPI_COMM_BIT_CS_DEASSERT_EN = 5,
+ /**<
+ * \ingroup spi
+ * The deassert enable bit.
+ */
+ SPI_COMM_BIT_CPHA = 8,
+ /**<
+ * \ingroup spi
+ * The clock format bit.
+ */
+ SPI_COMM_BIT_CPOL = 9,
+ /**<
+ * \ingroup spi
+ * The clock polarity bit.
+ */
+ SPI_COMM_BIT_RX_DMA_EN = 10,
+ /**<
+ * \ingroup spi
+ * The RX DMA enable/disable bit.
+ */
+ SPI_COMM_BIT_TX_DMA_EN = 11,
+ /**<
+ * \ingroup spi
+ * The TX DMA enable/disable bit.
+ */
+ SPI_COMM_BIT_TX_MSBF = 12,
+ /**<
+ * \ingroup spi
+ * The TX MSB/LSB select bit.
+ */
+ SPI_COMM_BIT_RX_MSBF = 13,
+ /**<
+ * \ingroup spi
+ * The RX MSB/LSB select bit.
+ */
+ SPI_COMM_BIT_RX_ENDIAN = 14,
+ /**<
+ * \ingroup spi
+ * The RX big/little endian select bit.
+ */
+ SPI_COMM_BIT_TX_ENDIAN = 15,
+ /**<
+ * \ingroup spi
+ * The TX big/little endian select bit.
+ */
+ SPI_COMM_BIT_FINISH_IE = 16,
+ /**<
+ * \ingroup spi
+ * The finish mode enable/disable bit.
+ */
+ SPI_COMM_BIT_PAUSE_IE = 17
+ /**<
+ * \ingroup spi
+ * The pause mode enable/disable bit.
+ */
+};
+typedef enum SPI_COMM_REG_BIT_POS SPI_COMM_REG_BIT_POS;
+
+/** \enum SPI_STATUS1_BIT
+ * \ingroup spi
+ *
+ * @brief
+ * Specify the bit position in the SPI status register 1.
+ */
+enum SPI_STATUS1_BIT
+{
+ SPI_STATUS1_BIT_FINISH = (1 << 0),
+ /**<
+ * \ingroup spi
+ * The finish bit in the SPI status register 1.
+ */
+ SPI_STATUS1_BIT_PAUSE = (1 << 1)
+ /**<
+ * \ingroup spi
+ * The pause bit in the SPI status register 1.
+ */
+};
+typedef enum SPI_STATUS1_BIT SPI_STATUS1_BIT;
+
+/** \enum SPI_STATUS2_BIT
+ * \ingroup spi
+ *
+ * @brief
+ * Specify the bit position in the SPI status register 2.
+ */
+enum SPI_STATUS2_BIT
+{
+ SPI_STATUS2_BIT_BUSY = (1 << 0)
+ /**<
+ * \ingroup spi
+ * The busy bit in the SPI status register 2.
+ */
+};
+typedef enum SPI_STATUS2_BIT SPI_STATUS2_BIT;
+
+/** \enum SPI_STATUS_REG
+ * \ingroup spi
+ *
+ * @brief Choose the supported status registers.
+ */
+enum SPI_STATUS_REG
+{
+ SPI_STATUS_REG_1,
+ /**<
+ * \ingroup spi
+ * status register 1
+ */
+ SPI_STATUS_REG_2
+ /**<
+ * \ingroup spi
+ * status register 2
+ */
+};
+typedef enum SPI_STATUS_REG SPI_STATUS_REG;
+
+typedef enum
+{
+ SPI_GMC_SLOW_DOWN_ENABLE = 0,
+ SPI_GMC_SPLIT_BURST_ENABLE = 4
+} SPI_GMC_SLOW_DOWN_REG_BIT_POS;
+
+typedef enum
+{
+ SPI_ULTRA_HIGH_ENABLE = 0
+} SPI_ULTRA_HIGH_PRIORITY_REG_BIT_POS;
+
+#endif
diff --git a/mcu/driver/peripheral/inc/touch_panel.h b/mcu/driver/peripheral/inc/touch_panel.h
new file mode 100644
index 0000000..e244602
--- /dev/null
+++ b/mcu/driver/peripheral/inc/touch_panel.h
@@ -0,0 +1,90 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * serial_interface.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines Touch Panel Interface.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef TOUCH_PANEL_H
+#define TOUCH_PANEL_H
+#include "touch_panel_.h"
+
+
+/********************For upper layer*************************/
+void touch_panel_enable(kal_bool enable);/*enable/disable touch panel*/
+kal_bool touch_panel_get_event(TouchPanelMultipleEventStruct *touch_data);/*get touch event*/
+void touch_panle_conf_timeout_period(kal_uint32 longtap,
+ kal_uint32 repeat,
+ kal_uint32 handwriting_longtap);
+void touch_panle_conf_sample_period(kal_uint32 low, kal_uint32 high);
+void touch_panel_flush(void);/*flsuh data in ring buffer*/
+void touch_panel_start_cali(TouchPanelCoordStruct *point, kal_uint16 num);
+void touch_panel_stop_cali(void);
+void touch_panel_read_cali(TouchPanelCaliStruct *cali);
+void touch_panel_set_cali(TouchPanelCaliStruct cali);
+void touch_panel_reset(kal_bool skip_unrelease_enable);
+void touch_panel_reset_handwriting(void);
+void touch_panel_conf_move_offset(kal_uint16 pen_offset, kal_uint16 stroke_offset,
+ kal_uint16 longtap_pen_offset,
+ kal_uint16 longtap_stroke_offset);
+void touch_panel_conf_handwriting(TouchPanelHandAreaStruct *area, kal_uint16 n,
+ TouchPanelHandAreaStruct *ext_area);
+void touch_panel_cb_registration (TP_EVENT_FUNC function, void *parameter);
+
+#endif
+
+
diff --git a/mcu/driver/peripheral/inc/touch_panel_.h b/mcu/driver/peripheral/inc/touch_panel_.h
new file mode 100644
index 0000000..a6929d1
--- /dev/null
+++ b/mcu/driver/peripheral/inc/touch_panel_.h
@@ -0,0 +1,514 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * serial_interface.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines Touch Panel Interface.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef TOUCH_PANEL__H
+#define TOUCH_PANEL__H
+#include "eint.h"
+#include "intrCtrl.h"
+#include "dcl_hts.h"
+#include "kal_public_api.h"
+
+#if defined(__TOUCH_PANEL_CAPACITY__)
+#define TOUCH_PANEL_BUFFER_SIZE 512*16 //size MUST be exponential of 2
+#define CTP_SUPPORT_POINTS 5
+#define CTP_EVENT_HEADER 8
+#define BASIC_EVENT_UNIT CTP_EVENT_HEADER + 40 // size of TouchPanelMultipleEventStruct
+
+#else
+#define TOUCH_PANEL_BUFFER_SIZE 512
+#define BASIC_EVENT_UNIT 13 // 5 -> 7, for 2 more time stamp.
+#endif//#if defined(__TOUCH_PANEL_CAPACITY__)
+
+#define TOUCH_PANEL_BUFFER_HIGH_THRES TOUCH_PANEL_BUFFER_SIZE*90/100
+#define TOUCH_PANEL_BUFFER_LOW_THRES TOUCH_PANEL_BUFFER_SIZE*80/100
+#define HAND_WRITING_AREA_NUM 3
+
+#if !defined(DRV_TOUCH_PANEL_CUSTOMER_PARAMETER)
+#define MIN_PEN_MOVE_OFFSET 5
+#define HAND_WRITING_MAX_OFFSET 50
+#define NONHAND_WRITING_MAX_OFFSET 100
+#define MAX_STROKE_MOVE_OFFSET 1
+
+#if defined(TRULY_HVGA_LCM)
+#define TOUCH_PANEL_CALI_CHECK_OFFSET 12
+#else
+#define TOUCH_PANEL_CALI_CHECK_OFFSET 6
+#endif //#if defined(TRULY_HVGA_LCM)
+#endif //#if !defined(DRV_TOUCH_PANEL_CUSTOMER_PARAMETER)
+
+#define MAX_ADC_VALUE 4095
+
+#define touch_down_level LEVEL_LOW /*touch down level*/
+#define touch_up_level LEVEL_HIGH /*touch up level*/
+
+#if !defined(IRQ_TS_CODE)
+#if defined(DRV_TP_6516_AP_SETTING)
+#define IRQ_TS_CODE IRQ_TOUCHSCREEN_CODE
+#elif defined(DRV_TP_IRQ_TPC)
+#define IRQ_TS_CODE IRQ_TPC_CODE
+#else
+#define IRQ_TS_CODE IRQ_AUXADC_CODE
+#endif
+#endif//#if !defined(IRQ_TS_CODE)
+
+#define CTP_PATTERN 0xAA
+
+typedef enum {
+ CTP_NO_POINT,
+ CTP_GESTURE, //save the gesture information in one point event
+ CTP_1POINT=1,
+ CTP_2POINTS,
+ CTP_3POINTS,
+ CTP_4POINTS,
+ CTP_5POINTS,
+ CTP_6POINTS,
+ CTP_7POINTS,
+ CTP_8POINTS,
+ CTP_9POINTS,
+ CTP_10POINTS,
+ //add new detection type before unknown
+ CTP_UNKNOWN
+} CTP_EVENT_NUMBER_ENUM;
+
+typedef struct
+{
+ // Touch_Panel_Event_enum
+ kal_uint16 event;
+ /*coordinate point, not diff*/
+ kal_uint16 x;
+ kal_uint16 y;
+ kal_uint16 z; //resistance TP: presure, capacitive TP: area
+} TP_SINGLE_EVENT_T;
+
+typedef enum {
+ UP,
+ DOWN
+} Touch_Panel_PenState_enum;
+
+typedef enum {
+ CTP_LAST_EVENT_GET,
+ CTP_LAST_EVENT_SET
+} Touch_Panel_Handle_LastEvent_enum;
+
+typedef enum {
+ HAND_WRITING,
+ NON_HAND_WRITING
+} Touch_Panel_Area_enum;
+typedef enum {
+ PEN_DOWN, /*0*/
+ PEN_UP, /*1*/
+ PEN_MOVE, /*2*/
+ PEN_LONGTAP, /*3*/
+ PEN_REPEAT, /*4*/
+ PEN_ABORT, /*5*/
+ TP_UNKNOWN_EVENT,/*6*/
+ STROKE_MOVE, /*7*/
+ STROKE_STATICAL, /*8*/
+ STROKE_HOLD, /*9*/
+ PEN_LONGTAP_HOLD, /*10*/
+ PEN_REPEAT_HOLD, /*11*/
+ STROKE_DOWN_, /*12*/
+ STROKE_LONGTAP_, /*13*/
+ STROKE_UP_,/*14*/
+ STROKE_DOWN=0xc0, /*0*/ /*1*/
+ STROKE_LONGTAP=0x7e, /*8*/
+ STROKE_UP=0x7f/*127*/
+} Touch_Panel_Event_enum;
+typedef kal_uint16 (*CTP_FUNC)(kal_int16 x_diff, kal_int16 y_diff, kal_uint16 count);
+
+typedef struct
+{
+ kal_int16 x; /*x coordinate*/
+ kal_int16 y; /*y coordinate*/
+}TouchPanelCoordStruct;
+typedef struct
+{
+ TouchPanelCoordStruct min;
+ TouchPanelCoordStruct max;
+}TouchPanelHandAreaStruct;
+
+typedef struct
+{
+ /*x*/
+ double x_slope;
+ double x_offset;
+ /*y*/
+ double y_slope;
+ double y_offset;
+}TouchPanelCaliStruct ;
+typedef void (*TP_EVENT_FUNC)(void *parameter, Touch_Panel_Event_enum state) ;
+typedef struct
+{
+ kal_eventgrpid event; /*event id*/
+ kal_uint8 gpthandle; /*gpt handle*/
+ kal_uint8 eint_chan;
+ kal_uint32 longtap_cnt; /*LongTap cnt*/
+ kal_uint32 handwriting_longtap_cnt; /*LongTap cnt*/
+ kal_uint32 repeat_cnt; /*Repeat cnt*/
+ kal_uint32 low_sample_period;
+ kal_uint32 high_sample_period;
+ TouchPanelHandAreaStruct handarea[HAND_WRITING_AREA_NUM]; /*hand area*/
+ TouchPanelHandAreaStruct ext_handarea; /*extended area*/
+ kal_uint16 hand_num;
+ kal_bool ext_enable; /*extended stroke or not*/
+ TouchPanelCoordStruct cur; /*current point coord.*/
+ TouchPanelCoordStruct pre; /*previous point coord.*/
+ TouchPanelCoordStruct temp; /*previous point coord.*/
+ TouchPanelCoordStruct begin; /*the first down point coord.*/
+ TP_EVENT_FUNC touch_panel_event_cb;
+ void *cb_para;
+ Touch_Panel_Area_enum area; /*(non)handwriting*/
+ Touch_Panel_PenState_enum state; /*Down or UP*/
+ kal_bool skip_unrelease_enable;
+ kal_bool skip_unrelease_state;
+ kal_bool is_buff_full;
+ kal_bool wait_next_down; /*inidcate if the down point reasonable*/
+ kal_uint16 pen_offset; /*pen move offset*/
+ kal_uint16 longtap_pen_offset;/*longtap pen move offset*/
+ kal_uint16 longtap_stroke_offset; /*longtap stroke move offset*/
+ kal_uint16 storke_offset; /*stroke offset*/
+ kal_bool longtap_state; /*wait longtap timeout or not*/
+#if defined(DRV_TOUCH_PANEL_PAIR_GUARANTEE)
+ Touch_Panel_Event_enum buffer_push_stat;
+ TouchPanelCoordStruct buffer_push_point; /*previous point coord.*/
+#endif //#if defined(DRV_TOUCH_PANEL_PAIR_GUARANTEE)
+
+ DCL_HANDLE hts_handle;
+ PFN_DCL_CALLBACK tp_down_cb;
+ void * tp_down_cb_para;
+ PFN_DCL_CALLBACK tp_up_cb;
+ void * tp_up_cb_para;
+
+}TouchPanelDataStruct;
+
+typedef struct
+{
+ kal_int16 x_adc;
+ kal_int16 y_adc;
+ Touch_Panel_Event_enum event;
+ kal_uint16 time_stamp; // unit: system tick
+}TouchPanelEventStruct;
+
+typedef struct
+{
+ kal_uint16 model; // Single/Dual/Triple/Four/Five/All gesture
+ kal_uint16 padding; //currently use for check the structure format correctness, 0xAA
+ kal_uint32 time_stamp;
+ TP_SINGLE_EVENT_T points[5];
+} TouchPanelMultipleEventStruct;
+
+
+typedef struct
+{
+ kal_uint8 touch_panel_data[TOUCH_PANEL_BUFFER_SIZE];
+ kal_uint16 touch_buffer_rindex;
+ kal_uint16 touch_buffer_windex;
+#if defined(__TOUCH_PANEL_CAPACITY__)
+ kal_uint16 touch_buffer_last_rindex;
+ kal_uint16 touch_buffer_last_windex;
+#endif
+}TouchPanelBufferStruct;
+
+typedef struct {
+#if defined(DRV_TOUCH_PANEL_CUSTOMER_PARAMETER)
+ kal_uint32 ts_debounce_time; //TS_DEBOUNCE_TIME
+ kal_uint32 touch_panel_cali_check_offset;
+ kal_uint32 min_pen_move_offset;// MIN_PEN_MOVE_OFFSET = 10;
+ kal_uint32 hand_writing_max_offset;// HAND_WRITING_MAX_OFFSET = 50;
+ kal_uint32 nonhand_writing_max_offset;// NONHAND_WRITING_MAX_OFFSET = 100;
+ kal_uint32 max_stroke_move_offset;// MAX_STROKE_MOVE_OFFSET = 1;
+ kal_uint32 touch_pressure_threshold_high;// TOUCH_PRESSURE_THRESHOLD_HIGH=6000;
+#if defined(DRV_TOUCH_PANEL_MULTIPLE_PICK)
+ kal_uint32 multiple_point_selection;// MULTIPLE_POINT_SELECTION= 3;
+#endif //#if defined(DRV_TOUCH_PANEL_MULTIPLE_PICK)
+#if defined(__DRV_TP_DISCARD_SHIFTING__)
+ kal_uint32 pressure_check_boundary;// PRESSURE_CHECK_BOUNDARY = 2000;
+ kal_uint32 pressure_shifting_boundary;// PRESSURE_SHIFTING_BOUNDARY = 800;
+#endif //#if defined(__DRV_TP_DISCARD_SHIFTING__)
+#endif //#if defined(DRV_TOUCH_PANEL_CUSTOMER_PARAMETER)
+ kal_int32 touch_panel_filter_thresold;
+ /*ADC*/
+ kal_int32 x_adc_start;
+ kal_int32 x_adc_end;
+ kal_int32 y_adc_start;
+ kal_int32 y_adc_end;
+ /*Coord.*/
+ kal_int32 x_coord_start;
+ kal_int32 x_coord_end;
+ kal_int32 y_coord_start;
+ kal_int32 y_coord_end;
+ /*Size.*/
+ kal_int32 x_millimeter;
+ kal_int32 y_millimeter;
+ /*EINT*/
+ kal_uint8 eint_down_level;
+} TouchPanel_custom_data_struct;
+
+typedef struct {
+ TouchPanel_custom_data_struct * (*tp_get_data)(void);
+ void (*tp_read_adc)(kal_uint16 *x, kal_uint16 *y);
+#ifdef TOUCH_PANEL_PRESSURE
+ kal_bool (*tp_pressure_check)(void);
+#endif
+ void (*tp_irq_enable)(kal_bool on);
+}TouchPanel_customize_function_struct;
+
+typedef enum {
+ CTP_PARA_START,
+ CTP_PARA_RESOLUTION=1,
+ CTP_PARA_THRESHOLD=2,
+ CTP_PARA_REPORT_INTVAL=4,
+ CTP_PARA_IDLE_INTVAL=8,
+ CTP_PARA_SLEEP_INTVAL=0x10,
+ CTP_PARA_END
+} CTP_parameters_enum;
+
+typedef struct
+{
+ kal_uint16 resolution; // CTP_RESOLTION,
+ kal_uint16 threshold; // CTP_THRESHOLD,
+ kal_uint16 Report_interval;
+ kal_uint16 Idle_time_interval;
+ kal_uint16 sleep_time_interval;
+ kal_uint16 gesture_active_distance;
+ kal_uint16 MS_calibration[128];
+}CTP_parameters_struct;// ctp_get_set_enum
+
+typedef struct
+{
+ char vendor[8];
+ char product[8];
+ char FirmwareVersion[8];
+}CTP_custom_information_struct;
+
+typedef enum {
+ CTP_ACTIVE_MODE,
+ CTP_IDLE_MODE,
+ CTP_SLEEP_MODE,
+ CTP_GESTURE_DETECTION_MODE,
+ CTP_MULTIPLE_POINT_MODE,
+ CTP_FIRMWARE_UPDATE,
+ CTP_FM_ENABLE,
+ CTP_FM_DISABLE
+}ctp_device_mode_enum;
+
+typedef struct{
+ kal_bool (*ctp_init)(void);
+ kal_bool (*ctp_set_device_mode)(ctp_device_mode_enum);
+ Touch_Panel_PenState_enum (*ctp_hisr)(void);
+ kal_bool (*ctp_get_data)(TouchPanelMultipleEventStruct *);
+ kal_bool (*ctp_parameters)(CTP_parameters_struct *, kal_uint32, kal_uint32);
+ void (*ctp_power_on)(kal_bool);
+ kal_uint32 (*ctp_command)(kal_uint32, void *, void *);
+}CTP_customize_function_struct;
+
+/********************Function Declaration********************/
+/********************For upper layer*************************/
+void Touch_Panel_Ctrl_Param(DCL_CTRL_CUSTOM_PARAM_T param);
+void Touch_Panel_Ctrl_Param_Range(DCL_CTRL_CUSTOM_PARAM_RANGE_T param);
+void Touch_Panel_MicronMeter_To_Coord(DCL_CTRL_MICRONMETER_COORD_T* pparam);
+void Touch_Panel_Coord_To_MicronMeter(DCL_CTRL_MICRONMETER_COORD_T* pparam );
+
+
+void touch_panel_enable_(kal_bool enable);/*enable/disable touch panel*/
+kal_bool touch_panel_get_event_(TouchPanelMultipleEventStruct *touch_data);/*get touch event*/
+void touch_panle_conf_timeout_period_(kal_uint32 longtap,
+ kal_uint32 repeat,
+ kal_uint32 handwriting_longtap);
+void touch_panle_conf_sample_period_(kal_uint32 low, kal_uint32 high);
+void touch_panel_flush_(void);/*flsuh data in ring buffer*/
+void touch_panel_start_cali_(TouchPanelCoordStruct *point, kal_uint16 num);
+void touch_panel_stop_cali_(void);
+void touch_panel_read_cali_(TouchPanelCaliStruct *cali);
+void touch_panel_set_cali_(TouchPanelCaliStruct cali);
+void touch_panel_reset_(kal_bool skip_unrelease_enable);
+void touch_panel_reset_handwriting_(void);
+void touch_panel_conf_move_offset_(kal_uint16 pen_offset, kal_uint16 stroke_offset,
+ kal_uint16 longtap_pen_offset,
+ kal_uint16 longtap_stroke_offset);
+void touch_panel_conf_handwriting_(TouchPanelHandAreaStruct *area, kal_uint16 n,
+ TouchPanelHandAreaStruct *ext_area);
+void touch_panel_cb_registration_ (TP_EVENT_FUNC function, void *parameter);
+void Touch_Panel_Pixel_To_MicronMeter(DCL_CTRL_MICRONMETER_COORD_T* pparam);
+void Touch_Panel_MicronMeter_To_Coord(DCL_CTRL_MICRONMETER_COORD_T* pparam);
+#if defined(__TOUCH_PANEL_CAPACITY__)
+void touch_panel_capacitive_up_hdr(DCL_EVENT event);
+void touch_panel_capacitive_down_hdr(DCL_EVENT event);
+void touch_panel_capacitive_power_on(kal_bool on);
+kal_bool touch_panel_capacitive_set_device(ctp_device_mode_enum mode);
+kal_uint32 touch_panel_capacitive_command(kal_uint32 cmd, void *p1, void*p2);
+#endif //#if defined(__TOUCH_PANEL_CAPACITY__)
+/********************For touch panel driver only*************/
+// MoDIS parser skip start
+// The following are private APIs
+#ifdef TOUCH_PANEL_PRESSURE
+kal_bool tp_level(void);
+kal_bool tp_level_pressure(kal_uint32 *pressure);
+kal_uint32 tp_pressure_value(void);
+kal_bool tp_pressure_check(void);
+kal_bool tp_pressure_check_value(kal_uint32 *pressure);
+#endif //#ifdef TOUCH_PANEL_PRESSURE
+
+void touch_panel_read_adc(kal_uint16 *x, kal_uint16 *y);
+kal_bool touch_panel_adc_to_coordinate(kal_uint16 *x, kal_uint16 *y);/*tranlate*/
+void touch_panel_event_cb(void *parameter);
+void touch_panel_repeat_cb(void *parameter);
+void touch_panel_longtap_cb(void *parameter);
+void touch_panel_stroke_cb(void *parameter);
+void touch_panel_up_hdr(DCL_EVENT event);
+void touch_panel_down_hdr(DCL_EVENT event);
+void touch_panel_event_hdr(void);
+void touch_start_longtap(void);
+void touch_panel_stroke_hdr(void);
+void touch_excute_cali(kal_uint16 x_adc, kal_uint16 y_adc);
+void touch_panel_sendilm(void *para, Touch_Panel_Event_enum state);
+void tp_data_pop(Touch_Panel_Event_enum event, kal_int16 x, kal_int16 y);
+void tp_data_push(TP_SINGLE_EVENT_T* push_event);
+
+void touch_panel_init(void);
+void touch_start_handwriting_longtap(void);
+// MoDIS parser skip end
+/*variable*/
+extern TouchPanelDataStruct TP;
+extern Touch_Panel_Event_enum touch_panel_track_stauts; /*pen/stroke status*/
+extern TouchPanelBufferStruct touch_panel_data_buffer;
+extern TouchPanelCoordStruct pre_coord;
+extern TouchPanelCoordStruct tp_stroke_pre;
+
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_TP_REG_DBG__)
+#define DRV_TP_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+#define DRV_TP_Reg(addr) DRV_DBG_Reg(addr)
+#define DRV_TP_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define DRV_TP_Reg32(addr) DRV_DBG_Reg32(addr)
+#define DRV_TP_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+#define DRV_TP_Reg8(addr) DRV_DBG_Reg8(addr)
+#define DRV_TP_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+#define DRV_TP_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+#define DRV_TP_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#define DRV_TP_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+#define DRV_TP_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+#define DRV_TP_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+#define DRV_TP_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+#define DRV_TP_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+#define DRV_TP_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+#else
+#define DRV_TP_WriteReg(addr,data) DRV_WriteReg(addr,data)
+#define DRV_TP_Reg(addr) DRV_Reg(addr)
+#define DRV_TP_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define DRV_TP_Reg32(addr) DRV_Reg32(addr)
+#define DRV_TP_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+#define DRV_TP_Reg8(addr) DRV_Reg8(addr)
+#define DRV_TP_ClearBits(addr,data) DRV_ClearBits(addr,data)
+#define DRV_TP_SetBits(addr,data) DRV_SetBits(addr,data)
+#define DRV_TP_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define DRV_TP_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+#define DRV_TP_SetBits32(addr,data) DRV_SetBits32(addr,data)
+#define DRV_TP_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+#define DRV_TP_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+#define DRV_TP_SetBits8(addr,data) DRV_SetBits8(addr,data)
+#define DRV_TP_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_TP_REG_DBG__)
+#if defined(__MTK_INTERNAL__) && !defined(__MAUI_BASIC__) && defined(__DRV_DBG_MEMORY_TRACE_SUPPORT__) && defined(__DRV_TP_MEMORY_TRACE__)
+typedef struct{
+ kal_uint16 tag;
+ kal_uint32 time;
+ kal_uint32 data1;
+ kal_uint32 data2;
+}TP_DRV_DBG_DATA;
+#define MAX_TP_DRV_DBG_INFO_SIZE 16
+typedef struct{
+ TP_DRV_DBG_DATA dbg_data[MAX_TP_DRV_DBG_INFO_SIZE];
+ kal_uint16 dbg_data_idx;
+}TP_DRV_DBG_STRUCT;
+extern void tp_drv_dbg_trace(kal_uint16 index, kal_uint32 time, kal_uint32 data1, kal_uint32 data2);
+#define TP_DBG(a,b,c,d) tp_drv_dbg_trace(a,b,c,d);
+#include "us_timer.h"
+extern kal_uint32 L1I_GetTimeStamp(void);
+#define TP_GetTimeStamp L1I_GetTimeStamp
+#else //#if defined(__MTK_INTERNAL__) && !defined(LOW_COST_SUPPORT)
+#define TP_DBG(a,b,c,d) ;
+#endif //#if defined(__MTK_INTERNAL__) && !defined(LOW_COST_SUPPORT)
+#endif
+
diff --git a/mcu/driver/peripheral/inc/touch_panel_buff.h b/mcu/driver/peripheral/inc/touch_panel_buff.h
new file mode 100644
index 0000000..8ef3379
--- /dev/null
+++ b/mcu/driver/peripheral/inc/touch_panel_buff.h
@@ -0,0 +1,90 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * serial_interface.c
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines Touch Panel Interface.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef TOUCH_PANEL_BUFF_H
+#define TOUCH_PANEL_BUFF_H
+#include "touch_panel.h"
+#include "kal_public_api.h"
+
+void tp_get_buf_roomleft_(kal_uint16* pleft);
+void tp_get_buf_avail_(kal_uint16* pleft);
+void touhc_push_data_to_buffer(kal_uint8 _data, kal_uint8 _state) ;
+void touch_pop_data_from_buffer_(kal_uint8*pdata) ;
+void touch_peek_data_from_buffer(kal_uint8*_ptr, kal_uint8 _num);
+void touch_flush_data_buffer(void);
+
+
+#define tp_get_buf_roomleft(_left) \
+{\
+ tp_get_buf_roomleft_(&_left);\
+}
+
+#define tp_get_buf_avail(_left) \
+{\
+ tp_get_buf_avail_(&_left);\
+}
+
+#define touch_pop_data_from_buffer(_data)\
+{\
+ touch_pop_data_from_buffer_(&_data);\
+}
+
+#endif
diff --git a/mcu/driver/peripheral/inc/touch_panel_trc.h b/mcu/driver/peripheral/inc/touch_panel_trc.h
new file mode 100644
index 0000000..f12d9c8
--- /dev/null
+++ b/mcu/driver/peripheral/inc/touch_panel_trc.h
@@ -0,0 +1,133 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * touch_panel_trc.h
+ *
+ * Project:
+ * --------
+ * MAUI
+ *
+ * Description:
+ * ------------
+ * This is trace map definition for touch panel driver
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ ****************************************************************************/
+#ifndef _TP_TRC_H
+#define _TP_TRC_H
+
+
+#ifndef GEN_FOR_PC
+
+ #ifndef _STACK_CONFIG_H
+ #error "stack_config.h should be included before tst_config.h"
+ #endif
+
+#else
+ #include "kal_trace.h"
+#endif /* GEN_FOR_PC */
+
+
+#ifndef _KAL_TRACE_H
+ #error "kal_trace.h should be included before tst_trace.h"
+#endif
+
+#if !defined(GEN_FOR_PC)
+#if defined(__TST_MODULE__) || defined(__CUSTOM_RELEASE__)
+ #include "touch_panel_trc_gen.h"
+#endif /* TST Trace Defintion */
+#endif
+BEGIN_TRACE_MAP(MOD_TP_TASK)
+
+ TRC_MSG(TP_HISR_DOWN,"TP HISR Down")
+ TRC_MSG(TP_HISR_UP,"TP HISR UP")
+ TRC_MSG(TP_DOWN_HDR,"TP down handler")
+ TRC_MSG(TP_UP_HDR,"TP up handler")
+ TRC_MSG(TP_STAT,"TP stat: %d")
+
+ TRC_MSG(TP_UP_INTR_LOST,"TP up intr lost")
+ TRC_MSG(TP_DOWN_INTR_LOST,"TP down intr lost")
+
+ TRC_MSG(TP_PRESSURE_RESULT,"TP pressure result: %d")
+ TRC_MSG(TP_PRESSURE_VALUE,"TP pressure value: pressure: %d, x: %d, z1: %d, z2: %d")
+
+ TRC_MSG(TP_ADC_VALUE,"TP ADC value: x: %d, y: %d")
+ TRC_MSG(TP_VALID_COORD_VALUE,"TP valid coord value: x: %d, y: %d")
+ TRC_MSG(TP_CUSTOM_SETTING,"TP custom setting: ADC_X_Start: %d, ADC_X_End: %d, ADC_Y_Start: %d, ADC_Y_End: %d, ScreenX_Start: %d, ScreenX_End: %d, ScreenY_Start: %d, ScreenY_End: %d")
+ TRC_MSG(TP_INVALID_COORD_VALUE,"TP invalid coord value: ScreenX_Start: %d, ScreenX_End: %d, ScreenY_Start: %d, ScreenY_End: %d, x: %d, y: %d")
+ TRC_MSG(TP_WAIT_NEXT_TRUE,"TP wait next is TRUE, just return")
+ TRC_MSG(TP_WAIT_NEXT_SET_TRUE,"TP wait next is set to TRUE!!!!")
+ TRC_MSG(TP_FLUSH,"TP flush all data")
+ TRC_MSG(TP_RESET,"TP reset")
+ TRC_MSG(TP_EXCEED_PENMOVE,"TP exceed penmove: %d")
+
+ TRC_MSG(TP_CONF_SAMPLE_PERIOD,"TP config sample period: low: %d, high: %d")
+ TRC_MSG(TP_CONF_TIMEOUT_PERIOD,"TP config timeout period: longtap: %d, repeat: %d, handwriting_longtap: %d")
+ TRC_MSG(TP_CONF_MOVE_OFFSET,"TP config move offset: pen_offset: %d, stroke_offset: %d, longtap_pen_offset: %d, longtap_stroke_offset: %d")
+
+ TRC_MSG(TP_GET_EVENT,"TP get_event: event: %d, x: %d, y: %d")
+ TRC_MSG(TP_PEEK_EVENT,"TP get_event: event: %d, x: %d, y: %d")
+
+ // Stroke
+ TRC_MSG(TP_STROKE_UP,"TP stroke up")
+ TRC_MSG(TP_STROKE_MOVE,"TP stroke move x: %d, y: %d")
+
+ // Pen
+ TRC_MSG(TP_PEN_UP,"TP pen up")
+ TRC_MSG(TP_PEN_LONGTAP,"TP longtap x: %d, y: %d")
+ TRC_MSG(TP_PEN_REPEAT,"TP repeat x: %d, y: %d")
+ TRC_MSG(TP_PEN_MOVE,"TP move x: %d, y: %d")
+
+
+
+ // Calibration messages
+ TRC_MSG(TP_CALI_FORCE_VALID_COORD_VALUE,"TP cali mode force validate coord value")
+ TRC_MSG(TP_CALI_ADC_DIFF,"TP cali ADC diff: x_diff: %d, x_diff_high: %d, x_diff_low: %d, y_diff: %d, y_diff_high: %d, y_diff_low: %d")
+ TRC_MSG(TP_CALI_1ST_ADC,"TP 1st adc: x: %d, y: %d")
+ TRC_MSG(TP_CALI_2ND_ADC,"TP 2nd adc: x: %d, y: %d")
+ TRC_MSG(TP_CALI_RESULT,"TP cali formula: x_slope: %d, x_offset: %d, y_slope: %d, y_offset: %d, result: %d")
+
+
+END_TRACE_MAP(MOD_TP_TASK)
+
+#endif /* _TP_TRC_H */
+
+
diff --git a/mcu/driver/peripheral/inc/ts_hw.h b/mcu/driver/peripheral/inc/ts_hw.h
new file mode 100644
index 0000000..c3ea3f0
--- /dev/null
+++ b/mcu/driver/peripheral/inc/ts_hw.h
@@ -0,0 +1,192 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * tp_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for GPT driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef TP_HW_H
+#define TP_HW_H
+#include "drv_features.h"
+#include "drv_comm.h"
+#if defined(DRV_ADC_TOUCH_SCREEN)
+#if !defined(DRV_TS_OFF)
+
+#if defined(DRV_ADC_OFF)
+#error "ADC module should exist!! "
+#endif
+#include "reg_base.h"
+ #ifdef DRV_ADC_TOUCH_SCREEN_OFFSET_0X50
+ #define AUX_TS_DEBT (AUXADC_base+0x0050)
+ #define AUX_TS_CMD (AUXADC_base+0x0054)
+ #define AUX_TS_CON (AUXADC_base+0x0058)
+ #define AUX_TS_DATA0 (AUXADC_base+0x005c)
+ #else // #ifdef DRV_ADC_TOUCH_SCREEN_OFFSET_0X50
+ #define AUX_TS_DEBT (AUXADC_base+0x0030)
+ #define AUX_TS_CMD (AUXADC_base+0x0034)
+ #define AUX_TS_CON (AUXADC_base+0x0038)
+ #define AUX_TS_DATA0 (AUXADC_base+0x003c)
+ #endif // #ifdef DRV_ADC_TOUCH_SCREEN_OFFSET_0X50
+
+#endif /*#if !defined(DRV_TS_OFF)*/
+
+#define TS_DEBT_MASK 0x3fff
+
+#define TS_CMD_PD_MASK 0x0003
+ #define TS_CMD_PD_YDRV_SH 0x0000
+ #define TS_CMD_PD_IRQ_SH 0x0001
+ #define TS_CMD_PD_IRQ 0x0003
+#define TS_CMD_SE_DF_MASK 0x0004
+ #define TS_CMD_DIFFERENTIAL 0x0000
+ #define TS_CMD_SINGLE_END 0x0004
+#define TS_CMD_MODE_MASK 0x0008
+ #define TS_CMD_MODE_10BIT 0x0000
+ #define TS_CMD_MODE_8BIT 0x0008
+#define TS_CMD_ADDR_MASK 0x0070
+ #define TS_CMD_ADDR_Y 0x0010
+ #define TS_CMD_ADDR_Z1 0x0030
+ #define TS_CMD_ADDR_Z2 0x0040
+ #define TS_CMD_ADDR_X 0x0050
+
+#define TS_CON_SPL_MASK 0x0001
+
+#if defined(DRV_TP_PENUP_FIXED)
+ #define TS_CON_SPL_TRIGGER 0x8001
+ #else
+ #define TS_CON_SPL_TRIGGER 0x0001
+#endif
+
+#define TS_CON_STATUS_MASK 0x0002
+
+#define TS_DAT0_DAT_MASK 0x03ff
+
+#if defined(DRV_TP_SPL_NUM_ABB_1708)
+#define AUX_SPL_NUM (PLL_base+0x1708)
+#define AUX_SPL_NUM_SHIFT 8
+#define AUX_SPL_NUM_MASK 0xFF00
+
+#elif defined(DRV_TP_SPL_NUM_ABB_8708)
+#define AUX_SPL_NUM (ABBSYS_base+0x8708)
+#define AUX_SPL_NUM_SHIFT 8
+#define AUX_SPL_NUM_MASK 0xFF00
+
+#else
+#define AUX_SPL_NUM 0
+#define AUX_SPL_NUM_SHIFT 0
+#define AUX_SPL_NUM_MASK 0
+#endif//#if defined(DRV_TP_SPL_NUM_ABB_1708)
+
+#if !defined(DRV_TS_OFF)
+
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_TP_REG_DBG__)
+#define DRV_TP_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+#define DRV_TP_Reg(addr) DRV_DBG_Reg(addr)
+#define DRV_TP_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define DRV_TP_Reg32(addr) DRV_DBG_Reg32(addr)
+#define DRV_TP_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+#define DRV_TP_Reg8(addr) DRV_DBG_Reg8(addr)
+#define DRV_TP_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+#define DRV_TP_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+#define DRV_TP_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#define DRV_TP_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+#define DRV_TP_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+#define DRV_TP_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+#define DRV_TP_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+#define DRV_TP_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+#define DRV_TP_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+#else
+#define DRV_TP_WriteReg(addr,data) DRV_WriteReg(addr,data)
+#define DRV_TP_Reg(addr) DRV_Reg(addr)
+#define DRV_TP_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define DRV_TP_Reg32(addr) DRV_Reg32(addr)
+#define DRV_TP_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+#define DRV_TP_Reg8(addr) DRV_Reg8(addr)
+#define DRV_TP_ClearBits(addr,data) DRV_ClearBits(addr,data)
+#define DRV_TP_SetBits(addr,data) DRV_SetBits(addr,data)
+#define DRV_TP_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define DRV_TP_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+#define DRV_TP_SetBits32(addr,data) DRV_SetBits32(addr,data)
+#define DRV_TP_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+#define DRV_TP_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+#define DRV_TP_SetBits8(addr,data) DRV_SetBits8(addr,data)
+#define DRV_TP_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_TP_REG_DBG__)
+
+#else //!defined(DRV_TS_OFF)
+
+#define DRV_TP_WriteReg(addr,data)
+#define DRV_TP_Reg(addr) drv_dummy_return()
+#define DRV_TP_WriteReg32(addr,data)
+#define DRV_TP_Reg32(addr) drv_dummy_return()
+#define DRV_TP_WriteReg8(addr,data)
+#define DRV_TP_Reg8(addr) drv_dummy_return()
+#define DRV_TP_ClearBits(addr,data)
+#define DRV_TP_SetBits(addr,data)
+#define DRV_TP_SetData(addr, bitmask, value)
+#define DRV_TP_ClearBits32(addr,data)
+#define DRV_TP_SetBits32(addr,data)
+#define DRV_TP_SetData32(addr, bitmask, value)
+#define DRV_TP_ClearBits8(addr,data)
+#define DRV_TP_SetBits8(addr,data)
+#define DRV_TP_SetData8(addr, bitmask, value)
+
+#endif //!defined(DRV_TS_OFF)
+
+#endif /*defined(DRV_ADC_TOUCH_SCREEN)*/
+
+#endif /*TP_HW_H*/
+
diff --git a/mcu/driver/peripheral/inc/uart_hw.h b/mcu/driver/peripheral/inc/uart_hw.h
new file mode 100644
index 0000000..798ddeb
--- /dev/null
+++ b/mcu/driver/peripheral/inc/uart_hw.h
@@ -0,0 +1,746 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * uart_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for UART driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef UART_HW_H
+#define UART_HW_H
+//#include "drv_features.h"
+/*#define SLEEP_DONT_CARE_DBG_INFO */
+#include "dma_hw.h"
+#include "drv_comm.h"
+#if !defined(DRV_UART_OFF)
+/*UART1 MMP address, UART1_base = 0x80130000, UART2_base = 0x80180000,, UART3_base = 0x801b0000*/
+/*used in Task or normal function*/
+#define UART_RBR(_baseaddr) (_baseaddr+0x0) /* Read only */
+#define UART_THR(_baseaddr) (_baseaddr+0x0) /* Write only */
+#define UART_IER(_baseaddr) (_baseaddr+0x4)
+#define UART_IIR(_baseaddr) (_baseaddr+0x8) /* Read only */
+#define UART_FCR(_baseaddr) (_baseaddr+0x8) /* Write only */
+#define UART_LCR(_baseaddr) (_baseaddr+0xc)
+#define UART_MCR(_baseaddr) (_baseaddr+0x10)
+#define UART_LSR(_baseaddr) (_baseaddr+0x14)
+#define UART_MSR(_baseaddr) (_baseaddr+0x18)
+#define UART_SCR(_baseaddr) (_baseaddr+0x1c)
+#define UART_DLL(_baseaddr) (_baseaddr+0x0)
+#define UART_DLH(_baseaddr) (_baseaddr+0x4)
+#define UART_EFR(_baseaddr) (_baseaddr+0x8) /* Only when LCR = 0xbf */
+#define UART_XON1(_baseaddr) (_baseaddr+0x10) /* Only when LCR = 0xbf */
+#define UART_XON2(_baseaddr) (_baseaddr+0x14) /* Only when LCR = 0xbf */
+#define UART_XOFF1(_baseaddr) (_baseaddr+0x18) /* Only when LCR = 0xbf */
+#define UART_XOFF2(_baseaddr) (_baseaddr+0x1c) /* Only when LCR = 0xbf */
+#define UART_FRACDIV_L(_baseaddr) (_baseaddr+0x54)
+#define UART_FRACDIV_M(_baseaddr) (_baseaddr+0x58)
+
+#if defined(DRV_UART_FCR_RD)
+#define UART_FCR_RD(_baseaddr) (_baseaddr+0x5C) /* Read only */
+#endif
+
+#if defined(DRV_UART_TX_ACTIVE)
+#define UART_TX_ACTIVE_EN(_baseaddr) (_baseaddr+0x5C)
+#endif
+
+#ifdef DRV_UART_6205B_REG
+ #define UART_RATE_STEP(_baseaddr) (_baseaddr+0x20)
+ #define UART_STEP_COUNT(_baseaddr) (_baseaddr+0x24)
+ #define UART_SAMPLE_COUNT(_baseaddr) (_baseaddr+0x28)
+#endif /*DRV_UART_6205B_REG*/
+#if 0
+#ifdef MT6217/*TY add this 10/01/2004,*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif /*MT6217*/
+#endif
+#if defined(DRV_UART_BASIC_REG)
+ #define UART_AUTOBAUD_EN(_baseaddr) (_baseaddr+0x20)
+ #define UART_RATE_STEP(_baseaddr) (_baseaddr+0x24)
+ #define UART_STEP_COUNT(_baseaddr) (_baseaddr+0x28)
+ #define UART_SAMPLE_COUNT(_baseaddr) (_baseaddr+0x2c)
+ #define UART_AUTOBAUD_REG(_baseaddr) (_baseaddr+0x30)
+ #define UART_RATE_FIX_REG(_baseaddr) (_baseaddr+0x34)
+ #define UART_AUTO_BAUDSAMPLE(_baseaddr) (_baseaddr+0x38)
+ #define UART_GUARD(_baseaddr) (_baseaddr+0x3C)
+ #define UART_ESCAPE_DAT(_baseaddr) (_baseaddr+0x40)
+ #define UART_ESCAPE_EN(_baseaddr) (_baseaddr+0x44)
+ #define UART_SLEEP_EN(_baseaddr) (_baseaddr+0x48)
+#endif /*DRV_UART_BASIC_REG*/
+#if defined(DRV_UART_VFIFO_EN_REG)
+ #define UART_RXDMA(_baseaddr) (_baseaddr+0x4c)
+#endif
+#define UART_RXTRI(_baseaddr) (_baseaddr+0x50)
+
+
+//IER
+#if defined(DRV_UART_FIFO_FLOW_CONTROL)
+#define UART_IER_ERBFI 0x0001
+#define UART_IER_ETBEI 0x0002
+#define UART_IER_ELSI 0x0004
+#define UART_IER_EDSSI 0x0008
+#define UART_IER_VFF_FC_EN 0x0010
+#define UART_IER_XOFFI 0x0020
+#define UART_IER_RTSI 0x0040
+#define UART_IER_CTSI 0x0080
+
+#ifdef DRV_UART_6208_REG
+ #define UART1_IER_HW_NORMALINTS 0x001d
+ #define UART1_IER_HW_ALLINTS 0x001f
+ #define UART1_IER_SW_NORMALINTS 0x003d
+ #define UART1_IER_SW_ALLINTS 0x003f
+ /*Disable MSR interrupt*/
+ #define UART2_IER_HW_NORMALINTS 0x0015
+ #define UART2_IER_HW_ALLINTS 0x0017
+ #define UART2_IER_SW_NORMALINTS 0x0035
+ #define UART2_IER_SW_ALLINTS 0x0037
+#endif /*DRV_UART_6208_REG*/
+#if defined(DRV_UART_6205_REG) || defined(DRV_UART_6205B_REG) || defined(FPGA)|| defined(DRV_UART_BASIC_REG)
+ #define IER_HW_NORMALINTS 0x001d
+ #define IER_HW_ALLINTS 0x001f
+ #define IER_SW_NORMALINTS 0x003d
+ #define IER_SW_ALLINTS 0x003f
+#endif /*DRV_UART_6205_REG, DRV_UART_6205B_REG, FPGA, DRV_UART_BASIC_REG*/
+#define UART_IER_ALLOFF 0x0010 //because of UART_IER_VFF_FC_EN not one of interrupt masks
+#define UART_IER_VFIFO 0x0011
+#else //#if defined(DRV_UART_FIFO_FLOW_CONTROL)
+#define UART_IER_ERBFI 0x0001
+#define UART_IER_ETBEI 0x0002
+#define UART_IER_ELSI 0x0004
+#define UART_IER_EDSSI 0x0008
+#define UART_IER_VFF_FC_EN 0x0010
+#define UART_IER_XOFFI 0x0020
+#define UART_IER_RTSI 0x0040
+#define UART_IER_CTSI 0x0080
+
+#ifdef DRV_UART_6208_REG
+ #define UART1_IER_HW_NORMALINTS 0x000d
+ #define UART1_IER_HW_ALLINTS 0x000f
+ #define UART1_IER_SW_NORMALINTS 0x002d
+ #define UART1_IER_SW_ALLINTS 0x002f
+ /*Disable MSR interrupt*/
+ #define UART2_IER_HW_NORMALINTS 0x0005
+ #define UART2_IER_HW_ALLINTS 0x0007
+ #define UART2_IER_SW_NORMALINTS 0x0025
+ #define UART2_IER_SW_ALLINTS 0x0027
+#endif /*DRV_UART_6208_REG*/
+#if defined(DRV_UART_6205_REG) || defined(DRV_UART_6205B_REG) || defined(FPGA)|| defined(DRV_UART_BASIC_REG)
+ #define IER_HW_NORMALINTS 0x000d
+ #define IER_HW_ALLINTS 0x000f
+ #define IER_SW_NORMALINTS 0x002d
+ #define IER_SW_ALLINTS 0x002f
+#endif /*DRV_UART_6205_REG, DRV_UART_6205B_REG, FPGA, DRV_UART_BASIC_REG*/
+
+#define UART_IER_ALLOFF 0x0000
+#define UART_IER_VFIFO 0x0001
+#endif //#if defined(DRV_UART_FIFO_FLOW_CONTROL)
+
+
+
+
+
+
+#if defined(DRV_UART_6205B_REG) || defined(DRV_UART_BASIC_REG)
+ #define UART_RATE_STEP_16 0x0000 /* baud = clock/UART_RATE_STEP/divisor */
+ #define UART_RATE_STEP_8 0x0001
+ #define UART_RATE_STEP_4 0x0002
+ #define UART_RATE_STEP_COUNT 0x0003 /* baud = clock/UART_RATE_STEP_COUNT */
+ #define UART_STEP_COUNT_MASK 0x00ff
+ #define UART_SAMPLE_COUNT_MASK 0x00ff
+#endif /*DRV_UART_6205B_REG, DRV_UART_BASIC_REG*/
+
+//FCR
+#define UART_FCR_FIFOEN 0x0001
+#define UART_FCR_CLRR 0x0002
+#define UART_FCR_CLRT 0x0004
+#define UART_FCR_FIFOINI 0x0007
+#define UART_FCR_RX1Byte_Level 0x0000
+#define UART_FCR_RX16Byte_Level 0x0040
+#define UART_FCR_RX32Byte_Level 0x0080
+#define UART_FCR_RX62Byte_Level 0x00c0
+
+#define UART_FCR_TX1Byte_Level 0x0000
+#define UART_FCR_TX16Byte_Level 0x0010
+#define UART_FCR_TX32Byte_Level 0x0020
+#define UART_FCR_TX62Byte_Level 0x0030
+#if ( (defined(SLEEP_DONT_CARE_DBG_INFO)) || (!defined(__MTK_INTERNAL__)) )
+ #if defined(DRV_UART_6205_REG) || defined(FPGA)
+ #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX1Byte_Level | UART_FCR_FIFOINI)
+ #define UART_FCR_RX_Normal (UART_FCR_RX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART1_TxFIFO_DEPTH 16
+ #define UART1_RxFIFO_DEPTH 16
+ #define UART2_TxFIFO_DEPTH 4
+ #define UART2_RxFIFO_DEPTH 16
+ #endif /*DRV_UART_6205B_REG,FPGA*/
+
+ #if defined(DRV_UART_BASIC_REG)
+ #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI)
+ #define UART_FCR_RX_Normal (UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART1_TxFIFO_DEPTH 16
+ #define UART1_RxFIFO_DEPTH 24
+ #define UART2_TxFIFO_DEPTH 4
+ #define UART2_RxFIFO_DEPTH 24
+ #if defined(DRV_UART_FIFO_FLOW_CONTROL) //Use larger size of RX FIFO, because it can trigger flow control
+ #define UART_VFIFO_DEPTH (UART_FCR_FIFOINI | UART_FCR_RX16Byte_Level)
+ #else
+ #define UART_VFIFO_DEPTH 7
+ #endif
+ #endif /*DRV_UART_BASIC_REG*/
+
+ #ifdef DRV_UART_6205B_REG
+ #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI)
+ #define UART_FCR_RX_Normal (UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART1_TxFIFO_DEPTH 16
+ #define UART1_RxFIFO_DEPTH 24
+ #define UART2_TxFIFO_DEPTH 4
+ #define UART2_RxFIFO_DEPTH 24
+ #endif /*DRV_UART_6205B_REG*/
+
+ #ifdef DRV_UART_6208_REG
+ #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX32Byte_Level | UART_FCR_FIFOINI)
+ #define UART_FCR_RX_Normal (UART_FCR_RX32Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART_TxFIFO_DEPTH 64
+ #define UART_RxFIFO_DEPTH 32
+ #endif /*DRV_UART_6208_REG*/
+#else /*!SLEEP_DONT_CARE_DBG_INFO*/
+ #if defined(DRV_UART_6205_REG) || defined(FPGA)
+ #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX1Byte_Level | UART_FCR_FIFOINI)
+ #define UART_FCR_RX_Normal (UART_FCR_RX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART1_TxFIFO_DEPTH 16
+ #define UART1_RxFIFO_DEPTH 16
+ #define UART2_TxFIFO_DEPTH 4
+ #define UART2_RxFIFO_DEPTH 16
+ #endif /*DRV_UART_6205_REG,FPGA*/
+
+ #if defined(DRV_UART_BASIC_REG)
+ #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI)
+ #define UART_FCR_RX_Normal (UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART1_TxFIFO_DEPTH 16
+ #define UART1_RxFIFO_DEPTH 24
+ #define UART2_TxFIFO_DEPTH 4
+ #define UART2_RxFIFO_DEPTH 24
+ #if defined(DRV_UART_FIFO_FLOW_CONTROL) //Use larger size of RX FIFO, because it can trigger flow control
+ #define UART_VFIFO_DEPTH (UART_FCR_FIFOINI | UART_FCR_RX16Byte_Level)
+ #else
+ #define UART_VFIFO_DEPTH 7
+ #endif
+ #endif /*DRV_UART_BASIC_REG*/
+
+ #ifdef DRV_UART_6205B_REG
+ #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI)
+ #define UART_FCR_RX_Normal (UART_FCR_RX16Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART1_TxFIFO_DEPTH 16
+ #define UART1_RxFIFO_DEPTH 24
+ #define UART2_TxFIFO_DEPTH 4
+ #define UART2_RxFIFO_DEPTH 24
+ #endif /*DRV_UART_6205B_REG*/
+
+ #ifdef DRV_UART_6208_REG
+ #define UART_FCR_Normal (UART_FCR_TX1Byte_Level | UART_FCR_RX32Byte_Level | UART_FCR_FIFOINI)
+ #define UART_FCR_RX_Normal (UART_FCR_RX32Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART_FCR_TX_Normal (UART_FCR_TX1Byte_Level | UART_FCR_FIFOINI) //VFIFO single channel
+ #define UART_TxFIFO_DEPTH 64
+ #define UART_RxFIFO_DEPTH 32
+ #endif /*DRV_UART_6208_REG*/
+#endif /*SLEEP_DONT_CARE_DBG_INFO*/
+
+//IIR,RO
+#define UART_IIR_INT_INVALID 0x0001
+#define UART_IIR_RLS 0x0006 // Receiver Line Status
+#define UART_IIR_RDA 0x0004 // Receive Data Available
+#define UART_IIR_CTI 0x000C // Character Timeout Indicator
+#define UART_IIR_THRE 0x0002 // Transmit Holding Register Empty
+#define UART_IIR_MS 0x0000 // Check Modem Status Register
+#define UART_IIR_SWFlowCtrl 0x0010 // Receive XOFF characters
+#define UART_IIR_HWFlowCtrl 0x0020 // CTS or RTS Rising Edge
+#define UART_IIR_FIFOS_ENABLED 0x00c0
+#define UART_IIR_NO_INTERRUPT_PENDING 0x0001
+#define UART_IIR_INT_MASK 0x001f
+
+//===============================LCR================================
+//WLS
+#define UART_WLS_8 0x0003
+#define UART_WLS_7 0x0002
+#define UART_WLS_6 0x0001
+#define UART_WLS_5 0x0000
+#define UART_DATA_MASK 0x0003
+
+//Parity
+#define UART_NONE_PARITY 0x0000
+#define UART_ODD_PARITY 0x0008
+#define UART_EVEN_PARITY 0x0018
+#define UART_MARK_PARITY 0x0028
+#define UART_SPACE_PARITY 0x0038
+#define UART_PARITY_MASK 0x0038
+
+//Stop bits
+#define UART_1_STOP 0x0000
+#define UART_1_5_STOP 0x0004 // Only valid for 5 data bits
+#define UART_2_STOP 0x0004
+#define UART_STOP_MASK 0x0004
+
+#define UART_LCR_DLAB 0x0080
+#define UART_LCR_BREAK 0x0040
+//===============================LCR================================
+
+//MCR
+#define UART_MCR_DTR 0x0001
+#define UART_MCR_RTS 0x0002
+#define UART_MCR_LOOPB 0x0010
+#define UART_MCR_IRE 0x0040 //Enable IrDA modulation/demodulation
+#define UART_MCR_XOFF 0x0080
+#define UART_MCR_Normal (UART_MCR_DTR | UART_MCR_RTS)
+#define UART_MCR_DCM_EN 0x0020
+
+
+//LSR
+#define UART_LSR_DR 0x0001
+#define UART_LSR_OE 0x0002
+#define UART_LSR_PE 0x0004
+#define UART_LSR_FE 0x0008
+#define UART_LSR_BI 0x0010
+#define UART_LSR_THRE 0x0020
+#define UART_LSR_TEMT 0x0040
+#define UART_LSR_FIFOERR 0x0080
+
+//MSR
+#define UART_MSR_DCTS 0x0001
+#define UART_MSR_DDSR 0x0002
+#define UART_MSR_TERI 0x0004
+#define UART_MSR_DDCD 0x0008
+#define UART_MSR_CTS 0x0010
+#define UART_MSR_DSR 0x0020
+#define UART_MSR_RI 0x0040
+#define UART_MSR_DCD 0x0080
+
+//DLL
+//DLM
+//EFR
+#define UART_EFR_AutoCTS 0x0080
+#define UART_EFR_AutoRTS 0x0040
+#define UART_EFR_Enchance 0x0010
+#define UART_EFR_SWCtrlMask 0x000f
+#define UART_EFR_NoSWFlowCtrl 0x0000
+#define UART_EFR_ALLOFF 0x0000
+#define UART_EFR_AutoRTSCTS 0x00c0
+
+#if defined(DRV_UART_FIFO_FLOW_CONTROL) //add 0x10 RX FIFO flow control in all values.
+//Tx/Rx XON1/Xoff1 as flow control word
+#define UART_EFR_SWFlowCtrlX1 0x001a
+//Tx/Rx XON2/Xoff2 as flow control word
+#define UART_EFR_SWFlowCtrlX2 0x0015
+//Tx/Rx XON1&XON2/Xoff1&Xoff2 as flow control word
+#define UART_EFR_SWFlowCtrlXAll 0x001f
+#else //#if defined(DRV_UART_FIFO_FLOW_CONTROL)
+#define UART_EFR_SWFlowCtrlX1 0x000a
+#define UART_EFR_SWFlowCtrlX2 0x0005
+#define UART_EFR_SWFlowCtrlXAll 0x000f
+#endif//#if defined(DRV_UART_FIFO_FLOW_CONTROL)
+
+/*AutoBaud*/
+#if defined(DRV_UART_BASIC_REG)
+#define AUTOBAUD_EN 0x1
+#define AUTOBAUDSAMPLE_13M 0x6
+#define AUTOBAUDSAMPLE_26M 0xd
+#define AUTOBAUDSAMPLE_52M 0x1b
+#define AUTOBAUDSAMPLE_15_36M 0x7
+#define AUTOBAUDSAMPLE_30_72M 0xf
+#define AUTOBAUDSAMPLE_61_44M 0x1f
+#endif /*MDRV_UART_BASIC_REG*/
+
+#if defined(DRV_UART_VFIFO_EN_REG)
+ #if defined(DRV_UART_DMA_EXTEND)
+#define UART_RX_DMA_EN 0x0001
+#define UART_TX_DMA_EN 0x0002
+#define UART_TO_CNT_AUTORST 0x0004
+#if defined(DRV_UART_DMA_INTERNAL_BUFFER_WORKAROUND) || defined( DRV_UART_NEW_UART_AND_OLG_DMA )
+#define UART_TXRXDMA_ON 0x0003
+#else
+#define UART_TXRXDMA_ON 0x0007
+#endif
+ #else
+#define UART_TXRXDMA_ON 0x0001
+ #endif
+#define UART_TXRXDMA_OFF 0x0000
+#endif /*DRV_UART_VFIFO_EN_REG*/
+
+
+#if defined(DRV_UART_AUTOBAUD_61M)
+ #if defined(MCU_650M) || defined(MCU_611M) || defined(MCU_520M)||defined(MCU_416M)//add 416M for 76M
+#define UART_RATE_FIX 0x1f
+#define UART_RATE_UNFIX 0x10
+ #else
+#define UART_RATE_FIX 0xf
+#define UART_RATE_UNFIX 0x0
+ #endif
+#else
+#define UART_RATE_FIX 0xf
+#define UART_RATE_UNFIX 0x0
+#endif
+
+
+
+#define UART_RXTRI_VALUE 0x12
+#if defined(DRV_UART_VFIFO_V2)
+
+#ifdef DMA_POP
+#undef DMA_POP
+#endif
+
+#ifdef DMA_PUSH
+#undef DMA_PUSH
+#endif
+
+#define DMA_POP(_n) DRV_Reg8(DRV_Reg(DMA_VFF_RPT(_n))+DRV_Reg32(DMA_SRC(_n)));\
+ if(DRV_Reg(DMA_VFF_RPT(_n)) == (DRV_Reg(DMA_VFF_SIZE(_n))-1))\
+ DRV_WriteReg32(DMA_VFF_RPT(_n), (~DRV_Reg32(DMA_VFF_RPT(_n)))&0x10000);\
+ else \
+ DRV_WriteReg32(DMA_VFF_RPT(_n), DRV_Reg32(DMA_VFF_RPT(_n))+1);
+
+#define DMA_PUSH(_n,_data) while(DRV_Reg(DMA_W_INT_BUF_SIZE(_n))>=64);*(volatile kal_uint8*)DMA_VPORT(_n) = (kal_uint8)_data;
+#define DMA_PUSH32(_n,_data) while(DRV_Reg(DMA_W_INT_BUF_SIZE(_n))>60);*(volatile kal_uint32*)DMA_VPORT(_n) = (kal_uint32)_data;
+
+#endif //#if defined(DRV_UART_VFIFO_V2)
+
+#if defined(DRV_UART_VFIFO_V3)
+
+#ifdef DMA_POP
+#undef DMA_POP
+#endif
+
+#ifdef DMA_PUSH
+#undef DMA_PUSH
+#endif
+
+#define DMA_POP(_n) DRV_Reg8(DRV_Reg(DMA_VFF_RPT(_n))+DRV_Reg32(DMA_SRC(_n)));\
+ if(DRV_Reg(DMA_VFF_RPT(_n)) == (DRV_Reg(DMA_VFF_SIZE(_n))-1))\
+ DRV_WriteReg32(DMA_VFF_RPT(_n), (~DRV_Reg32(DMA_VFF_RPT(_n)))&0x10000);\
+ else \
+ DRV_WriteReg32(DMA_VFF_RPT(_n), DRV_Reg32(DMA_VFF_RPT(_n))+1);
+
+#define DMA_PUSH(_n,_data) \
+ DRV_WriteReg8(DRV_Reg(DMA_VFF_WPT(_n))+DRV_Reg32(DMA_SRC(_n)),_data);\
+ if(DRV_Reg(DMA_VFF_WPT(_n)) == (DRV_Reg(DMA_VFF_SIZE(_n))-1))\
+ DRV_WriteReg32(DMA_VFF_WPT(_n), (~DRV_Reg32(DMA_VFF_WPT(_n)))&0x10000);\
+ else \
+ DRV_WriteReg32(DMA_VFF_WPT(_n), DRV_Reg32(DMA_VFF_WPT(_n))+1);
+
+#endif //#if defined(DRV_UART_VFIFO_V3)
+
+
+
+#endif /*#if !defined(DRV_UART_OFF)*/
+#endif /*UART_HW_H*/
+
+
diff --git a/mcu/driver/peripheral/inc/uart_internal.h b/mcu/driver/peripheral/inc/uart_internal.h
new file mode 100644
index 0000000..5128c68
--- /dev/null
+++ b/mcu/driver/peripheral/inc/uart_internal.h
@@ -0,0 +1,569 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_uart.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for UART.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __UART_INTERNAL_H__
+#define __UART_INTERNAL_H__
+
+#include "uart_sw.h"
+#include "dcl.h"
+
+#include "kal_general_types.h"
+#include "drv_comm.h"
+//#include "btif_sw.h"
+
+typedef enum {
+ UART_ON_VFIFO,
+ UART_ON_DMA,
+ UART_ON_MCU,
+ UART_ON_UNKNOWN
+} UART_WORKING_MODE;
+
+#define UART_STAT_EscDet 0x01
+#define UART_STAT_Break 0x02
+
+#define UART_RecNormal 0
+#define UART_Get3EscChar 1
+#define UART_StartCheckESC 2
+
+//Size = 8bit, sinc en, dinc disable, hw management,
+//1 trans/dma cycle, UART1 master,Interrupt enable
+#define DMA_CON_UART1TxNormal 0x8034
+//Size = 8bit, sinc disable, dinc enable, hw management,
+//1 trans/dma cycle, UART1 master,Interrupt enable
+#define DMA_CON_UART1RxNormal 0x8038
+//Size = 8bit, sinc en, dinc disable, hw management,
+//1 trans/dma cycle, UART2 master,Interrupt enable
+#define DMA_CON_UART2TxNormal 0x8054
+//Size = 8bit, sinc disable, dinc enable, hw management,
+//1 trans/dma cycle, UART2 master,Interrupt enable
+#define DMA_CON_UART2RxNormal 0x8058
+
+
+
+/*TY adds these to expand flexibility 2004/10/15*/
+typedef void (*UART_TX_FUNC)(UART_PORT port);
+typedef void (*UART_RX_FUNC)(UART_PORT port) ;
+
+
+typedef struct
+{
+ UART_PORT port_no;
+ kal_bool initialized;
+ kal_bool power_on;
+ module_type ownerid;
+ module_type UART_id;
+ kal_bool breakDet;
+ kal_bool EscFound;
+ UARTDCBStruct DCB;
+ UART_RingBufferStruct RingBuffers;
+ UART_ESCDetectStruct ESCDet;
+ BUFFER_INFO Tx_Buffer_ISR; /* receive buffer */
+ BUFFER_INFO Rx_Buffer; /* receive buffer */
+ BUFFER_INFO Tx_Buffer; /* transmit buffer */
+ kal_hisrid hisr;
+ IO_level DSR;
+ /*detect Escape*/
+ DCL_HANDLE handle; /*GPT handle*/
+#if defined(DRV_UART_COMPENSATE_AT)
+ UART_Compensate_enum CompensateAT;
+#endif
+ kal_uint8 EscCount;
+ kal_uint8 Rec_state; /**/
+ UART_SLEEP_ON_TX sleep_on_tx;
+ kal_bool EnableTX;
+ /*TY adds these to expand flexibility 2004/10/15*/
+ UART_TX_FUNC tx_cb;
+ UART_RX_FUNC rx_cb;
+ //#ifdef __DMA_UART_VIRTUAL_FIFO__
+ kal_uint8 Rx_DMA_Ch;
+ kal_uint8 Tx_DMA_Ch;
+ //#endif
+
+#if defined(DRV_UART_VFIFO_V2)
+#if defined(DRV_UART_VFIFO_V2_USE_GPT)
+ DCL_HANDLE uart_flush_timer_handle; /*GPT handle*/
+ DCL_HANDLE uart_isr_flush_timer_handle; /*GPT handle*/
+#else
+ kal_timerid uart_flush_timer_id;
+#endif //DRV_UART_VFIFO_V2_USE_GPT
+#endif /* defined(DRV_UART_VFIFO_V1) */
+
+} UARTStruct;
+
+// for uart dispatch table
+typedef enum
+{
+ UART_TYPE = 0,
+ IRDA_TYPE,
+ USB_TYPE,
+ BLUETOOTH_TYPE,
+ CMUX_TYPE
+}UartType_enum;
+
+typedef struct _uartdriver
+{
+
+ kal_bool (*Open)(UART_PORT port, module_type ownerid);
+ void (*Close)(UART_PORT port, module_type ownerid);
+ kal_uint16 (*GetBytes)(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, kal_uint8 *status, module_type ownerid);
+ kal_uint16 (*PutBytes)(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
+ kal_uint16 (*GetRxAvail)(UART_PORT port);
+ kal_uint16 (*GetTxAvail)(UART_PORT port);
+ kal_uint16 (*PutISRBytes)(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
+ kal_uint16 (*GetISRTxAvail)(UART_PORT port);
+ void (*Purge)(UART_PORT port, UART_buffer dir, module_type ownerid);
+ //void (*SetOwner)(UART_PORT port, kal_uint8 ownerid);
+ void (*SetOwner)(UART_PORT port, module_type ownerid);
+ void (*SetFlowCtrl)(UART_PORT port, kal_bool XON, module_type ownerid);
+ void (*ConfigEscape)(UART_PORT port, kal_uint8 EscChar, kal_uint16 ESCGuardtime, module_type ownerid);
+ void (*SetDCBConfig)(UART_PORT port, UARTDCBStruct *UART_Config, module_type ownerid);
+ void (*CtrlDCD)(UART_PORT port, IO_level SDCD, module_type ownerid);
+ void (*CtrlBreak)(UART_PORT port, IO_level SBREAK, module_type ownerid);
+ void (*ClrRxBuffer)(UART_PORT port, module_type ownerid);
+ void (*ClrTxBuffer)(UART_PORT port, module_type ownerid);
+ void (*SetBaudRate)(UART_PORT port, UART_baudrate baudrate, module_type ownerid);
+ kal_uint16 (*SendISRData)(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode, kal_uint8 escape_char, module_type ownerid);
+ kal_uint16 (*SendData)(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode,kal_uint8 escape_char, module_type ownerid);
+ module_type (*GetOwnerID)(UART_PORT port);
+ void (*SetAutoBaud_Div)(UART_PORT port, module_type ownerid);
+ /*TY adds these to expand flexibility 2004/10/15*/
+ void (*UART_Register_TX_cb)(UART_PORT port, module_type ownerid, UART_TX_FUNC func);
+ void (*UART_Register_RX_cb)(UART_PORT port, module_type ownerid, UART_RX_FUNC func);
+ /*TY adds these to let virtual COM port can retrive exception log 2005/3/8*/
+ kal_uint8 (*GetUARTByte)(UART_PORT port);
+ void (*PutUARTByte)(UART_PORT port, kal_uint8 data);
+ void (*PutUARTBytes)(UART_PORT port, kal_uint8 *data, kal_uint16 len);
+ /*for virtual com port to return DCB configuration*/
+ void (*ReadDCBConfig)(UART_PORT port, UARTDCBStruct *UART_Config);
+ void (*CtrlRI)(UART_PORT port, IO_level SRI, module_type ownerid);
+ void (*CtrlDTR)(UART_PORT port, IO_level SDTR, module_type ownerid);
+ void (*ReadHWStatus)(UART_PORT port, IO_level *SDSR, IO_level *SCTS);
+ kal_uint8 (*GetUARTByte_WithTimeOut)(UART_PORT port, kal_uint8* ch, kal_uint32 timeout_value);
+}UartDriver_strcut;
+
+/*Function Declaration*/
+extern UartDriver_strcut UartDriver;
+
+#if defined(__DMA_UART_VFIFO_SINGLE_TUNNEL__)
+extern kal_bool UART_SINGLE_VFIFO_support[MAX_UART_TUNNEL_NUM] ; //toy add for single tunnel vfifo
+extern kal_bool UART_IsVfifoSetting(UART_PORT port, UART_TxRx_VFIFO_support vs);
+#ifdef __DMA_UART_VIRTUAL_FIFO__
+extern UartDriver_strcut UartDriver_VFIFO;
+extern UartDriver_strcut UartDriver_VFIFO_RX;
+extern UartDriver_strcut UartDriver_VFIFO_TX;
+#endif
+#else
+extern kal_bool UART_VFIFO_support[MAX_UART_PORT_NUM];
+#ifdef __DMA_UART_VIRTUAL_FIFO__
+extern UartDriver_strcut UartDriver_VFIFO;
+#endif
+#endif
+
+extern UartDriver_strcut* pUart_CMD_FUNC[];
+
+
+#if defined(DRV_UART_COMPENSATE_AT)
+extern void UART_CompensateAT(UART_PORT port);
+extern void UART_CheckAT_Callback(void *parameter);
+#endif //#if defined(DRV_UART_COMPENSATE_AT)
+
+extern void UART1_PDN_ENABLE(void);
+extern void UART1_PDN_DISABLE(void);
+extern void UART2_PDN_ENABLE(void);
+extern void UART2_PDN_DISABLE(void);
+#ifdef __UART3_SUPPORT__
+extern void UART3_PDN_ENABLE(void);
+extern void UART3_PDN_DISABLE(void);
+#endif //#ifdef __UART3_SUPPORT__
+
+/*ISR handler for VFIFO*/
+extern void UART_RecTimeOutHandler(UART_PORT port);
+extern void UART_TrxHandler_VFIFO(UART_PORT port);
+extern void UART_RecHandler_VFIFO(UART_PORT port);
+extern void UART_THRE_hdr_VFIFO(UART_PORT port);
+/*API for VFIFO*/
+extern void U_configure_DMA_VFIFO(void);
+extern kal_uint16 U_GetTxISRRoomLeft_VFIFO(UART_PORT port);
+extern kal_uint16 U_GetTxRoomLeft_VFIFO(UART_PORT port);
+extern kal_uint16 U_GetBytesAvail_VFIFO(UART_PORT port);
+extern kal_uint8 U_GetUARTByte_VFIFO(UART_PORT port);
+extern void U_PutUARTByte_VFIFO(UART_PORT port, kal_uint8 data);
+extern void PutUARTData_VFIFO(UART_PORT port, kal_uint8 escape_char, kal_uint8 data);
+extern kal_uint16 U_GetBytes_VFIFO(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, kal_uint8 *status, module_type ownerid);
+extern kal_uint16 U_PutBytes_VFIFO(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
+extern kal_uint16 U_PutISRBytes_VFIFO(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
+extern kal_uint16 U_SendData_VFIFO(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode,kal_uint8 escape_char, module_type ownerid);
+extern kal_uint16 U_SendISRData_VFIFO(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode,kal_uint8 escape_char, module_type ownerid);
+extern kal_bool UART_UseVFIFO(UART_PORT port, kal_bool use_vfifo);
+
+extern void UART_DriverInit(UART_PORT port,kal_uint32 flag);
+extern void UART_Boot_Trace_Release(kal_bool flag);//for bootup trace
+
+extern void UART_set_FIFO_trigger(UART_PORT port, kal_uint16 tx_level, kal_uint16 rx_level);
+
+#ifdef __UART3_SUPPORT__
+ extern void UART3_HISR(void);
+ extern void UART3_LISR(void);
+#endif /*MT6218*/
+// for Uart Dispatch
+//extern void UART_Register(UART_PORT port, UartType_enum type, UartDriver_strcut* drv);
+
+/* Note: for ROM code start */
+#ifdef __ROMSA_SUPPORT__
+/*for mcu rom*/
+extern kal_uint16 U_GetTxISRRoomLeft(UART_PORT port);
+extern kal_uint16 U_PutISRBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
+extern kal_uint16 U_ROM_GetTxISRRoomLeft(UART_PORT port);
+extern UARTStruct *U_ROM_GetUARTPort(UART_PORT port);
+extern kal_uint8 *U_ROM_GetUART_TXilm(UART_PORT port);
+extern void U_ROM_InformUARTOwner(UART_PORT port);
+extern void U_ROM_PushDataToBuf(UART_PORT port, kal_uint8 *data, kal_uint32 real_count);
+extern void U_ROM_EnableTxIntr(UART_PORT port);
+//extern void DRVPDN_Disable(kal_uint32 addr,kal_uint16 code,kal_uint8 handle);
+#endif
+/* Note: for ROM code end */
+
+// Used under ASSERT condition
+// This has effect only when the port does NOT support VFIFO and used as Catcher port
+extern void UART_AssertWaitPrevDataSentOut(UART_PORT port);
+
+
+extern kal_bool UART1DMA_Ini(kal_bool Tx);
+extern kal_bool UART2DMA_Ini(kal_bool Tx);
+extern kal_uint8 GetUARTByte(UART_PORT port);
+extern void PutUARTByte(UART_PORT port, kal_uint8 data);
+extern void UART_SetBaudRate(UART_PORT port, UART_baudrate baud_rate, module_type ownerid);
+extern void UART_SetDCBConfig(UART_PORT port, UARTDCBStruct *UART_Config, module_type ownerid);
+extern void UART_ReadDCBConfig (UART_PORT port, UARTDCBStruct *DCB);
+extern void UART_loopback(UART_PORT port);
+extern void UART_HWInit(UART_PORT port);
+extern kal_bool UART_Open(UART_PORT port, module_type ownerid);
+extern void UART_Close(UART_PORT port, module_type ownerid);
+//extern void UART_SetOwner (UART_PORT port, kal_uint8 ownerid);
+extern void UART_SetOwner (UART_PORT port, module_type ownerid);
+extern void UART_ConfigEscape (UART_PORT port, kal_uint8 EscChar, kal_uint16 ESCGuardtime, module_type ownerid);
+extern void UART_CtrlDTR (UART_PORT port, IO_level SDTR, module_type ownerid);
+extern void UART_ReadHWStatus(UART_PORT port, IO_level *SDSR, IO_level *SCTS);
+extern void UART_CtrlBreak(UART_PORT port, IO_level SBREAK, module_type ownerid);
+extern void UART_Purge(UART_PORT port, UART_buffer dir, module_type ownerid);
+extern void UART_Register_RX_cb(UART_PORT port, module_type ownerid, UART_RX_FUNC func);
+extern void UART_Register_TX_cb(UART_PORT port, module_type ownerid, UART_TX_FUNC func);
+extern void UART_PDN_Disable(UART_PORT port);
+extern void UART_PDN_Enable(UART_PORT port);
+
+
+//API for single tunnel VFIFO
+extern kal_uint16 U_GetBytesAvail(UART_PORT port);
+extern kal_uint16 U_GetBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, kal_uint8 *status, module_type ownerid);
+extern kal_uint8 U_GetUARTByte(UART_PORT port);
+extern kal_uint16 U_PutBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid );
+extern kal_uint16 U_GetTxRoomLeft(UART_PORT port);
+extern kal_uint16 U_SendISRData(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode, kal_uint8 escape_char, module_type ownerid);
+extern kal_uint16 U_SendData(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode,kal_uint8 escape_char, module_type ownerid);
+extern void U_PutUARTByte(UART_PORT port, kal_uint8 data);
+
+extern void UART_Boot_PutUARTBytes(UART_PORT port, kal_uint8 *data,kal_uint16 len);
+extern void UART_Bootup_Init(void);
+extern kal_uint16 UART_GetBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, kal_uint8 *status, module_type ownerid);
+extern kal_uint16 UART_PutBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
+extern kal_uint16 UART_PutISRBytes(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length, module_type ownerid);
+extern kal_uint16 UART_SendISRData(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode, kal_uint8 escape_char, module_type ownerid);
+extern kal_uint16 UART_SendData(UART_PORT port, kal_uint8 *Buffaddr, kal_uint16 Length,kal_uint8 mode,kal_uint8 escape_char, module_type ownerid );
+extern void UART_SetFlowCtrl(UART_PORT port, kal_bool XON, module_type ownerid);
+extern void UART_CtrlDCD(UART_PORT port, IO_level SDCD, module_type ownerid);
+extern void UART_CtrlRI (UART_PORT port, IO_level SRI, module_type ownerid);
+extern kal_uint16 UART_GetBytesAvail(UART_PORT port);
+extern void UART_SleepOnTx_Enable(UART_PORT port, UART_SLEEP_ON_TX enable_flag);
+extern void UART_SetSleepEnable(kal_bool enable);
+extern void UART_SwitchPort(UART_PORT *APP_port, UART_PORT new_uart_port);
+extern void UART_dafault_tx_cb(UART_PORT port);
+extern void UART_dafault_rx_cb(UART_PORT port);
+extern void UART_TurnOnPower(UART_PORT port, kal_bool enable);
+extern kal_bool UART_CheckTxBufferEmpty(UART_PORT port);
+extern kal_bool UART_CheckTxAllSentOut(UART_PORT port);
+extern void UART_GetTxBufferSize(UART_PORT port, kal_uint32 *total_size, kal_uint32 *rest_size);
+extern void UART1_HISR(void);
+extern void UART2_HISR(void);
+extern void UART1_LISR(void);
+extern void UART2_LISR(void);
+extern kal_bool uart_support_autoescape(void);
+extern void UART_VFIFO_TX_DMA_Enable(UART_PORT port,kal_bool enable);
+extern void UART_dsp_dafault_rx_cb(UART_PORT port);
+extern void UART_dsp_dafault_tx_cb(UART_PORT port);
+extern kal_uint32 UART_Get_Maxbaudrate(UART_PORT port);
+
+
+
+/*end of local parameter struct */
+#define EnableRxIntr(_baseaddr) \
+{\
+ kal_uint32 _savedMask;\
+ kal_uint16 _IER;\
+ _savedMask = SaveAndSetIRQMask();\
+ _IER = DRV_Reg(UART_IER(_baseaddr));\
+ _IER |= (UART_IER_ERBFI | UART_IER_ELSI);\
+ DRV_WriteReg(UART_IER(_baseaddr),_IER);\
+ RestoreIRQMask(_savedMask);\
+}
+
+#define DisableRxIntr(_baseaddr) \
+{\
+ kal_uint16 _IER;\
+ kal_uint32 _savedMask;\
+ _savedMask = SaveAndSetIRQMask();\
+ _IER = DRV_Reg(UART_IER(_baseaddr));\
+ _IER &= ~(UART_IER_ERBFI|UART_IER_ELSI);\
+ DRV_WriteReg(UART_IER(_baseaddr),_IER);\
+ RestoreIRQMask(_savedMask);\
+}
+
+
+#define EnableTxIntr(_baseaddr) \
+{\
+ kal_uint16 _IER;\
+ kal_uint32 _savedMask;\
+ _savedMask = SaveAndSetIRQMask();\
+ _IER = DRV_Reg(UART_IER(_baseaddr));\
+ _IER |= UART_IER_ETBEI;\
+ DRV_WriteReg(UART_IER(_baseaddr),_IER);\
+ RestoreIRQMask(_savedMask);\
+}
+
+#define DisableTxIntr(_baseaddr) \
+{\
+ kal_uint16 _IER;\
+ kal_uint32 _savedMask;\
+ _savedMask = SaveAndSetIRQMask();\
+ _IER = DRV_Reg(UART_IER(_baseaddr));\
+ _IER &= ~UART_IER_ETBEI;\
+ DRV_WriteReg(UART_IER(_baseaddr),_IER);\
+ RestoreIRQMask(_savedMask);\
+}
+
+#define UART_SetDMAIntr(_baseaddr) \
+{\
+ kal_uint16 _IER;\
+ kal_uint32 _savedMask;\
+ _savedMask = SaveAndSetIRQMask();\
+ _IER = DRV_Reg(UART_IER(_baseaddr));\
+ _IER &= ~(UART_IER_ETBEI);\
+ DRV_WriteReg(UART_IER(_baseaddr),_IER);\
+ RestoreIRQMask(_savedMask);\
+}
+
+#define DisableRLSIntr(_baseaddr) \
+{\
+ kal_uint16 _IER;\
+ kal_uint32 _savedMask;\
+ _savedMask = SaveAndSetIRQMask();\
+ _IER = DRV_Reg(UART_IER(_baseaddr));\
+ _IER &= ~(UART_IER_ELSI);\
+ DRV_WriteReg(UART_IER(_baseaddr),_IER);\
+ RestoreIRQMask(_savedMask);\
+}
+
+
+extern UART_WORKING_MODE UART_GetTxWorkingMode(UART_PORT port);
+
+#if defined(__MTK_INTERNAL__) && !defined(__MAUI_BASIC__) && defined(__DRV_DBG_MEMORY_TRACE_SUPPORT__)
+#define DRV_UART_MEMORY_TRACE
+typedef struct{
+ kal_uint16 tag;
+ kal_uint32 time;
+ kal_uint32 data1;
+ kal_uint32 data2;
+}UART_DRV_DBG_DATA;
+#define MAX_UART_DRV_DBG_INFO_SIZE 512
+typedef struct{
+ UART_DRV_DBG_DATA dbg_data[MAX_UART_DRV_DBG_INFO_SIZE];
+ kal_uint16 dbg_data_idx;
+}UART_DRV_DBG_STRUCT;
+extern void uart_drv_dbg_trace(kal_uint16 index, kal_uint32 time, kal_uint32 data1, kal_uint32 data2);
+#define UART_DBG(a,b,c,d) uart_drv_dbg_trace(a,b,c,d);
+#include "us_timer.h"
+extern kal_uint32 L1I_GetTimeStamp(void);
+#define UART_GetTimeStamp L1I_GetTimeStamp
+#else //#if defined(__MTK_INTERNAL__) && !defined(LOW_COST_SUPPORT)
+#define UART_DBG(a,b,c,d) ;
+#endif //#if defined(__MTK_INTERNAL__) && !defined(LOW_COST_SUPPORT)
+
+
+#if defined(__SSDVT_TEST__) /* add for SSDVT , make sure that UART init Value is satisfied for DVT's need */
+#define DRV_UART_WriteReg(addr,data)
+#define DRV_UART_Reg(addr) DRV_Reg(addr)
+#define DRV_UART_WriteReg32(addr,data)
+#define DRV_UART_Reg32(addr) DRV_Reg32(addr)
+#define DRV_UART_WriteReg8(addr,data)
+#define DRV_UART_Reg8(addr) DRV_Reg8(addr)
+#define DRV_UART_ClearBits(addr,data)
+#define DRV_UART_SetBits(addr,data)
+#define DRV_UART_SetData(addr, bitmask, value)
+#define DRV_UART_ClearBits32(addr,data)
+#define DRV_UART_SetBits32(addr,data)
+#define DRV_UART_SetData32(addr, bitmask, value)
+#define DRV_UART_ClearBits8(addr,data)
+#define DRV_UART_SetBits8(addr,data)
+#define DRV_UART_SetData8(addr, bitmask, value)
+#elif defined(__DRV_COMM_REG_DBG__) && defined(__DRV_UART_REG_DBG__) /*normal case */
+#define DRV_UART_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+#define DRV_UART_Reg(addr) DRV_DBG_Reg(addr)
+#define DRV_UART_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define DRV_UART_Reg32(addr) DRV_DBG_Reg32(addr)
+#define DRV_UART_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+#define DRV_UART_Reg8(addr) DRV_DBG_Reg8(addr)
+#define DRV_UART_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+#define DRV_UART_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+#define DRV_UART_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#define DRV_UART_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+#define DRV_UART_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+#define DRV_UART_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+#define DRV_UART_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+#define DRV_UART_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+#define DRV_UART_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+#else
+#define DRV_UART_WriteReg(addr,data) DRV_WriteReg(addr,data)
+#define DRV_UART_Reg(addr) DRV_Reg(addr)
+#define DRV_UART_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define DRV_UART_Reg32(addr) DRV_Reg32(addr)
+#define DRV_UART_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+#define DRV_UART_Reg8(addr) DRV_Reg8(addr)
+#define DRV_UART_ClearBits(addr,data) DRV_ClearBits(addr,data)
+#define DRV_UART_SetBits(addr,data) DRV_SetBits(addr,data)
+#define DRV_UART_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define DRV_UART_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+#define DRV_UART_SetBits32(addr,data) DRV_SetBits32(addr,data)
+#define DRV_UART_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+#define DRV_UART_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+#define DRV_UART_SetBits8(addr,data) DRV_SetBits8(addr,data)
+#define DRV_UART_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_UART_REG_DBG__)
+
+
+#endif
+
diff --git a/mcu/driver/peripheral/inc/uart_sw_int.h b/mcu/driver/peripheral/inc/uart_sw_int.h
new file mode 100644
index 0000000..50fd3f4
--- /dev/null
+++ b/mcu/driver/peripheral/inc/uart_sw_int.h
@@ -0,0 +1,53 @@
+#ifndef __UART_SW_INT_H__
+#define __UART_SW_INT_H__
+
+ /*
+ * NoteXXX: Below is the sample code to set UART
+ * UART clock is MPLL clock / 8.
+ * baud rate is 115200.
+ * Thus UART1_DLL = 0xE.
+ * You should specify UART1_DLL based on
+ * divisor(DLH+DLL) = (UART_CLOCK_RATE)
+ */
+
+
+#define UART_SETUP(_n, _divL, _divH) \
+ do { \
+ volatile kal_uint16 tmp; \
+ \
+ /* Setup 8-N-1,(UART_WLS_8 | UART_NONE_PARITY | UART_ */ \
+ UART_WriteReg(UART##_n##_LCR,0x0003); \
+ \
+ /* divisor: 8 */ \
+ UART_WriteReg(UART##_n##_HIGHSPEED,0x0001); \
+ \
+ /* Set BaudRate */ \
+ tmp = UART_ReadReg(UART##_n##_LCR); \
+ tmp |= UART_LCR_DLAB; \
+ UART_WriteReg(UART##_n##_LCR, tmp); \
+ \
+ /* MCU_CLK 491520000(491.52MHz) */ \
+ /* UART_CLK (MCU_CLK / 8) */ \
+ \
+ /* divisorL = ((UART_CLK / 8) / 115200) & 0xFF; */ \
+ /* divisorH = ((UART_CLK / 8) / 115200) >> 8; */ \
+ \
+ /* UART_WriteReg(_DLL, divisorL); */ \
+ UART_WriteReg(UART##_n##_DLL, (_divL)); \
+ /* UART_WriteReg(_DLM, divisorH); */ \
+ UART_WriteReg(UART##_n##_DLM, (_divH)); \
+ \
+ UART_WriteReg(UART##_n##_LCR, 0x0003); \
+ /* Enable Fifo, and Rx Trigger level = 16bytes, flush */ \
+ /* (UART_FCR_FIFOEN | UART_FCR_4Byte_Level | UART_FCR */ \
+ UART_WriteReg(UART##_n##_FCR, 0x0047); \
+ \
+ /* DTR , RTS is on, data will be coming,Output2 is hi */ \
+ UART_WriteReg(UART##_n##_MCR,(kal_uint16)0x0003); \
+ \
+ /* _IER, enable RDA, RLS, MS , disable THR inter */ \
+ /* UART_WriteReg(UART##_n##_IER, UART_IER_RDA); */ \
+ UART_WriteReg(UART##_n##_IER, IER_HW_NORMALINTS); \
+ } while(0)
+
+#endif /* __UART_SW_INT_H__ */
diff --git a/mcu/driver/peripheral/inc/wdt_hw.h b/mcu/driver/peripheral/inc/wdt_hw.h
new file mode 100644
index 0000000..832ff0f
--- /dev/null
+++ b/mcu/driver/peripheral/inc/wdt_hw.h
@@ -0,0 +1,365 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * wdt_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for WDT driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _WDT_HW_H
+#define _WDT_HW_H
+#include "drv_features_wdt.h"
+#include "reg_base.h"
+#if !defined(DRV_WDT_OFF)
+
+#define WDT_base RGU_base /* Watchdog Timer */
+
+/*****************
+ * WDT Registers *
+ *****************/
+#if defined(DRV_WDT_LIMIT_REG) || defined(FPGA)
+ #define WDT_MODE (WDT_base+0x0000)
+ #define WDT_LENGTH (WDT_base+0x0004)
+ #define WDT_RESTART (WDT_base+0x0008)
+ #define WDT_STATUS (WDT_base+0x000C)
+ #define RGU_PERIPH_RESET (WDT_base+0x0010)
+ #define RGU_DSP_RESET (WDT_base+0x0014)
+ #define WDT_RSTINTERVAL (WDT_base+0x0018)
+
+ #define WDT_MODE_KEYMASK 0xff00
+ #define WDT_MODE_EXTEN 0x0004
+ #define WDT_MODE_EXTPOL 0x0002
+ #define WDT_MODE_ENABLE 0x0001
+ #define WDT_LENGTH_TOUT 0xff00
+ #define WDT_LENGTH_KEYMASK 0x00ff
+ #define WDT_RESTART_KEY 0x1971
+ #define WDT_STATUS_BITMASK 0x8000
+ #define WDT_LENGTH_KEY 0x0008
+ #define WDT_MODE_KEY 0x2200
+ #define WDT_RSTINTERVAL_MASK 0x0fff
+
+ #define RGU_PERIPH_RESET_APB_PERIPH 0x8000
+ #define RGU_PERIPH_RESET_DMA 0x4000
+
+ #define RGU_DSP_RESET_BIT 0x8000
+#endif /*DRV_WDT_LIMIT_REG,FPGA*/
+
+#if defined(DRV_WDT_BASIC_REG)
+ #define WDT_MODE (WDT_base+0x0000)
+ #define WDT_LENGTH (WDT_base+0x0004)
+ #define WDT_RESTART (WDT_base+0x0008)
+ #define WDT_STATUS (WDT_base+0x000C)
+ #define RGU_PERIPH_RESET (WDT_base+0x0010)
+ #define RGU_DSP_RESET (WDT_base+0x0014)
+ #define WDT_RSTINTERVAL (WDT_base+0x0018)
+ #define WDT_SWRST (WDT_base+0x001c)
+
+ /*WDT_MODE*/
+ #define WDT_MODE_KEYMASK 0xff00
+ #define WDT_MODE_AUTORST 0x0010
+ #define WDT_MODE_IRQEN 0x0008
+ #define WDT_MODE_EXTEN 0x0004
+ #define WDT_MODE_EXTPOL 0x0002
+ #define WDT_MODE_ENABLE 0x0001
+ #define WDT_MODE_KEY 0x2200
+
+ /*WDT_LENGTH*/
+ #define WDT_LENGTH_TOUT 0xffe0
+ #define WDT_LENGTH_KEYMASK 0x001f
+ #define WDT_LENGTH_KEY 0x0008
+
+ /*WDT_RESTART*/
+ #define WDT_RESTART_KEY 0x1971
+
+ /*WDT_STATUS*/
+ #define WDT_STATUS_BITMASK 0xc000
+ #define WDT_STATUS_SWWDT 0x4000
+
+ /*WDT_RSTINTERVAL*/
+ #define WDT_RSTINTERVAL_MASK 0x0fff
+ #define WDT_RSTINTERVAL_VAL 0x0ffa //KC
+
+ /*RGU_PERIPH_RESET*/
+ #define RGU_PERIPH_RESET_APB_PERIPH 0x8000
+ #define RGU_PERIPH_RESET_DMA 0x4000
+ #define RGU_PERIPH_RESET_USB 0x2000
+ #define RGU_PERIPH_RESET_DISP 0x0800
+
+ /*RGU_DSP_RESET*/
+ #define RGU_DSP_RESET_BIT 0x8000
+
+ /*WDT_SWRST*/
+ #define WDT_SWRST_KEY 0x1209
+#endif /*DRV_WDT_BASIC_REG*/
+
+#if defined(DRV_WDT_RETN_REG)
+//for USBDLv2,when WDT reset,let BROM or bootloader know the two things:
+// 1: whether do USBDL or not is depends on The register:RETN_FLAG
+// 2: RETN_DAT0: How long the USBDL timeout
+ #define WDT_RETN_FLAG (WDT_base+0x800)
+ #define WDT_RETN_FLAG_SET (WDT_base+0x804)
+ #define WDT_RETN_FLAG_CLR (WDT_base+0x808)
+ #define WDT_RETN_DAT0 (WDT_base+0x814)
+
+ #define WDT_RETN_FLAG_KEY 0x4e000000
+#endif
+
+
+#if defined(DRV_WDT_6573_REG)
+
+
+#define WDT_base RGU_SD_base
+
+ #define WDT_MODE (WDT_base+0x0000)
+ #define WDT_LENGTH (WDT_base+0x0004)
+ #define WDT_RESTART (WDT_base+0x0008)
+ #define WDT_STATUS (WDT_base+0x000C)
+ #define WDT_RSTINTERVAL (WDT_base+0x0010)
+ #define WDT_SWRST (WDT_base+0x0014)
+
+ /*WDT_MODE*/
+ #define WDT_MODE_KEYMASK 0xff00
+ #define WDT_MODE_IRQEN 0x0008
+ #define WDT_MODE_EXTEN 0x0000
+ #define WDT_MODE_EXTPOL 0x0000
+ #define WDT_MODE_ENABLE 0x0001
+ #define WDT_MODE_KEY 0x2200
+
+ /*WDT_LENGTH*/
+ #define WDT_LENGTH_TOUT 0xffe0
+ #define WDT_LENGTH_KEYMASK 0x001f
+ #define WDT_LENGTH_KEY 0x0008
+
+ /*WDT_RESTART*/
+ #define WDT_RESTART_KEY 0x1971
+
+ /*WDT_STATUS*/
+ #define WDT_STATUS_BITMASK 0xc000
+ #define WDT_STATUS_SWWDT 0x4000
+
+ /*WDT_RSTINTERVAL*/
+ #define WDT_RSTINTERVAL_MASK 0x0fff
+ #define WDT_RSTINTERVAL_VAL 0x0ffa //KC
+
+ /*WDT_SWRST*/
+ #define WDT_SWRST_KEY 0x1209
+#endif /*DRV_WDT_6573_REG*/
+
+#if defined(DRV_WDT_6575_REG)
+ #define WDT_MODE (WDT_base+0x0000)
+ #define WDT_LENGTH (WDT_base+0x0004)
+ #define WDT_RESTART (WDT_base+0x0008)
+ #define WDT_STATUS (WDT_base+0x000C)
+ #define WDT_SWRST (WDT_base+0x0010)
+ #define MCU_RESET (WDT_base+0x0040)
+ #define RGU_DSP_RESET (WDT_base+0x0044)
+
+ /*WDT_MODE*/
+ #define WDT_MODE_KEYMASK 0xff00
+ #define WDT_MODE_IRQEN 0x0002
+ // #define WDT_MODE_EXTEN 0x0000
+ // #define WDT_MODE_EXTPOL 0x0000
+ #define WDT_MODE_ENABLE 0x0001
+ #define WDT_MODE_KEY 0x2200
+
+ /*WDT_LENGTH*/
+ #define WDT_LENGTH_TOUT 0xffe0
+ #define WDT_LENGTH_KEYMASK 0x001f
+ #define WDT_LENGTH_KEY 0x0008
+
+ /*WDT_RESTART*/
+ #define WDT_RESTART_KEY 0x1971
+
+ /*WDT_STATUS*/
+ #define WDT_STATUS_BITMASK 0xc000
+ #define WDT_STATUS_SWWDT 0x4000
+
+ /*WDT_RSTINTERVAL*/
+ #define WDT_RSTINTERVAL_MASK 0x0fff
+
+ /*WDT_SWRST*/
+ #define WDT_SWRST_KEY 0x1209
+
+ /*MCU_SWRST*/
+ #define MCU_RESET_KEY 0x37
+
+ /*DSP_SWRST*/
+ #define MCU_RESET_KEY 0x48
+
+ /*WDT_LENGTH_VALUE_INIT*/
+ #define WDT_LENGTH_VALUE_INIT 0x1fe0
+#endif /*DRV_WDT_6575_REG*/
+
+#endif /*#if !defined(DRV_WDT_OFF)*/
+#endif /*_WDT_HW_H*/
+
diff --git a/mcu/driver/peripheral/inc/wdt_sw.h b/mcu/driver/peripheral/inc/wdt_sw.h
new file mode 100644
index 0000000..571b178
--- /dev/null
+++ b/mcu/driver/peripheral/inc/wdt_sw.h
@@ -0,0 +1,225 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * wdt_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for WDT driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef WDT_SW_H
+#define WDT_SW_H
+
+#include "drv_features_wdt.h"
+#include "drv_comm.h"
+#include "wdt_hw.h"
+//#include "wdt_hw.h"
+//#include "kal_non_specific_general_types.h"
+
+/*Must include "drv_comm.h*/
+#define WDT_RSTINTERVAL_VALUE 0xffa
+#define WDT_Restart() DRV_WriteReg(WDT_RESTART,WDT_RESTART_KEY)
+void WDT_SetValue(kal_uint16 value);
+void WDT_Enable(kal_bool en);
+void WDT_EnableInterrupt(kal_bool enable);
+void WDT_SetExtpol(IO_level extpol);
+void WDT_SetExten(kal_bool en);
+void WDT_Config(IO_level extpol, kal_bool exten);
+void WDT_Enable_Debug_Mode(kal_bool en);
+void WDT_init(void);
+void DRV_RESET(void);
+void DRV_ABN_RESET(void);
+void WDT_Restart2(void);
+
+#if defined(DRV_WDT_RETN_REG)
+void WDT_Write_RETN_FLAG(kal_uint8 flag);
+void WDT_SET_RETN_FLAG(kal_uint8 flag);
+void WDT_CLR_RETN_FLAG(kal_uint8 flag);
+kal_uint8 WDT_Read_RETN_FLAG(void);
+void WDT_Write_RETN_DAT0(kal_uint32 value);
+kal_uint32 WDT_Read_RETN_DAT0(void);
+#endif
+
+
+
+#if !defined(DRV_WDT_OFF)
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_WDT_REG_DBG__)
+#define DRV_WDT_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+#define DRV_WDT_Reg(addr) DRV_DBG_Reg(addr)
+#define DRV_WDT_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define DRV_WDT_Reg32(addr) DRV_DBG_Reg32(addr)
+#define DRV_WDT_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+#define DRV_WDT_Reg8(addr) DRV_DBG_Reg8(addr)
+#define DRV_WDT_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+#define DRV_WDT_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+#define DRV_WDT_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#define DRV_WDT_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+#define DRV_WDT_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+#define DRV_WDT_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+#define DRV_WDT_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+#define DRV_WDT_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+#define DRV_WDT_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+#else
+#define DRV_WDT_WriteReg(addr,data) DRV_WriteReg(addr,data)
+#define DRV_WDT_Reg(addr) DRV_Reg(addr)
+#define DRV_WDT_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define DRV_WDT_Reg32(addr) DRV_Reg32(addr)
+#define DRV_WDT_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+#define DRV_WDT_Reg8(addr) DRV_Reg8(addr)
+#define DRV_WDT_ClearBits(addr,data) DRV_ClearBits(addr,data)
+#define DRV_WDT_SetBits(addr,data) DRV_SetBits(addr,data)
+#define DRV_WDT_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define DRV_WDT_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+#define DRV_WDT_SetBits32(addr,data) DRV_SetBits32(addr,data)
+#define DRV_WDT_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+#define DRV_WDT_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+#define DRV_WDT_SetBits8(addr,data) DRV_SetBits8(addr,data)
+#define DRV_WDT_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_WDT_REG_DBG__)
+
+#else // !defined(DRV_WDT_OFF)
+
+#define DRV_WDT_WriteReg(addr,data)
+#define DRV_WDT_Reg(addr) drv_dummy_return()
+#define DRV_WDT_WriteReg32(addr,data)
+#define DRV_WDT_Reg32(addr) drv_dummy_return()
+#define DRV_WDT_WriteReg8(addr,data)
+#define DRV_WDT_Reg8(addr) drv_dummy_return()
+#define DRV_WDT_ClearBits(addr,data)
+#define DRV_WDT_SetBits(addr,data)
+#define DRV_WDT_SetData(addr, bitmask, value)
+#define DRV_WDT_ClearBits32(addr,data)
+#define DRV_WDT_SetBits32(addr,data)
+#define DRV_WDT_SetData32(addr, bitmask, value)
+#define DRV_WDT_ClearBits8(addr,data)
+#define DRV_WDT_SetBits8(addr,data)
+#define DRV_WDT_SetData8(addr, bitmask, value)
+
+#endif //!defined(DRV_WDT_OFF)
+#endif
+