[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6

MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF  modem version: NA

Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/driver/devdrv/asm/drv_asm.h b/mcu/interface/driver/devdrv/asm/drv_asm.h
new file mode 100644
index 0000000..b084925
--- /dev/null
+++ b/mcu/interface/driver/devdrv/asm/drv_asm.h
@@ -0,0 +1,286 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * drv_asm.h
+ *
+ * Project:
+ * --------
+ *   UMOLY_Software
+ *
+ * Description:
+ * ------------
+ *   This file defines ASM drivers interface
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *==============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DRV_ASM_H__
+#define __DRV_ASM_H__
+
+#include "kal_general_types.h"
+
+typedef enum {
+	ASM_SW_SWLA_MODE = 0,
+	ASM_SW_SWTR_MODE,
+	ASM_HW_SWLA_STRAM_MODE,
+	ASM_HW_SWLA_WRAP_MODE, 
+	ASM_HW_SWTR_STRAM_MODE, 
+	ASM_HW_SWTR_WRAP_MODE, 
+	ASM_MODE_END
+}ASM_MODE;
+
+#if defined (__MD93__)  
+
+typedef enum 
+{
+    ASM_CORE0_INT = 0,
+    ASM_CORE1_INT,
+}ASM_INT_CORE_NUM;
+
+
+typedef enum 
+{
+    ASM_CORE0 = 0,
+    ASM_CORE1,
+    ASM_NUM
+}ASM_MCU_CORE;
+
+typedef enum 
+{
+	ASM_TC_ID_CORE_ID_EN = 0,
+	ASM_PC_EN,
+	ASM_MCU_PMC0_EN,
+	ASM_MCU_PMC1_EN,
+	ASM_MCU_ELM_CNT0_EN,
+	ASM_MCU_ELM_CNT1_EN,
+	ASM_MCU_ELM_CNT2_EN,
+	ASM_MCU_ELM_CNT3_EN,
+	ASM_ADDON_INFO0_EN,
+	ASM_ADDON_INFO1_EN,
+	ASM_ADDON_INFO2_EN,
+	ASM_ADDON_INFO3_EN,
+	ASM_PROFILE_END,
+}ASM_PROFILE_OPTION;
+
+
+
+#elif defined (__MD95__) 
+
+typedef enum 
+{
+    ASM_CORE0_INT = 0,
+    ASM_CORE1_INT,
+#ifndef __MD95_IS_2CORES__
+    ASM_CORE2_INT,
+#endif // ifndef(__MD95_IS_2CORES__)
+}ASM_INT_CORE_NUM;
+
+
+typedef enum 
+{
+    ASM_CORE0 = 0,
+    ASM_CORE1,
+#ifndef __MD95_IS_2CORES__
+    ASM_CORE2,
+#endif // ifndef(__MD95_IS_2CORES__)
+    ASM_NUM
+}ASM_MCU_CORE;
+
+typedef enum 
+{
+	ASM_TC_ID_CORE_ID_EN = 0,
+	ASM_PC_EN,
+	ASM_MCU_PMC0_EN,
+	ASM_MCU_PMC1_EN,
+	ASM_MCU_ELM_CNT0_EN,
+	ASM_MCU_ELM_CNT1_EN,
+	ASM_MCU_ELM_CNT2_EN,
+	ASM_MCU_ELM_CNT3_EN,
+	ASM_MCU_ELM_CNT4_EN,
+	ASM_MCU_ELM_CNT5_EN,
+	ASM_ADDON_INFO0_EN,
+	ASM_ADDON_INFO1_EN,
+	ASM_ADDON_INFO2_EN,
+	ASM_ADDON_INFO3_EN,
+	ASM_PROFILE_END,
+}ASM_PROFILE_OPTION;
+
+
+#else
+
+typedef enum 
+{
+    ASM_CORE0_INT = 0,
+    ASM_CORE1_INT,
+    ASM_CORE2_INT,
+    ASM_CORE3_INT,
+}ASM_INT_CORE_NUM;
+
+
+typedef enum 
+{
+    ASM_CORE0 = 0,
+    ASM_CORE1,
+    ASM_CORE2,
+    ASM_CORE3,
+    ASM_NUM
+}ASM_MCU_CORE;
+
+
+typedef enum 
+{
+	ASM_TC_ID_CORE_ID_EN = 0,
+	ASM_PC_EN,
+	ASM_MCU_PMC0_EN,
+	ASM_MCU_PMC1_EN,
+	ASM_MCU_ELM_CNT0_EN,
+	ASM_MCU_ELM_CNT1_EN,
+	ASM_MCU_ELM_CNT2_EN,
+	ASM_MCU_ELM_CNT3_EN,
+	ASM_MCU_ELM_CNT4_EN,
+	ASM_MCU_ELM_CNT5_EN,
+	ASM_ADDON_INFO0_EN,
+	ASM_ADDON_INFO1_EN,
+	ASM_ADDON_INFO2_EN,
+	ASM_ADDON_INFO3_EN,
+	ASM_PROFILE_END,
+}ASM_PROFILE_OPTION;
+
+
+#endif // if defined (__MD93__)  
+
+
+
+typedef enum 
+{
+    ASM_THRESHOLD_INT = 0,
+    ASM_AGGRESSIVE_TRIG_INT,
+    ASM_APB_WR_GCR_ILLEGAL_INT,
+    ASM_ILLEGAL_DISABLE_INT,
+    ASM_PDI_INT,
+}ASM_INT_TYPE;
+
+
+
+typedef enum 
+{
+    ASM_ERROR_CODE_NO_ERROR = 0,                  // NO error
+    ASM_ERROR_CODE_BUFFER_TOO_SMALL,              // Buffer size is less than 1KB
+    ASM_ERROR_CODE_BUFFER_TOO_LARGE,              // Buffer size is over limitation
+    ASM_ERROR_CODE_WRONG_MODE,                    // ASM mode is not defined
+    ASM_ERROR_CODE_WAIT_IDLE_FAIL,                // wait idle timeout
+    ASM_ERROR_CODE_OVER_ADDON_INDEX,              // start index is not druing addon range
+    ASM_ERROR_CODE_OVER_ADDON_SIZE,               // addon size over 8
+    ASM_ERROR_CODE_INVALID_SAMPLE_RATE,           // sampeling = 0
+    ASM_ERROR_CODE_INVALID_RW_POINTER,            // invalid r/w pointer
+    
+}ASM_ERROR_CODE;
+
+//////////////////ASM API/////////////////////////////
+
+//#define ASM_SendTriggerCmd(core,tc) {kal_uint32 val;ASM_SET_SWLA_TRIG(core,tc);ASM_GET_SWLA_TRIG(core,val);}
+
+void ASM_GetBufferInfor(kal_uint32 core,kal_uint32* addr,kal_uint32* size, kal_uint32* read_addr, kal_uint32* write_addr);
+ASM_ERROR_CODE ASM_GetBufReadWriteAddress(kal_uint32 core,kal_uint32* rd_addr, kal_uint32* wr_addr,kal_uint32 *remain_size);
+void ASM_UpdateBufReadAddress(kal_uint32 core,kal_uint32 addr);
+
+void ASM_GetBufReadWritePtr(kal_uint32 core,kal_uint32* rd_ptr, kal_uint32* wr_ptr);
+kal_uint32 ASM_GetBufferSettingSize(kal_uint32 core);
+kal_bool ASM_BufferIsWrap(kal_uint32 core);
+void ASM_UpdateBufReadPtr(kal_uint32 core,kal_uint32 addr);
+
+
+ASM_ERROR_CODE ASM_InitSetting(kal_uint32 core,kal_uint32 mode, kal_uint32 *buffer,kal_uint32 buffer_size,kal_uint32 option_en,kal_uint32 sampling_rate);
+ASM_ERROR_CODE ASM_Start(kal_uint32 core);
+ASM_ERROR_CODE ASM_Stop(kal_uint32 core);
+void ASM_StopWithoutWaitIdle(kal_uint32 core);
+void ASM_SetSwtrTc(kal_uint32 core,kal_uint32 value);
+ASM_ERROR_CODE ASM_SetMcuSwtrAuto(kal_uint32 core);
+
+void ASM_McuIntRegsterLISR(void* reg_lisr);
+void ASM_McuIntIRQUnMask(void);
+void ASM_McuIntIRQMask(void);
+void ASM_McuCoreIntIRQMask(kal_uint32 core);
+void ASM_McuCoreIntIRQUnMask(kal_uint32 core);
+void ASM_McuCoreIntIRQAck(kal_uint32 core);
+void ASM_GetMcuIntStatusAndMask(kal_uint32* status,kal_uint32* mask);
+
+void Asm_InitInforAllCore(void);
+ASM_ERROR_CODE ASM_SetAddon(kal_uint32 core,kal_uint32 tc,kal_uint32* addon_infor,kal_uint32 size,kal_uint32 start_index );
+kal_uint32 ASM_GetBufferWrapCnt(kal_uint32 core);
+void ASM_EnableApbWrite(kal_uint32 core);
+void ASM_DisableApbWrite(kal_uint32 core);
+void ASM_SendTrigger(kal_uint32 core,kal_uint32 tc);
+
+//extern ASM_STRUCT Asm_Infor[];
+//void ASM_SendTrigger(kal_uint32 core, kal_uint32 tc);
+//#define ASM_SendTrigger(core,tc) {Asm_Infor[core].trigger_cnt++; ASM_SET_GCR_SWLA_TRIG(core,tc);}
+//#define ASM_SendTrigger(core,tc) {Asm_Infor[core].trigger_cnt++; ASM_SET_SWLA_TRIG(core,tc);}
+#define ASM_SendAPBTrigger(core,tc)  ASM_SET_SWLA_TRIG(core,tc)
+#define ASM_SendGCRTrigger(core,tc)  ASM_SET_GCR_SWLA_TRIG(core,tc)
+
+kal_uint32 ASM_GetPDICnt(kal_uint32 core);
+
+void ASM_SaveConfigForSPM_AllCore(void);
+void ASM_SaveCoreConfigForSPM(void);
+void ASM_SaveConfigForSPM(kal_uint32 core);
+void ASM_RestoreConfigforSPM_AllCore(void);
+void ASM_RestoreCoreConfigforSPM(void);
+void ASM_RestoreConfigforSPM(kal_uint32 core);
+
+void ASM_SetTCContextID(kal_uint32 core, kal_uint32 tc,kal_uint32 id);
+kal_uint32 ASM_GetTcContextId(kal_uint32 core,kal_uint32 tc);
+
+kal_uint32 ASM_GetSRAMWaterLevel(kal_uint32 core);
+void ASM_SetDumpRegion(void);
+
+
+
+#endif  //__DRV_ASM_H__
diff --git a/mcu/interface/driver/devdrv/btdma/btdma_callback_reg.h b/mcu/interface/driver/devdrv/btdma/btdma_callback_reg.h
new file mode 100644
index 0000000..febe208
--- /dev/null
+++ b/mcu/interface/driver/devdrv/btdma/btdma_callback_reg.h
@@ -0,0 +1,3 @@
+//BTDMA_CALLBACK_REGISTER(YOUR_KEY_NAME,YOUR_CALLBACK_FUNCTION_NAME)
+
+BTDMA_CALLBACK_REGISTER(DSP_LOADER, DSP_BTDMACB)
diff --git a/mcu/interface/driver/devdrv/btdma/btdma_public.h b/mcu/interface/driver/devdrv/btdma/btdma_public.h
new file mode 100644
index 0000000..ad5f43b
--- /dev/null
+++ b/mcu/interface/driver/devdrv/btdma/btdma_public.h
@@ -0,0 +1,155 @@
+#ifndef _BTDMA_PUBLIC_H_
+#define _BTDMA_PUBLIC_H_
+
+
+typedef kal_uint32 btdma_uint32;
+typedef kal_int32  btdma_int32 ;
+typedef kal_uint8  btdma_uint8 ;
+
+typedef enum BTDMA_PRIORITY_CHAIN
+{
+  PRIORITY_0 = 0,
+  PRIORITY_1    ,
+  PRIORITY_2    ,
+  PRIORITY_3    ,
+  PRIORITY_4    ,
+  PRIORITY_5    ,
+  PRIORITY_6    ,
+  PRIORITY_7
+
+} btdma_priority_chain;
+
+typedef enum BTDMA_IP
+{
+  TTBIT = 0  ,
+  SFBIT      ,
+  OTEBIT   
+} btdma_ip;
+
+typedef enum BTDMA_CORE
+{
+  UNGATE_VCORE  = 0  ,
+  UNGATE_MCORE0 = 2  ,
+  UNGATE_MCORE1 = 3   
+} btdma_core;
+
+typedef enum BTDMA_CALLBACK
+{
+  #undef BTDMA_CALLBACK_REGISTER
+  #define BTDMA_CALLBACK_REGISTER(KEY,CALLBACK) KEY,
+  #include "btdma_callback_reg.h"
+  #undef BTDMA_CALLBACK_REGISTER
+  BTDMA_CALLBACK_NUM
+} btdma_callback_index;
+
+
+typedef struct BTDMA_DESCRIPTION
+{
+  btdma_uint32          source_address                    ;
+  btdma_uint32          target_address                    ;
+  btdma_uint32          crc32                             ;
+  btdma_uint32          length                :19         ;
+  btdma_uint32          reserved_1            :5          ;
+  btdma_uint32          crc_enable            :1          ;
+  btdma_ip              src_ip                :2          ;
+  btdma_ip              dest_ip               :2          ;
+  btdma_uint32          reserved_2            :3          ;
+  btdma_uint32          signal_enable         :14         ;
+  btdma_uint32          reserved_5            :10         ;
+  btdma_uint32          axi_qos_r_ultra       :2          ;
+  btdma_uint32          axi_qos_r_flush       :2          ;
+  btdma_uint32          axi_qos_w_ultra       :2          ;
+  btdma_uint32          axi_qos_w_flush       :2          ;
+  btdma_callback_index  callback_key                      ;
+  btdma_uint32          caller                            ;
+  btdma_uint8           job_num               :4          ;
+  btdma_uint32          reserved_6            :20         ;
+  btdma_uint8           own                               ;
+} btdma_description;
+
+#define BTDMA_NO_SIGNAL_ENABLE                       (0)
+#define BTDMA_MCORE0_BOOTDONE_ENABLE                 (1 << 0)
+#define BTDMA_MCORE1_BOOTDONE_ENABLE                 (1 << 1)
+#define BTDMA_VCORE0_BOOTDONE_ENABLE                 (1 << 2)
+#define BTDMA_MCORE0_INTERRUPT_ENABLE                (1 << 3)
+#define BTDMA_MCORE1_INTERRUPT_ENABLE                (1 << 4)
+#define BTDMA_L1CORE_INTERRUPT_ENABLE                (1 << 5)
+
+
+#define BTDMA_MCORE0_TH0_COMPLETE_ENABLE             (1 << 6)
+#define BTDMA_MCORE1_TH0_COMPLETE_ENABLE             (1 << 7)
+#define BTDMA_MCORE0_TH1_COMPLETE_ENABLE             (1 << 8)
+#define BTDMA_MCORE1_TH1_COMPLETE_ENABLE             (1 << 9)
+#define BTDMA_MCORE0_TH2_COMPLETE_ENABLE             (1 << 10)
+#define BTDMA_MCORE1_TH2_COMPLETE_ENABLE             (1 << 11)
+#define BTDMA_MCORE0_TH3_COMPLETE_ENABLE             (1 << 12)
+#define BTDMA_MCORE1_TH3_COMPLETE_ENABLE             (1 << 13)
+
+#define BTDMA_MCORE_TH_COMPLETE_ENABLE               (1 << 6)
+
+
+#define BTDMA_Trigger_User(source_addr,source_ip,target_addr,target_ip,length,BTDMA_L1CORE_INTERRUPT_ENABLE,priority,callback_key)
+
+void SS_BTDMA_Trigger(btdma_description* desc,
+		      btdma_priority_chain priority,
+		      btdma_callback_index callback_key);
+void BTDMA_MPU_EMI_Region_Set(btdma_uint32 start_address,btdma_uint32 end_address);
+
+void BTDMA_SW_Enable_Ungate_Signal(btdma_core core);
+void BTDMA_SW_Disable_Ungate_Signal(btdma_core core);
+void BTDMA_Init();
+void BTDMA_Polling_Priority_idle(btdma_uint32 priority);
+
+/***************************************************
+*
+*
+*  Marco for assign descriptor
+*
+*
+***************************************************/
+#define DESCRIPTION_ASSIGN(SA,TA,SIZE,SE)         \
+.source_address = SA     ,                        \
+.target_address = TA     ,                        \
+.crc32          = 0      ,                        \
+.length         = SIZE   ,                        \
+.signal_enable  = SE     ,                        \
+.src_ip         = OTEBIT    ,                     \
+.dest_ip        = OTEBIT   ,                      \
+.own            = 0xA5
+
+
+#define DESCRIPTION_ASSIGN_CRC(SA,SIP,TA,TIP,SIZE,SE,CRC)        \
+.source_address = SA     ,                                       \
+.target_address = TA     ,                                       \
+.crc32          = CRC    ,                                       \
+.length         = SIZE   ,                                       \
+.signal_enable  = SE     ,                                       \
+.crc_enable     = 1      ,                                       \
+.src_ip         = SIP    ,                                       \
+.dest_ip        = TIP   ,                                        \
+.own            = 0xA5
+
+#define DESCRIPTION_ASSIGN_NO_CRC(SA,SIP,TA,TIP,SIZE,SE)         \
+.source_address = SA     ,                                       \
+.target_address = TA     ,                                       \
+.length         = SIZE   ,                                       \
+.signal_enable  = SE     ,                                       \
+.crc_enable     = 0      ,                                       \
+.src_ip         = SIP    ,                                       \
+.dest_ip        = TIP   ,                                        \
+.own            = 0xA5
+
+
+
+#define DESCRIPTION_END                           \
+.source_address = 0,                              \
+.target_address = 0,                              \
+.crc32          = 0,                              \
+.length         = 0,                              \
+.crc_enable     = 0,                              \
+.src_ip         = TTBIT,                          \
+.dest_ip        = TTBIT,                          \
+.own            = 0
+
+
+#endif
diff --git a/mcu/interface/driver/devdrv/busmon/md93/busmon_reg.h b/mcu/interface/driver/devdrv/busmon/md93/busmon_reg.h
new file mode 100644
index 0000000..866e8b5
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmon/md93/busmon_reg.h
@@ -0,0 +1,538 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2013
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   busmon_reg.h
+ *
+ * Project:
+ * --------
+ *   MOLY
+ *
+ * Description:
+ * ------------
+ *   Busmon register definition
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 10 30 2017 liang.yan
+ * [MOLY00285812] [MT6295M]Patch back CL4112332 from MT6295M.DEV to TRUNK
+ *
+ * 10 25 2017 liang.yan
+ * [MOLY00285147] [MT6765]Update busmon build option for cervino
+ *
+ * 08 25 2017 liang.yan
+ * [MOLY00273772] [Sylvia]Add Sylvia build option for bus monitor driver
+ *
+ * 06 09 2017 liang.yan
+ * [MOLY00244888] [ZION]Bus monitor driver build error call for check in
+ * 	
+ * 	[UMOLYA]Merge ZION project defining
+ *
+ * 03 02 2017 liang.yan
+ * [MOLY00232074] [Change Feature][BIANCO]Adding busmon monitor MO port Latency feature
+ *
+ * 08 05 2016 liang.yan
+ * [MOLY00195782] [Change Feature]93 busmon driver update
+ *
+ * 03 30 2016 i-chun.liu
+ * [MOLY00171939] 93 Busmon check in
+ * busmon check in .
+ *
+ * 01 29 2016 i-chun.liu
+ * [MOLY00163360] Busmon driver update
+ * fix code defect for ahb_busmon.
+ *
+ * 08 17 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * bus monitor update for ELBRUS.
+ *
+ * 06 09 2015 i-chun.liu
+ * [MOLY00119728] JADE bring up call for check in  (MDCIRQ and Bus monitor )
+ * JADE PCORE BUSMON.
+ *
+ * 04 07 2015 i-chun.liu
+ * [MOLY00106215] TK6291 bus monitor driver update
+ * Pcore bus monitor driver update.
+ *
+ * 12 17 2014 i-chun.liu
+ * [MOLY00087840] Update Moly bus monitor driver for denali1
+ * Moly bus monitor driver update.
+ *
+ * 07 29 2014 brian.chiang
+ * [MOLY00070757] busmon drvier update
+ * Bus monitor driver enhancement
+ *
+ * 04 23 2014 brian.chiang
+ * [MOLY00063514] 6595 busmon driver
+ * 6595 busmon deriver porting
+ *
+ * 12 06 2013 vend_brian.chiang
+ * [MOLY00041938] Fix ATEST linking error
+ * Merge MT6595_E1_DEV  into MOLY trunk
+ *
+ * 03 29 2013 vend_hsientang.lee
+ * [MOLY00013013] Add Busmon driver
+ *
+ ****************************************************************************/
+
+#ifndef __BUSMON_REG_H__
+#define __BUSMON_REG_H__
+#include <reg_base.h>
+
+
+//#define    DEBUG_APB
+
+/*Add MT6295M define only for build, need update when 95 busmon driver ready*/
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)||defined(MT6765)||defined(MT6295M)
+
+#define BASE_DEBUGAPB_MDMCU_AXIMON0      (BASE_MADDR_DBGSYS_1 + 0x6000)
+#define BASE_DEBUGAPB_MDINFRA_AXIMON0    (BASE_MADDR_DBGSYS_1 + 0x8000)
+    
+#if defined(DEBUG_APB)
+#define BASE_ADDR_MDMAXIMON0           BASE_DEBUGAPB_MDMCU_AXIMON0
+#define BASE_MADDR_MDMCU_AXIMON        BASE_DEBUGAPB_MDMCU_AXIMON0
+#define BASE_MADDR_MDINFRA_AXIMON      BASE_DEBUGAPB_MDINFRA_AXIMON0
+#define BASE_ADDR_MDMCUSYS             BASE_DEBUGAPB_MDMCU_AXIMON0
+#define BASE_ADDR_MDPERISYS            BASE_DEBUGAPB_MDINFRA_AXIMON0    
+#else /* Normal APB */
+#define BASE_ADDR_MDMAXIMON0           BASE_MADDR_MDMCU_BUSMON
+#define BASE_MADDR_MDMCU_AXIMON        BASE_MADDR_MDMCU_BUSMON
+#define BASE_MADDR_MDINFRA_AXIMON      BASE_MADDR_MDINFRABUSMON
+#define BASE_ADDR_MDMCUSYS             BASE_MADDR_MDMCU_BUSMON
+#define BASE_ADDR_MDPERISYS            BASE_MADDR_MDINFRABUSMON    
+#endif
+
+#endif /*MT6763*/	
+    
+/*
+ * AXI Bus Monitor
+ */
+#define AXIMON_BASE                             (0)
+
+#define AXIMON_COD_VERSION                      (AXIMON_BASE + 0x0000)
+#define AXIMON_DMY_REG                          (AXIMON_BASE + 0x0004)
+#define AXIMON_CTL                              (AXIMON_BASE + 0x0010)
+#define AXIMON_TST                              (AXIMON_BASE + 0x0014)
+#define AXIMON_STS                              (AXIMON_BASE + 0x0018)
+#define AXIMON_INT                              (AXIMON_BASE + 0x0020)
+#define AXIMON_INT_MSK                          (AXIMON_BASE + 0x0024)
+
+#define AXIMON_IP0_TG                           (AXIMON_BASE + 0x0030)
+#define AXIMON_IP0_TMR                          (AXIMON_BASE + 0x0034)
+#define AXIMON_IP0_ID_CTL                       (AXIMON_BASE + 0x0040)
+#define AXIMON_IP0_VPE                          (AXIMON_BASE + 0x0044)
+#define AXIMON_IP0_ADDR                         (AXIMON_BASE + 0x0048)
+#define AXIMON_IP0_ADDRMSK                      (AXIMON_BASE + 0x004C)
+#define AXIMON_IP0_DATA                         (AXIMON_BASE + 0x0050)
+#define AXIMON_IP0_DATAMSK                      (AXIMON_BASE + 0x0060)
+
+#define AXIMON_IP_TG_OFFSET                           (0x0030)
+#define AXIMON_IP_TMR_OFFSET                          (0x0034)
+#define AXIMON_IP_ID_CTL_OFFSET                       (0x0040)
+#define AXIMON_IP_VPE_OFFSET                          (0x0044)
+#define AXIMON_IP_ADDR_OFFSET                         (0x0048)
+#define AXIMON_IP_ADDRMSK_OFFSET                      (0x004C)
+#define AXIMON_IP_DATA_OFFSET                         (0x0050)
+#define AXIMON_IP_DATAMSK_OFFSET                      (0x0060)
+
+
+#define AXIMON_IP1_TG                           (AXIMON_BASE + 0x0070)
+#define AXIMON_IP1_TMR                          (AXIMON_BASE + 0x0074)
+#define AXIMON_IP1_ID_CTL                       (AXIMON_BASE + 0x0080)
+#define AXIMON_IP1_VPE                          (AXIMON_BASE + 0x0084)
+#define AXIMON_IP1_ADDR                         (AXIMON_BASE + 0x0088)
+#define AXIMON_IP1_ADDRMSK                      (AXIMON_BASE + 0x008C)
+#define AXIMON_IP1_DATA                         (AXIMON_BASE + 0x0090)
+#define AXIMON_IP1_DATAMSK                      (AXIMON_BASE + 0x00A0)
+
+
+#define AXIMON_TOT_BUS_CYC                      (AXIMON_BASE + 0x0100)
+
+#define AXIMON_IP0_NON_OV_TRANS_NUM             (AXIMON_BASE + 0x0200)
+#define AXIMON_IP0_OV_TRANS_NUM                 (AXIMON_BASE + 0x0204)
+#define AXIMON_IP0_NON_WGT_TRANS_CYC            (AXIMON_BASE + 0x0208)
+#define AXIMON_IP0_WGT_TRANS_CYC                (AXIMON_BASE + 0x020C)
+#define AXIMON_IP0_MAX_TRANS_CYC                (AXIMON_BASE + 0x0210)
+#define AXIMON_IP0_MAX_OST_TRANS_NUM            (AXIMON_BASE + 0x0214)
+
+#define AXIMON_IP0_SNAP_INFO0                   (AXIMON_BASE + 0x0300)
+#define AXIMON_IP0_SNAP_INFO1                   (AXIMON_BASE + 0x0304) 
+#define AXIMON_IP0_SNAP_INFO2                   (AXIMON_BASE + 0x0308)
+#define AXIMON_IP0_SNAP_INFO3                   (AXIMON_BASE + 0x030C)
+#define AXIMON_IP0_SNAP_INFO4                   (AXIMON_BASE + 0x0310)
+#define AXIMON_IP0_SNAP_INFO5                   (AXIMON_BASE + 0x0314)
+#define AXIMON_IP0_SNAP_INFO6                   (AXIMON_BASE + 0x0318)
+#define AXIMON_IP0_SNAP_INFO7                   (AXIMON_BASE + 0x031C)
+#define AXIMON_IP0_SNAP_INFO8                   (AXIMON_BASE + 0x0320)
+#define AXIMON_IP0_SNAP_INFO9                   (AXIMON_BASE + 0x0324)
+#define AXIMON_IP0_SNAP_INFO10                  (AXIMON_BASE + 0x0328)
+#define AXIMON_IP0_SNAP_INFO11                  (AXIMON_BASE + 0x032C)
+
+#define AXIMON_IP1_NON_OV_TRANS_NUM             (AXIMON_BASE + 0x0400)
+#define AXIMON_IP1_OV_TRANS_NUM                 (AXIMON_BASE + 0x0404)
+#define AXIMON_IP1_NON_WGT_TRANS_CYC            (AXIMON_BASE + 0x0408)
+#define AXIMON_IP1_WGT_TRANS_CYC                (AXIMON_BASE + 0x040C)
+#define AXIMON_IP1_MAX_TRANS_CYC                (AXIMON_BASE + 0x0410)
+#define AXIMON_IP1_MAX_OST_TRANS_NUM            (AXIMON_BASE + 0x0414)
+
+#define AXIMON_IP1_SNAP_INFO0                   (AXIMON_BASE + 0x0500)
+#define AXIMON_IP1_SNAP_INFO1                   (AXIMON_BASE + 0x0504) 
+#define AXIMON_IP1_SNAP_INFO2                   (AXIMON_BASE + 0x0508)
+#define AXIMON_IP1_SNAP_INFO3                   (AXIMON_BASE + 0x050C)
+#define AXIMON_IP1_SNAP_INFO4                   (AXIMON_BASE + 0x0510)
+#define AXIMON_IP1_SNAP_INFO5                   (AXIMON_BASE + 0x0514)
+#define AXIMON_IP1_SNAP_INFO6                   (AXIMON_BASE + 0x0518)
+#define AXIMON_IP1_SNAP_INFO7                   (AXIMON_BASE + 0x051C)
+#define AXIMON_IP1_SNAP_INFO8                   (AXIMON_BASE + 0x0520)
+#define AXIMON_IP1_SNAP_INFO9                   (AXIMON_BASE + 0x0524)
+#define AXIMON_IP1_SNAP_INFO10                  (AXIMON_BASE + 0x0528)
+#define AXIMON_IP1_SNAP_INFO11                  (AXIMON_BASE + 0x052C)
+
+#define AXIMON_CFG_OFFSET                       (0x40)
+#define AXIMON_INFO_OFFSET                      (0x200)
+
+#define AXIMON_IP_NON_OV_TRANS_NUM_OFFSET             (0x0200)
+#define AXIMON_IP_OV_TRANS_NUM_OFFSET                 (0x0204)
+#define AXIMON_IP_NON_WGT_TRANS_CYC_OFFSET            (0x0208)
+#define AXIMON_IP_WGT_TRANS_CYC_OFFSET                (0x020C)
+#define AXIMON_IP_MAX_TRANS_CYC_OFFSET                (0x0210)
+#define AXIMON_IP_MAX_OST_TRANS_NUM_OFFSET            (0x0214)
+
+#define AXIMON_IP_SNAP_INFO0_OFFSET                   (0x0300)
+#define AXIMON_IP_SNAP_INFO1_OFFSET                   (0x0304) 
+#define AXIMON_IP_SNAP_INFO2_OFFSET                   (0x0308)
+#define AXIMON_IP_SNAP_INFO3_OFFSET                   (0x030C)
+#define AXIMON_IP_SNAP_INFO4_OFFSET                   (0x0310)
+#define AXIMON_IP_SNAP_INFO5_OFFSET                   (0x0314)
+#define AXIMON_IP_SNAP_INFO6_OFFSET                   (0x0318)
+#define AXIMON_IP_SNAP_INFO7_OFFSET                   (0x031C)
+#define AXIMON_IP_SNAP_INFO8_OFFSET                   (0x0320)
+#define AXIMON_IP_SNAP_INFO9_OFFSET                   (0x0324)
+#define AXIMON_IP_SNAP_INFO10_OFFSET                  (0x0328)
+#define AXIMON_IP_SNAP_INFO11_OFFSET                  (0x032C)
+
+/* Default Vaule */
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)||defined(MT6765)||defined(MT6295M)
+#define AXIMON_COD_VERSION_DEFAULT              (0x20160608)
+#define AXIMON_TST_DEFAULT                      (0x0000000A)
+#endif	//MT6763
+
+/* Bit Field & Mask */
+#define AXIMON_CODA_VERSION_MASK                (0xFFFFFFFF)   /* [31:0] */
+#define AXIMON_CODA_VERSION_SHIFT               (0)            /* [31:0] */
+
+#define AXIMON_CTL_START_MASK                   (0x1)          /* [0] */
+#define AXIMON_CTL_START_SHIFT                  (0)            /* [0] */
+
+#define AXIMON_TST_SEQ_TRG_MODE_MASK            (0x1)          /* [0] */
+#define AXIMON_TST_SEQ_TRG_MODE_SHIFT           (0)            /* [0] */
+#define AXIMON_TST_SEQ_CHECK_MODE_MASK          (0x1)          /* [1] */
+#define AXIMON_TST_SEQ_CHECK_MODE_SHIFT         (1)            /* [1] */
+#define AXIMON_TST_DISABLE_CG_MASK              (0x1)          /* [2] */
+#define AXIMON_TST_DISABLE_CG_SHIFT             (2)            /* [2] */
+#define AXIMON_TST_CLEAR_AT_BUSIDLE_MASK        (0x1)          /* [3] */
+#define AXIMON_TST_CLEAR_AT_BUSIDLE_SHIFT       (3)            /* [3] */
+#define AXIMON_TST_SPEED_SIM_MASK               (0x1)          /* [8] */
+#define AXIMON_TST_SPEED_SIM_SHIFT              (8)            /* [8] */
+#define AXIMON_TST_LYR_AXI_SEL_MASK             (0xF)          /* [19:16] */
+#define AXIMON_TST_LYR_AXI_SEL_SHIFT            (16)           /* [19:16] */
+
+
+#define AXIMON_STS_STAT0_MASK                   (0x3)          /* [1:0] */
+#define AXIMON_STS_STAT0_SHIFT                  (0)            /* [1:0] */
+#define AXIMON_STS_STAT1_MASK                   (0x3)          /* [5:4] */
+#define AXIMON_STS_STAT1_SHIFT                  (4)            /* [5:4] */
+#define AXIMON_STS_IP0_CUR_OVERFLOW_MASK        (0x1)          /* [8] */
+#define AXIMON_STS_IP0_CUR_OVERFLOW_SHIFT       (8)            /* [8] */
+#define AXIMON_STS_IP0_CUR_UNDERFLOW_MASK       (0x1)          /* [9] */
+#define AXIMON_STS_IP0_CUR_UNDERFLOW_SHIFT      (9)            /* [9] */
+#define AXIMON_STS_IP1_CUR_OVERFLOW_MASK        (0x1)          /* [10] */
+#define AXIMON_STS_IP1_CUR_OVERFLOW_SHIFT       (10)           /* [10] */
+#define AXIMON_STS_IP1_CUR_UNDERFLOW_MASK       (0x1)          /* [11] */
+#define AXIMON_STS_IP1_CUR_UNDERFLOW_SHIFT      (11)           /* [11] */
+#define AXIMON_STS_IP0_HIS_OVERFLOW_MASK        (0x1)          /* [12] */
+#define AXIMON_STS_IP0_HIS_OVERFLOW_SHIFT       (12)           /* [12] */
+#define AXIMON_STS_IP0_HIS_UNDERFLOW_MASK       (0x1)          /* [13] */
+#define AXIMON_STS_IP0_HIS_UNDERFLOW_SHIFT      (13)           /* [13] */
+#define AXIMON_STS_IP1_HIS_OVERFLOW_MASK        (0x1)          /* [14] */
+#define AXIMON_STS_IP1_HIS_OVERFLOW_SHIFT       (14)           /* [14] */
+#define AXIMON_STS_IP1_HIS_UNDERFLOW_MASK       (0x1)          /* [15] */
+#define AXIMON_STS_IP1_HIS_UNDERFLOW_SHIFT      (15)           /* [15] */
+#define AXIMON_STS_IP0_CUR_ID_MISS_MASK         (0x1)          /* [16] */
+#define AXIMON_STS_IP0_CUR_ID_MISS_SHIFT        (16)           /* [16] */
+#define AXIMON_STS_IP1_CUR_ID_MISS_MASK         (0x1)          /* [17] */
+#define AXIMON_STS_IP1_CUR_ID_MISS_SHIFT        (17)           /* [17] */
+#define AXIMON_STS_IP0_HIS_ID_MISS_MASK         (0x1)          /* [18] */
+#define AXIMON_STS_IP0_HIS_ID_MISS_SHIFT        (18)           /* [18] */
+#define AXIMON_STS_IP1_HIS_ID_MISS_MASK         (0x1)          /* [19] */
+#define AXIMON_STS_IP1_HIS_ID_MISS_SHIFT        (19)           /* [19] */
+#define AXIMON_STS_IP_TRG_INT_MASK              (0x1)          /* [20] */
+#define AXIMON_STS_IP_TRG_INT_SHIFT             (20)           /* [20] */
+#define AXIMON_STS_MON_REALENABLE_MASK          (0x1)          /* [31] */
+#define AXIMON_STS_MON_REALENABLE_SHIFT         (31)           /* [31] */
+
+#define AXIMON_STS_IP0_CUR_OVERFLOW           (1U << AXIMON_STS_IP0_CUR_OVERFLOW_SHIFT)
+#define AXIMON_STS_IP0_CUR_UNDERFLOW          (1U << AXIMON_STS_IP0_CUR_UNDERFLOW_SHIFT)
+#define AXIMON_STS_IP1_CUR_OVERFLOW           (1U << AXIMON_STS_IP1_CUR_OVERFLOW_SHIFT)
+#define AXIMON_STS_IP1_CUR_UNDERFLOW          (1U << AXIMON_STS_IP1_CUR_UNDERFLOW_SHIFT)
+#define AXIMON_STS_IP0_CUR_ID_MISS            (1U << AXIMON_STS_IP0_CUR_ID_MISS_SHIFT)
+#define AXIMON_STS_IP1_CUR_ID_MISS            (1U << AXIMON_STS_IP1_CUR_ID_MISS_SHIFT)
+#define AXIMON_STS_IP0_HIS_OVERFLOW           (1U << AXIMON_STS_IP0_HIS_OVERFLOW_SHIFT)
+#define AXIMON_STS_IP0_HIS_UNDERFLOW          (1U << AXIMON_STS_IP0_HIS_UNDERFLOW_SHIFT)
+#define AXIMON_STS_IP1_HIS_OVERFLOW           (1U << AXIMON_STS_IP1_HIS_OVERFLOW_SHIFT)
+#define AXIMON_STS_IP1_HIS_UNDERFLOW          (1U << AXIMON_STS_IP1_HIS_UNDERFLOW_SHIFT)	
+#define AXIMON_STS_IP0_HIS_ID_MISS            (1U << AXIMON_STS_IP0_HIS_ID_MISS_SHIFT)
+#define AXIMON_STS_IP1_HIS_ID_MISS            (1U << AXIMON_STS_IP1_HIS_ID_MISS_SHIFT)	
+#define AXIMON_STS_MON_REALENABLE             (1U << AXIMON_STS_MON_REALENABLE_SHIFT)
+
+#define AXIMON_INT_MASK                         (0x1)          /* [0] */
+#define AXIMON_INT_SHIFT                        (0)            /* [0] */
+
+#define AXIMON_INT_MSK_MASK                     (0x1)          /* [0] */
+#define AXIMON_INT_MSK_SHIFT                    (0)            /* [0] */
+
+#define AXIMON_TG_MON_RWSEL_MASK                (0x1)          /* [8] */
+#define AXIMON_TG_MON_RWSEL_SHIFT               (8)            /* [8] */
+#define AXIMON_TG_MON_MODE_MASK                 (0x1)          /* [9] */
+#define AXIMON_TG_MON_MODE_SHIFT                (9)            /* [9] */
+#define AXIMON_TG_MON_ENABLE_MASK               (0x1)          /* [10] */
+#define AXIMON_TG_MON_ENABLE_SHIFT              (10)           /* [10] */
+#define AXIMON_TG_TRG_MODE_MASK                 (0x1)          /* [11] */
+#define AXIMON_TG_TRG_MODE_SHIFT                (11)           /* [11] */
+#define AXIMON_TG_MON_ALL_MST_MASK              (0x1)          /* [12] */
+#define AXIMON_TG_MON_ALL_MST_SHIFT             (12)            /* [12] */
+#define AXIMON_TG_SNAP_DATA_ENABLE_MASK         (0x1)          /* [13] */
+#define AXIMON_TG_SNAP_DATA_ENABLE_SHIFT        (13)            /* [13] */
+#define AXIMON_TG_MON_CNT_MASK                  (0xFFFF)       /* [31:16] */
+#define AXIMON_TG_MON_CNT_SHIFT                 (16)           /* [31:16] */
+
+#define AXIMON_TMR_MON_TRG_CYC_MASK             (0xFFFF)       /* [15:0] */ /* R_IPx_AXIMON_TMR */
+#define AXIMON_TMR_MON_TRG_CYC_SHIFT            (0)            /* [15:0] */
+
+/* R_IPx_AXIMON_ID */
+#define AXIMON_ID_MON_MASTER_MASK               (0xFFFF)       /* [15:0] */ 
+#define AXIMON_ID_MON_MASTER_SHIFT              (0)            /* [15:0] */
+#define AXIMON_ID_MON_MASTER_MSK_MASK           (0xFFFF)       /* [31:16] */ 
+#define AXIMON_ID_MON_MASTER_MSK_SHIFT          (16)            /* [31:16] */
+
+/* R_IPx_AXIMON_VPE */
+#define AXIMON_VPE_MON_VPE_MASK                 (0x7)           /* [2:0] */ 
+#define AXIMON_VPE_MON_VPE_SHIFT                (0)             /* [2:0] */
+#define AXIMON_VPE_MON_VPE_MSK_MASK             (0x7)           /* [6:4] */ 
+#define AXIMON_VPE_MON_VPE_MSK_SHIFT            (4)             /* [6:4] */
+#define AXIMON_VPE_MON_ULTRA_MASK               (0x3)           /* [9:8] */ 
+#define AXIMON_VPE_MON_ULTRA_SHIFT              (8)             /* [9:8] */
+#define AXIMON_VPE_MON_ULTRA_MSK_MASK           (0x3)           /* [13:12] */ 
+#define AXIMON_VPE_MON_ULTRA_MSK_SHIFT          (12)            /* [13:12] */
+
+#define AXIMON_ADDR_MASK                        (0xFFFFFFFF)   /* [31:0] */
+#define AXIMON_ADDR_SHIFT                       (0)            /* [31:0] */
+
+#define AXIMON_ADDRMSK_MASK                     (0xFFFFFFFF)   /* [31:0] */
+#define AXIMON_ADDRMSK_SHIFT                    (0)            /* [31:0] */
+
+/* For IPx_AXIMON_DATA */
+#define AXIMON_DATA_MASK                       (0xFFFFFFFF)   /* [31:0] */
+#define AXIMON_DATA_SHIFT                      (0)            /* [31:0] */
+
+/* For IPx_AXIMON_DATAMSK */
+#define AXIMON_DATAMSK_MASK                    (0xFFFFFFFF)   /* [31:0] */
+#define AXIMON_DATAMSK_SHIFT                   (0)            /* [31:0] */
+
+#define AXIMON_TOT_BUS_CYC_MASK                 (0xFFFFFF)   /* [23:0] */
+#define AXIMON_TOT_BUS_CYC_SHIFT                (0)            /* [23:0] */
+
+#define AXIMON_NON_OV_TRANS_NUM_MASK            (0xFFFFFF)    /* [23:0] */
+#define AXIMON_NON_OV_TRANS_NUM_SHIFT           (0)            /* [23:0] */
+
+#define AXIMON_OV_TRANS_NUM_MASK                (0xFFFFFF)    /* [23:0] */
+#define AXIMON_OV_TRANS_NUM_SHIFT               (0)            /* [23:0] */
+
+#define AXIMON_NON_WGT_TRANS_CYC_MASK           (0xFFFFFFF)  /* [27:0] */
+#define AXIMON_NON_WGT_TRANS_CYC_SHIFT          (0)            /* [27:0] */
+
+#define AXIMON_WGT_TRANS_CYC_MASK               (0xFFFFFFFF)  /* [31:0] */
+#define AXIMON_WGT_TRANS_CYC_SHIFT              (0)            /* [31:0] */
+
+#define AXIMON_MAX_TRANS_CYC_MASK               (0xFFFFFF)    /* [23:0] */
+#define AXIMON_MAX_TRANS_CYC_SHIFT              (0)            /* [23:0] */
+
+#define AXIMON_MAX_OST_TRANS_NUM_MASK           (0x3F)         /* [5:0] */
+#define AXIMON_MAX_OST_TRANS_NUM_SHIFT          (0)            /* [5:0] */
+
+#define AXIMON_SNAP_INFO0_VPE_MASK              (0x7)          /* [2:0] */
+#define AXIMON_SNAP_INFO0_VPE_SHIFT             (0)             /* [2:0] */
+#define AXIMON_SNAP_INFO0_LEN_MASK              (0xF)           /* [7:4] */
+#define AXIMON_SNAP_INFO0_LEN_SHIFT             (4)             /* [7:4] */
+#define AXIMON_SNAP_INFO0_SIZE_MASK             (0x7)           /* [10:8] */
+#define AXIMON_SNAP_INFO0_SIZE_SHIFT            (8)             /* [10:8] */
+#define AXIMON_SNAP_INFO0_ULTRA_MASK            (0x3)           /* [13:12] */
+#define AXIMON_SNAP_INFO0_ULTRA_SHIFT           (12)            /* [13:12] */
+#define AXIMON_SNAP_INFO0_BURST_MASK            (0x3)           /* [17:16] */
+#define AXIMON_SNAP_INFO0_BURST_SHIFT           (16)            /* [17:16] */
+#define AXIMON_SNAP_INFO0_LOCK_MASK             (0x3)           /* [19:18] */
+#define AXIMON_SNAP_INFO0_LOCK_SHIFT            (18)            /* [19:18] */
+#define AXIMON_SNAP_INFO0_CACHE_MASK            (0xF)           /* [23:20] */
+#define AXIMON_SNAP_INFO0_CACHE_SHIFT           (20)            /* [23:20] */
+#define AXIMON_SNAP_INFO0_PROT_MASK             (0x7)           /* [26:24] */
+#define AXIMON_SNAP_INFO0_PROT_SHIFT            (24)            /* [26:24] */
+#define AXIMON_SNAP_INFO0_RESP_MASK             (0x3)           /* [29:28] */
+#define AXIMON_SNAP_INFO0_RESP_SHIFT            (28)            /* [29:28] */
+
+#define AXIMON_SNAP_INFO1_QID_MASK              (0xFFFF)        /* [15:0] */
+#define AXIMON_SNAP_INFO1_QID_SHIFT             (0)             /* [15:0] */
+#define AXIMON_SNAP_INFO1_CNT_MASK              (0xFFFF)       /* [31:16] */
+#define AXIMON_SNAP_INFO1_CNT_SHIFT             (16)            /* [31:16] */
+
+#define AXIMON_SNAP_INFO2_ADDRESS_MASK          (0xFFFFFFFF)   /* [31:0] */
+#define AXIMON_SNAP_INFO2_ADDRESS_SHIFT         (0)             /* [31:0] */
+
+#define AXIMON_SNAP_INFO3_STRB0_MASK            (0xFFFF)        /* [15:0] */
+#define AXIMON_SNAP_INFO3_STRB0_SHIFT           (0)             /* [15:0] */
+#define AXIMON_SNAP_INFO3_STRB1_MASK            (0xFFFF)        /* [31:16] */
+#define AXIMON_SNAP_INFO3_STRB1_SHIFT           (16)            /* [31:16] */
+
+#define AXIMON_SNAP_INFO4_DATA00_MASK           (0xFFFFFFFF)    /* [31:0] */
+#define AXIMON_SNAP_INFO4_DATA00_SHIFT          (0)             /* [31:0] */
+#define AXIMON_SNAP_INFO5_DATA01_MASK           (0xFFFFFFFF)    /* [31:0] */
+#define AXIMON_SNAP_INFO5_DATA01_SHIFT          (0)             /* [31:0] */
+#define AXIMON_SNAP_INFO6_DATA02_MASK           (0xFFFFFFFF)    /* [31:0] */
+#define AXIMON_SNAP_INFO6_DATA02_SHIFT          (0)             /* [31:0] */
+#define AXIMON_SNAP_INFO7_DATA03_MASK           (0xFFFFFFFF)    /* [31:0] */
+#define AXIMON_SNAP_INFO7_DATA03_SHIFT          (0)             /* [31:0] */
+
+#define AXIMON_SNAP_INFO8_DATA10_MASK           (0xFFFFFFFF)    /* [31:0] */
+#define AXIMON_SNAP_INFO8_DATA10_SHIFT          (0)             /* [31:0] */
+#define AXIMON_SNAP_INFO9_DATA11_MASK           (0xFFFFFFFF)    /* [31:0] */
+#define AXIMON_SNAP_INFO9_DATA11_SHIFT          (0)             /* [31:0] */
+#define AXIMON_SNAP_INFO10_DATA12_MASK          (0xFFFFFFFF)    /* [31:0] */
+#define AXIMON_SNAP_INFO10_DATA12_SHIFT         (0)             /* [31:0] */
+#define AXIMON_SNAP_INFO11_DATA13_MASK          (0xFFFFFFFF)    /* [31:0] */
+#define AXIMON_SNAP_INFO11_DATA13_SHIFT         (0)             /* [31:0] */
+
+#define AXIMON_SNAP_DATA_NUMBER                 (8)
+
+#define AXIMON_MATCH_NONE                       (0xFFFFFFFF)
+#define AXIMON_MATCH_ALL                        (0)
+
+#define AXIMON_MDMCU_LAYER_SELECT               (BASE_MADDR_MDPERIMISC + 0x504)
+#define AXIMON_MDINFRA_LAYER_SELECT             (BASE_MADDR_MDPERIMISC + 0x500)
+
+/* ************************************************************************************************
+Below is for Bus recorder 
+************************************************************************************************ */
+#define BUSREC_REG_RECORDER_CTL       (AXIMON_BASE + 0x700U)
+#define BUSREC_REG_RECORDER_TEST      (AXIMON_BASE + 0x704U)
+
+#define BUSREC_REG_IP0_BUFF_CNT       (AXIMON_BASE + 0x800U)
+#define BUSREC_REG_IP0_GRP1_ID_STS    (AXIMON_BASE + 0x900U) /* there 1~32 ID STS*/
+#define BUSREC_REG_IP0_GRP1_ADDR_STS  (AXIMON_BASE + 0x904U) /* there 1~32 ADDR STS*/
+#define BUSREC_REG_IP0_GRP1_ID_STS_(n)            (AXIMON_BASE + 0x900U + (n) * 0x8)
+#define BUSREC_REG_IP0_GRP1_ADDR_STS_(n)          (AXIMON_BASE + 0x904U + (n) * 0x8)
+
+#define BUSREC_REG_IP1_BUFF_CNT       (AXIMON_BASE + 0xA00U)
+#define BUSREC_REG_IP1_GRP1_ID_STS    (AXIMON_BASE + 0xB00U) /* there 1~32 ID STS*/
+#define BUSREC_REG_IP1_GRP1_ADDR_STS  (AXIMON_BASE + 0xB04U) /* there 1~32 ADDR STS*/
+#define BUSREC_REG_IP1_GRP1_ID_STS_(n)            (AXIMON_BASE + 0xB00U + (n) * 0x8)
+#define BUSREC_REG_IP1_GRP1_ADDR_STS_(n)          (AXIMON_BASE + 0xB04U + (n) * 0x8)
+
+#define BUSREC_STS_OFFSET             (0x8)
+
+#define BUSREC_REG_CURR_IP0_ID_STS   (AXIMON_BASE + 0xC00U)
+#define BUSREC_REG_CURR_IP0_ADDR_STS (AXIMON_BASE + 0xC04U)
+#define BUSREC_REG_CURR_IP0_CTRL_STS (AXIMON_BASE + 0xC08U)
+
+#define BUSREC_REG_CURR_IP1_ID_STS   (AXIMON_BASE + 0xC10U)
+#define BUSREC_REG_CURR_IP1_ADDR_STS (AXIMON_BASE + 0xC14U)
+#define BUSREC_REG_CURR_IP1_CTRL_STS (AXIMON_BASE + 0xC18U)
+
+/* REG_RECORDER_CTL */
+#define BUSREC_CTL_TEST_MODE_MASK                   (0x1)          /* [2] */
+#define BUSREC_CTL_TEST_MODE_SHIFT                  (2)            /* [2] */
+#define BUSREC_CTL_GATE_AR_MASK                     (0x1)          /* [4] */
+#define BUSREC_CTL_GATE_AR_SHIFT                    (4)            /* [4] */
+#define BUSREC_CTL_GATE_AW_MASK                     (0x1)          /* [5] */
+#define BUSREC_CTL_GATE_AW_SHIFT                    (5)            /* [5] */
+#define BUSREC_CTL_GATE_R_RESP_MASK                 (0x1)          /* [6] */
+#define BUSREC_CTL_GATE_R_RESP_SHIFT                (6)            /* [6] */
+#define BUSREC_CTL_GATE_B_RESP_MASK                 (0x1)          /* [7] */
+#define BUSREC_CTL_GATE_B_RESP_SHIFT                (7)            /* [7] */
+#define BUSREC_CTL_GATE_W_RESP_MASK                 (0x1)          /* [8] */
+#define BUSREC_CTL_GATE_W_RESP_SHIFT                (8)            /* [8] */
+
+/* REG_RECORDER_CTL */
+#define BUSREC_TEST_MODE            (1U << 2)
+#define BUSREC_GATE_AR_BIT          (4)
+#define BUSREC_GATE_AW_BIT          (5)
+#define BUSREC_GATE_R_RESP_BIT      (6)
+#define BUSREC_GATE_B_RESP_BIT      (7)	
+#define BUSREC_GATE_W_RESP_BIT      (8)	
+#define BUSREC_GATE_AR              (1U<<BUSREC_GATE_AR_BIT)
+#define BUSREC_GATE_AW              (1U<<BUSREC_GATE_AW_BIT)
+#define BUSREC_GATE_R_RESP          (1U<<BUSREC_GATE_R_RESP_BIT)
+#define BUSREC_GATE_B_RESP          (1U<<BUSREC_GATE_B_RESP_BIT)	
+#define BUSREC_GATE_W_RESP          (1U<<BUSREC_GATE_W_RESP_BIT)    
+
+/* REG_RECORDER_TEST */
+#define BUSREC_TEST_TRANS_ADD_MASK                   (0x1)          /* [0] */
+#define BUSREC_TEST_TRANS_ADD_SHIFT                  (0)            /* [0] */
+#define BUSREC_TEST_TRANS_ADD_ID_MASK                (0xFF)         /* [15:8] */
+#define BUSREC_TEST_TRANS_ADD_ID_SHIFT               (8)            /* [15:8] */
+#define BUSREC_TEST_TRANS_SUB_MASK                   (0x1)          /* [16] */
+#define BUSREC_TEST_TRANS_SUB_SHIFT                  (16)            /* [16] */
+#define BUSREC_TEST_TRANS_SUB_ID_MASK                (0xFF)         /* [31:24] */
+#define BUSREC_TEST_TRANS_SUB_ID_SHIFT               (24)            /* [31:24] */
+
+/* REG_RECORDER_TEST */
+#define BUSREC_TRANS_ADD            (1U << 0)
+#define BUSREC_ADD_ID_SHIFT         (8)
+#define BUSREC_ADD_ID_MASK          (0xFF)
+#define BUSREC_TRANS_SUB            (1U << 16)
+#define BUSREC_SUB_ID_SHIFT         (24)
+#define BUSREC_SUB_ID_MASK          (0xFF)
+
+/* ************************************************************************************************ 
+Above is for Bus recorder 
+************************************************************************************************ */
+
+#endif /* end of __BUSMON_REG_H__ */
+
diff --git a/mcu/interface/driver/devdrv/busmon/md93/drv_busmon.h b/mcu/interface/driver/devdrv/busmon/md93/drv_busmon.h
new file mode 100644
index 0000000..9f96b9a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmon/md93/drv_busmon.h
@@ -0,0 +1,1026 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   drv_busmon.h
+ *
+ * Project:
+ * --------
+ *   MOLY
+ *
+ * Description:
+ * ------------
+ *   Header file for Bus monitor control
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 03 12 2018 liang.yan
+ * [MOLY00312854] [Change Feature]Add AT feature for 93 busmon driver
+ *
+ * 10 30 2017 liang.yan
+ * [MOLY00285812] [MT6295M]Patch back CL4112332 from MT6295M.DEV to TRUNK
+ *
+ * 10 25 2017 liang.yan
+ * [MOLY00285147] [MT6765]Update busmon build option for cervino
+ *
+ * 09 15 2017 liang.yan
+ * [MOLY00277630] [Gen93]Update MDMCU Busmon APB access latency monitor policy
+ * 	
+ * 	[UMOLYA/TRUNK]busmon
+ *
+ * 08 25 2017 liang.yan
+ * [MOLY00273772] [Sylvia]Add Sylvia build option for bus monitor driver
+ *
+ * 06 09 2017 liang.yan
+ * [MOLY00244888] [ZION]Bus monitor driver build error call for check in
+ * 	
+ * 	[UMOLYA]Merge ZION project defining
+ *
+ * 06 07 2017 liang.yan
+ * [MOLY00248491] [MT6763][Gen93][System Service][MDCIRQ] Debugging code for GPT IRQ not entered issue
+ * 	[UMOLYA]Revert busmon layer id to PWB in initial stage
+ *
+ * 06 06 2017 liang.yan
+ * [MOLY00248491] [MT6763][Gen93][System Service][MDCIRQ] Debugging code for GPT IRQ not entered issue
+ * 	
+ * 	[UMOLYA]Rollback the bus monitor configuration for MDCIRQ issue
+ *
+ * 05 15 2017 yen-chun.liu
+ * [MOLY00248491] [MT6763][Gen93][System Service][MDCIRQ] Debugging code for GPT IRQ not entered issue
+ * busmon debug code for MDCIRQ.
+ *
+ * 05 10 2017 liang.yan
+ * [MOLY00242841] [SE2 Internal CR][Bianco][N1] Kernel API Dump,0,0,99,/data/core/,1,,EMI MPU,Fri Apr 14 23:02:16 CST 2017 @ 2017-04-14 23:02:16.77644,1,2372648
+ * 	Remove busmon debug code for MPU violation in TRUNK
+ *
+ * 05 05 2017 liang.yan
+ * [MOLY00242841] [SE2 Internal CR][Bianco][N1] Kernel API Dump,0,0,99,/data/core/,1,,EMI MPU,Fri Apr 14 23:02:16 CST 2017 @ 2017-04-14 23:02:16.77644,1,2372648
+ * 	[TRUNK]Add MDINFRA busmon debug for mpu violation
+ *
+ * 05 03 2017 liang.yan
+ * [MOLY00242841] [SE2 Internal CR][Bianco][N1] Kernel API Dump,0,0,99,/data/core/,1,,EMI MPU,Fri Apr 14 23:02:16 CST 2017 @ 2017-04-14 23:02:16.77644,1,2372648
+ * 	[TRUNK]bus monitor mo debug for MPU violation
+ *
+ * 05 02 2017 liang.yan
+ * [MOLY00244750] [System Service][MDGDMA][MT6763] Update GDMA debug log for DDL fail.
+ * 	Change MDMCU/MDINFRA busmon parking layer to default point
+ *
+ * 04 25 2017 liang.yan
+ * [MOLY00245013] [BIANCO][MT6763][RDIT][PHONE][Overnight][HQ][MTBF][Lab][Ericsson]Externel (EE) [Others] MD long time no response
+ * 	[TRUNK]Change MDMCU busmon parking layer to MCU2EMI
+ *
+ * 04 14 2017 liang.yan
+ * [MOLY00241937] [VTF_SMT][MT6293][SMT][Bianco][MT6763]Externel (EE),0,0,99,/data/core/,1,modem,md1:(USIP0_USIP0),[ASSERT] file:md32/usip/common/service/loader/src/loader.c line:1086 when overnight cal(1/601times)
+ * 	[UMOLYA]Change mdinfra busmon parking layer after MI
+ *
+ * 03 30 2017 liang.yan
+ * [MOLY00238383] [Change Feature][BUSMON]Change MDMCU busmon parking to PWB
+ *
+ * 03 15 2017 liang.yan
+ * [MOLY00235447] [Change Feature][SS][BUSMON]Add busmon profiling API for user
+ *
+ * 03 02 2017 liang.yan
+ * [MOLY00232074] [Change Feature][BIANCO]Adding busmon monitor MO port Latency feature
+ *
+ * 02 13 2017 i-chun.liu
+ * [MOLY00228094] [Bianco][Bringup] DEV patch back
+ * merge back busmon MO port setting.
+ *
+ * 02 03 2017 i-chun.liu
+ * [MOLY00227643] [Bianco Bring-up][Gen93/INIT/BUSMON] Change MDMCU BUSMON to MO port at init stage.
+ * Change MDMCU BUSMON to MO port at init stage.
+ *
+ * 08 05 2016 liang.yan
+ * [MOLY00195782] [Change Feature]93 busmon driver update
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * workaround for CIRQ driver.
+ *
+ * 03 30 2016 i-chun.liu
+ * [MOLY00171939] 93 Busmon check in
+ * busmon check in .
+ *
+ * 10 07 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * Update bus monitor IRQ code for ELBRUS.
+ *
+ * 08 17 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * bus monitor update for ELBRUS.
+ *
+ * 06 09 2015 i-chun.liu
+ * [MOLY00119728] JADE bring up call for check in  (MDCIRQ and Bus monitor )
+ * JADE PCORE BUSMON.
+ *
+ * 04 07 2015 i-chun.liu
+ * [MOLY00106215] TK6291 bus monitor driver update
+ * pcore busmonitor driver update to prevent modis build fail.
+ *
+ * 04 07 2015 i-chun.liu
+ * [MOLY00106215] TK6291 bus monitor driver update
+ * Pcore bus monitor driver update.
+ *
+ * 07 29 2014 brian.chiang
+ * [MOLY00070757] busmon drvier update
+ * Bus monitor driver enhancement
+ *
+ * 04 23 2014 brian.chiang
+ * [MOLY00063514] 6595 busmon driver
+ * 6595 busmon deriver porting
+ *
+ * 02 21 2014 i-chun.liu
+ * [MOLY00057041] Solve MT6290 bus monitor driver API bug
+ * bus monitor bug
+ *
+ * 05 31 2013 vend_hsientang.lee
+ * [MOLY00024631] Update busmon driver
+ * Use non-post-write to get accurate counter
+ *
+ * 03 29 2013 vend_hsientang.lee
+ * [MOLY00013013] Add Busmon driver
+ *
+ ****************************************************************************/
+
+
+#ifndef __DRV_BUSMON_H__
+#define __DRV_BUSMON_H__
+
+#if defined(__ASSEMBLER__)
+
+.macro BUSMON_PRE_CONFIG
+.set push
+.set nomips16
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)||defined(MT6765)||defined(MT6295M)
+    lui   t1, 0xA031
+    addiu t1, t1, 0x10
+    sw    zero, 0(t1)
+    sync  0x3
+    lui   t0, 0xA1FF
+    lw    t1,0(t0)
+    sw    t1,0(t0)
+    lui   t1, 0xA006
+    addiu t1, t1, 0x504
+    addiu t0, zero, 0x4
+    sw	  t0, 0(t1)
+    sync  0x3
+    lui   t0, 0xA1FF
+    lw	  t1,0(t0)
+    sw	  t1,0(t0)
+    lui   t1, 0xA031
+    addiu t1, t1, 0x10
+    addiu t0, zero, 0x1
+    sw	  t0, 0(t1)
+    sync  0x3
+    lui   t0, 0xA1FF
+    lw	  t1,0(t0)
+    sw	  t1,0(t0)
+#endif
+.set pop
+.endm BUSMON_PRE_CONFIG
+#else
+
+#include "kal_public_defs.h"
+#include "irqid.h"
+#include "busmon_reg.h"
+#include "intrCtrl.h"
+
+
+/*******************************************************************************
+ * Define Chip-dependet settings.
+ *******************************************************************************/
+/*Add MT6295M define only for build, need update when 95 busmon driver ready*/
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)||defined(MT6765)||defined(MT6295M)
+typedef enum {
+   MDMCUSYS_BUSMON_IRQID = MD_IRQID_MDMCU_BUSMON_MATCH_STS,
+   MDPERISYS_BUSMON_IRQID = MD_IRQID_MDINFRA_BUSMON_MATCH_STS,
+   MD_BUSMON_IRQID_NUM = 2,
+} drv_busmon_irqid_t;
+#endif /*MT6763*/	
+
+
+/*******************************************************************************
+ * Define constants.
+ *******************************************************************************/
+/* MD AXI BusMon */
+typedef enum {
+   MONID_MDMCU_AXIMON = 0,  /* MD_AXImon_1 */
+   MONID_MDINFRA_AXIMON,    /* MD_AXImon_2 */
+
+   MONID_MDAXI_MAX
+} drv_aximon_monid_md_t;
+
+
+typedef drv_aximon_monid_md_t drv_aximon_monid_t;
+#define MAX_AXIMON_NUM      MONID_MDAXI_MAX
+
+/*
+*  Define 15us which is the max latency time from mcu to apb read access
+*  bus clk is 432MHz in BIANCO(MT6763) & SYLVIA(MT6771) & Cervino(MT6765), so the limit bus cycle count is 0x1950 in BIANCO & SYLVIA
+*  bus clk is 300MHz(fixed) in ZION(MT6739), so the limit bus cycle count is 0x1194 in ZION
+*/
+#if defined(MT6763)||defined(MT6771)||defined(MT6765)||defined(MT6295M)
+#define MCU2REG_LIMITED_LATENCY_CNT   0x1950   //0x1B0 1us, 0x1950 15us
+#endif
+
+#if defined(MT6739)
+#define MCU2REG_LIMITED_LATENCY_CNT   0x1194   //0x1194 15us
+#endif
+
+#define MO_LATENCY_RECORD_NUM     20
+
+/*
+ * Busmon layer select id
+ */
+typedef enum {
+   /* MD_AXImon_1 */
+   BUSMON_BUSID_MDMCUSYS_START = 0UL,   
+   BUSMON_BUSID_MDMCU_EMI=BUSMON_BUSID_MDMCUSYS_START,   
+   BUSMON_BUSID_IA_MM=1,
+   BUSMON_BUSID_IA_MO=2,
+   BUSMON_BUSID_uSIP_APB=3,
+   BUSMON_BUSID_IA_MO_PWB=4,  
+   BUSMON_BUSID_MDMCUSYS_END=5,   
+   /* busmon on MD INFRA */
+   BUSMON_BUSID_MDINFRA_START = 0,   
+   BUSMON_BUSID_MDINFRA_EMI = BUSMON_BUSID_MDINFRA_START,
+   BUSMON_BUSID_MDINFRA_IOCU = 1,
+   BUSMON_BUSID_MDINFRA_END = 2,  
+  
+} busmon_busid_t;  
+
+typedef enum {
+   BUSMON_MON_DISABLE,
+   BUSMON_MON_ENABLE
+} drv_busmon_active_t;
+
+typedef enum {
+   BUSMON_MON_STATE_INACTIVE,
+   BUSMON_MON_STATE_ACTIVE
+} drv_busmon_mon_state_t;
+
+/* Busmon internal IP */
+typedef enum {
+   BUSMON_IP0,
+   BUSMON_IP1,
+
+   BUSMON_IP_MAX
+} drv_busmon_ip_t;
+
+/* Busmon IP status */
+typedef enum {
+   IP_IDLE = 0,
+   IP_REAL_ENABLE = 1,
+   IP_STOP = 2,
+} busmon_ip_status_t;
+
+/* AXImon Read/Write Selection */
+typedef enum {
+   AXIMON_RWSEL_WRITE=0,
+   AXIMON_RWSEL_READ=1,
+
+   AXIMON_RWSEL_MAX
+} drv_aximon_rwsel_t;
+
+typedef enum {
+   START_ORDER_IP0_IP1=0,
+   STOP_ORDER_IP0_IP1=1,
+   ORDER_IP0_IP1_MAX=2   
+} drv_busmon_mon_seq_check_mode_t;
+
+/*
+ * Busmon Target Monitor Mode
+ */
+typedef enum {
+   BUSMON_TG_MON_MODE_SNAP,
+   BUSMON_TG_MON_MODE_MONITOR,
+
+   BUSMON_TG_MON_MODE_MAX
+} drv_busmon_tg_mon_mode_t;
+
+/* Busmon Trigger Mode */
+typedef enum {
+   BUSMON_TRG_ADDRDATA,                 /* Address & Data Trigger */
+   BUSMON_TRG_CYCLE,                    /* Cycle Trigger */
+
+   BUSMON_TRG_MAX
+} drv_busmon_trg_mode_t;
+
+typedef enum {
+   MON_VPE_0 = 0,     /*93 only include 2 cores, core0 and core1*/
+   MON_VPE_1 = 4,
+   MON_VPE_2 = 1,
+   MON_VPE_3 = 5,   
+} busmon_vpe_id_t;
+
+typedef enum {
+    MONITOR_START = 0,
+    MCR0 = 0,
+    MCR1 = 1,
+    MCW0 = 2,
+    MCW1 = 3,
+    MIR0 = 4,
+    MIR1 = 5,
+    MIW0 = 6,
+    MIW1 = 7,
+    MONITOR_END = 7,
+
+    LATENCY_START = 16,
+    LCR0G = 16,
+    LCR1G = 17,
+    LCW0G = 18,
+    LCW1G= 19,
+    LCR0S = 20,
+    LCR1S = 21,
+    LCW0S = 22,
+    LCW1S = 23,
+    LIR0G = 24,
+    LIR1G = 25,
+    LIW0G = 26,
+    LIW1G= 27,
+    LIR0S = 28,
+    LIR1S = 29,
+    LIW0S = 30,
+    LIW1S = 31,
+    LATENCY_END = 31,
+
+    ADDR_START = 48,
+    ACR0G = 48,
+    ACR1G = 49,
+    ACW0G = 50,
+    ACW1G= 51,
+    ACR0S = 52,
+    ACR1S = 53,
+    ACW0S = 54,
+    ACW1S = 55,
+    AIR0G = 56,
+    AIR1G = 57,
+    AIW0G = 58,
+    AIW1G= 59,
+    AIR0S = 60,
+    AIR1S = 61,
+    AIW0S = 62,
+    AIW1S = 63,
+    ADDR_END = 63,
+
+    STARTC = 100,
+    STOPC = 101,
+    STARTI = 102,
+    STOPI = 103,
+    
+	ENBMIP = 110,
+	ENBIIP = 111,
+
+	MOD_CFG_START = 120,
+	CLOG = 121,
+	CASST = 122,
+	ILOG = 123,
+	IASST = 124,
+    MOD_CFG_END = 125 
+	
+} busmon_at_config_t;
+
+typedef enum {
+   MODE_LOG,
+   MODE_ASSERT,
+   MODE_MAX,   
+} busmon_log_assert_mode_t;
+
+/*
+ * Busmon target selection - master id
+ * For AXI, master id is to select transaction ID
+ * Here only list MDMCU layer0,1,2 master id, we don't care master id from uSIP(layer3)
+ */
+#if defined(MT6763)||defined(MT6739)||defined(MT6771)||defined(MT6765)||defined(MT6295M)
+
+typedef enum {
+   /*MDMCU master id*/
+   BUSMON_TGID_IA_MM_NONCACHE_RW_CORE0_VPE0=16,   //0x10  MM port layer1 (BUSMON_BUSID_IA_MM)
+   BUSMON_TGID_IA_MM_NONCACHE_RW_CORE1_VPE0=17,   //0x11  MM port layer1
+   BUSMON_TGID_IA_MM_NONCACHE_RW_IOCU=20,         //0x14  MM port layer1
+   BUSMON_TGID_IA_MM_NONCACHE_RW_CORE0_VPE1=24,   //0x18  MM port layer1
+   BUSMON_TGID_IA_MM_NONCACHE_RW_CORE1_VPE1=25,   //0x19  MM port layer1
+
+   BUSMON_TGID_IA_MM_CACHE_W=7,                   //0x7  MM port layer1 outstanding capability is 8, master id always 7
+   BUSMON_TGID_IA_MM_CACHE_R=0,                   // Note: may be 0x0~0x6, 0x8~0xF, outstanding capability is 16
+
+   BUSMON_TGID_IA_MO_NONBUF_RW_CORE0=0,           //0x0 MO port layer2 (BUSMON_BUSID_IA_MO)
+   BUSMON_TGID_IA_MO_NONBUF_RW_CORE1=1,           //0x1 MO port layer2
+
+   BUSMON_TGID_IA_MO_BUF_W=15,                    //0xF MO port layer2 outstanding capability is 8, master id always 15
+
+   BUSMON_TGID_IA_MM_NONCACHE_RW_CORE0_VPE0_EMI=40,   //0b1000000  MM port layer0 (BUSMON_BUSID_MDMCU_EMI) (MM->EMI )
+   BUSMON_TGID_IA_MM_NONCACHE_RW_CORE1_VPE0_EMI=44,   //0b1000100  MM port layer0 (MM->EMI )
+   BUSMON_TGID_IA_MM_NONCACHE_RW_IOCU_EMI=50,         //0b1010000  MM port layer0 (MM->EMI )
+   BUSMON_TGID_IA_MM_NONCACHE_RW_CORE0_VPE1_EMI=60,   //0b1100000  MM port layer0 (MM->EMI )
+   BUSMON_TGID_IA_MM_NONCACHE_RW_CORE1_VPE1_EMI=64,   //0b1100100  MM port layer0 (MM->EMI )
+
+   BUSMON_TGID_IA_MM_CACHE_W_EMI=28,                  //0b11100  MM port layer0 (MM->EMI )
+   BUSMON_TGID_IA_MM_CACHE_R_EMI=0,                   // Note: may be 0x0~0x6, 0x8~0xF(need append 2'b00 at the LSB of the original id)
+                                                                       
+   BUSMON_TGID_IA_MM_NONCACHE_RW_CORE0_VPE0_MML2_EMI=41,   //0b1000001  MM port layer0 (BUSMON_BUSID_MDMCU_EMI) (MM->MML2_MMU->EMI )
+   BUSMON_TGID_IA_MM_NONCACHE_RW_CORE1_VPE0_MML2_EMI=45,   //0b1000101  MM port layer0 (MM->MML2_MMU->EMI )
+   BUSMON_TGID_IA_MM_NONCACHE_RW_IOCU_MML2_EMI=51,         //0b1010001  MM port layer0 (MM->MML2_MMU->EMI )
+   BUSMON_TGID_IA_MM_NONCACHE_RW_CORE0_VPE1_MML2_EMI=61,   //0b1100001  MM port layer0 (MM->MML2_MMU->EMI )
+   BUSMON_TGID_IA_MM_NONCACHE_RW_CORE1_VPE1_MML2_EMI=65,   //0b1100101  MM port layer0 (MM->MML2_MMU->EMI )
+
+   BUSMON_TGID_IA_MM_CACHE_W_MML2_EMI=29,                  //0b11101  MM port layer0 (MM->MML2_MMU->EMI )
+   BUSMON_TGID_IA_MM_CACHE_R_MML2_EMI=1,                   // Note: may be 0x0~0x6, 0x8~0xF(need append 2'b01 at the LSB of the original id)
+
+   /*MDINFRA master id*/
+   BUSMON_TGID_INFRA_ABM_EMI=0,                  //12'0b0000_00xx_0000  MDINFRA layer0 (BUSMON_BUSID_MDINFRA_EMI, master -> emi)
+   BUSMON_TGID_INFRA_PPPHA_EMI=1,                //12'0b0000_000x_0001  MDINFRA layer0
+   BUSMON_TGID_INFRA_LOGTOPMCU_EMI=2,            //12'0b0000_000x_0010  MDINFRA layer0
+   BUSMON_TGID_INFRA_LOGTOPDSP_EMI=3,            //12'0b0000_000x_0011  MDINFRA layer0
+   BUSMON_TGID_INFRA_TRACETOP_EMI=4,             //12'0b0000_000x_0100  MDINFRA layer0
+   BUSMON_TGID_INFRA_IPSEC_EMI=5,                //12'0b0000_000x_0101  MDINFRA layer0
+   BUSMON_TGID_INFRA_DBGSYS_EMI=23,              //12'0b0000_0xx1_0111  MDINFRA layer0
+   BUSMON_TGID_INFRA_GDMA_EMI=7,                 //12'0b000x_xxx0_0111  MDINFRA layer0
+   BUSMON_TGID_INFRA_FE_MAS_EMI=8,               //12'0b00xx_xxxx_1000  MDINFRA layer0
+   BUSMON_TGID_INFRA_BIGRAM_MAS_EMI=1024,        //12'0b0100_0000_0xxx  MDINFRA layer0
+   BUSMON_TGID_INFRA_BRP_MAS_EMI=2048,           //12'0b1000_000x_xxxx  MDINFRA layer0
+   BUSMON_TGID_INFRA_MML2_MAS_EMI=3072,          //12'0b1100_0000_0xxx  MDINFRA layer0
+
+   BUSMON_TGID_INFRA_AP2MD=0,                    //10'0b00_0000_x000  MDINFRA layer1 (BUSMON_BUSID_MDINFRA_IOCU, master -> mdmcu bus)
+   BUSMON_TGID_INFRA_BIGRAM_MAS=17,		         //10'0b00_xxx1_0001   MDINFRA layer1
+   BUSMON_TGID_INFRA_BRP_MAS=9,			         //10'0bxx_xxx0_x1001  MDINFRA layer1
+   BUSMON_TGID_INFRA_MML2_MAS=1, 		         //10'0b00_xxx0_0001   MDINFRA layer1
+   BUSMON_TGID_INFRA_FE_MAS=2,                   //10'0b0x_xxxx_x010    MDINFRA layer1
+   BUSMON_TGID_INFRA_DBGSYS=11,                  //10'0b00_00xx_1011   MDINFRA layer1
+   BUSMON_TGID_INFRA_GDMA=3,                     //10'0b00_xxxx_0011   MDINFRA layer1
+   BUSMON_TGID_INFRA_IPSEC=5,                    //10'0b00_0000_x101  MDINFRA layer1
+} busmon_tg_id_t;
+
+#endif /*MT6763*/
+
+#define AXIID_IA_ID_MASK_ALL             0xFFFF
+#define AXIID_IA_ID_MASK_NONE            0x0000
+
+
+#define AXI_VPE_ID_MASK_ALL    0x7
+#define AXI_VPE_ID_MASK_NONE   0x0
+
+#define AXI_ULTRA_MASK_ALL     0x3
+#define AXI_ULTRA_MASK_NONE    0x0
+#define AXIMON_TOTAL_AT_CONFIG        0x6
+#define AXIMON_TOTAL_IP                           0x4
+
+//--------------------------
+// below for Bus Recorder
+//-------------------------
+#define BUSREC_RECORD_CNT_MAX     63
+#define BUSREC_SUPPORT_RECORD_CNT 32
+#define BUSREC_SUPPORT_RECORD_CNT_R   BUSREC_SUPPORT_RECORD_CNT
+#define BUSREC_SUPPORT_RECORD_CNT_W   BUSREC_SUPPORT_RECORD_CNT
+
+typedef enum {
+    BUSREC_MODE_NORMAL = 0,
+    BUSREC_MODE_TEST = 1,
+} BUSREC_MODE;
+
+typedef enum {
+    BUSREC_GATE_NONE,
+    BUSREC_GATE_RESP,
+    BUSREC_GATE_CMD,
+    BUSREC_GATE_ALL,
+} BUSREC_GATE;
+
+typedef enum {
+    BUSREC_TYPE_WR,
+    BUSREC_TYPE_RD,
+    BUSREC_TYPE_MAX,
+} BUSREC_REC_TYPE;
+
+typedef enum {
+    BUSREC_RET_OK = 0,
+    BUSREC_RET_FAIL = -1,
+    BUSREC_RET_NOT_SUPPORTED = -2,
+    BUSREC_RET_INVALID_PARAMETER = -3,
+    BUSREC_RET_STARTED = -4,
+} BUSREC_RET;
+//--------------------------
+// Above for Bus Recorder
+//-------------------------
+
+
+/*******************************************************************************
+ * Define data structures.
+ *******************************************************************************/
+/* AXImon IP configuration of Monitor mode */
+typedef struct {
+   drv_aximon_rwsel_t rwsel;
+   busmon_tg_id_t master_id;          /* specific transaction ID */
+   kal_uint32 master_id_mask;
+   kal_uint32 vpe_id;             /* specific VPE ID */
+   kal_uint32 vpe_id_mask;  
+   kal_uint32 ultra;              /* specific ULTRA */
+   kal_uint32 ultra_mask;    
+   kal_bool all_master_enable;    /* any transaction ID */
+   kal_uint32 addr;               /* address */
+   kal_uint32 addr_mask;          /* address mask, 0: check, 1: ignore */
+   kal_bool   data_enable;        /* data target check at counting snap count */    
+   kal_uint32 data;               /* data 0 32-bit of bus width */
+   kal_uint32 data_mask;          /* data 0 mask 0: check, 1: ignore */   
+} drv_aximon_mon_config_t;
+
+/* Configuration of Snapshot Mode */
+typedef struct {
+   drv_aximon_rwsel_t rwsel;
+   busmon_tg_id_t master_id;          /* specific transaction ID */
+   kal_uint32 master_id_mask;
+   kal_uint32 vpe_id;             /* specific VPE ID */
+   kal_uint32 vpe_id_mask;   
+   kal_uint32 ultra;              /* specific ULTRA */
+   kal_uint32 ultra_mask;   
+   kal_bool all_master_enable;    /* ALL Master should only use in Monitor mode */
+   drv_busmon_trg_mode_t trg_mode;  /* trigger mode */
+   kal_uint32 addr;               /* address */
+   kal_uint32 addr_mask;          /* address mask, 0: check, 1: ignore */
+   kal_bool   data_enable;        /* data target check at counting snap count */   
+   kal_uint32 data;               /* data 0 32-bit of bus width */
+   kal_uint32 data_mask;          /* data 0 mask 0: check, 1: ignore */
+   kal_uint32 mon_cnt;            /* count select */ 
+   kal_uint32 cycle_cnt;          /* max cycle */    
+} drv_aximon_snp_config_t;
+
+/* Configuration of Trigger Mode */
+typedef struct {
+   kal_bool enable_seq_trg;       /* TRUE==> sequencial mode, FALSE==> Concurrent mode */
+   drv_busmon_ip_t trigger_ip;    /* Only use in Concurrent mode, determine which IP would trigger interrupt */   
+   drv_busmon_mon_seq_check_mode_t seq_check_mode; /* START_ORDER_IP0_IP1/STOP_ORDER_IP0_IP1 */   
+   drv_aximon_snp_config_t ip[BUSMON_IP_MAX];
+} drv_aximon_trg_config_t;
+
+/* Monitor Mode: Read-related informatin */
+typedef struct {
+   kal_uint32 QID;
+   kal_uint32 tot_bus_cyc;          /* total bus cycle */
+   kal_uint32 non_ov_trans_num;     /* total transaction number */
+   kal_uint32 ov_trans_num;
+   kal_uint32 non_wgt_trans_cyc;    /* total transaction cycle */
+   kal_uint32 wgt_trans_cyc;
+   kal_uint32 max_trans_cyc;        /* max transaction cycle */
+   kal_uint32 max_ost_trans_num;
+
+   kal_uint32 bus_util;             /* bus utilization */
+   kal_uint32 avg_data_rate;        /* average data rate ,not used in Elbrus*/
+   kal_uint32 avg_xac_cyc;          /* average transaction cycle */
+} drv_aximon_mon_transaction_info_t;
+
+/* Snapshot Mode */
+typedef struct {
+   kal_uint32 info0;                /*current AXI bus signal (burst, lock, cache, size...), VPE*/
+   kal_uint32 info1;                /*current target id (QID),target match count*/
+   kal_uint32 info2;                /*snap target address*/
+   kal_uint32 info3;                /*data0&data1 strobe*/
+   kal_uint32 info4;                /*last data[31:0]*/
+   kal_uint32 info5;                /*last data[63:32]*/
+   kal_uint32 info6;                /*last data[95:64]*/
+   kal_uint32 info7;                /*last data[127:96]*/
+   kal_uint32 info8;                /*last second data[31:0]*/
+   kal_uint32 info9;                /*last second data[63:32]*/
+   kal_uint32 info10;               /*last second data[95:64]*/
+   kal_uint32 info11;               /*last second data[127:96]*/
+} drv_aximon_snp_info_t;
+
+/* Sequential Mode: */
+typedef struct {
+   drv_aximon_snp_info_t ip[BUSMON_IP_MAX];
+} drv_aximon_trg_info_t;
+
+typedef void (*busmon_intr_cb)(void);
+
+typedef struct {
+   kal_uint32 mo_index;
+   kal_uint32 mo_frc_count[MO_LATENCY_RECORD_NUM];
+   kal_uint32 mo_latency[MO_LATENCY_RECORD_NUM];
+   kal_uint32 mo_address[MO_LATENCY_RECORD_NUM];
+   kal_uint32 mo_vpe_id[MO_LATENCY_RECORD_NUM];      /*snap_info0 bit[2:0]*/
+   kal_uint32 mo_master_id[MO_LATENCY_RECORD_NUM];   /*snap_info1 bit[15:0]*/
+} aximon_mo_latency_info_t;
+
+/*this struct is used to record the at comand that user input.*/
+typedef struct{
+    busmon_at_config_t at_config_g;
+    busmon_busid_t at_bus_id_g;
+    kal_uint32 at_addr_g;
+    kal_uint32 at_addr_msk_g;
+    kal_uint32 at_master_g; 
+    kal_uint32 at_master_msk_g;
+    kal_uint32 at_vpe_g;
+    kal_uint32 at_vpe_msk_g;
+    kal_uint32 at_ultra_g;
+    kal_uint32 at_ultra_msk_g;
+    kal_uint32 at_data_latcy_g;
+    kal_uint32 at_data_msk_g;
+}drv_aximon_at_config;
+
+/*this struct is used to record registers value before entering dormant*/
+typedef struct{
+    volatile kal_uint32 aximon_ctl_r;
+    volatile kal_uint32 aximon_tst_r;
+    volatile kal_uint32 aximon_intmsk_r;
+    volatile kal_uint32 aximon_ip0_tg_r;
+    volatile kal_uint32 aximon_ip0_tmr_r;
+    volatile kal_uint32 aximon_ip0_id_r;
+    volatile kal_uint32 aximon_ip0_vpe_r;
+    volatile kal_uint32 aximon_ip0_addr_r;
+    volatile kal_uint32 aximon_ip0_addrmsk_r;
+    volatile kal_uint32 aximon_ip0_data_r;
+    volatile kal_uint32 aximon_ip0_datamsk_r;
+    volatile kal_uint32 aximon_ip1_tg_r;
+    volatile kal_uint32 aximon_ip1_tmr_r;
+    volatile kal_uint32 aximon_ip1_id_r;
+    volatile kal_uint32 aximon_ip1_vpe_r;
+    volatile kal_uint32 aximon_ip1_addr_r;
+    volatile kal_uint32 aximon_ip1_addrmsk_r;
+    volatile kal_uint32 aximon_ip1_data_r;
+    volatile kal_uint32 aximon_ip1_datamsk_r;
+}drv_aximon_dormant_backup;
+//--------------------------
+// Below for Bus Recorder
+//-------------------------
+typedef struct {
+   kal_bool IP_enable[BUSMON_IP_MAX];	/* IP 0 and IP1 enable or not when BUS recorder testing */
+   drv_aximon_rwsel_t rwsel[BUSMON_IP_MAX];            /* Note: In IPx_AXIMON_TG, BUS Recorder only take care RWSEL & IPx_MON_ENABLE */
+} UT_BUSREC_IP_CFG;
+//--------------------------
+// Above for Bus Recorder
+//-------------------------
+
+
+/*******************************************************************************
+ * Define Macros.
+ *******************************************************************************/
+/* Register field manipulation macro */
+#define EXTRACT_REG_FIELD_VAL(field_val, field_name) (((field_val) >> (field_name##_SHIFT)) & (field_name##_MASK))
+#define EXPAND_REG_FIELD_VAL(field_val, field_name) (((field_val) & (field_name##_MASK)) << (field_name##_SHIFT))
+#define CLEAR_REG_FIELD(reg_val, field_name) ((reg_val) & (~((field_name##_MASK) << (field_name##_SHIFT))))
+#define SET_REG_FIELD_VAL(reg_val, field_val, field_name) (CLEAR_REG_FIELD(reg_val, field_name) | EXPAND_REG_FIELD_VAL(field_val, field_name))
+
+
+/**************************************************
+AXIMon External Fucntion Declearation
+***************************************************/
+kal_uint32 aximon_read_base_addr(drv_aximon_monid_t axi_mon_id);
+void drv_busmon_set_trg_cb(busmon_intr_cb callback, drv_busmon_irqid_t irq_type);
+
+/**
+ * @brief  Set bus id to the layer select
+ * @param  bus_id
+ * @return
+ * @retval
+ * @retval
+ *
+ *  The BusMon shall be disabled before changing the bus id.
+ */
+kal_int32 aximon_set_busid(drv_aximon_monid_t axi_mon_id, busmon_busid_t bus_id);
+
+/**
+ * @brief Enable/Disable Speed Sim
+ * @param axi_mon_id
+ * @param enabled
+ * @retval
+ * @retval
+ */
+void aximon_set_speedsim(drv_aximon_monid_t axi_mon_id, kal_bool enabled);
+
+void aximon_set_clear_at_bus_idle(drv_aximon_monid_t axi_mon_id, kal_bool enabled);
+
+void aximon_polling_IP_Real_Enable(drv_aximon_monid_md_t axi_mon_id, drv_busmon_ip_t mon_ip);
+
+/**
+ * @brief  Configure parameters used in Monitor Mode
+ * @param  axi_mon_id
+ * @param  mon_ip
+ * @param  config
+ * @return The configuration result
+ * @retval 0 if the configuration applied
+ * @retval -1 if the configuration rejected
+ *
+ *  The BusMon shall stop before changing the configuration.
+ */
+kal_int32 aximon_set_monitor(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip, drv_aximon_mon_config_t *config);
+
+/**
+ * @brief  Configure parametes used in Snapshot Mode
+ * @param  axi_mon_id
+ * @param  config
+ * @param  mon_ip
+ * @return The configuration result
+ * @retval 0 if the configuration succeeds
+ * @retval -1 if the configuration fails
+ *
+ *  The BusMon shall stop before changing the configuration.
+ */
+kal_int32 aximon_set_snap(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip, drv_aximon_snp_config_t *config);
+
+/**
+ * @brief  Configure parameters in Sequential Trigger Mode
+ * @param  axi_mon_id
+ * @param  config
+ * @return The configuration result
+ * @retval 0 if the configuration applied
+ * @retval -1 if the configuration rejected
+ *
+ *  The BusMon shall be disabled before changing the
+ *  configuration.
+ */
+kal_int32 aximon_set_sq_trg(drv_aximon_monid_t axi_mon_id, drv_aximon_trg_config_t *config);
+
+/**
+ * @brief  Start recording
+ * @param  axi_mon_id
+ * @return
+ * @retval
+ *
+ *  BusMon clears the counts first.
+ *  BusMon always waits for the on-going transaction finished
+ *  before starting to update the counts.
+ */
+void aximon_start(drv_aximon_monid_t axi_mon_id);
+
+/**
+ * @brief  Stop recording
+ * @param
+ * @return
+ * @retval
+ *
+ *  BusMon always waits for the on-going transaction finished
+ *  before pausing to update the counts.
+ *  Some counts stop to update once paused received Some counts
+ *  continues to update until all transactions fishished.
+ */
+void aximon_stop(drv_aximon_monid_t axi_mon_id);
+
+/**
+ * @brief  Enable interrupt
+ * @param  axi_mon_id
+ * @return
+ * @retval
+ */
+void aximon_enable_interrupt(drv_aximon_monid_md_t axi_mon_id);
+
+/**
+ * @brief  Disable interrupt
+ * @param  axi_mon_id
+ * @return
+ * @retval
+ */
+void aximon_disable_interrupt(drv_aximon_monid_md_t axi_mon_id);
+
+void aximon_clear_interrupt(drv_aximon_monid_md_t axi_mon_id);
+
+
+/**
+ * @brief Get triggered information in Snapshot mode
+ * @param axi_mon_id
+ * @param mon_ip
+ * @param info
+ * @retval
+ * @retval
+ */
+void aximon_get_snap_info(drv_aximon_monid_md_t axi_mon_id, drv_busmon_ip_t mon_ip, drv_aximon_snp_info_t *info);
+
+/**
+ * @brief Read-related Information in Monitor mode
+ * @param axi_mon_id
+ * @param mon_ip
+ * @param info
+ * @retval
+ * @retval
+ */
+void aximon_get_ip_transaction_info(drv_aximon_monid_md_t axi_mon_id, drv_busmon_ip_t mon_ip, drv_aximon_mon_transaction_info_t *info);
+
+/**
+ * @brief Get information in Triggered Mode
+ * @param axi_mon_id
+ * @param info
+ * @retval
+ * @retval
+ */
+void aximon_get_trigger_info(drv_aximon_monid_md_t axi_mon_id, drv_aximon_trg_info_t *info);
+
+/**
+ * @brief Polling the triggered status
+ * @param axi_mon_id
+ * @param max_count
+ * @return
+ * @retval 0 if the interrupt triggered and in inactive state
+ * @retval -1 if no interrupt triggered or in active state
+ */
+kal_int32 aximon_poll_trigged(drv_aximon_monid_md_t axi_mon_id, kal_uint32 max_count, drv_busmon_mon_state_t *ip0_state, drv_busmon_mon_state_t *ip1_state);
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDINFRA busmon interrupt occurs. 
+*   After MDMCU busmon interrupt occurs, just record the registers information and clear interrupt.
+*   The define as follows
+*      AXIMON_IP0_SNAP_INFO2: the address of target transaction in IP0;
+*      AXIMON_IP0_MAX_TRANS_CYC: tha max transaction cycle in IP0;
+*      AXIMON_IP0_SNAP_INFO0: transaction information in IP0;
+*      AXIMON_IP0_SNAP_INFO1: master id of target transaction in IP0.
+*
+*************************************************************************/
+void busmon_mdinfra_record(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDMCU busmon interrupt occurs. 
+*   After MDMCU busmon interrupt occurs, just record the registers information and clear interrupt.
+*   The define as follows
+*      AXIMON_IP0_SNAP_INFO2: the address of target transaction in IP0;
+*      AXIMON_IP0_MAX_TRANS_CYC: tha max transaction cycle in IP0;
+*      AXIMON_IP0_SNAP_INFO0: transaction information in IP0;
+*      AXIMON_IP0_SNAP_INFO1: master id of target transaction in IP0.
+*
+*************************************************************************/
+void busmon_mdmcu_record(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function is the callback function for mdinfra busmon in snap-cycle trigger mode.
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_MAX_TRANS_CYC: IP0 max transaction cycle;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdinfra_busmon_latency_assert(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function is the callback function for mdmcu busmon in snap-cycle trigger mode.
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_MAX_TRANS_CYC: IP0 max transaction cycle;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdmcu_busmon_latency_assert(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function is the callback function for mdinfra busmon in snap-data trigger mode.
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_SNAP_INFO0: IP0 master ID;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdinfra_busmon_addr_assert(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function is the callback function for mdmcu busmon in snap-data trigger mode.
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_SNAP_INFO0: IP0 master ID;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdmcu_busmon_addr_assert(void);
+
+void busmon_init(void);
+void busmon_dormant_init(void);
+void busmon_dormant_backup(void);
+void busmon_snap_mo_init(void);
+void busmon_monitor_mo_init(void);
+void busmon_get_avg_latency_and_xac_count(drv_aximon_mon_transaction_info_t *mon_info0, drv_aximon_mon_transaction_info_t *mon_info1);
+void busmon_monitor_mdinfra_init(void);
+void busmon_mpu_vio_debug(void);
+void mdinfra_busmon_mpu_vio_debug(void);
+void mdinfra_busmon_snap_init(void);
+void aximon_enable_both_ip(drv_aximon_monid_md_t axi_mon_id);
+void aximon_assert_log_mode_config(drv_aximon_monid_md_t axi_mon_id, busmon_log_assert_mode_t mode);
+
+//--------------------------
+// Below for Bus Recorder
+//-------------------------
+kal_int32 drv_busrec_start(BUSREC_GATE gate, drv_aximon_monid_t axi_mon_id);
+kal_int32 drv_busrec_stop(drv_aximon_monid_t axi_mon_id);
+kal_bool  drv_busrec_is_started(drv_aximon_monid_t axi_mon_id);
+kal_int32 drv_busrec_get_count(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip);
+busmon_ip_status_t drv_busrec_get_ip_status(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip);
+kal_int32 drv_busrec_get_ip_record(drv_aximon_monid_md_t axi_mon_id, drv_busmon_ip_t mon_ip, kal_uint32 index, kal_uint32 *id, kal_uint32 *addr);
+kal_int32 drv_busrec_get_ip_curr(drv_aximon_monid_md_t axi_mon_id, drv_busmon_ip_t mon_ip, kal_uint32 *id, kal_uint32 *addr, kal_uint32 *ctrl_sts);
+kal_bool  drv_busrec_is_overflow(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip);
+kal_bool  drv_busrec_is_underflow(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip);
+kal_bool drv_busrec_is_id_miss(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip);
+kal_bool drv_busrec_history_is_overflow(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip);
+kal_bool drv_busrec_history_is_underflow(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip);
+kal_bool drv_busrec_history_is_id_miss(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip);
+kal_int32 drv_busrec_set_mode(BUSREC_MODE mode, drv_aximon_monid_t axi_mon_id, UT_BUSREC_IP_CFG *ip_cfg);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_at_config
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   bus_id - to select layer;
+*
+* DESCRIPTION
+*   This function is used for config bus monitor through AT command;
+*
+*************************************************************************/
+void aximon_atcmd_config(busmon_at_config_t at_config, busmon_busid_t at_bus_id, kal_uint32 at_addr, 
+    kal_uint32 at_addr_msk, kal_uint32 at_master, kal_uint32 at_master_msk, kal_uint32 at_vpe, 
+    kal_uint32 at_vpe_msk, kal_uint32 at_ultra, kal_uint32 at_ultra_msk, kal_uint32 at_data_latcy, kal_uint32 at_data_msk);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_at_config_monitor
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   at_bus_id - to select layer;
+*
+* DESCRIPTION
+*   config busmon monitor mode through AT command;
+*
+*************************************************************************/
+void aximon_at_config_monitor(busmon_at_config_t at_config, busmon_busid_t at_bus_id, 
+    kal_uint32 at_addr, kal_uint32 at_addr_msk, kal_uint32 at_master, kal_uint32 at_master_msk, 
+    kal_uint32 at_vpe, kal_uint32 at_vpe_msk, kal_uint32 at_ultra, kal_uint32 at_ultra_msk);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_at_config_latency
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   at_bus_id - to select layer;
+*
+* DESCRIPTION
+*   config busmon snap mode cycle trigger through AT command;
+*
+*************************************************************************/
+void aximon_at_config_latency (busmon_at_config_t at_config, busmon_busid_t at_bus_id, kal_uint32 at_addr, 
+    kal_uint32 at_addr_msk, kal_uint32 at_master, kal_uint32 at_master_msk, 
+    kal_uint32 at_vpe, kal_uint32 at_vpe_msk, kal_uint32 at_ultra, kal_uint32 at_ultra_msk, kal_uint32 at_data_latcy);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_at_config_addr
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   at_bus_id - to select layer;
+*
+* DESCRIPTION
+*   config busmon monitor mode through AT command;
+*
+*************************************************************************/
+void aximon_at_config_addr(busmon_at_config_t at_config, busmon_busid_t at_bus_id, kal_uint32 at_addr, kal_uint32 at_addr_msk, 
+     kal_uint32 at_master, kal_uint32 at_master_msk, kal_uint32 at_vpe, kal_uint32 at_vpe_msk, 
+     kal_uint32 at_ultra, kal_uint32 at_ultra_msk, kal_uint32 at_data_latcy, kal_uint32 at_data_msk);
+
+
+//--------------------------
+// Above for Bus Recorder
+//-------------------------
+
+
+#endif /* end of __ASSEMBLER__ */
+
+#endif /* end of __DRV_BUSMON_H__ */
+
diff --git a/mcu/interface/driver/devdrv/busmon/md95/busmon_reg.h b/mcu/interface/driver/devdrv/busmon/md95/busmon_reg.h
new file mode 100644
index 0000000..b266899
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmon/md95/busmon_reg.h
@@ -0,0 +1,629 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2013
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   busmon_reg.h
+ *
+ * Project:
+ * --------
+ *   MOLY
+ *
+ * Description:
+ * ------------
+ *   Busmon register definition
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 01 21 2019 hedy.han
+ * [MOLY00380374] [Gen97][build error solving] MT6779_SP(LWCTG) on VMOLY.EVB.SEPT.DEV
+ * [VMOLY.EVB.SEPT.DEV][GEN95 BUSMON]merge 95busmon from UMOLYE branch.
+ *
+ * 03 29 2018 hedy.han
+ * [MOLY00316943] [New feature][Address logger] Add address logger enable and disable function.
+ * [New feature][Address logger] add address logger enable and disable function.
+ *
+ * 03 12 2018 hedy.han
+ * [MOLY00312512] [UMOLYE TRUNK][GEN95][BUSMON][New Feature][AT command]
+ *
+ * 07 04 2017 liang.yan
+ * [MOLY00244793] [MT6295M]Bus monitor driver build error call for check in
+ * 	.Patch busmon change to MT6295 MP2 branch
+ *
+ * 06 09 2017 liang.yan
+ * [MOLY00244888] [ZION]Bus monitor driver build error call for check in
+ * 	
+ * 	[LR12A.MP1.5.RDIT]Merge ZION project defining
+ *
+ * 03 02 2017 liang.yan
+ * [MOLY00232074] [Change Feature][BIANCO]Adding busmon monitor MO port Latency feature
+ *
+ * 08 05 2016 liang.yan
+ * [MOLY00195782] [Change Feature]93 busmon driver update
+ *
+ * 03 30 2016 i-chun.liu
+ * [MOLY00171939] 93 Busmon check in
+ * busmon check in .
+ *
+ * 01 29 2016 i-chun.liu
+ * [MOLY00163360] Busmon driver update
+ * fix code defect for ahb_busmon.
+ *
+ * 08 17 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * bus monitor update for ELBRUS.
+ *
+ * 06 09 2015 i-chun.liu
+ * [MOLY00119728] JADE bring up call for check in  (MDCIRQ and Bus monitor )
+ * JADE PCORE BUSMON.
+ *
+ * 04 07 2015 i-chun.liu
+ * [MOLY00106215] TK6291 bus monitor driver update
+ * Pcore bus monitor driver update.
+ *
+ * 12 17 2014 i-chun.liu
+ * [MOLY00087840] Update Moly bus monitor driver for denali1
+ * Moly bus monitor driver update.
+ *
+ * 07 29 2014 brian.chiang
+ * [MOLY00070757] busmon drvier update
+ * Bus monitor driver enhancement
+ *
+ * 04 23 2014 brian.chiang
+ * [MOLY00063514] 6595 busmon driver
+ * 6595 busmon deriver porting
+ *
+ * 12 06 2013 vend_brian.chiang
+ * [MOLY00041938] Fix ATEST linking error
+ * Merge MT6595_E1_DEV  into MOLY trunk
+ *
+ * 03 29 2013 vend_hsientang.lee
+ * [MOLY00013013] Add Busmon driver
+ *
+ ****************************************************************************/
+
+#ifndef __BUSMON_REG_H__
+#define __BUSMON_REG_H__
+#include <reg_base.h>
+
+
+/* ************************************************************************************************
+Below is for Bus Monitor Base Address
+************************************************************************************************ */
+#define BASE_DEBUGAPB_MDMCU_AXIMON0       (BASE_MADDR_DBGSYS_1 + 0x6000)  //0xA008 0000
+#define BASE_DEBUGAPB_MDINFRA_AXIMON0    (BASE_MADDR_DBGSYS_1 + 0x8000)  //0xA008 0000    
+
+#if defined(DEBUG_APB)
+#define BASE_MADDR_MDMCU_AXIMON         BASE_DEBUGAPB_MDMCU_AXIMON0     //0xA008 6000
+#define BASE_MADDR_MDINFRA_AXIMON      BASE_DEBUGAPB_MDINFRA_AXIMON0  //0xA008 8000
+#else /* Normal APB */
+#define BASE_MADDR_MDMCU_AXIMON         BASE_MADDR_MDMCU_BUSMON            //0xA031 0000
+#define BASE_MADDR_MDINFRA_AXIMON      BASE_MADDR_MDINFRABUSMON            //0xA042 0000
+#endif
+    
+/* ************************************************************************************************
+Below is for Bus Monitor 
+************************************************************************************************ */
+/********************************Register Field ********************************/
+#define AXIMON_BASE                                             	           (0)
+
+#define AXIMON_COD_VERSION				(AXIMON_BASE + 0x0000)
+#define AXIMON_DMY_REG					(AXIMON_BASE + 0x0004)
+#define AXIMON_CTL						(AXIMON_BASE + 0x0010)
+#define AXIMON_TST						(AXIMON_BASE + 0x0014)
+#define AXIMON_STS						(AXIMON_BASE + 0x0018)
+#define AXIMON_INT						(AXIMON_BASE + 0x0020)
+#define AXIMON_INT_MSK					(AXIMON_BASE + 0x0024)
+
+#define AXIMON_IP0_TG						(AXIMON_BASE + 0x0030)
+#define AXIMON_IP0_TMR					(AXIMON_BASE + 0x0034)
+#define AXIMON_IP0_ID_CTL					(AXIMON_BASE + 0x0040)
+#define AXIMON_IP0_VPE					           (AXIMON_BASE + 0x0044)
+#define AXIMON_IP0_ADDR					(AXIMON_BASE + 0x0048)
+#define AXIMON_IP0_ADDRMSK				(AXIMON_BASE + 0x004C)
+#define AXIMON_IP0_DATA					(AXIMON_BASE + 0x0050)
+#define AXIMON_IP0_DATAMSK				(AXIMON_BASE + 0x0060)
+
+#define AXIMON_IP1_TG						(AXIMON_BASE + 0x0070)
+#define AXIMON_IP1_TMR					(AXIMON_BASE + 0x0074)
+#define AXIMON_IP1_ID_CTL					(AXIMON_BASE + 0x0080)
+#define AXIMON_IP1_VPE					           (AXIMON_BASE + 0x0084)
+#define AXIMON_IP1_ADDR					(AXIMON_BASE + 0x0088)
+#define AXIMON_IP1_ADDRMSK				(AXIMON_BASE + 0x008C)
+#define AXIMON_IP1_DATA					(AXIMON_BASE + 0x0090)
+#define AXIMON_IP1_DATAMSK				(AXIMON_BASE + 0x00A0)
+
+#define AXIMON_TOT_BUS_CYC				(AXIMON_BASE + 0x0100)
+
+#define AXIMON_IP0_NON_OV_TRANS_NUM	           (AXIMON_BASE + 0x0200)
+#define AXIMON_IP0_OV_TRANS_NUM			(AXIMON_BASE + 0x0204)
+#define AXIMON_IP0_NON_WGT_TRANS_CYC	           (AXIMON_BASE + 0x0208)
+#define AXIMON_IP0_WGT_TRANS_CYC			(AXIMON_BASE + 0x020C)
+#define AXIMON_IP0_MAX_TRANS_CYC			(AXIMON_BASE + 0x0210)
+#define AXIMON_IP0_MAX_OST_TRANS_NUM	           (AXIMON_BASE + 0x0214)
+#define AXIMON_IP0_CUR_OST_TRANS_NUM               (AXIMON_BASE + 0x0218) /*MT6295 NEW Add*/
+
+#define AXIMON_IP0_SNAP_INFO0				(AXIMON_BASE + 0x0220)
+#define AXIMON_IP0_SNAP_INFO1				(AXIMON_BASE + 0x0224) 
+#define AXIMON_IP0_SNAP_INFO2				(AXIMON_BASE + 0x0228)
+#define AXIMON_IP0_SNAP_INFO3				(AXIMON_BASE + 0x022C)
+#define AXIMON_IP0_SNAP_INFO4				(AXIMON_BASE + 0x0230)
+#define AXIMON_IP0_SNAP_INFO5				(AXIMON_BASE + 0x0234)
+#define AXIMON_IP0_SNAP_INFO6				(AXIMON_BASE + 0x0238)
+#define AXIMON_IP0_SNAP_INFO7				(AXIMON_BASE + 0x023C)
+#define AXIMON_IP0_SNAP_INFO8				(AXIMON_BASE + 0x0240)
+#define AXIMON_IP0_SNAP_INFO9				(AXIMON_BASE + 0x0244)
+#define AXIMON_IP0_SNAP_INFO10			           (AXIMON_BASE + 0x0248)
+#define AXIMON_IP0_SNAP_INFO11			           (AXIMON_BASE + 0x024C)    
+
+#define AXIMON_IP1_NON_OV_TRANS_NUM	           (AXIMON_BASE + 0x0280)
+#define AXIMON_IP1_OV_TRANS_NUM			(AXIMON_BASE + 0x0284)
+#define AXIMON_IP1_NON_WGT_TRANS_CYC	           (AXIMON_BASE + 0x0288)
+#define AXIMON_IP1_WGT_TRANS_CYC			(AXIMON_BASE + 0x028C)
+#define AXIMON_IP1_MAX_TRANS_CYC			(AXIMON_BASE + 0x0290)
+#define AXIMON_IP1_MAX_OST_TRANS_NUM	           (AXIMON_BASE + 0x0294)
+#define AXIMON_IP1_CUR_OST_TRANS_NUM	           (AXIMON_BASE + 0x0298) /*MT6295 NEW Add*/
+
+#define AXIMON_IP1_SNAP_INFO0				(AXIMON_BASE + 0x02A0)
+#define AXIMON_IP1_SNAP_INFO1				(AXIMON_BASE + 0x02A4) 
+#define AXIMON_IP1_SNAP_INFO2				(AXIMON_BASE + 0x02A8)
+#define AXIMON_IP1_SNAP_INFO3				(AXIMON_BASE + 0x02AC)
+#define AXIMON_IP1_SNAP_INFO4				(AXIMON_BASE + 0x02B0)
+#define AXIMON_IP1_SNAP_INFO5				(AXIMON_BASE + 0x02B4)
+#define AXIMON_IP1_SNAP_INFO6				(AXIMON_BASE + 0x02B8)
+#define AXIMON_IP1_SNAP_INFO7				(AXIMON_BASE + 0x02BC)
+#define AXIMON_IP1_SNAP_INFO8				(AXIMON_BASE + 0x02C0)
+#define AXIMON_IP1_SNAP_INFO9				(AXIMON_BASE + 0x02C4)
+#define AXIMON_IP1_SNAP_INFO10			           (AXIMON_BASE + 0x02C8)
+#define AXIMON_IP1_SNAP_INFO11			           (AXIMON_BASE + 0x02CC)
+
+/********************************Register Offset Field ********************************/
+#define AXIMON_CFG_OFFSET                       				           (0x0040) /*AXIMON_IP1_TG - AXIMON_IP0_TG*/
+#define AXIMON_INFO_OFFSET                      				           (0x0080) /*AXIMON_IP1_SNAP_INFO0 - AXIMON_IP0_SNAP_INFO0*/
+
+#define AXIMON_IP_TG_OFFSET						(0x0030) /*AXIMON_IP0_TG - AXIMON_BASE*/
+#define AXIMON_IP_TMR_OFFSET						(0x0034) /*AXIMON_IP0_TMR_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_ID_CTL_OFFSET					           (0x0040) /*AXIMON_IP0_ID_CTL_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_VPE_OFFSET						(0x0044) /*AXIMON_IP0_VPE_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_ADDR_OFFSET						(0x0048) /*AXIMON_IP0_ADDR_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_ADDRMSK_OFFSET					(0x004C) /*AXIMON_IP0_ADDRMSK_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_DATA_OFFSET						(0x0050) /*AXIMON_IP0_DATA_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_DATAMSK_OFFSET					(0x0060) /*AXIMON_IP0_DATAMSK_OFFSET - AXIMON_BASE*/
+
+#define AXIMON_IP_NON_OV_TRANS_NUM_OFFSET                        (0x0200) /*AXIMON_IP0_NON_OV_TRANS_NUM_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_OV_TRANS_NUM_OFFSET                 		(0x0204) /*AXIMON_IP0_OV_TRANS_NUM_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_NON_WGT_TRANS_CYC_OFFSET            	(0x0208) /*AXIMON_IP0_NON_WGT_TRANS_CYC_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_WGT_TRANS_CYC_OFFSET                		(0x020C) /*AXIMON_IP0_WGT_TRANS_CYC_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_MAX_TRANS_CYC_OFFSET                		(0x0210) /*AXIMON_IP0_MAX_TRANS_CYC_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_MAX_OST_TRANS_NUM_OFFSET            	(0x0214) /*AXIMON_IP0_MAX_OST_TRANS_NUM_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_CUR_OST_TRANS_NUM				(0x0218) /*MT6295 NEW Add:AXIMON_IP_CUR_OST_TRANS_NUM - AXIMON_BASE*/
+
+#define AXIMON_IP_SNAP_INFO0_OFFSET                   		(0x0220) /*AXIMON_IP0_SNAP_INFO0_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO1_OFFSET                   		(0x0224) /*AXIMON_IP0_SNAP_INFO1_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO2_OFFSET                   		(0x0228) /*AXIMON_IP0_SNAP_INFO2_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO3_OFFSET                   		(0x022C) /*AXIMON_IP0_SNAP_INFO3_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO4_OFFSET                   		(0x0230) /*AXIMON_IP0_SNAP_INFO4_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO5_OFFSET                    		(0x0234) /*AXIMON_IP0_SNAP_INFO5_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO6_OFFSET                    		(0x0238) /*AXIMON_IP0_SNAP_INFO6_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO7_OFFSET                    		(0x023C) /*AXIMON_IP0_SNAP_INFO7_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO8_OFFSET                    		(0x0240) /*AXIMON_IP0_SNAP_INFO8_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO9_OFFSET                    		(0x0244) /*AXIMON_IP0_SNAP_INFO9_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO10_OFFSET                  		(0x0248) /*AXIMON_IP0_SNAP_INFO10_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO11_OFFSET                  		(0x024C) /*AXIMON_IP0_SNAP_INFO11_OFFSET - AXIMON_BASE*/
+
+/******************************** Default Value ********************************/
+#define AXIMON_COD_VERSION_DEFAULT              			(0x20170728)
+
+/******************************** Bit Field & Mask ********************************/
+#define AXIMON_CODA_VERSION_MASK				           (0xFFFFFFFF)   
+#define AXIMON_CODA_VERSION_SHIFT               			(0)           			 
+
+/*register:AXIMON_CTL*/
+#define AXIMON_CTL_START_MASK					           (0x1)         
+#define AXIMON_CTL_START_SHIFT						(0)            
+
+/*register:AXIMON_TST*/
+#define AXIMON_TST_SEQ_TRG_MODE_MASK			          (0x1)      
+#define AXIMON_TST_SEQ_TRG_MODE_SHIFT           		           (0)            
+#define AXIMON_TST_SEQ_CHECK_MODE_MASK          		(0x1) /*default value is 1*/      
+#define AXIMON_TST_SEQ_CHECK_MODE_SHIFT         		(1)             
+#define AXIMON_TST_DISABLE_CG_MASK              			(0x1)        
+#define AXIMON_TST_DISABLE_CG_SHIFT             			(2)          
+#define AXIMON_TST_CLEAR_AT_BUSIDLE_MASK        		(0x1) /*default value is 1*/  
+#define AXIMON_TST_CLEAR_AT_BUSIDLE_SHIFT       		(3)           
+#define AXIMON_TST_SPEED_SIM_MASK               			(0x1)   
+#define AXIMON_TST_SPEED_SIM_SHIFT              			(8)           
+#define AXIMON_TST_CYC_CNT_WRAP_EN_MASK			(0x1) /*MT6295 NEW ADD, default value is 1*/
+#define AXIMON_TST_CYC_CNT_WRAP_EN_SHIFT			(9)		
+#define AXIMON_TST_LYR_AXI_SEL_MASK             			(0xF) /*default value: MDMCU busmon is 4, MDINFRA busmon is 0*/          
+#define AXIMON_TST_LYR_AXI_SEL_SHIFT            			(16)        
+
+/*register:AXIMON_STS*/
+#define AXIMON_STS_STAT0_MASK                   				(0x3)          
+#define AXIMON_STS_STAT0_SHIFT                 	 			(0)		
+#define AXIMON_STS_STAT1_MASK                   				(0x3)      
+#define AXIMON_STS_STAT1_SHIFT                  				(4)		
+#define AXIMON_STS_IP0_CUR_OVERFLOW_MASK        		(0x1)        
+#define AXIMON_STS_IP0_CUR_OVERFLOW_SHIFT       		(8) 		
+#define AXIMON_STS_IP0_CUR_UNDERFLOW_MASK       	           (0x1)        
+#define AXIMON_STS_IP0_CUR_UNDERFLOW_SHIFT      		(9)      	
+#define AXIMON_STS_IP1_CUR_OVERFLOW_MASK        		(0x1)
+#define AXIMON_STS_IP1_CUR_OVERFLOW_SHIFT       		(10)   	
+#define AXIMON_STS_IP1_CUR_UNDERFLOW_MASK       	           (0x1)   
+#define AXIMON_STS_IP1_CUR_UNDERFLOW_SHIFT      		(11)  	
+#define AXIMON_STS_IP0_HIS_OVERFLOW_MASK        		(0x1)    
+#define AXIMON_STS_IP0_HIS_OVERFLOW_SHIFT       		(12)   	
+#define AXIMON_STS_IP0_HIS_UNDERFLOW_MASK       		(0x1)        
+#define AXIMON_STS_IP0_HIS_UNDERFLOW_SHIFT      		(13)  	
+#define AXIMON_STS_IP1_HIS_OVERFLOW_MASK        		(0x1)        
+#define AXIMON_STS_IP1_HIS_OVERFLOW_SHIFT       		(14)   	
+#define AXIMON_STS_IP1_HIS_UNDERFLOW_MASK       		(0x1)    
+#define AXIMON_STS_IP1_HIS_UNDERFLOW_SHIFT      		(15)   	
+#define AXIMON_STS_IP0_CUR_ID_MISS_MASK         		           (0x1)          
+#define AXIMON_STS_IP0_CUR_ID_MISS_SHIFT        		           (16)  	
+#define AXIMON_STS_IP1_CUR_ID_MISS_MASK         		           (0x1)        
+#define AXIMON_STS_IP1_CUR_ID_MISS_SHIFT        		           (17)   
+#define AXIMON_STS_IP0_HIS_ID_MISS_MASK         		           (0x1)    
+#define AXIMON_STS_IP0_HIS_ID_MISS_SHIFT        			(18)          
+#define AXIMON_STS_IP1_HIS_ID_MISS_MASK         		           (0x1)         
+#define AXIMON_STS_IP1_HIS_ID_MISS_SHIFT        			(19)         
+#define AXIMON_STS_IP_TRG_INT_MASK              			(0x1)   
+#define AXIMON_STS_IP_TRG_INT_SHIFT             			(20)           
+#define AXIMON_STS_MON_REALENABLE_MASK          		(0x1)     
+#define AXIMON_STS_MON_REALENABLE_SHIFT        	 	(31)       
+
+/*register:AXIMON_INT*/
+#define AXIMON_INT_MASK                         				           (0x1)
+#define AXIMON_INT_SHIFT                        					(0)		
+
+/*register:AXIMON_INT_MSK*/
+#define AXIMON_INT_MSK_MASK                     				(0x1)      
+#define AXIMON_INT_MSK_SHIFT                    				(0)		
+
+/*register:AXIMON_IP0_TG&AXIMON_IP1_TG*/
+#define AXIMON_TG_MON_CNT_WRAP_EN_MASK		           (0x1) /*MT6295 NEW ADD:default value is 1*/
+#define AXIMON_TG_MON_CNT_WRAP_EN_SHIFT			(4) /* [4] */
+#define AXIMON_TG_MON_RWSEL_MASK                			(0x1) /*IP0 default value is 1:read transaction; IP1 default value is 0:write transaction*/      
+#define AXIMON_TG_MON_RWSEL_SHIFT               			(8)            	
+#define AXIMON_TG_MON_MODE_MASK                 			(0x1) /*default value is 1*/      
+#define AXIMON_TG_MON_MODE_SHIFT                			(9)            	
+#define AXIMON_TG_MON_ENABLE_MASK               		           (0x1) /*default value is 1*/         
+#define AXIMON_TG_MON_ENABLE_SHIFT              			(10)           
+#define AXIMON_TG_TRG_MODE_MASK                 			(0x1) /*default value is 0*/  
+#define AXIMON_TG_TRG_MODE_SHIFT                			(11)           	
+#define AXIMON_TG_MON_ALL_MST_MASK              		           (0x1) /*default value is 1*/     
+#define AXIMON_TG_MON_ALL_MST_SHIFT             			(12)           
+#define AXIMON_TG_SNAP_DATA_ENABLE_MASK         		(0x1)  /*default value is 0*/            
+#define AXIMON_TG_SNAP_DATA_ENABLE_SHIFT        		(13) 
+#define AXIMON_TG_MON_CNT_MASK                  			           (0xFFFF)	
+#define AXIMON_TG_MON_CNT_SHIFT                 			           (16)           	
+
+/*register:AXIMON_IP0_TMR&AXIMON_IP1_TMR*/
+#define AXIMON_TMR_MON_TRG_CYC_MASK             		(0xFFFF)    
+#define AXIMON_TMR_MON_TRG_CYC_SHIFT            		(0)            
+
+/*register:AXIMON_IP0_ID_CTL&AXIMON_IP1_ID_CTL*/
+#define AXIMON_ID_MON_MASTER_MASK               		           (0xFFFF)      
+#define AXIMON_ID_MON_MASTER_SHIFT              			(0)            
+#define AXIMON_ID_MON_MASTER_MSK_MASK           		(0xFFFF)      
+#define AXIMON_ID_MON_MASTER_MSK_SHIFT          		(16)        
+
+/*register:AXIMON_IP0_VPE&AXIMON_IP1_VPE*/
+#define AXIMON_VPE_MON_VPE_MASK                 			(0x7F) /*MT6295 NEW CHANGE:this just for MDMCU busmon, MDINFRA busmon do not have VPE signal*/       
+#define AXIMON_VPE_MON_VPE_SHIFT                			(0)         /* [6:0] */
+#define AXIMON_VPE_MON_VPE_MSK_MASK             		           (0x7F) /*MT6295 NEW CHANGE:this just for MDMCU busmon, MDINFRA busmon do not have VPE signal*/ 
+#define AXIMON_VPE_MON_VPE_MSK_SHIFT            		           (7)         /* [13:7] */
+#define AXIMON_VPE_MON_ULTRA_MASK               		           (0x3)   /*MT6295 NEW CHANGE*/      
+#define AXIMON_VPE_MON_ULTRA_SHIFT              			(24)      /* [25:24] */  
+#define AXIMON_VPE_MON_ULTRA_MSK_MASK           		(0x3)   /*MT6295 NEW CHANGE*/       
+#define AXIMON_VPE_MON_ULTRA_MSK_SHIFT          		(28)      /* [29:28] */
+
+/*register:AXIMON_IP0_ADDR&AXIMON_IP1_ADDR*/
+#define AXIMON_ADDR_MASK                        				(0xFFFFFFFF)   
+#define AXIMON_ADDR_SHIFT                       				           (0)            
+
+/*register:AXIMON_IP0_ADDRMSK&AXIMON_IP1_ADDRMSK*/
+#define AXIMON_ADDRMSK_MASK                     			           (0xFFFFFFFF)  
+#define AXIMON_ADDRMSK_SHIFT                    				(0)     
+
+/*register:AXIMON_IP0_DATA&AXIMON_IP1_DATA*/
+#define AXIMON_DATA_MASK                       				           (0xFFFFFFFF)  
+#define AXIMON_DATA_SHIFT                      				           (0)           
+
+/*register:AXIMON_IP0_DATAMSK&AXIMON_IP1_DATAMSK*/
+#define AXIMON_DATAMSK_MASK                    				(0xFFFFFFFF)  
+#define AXIMON_DATAMSK_SHIFT                   				(0)          
+
+/*register:AXIMON_TOT_BUS_CYC*/
+#define AXIMON_TOT_BUS_CYC_MASK                 			           (0xFFFFFF) /* [23:0] */
+#define AXIMON_TOT_BUS_CYC_SHIFT                			           (0)            
+
+/*register:AXIMON_IP0_NON_OV_TRANS_NUM&AXIMON_IP1_NON_OV_TRANS_NUM*/
+#define AXIMON_NON_OV_TRANS_NUM_MASK            		(0xFFFFFF)    
+#define AXIMON_NON_OV_TRANS_NUM_SHIFT           		           (0)          
+
+/*register:AXIMON_IP0_OV_TRANS_NUM&AXIMON_IP1_OV_TRANS_NUM*/
+#define AXIMON_OV_TRANS_NUM_MASK                			(0xFFFFFF)    
+#define AXIMON_OV_TRANS_NUM_SHIFT               			(0)            
+
+/*register:AXIMON_IP0_NON_WGT_TRANS_CYC&AXIMON_IP1_NON_WGT_TRANS_CYC*/
+#define AXIMON_NON_WGT_TRANS_CYC_MASK           		(0xFFFFFFF) /* [27:0] */
+#define AXIMON_NON_WGT_TRANS_CYC_SHIFT          		(0)           
+
+/*register:AXIMON_IP0_WGT_TRANS_CYC&AXIMON_IP1_WGT_TRANS_CYC*/
+#define AXIMON_WGT_TRANS_CYC_MASK               			(0xFFFFFFFF) /* [31:0] */
+#define AXIMON_WGT_TRANS_CYC_SHIFT              			(0)          
+
+/*register:AXIMON_IP0_MAX_TRANS_CYC&AXIMON_IP1_MAX_TRANS_CYC*/
+#define AXIMON_MAX_TRANS_CYC_MASK               			(0xFFFFFF) /* [23:0] */
+#define AXIMON_MAX_TRANS_CYC_SHIFT              			(0)            
+
+/*register:AXIMON_IP0_MAX_OST_TRANS_NUM&AXIMON_IP1_MAX_OST_TRANS_NUM*/
+#define AXIMON_MAX_OST_TRANS_NUM_MASK           		(0x3F) /* [5:0] */        
+#define AXIMON_MAX_OST_TRANS_NUM_SHIFT          		(0) 
+
+/*register:AXIMON_IP0_CUR_OST_TRANS_NUM&AXIMON_IP1_CUR_OST_TRANS_NUM*/
+#define AXIMON_CUR_OST_TRANS_NUM_MASK			(0x3F) /*MT6295 NEW ADD*/       
+#define AXIMON_CUR_OST_TRANS_NUM_SHIFT			(0)         /*[5:0]*/
+
+/*register:AXIMON_IP0_SNAP_INFO0&AXIMON_IP1_SNAP_INFO0*/
+#define AXIMON_SNAP_INFO0_VPE_MASK              			(0x7F) /*MT6295 NEW CHANGE:this just for MDMCU busmon, MDINFRA busmon do not have VPE signal*/       
+#define AXIMON_SNAP_INFO0_VPE_SHIFT             			(0)         /* [6:0] */
+#define AXIMON_SNAP_INFO0_LEN_MASK             			(0xF)   /*MT6295 NEW CHANGE*/     
+#define AXIMON_SNAP_INFO0_LEN_SHIFT             			(8)         /* [11:8] */
+#define AXIMON_SNAP_INFO0_SIZE_MASK             			(0x7)    /*MT6295 NEW CHANGE*/       
+#define AXIMON_SNAP_INFO0_SIZE_SHIFT            			(12)       /* [14:12] */ 
+#define AXIMON_SNAP_INFO0_ULTRA_MASK            		           (0x3)    /*MT6295 NEW CHANGE*/       
+#define AXIMON_SNAP_INFO0_ULTRA_SHIFT           		           (15)       /* [16:15] */
+#define AXIMON_SNAP_INFO0_BURST_MASK            		           (0x3)    /*MT6295 NEW CHANGE*/       
+#define AXIMON_SNAP_INFO0_BURST_SHIFT           		           (17)       /* [18:17] */ 
+#define AXIMON_SNAP_INFO0_LOCK_MASK             		           (0x3)     /*MT6295 NEW CHANGE*/        
+#define AXIMON_SNAP_INFO0_LOCK_SHIFT            			(19)        /* [20:19] */
+#define AXIMON_SNAP_INFO0_CACHE_MASK            		           (0xF)     /*MT6295 NEW CHANGE*/        
+#define AXIMON_SNAP_INFO0_CACHE_SHIFT           		           (21)        /* [24:21] */
+#define AXIMON_SNAP_INFO0_PROT_MASK             		           (0x7)     /*MT6295 NEW CHANGE*/      
+#define AXIMON_SNAP_INFO0_PROT_SHIFT            			(25)        /* [27:25] */
+#define AXIMON_SNAP_INFO0_RESP_MASK             		           (0x3)     /*MT6295 NEW CHANGE*/      
+#define AXIMON_SNAP_INFO0_RESP_SHIFT            			(28)        /* [29:28] */
+
+/*register:AXIMON_IP0_SNAP_INFO1&AXIMON_IP1_SNAP_INFO1*/
+#define AXIMON_SNAP_INFO1_QID_MASK              			(0xFFFF)        
+#define AXIMON_SNAP_INFO1_QID_SHIFT            			(0)            
+#define AXIMON_SNAP_INFO1_CNT_MASK              			(0xFFFF)       
+#define AXIMON_SNAP_INFO1_CNT_SHIFT             			(16)            
+
+#define AXIMON_SNAP_INFO2_ADDRESS_MASK          		(0xFFFFFFFF)  
+#define AXIMON_SNAP_INFO2_ADDRESS_SHIFT         		(0)             
+
+#define AXIMON_SNAP_INFO3_STRB0_MASK            		           (0xFFFF)       
+#define AXIMON_SNAP_INFO3_STRB0_SHIFT           			(0)             
+#define AXIMON_SNAP_INFO3_STRB1_MASK            		           (0xFFFF)       
+#define AXIMON_SNAP_INFO3_STRB1_SHIFT           			(16)       
+
+#define AXIMON_SNAP_INFO4_DATA00_MASK           		           (0xFFFFFFFF)   
+#define AXIMON_SNAP_INFO4_DATA00_SHIFT          		           (0)      
+
+#define AXIMON_SNAP_INFO5_DATA01_MASK           		           (0xFFFFFFFF)    
+#define AXIMON_SNAP_INFO5_DATA01_SHIFT          		           (0)          
+
+#define AXIMON_SNAP_INFO6_DATA02_MASK           		           (0xFFFFFFFF)  
+#define AXIMON_SNAP_INFO6_DATA02_SHIFT          		           (0)         
+
+#define AXIMON_SNAP_INFO7_DATA03_MASK           		           (0xFFFFFFFF)    
+#define AXIMON_SNAP_INFO7_DATA03_SHIFT          		           (0)  
+
+#define AXIMON_SNAP_INFO8_DATA10_MASK           		           (0xFFFFFFFF)    
+#define AXIMON_SNAP_INFO8_DATA10_SHIFT          		           (0)    
+
+#define AXIMON_SNAP_INFO9_DATA11_MASK           		           (0xFFFFFFFF)    
+#define AXIMON_SNAP_INFO9_DATA11_SHIFT          		           (0)  
+
+#define AXIMON_SNAP_INFO10_DATA12_MASK          		(0xFFFFFFFF)    
+#define AXIMON_SNAP_INFO10_DATA12_SHIFT         		(0)       
+
+#define AXIMON_SNAP_INFO11_DATA13_MASK          		(0xFFFFFFFF)   
+#define AXIMON_SNAP_INFO11_DATA13_SHIFT         		(0)             
+
+#define AXIMON_MATCH_NONE                      				(0xFFFFFFFF)
+#define AXIMON_MATCH_ALL                       		 		           (0)
+
+#define AXIMON_MDMCU_LAYER_SELECT               			(BASE_MADDR_MDPERIMISC + 0x504)
+#define AXIMON_MDINFRA_LAYER_SELECT             			(BASE_MADDR_MDPERIMISC + 0x500) 
+
+
+/* ************************************************************************************************
+Below is for Bus recorder 
+************************************************************************************************ */
+/******************************** Register Field ********************************/
+#define BUSREC_REG_RECORDER_CTL       				(AXIMON_BASE + 0x400U)
+#define BUSREC_REG_RECORDER_TEST      				(AXIMON_BASE + 0x404U)
+#define BUSREC_REG_MON_REC_OBSRV_CTRL			           (AXIMON_BASE + 0x408U)	/*MT6295 NEW ADD*/     
+
+#define BUSREC_REG_IP0_BUFF_CNT       					(AXIMON_BASE + 0x500U)
+#define BUSREC_REG_MON_IP0_GRP_CMD_STS			(AXIMON_BASE + 0x504U)	/*MT6295 NEW ADD*/     
+#define BUSREC_REG_IP0_GRP1_ID_STS    				(AXIMON_BASE + 0x510U)
+#define BUSREC_REG_IP0_GRP1_ADDR_STS  				(AXIMON_BASE + 0x514U) 
+#define BUSREC_REG_IP0_GRP1_ID_STS_(n)            			(AXIMON_BASE + 0x510U + (n) * 0x8)
+#define BUSREC_REG_IP0_GRP1_ADDR_STS_(n)          		(AXIMON_BASE + 0x514U + (n) * 0x8)
+
+#define BUSREC_REG_IP1_BUFF_CNT       					(AXIMON_BASE + 0x700U)
+#define BUSREC_REG_MON_IP1_GRP_CMD_STS			(AXIMON_BASE + 0x704U)	/*MT6295 NEW ADD*/
+#define BUSREC_REG_IP1_GRP1_ID_STS    				(AXIMON_BASE + 0x710U)
+#define BUSREC_REG_IP1_GRP1_ADDR_STS  				(AXIMON_BASE + 0x714U) 
+#define BUSREC_REG_IP1_GRP1_ID_STS_(n)            			(AXIMON_BASE + 0x710U + (n) * 0x8)
+#define BUSREC_REG_IP1_GRP1_ADDR_STS_(n)          		(AXIMON_BASE + 0x714U + (n) * 0x8)
+
+#define BUSREC_REG_CURR_IP0_ID_STS   				(AXIMON_BASE + 0x820U)
+#define BUSREC_REG_CURR_IP0_ADDR_STS 				(AXIMON_BASE + 0x824U)
+#define BUSREC_REG_CURR_IP0_VPE_STS				(AXIMON_BASE + 0x828U)	/*MT6295 NEW ADD*/
+#define BUSREC_REG_CURR_IP0_CTRL_STS 				(AXIMON_BASE + 0x82CU)
+
+#define BUSREC_MON_IP0_GRP_HIS_ID_STS				(AXIMON_BASE + 0x830U)	/*MT6295 NEW ADD*/
+#define BUSREC_MON_IP0_GRP_HIS_CMD_STS			           (AXIMON_BASE + 0x834U)	/*MT6295 NEW ADD*/
+#define BUSREC_MON_IP0_GRP_HIS_ADDR_STS			(AXIMON_BASE + 0x838U)	/*MT6295 NEW ADD*/
+
+#define BUSREC_REG_CURR_IP1_ID_STS   				(AXIMON_BASE + 0x850U)
+#define BUSREC_REG_CURR_IP1_ADDR_STS 				(AXIMON_BASE + 0x854U)
+#define BUSREC_REG_CURR_IP1_VPE_STS				(AXIMON_BASE + 0x858U)	/*MT6295 NEW ADD*/
+#define BUSREC_REG_CURR_IP1_CTRL_STS 				(AXIMON_BASE + 0x85CU)
+
+#define BUSREC_MON_IP1_GRP_HIS_ID_STS				(AXIMON_BASE + 0x860U)	/*MT6295 NEW ADD*/
+#define BUSREC_MON_IP1_GRP_HIS_CMD_STS			           (AXIMON_BASE + 0x864U)	/*MT6295 NEW ADD*/
+#define BUSREC_MON_IP1_GRP_HIS_ADDR_STS			(AXIMON_BASE + 0x868U)	/*MT6295 NEW ADD*/
+
+#define BUSREC_MON_IDLE_CTRL						(AXIMON_BASE + 0x918U)	/*MT6295 NEW ADD*/
+
+#define BUSREC_REG_LOG_CTL                                                                   (AXIMON_BASE + 0x900U)
+#define BUSREC_REG_LOG_STS                                                                   (AXIMON_BASE + 0x904U)
+#define BUSREC_REG_LOG_SW_FORCE_OUT                                         (AXIMON_BASE + 0x908U)
+#define BUSREC_REG_LOG_CG_DIS                                                            (AXIMON_BASE + 0x90CU)
+#define BUSREC_REG_LOG_TEST_CTL                                                      (AXIMON_BASE + 0x910U)
+
+/******************************** Bit Field & Mask ********************************/
+/*register:BUSREC_REG_RECORDER_CTL*/
+#define BUSREC_CTL_TEST_MODE_MASK                   			(0x1)          
+#define BUSREC_CTL_TEST_MODE_SHIFT                  			(2)            
+#define BUSREC_CTL_GATE_AR_MASK                     			(0x1)          
+#define BUSREC_CTL_GATE_AR_SHIFT                    			(4)           
+#define BUSREC_CTL_GATE_AW_MASK                     			(0x1)          
+#define BUSREC_CTL_GATE_AW_SHIFT                    			(5)            
+#define BUSREC_CTL_GATE_R_RESP_MASK                 		           (0x1)          
+#define BUSREC_CTL_GATE_R_RESP_SHIFT                			(6)            
+#define BUSREC_CTL_GATE_B_RESP_MASK                 		           (0x1)          
+#define BUSREC_CTL_GATE_B_RESP_SHIFT                			(7)           
+#define BUSREC_CTL_GATE_W_RESP_MASK                 		           (0x1)          
+#define BUSREC_CTL_GATE_W_RESP_SHIFT                		           (8)          
+
+/*register:BUSREC_REG_RECORDER_TEST*/
+#define BUSREC_TEST_TRANS_ADD_MASK                   		           (0x1)          
+#define BUSREC_TEST_TRANS_ADD_SHIFT                  		           (0)            
+#define BUSREC_TEST_TRANS_ADD_ID_MASK                		(0xFF)         
+#define BUSREC_TEST_TRANS_ADD_ID_SHIFT               		(8)        
+#define BUSREC_TEST_TRANS_SUB_MASK                   		           (0x1)        
+#define BUSREC_TEST_TRANS_SUB_SHIFT                  			(16)            
+#define BUSREC_TEST_TRANS_SUB_ID_MASK                		(0xFF)       
+#define BUSREC_TEST_TRANS_SUB_ID_SHIFT               		(24)            
+
+/*register:BUSREC_REG_MON_REC_OBSRV_CTRL*/
+#define BUSREC_IP0_MON_HIS_FILTER_EN_MASK			(0x1)	/*MT6295 NEW ADD*/
+#define BUSREC_IP0_MON_HIS_FILTER_EN_SHIFT			(0)		/*MT6295 NEW ADD*/
+#define BUSREC_IP0_HIS_REC_ENTRY_SEL_MASK			(0x7)	/*MT6295 NEW ADD*/
+#define BUSREC_IP0_HIS_REC_ENTRY_SEL_SHIFT			(4)		/*MT6295 NEW ADD*/
+#define BUSREC_IP0_REC_ENTRY_SEL_MASK				(0x1F)	/*MT6295 NEW ADD*/
+#define BUSREC_IP0_REC_ENTRY_SEL_SHIFT				(8)		/*MT6295 NEW ADD*/
+#define BUSREC_IP1_MON_HIS_FILTER_EN_MASK			(0x1)	/*MT6295 NEW ADD*/
+#define BUSREC_IP1_MON_HIS_FILTER_EN_SHIFT			(16)		/*MT6295 NEW ADD*/
+#define BUSREC_IP1_HIS_REC_ENTRY_SEL_MASK			(0x7)	/*MT6295 NEW ADD*/
+#define BUSREC_IP1_HIS_REC_ENTRY_SEL_SHIFT			(20)		/*MT6295 NEW ADD*/
+#define BUSREC_IP1_REC_ENTRY_SEL_MASK				(0x1F)	/*MT6295 NEW ADD*/
+#define BUSREC_IP1_REC_ENTRY_SEL_SHIFT				(24)		/*MT6295 NEW ADD*/
+#define BUSREC_MON_HIS_REC_EN_MASK				(0x1)	/*MT6295 NEW ADD*/
+#define BUSREC_MON_HIS_REC_EN_SHIFT				(31)		/*MT6295 NEW ADD*/
+
+/*register:BUSREC_REG_MON_IP0_GRP_CMD_STS&BUSREC_REG_MON_IP1_GRP_CMD_STS*/
+#define BUSREC_GRP_CMD_AXLEN_MASK				           (0XF)	/*MT6295 NEW ADD*/
+#define BUSREC_GRP_CMD_AXLEN_SHIFT				(0)		/*MT6295 NEW ADD*/
+#define BUSREC_GRP_CMD_AXSIZE_MASK				(0X7)	/*MT6295 NEW ADD*/
+#define BUSREC_GRP_CMD_AXSIZE_SHIFT				(4)		/*MT6295 NEW ADD*/
+#define BUSREC_GRP_CMD_AXULTRA_MASK				(0X3)	/*MT6295 NEW ADD*/
+#define BUSREC_GRP_CMD_AXULTRA_SHIFT				(7)		/*MT6295 NEW ADD*/
+#define BUSREC_GRP_CMD_AXBURST_MASK				(0X3)	/*MT6295 NEW ADD*/
+#define BUSREC_GRP_CMD_AXBURST_SHIFT				(9)		/*MT6295 NEW ADD*/
+#define BUSREC_GRP_CMD_AXLOCK_MASK				(0X3)	/*MT6295 NEW ADD*/
+#define BUSREC_GRP_CMD_AXLOCK_SHIFT				(11)		/*MT6295 NEW ADD*/
+#define BUSREC_GRP_CMD_AXCACHE_MASK				(0XF)	/*MT6295 NEW ADD*/
+#define BUSREC_GRP_CMD_AXCACHE_SHIFT				(13)		/*MT6295 NEW ADD*/
+#define BUSREC_GRP_CMD_AXPORT_MASK				(0X7)	/*MT6295 NEW ADD*/
+#define BUSREC_GRP_CMD_AXPORT_SHIFT				(17)		/*MT6295 NEW ADD*/
+#define BUSREC_GRP_CMD_AXMATCH_MASK			           (0X1)	/*MT6295 NEW ADD*/
+#define BUSREC_GRP_CMD_AXMATCH_SHIFT				(20)		/*MT6295 NEW ADD*/
+
+#define BUSREC_MDMCU_HIS_AXVPE_MASK				(0X7F)	/*MT6295 NEW ADD*/
+#define BUSREC_MDMCU_HIS_AXVPE_SHIFT				(0)		/*MT6295 NEW ADD*/
+#define BUSREC_MDMCU_HIS_AXLEN_MASK				(0XF)	/*MT6295 NEW ADD*/
+#define BUSREC_MDMCU_HIS_AXLEN_SHIFT				(7)		/*MT6295 NEW ADD*/
+#define BUSREC_MDMCU_HIS_AXSIZE_MASK				(0X7)	/*MT6295 NEW ADD*/
+#define BUSREC_MDMCU_HIS_AXSIZE_SHIFT				(11)		/*MT6295 NEW ADD*/
+#define BUSREC_MDMCU_HIS_AXULTRA_MASK			(0X3)	/*MT6295 NEW ADD*/
+#define BUSREC_MDMCU_HIS_AXULTRA_SHIFT			(14)		/*MT6295 NEW ADD*/
+#define BUSREC_MDMCU_HIS_AXBURST_MASK			(0X3)	/*MT6295 NEW ADD*/
+#define BUSREC_MDMCU_HIS_AXBURST_SHIFT			(16)		/*MT6295 NEW ADD*/
+#define BUSREC_MDMCU_HIS_AXLOCK_MASK			           (0X3)	/*MT6295 NEW ADD*/
+#define BUSREC_MDMCU_HIS_AXLOCK_SHIFT			           (18)		/*MT6295 NEW ADD*/
+#define BUSREC_MDMCU_HIS_AXCACHE_MASK			(0XF)	/*MT6295 NEW ADD*/
+#define BUSREC_MDMCU_HIS_AXCACHE_SHIFT			(20)		/*MT6295 NEW ADD*/
+#define BUSREC_MDMCU_HIS_AXPORT_MASK			           (0X7)	/*MT6295 NEW ADD*/
+#define BUSREC_MDMCU_HIS_AXPORT_SHIFT			           (24)		/*MT6295 NEW ADD*/
+
+#define BUSREC_MDINFRA_HIS_AXVPE_MASK			           (0X0)	/*MT6295 NEW ADD*/
+#define BUSREC_MDINFRA_HIS_AXVPE_SHIFT			           (0)		/*MT6295 NEW ADD*/
+#define BUSREC_MDINFRA_HIS_AXLEN_MASK			           (0XF)	/*MT6295 NEW ADD*/
+#define BUSREC_MDINFRA_HIS_AXLEN_SHIFT			           (1)		/*MT6295 NEW ADD*/
+#define BUSREC_MDINFRA_HIS_AXSIZE_MASK			           (0X7)	/*MT6295 NEW ADD*/
+#define BUSREC_MDINFRA_HIS_AXSIZE_SHIFT			(5)		/*MT6295 NEW ADD*/
+#define BUSREC_MDINFRA_HIS_AXULTRA_MASK			(0X3)	/*MT6295 NEW ADD*/
+#define BUSREC_MDINFRA_HIS_AXULTRA_SHIFT			(8)		/*MT6295 NEW ADD*/
+#define BUSREC_MDINFRA_HIS_AXBURST_MASK			(0X3)	/*MT6295 NEW ADD*/
+#define BUSREC_MDINFRA_HIS_AXBURST_SHIFT			(10)		/*MT6295 NEW ADD*/
+#define BUSREC_MDINFRA_HIS_AXLOCK_MASK			(0X3)	/*MT6295 NEW ADD*/
+#define BUSREC_MDINFRA_HIS_AXLOCK_SHIFT			(12)		/*MT6295 NEW ADD*/
+#define BUSREC_MDINFRA_HIS_AXCACHE_MASK			(0XF)	/*MT6295 NEW ADD*/
+#define BUSREC_MDINFRA_HIS_AXCACHE_SHIFT			(14)		/*MT6295 NEW ADD*/
+#define BUSREC_MDINFRA_HIS_AXPORT_MASK			(0X7)	/*MT6295 NEW ADD*/
+#define BUSREC_MDINFRA_HIS_AXPORT_SHIFT			(18)		/*MT6295 NEW ADD*/
+
+#define BUSREC_MON_FORCE_BUSY_MASK				(0x1)	/*MT6295 NEW ADD:default value is 0*/
+#define BUSREC_MON_FORCE_BUSY_SHIFT				(0)		/*MT6295 NEW ADD*/
+#define BUSREC_MON_BUS_IDLE_MSK_MASK			           (0x1)	/*MT6295 NEW ADD:default value is 0*/
+#define BUSREC_MON_BUS_IDLE_MSK_SHIFT				(16)		/*MT6295 NEW ADD*/
+
+/********************************Register Offset Field ********************************/
+#define BUSREC_IP_CURR_CTRL_OFFSET                                         (0X30)
+#define BUSREC_IP_GRP_OFFSET                                                          (0X200)
+
+#define BUSREC_LOG_EN_MASK                                                            (0x1)
+#define BUSREC_LOG_EN_SHIFT                                                            (0)
+#define BUSREC_LOG_ACLK_CG_DIS_MASK                                      (0x1)
+#define BUSREC_LOG_ACLK_CG_DIS_SHIFT                                      (0)
+
+
+#endif /* end of __BUSMON_REG_H__ */
+
diff --git a/mcu/interface/driver/devdrv/busmon/md95/drv_busmon.h b/mcu/interface/driver/devdrv/busmon/md95/drv_busmon.h
new file mode 100644
index 0000000..eb77115
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmon/md95/drv_busmon.h
@@ -0,0 +1,1230 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   drv_busmon.h
+ *
+ * Project:
+ * --------
+ *   MOLY
+ *
+ * Description:
+ * ------------
+ *   Header file for Bus monitor control
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 01 21 2019 hedy.han
+ * [MOLY00380374] [Gen97][build error solving] MT6779_SP(LWCTG) on VMOLY.EVB.SEPT.DEV
+ * [VMOLY.EVB.SEPT.DEV][GEN95 BUSMON]merge 95busmon from UMOLYE branch.
+ *
+ * 08 06 2018 hedy.han
+ * [MOLY00344260] [Gen95 Busmon][LR13.R0.MP] Remove assert and backup address logger in dormant backup.
+ * [Gen95Busmon][LR13.R0.MP][Delete Assert] delete assert as customer's ask; backup address logger register.
+ *
+ * 04 26 2018 hedy.han
+ * [MOLY00322462] [UMOLYE][HISR] Remove some HISRs and move them to related LISRs
+ * [Busmon Hisr]Delete Busmon HISR.
+ *
+ * 03 29 2018 hedy.han
+ * [MOLY00316943] [New feature][Address logger] Add address logger enable and disable function.
+ * [New feature][Address logger] add address logger enable and disable function.
+ *
+ * 03 12 2018 hedy.han
+ * [MOLY00312512] [UMOLYE TRUNK][GEN95][BUSMON][New Feature][AT command]
+ *
+ * 07 04 2017 liang.yan
+ * [MOLY00244793] [MT6295M]Bus monitor driver build error call for check in
+ * 	.Patch busmon change to MT6295 MP2 branch
+ *
+ * 06 09 2017 liang.yan
+ * [MOLY00244888] [ZION]Bus monitor driver build error call for check in
+ * 	
+ * 	[LR12A.MP1.5.RDIT]Merge ZION project defining
+ *
+ * 06 06 2017 liang.yan
+ * [MOLY00248491] [MT6763][Gen93][System Service][MDCIRQ] Debugging code for GPT IRQ not entered issue
+ * 	[LR12A]Rollback the bus monitor configuration for MDCIRQ issue
+ *
+ * 05 15 2017 yen-chun.liu
+ * [MOLY00248491] [MT6763][Gen93][System Service][MDCIRQ] Debugging code for GPT IRQ not entered issue
+ * busmon debug code for MDCIRQ.
+ *
+ * 05 10 2017 liang.yan
+ * [MOLY00242841] [SE2 Internal CR][Bianco][N1] Kernel API Dump,0,0,99,/data/core/,1,,EMI MPU,Fri Apr 14 23:02:16 CST 2017 @ 2017-04-14 23:02:16.77644,1,2372648
+ * 	Remove busmon debug code for MPU violation in TRUNK
+ *
+ * 05 05 2017 liang.yan
+ * [MOLY00242841] [SE2 Internal CR][Bianco][N1] Kernel API Dump,0,0,99,/data/core/,1,,EMI MPU,Fri Apr 14 23:02:16 CST 2017 @ 2017-04-14 23:02:16.77644,1,2372648
+ * 	[TRUNK]Add MDINFRA busmon debug for mpu violation
+ *
+ * 05 03 2017 liang.yan
+ * [MOLY00242841] [SE2 Internal CR][Bianco][N1] Kernel API Dump,0,0,99,/data/core/,1,,EMI MPU,Fri Apr 14 23:02:16 CST 2017 @ 2017-04-14 23:02:16.77644,1,2372648
+ * 	[TRUNK]bus monitor mo debug for MPU violation
+ *
+ * 05 02 2017 liang.yan
+ * [MOLY00244750] [System Service][MDGDMA][MT6763] Update GDMA debug log for DDL fail.
+ * 	Change MDMCU/MDINFRA busmon parking layer to default point
+ *
+ * 04 25 2017 liang.yan
+ * [MOLY00245013] [BIANCO][MT6763][RDIT][PHONE][Overnight][HQ][MTBF][Lab][Ericsson]Externel (EE) [Others] MD long time no response
+ * 	[TRUNK]Change MDMCU busmon parking layer to MCU2EMI
+ *
+ * 04 14 2017 liang.yan
+ * [MOLY00241937] [VTF_SMT][MT6293][SMT][Bianco][MT6763]Externel (EE),0,0,99,/data/core/,1,modem,md1:(USIP0_USIP0),[ASSERT] file:md32/usip/common/service/loader/src/loader.c line:1086 when overnight cal(1/601times)
+ * 	[UMOLYA]Change mdinfra busmon parking layer after MI
+ *
+ * 03 30 2017 liang.yan
+ * [MOLY00238383] [Change Feature][BUSMON]Change MDMCU busmon parking to PWB
+ *
+ * 03 15 2017 liang.yan
+ * [MOLY00235447] [Change Feature][SS][BUSMON]Add busmon profiling API for user
+ *
+ * 03 02 2017 liang.yan
+ * [MOLY00232074] [Change Feature][BIANCO]Adding busmon monitor MO port Latency feature
+ *
+ * 02 13 2017 i-chun.liu
+ * [MOLY00228094] [Bianco][Bringup] DEV patch back
+ * merge back busmon MO port setting.
+ *
+ * 02 03 2017 i-chun.liu
+ * [MOLY00227643] [Bianco Bring-up][Gen93/INIT/BUSMON] Change MDMCU BUSMON to MO port at init stage.
+ * Change MDMCU BUSMON to MO port at init stage.
+ *
+ * 08 05 2016 liang.yan
+ * [MOLY00195782] [Change Feature]93 busmon driver update
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * workaround for CIRQ driver.
+ *
+ * 03 30 2016 i-chun.liu
+ * [MOLY00171939] 93 Busmon check in
+ * busmon check in .
+ *
+ * 10 07 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * Update bus monitor IRQ code for ELBRUS.
+ *
+ * 08 17 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * bus monitor update for ELBRUS.
+ *
+ * 06 09 2015 i-chun.liu
+ * [MOLY00119728] JADE bring up call for check in  (MDCIRQ and Bus monitor )
+ * JADE PCORE BUSMON.
+ *
+ * 04 07 2015 i-chun.liu
+ * [MOLY00106215] TK6291 bus monitor driver update
+ * pcore busmonitor driver update to prevent modis build fail.
+ *
+ * 04 07 2015 i-chun.liu
+ * [MOLY00106215] TK6291 bus monitor driver update
+ * Pcore bus monitor driver update.
+ *
+ * 07 29 2014 brian.chiang
+ * [MOLY00070757] busmon drvier update
+ * Bus monitor driver enhancement
+ *
+ * 04 23 2014 brian.chiang
+ * [MOLY00063514] 6595 busmon driver
+ * 6595 busmon deriver porting
+ *
+ * 02 21 2014 i-chun.liu
+ * [MOLY00057041] Solve MT6290 bus monitor driver API bug
+ * bus monitor bug
+ *
+ * 05 31 2013 vend_hsientang.lee
+ * [MOLY00024631] Update busmon driver
+ * Use non-post-write to get accurate counter
+ *
+ * 03 29 2013 vend_hsientang.lee
+ * [MOLY00013013] Add Busmon driver
+ *
+ ****************************************************************************/
+
+#ifndef __DRV_BUSMON_H__
+#define __DRV_BUSMON_H__
+
+#if defined(__ASSEMBLER__)
+
+.macro BUSMON_PRE_CONFIG
+.set push
+.set nomips16
+//this is used in Gen93, no need in Gen95
+.set pop
+.endm BUSMON_PRE_CONFIG
+#else
+
+#include "kal_public_defs.h"
+#include "irqid.h"
+#include "busmon_reg.h"
+
+/*******************************************************************************
+ * MACRO DEFINE
+ *******************************************************************************/
+#define AXIID_IA_ID_MASK_ALL             	0xFFFF
+#define AXIID_IA_ID_MASK_NONE             0x0000
+#define AXI_VPE_ID_MASK_ALL    		0x7F
+#define AXI_VPE_ID_MASK_NONE   		0x0
+#define AXI_ULTRA_MASK_ALL     		0x3
+#define AXI_ULTRA_MASK_NONE    		0x0
+#define AXI_MDINFRA_VPE_MASK		0x2 /*MT6295 NEW CHANGE: this bit for MDINFRA BUSMON VPE MASK, there is no need VPE signal in MDINFRA */ 
+#define MO_LATENCY_RECORD_NUM     	20
+#define AXIMON_TOTAL_AT_CONFIG        0x20
+#define AXIMON_TOTAL_IP                           0x4
+
+/*
+*  Define 15us which is the max latency time from mcu to apb read access
+*  bus clk is 208MHz in MT6295T MDMCU, so the limit bus cycle count is 0xC30
+*  bus clk is 100MHz in MT6295T MDINFRA, so the limit bus cycle count is 0x5DC
+*/
+#define MCU2REG_LIMITED_LATENCY_CNT_MDMCU 	0xC30
+#define MCU2REG_LIMITED_LATENCY_CNT_MDINFRA	0x5DC	
+
+/* Register field manipulation macro */
+#define EXTRACT_REG_FIELD_VAL(field_val, field_name)            (((field_val) >> (field_name##_SHIFT)) & (field_name##_MASK))
+#define EXPAND_REG_FIELD_VAL(field_val, field_name)             (((field_val) & (field_name##_MASK)) << (field_name##_SHIFT))
+#define CLEAR_REG_FIELD(reg_val, field_name)                            ((reg_val) & (~((field_name##_MASK) << (field_name##_SHIFT))))
+#define SET_REG_FIELD_VAL(reg_val, field_val, field_name)       (CLEAR_REG_FIELD(reg_val, field_name) | EXPAND_REG_FIELD_VAL(field_val, field_name))
+
+/*******************************************************************************
+ *Below for bus monitor
+ *******************************************************************************/
+typedef enum {
+    MDMCUSYS_BUSMON_IRQID = MD_IRQID_MDMCU_BUSMON_MATCH_STS,
+    MDPERISYS_BUSMON_IRQID = MD_IRQID_MDINFRA_BUSMON_MATCH_STS,
+    MD_BUSMON_IRQID_NUM = 2
+ } drv_busmon_irqid_t;
+
+typedef enum {
+    MONID_MDMCU_AXIMON = 0, 
+    MONID_MDINFRA_AXIMON,    
+    MONID_MDAXI_MAX
+} drv_aximon_monid_t;
+
+/* Busmon layer select id */
+typedef enum {
+    /* MONID_MDMCU_AXIMON */
+    BUSMON_BUSID_MDMCUSYS_START = 0UL,   
+    BUSMON_BUSID_MDMCU_EMI = BUSMON_BUSID_MDMCUSYS_START,   
+    BUSMON_BUSID_IA_MM = 1,
+    BUSMON_BUSID_IA_MO = 2,
+    BUSMON_BUSID_uSIP_APB = 3,
+    BUSMON_BUSID_IA_MO_PWB = 4,  /* default */ 
+    BUSMON_BUSID_MO_uSIP_DEBUG = 5,
+    BUSMON_BUSID_uSIP_EMI =  6,
+    BUSMON_BUSID_MDMCUSYS_END = 7,   
+    /*MONID_MDINFRA_AXIMON */
+    BUSMON_BUSID_MDINFRA_START = 0,   			
+    BUSMON_BUSID_MDINFRA_EMI = BUSMON_BUSID_MDINFRA_START, /* default */ 
+    BUSMON_BUSID_MDINFRA_IOCU = 1,
+    BUSMON_BUSID_MDINFRA_END = 2
+} busmon_busid_t;  
+
+typedef enum {
+    BUSMON_MON_DISABLE = 0,
+    BUSMON_MON_ENABLE
+} drv_busmon_active_t;
+
+typedef enum {
+    BUSMON_MON_STATE_INACTIVE = 0,
+    BUSMON_MON_STATE_ACTIVE
+} drv_busmon_mon_state_t;
+
+typedef enum {
+    BUSMON_IP0 = 0,
+    BUSMON_IP1,
+    BUSMON_IP_MAX
+} drv_busmon_ip_t;
+
+typedef enum {
+    IP_IDLE = 0,
+    IP_REAL_ENABLE,
+    IP_STOP
+} busmon_ip_status_t;
+
+typedef enum {
+    AXIMON_RWSEL_WRITE = 0,
+    AXIMON_RWSEL_READ,
+    AXIMON_RWSEL_MAX
+} drv_aximon_rwsel_t;
+
+typedef enum {
+    START_ORDER_IP0_IP1= 0,
+    STOP_ORDER_IP0_IP1,
+    ORDER_IP0_IP1_MAX  
+} drv_busmon_mon_seq_check_mode_t;
+
+typedef enum {
+    BUSMON_TG_MON_MODE_SNAP = 0,
+    BUSMON_TG_MON_MODE_MONITOR,
+    BUSMON_TG_MON_MODE_MAX
+} drv_busmon_tg_mon_mode_t;
+
+/* Busmon Trigger Mode */
+typedef enum {
+    BUSMON_TRG_ADDRDATA,               
+    BUSMON_TRG_CYCLE,                    
+    BUSMON_TRG_MAX
+} drv_busmon_trg_mode_t;
+
+typedef enum {
+    MON_VPE_0 = 0x01,
+    MON_VPE_1 = 0x05,
+    MON_VPE_2 = 0x11,
+    MON_VPE_3 = 0x15,   
+    MON_VPE_4 = 0x21,   
+    MON_VPE_5 = 0x25,   
+    MON_SFU      = 0x2,
+    MON_SPU      = 0x3,
+} busmon_vpe_id_t;
+
+typedef enum {
+    MONITOR_START = 0,
+    MCR0 = 0,
+    MCR1 = 1,
+    MCW0 = 2,
+    MCW1 = 3,
+    MIR0 = 4,
+    MIR1 = 5,
+    MIW0 = 6,
+    MIW1 = 7,
+    MONITOR_END = 7,
+
+    LATENCY_START = 16,
+    LCR0G = 16,
+    LCR1G = 17,
+    LCW0G = 18,
+    LCW1G= 19,
+    LCR0S = 20,
+    LCR1S = 21,
+    LCW0S = 22,
+    LCW1S = 23,
+    LIR0G = 24,
+    LIR1G = 25,
+    LIW0G = 26,
+    LIW1G= 27,
+    LIR0S = 28,
+    LIR1S = 29,
+    LIW0S = 30,
+    LIW1S = 31,
+    LATENCY_END = 31,
+
+    ADDR_START = 48,
+    ACR0G = 48,
+    ACR1G = 49,
+    ACW0G = 50,
+    ACW1G= 51,
+    ACR0S = 52,
+    ACR1S = 53,
+    ACW0S = 54,
+    ACW1S = 55,
+    AIR0G = 56,
+    AIR1G = 57,
+    AIW0G = 58,
+    AIW1G= 59,
+    AIR0S = 60,
+    AIR1S = 61,
+    AIW0S = 62,
+    AIW1S = 63,
+    ADDR_END = 63,
+
+    STARTC = 100,
+    STOPC = 101,
+    STARTI = 102,
+    STOPI = 103,
+
+    ENADDRLOG = 200,
+    DISADDRLOG = 201,
+
+} busmon_at_config_t;
+
+/*
+ * Busmon target selection - master id
+ * For AXI, master id is to select transaction ID
+ * Here only list MDMCU layer0,1,2 master id, we don't care master id from uSIP(layer3)
+ */
+typedef enum {
+   /*MDMCU master id*/
+    BUSMON_TGID_IA_MM_NONCACHE_RW_CORE0_VPE0=16,   			//0x10  MM port layer1 (BUSMON_BUSID_IA_MM)
+    BUSMON_TGID_IA_MM_NONCACHE_RW_CORE1_VPE0=17,   			//0x11  MM port layer1
+    BUSMON_TGID_IA_MM_NONCACHE_RW_IOCU		=20,         			//0x14  MM port layer1
+    BUSMON_TGID_IA_MM_NONCACHE_RW_CORE0_VPE1=24,   			//0x18  MM port layer1
+    BUSMON_TGID_IA_MM_NONCACHE_RW_CORE1_VPE1=25,   			//0x19  MM port layer1
+
+    BUSMON_TGID_IA_MM_CACHE_W=7,                   						//0x7  MM port layer1 outstanding capability is 8, master id always 7
+    BUSMON_TGID_IA_MM_CACHE_R	=0,                   				        // Note: may be 0x0~0x6, 0x8~0xF, outstanding capability is 16
+
+    BUSMON_TGID_IA_MO_NONBUF_RW_CORE0=0,           		                    //0x0 MO port layer2 (BUSMON_BUSID_IA_MO)
+    BUSMON_TGID_IA_MO_NONBUF_RW_CORE1=1,           					//0x1 MO port layer2
+
+    BUSMON_TGID_IA_MO_BUF_W=15,                    						//0xF MO port layer2 outstanding capability is 8, master id always 15
+
+    BUSMON_TGID_IA_MM_NONCACHE_RW_CORE0_VPE0_EMI=40,   		//0b1000000  MM port layer0 (BUSMON_BUSID_MDMCU_EMI) (MM->EMI )
+    BUSMON_TGID_IA_MM_NONCACHE_RW_CORE1_VPE0_EMI=44,   		//0b1000100  MM port layer0 (MM->EMI )
+    BUSMON_TGID_IA_MM_NONCACHE_RW_IOCU_EMI		=50,         		//0b1010000  MM port layer0 (MM->EMI )
+    BUSMON_TGID_IA_MM_NONCACHE_RW_CORE0_VPE1_EMI=60,  	 	//0b1100000  MM port layer0 (MM->EMI )
+    BUSMON_TGID_IA_MM_NONCACHE_RW_CORE1_VPE1_EMI=64,  	 	//0b1100100  MM port layer0 (MM->EMI )
+
+    BUSMON_TGID_IA_MM_CACHE_W_EMI=28,                  					//0b11100  MM port layer0 (MM->EMI )
+    BUSMON_TGID_IA_MM_CACHE_R_EMI	=0,                   					// Note: may be 0x0~0x6, 0x8~0xF(need append 2'b00 at the LSB of the original id)
+                                                                       
+    BUSMON_TGID_IA_MM_NONCACHE_RW_CORE0_VPE0_MML2_EMI=41,   	//0b1000001  MM port layer0 (BUSMON_BUSID_MDMCU_EMI) (MM->MML2_MMU->EMI )
+    BUSMON_TGID_IA_MM_NONCACHE_RW_CORE1_VPE0_MML2_EMI=45,   	//0b1000101  MM port layer0 (MM->MML2_MMU->EMI )
+    BUSMON_TGID_IA_MM_NONCACHE_RW_IOCU_MML2_EM		     =51,      //0b1010001  MM port layer0 (MM->MML2_MMU->EMI )
+    BUSMON_TGID_IA_MM_NONCACHE_RW_CORE0_VPE1_MML2_EMI=61,   	//0b1100001  MM port layer0 (MM->MML2_MMU->EMI )
+    BUSMON_TGID_IA_MM_NONCACHE_RW_CORE1_VPE1_MML2_EMI=65,   	//0b1100101  MM port layer0 (MM->MML2_MMU->EMI )
+
+    BUSMON_TGID_IA_MM_CACHE_W_MML2_EMI	=29,                  			//0b11101  MM port layer0 (MM->MML2_MMU->EMI )
+    BUSMON_TGID_IA_MM_CACHE_R_MML2_EMI	=1,                   			// Note: may be 0x0~0x6, 0x8~0xF(need append 2'b01 at the LSB of the original id)
+
+    /*MDINFRA master id*/
+    BUSMON_TGID_INFRA_ABM_EMI  = 0,                  						//12'0b0000_00xx_0000  MDINFRA layer0 (BUSMON_BUSID_MDINFRA_EMI, master -> emi)
+    BUSMON_TGID_INFRA_PPPHA_EMI = 1,               						//12'0b0000_000x_0001  MDINFRA layer0
+    BUSMON_TGID_INFRA_LOGTOPMCU_EMI = 2,            					//12'0b0000_000x_0010  MDINFRA layer0
+    BUSMON_TGID_INFRA_LOGTOPDSP_EMI = 3,            					//12'0b0000_000x_0011  MDINFRA layer0
+    BUSMON_TGID_INFRA_TRACETOP_EMI = 4,             						//12'0b0000_000x_0100  MDINFRA layer0
+    BUSMON_TGID_INFRA_IPSEC_EMI = 5,                						//12'0b0000_000x_0101  MDINFRA layer0
+    BUSMON_TGID_INFRA_DBGSYS_EMI = 23,              						//12'0b0000_0xx1_0111  MDINFRA layer0
+    BUSMON_TGID_INFRA_GDMA_EMI = 0x6,                 						//12'0b000x_xxx0_0111  MDINFRA layer0
+    BUSMON_TGID_INFRA_FE_MAS_EMI = 8,               						//12'0b00xx_xxxx_1000  MDINFRA layer0
+    BUSMON_TGID_INFRA_BIGRAM_MAS_EMI = 1024,        				//12'0b0100_0000_0xxx  MDINFRA layer0
+    BUSMON_TGID_INFRA_BRP_MAS_EM = 2048,           					//12'0b1000_000x_xxxx  MDINFRA layer0
+    BUSMON_TGID_INFRA_MML2_MAS_EMI = 3072,          					//12'0b1100_0000_0xxx  MDINFRA layer0
+
+    BUSMON_TGID_INFRA_AP2MD = 0,                    						//10'0b00_0000_x000  MDINFRA layer1 (BUSMON_BUSID_MDINFRA_IOCU, master -> mdmcu bus)
+    BUSMON_TGID_INFRA_BIGRAM_MAS = 17,		         					//10'0b00_xxx1_0001   MDINFRA layer1
+    BUSMON_TGID_INFRA_BRP_MAS = 9,			         					//10'0bxx_xxx0_x1001  MDINFRA layer1
+    BUSMON_TGID_INFRA_MML2_MAS = 1, 		         					//10'0b00_xxx0_0001   MDINFRA layer1
+    BUSMON_TGID_INFRA_FE_MAS = 2,                  						//10'0b0x_xxxx_x010    MDINFRA layer1
+    BUSMON_TGID_INFRA_DBGSYS = 11,                  						//10'0b00_00xx_1011   MDINFRA layer1
+    BUSMON_TGID_INFRA_GDMA = 3,                     						//10'0b00_xxxx_0011   MDINFRA layer1
+    BUSMON_TGID_INFRA_IPSEC = 5,                    							//10'0b00_0000_x101  MDINFRA layer1
+    BUSMON_TGID_INFRA_END = 0xFFFFFFF0,
+}busmon_tg_id_t;
+
+
+/*************************************************************************************************
+* Below is for Bus recorder 
+*************************************************************************************************/
+typedef enum {
+    BUSREC_MODE_NORMAL = 0,
+    BUSREC_MODE_TEST,
+} BUSREC_MODE;
+
+typedef enum {
+    BUSREC_GATE_NONE = 0,
+    BUSREC_GATE_RESP,
+    BUSREC_GATE_CMD,
+    BUSREC_GATE_ALL,
+} BUSREC_GATE;
+
+typedef enum {
+    BUSREC_HIS_FILTER_EN_DISABLE= 0,             /* MT6295M NEW ADD:disable bus recorder history filter */
+    BUSREC_HIS_FILTER_EN_ENABLE,                    /* MT6295M NEW ADD: enable bus recorder history filter */
+} BUSREC_HIS_FILTER_EN;                             /* MT6295M NEW ADD */
+
+typedef enum {
+    BUSREC_HIS_REC_EN_DISABLE= 0,                   /* MT6295M NEW ADD:disable bus recorder history recorder */
+    BUSREC_HIS_REC_EN_ENABLE,                          /* MT6295M NEW ADD: enable bus recorder history recorder */
+} BUSREC_HIS_REC_EN;                                    /* MT6295M NEW ADD */
+
+typedef enum {
+    BUSREC_MON_FORCE_BUSY_DISABLE = 0,  /* MT6295M NEW ADD:disable bus monitor force busy -bus monitor output nomal signal to bus */
+    BUSREC_MON_FORCE_BUSY_ENABLE,          /* MT6295M NEW ADD: enable bus monitor force busy - bus monitor output busy signal to bus */
+} BUSREC_FORCE_BUSY;                                /* MT6295M NEW ADD */
+
+typedef enum {
+    BUSREC_MON_BUS_IDLE_MSK_DISABLE = 0,    /* MT6295M NEW ADD: do not mask bus idle signal */
+    BUSREC_MON_BUS_IDLE_MSK_ENABLE,            /* MT6295M NEW ADD: mask bus idle signal */
+} BUSREC_BUS_IDLE_MSK;                                  /* MT6295M NEW ADD */
+
+
+/*******************************************************************************
+ * Define data structures.
+ *******************************************************************************/
+typedef struct {
+    BUSREC_HIS_FILTER_EN mon_his_filter_en;	    /* MT6295M NEW ADD:enable/disable history filter */		
+    kal_uint32 his_rec_entry_sel;			    /* MT6295M NEW ADD: history command entry select (8 history entry for each IP) */
+    kal_uint32 rec_entry_sel;                                        /* MT6295M NEW ADD: current command entry select (32 current entry for each IP)*/
+    } drv_busrec_rec_obsrv_ip_ctrl;                /* MT6295M NEW ADD */
+
+typedef struct {
+    BUSREC_FORCE_BUSY mon_force_busy;            /* MT6295M NEW ADD: enable/disable force busmon busy */
+    BUSREC_BUS_IDLE_MSK mon_bus_idle_msk;  /* MT6295M NEW ADD: enable/disable bus idle mask */		
+} drv_busrec_idle_ctrl;	
+
+/* AXImon IP configuration of Monitor mode */
+typedef struct {
+    kal_bool cnt_wrap_en_t;				/* MT6295M NEW ADD */
+    drv_aximon_rwsel_t rwsel;
+    kal_bool all_master_enable;				/* any transaction ID */
+    kal_bool   data_enable;					/* data target check at counting snap count */    	
+    busmon_tg_id_t master_id;				/* specific transaction ID */
+    kal_uint32 master_id_mask;
+    kal_uint32 vpe_id;						/* specific VPE ID */
+    kal_uint32 vpe_id_mask;  
+    kal_uint32 ultra;						/* specific ULTRA */
+    kal_uint32 ultra_mask;    
+    kal_uint32 addr;                       				/* address: only used in snap mode */
+    kal_uint32 addr_mask;          				/* address mask, 0: check, 1: ignore. only used in snap mode */
+    kal_uint32 data;                       				/* data 0 32-bit of bus width. only used in snap mode */
+    kal_uint32 data_mask;          				/* data 0 mask 0: check, 1: ignore. only used in snap mode */  	
+} drv_aximon_mon_config_t;
+
+/* Configuration of Snap Mode */
+typedef struct {
+    kal_bool cnt_wrap_en_t;                      	/* MT6295M NEW ADD: enable/disable performance counter wrap around. KAL_TRUE - performance counter warp around. KAL_FALSE - performance counter no wrap around*/
+    drv_aximon_rwsel_t rwsel;	
+    drv_busmon_trg_mode_t trg_mode;	/* trigger mode */
+    kal_bool all_master_enable;                	/* ALL Master should only use in Monitor mode */
+    kal_bool   data_enable;                          	/* data target check at counting snap count */  
+    kal_uint32 mon_cnt;                               	/* count select */ 	
+    kal_uint32 cycle_cnt;                              	/* max cycle, only use in cycle trigger mode*/   	
+    busmon_tg_id_t master_id;                 	/* specific transaction ID */
+    kal_uint32 master_id_mask;
+    kal_uint32 vpe_id;                                  	/* specific VPE ID */
+    kal_uint32 vpe_id_mask;   
+    kal_uint32 ultra;                                     	/* specific ULTRA */ 
+    kal_uint32 ultra_mask;  	
+    kal_uint32 addr;                                      	/* address */
+    kal_uint32 addr_mask;                         	/* address mask, 0: check, 1: ignore */
+    kal_uint32 data;                                     	/* data 0 32-bit of bus width */
+    kal_uint32 data_mask;                        	/* data 0 mask 0: check, 1: ignore */
+} drv_aximon_snp_config_t;
+
+/* Configuration of Snap Mode */
+typedef struct {
+    kal_bool enable_seq_trg;       						/* TRUE==> sequencial mode, FALSE==> Concurrent mode */
+    drv_busmon_mon_seq_check_mode_t seq_check_mode; 	/* START_ORDER_IP0_IP1/STOP_ORDER_IP0_IP1 */   
+    drv_aximon_snp_config_t ip[BUSMON_IP_MAX];
+} drv_aximon_trg_config_t;
+
+/* Monitor Mode: Read-related information */
+typedef struct {
+    kal_uint32 QID;
+    kal_uint32 tot_bus_cyc;          		/* total bus cycle */
+    kal_uint32 non_ov_trans_num;     		/* total transaction number */
+    kal_uint32 ov_trans_num;
+    kal_uint32 non_wgt_trans_cyc;    		/* total transaction cycle */
+    kal_uint32 wgt_trans_cyc;
+    kal_uint32 max_trans_cyc;        		/* max transaction cycle */
+    kal_uint32 max_ost_trans_num;
+    kal_uint32 cur_ost_trans_num;		/* MT6295M NEW ADD: current outstanding transaction number */ 
+    kal_uint32 bus_util;             			/* bus utilization */
+    kal_uint32 avg_data_rate;        		/* average data rate ,not used in Elbrus*/
+    kal_uint32 avg_xac_cyc;          		/* average transaction cycle */
+} drv_aximon_mon_transaction_info_t;
+
+/* Snap Mode :Read-related informatin */
+typedef struct {
+    kal_uint32 info0;                                          /* current AXI bus signal (burst, lock, cache, size...), VPE */
+    kal_uint32 info1;                                          /* current target id (QID),target match count */
+    kal_uint32 info2;                                          /* snap target address */
+    kal_uint32 info3;                                          /* data0&data1 strobe */
+    kal_uint32 info4;                                          /* last data[31:0] */
+    kal_uint32 info5;                                          /* last data[63:32] */
+    kal_uint32 info6;                                          /* last data[95:64] */
+    kal_uint32 info7;                                          /* last data[127:96] */
+    kal_uint32 info8;                                          /* last second data[31:0] */
+    kal_uint32 info9;                                          /* last second data[63:32] */
+    kal_uint32 info10;                                       /* last second data[95:64] */
+    kal_uint32 info11;                                      /* last second data[127:96] */
+} drv_aximon_snp_info_t;
+
+/* Sequential Mode */
+typedef struct {
+   drv_aximon_snp_info_t ip[BUSMON_IP_MAX];
+} drv_aximon_trg_info_t;
+
+typedef struct{
+    kal_uint32 curr_id;                     /* current transaction id */
+    kal_uint32 curr_addr;               /* current transaction addr */
+    kal_uint32 curr_vpe;                /* current transaction vpe */
+    kal_uint32 curr_ctrl;                 /* current transaction ctrl */
+    kal_uint32 his_id;                      /* history transaction id */
+    kal_uint32 his_cmd;                 /* history transaction cmd */
+    kal_uint32 his_addr;                /* history transaction addr */
+}drv_aximon_rec_hiscur_info;
+
+typedef struct{
+    kal_uint32 buff_cnt;
+    kal_uint32 grp_cmd;
+    kal_uint32 grp_addr[32];
+    kal_uint32 grp_id[32];
+}drv_aximon_rec_grp_info;
+
+typedef void (*busmon_intr_cb)(void);
+
+typedef struct {
+    kal_uint32 mo_index;
+    kal_uint32 mo_frc_count[MO_LATENCY_RECORD_NUM];
+    kal_uint32 mo_latency[MO_LATENCY_RECORD_NUM];
+    kal_uint32 mo_address[MO_LATENCY_RECORD_NUM];
+    kal_uint32 mo_vpe_id[MO_LATENCY_RECORD_NUM];      	/*snap_info0 bit[2:0]*/
+    kal_uint32 mo_master_id[MO_LATENCY_RECORD_NUM];   	/*snap_info1 bit[15:0]*/
+} aximon_mo_latency_info_t;
+
+typedef struct {
+    kal_bool IP_enable[BUSMON_IP_MAX];  /* IP0 and IP1 enable or not when BUS recorder testing */
+    drv_aximon_rwsel_t rwsel[BUSMON_IP_MAX];    /* Note: In IPx_AXIMON_TG, BUS Recorder only take care RWSEL & IPx_MON_ENABLE */
+} UT_BUSREC_IP_CFG;
+
+/*this struct is used to record the at comand that user input.*/
+typedef struct{
+    busmon_at_config_t at_config_g;
+    busmon_busid_t at_bus_id_g;
+    kal_uint32 at_addr_g;
+    kal_uint32 at_addr_msk_g;
+    kal_uint32 at_master_g; 
+    kal_uint32 at_master_msk_g;
+    kal_uint32 at_vpe_g;
+    kal_uint32 at_vpe_msk_g;
+    kal_uint32 at_ultra_g;
+    kal_uint32 at_ultra_msk_g;
+    kal_uint32 at_data_latcy_g;
+    kal_uint32 at_data_msk_g;
+}drv_aximon_at_config;
+
+/*this struct is used to record registers value before entering dormant*/
+typedef struct{
+    kal_uint32 aximon_ctl_r;
+    kal_uint32 aximon_tst_r;
+    kal_uint32 aximon_intmsk_r;
+    kal_uint32 aximon_ip0_tg_r;
+    kal_uint32 aximon_ip0_tmr_r;
+    kal_uint32 aximon_ip0_id_r;
+    kal_uint32 aximon_ip0_vpe_r;
+    kal_uint32 aximon_ip0_addr_r;
+    kal_uint32 aximon_ip0_addrmsk_r;
+    kal_uint32 aximon_ip0_data_r;
+    kal_uint32 aximon_ip0_datamsk_r;
+    kal_uint32 aximon_ip1_tg_r;
+    kal_uint32 aximon_ip1_tmr_r;
+    kal_uint32 aximon_ip1_id_r;
+    kal_uint32 aximon_ip1_vpe_r;
+    kal_uint32 aximon_ip1_addr_r;
+    kal_uint32 aximon_ip1_addrmsk_r;
+    kal_uint32 aximon_ip1_data_r;
+    kal_uint32 aximon_ip1_datamsk_r;
+    kal_uint32 busrec_obsrv_ctrl_r;
+    kal_uint32 busrec_reg_log_ctr_r;
+    kal_uint32 busrec_reg_log_cg_dis_r;
+}drv_aximon_dormant_backup;
+	
+/* ************************************************************************************************
+* 
+* AXIMon External Fucntion Declearation
+*
+**************************************************************************************************/
+void drv_busmon_lisr(drv_busmon_irqid_t busmon_irq_id);
+
+/*************************************************************************
+ * DESCRIPTION
+ *	Bus monitor register lisr & callback function in trigger mode.
+ *
+ * PARAMETERS
+ *	 callback,busmon_irq_id
+ *
+ * RETURNS
+ *
+ * NOTE
+ *************************************************************************/
+void drv_busmon_set_trg_cb(busmon_intr_cb callback, drv_busmon_irqid_t busmon_irq_id);
+
+ /*************************************************************************
+* DESCRIPTION
+*   Get BusMon base address
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*    base address
+*************************************************************************/
+kal_uint32 aximon_read_base_addr(drv_aximon_monid_t axi_mon_id);
+
+ /*************************************************************************
+* DESCRIPTION
+*   Config busmon layer.
+*
+* PARAMETERS
+*   axi_mon_id, bus_id
+*
+* RETURNS
+*     1     config success;
+*   -1     wrong bus monitor id;
+*   -2     select MDMCU busmon, wrong bus layer id in MDMCU busmon;
+*   -3     select MDINFRA busmon, wrong bus layer id in MDINFRA busmon;
+*   -4     bus monitor is started;
+*   -5     config layer is not equal with the value in AXIMON_TST register.
+*************************************************************************/
+kal_int32  aximon_set_busid(drv_aximon_monid_t axi_mon_id, busmon_busid_t bus_id);
+
+
+/*************************************************************************
+* DESCRIPTION
+*   Enable/Disable Speed Sim
+*
+* PARAMETERS
+*   axi_mon_id, enabled
+*
+* RETURNS
+*   NONE
+*************************************************************************/
+void aximon_set_speedsim(drv_aximon_monid_t axi_mon_id, kal_bool enabled);
+
+ /*************************************************************************
+* DESCRIPTION
+*   Whether clear some flag and registers when bus is idle.
+*	enabled = KAL_FALSE: not clear
+*	enabled = KAL_TRUE:  clear
+*
+* PARAMETERS
+*   axi_mon_id, enabled
+*
+* RETURNS
+*   NONE
+*************************************************************************/
+void aximon_set_clear_at_bus_idle(drv_aximon_monid_t axi_mon_id, kal_bool enabled);
+
+  /*************************************************************************
+ * DESCRIPTION
+ *  wait IP real enable
+ *
+ * PARAMETERS
+ *   axi_mon_id, mon_ip
+ *
+ * RETURNS
+ *   NONE
+ *************************************************************************/
+ void aximon_polling_IP_Real_Enable(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip);
+
+   /*************************************************************************
+ * DESCRIPTION
+ *	 disable = KAL_FALSE: enable clock gated, bus monitor can power down.
+ *	 disable = KAL_TURE: disable clock gated, bus monitor will not power down, this function maily for debug.
+ *
+ * PARAMETERS
+ *	 axi_mon_id, disable
+ *
+ * RETURNS
+ *
+ *
+ * NOTE
+ *   MT6295M NEW FEATURE
+ *************************************************************************/
+ void aximon_set_disable_cg(drv_aximon_monid_t axi_mon_id, kal_bool disable);
+
+    /*************************************************************************
+* DESCRIPTION
+*   enable/disable bus monitor cycle count wrap.
+*   enabled = KAL_TRUE: enable bus monitor cycle count wrap.
+*   enabled = KAL_FALSE:  disable bus monitor cycle count wrap.
+*
+* PARAMETERS
+*   axi_mon_id, enabled
+*
+* RETURNS
+*   NONE
+*
+* NOTE
+*   MT6295M NEW FEATURE
+*************************************************************************/
+void aximon_set_cyc_cnt_wrap_en(drv_aximon_monid_t axi_mon_id, kal_bool enabled);
+
+/*************************************************************************
+* DESCRIPTION
+*   enable/disable bus recorder history record.
+*   enabled = KAL_FALSE: disable bus recorder history record;
+*   enabled = KAL_TRUE:   enable bus recorder history record;
+*
+* PARAMETERS
+*   axi_mon_id, enabled
+*
+* RETURNS
+*   NONE
+*
+* NOTE
+*   MT6295M NEW FEATURE
+*************************************************************************/
+void aximon_set_mon_his_rec_en(drv_aximon_monid_t axi_mon_id, kal_bool enabled);
+
+/*************************************************************************
+* DESCRIPTION
+*    set bus recorder abservation register
+*	obsrv_ip_ctrl->mon_his_filter_en = KAL_FALSE, bus recorder no need condition match when record history transaction command
+*	obsrv_ip_ctrl->mon_his_filter_en = KAL_TRUE , bus recorder need condition match when record history transaction command
+*    obsrv_ip_ctrl->his_rec_entry_sel (0-7), select history transaction command entry to observe
+*    obsrv_ip_ctrl->rec_entry_sel (0-31), select current transaction command entry to observe
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip, obsrv_ip_ctrl
+*
+* RETURNS
+*   NONE
+*
+* NOTE
+*   MT6295M NEW FEATURE
+*************************************************************************/
+void aximon_set_mon_obsrv_entry(drv_aximon_monid_t axi_mon_id,  drv_busmon_ip_t mon_ip, 
+drv_busrec_rec_obsrv_ip_ctrl *obsrv_ip_ctrl);
+
+/*************************************************************************
+* DESCRIPTION
+*  config the busmon&bus idle signal
+*
+* PARAMETERS
+*   axi_mon_id;busrec_idle_ctrl;
+*
+* RETURNS
+*	MT6295M NEW ADD
+*************************************************************************/
+void  aximon_set_idle_ctrl (drv_aximon_monid_t axi_mon_id, drv_busrec_idle_ctrl* busrec_idle_ctrl);
+
+/*************************************************************************
+* DESCRIPTION
+*  Configure parameters used in Monitor Mode
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip, config
+*
+* RETURNS
+*   1  if the configuration applied
+*************************************************************************/
+kal_int32 aximon_set_monitor(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip, drv_aximon_mon_config_t *config);
+
+/*************************************************************************
+* DESCRIPTION
+*  Configure parametes used in Snapshot Mode
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip, config
+*
+* RETURNS
+*   1  if the configuration applied
+*************************************************************************/
+kal_int32 aximon_set_snap(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip, drv_aximon_snp_config_t *config);
+
+/*************************************************************************
+* DESCRIPTION
+*  Configure parameters in Sequential Trigger Mode
+*
+* PARAMETERS
+*   axi_mon_id, config
+*
+* RETURNS
+*   1   if the configuration applied
+*************************************************************************/
+kal_int32 aximon_set_sq_trg(drv_aximon_monid_t axi_mon_id, drv_aximon_trg_config_t *config);
+
+/*************************************************************************
+ * DESCRIPTION
+ *	Start bus monitor
+ *
+ * PARAMETERS
+ *	 axi_mon_id
+ *
+ * RETURNS
+ *
+ * NOTE
+ *	 BusMon clears the counts first.
+ *	 BusMon always waits for the on-going transaction finished
+ *	 before starting to update the counts.
+ *************************************************************************/
+ void aximon_start(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Stop bus monitor
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*
+* NOTE
+*   BusMon always waits for the on-going transaction finished
+*   before stopping to update the counts.
+*   Some counts stop to update once stopped received Some counts
+*   continues to update until all transactions fishished.
+*************************************************************************/
+void aximon_stop(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Enable interrupt
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*************************************************************************/
+void aximon_enable_interrupt(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Disable interrupt
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*************************************************************************/
+void aximon_disable_interrupt(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Clear interrupt
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*************************************************************************/
+void aximon_clear_interrupt(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Read-related Information in Monitor Mode
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip, info
+*
+* RETURNS
+*************************************************************************/
+void aximon_get_ip_transaction_info(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip, 
+drv_aximon_mon_transaction_info_t *info);
+
+/*************************************************************************
+* DESCRIPTION
+*  Get triggered information in Snapshot Mode
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip, info
+*
+* RETURNS
+*************************************************************************/
+void aximon_get_snap_info(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip, 
+drv_aximon_snp_info_t *info);
+
+/*************************************************************************
+* DESCRIPTION
+*  Get information in Triggered Mode
+*
+* PARAMETERS
+*   axi_mon_id, info
+*
+* RETURNS
+*************************************************************************/
+void aximon_get_trigger_info(drv_aximon_monid_t axi_mon_id, drv_aximon_trg_info_t *info);
+
+/*************************************************************************
+* DESCRIPTION
+*  Polling the triggered status
+*
+* PARAMETERS
+*   axi_mon_id, max_count, ip0_state, ip1_state
+*
+* RETURNS
+*	KAL_TRUE  if the interrupt triggered
+*	KAL_FALSE if no  interrupt triggered
+*************************************************************************/
+kal_bool  aximon_poll_trigged(drv_aximon_monid_t axi_mon_id, kal_uint32 max_count, 
+drv_busmon_mon_state_t *ip0_state, drv_busmon_mon_state_t *ip1_state);
+
+/*************************************************************************
+* DESCRIPTION
+*  disable IP0 and IP1.
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*************************************************************************/
+void aximon_disable_both_ip(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Confirm the AXI Monitor is enable or not
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*************************************************************************/
+kal_bool  drv_busmon_is_started(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDINFRA busmon interrupt occurs in log mode. 
+*   After MDINFRA busmon interrupt occurs in log mode, just record the registers information and clear interrupt.
+*   The define as follows
+*      AXIMON_IP0_SNAP_INFO2: the address of target transaction in IP0;
+*      AXIMON_IP0_MAX_TRANS_CYC: tha max transaction cycle in IP0;
+*      AXIMON_IP0_SNAP_INFO0: transaction information in IP0;
+*      AXIMON_IP0_SNAP_INFO1: master id of target transaction in IP0.
+*
+*************************************************************************/
+void mdinfra_busmon_record(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDMCU busmon interrupt occurs in log mode. 
+*   After MDMCU busmon interrupt occurs in log mode, just record the registers information and clear interrupt.
+*   The define as follows
+*      AXIMON_IP0_SNAP_INFO2: the address of target transaction in IP0;
+*      AXIMON_IP0_MAX_TRANS_CYC: tha max transaction cycle in IP0;
+*      AXIMON_IP0_SNAP_INFO0: transaction information in IP0;
+*      AXIMON_IP0_SNAP_INFO1: master id of target transaction in IP0.
+*
+*************************************************************************/
+void mdmcu_busmon_record(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDINFRA busmon interrupt occurs in latency&ASSERT mode. 
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_MAX_TRANS_CYC: IP0 max transaction cycle;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdinfra_busmon_latency_assert(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDMCU busmon interrupt occurs in latency&ASSERT mode. 
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_MAX_TRANS_CYC: IP0 max transaction cycle;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdmcu_busmon_latency_assert(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDINFRA busmon interrupt occurs in address&ASSERT mode. 
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_SNAP_INFO0: IP0 transaction info;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdinfra_busmon_addr_assert(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDMCU busmon interrupt occurs in address&ASSERT mode. 
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_SNAP_INFO0: IP0 transaction info;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdmcu_busmon_addr_assert(void);
+
+void addrlog_enable();
+
+void addrlog_disable();
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called in init.c
+*   Default config profiling MO port latency(configure busmon layer after PWB), the default define as follows:  
+*       IP0 monitor MO port read transaction
+*       IP1 monitor MO port write transaction
+*   default monitoring all master, all address, all data.
+*   user can modifiy these parameters if need
+*
+*************************************************************************/
+void busmon_init(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function can be called in dormant_service.c.
+*   This function will be used to restore the value of busmon registers after modem come out from dormant.
+*
+*************************************************************************/
+void busmon_dormant_init(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function can be called in dormant_service.c
+*   This function will be called before entering dormant, used for saving the registers value of busmon.
+*
+*************************************************************************/
+void busmon_dormant_backup(void);
+
+/*************************************************************************
+* FUNCTION
+*  mdmcu_busmon_monitor_init
+*
+* DESCRIPTION
+*   This function can be called in busmon_init
+*   Default config monitor MO port, the default define as follows:  
+*       IP0 monitor MO port read transaction
+*       IP1 monitor MO port write transaction
+*   default monitoring all master,address filter from bank A -- bank F, all data
+*   user can modifiy these parameters if need
+*
+*************************************************************************/
+void mdmcu_busmon_monitor_init(void);
+
+/*************************************************************************
+* FUNCTION
+*  mdmcu_busmon_snap_init
+*
+* DESCRIPTION
+*   This function can be called in busmon_init.c
+*   Default config profiling MO port latency(configure busmon layer after PWB), the default define as follows:  
+*   IP0 monitor MO port read transaction
+*   IP1 monitor MO port write transaction
+*   default monitoring all master, all address, all data, the max cycle cnt is MCU2REG_READ_LIMITED_LATENCY_CNT(1us)
+*   user can modifiy these parameters if need
+*
+*************************************************************************/
+void mdmcu_busmon_snap_init(void);
+
+void mdinfra_busmon_snap_init(void);
+
+/*************************************************************************
+* FUNCTION
+*  mdinfra_busmon_monitor_init
+*
+* DESCRIPTION
+*   This function can be called in busmon_init.c
+*   Default config profiling mdinfra GDMA transaction, the default define as follows:  
+*   IP0 monitor GDMA read transaction
+*   IP1 monitor GDMA write transaction
+*   user can modifiy these parameters if need
+*
+*************************************************************************/
+void mdinfra_busmon_monitor_init(void);
+
+
+/*************************************************************************
+* FUNCTION
+*  busmon_get_avg_latency_and_xac_count
+*
+* DESCRIPTION
+*   USER call this function to get transaction information (not stop busmon)
+*   (i.e. APB average latency and non_wgt_trans_cycle, wgt_trans_cycle..)
+*     
+*   mon_info0 include read transaction info
+*   mon_info1 include write transaction info
+*
+*************************************************************************/
+void busmon_get_avg_latency_and_xac_count(drv_aximon_mon_transaction_info_t *mon_info0, 
+drv_aximon_mon_transaction_info_t *mon_info1);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_atcmd_config
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   bus_id - to select layer;
+*
+* DESCRIPTION
+*   This function is used for configuring bus monitor through AT command;
+*
+*************************************************************************/
+void aximon_atcmd_config(busmon_at_config_t at_config, busmon_busid_t at_bus_id, kal_uint32 at_addr, 
+    kal_uint32 at_addr_msk, kal_uint32 at_master, kal_uint32 at_master_msk, kal_uint32 at_vpe, 
+    kal_uint32 at_vpe_msk, kal_uint32 at_ultra, kal_uint32 at_ultra_msk, kal_uint32 at_data_latcy, kal_uint32 at_data_msk);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_at_config_monitor
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   at_bus_id - to select layer;
+*
+* DESCRIPTION
+*   config busmon monitor mode through AT command;
+*
+*************************************************************************/
+void aximon_at_config_monitor(busmon_at_config_t at_config, busmon_busid_t at_bus_id, 
+    kal_uint32 at_addr, kal_uint32 at_addr_msk, kal_uint32 at_master, kal_uint32 at_master_msk, kal_uint32 at_vpe, 
+    kal_uint32 at_vpe_msk, kal_uint32 at_ultra, kal_uint32 at_ultra_msk);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_at_config_latency
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   at_bus_id - to select layer;
+*
+* DESCRIPTION
+*   config busmon snap mode cycle trigger through AT command;
+*
+*************************************************************************/
+void aximon_at_config_latency (busmon_at_config_t at_config, busmon_busid_t at_bus_id, 
+    kal_uint32 at_addr, kal_uint32 at_addr_msk, kal_uint32 at_master, kal_uint32 at_master_msk, 
+    kal_uint32 at_vpe, kal_uint32 at_vpe_msk, kal_uint32 at_ultra, kal_uint32 at_ultra_msk, kal_uint32 at_data_latcy);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_at_config_addr
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   at_bus_id - to select layer;
+*
+* DESCRIPTION
+*   config busmon monitor mode through AT command;
+*
+*************************************************************************/
+void aximon_at_config_addr(busmon_at_config_t at_config, busmon_busid_t at_bus_id, 
+    kal_uint32 at_addr, kal_uint32 at_addr_msk, kal_uint32 at_master, kal_uint32 at_master_msk, kal_uint32 at_vpe, 
+    kal_uint32 at_vpe_msk, kal_uint32 at_ultra, kal_uint32 at_ultra_msk, kal_uint32 at_data_latcy, kal_uint32 at_data_msk);
+
+
+#endif /* end of __ASSEMBLER__ */
+#endif /* end of __DRV_BUSMON_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/busmon/md97/busmon_reg.h b/mcu/interface/driver/devdrv/busmon/md97/busmon_reg.h
new file mode 100644
index 0000000..6547c62
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmon/md97/busmon_reg.h
@@ -0,0 +1,645 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2013
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   busmon_reg.h
+ *
+ * Project:
+ * --------
+ *   MOLY
+ *
+ * Description:
+ * ------------
+ *   Busmon register definition
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 21 2020 hans.zhang
+ * [MOLY00547955] [Gen97][BUSMON] Busmon ATCMD is removed from C2K to L4
+ * 	
+ * 	EWSP0000133751
+ *
+ * 12 09 2019 hedy.han
+ * [MOLY00443074] [BUSMON]
+ * 	
+ * 	[VMOLY TRUNK][Gen97 Busmon][Change Feature] Save busmon register in exception flow, and config as monitor mode.
+ *
+ * 03 14 2019 hedy.han
+ * [MOLY00345970] [VMOLY.TRUNK]
+ * [VMOLY TRUNK][Gen97 Busmon][New Feature] Porting address logger driver and porting Petrus busmon New feature.
+ *
+ * 12 29 2018 hedy.han
+ * [MOLY00375594] [VMOLY.EVB.SEPT.DEV]
+ * [Gen97 Busmon] Fix enum (Busmon to GCR select value)
+ *
+ * 09 22 2018 hedy.han
+ * [MOLY00345970] [VMOLY.TRUNK]
+ * [New Feature]Gen97 busmon driver.
+ *
+ * 03 29 2018 hedy.han
+ * [MOLY00316943] [New feature][Address logger] Add address logger enable and disable function.
+ * [New feature][Address logger] add address logger enable and disable function.
+ *
+ * 03 12 2018 hedy.han
+ * [MOLY00312512] [UMOLYE TRUNK][GEN95][BUSMON][New Feature][AT command]
+ *
+ * 07 04 2017 liang.yan
+ * [MOLY00244793] [MT6295M]Bus monitor driver build error call for check in
+ * 	.Patch busmon change to MT6295 MP2 branch
+ *
+ * 06 09 2017 liang.yan
+ * [MOLY00244888] [ZION]Bus monitor driver build error call for check in
+ * 	
+ * 	[LR12A.MP1.5.RDIT]Merge ZION project defining
+ *
+ * 03 02 2017 liang.yan
+ * [MOLY00232074] [Change Feature][BIANCO]Adding busmon monitor MO port Latency feature
+ *
+ * 08 05 2016 liang.yan
+ * [MOLY00195782] [Change Feature]93 busmon driver update
+ *
+ * 03 30 2016 i-chun.liu
+ * [MOLY00171939] 93 Busmon check in
+ * busmon check in .
+ *
+ * 01 29 2016 i-chun.liu
+ * [MOLY00163360] Busmon driver update
+ * fix code defect for ahb_busmon.
+ *
+ * 08 17 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * bus monitor update for ELBRUS.
+ *
+ * 06 09 2015 i-chun.liu
+ * [MOLY00119728] JADE bring up call for check in  (MDCIRQ and Bus monitor )
+ * JADE PCORE BUSMON.
+ *
+ * 04 07 2015 i-chun.liu
+ * [MOLY00106215] TK6291 bus monitor driver update
+ * Pcore bus monitor driver update.
+ *
+ * 12 17 2014 i-chun.liu
+ * [MOLY00087840] Update Moly bus monitor driver for denali1
+ * Moly bus monitor driver update.
+ *
+ * 07 29 2014 brian.chiang
+ * [MOLY00070757] busmon drvier update
+ * Bus monitor driver enhancement
+ *
+ * 04 23 2014 brian.chiang
+ * [MOLY00063514] 6595 busmon driver
+ * 6595 busmon deriver porting
+ *
+ * 12 06 2013 vend_brian.chiang
+ * [MOLY00041938] Fix ATEST linking error
+ * Merge MT6595_E1_DEV  into MOLY trunk
+ *
+ * 03 29 2013 vend_hsientang.lee
+ * [MOLY00013013] Add Busmon driver
+ *
+ ****************************************************************************/
+
+#ifndef __BUSMON_REG_H__
+#define __BUSMON_REG_H__
+#include <reg_base.h>
+
+
+/* ************************************************************************************************
+* Below is for Bus Monitor Base Address
+************************************************************************************************ */
+#define BASE_DEBUGAPB_MDMCU_AXIMON0    (BASE_MADDR_MDPERI_MDDBGSYS + 0x38000) //0xA063 8000
+#define BASE_DEBUGAPB_MDINFRA_AXIMON0  (BASE_MADDR_MDPERI_MDDBGSYS + 0x08000) //0xA060 8000  
+#define BASE_ADDR_GCR_COUNTER          (GCR_CUSTOM_ADDR) //0x1F010000
+
+#if defined(DEBUG_APB)
+#define BASE_MADDR_MDMCU_AXIMON   BASE_DEBUGAPB_MDMCU_AXIMON0 //0xA063 8000
+#define BASE_MADDR_MDINFRA_AXIMON BASE_DEBUGAPB_MDINFRA_AXIMON0 //0xA060 8000 
+#else /* Normal APB */
+#define BASE_MADDR_MDMCU_AXIMON   BASE_MADDR_MDMCU_BUSMON //0xA031 0000
+#define BASE_MADDR_MDINFRA_AXIMON BASE_MADDR_MDINFRABUSMON //0xA042 0000
+#endif
+    
+/* ************************************************************************************************
+* Below is for Bus Monitor 
+************************************************************************************************ */
+/********************************Register Field ********************************/
+#define AXIMON_BASE (0)
+
+#define AXIMON_COD_VERSION (AXIMON_BASE + 0x0000)
+#define AXIMON_DMY_REG     (AXIMON_BASE + 0x0004)
+#define AXIMON_TST         (AXIMON_BASE + 0x0014)
+#define AXIMON_STS         (AXIMON_BASE + 0x0018)
+#define AXIMON_INT         (AXIMON_BASE + 0x0020)
+#define AXIMON_INT_MSK     (AXIMON_BASE + 0x0024)
+
+#define AXIMON_IP0_TG      (AXIMON_BASE + 0x0030)
+#define AXIMON_IP0_TMR     (AXIMON_BASE + 0x0034)
+#define AXIMON_IP0_ID_CTL  (AXIMON_BASE + 0x0040)
+#define AXIMON_IP0_VPE     (AXIMON_BASE + 0x0044)
+#define AXIMON_IP0_ADDR    (AXIMON_BASE + 0x0048)
+#define AXIMON_IP0_ADDRMSK (AXIMON_BASE + 0x004C)
+#define AXIMON_IP0_DATA    (AXIMON_BASE + 0x0050)
+#define AXIMON_IP0_DATAMSK (AXIMON_BASE + 0x0060)
+#define AXIMON_IP0_CONSTR  (AXIMON_BASE + 0x0064) /*Ultra length size config*/
+
+#define AXIMON_IP1_TG      (AXIMON_BASE + 0x0070)
+#define AXIMON_IP1_TMR     (AXIMON_BASE + 0x0074)
+#define AXIMON_IP1_ID_CTL  (AXIMON_BASE + 0x0080)
+#define AXIMON_IP1_VPE     (AXIMON_BASE + 0x0084)
+#define AXIMON_IP1_ADDR    (AXIMON_BASE + 0x0088)
+#define AXIMON_IP1_ADDRMSK (AXIMON_BASE + 0x008C)
+#define AXIMON_IP1_DATA    (AXIMON_BASE + 0x0090)
+#define AXIMON_IP1_DATAMSK (AXIMON_BASE + 0x00A0)
+#define AXIMON_IP1_CONSTR  (AXIMON_BASE + 0x00A4) /*Ultra length size config*/
+
+
+#define AXIMON_TOT_BUS_CYC (AXIMON_BASE + 0x0100)
+#define AXIMON_INT_FRC_VAL (AXIMON_BASE + 0x0104) /*Record FRC when INT*/
+
+#define AXIMON_IP0_NON_OV_TRANS_NUM  (AXIMON_BASE + 0x0200)
+#define AXIMON_IP0_OV_TRANS_NUM      (AXIMON_BASE + 0x0204)
+#define AXIMON_IP0_NON_WGT_TRANS_CYC (AXIMON_BASE + 0x0208)
+#define AXIMON_IP0_WGT_TRANS_CYC     (AXIMON_BASE + 0x020C)
+#define AXIMON_IP0_MAX_TRANS_CYC     (AXIMON_BASE + 0x0210)
+#define AXIMON_IP0_MAX_OST_TRANS_NUM (AXIMON_BASE + 0x0214)
+#define AXIMON_IP0_CUR_OST_TRANS_NUM (AXIMON_BASE + 0x0218)
+
+#define AXIMON_IP0_SNAP_INFO0  (AXIMON_BASE + 0x0220)
+#define AXIMON_IP0_SNAP_INFO1  (AXIMON_BASE + 0x0224)
+#define AXIMON_IP0_SNAP_INFO2  (AXIMON_BASE + 0x0228)
+#define AXIMON_IP0_SNAP_INFO3  (AXIMON_BASE + 0x022C)
+#define AXIMON_IP0_SNAP_INFO4  (AXIMON_BASE + 0x0230)
+#define AXIMON_IP0_SNAP_INFO5  (AXIMON_BASE + 0x0234)
+#define AXIMON_IP0_SNAP_INFO6  (AXIMON_BASE + 0x0238)
+#define AXIMON_IP0_SNAP_INFO7  (AXIMON_BASE + 0x023C)
+#define AXIMON_IP0_SNAP_INFO8  (AXIMON_BASE + 0x0240)
+#define AXIMON_IP0_SNAP_INFO9  (AXIMON_BASE + 0x0244)
+#define AXIMON_IP0_SNAP_INFO10 (AXIMON_BASE + 0x0248)
+#define AXIMON_IP0_SNAP_INFO11 (AXIMON_BASE + 0x024C)
+#define AXIMON_IP0_SNAP_INFO12 (AXIMON_BASE + 0x0250) /*Snap VPE status*/
+
+#define AXIMON_IP1_NON_OV_TRANS_NUM  (AXIMON_BASE + 0x0280)
+#define AXIMON_IP1_OV_TRANS_NUM      (AXIMON_BASE + 0x0284)
+#define AXIMON_IP1_NON_WGT_TRANS_CYC (AXIMON_BASE + 0x0288)
+#define AXIMON_IP1_WGT_TRANS_CYC     (AXIMON_BASE + 0x028C)
+#define AXIMON_IP1_MAX_TRANS_CYC     (AXIMON_BASE + 0x0290)
+#define AXIMON_IP1_MAX_OST_TRANS_NUM (AXIMON_BASE + 0x0294)
+#define AXIMON_IP1_CUR_OST_TRANS_NUM (AXIMON_BASE + 0x0298)
+
+#define AXIMON_IP1_SNAP_INFO0   (AXIMON_BASE + 0x02A0)
+#define AXIMON_IP1_SNAP_INFO1   (AXIMON_BASE + 0x02A4)
+#define AXIMON_IP1_SNAP_INFO2   (AXIMON_BASE + 0x02A8)
+#define AXIMON_IP1_SNAP_INFO3   (AXIMON_BASE + 0x02AC)
+#define AXIMON_IP1_SNAP_INFO4   (AXIMON_BASE + 0x02B0)
+#define AXIMON_IP1_SNAP_INFO5   (AXIMON_BASE + 0x02B4)
+#define AXIMON_IP1_SNAP_INFO6   (AXIMON_BASE + 0x02B8)
+#define AXIMON_IP1_SNAP_INFO7   (AXIMON_BASE + 0x02BC)
+#define AXIMON_IP1_SNAP_INFO8   (AXIMON_BASE + 0x02C0)
+#define AXIMON_IP1_SNAP_INFO9   (AXIMON_BASE + 0x02C4)
+#define AXIMON_IP1_SNAP_INFO10  (AXIMON_BASE + 0x02C8)
+#define AXIMON_IP1_SNAP_INFO11  (AXIMON_BASE + 0x02CC)
+#define AXIMON_IP1_SNAP_INFO12  (AXIMON_BASE + 0x02D0) /*Snap VPE status*/
+
+/********************************Register Offset Field ********************************/
+#define AXIMON_CFG_OFFSET      (0x0040) /*AXIMON_IPx_TG*/
+#define AXIMON_INFO_OFFSET     (0x0080) /*AXIMON_IPx_SNAP_INFO0*/
+
+#define AXIMON_IP_TG_OFFSET                (0x0030) /*AXIMON_IP0_TG - AXIMON_BASE*/
+#define AXIMON_IP_TMR_OFFSET               (0x0034) /*AXIMON_IP0_TMR_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_ID_CTL_OFFSET            (0x0040) /*AXIMON_IP0_ID_CTL_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_VPE_OFFSET               (0x0044) /*AXIMON_IP0_VPE_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_ADDR_OFFSET              (0x0048) /*AXIMON_IP0_ADDR_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_ADDRMSK_OFFSET           (0x004C) /*AXIMON_IP0_ADDRMSK_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_DATA_OFFSET              (0x0050) /*AXIMON_IP0_DATA_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_DATAMSK_OFFSET           (0x0060) /*AXIMON_IP0_DATAMSK_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_CONSTR_OFFSET            (0x0064) /*Ultra length size config*/
+
+#define AXIMON_IP_NON_OV_TRANS_NUM_OFFSET  (0x0200) /*AXIMON_IP0_NON_OV_TRANS_NUM_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_OV_TRANS_NUM_OFFSET      (0x0204) /*AXIMON_IP0_OV_TRANS_NUM_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_NON_WGT_TRANS_CYC_OFFSET (0x0208) /*AXIMON_IP0_NON_WGT_TRANS_CYC_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_WGT_TRANS_CYC_OFFSET     (0x020C) /*AXIMON_IP0_WGT_TRANS_CYC_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_MAX_TRANS_CYC_OFFSET     (0x0210) /*AXIMON_IP0_MAX_TRANS_CYC_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_MAX_OST_TRANS_NUM_OFFSET (0x0214) /*AXIMON_IP0_MAX_OST_TRANS_NUM_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_CUR_OST_TRANS_NUM        (0x0218) /*AXIMON_IP0_CUR_OST_TRANS_NUM - AXIMON_BASE*/
+
+#define AXIMON_IP_SNAP_INFO0_OFFSET  (0x0220) /*AXIMON_IP0_SNAP_INFO0_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO1_OFFSET  (0x0224) /*AXIMON_IP0_SNAP_INFO1_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO2_OFFSET  (0x0228) /*AXIMON_IP0_SNAP_INFO2_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO3_OFFSET  (0x022C) /*AXIMON_IP0_SNAP_INFO3_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO4_OFFSET  (0x0230) /*AXIMON_IP0_SNAP_INFO4_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO5_OFFSET  (0x0234) /*AXIMON_IP0_SNAP_INFO5_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO6_OFFSET  (0x0238) /*AXIMON_IP0_SNAP_INFO6_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO7_OFFSET  (0x023C) /*AXIMON_IP0_SNAP_INFO7_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO8_OFFSET  (0x0240) /*AXIMON_IP0_SNAP_INFO8_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO9_OFFSET  (0x0244) /*AXIMON_IP0_SNAP_INFO9_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO10_OFFSET (0x0248) /*AXIMON_IP0_SNAP_INFO10_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO11_OFFSET (0x024C) /*AXIMON_IP0_SNAP_INFO11_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO12_OFFSET (0x0250) /*AXIMON_IP0_SNAP_INFO12_OFFSET - AXIMON_BASE*/
+
+/******************************** Default Value ********************************/
+#define AXIMON_COD_VERSION_DEFAULT   (0x20180315)
+
+/******************************** Bit Field & Mask ********************************/
+/*register:AXIMON_TST*/
+#define AXIMON_TST_SEQ_TRG_MODE_MASK      (0x1)
+#define AXIMON_TST_SEQ_TRG_MODE_SHIFT     (0)
+#define AXIMON_TST_SEQ_CHECK_MODE_MASK    (0x1) /*default:1*/
+#define AXIMON_TST_SEQ_CHECK_MODE_SHIFT   (1)
+#define AXIMON_TST_DISABLE_CG_MASK        (0x1)
+#define AXIMON_TST_DISABLE_CG_SHIFT       (2)
+#define AXIMON_TST_CLEAR_AT_BUSIDLE_MASK  (0x1) /*default:1*/  
+#define AXIMON_TST_CLEAR_AT_BUSIDLE_SHIFT (3)
+#define AXIMON_TST_SPEED_SIM_MASK         (0x1)
+#define AXIMON_TST_SPEED_SIM_SHIFT        (8)
+#define AXIMON_TST_CYC_CNT_WRAP_EN_MASK   (0x1) /*default:1*/
+#define AXIMON_TST_CYC_CNT_WRAP_EN_SHIFT  (9)
+#define AXIMON_TST_MON_OST_MODE_MASK      (0x1) /*defaule:0; defeature in Petrus*/
+#define AXIMON_TST_MON_OST_MODE_SHIFT     (12)
+#define AXIMON_TST_LYR_AXI_SEL_MASK       (0xF)
+#define AXIMON_TST_LYR_AXI_SEL_SHIFT      (16)
+
+/*register:AXIMON_STS*/
+#define AXIMON_STS_STAT0_MASK               (0x3)
+#define AXIMON_STS_STAT0_SHIFT              (0)
+#define AXIMON_STS_STAT1_MASK               (0x3)
+#define AXIMON_STS_STAT1_SHIFT              (4)
+#define AXIMON_STS_IP0_CUR_OVERFLOW_MASK    (0x1)
+#define AXIMON_STS_IP0_CUR_OVERFLOW_SHIFT   (8)
+#define AXIMON_STS_IP0_CUR_UNDERFLOW_MASK   (0x1)
+#define AXIMON_STS_IP0_CUR_UNDERFLOW_SHIFT  (9)
+#define AXIMON_STS_IP1_CUR_OVERFLOW_MASK    (0x1)
+#define AXIMON_STS_IP1_CUR_OVERFLOW_SHIFT   (10)
+#define AXIMON_STS_IP1_CUR_UNDERFLOW_MASK   (0x1)
+#define AXIMON_STS_IP1_CUR_UNDERFLOW_SHIFT  (11)
+#define AXIMON_STS_IP0_HIS_OVERFLOW_MASK    (0x1)
+#define AXIMON_STS_IP0_HIS_OVERFLOW_SHIFT   (12)
+#define AXIMON_STS_IP0_HIS_UNDERFLOW_MASK   (0x1)
+#define AXIMON_STS_IP0_HIS_UNDERFLOW_SHIFT  (13)
+#define AXIMON_STS_IP1_HIS_OVERFLOW_MASK    (0x1)
+#define AXIMON_STS_IP1_HIS_OVERFLOW_SHIFT   (14)
+#define AXIMON_STS_IP1_HIS_UNDERFLOW_MASK   (0x1)
+#define AXIMON_STS_IP1_HIS_UNDERFLOW_SHIFT  (15)
+#define AXIMON_STS_IP0_CUR_ID_MISS_MASK     (0x1)
+#define AXIMON_STS_IP0_CUR_ID_MISS_SHIFT    (16)
+#define AXIMON_STS_IP1_CUR_ID_MISS_MASK     (0x1)
+#define AXIMON_STS_IP1_CUR_ID_MISS_SHIFT    (17)
+#define AXIMON_STS_IP0_HIS_ID_MISS_MASK     (0x1)
+#define AXIMON_STS_IP0_HIS_ID_MISS_SHIFT    (18)
+#define AXIMON_STS_IP1_HIS_ID_MISS_MASK     (0x1)
+#define AXIMON_STS_IP1_HIS_ID_MISS_SHIFT    (19)
+#define AXIMON_STS_IP_TRG_INT_MASK          (0x1)
+#define AXIMON_STS_IP_TRG_INT_SHIFT         (20)
+#define AXIMON_STS_MON_REALENABLE_MASK      (0x1)
+#define AXIMON_STS_MON_REALENABLE_SHIFT     (31)
+
+/*register:AXIMON_INT*/
+#define AXIMON_INT_MASK   (0x1)
+#define AXIMON_INT_SHIFT  (0)
+
+/*register:AXIMON_INT_MSK*/
+#define AXIMON_INT_MSK_MASK  (0x1)
+#define AXIMON_INT_MSK_SHIFT (0)
+
+/*register:AXIMON_IPx_TG*/
+#define AXIMON_TG_MON_START_SEL_MASK     (0x1)
+#define AXIMON_TG_MON_START_SEL_SHIFT    (0)
+#define AXIMON_TG_MON_CNT_WRAP_EN_MASK   (0x1) /*default value is 1*/
+#define AXIMON_TG_MON_CNT_WRAP_EN_SHIFT  (4) 
+#define AXIMON_TG_MON_RWSEL_MASK         (0x1)
+#define AXIMON_TG_MON_RWSEL_SHIFT        (8)
+#define AXIMON_TG_MON_MODE_MASK          (0x1) /*default value is 1*/
+#define AXIMON_TG_MON_MODE_SHIFT         (9)
+#define AXIMON_TG_MON_ENABLE_MASK        (0x1) /*default value is 1*/
+#define AXIMON_TG_MON_ENABLE_SHIFT       (10)
+#define AXIMON_TG_TRG_MODE_MASK          (0x1) /*default value is 0*/
+#define AXIMON_TG_TRG_MODE_SHIFT         (11)
+#define AXIMON_TG_MON_ALL_MST_MASK       (0x1) /*default value is 1*/
+#define AXIMON_TG_MON_ALL_MST_SHIFT      (12)
+#define AXIMON_TG_SNAP_DATA_ENABLE_MASK  (0x1) /*default value is 0*/
+#define AXIMON_TG_SNAP_DATA_ENABLE_SHIFT (13)
+#define AXIMON_TG_MON_CNT_MASK           (0xFFFF)
+#define AXIMON_TG_MON_CNT_SHIFT          (16)
+
+/*register:AXIMON_IPx_TMR*/
+#define AXIMON_TMR_MON_TRG_CYC_MASK      (0xFFFF)
+#define AXIMON_TMR_MON_TRG_CYC_SHIFT     (0)
+
+/*register:AXIMON_IPx_ID_CTL*/
+#define AXIMON_ID_MON_MASTER_MASK       (0x1FFF)
+#define AXIMON_ID_MON_MASTER_SHIFT      (0)
+#define AXIMON_ID_MON_MASTER_MSK_MASK   (0x1FFF)
+#define AXIMON_ID_MON_MASTER_MSK_SHIFT  (16)
+
+/*register:AXIMON_IPx_VPE*/
+#define AXIMON_VPE_MON_VPE_MASK       (0x3FFF)
+#define AXIMON_VPE_MON_VPE_SHIFT      (0)
+#define AXIMON_VPE_MON_VPE_MSK_MASK   (0x3FFF)
+#define AXIMON_VPE_MON_VPE_MSK_SHIFT  (16)
+
+/*register:AXIMON_IPx_CONSTR*/
+#define AXIMON_CONSTR_MON_ULTRA_MASK       (0x3)
+#define AXIMON_CONSTR_MON_ULTRA_SHIFT      (0)
+#define AXIMON_CONSTR_MON_ULTRA_MSK_MASK   (0x3)
+#define AXIMON_CONSTR_MON_ULTRA_MSK_SHIFT  (4)
+#define AXIMON_CONSTR_MON_LEN_MASK         (0xF)
+#define AXIMON_CONSTR_MON_LEN_SHIFT        (8)
+#define AXIMON_CONSTR_MON_LEN_MSK_MASK     (0xF)
+#define AXIMON_CONSTR_MON_LEN_MSK_SHIFT    (12)
+#define AXIMON_CONSTR_MON_SIZE_MASK        (0X7)
+#define AXIMON_CONSTR_MON_SIZE_SHIFT       (16)
+#define AXIMON_CONSTR_MON_SIZE_MSK_MASK    (0X7)
+#define AXIMON_CONSTR_MON_SIZE_MSK_SHIFT   (20)
+
+/*register:AXIMON_IPx_SNAP_INFO0*/
+#define AXIMON_SNAP_INFO0_LEN_MASK    (0xF)
+#define AXIMON_SNAP_INFO0_LEN_SHIFT   (0)
+#define AXIMON_SNAP_INFO0_SIZE_MASK   (0x7)
+#define AXIMON_SNAP_INFO0_SIZE_SHIFT  (4)
+#define AXIMON_SNAP_INFO0_ULTRA_MASK  (0x3)
+#define AXIMON_SNAP_INFO0_ULTRA_SHIFT (7)
+#define AXIMON_SNAP_INFO0_BURST_MASK  (0x3)
+#define AXIMON_SNAP_INFO0_BURST_SHIFT (9)
+#define AXIMON_SNAP_INFO0_LOCK_MASK   (0x3)
+#define AXIMON_SNAP_INFO0_LOCK_SHIFT  (11)
+#define AXIMON_SNAP_INFO0_CACHE_MASK  (0xF)
+#define AXIMON_SNAP_INFO0_CACHE_SHIFT (13)
+#define AXIMON_SNAP_INFO0_PROT_MASK   (0x7)
+#define AXIMON_SNAP_INFO0_PROT_SHIFT  (17)
+#define AXIMON_SNAP_INFO0_RESP_MASK   (0x3)
+#define AXIMON_SNAP_INFO0_RESP_SHIFT  (20)
+
+/*register:AXIMON_IPx_SNAP_INFO1*/
+#define AXIMON_SNAP_INFO1_QID_MASK  (0xFFFF)
+#define AXIMON_SNAP_INFO1_QID_SHIFT (0)
+#define AXIMON_SNAP_INFO1_CNT_MASK  (0xFFFF)
+#define AXIMON_SNAP_INFO1_CNT_SHIFT (16)
+
+#define AXIMON_SNAP_INFO3_STRB0_MASK  (0xFFFF)
+#define AXIMON_SNAP_INFO3_STRB0_SHIFT (0)
+#define AXIMON_SNAP_INFO3_STRB1_MASK  (0xFFFF)
+#define AXIMON_SNAP_INFO3_STRB1_SHIFT (16)
+
+#define AXIMON_MATCH_NONE (0xFFFFFFFF)
+#define AXIMON_MATCH_ALL  (0)
+
+/*************************** Register in AO Domain  ****************************/
+#define AXIMON_MDMCU_LAYER_SELECT   (BASE_MADDR_MDPERIMISC + 0x504) //0xA0060504
+#define AXIMON_MDINFRA_LAYER_SELECT (BASE_MADDR_MDPERIMISC + 0x500)  //0xA0060500
+
+#define AXIMON_BUSMON_LAYER_SEL_MASK  (0xF)
+#define AXIMON_BUSMON_LAYER_SEL_SHIFT (0x0)
+
+#define AXIMON_CTL_START_MASK  (0x1)
+#define AXIMON_CTL_START_SHIFT (16)
+
+/* ************************************************************************************************
+* Below is for Bus recorder 
+************************************************************************************************ */
+/******************************** Register Field ********************************/
+#define BUSREC_REG_RECORDER_CTL           (AXIMON_BASE + 0x400U)
+#define BUSREC_REG_RECORDER_TEST          (AXIMON_BASE + 0x404U)
+#define BUSREC_REG_MON_REC_OBSRV_CTRL     (AXIMON_BASE + 0x408U)
+
+#define BUSREC_REG_IP0_BUFF_CNT           (AXIMON_BASE + 0x500U)
+#define BUSREC_REG_MON_IP0_GRP_CMD_STS    (AXIMON_BASE + 0x504U)
+
+#define BUSREC_REG_IP1_BUFF_CNT           (AXIMON_BASE + 0x700U)
+#define BUSREC_REG_MON_IP1_GRP_CMD_STS    (AXIMON_BASE + 0x704U)
+
+#if defined(MT6297) /*BusRec address has changed in Pertus*/
+#define BUSREC_REG_IP0_GRP1_ID_STS        (AXIMON_BASE + 0x510U)
+#define BUSREC_REG_IP0_GRP1_ADDR_STS      (AXIMON_BASE + 0x514U)
+#define BUSREC_REG_IP0_GRP1_ID_STS_(n)    (AXIMON_BASE + 0x510U + (n) * 0x8)
+#define BUSREC_REG_IP0_GRP1_ADDR_STS_(n)  (AXIMON_BASE + 0x514U + (n) * 0x8)
+
+#define BUSREC_REG_IP1_GRP1_ID_STS        (AXIMON_BASE + 0x710U)
+#define BUSREC_REG_IP1_GRP1_ADDR_STS      (AXIMON_BASE + 0x714U) 
+#define BUSREC_REG_IP1_GRP1_ID_STS_(n)    (AXIMON_BASE + 0x710U + (n) * 0x8)
+#define BUSREC_REG_IP1_GRP1_ADDR_STS_(n)  (AXIMON_BASE + 0x714U + (n) * 0x8)
+
+#else 
+#define BUSREC_REG_IP0_GRP1_ID_STS        (AXIMON_BASE + 0xB00U)
+#define BUSREC_REG_IP0_GRP1_ADDR_STS      (AXIMON_BASE + 0xB04U)
+#define BUSREC_REG_IP0_GRP1_ID_STS_(n)    (AXIMON_BASE + 0xB00U + (n) * 0x8)
+#define BUSREC_REG_IP0_GRP1_ADDR_STS_(n)  (AXIMON_BASE + 0xB04U + (n) * 0x8)
+
+#define BUSREC_REG_IP1_GRP1_ID_STS        (AXIMON_BASE + 0xD00U)
+#define BUSREC_REG_IP1_GRP1_ADDR_STS      (AXIMON_BASE + 0xD04U) 
+#define BUSREC_REG_IP1_GRP1_ID_STS_(n)    (AXIMON_BASE + 0xD00U + (n) * 0x8)
+#define BUSREC_REG_IP1_GRP1_ADDR_STS_(n)  (AXIMON_BASE + 0xD04U + (n) * 0x8)
+#endif
+
+#define BUSREC_REG_CURR_IP0_ID_STS        (AXIMON_BASE + 0x820U)
+#define BUSREC_REG_CURR_IP0_ADDR_STS      (AXIMON_BASE + 0x824U)
+#define BUSREC_REG_CURR_IP0_VPE_STS       (AXIMON_BASE + 0x828U)
+#define BUSREC_REG_CURR_IP0_CTRL_STS      (AXIMON_BASE + 0x82CU)
+
+#define BUSREC_MON_IP0_GRP_HIS_ID_STS     (AXIMON_BASE + 0x830U)
+#define BUSREC_MON_IP0_GRP_HIS_CMD_STS    (AXIMON_BASE + 0x834U)
+#define BUSREC_MON_IP0_GRP_HIS_ADDR_STS   (AXIMON_BASE + 0x838U)
+
+#define BUSREC_REG_CURR_IP1_ID_STS        (AXIMON_BASE + 0x850U)
+#define BUSREC_REG_CURR_IP1_ADDR_STS      (AXIMON_BASE + 0x854U)
+#define BUSREC_REG_CURR_IP1_VPE_STS       (AXIMON_BASE + 0x858U)
+#define BUSREC_REG_CURR_IP1_CTRL_STS      (AXIMON_BASE + 0x85CU)
+
+#define BUSREC_MON_IP1_GRP_HIS_ID_STS     (AXIMON_BASE + 0x860U)
+#define BUSREC_MON_IP1_GRP_HIS_CMD_STS    (AXIMON_BASE + 0x864U)
+#define BUSREC_MON_IP1_GRP_HIS_ADDR_STS   (AXIMON_BASE + 0x868U)
+
+#define BUSREC_REG_LOG_CTL                (AXIMON_BASE + 0x900U)
+#define BUSREC_REG_LOG_STS                (AXIMON_BASE + 0x904U)
+#define BUSREC_REG_LOG_SW_FORCE_OUT       (AXIMON_BASE + 0x908U)
+#define BUSREC_REG_LOG_CG_DIS             (AXIMON_BASE + 0x90CU)
+#define BUSREC_REG_LOG_TEST_CTL           (AXIMON_BASE + 0x910U)
+
+#define BUSREC_MON_IDLE_CTRL              (AXIMON_BASE + 0x918U)
+
+#define BUSREC_MON_CURR_IP0_CMD_STS       (AXIMON_BASE + 0xA00U)
+#define BUSREC_MON_CURR_IP1_CMD_STS       (AXIMON_BASE + 0xA04U)
+
+#define BUSREC_MON_MON2GCR_CTL0           (AXIMON_BASE + 0xA10U)
+#define BUSREC_MON_MON2GCR_CTL1           (AXIMON_BASE + 0xA14U)
+#define BUSREC_MON_MON2GCR_CTL2           (AXIMON_BASE + 0xA18U)
+
+/*NOTE:this register not been defined in MT6297*/
+#define BUSREC_MON_SCAN_COV_DUM           (AXIMON_BASE + 0xF20U)
+
+/********************************Register Offset Field ********************************/
+#define BUSREC_IP_GRP_OFFSET      (0x0200) /*BUSREC_REG_IPX_BUFF_CNT*/
+#define BUSREC_IP_CURR_CTRL_OFFSET   (0x0030) /*BUSREC_REG_CURR_IPx_ID_STS*/
+
+/******************************** Bit Field & Mask ********************************/
+/*register:BUSREC_REG_RECORDER_CTL*/
+#define BUSREC_CTL_TEST_MODE_MASK     (0x1)
+#define BUSREC_CTL_TEST_MODE_SHIFT    (2)
+#define BUSREC_CTL_GATE_AR_MASK       (0x1)
+#define BUSREC_CTL_GATE_AR_SHIFT      (4)
+#define BUSREC_CTL_GATE_AW_MASK       (0x1)
+#define BUSREC_CTL_GATE_AW_SHIFT      (5)
+#define BUSREC_CTL_GATE_R_RESP_MASK   (0x1)
+#define BUSREC_CTL_GATE_R_RESP_SHIFT  (6)
+#define BUSREC_CTL_GATE_B_RESP_MASK   (0x1)
+#define BUSREC_CTL_GATE_B_RESP_SHIFT  (7)
+#define BUSREC_CTL_GATE_W_RESP_MASK   (0x1)
+#define BUSREC_CTL_GATE_W_RESP_SHIFT  (8)
+
+/*register:BUSREC_REG_RECORDER_TEST*/
+#define BUSREC_TEST_TRANS_ADD_MASK      (0x1)
+#define BUSREC_TEST_TRANS_ADD_SHIFT     (0)
+#define BUSREC_TEST_TRANS_ADD_ID_MASK   (0xFF)
+#define BUSREC_TEST_TRANS_ADD_ID_SHIFT  (8)
+#define BUSREC_TEST_TRANS_SUB_MASK      (0x1)
+#define BUSREC_TEST_TRANS_SUB_SHIFT     (16)
+#define BUSREC_TEST_TRANS_SUB_ID_MASK   (0xFF)
+#define BUSREC_TEST_TRANS_SUB_ID_SHIFT  (24)
+
+/*register:BUSREC_REG_MON_REC_OBSRV_CTRL*/
+#define BUSREC_IP0_MON_HIS_FILTER_EN_MASK   (0x1)
+#define BUSREC_IP0_MON_HIS_FILTER_EN_SHIFT  (0)
+#define BUSREC_IP0_HIS_REC_ENTRY_SEL_MASK   (0x7)
+#define BUSREC_IP0_HIS_REC_ENTRY_SEL_SHIFT  (4)
+#define BUSREC_IP0_REC_ENTRY_SEL_MASK       (0x3F) /*petrus busrec depth is 64*/
+#define BUSREC_IP0_REC_ENTRY_SEL_SHIFT      (8)
+#define BUSREC_IP1_MON_HIS_FILTER_EN_MASK   (0x1)
+#define BUSREC_IP1_MON_HIS_FILTER_EN_SHIFT  (16)
+#define BUSREC_IP1_HIS_REC_ENTRY_SEL_MASK   (0x7)
+#define BUSREC_IP1_HIS_REC_ENTRY_SEL_SHIFT  (20)
+#define BUSREC_IP1_REC_ENTRY_SEL_MASK       (0x3F)/*petrus busrec depth is 64*/
+#define BUSREC_IP1_REC_ENTRY_SEL_SHIFT      (24)
+#define BUSREC_MON_HIS_REC_EN_MASK          (0x1)
+#define BUSREC_MON_HIS_REC_EN_SHIFT         (31)
+
+/*register:BUSREC_REG_MON_IPx_GRP_CMD_STS*/
+#define BUSREC_GRP_CMD_AXLEN_MASK     (0XF)
+#define BUSREC_GRP_CMD_AXLEN_SHIFT    (0)
+#define BUSREC_GRP_CMD_AXSIZE_MASK    (0X7)
+#define BUSREC_GRP_CMD_AXSIZE_SHIFT   (4)
+#define BUSREC_GRP_CMD_AXULTRA_MASK   (0X3)
+#define BUSREC_GRP_CMD_AXULTRA_SHIFT  (7)
+#define BUSREC_GRP_CMD_AXBURST_MASK   (0X3)
+#define BUSREC_GRP_CMD_AXBURST_SHIFT  (9)
+#define BUSREC_GRP_CMD_AXLOCK_MASK    (0X3)
+#define BUSREC_GRP_CMD_AXLOCK_SHIFT   (11)
+#define BUSREC_GRP_CMD_AXCACHE_MASK   (0XF)
+#define BUSREC_GRP_CMD_AXCACHE_SHIFT  (13)
+#define BUSREC_GRP_CMD_AXPORT_MASK    (0X7)
+#define BUSREC_GRP_CMD_AXPORT_SHIFT   (17)
+#define BUSREC_GRP_CMD_AXMATCH_MASK   (0X1)
+#define BUSREC_GRP_CMD_AXMATCH_SHIFT  (20)
+
+/*register:BUSREC_MON_IP1_GRP_HIS_ID_STS*/
+#define BUSREC_HIS_ID_AXID_MASK    (0XFFFFF)
+#define BUSREC_HIS_ID_AXID_SHIFT   (0)
+#define BUSREC_HIS_ID_AXVPE_MASK   (0XFFFFF)
+#define BUSREC_HIS_ID_AXVPE_SHIFT  (16)
+
+/*register:BUSREC_MON_IPx_GRP_HIS_CMD_STS*/
+#define BUSREC_HIS_CMD_AXLEN_MASK     (0XF)
+#define BUSREC_HIS_CMD_AXLEN_SHIFT    (0)
+#define BUSREC_HIS_CMD_AXSIZE_MASK    (0X7)
+#define BUSREC_HIS_CMD_AXSIZE_SHIFT   (4)
+#define BUSREC_HIS_CMD_AXULTRA_MASK   (0X3)
+#define BUSREC_HIS_CMD_AXULTRA_SHIFT  (7)
+#define BUSREC_HIS_CMD_AXBURST_MASK   (0X3)
+#define BUSREC_HIS_CMD_AXBURST_SHIFT  (9)
+#define BUSREC_HIS_CMD_AXLOCK_MASK    (0X3)
+#define BUSREC_HIS_CMD_AXLOCK_SHIFT   (11)
+#define BUSREC_HIS_CMD_AXCACHE_MASK   (0XF)
+#define BUSREC_HIS_CMD_AXCACHE_SHIFT  (13)
+#define BUSREC_HIS_CMD_AXPORT_MASK    (0X7)
+#define BUSREC_HIS_CMD_AXPORT_SHIFT   (17)	
+#define BUSREC_HIS_CMD_AXMATCH_MASK   (0X1)
+#define BUSREC_HIS_CMD_AXMATCH_SHIFT  (20)	
+
+/*register:BUSREC_MON_IDLE_CTRL*/
+#define BUSREC_MON_FORCE_BUSY_MASK    (0x1)
+#define BUSREC_MON_FORCE_BUSY_SHIFT   (0)
+#define BUSREC_MON_BUS_IDLE_MSK_MASK  (0x1)
+#define BUSREC_MON_BUS_IDLE_MSK_SHIFT (16)
+
+/*register:BUSREC_MON_MON2GCR_CTL0*/
+#define BUSREC_MON2GCR_CNT0_MASK   (0x1F)
+#define BUSREC_MON2GCR_CNT0_SHIFT  (0)
+#define BUSREC_MON2GCR_CNT1_MASK   (0x1F)
+#define BUSREC_MON2GCR_CNT1_SHIFT  (8)
+#define BUSREC_MON2GCR_CNT2_MASK   (0x1F)
+#define BUSREC_MON2GCR_CNT2_SHIFT  (16)
+
+/*register:BUSREC_MON_MON2GCR_CTL2*/
+#define BUSREC_MON2GCR_STAGE_SEL_MASK   (0x1)
+#define BUSREC_MON2GCR_STAGE_SEL_SHIFT  (0)
+
+#define BUSREC_LOG_EN_MASK              (0x1)
+#define BUSREC_LOG_EN_SHIFT             (0)
+#define BUSREC_LOG_MODE_SEL_MASK        (0x1)
+#define BUSREC_LOG_MODE_SEL_SHIFT       (4)
+#define BUSREC_LOG_DATA_MODE_SEL_MASK   (0x1)
+#define BUSREC_LOG_DATA_MODE_SEL_SHIFT  (12)
+#define BUSREC_LOG_IP0_ATID_MASK        (0x7F)
+#define BUSREC_LOG_IP0_ATID_SHIFT       (16)
+#define BUSREC_LOG_IP1_ATID_MASK        (0x7F)
+#define BUSREC_LOG_IP1_ATID_SHIFT       (24)
+#define BUSREC_LOG_ACLK_CG_DIS_MASK     (0x3)
+#define BUSREC_LOG_ACLK_CG_DIS_SHIFT    (0)
+#define BUSREC_LOG_TEST_CTL_MASK        (0x3)
+#define BUSREC_LOG_TEST_CTL_SHIFT       (0)
+
+/******************************** GCR Register Field ********************************/
+#define MDMCU_BUSMON_CNT0    (BASE_ADDR_GCR_COUNTER + 0xc0)
+#define MDMCU_BUSMON_CNT1    (BASE_ADDR_GCR_COUNTER + 0xc4)
+#define MDMCU_BUSMON_CNT2    (BASE_ADDR_GCR_COUNTER + 0xc8)
+#define MDMCU_BUSMON_CNT3    (BASE_ADDR_GCR_COUNTER + 0xcc)
+#define MDMCU_BUSMON_CNT4    (BASE_ADDR_GCR_COUNTER + 0xd0)
+#define MDMCU_BUSMON_CNT5    (BASE_ADDR_GCR_COUNTER + 0xd4)
+
+#define MDINFRA_BUSMON_CNT0  (BASE_ADDR_GCR_COUNTER + 0xe0)
+#define MDINFRA_BUSMON_CNT1  (BASE_ADDR_GCR_COUNTER + 0xe4)
+#define MDINFRA_BUSMON_CNT2  (BASE_ADDR_GCR_COUNTER + 0xe8)
+#define MDINFRA_BUSMON_CNT3  (BASE_ADDR_GCR_COUNTER + 0xec)
+#define MDINFRA_BUSMON_CNT4  (BASE_ADDR_GCR_COUNTER + 0xf0)
+#define MDINFRA_BUSMON_CNT5  (BASE_ADDR_GCR_COUNTER + 0xf4)
+
+#define MD_BUSMON_CNT_OFFSET (MDINFRA_BUSMON_CNT0 -MDMCU_BUSMON_CNT0)
+
+#endif /* end of __BUSMON_REG_H__ */
+
diff --git a/mcu/interface/driver/devdrv/busmon/md97/drv_busmon.h b/mcu/interface/driver/devdrv/busmon/md97/drv_busmon.h
new file mode 100644
index 0000000..f036f54
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmon/md97/drv_busmon.h
@@ -0,0 +1,1499 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   drv_busmon.h
+ *
+ * Project:
+ * --------
+ *   MOLY
+ *
+ * Description:
+ * ------------
+ *   Header file for Bus monitor control
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 11 07 2020 hans.zhang
+ * [MOLY00591911] [Gen97][Palmer & Petrus_P] change busmon default monitor latency to 5us
+ * 	
+ * 	[Gen97] busmon trigger condition change to 5us
+ *
+ * 07 21 2020 hans.zhang
+ * [MOLY00547955] [Gen97][BUSMON] Busmon ATCMD is removed from C2K to L4
+ * 	
+ * 	EWSP0000133751
+ *
+ * 04 17 2020 hedy.han
+ * [MOLY00503527] [Gen97][Busmon]
+ * [Gen97] modify Mouton latency threshold form 15us to 5us.
+ *
+ * 03 06 2020 hedy.han
+ * [MOLY00503527] [Gen97][Busmon]
+ * [Busmon] Record interrupt FRC count.
+ *
+ * 03 05 2020 hedy.han
+ * [MOLY00503527] [Gen97][Busmon]
+ * 	
+ * 	[Gen97 Busmon]Change Margaux latency from 15us to 5us.
+ *
+ * 12 09 2019 hedy.han
+ * [MOLY00443074] [BUSMON]
+ * 	
+ * 	[VMOLY TRUNK][Gen97 Busmon][Change Feature] Save busmon register in exception flow, and config as monitor mode.
+ *
+ * 11 12 2019 hedy.han
+ * [MOLY00457779] [5G FT][MT6885][Petrus][CMCC FT][SQC][MP1][FT][5GMM][China][CMCC][NSA][Suzhou][MDST][CAT]file:mcu/protocol/enl2/mac/emac/isr/txisr/src/emac_slp.c line:1121
+ * [VMOLY][Busmon]rollback Debug Patch for TXDFE-A bus hang issue.
+ *
+ * 09 24 2019 hedy.han
+ * [MOLY00443074] [BUSMON]
+ * [Gen97 Busmon][ChangeFeature] Modified Petrus MDMCU latency threshold form 15us to 5us.
+ *
+ * 09 04 2019 hedy.han
+ * [MOLY00345970] [VMOLY.TRUNK]
+ * [VMOLY][Busmon] Modified busmon monitor latency throshold from 15us to 5 us.
+ *
+ * 08 21 2019 hedy.han
+ * [MOLY00345970] [VMOLY]
+ * [VMOLY.APOLLO.SQC] Modified IRQ type for LTO.
+ *
+ * 03 14 2019 hedy.han
+ * [MOLY00345970] [VMOLY.TRUNK]
+ * [VMOLY TRUNK][Gen97 Busmon][New Feature] Porting address logger driver and porting Petrus busmon New feature.
+ *
+ * 12 30 2018 hedy.han
+ * [MOLY00375594] [VMOLY.EVB.SEPT.DEV]
+ * [gen97 busmon] fix building warning
+ *
+ * 12 29 2018 hedy.han
+ * [MOLY00375594] [VMOLY.EVB.SEPT.DEV]
+ * [Gen97 Busmon] Fix enum (Busmon to GCR select value)
+ *
+ * 11 07 2018 hedy.han
+ * [MOLY00345970] [VMOLY.TRUNK]
+ * [Gen97 Busmon] Change IRQ group from hardcode to macro define.
+ *
+ * 09 22 2018 hedy.han
+ * [MOLY00345970] [VMOLY.TRUNK]
+ * [New Feature]Gen97 busmon driver.
+ *
+ * 08 06 2018 hedy.han
+ * [MOLY00344260] [Gen95 Busmon][LR13.R0.MP] Remove assert and backup address logger in dormant backup.
+ * [Gen95Busmon][LR13.R0.MP][Delete Assert] delete assert as customer's ask; backup address logger register.
+ *
+ * 04 26 2018 hedy.han
+ * [MOLY00322462] [UMOLYE][HISR] Remove some HISRs and move them to related LISRs
+ * [Busmon Hisr]Delete Busmon HISR.
+ *
+ * 03 29 2018 hedy.han
+ * [MOLY00316943] [New feature][Address logger] Add address logger enable and disable function.
+ * [New feature][Address logger] add address logger enable and disable function.
+ *
+ * 03 12 2018 hedy.han
+ * [MOLY00312512] [UMOLYE TRUNK][GEN95][BUSMON][New Feature][AT command]
+ *
+ * 07 04 2017 liang.yan
+ * [MOLY00244793] [MT6295M]Bus monitor driver build error call for check in
+ * 	.Patch busmon change to MT6295 MP2 branch
+ *
+ * 06 09 2017 liang.yan
+ * [MOLY00244888] [ZION]Bus monitor driver build error call for check in
+ * 	
+ * 	[LR12A.MP1.5.RDIT]Merge ZION project defining
+ *
+ * 06 06 2017 liang.yan
+ * [MOLY00248491] [MT6763][Gen93][System Service][MDCIRQ] Debugging code for GPT IRQ not entered issue
+ * 	[LR12A]Rollback the bus monitor configuration for MDCIRQ issue
+ *
+ * 05 15 2017 yen-chun.liu
+ * [MOLY00248491] [MT6763][Gen93][System Service][MDCIRQ] Debugging code for GPT IRQ not entered issue
+ * busmon debug code for MDCIRQ.
+ *
+ * 05 10 2017 liang.yan
+ * [MOLY00242841] [SE2 Internal CR][Bianco][N1] Kernel API Dump,0,0,99,/data/core/,1,,EMI MPU,Fri Apr 14 23:02:16 CST 2017 @ 2017-04-14 23:02:16.77644,1,2372648
+ * 	Remove busmon debug code for MPU violation in TRUNK
+ *
+ * 05 05 2017 liang.yan
+ * [MOLY00242841] [SE2 Internal CR][Bianco][N1] Kernel API Dump,0,0,99,/data/core/,1,,EMI MPU,Fri Apr 14 23:02:16 CST 2017 @ 2017-04-14 23:02:16.77644,1,2372648
+ * 	[TRUNK]Add MDINFRA busmon debug for mpu violation
+ *
+ * 05 03 2017 liang.yan
+ * [MOLY00242841] [SE2 Internal CR][Bianco][N1] Kernel API Dump,0,0,99,/data/core/,1,,EMI MPU,Fri Apr 14 23:02:16 CST 2017 @ 2017-04-14 23:02:16.77644,1,2372648
+ * 	[TRUNK]bus monitor mo debug for MPU violation
+ *
+ * 05 02 2017 liang.yan
+ * [MOLY00244750] [System Service][MDGDMA][MT6763] Update GDMA debug log for DDL fail.
+ * 	Change MDMCU/MDINFRA busmon parking layer to default point
+ *
+ * 04 25 2017 liang.yan
+ * [MOLY00245013] [BIANCO][MT6763][RDIT][PHONE][Overnight][HQ][MTBF][Lab][Ericsson]Externel (EE) [Others] MD long time no response
+ * 	[TRUNK]Change MDMCU busmon parking layer to MCU2EMI
+ *
+ * 04 14 2017 liang.yan
+ * [MOLY00241937] [VTF_SMT][MT6293][SMT][Bianco][MT6763]Externel (EE),0,0,99,/data/core/,1,modem,md1:(USIP0_USIP0),[ASSERT] file:md32/usip/common/service/loader/src/loader.c line:1086 when overnight cal(1/601times)
+ * 	[UMOLYA]Change mdinfra busmon parking layer after MI
+ *
+ * 03 30 2017 liang.yan
+ * [MOLY00238383] [Change Feature][BUSMON]Change MDMCU busmon parking to PWB
+ *
+ * 03 15 2017 liang.yan
+ * [MOLY00235447] [Change Feature][SS][BUSMON]Add busmon profiling API for user
+ *
+ * 03 02 2017 liang.yan
+ * [MOLY00232074] [Change Feature][BIANCO]Adding busmon monitor MO port Latency feature
+ *
+ * 02 13 2017 i-chun.liu
+ * [MOLY00228094] [Bianco][Bringup] DEV patch back
+ * merge back busmon MO port setting.
+ *
+ * 02 03 2017 i-chun.liu
+ * [MOLY00227643] [Bianco Bring-up][Gen93/INIT/BUSMON] Change MDMCU BUSMON to MO port at init stage.
+ * Change MDMCU BUSMON to MO port at init stage.
+ *
+ * 08 05 2016 liang.yan
+ * [MOLY00195782] [Change Feature]93 busmon driver update
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * workaround for CIRQ driver.
+ *
+ * 03 30 2016 i-chun.liu
+ * [MOLY00171939] 93 Busmon check in
+ * busmon check in .
+ *
+ * 10 07 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * Update bus monitor IRQ code for ELBRUS.
+ *
+ * 08 17 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * bus monitor update for ELBRUS.
+ *
+ * 06 09 2015 i-chun.liu
+ * [MOLY00119728] JADE bring up call for check in  (MDCIRQ and Bus monitor )
+ * JADE PCORE BUSMON.
+ *
+ * 04 07 2015 i-chun.liu
+ * [MOLY00106215] TK6291 bus monitor driver update
+ * pcore busmonitor driver update to prevent modis build fail.
+ *
+ * 04 07 2015 i-chun.liu
+ * [MOLY00106215] TK6291 bus monitor driver update
+ * Pcore bus monitor driver update.
+ *
+ * 07 29 2014 brian.chiang
+ * [MOLY00070757] busmon drvier update
+ * Bus monitor driver enhancement
+ *
+ * 04 23 2014 brian.chiang
+ * [MOLY00063514] 6595 busmon driver
+ * 6595 busmon deriver porting
+ *
+ * 02 21 2014 i-chun.liu
+ * [MOLY00057041] Solve MT6290 bus monitor driver API bug
+ * bus monitor bug
+ *
+ * 05 31 2013 vend_hsientang.lee
+ * [MOLY00024631] Update busmon driver
+ * Use non-post-write to get accurate counter
+ *
+ * 03 29 2013 vend_hsientang.lee
+ * [MOLY00013013] Add Busmon driver
+ *
+ ****************************************************************************/
+
+#ifndef __DRV_BUSMON_H__
+#define __DRV_BUSMON_H__
+
+#if defined(__ASSEMBLER__)
+.macro BUSMON_PRE_CONFIG
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+.endm BUSMON_PRE_CONFIG
+#else
+
+#include "kal_public_defs.h"
+#include "irqid.h"
+#include "busmon_reg.h"
+
+/*******************************************************************************
+ * MACRO DEFINE
+*******************************************************************************/
+#define MO_LATENCY_RECORD_NUM 0x20
+#define AXIMON_TOTAL_AT_CONFIG 0x20
+#define HIS_BUF_ENTRY 0x8
+#define AXIMON_GCR_NUM 0x6
+#define MON2GCR_REG_NUM 0x3
+#if defined(MT6297)
+#define GROUP_NUM 32
+#else
+#define GROUP_NUM 64
+#endif
+
+/*
+*  Define 15us which is the max latency time from mcu to apb read access
+*  MT6297: Busmon clock is fixed at 208M for MDMCU busmon and MDINFRA busmon.
+*  Petrus : Busmon clock is fixed at 216.7M for MDMCU busmon and MDINFRA busmon.  
+*/
+#if defined(MT6297)
+#define MCU2REG_LIMITED_LATENCY_CNT_MDMCU 0x410
+#define MCU2REG_LIMITED_LATENCY_CNT_MDINFRA 0xC30
+
+#elif defined(MT6885) || defined(MT6873) || defined(MT6875) || defined(MT6853)
+#define MCU2REG_LIMITED_LATENCY_CNT_MDMCU 0x43B
+#define MCU2REG_LIMITED_LATENCY_CNT_MDINFRA 0xCB2
+
+#else
+#define MCU2REG_LIMITED_LATENCY_CNT_MDMCU 0x43B
+#define MCU2REG_LIMITED_LATENCY_CNT_MDINFRA 0xCB2
+#endif
+
+#define MDMCUSYS_BUSMON_IRQID MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define MDPERISYS_BUSMON_IRQID MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define MD_BUSMON_IRQID_NUM 2
+
+/* Register field manipulation macro */
+#define EXTRACT_REG_FIELD_VAL(field_val, field_name)      (((field_val) >> (field_name##_SHIFT)) & (field_name##_MASK))
+#define EXPAND_REG_FIELD_VAL(field_val, field_name)       (((field_val) & (field_name##_MASK)) << (field_name##_SHIFT))
+#define CLEAR_REG_FIELD(reg_val, field_name)              ((reg_val) & (~((field_name##_MASK) << (field_name##_SHIFT))))
+#define SET_REG_FIELD_VAL(reg_val, field_val, field_name) (CLEAR_REG_FIELD(reg_val, field_name) | EXPAND_REG_FIELD_VAL(field_val, field_name))
+
+/*******************************************************************************
+ * Below for bus monitor
+ *******************************************************************************/
+typedef enum {
+    MONID_MDMCU_AXIMON = 0, 
+    MONID_MDINFRA_AXIMON,    
+    MONID_MDAXI_MAX
+} drv_aximon_monid_t;
+
+/*Busmon layer select id*/
+typedef enum {
+    /*MD MCU*/
+    BUSMON_BUSID_MDMCUSYS_START = 0UL,    
+    BUSMON_BUSID_MDMCU_MM = BUSMON_BUSID_MDMCUSYS_START,
+    BUSMON_BUSID_MDMCU_MO = 1,
+    BUSMON_BUSID_AF_MO_PWB = 2,/*default value*/
+    BUSMON_BUSID_AF_MO_PWB_MI = 3,
+    BUSMON_BUSID_MDMCU2EMI_AF_MI_BF_GALS = 4,
+    BUSMON_BUSID_RAKE_BRP_BRAM_INR = 5,
+    BUSMON_BUSID_FE_MDINFRA_BF_SI = 6,
+    BUSMON_BUSID_MDMCU2MCORE_BF_IDDWZ = 7,
+    BUSMON_BUSID_MDMCU2AP = 8,
+    BUSMON_BUSID_AF_MM_PWB = 9,
+    BUSMON_BUSID_USIP = 10,
+
+    #if defined (MT6297)
+    BUSMON_BUSID_MDMCUSYS_END = 11,
+    /*MD INFRA*/
+    BUSMON_BUSID_MDINFRA_START = 0,   
+    BUSMON_BUSID_MDINFRA_EMI_A = BUSMON_BUSID_MDINFRA_START,
+    BUSMON_BUSID_MDINFRA_EMI_B = 1,/*default value*/
+    #else
+    BUSMON_BUSID_USIP2L1APB = 11,
+    BUSMON_BUSID_MDMCUSYS_END = 12,
+    /*MD INFRA*/
+    BUSMON_BUSID_MDINFRA_START = 0, 
+    /*NOTE:no layer0 here.*/
+    BUSMON_BUSID_MDINFRA_EMI = 1,/*default value*/
+    #endif
+    
+    BUSMON_BUSID_MDINFRA_MDMCU = 2, 
+    BUSMON_BUSID_MDINFRA_AP = 3,
+    BUSMON_BUSID_MDINFRA_END = 4
+} busmon_busid_t;  
+
+typedef enum {
+    BUSMON_MON_DISABLE = 0,
+    BUSMON_MON_ENABLE
+} drv_busmon_active_t;
+
+typedef enum {
+    BUSMON_MON_STATE_INACTIVE = 0,
+    BUSMON_MON_STATE_ACTIVE
+} drv_busmon_mon_state_t;
+
+typedef enum {
+    BUSMON_IP0 = 0,
+    BUSMON_IP1,
+    BUSMON_IP_MAX
+} drv_busmon_ip_t;
+
+typedef enum {
+    IP_IDLE = 0,
+    IP_REAL_ENABLE,
+    IP_STOP
+} busmon_ip_status_t;
+
+typedef enum {
+    AXIMON_RWSEL_WRITE = 0,
+    AXIMON_RWSEL_READ,
+    AXIMON_RWSEL_MAX
+} drv_aximon_rwsel_t;
+
+typedef enum {
+    START_ORDER_IP0_IP1= 0,
+    STOP_ORDER_IP0_IP1,
+    ORDER_IP0_IP1_MAX  
+} drv_busmon_mon_seq_check_mode_t;
+
+typedef enum {
+    BUSMON_TG_MON_MODE_SNAP = 0,
+    BUSMON_TG_MON_MODE_MONITOR,
+    BUSMON_TG_MON_MODE_MAX
+} drv_busmon_tg_mon_mode_t;
+
+/*Busmon Trigger Mode*/
+typedef enum {
+    BUSMON_TRG_ADDRDATA,
+    BUSMON_TRG_CYCLE,
+    BUSMON_TRG_MAX
+} drv_busmon_trg_mode_t;
+
+typedef enum {
+    MON_VPE_0 = 0x10,   
+    MON_VPE_1 = 0x20,
+    MON_VPE_2 = 0x30,
+    MON_VPE_3 = 0x50,
+    MON_VPE_4 = 0x60,
+    MON_VPE_5 = 0x70,
+    MON_VPE_6 = 0x90,
+    MON_VPE_7 = 0xa0,
+    MON_VPE_8 = 0xb0,
+    MON_VPE_9 = 0xd0,
+    MON_VPE_10 = 0xe0,
+    MON_VPE_11 = 0xf0,
+    MON_SFU_CORE0 = 0x103 ,
+    MON_SFU_CORE1 = 0x143 ,
+    MON_SFU_CORE2 = 0x183 ,
+    MON_SFU_CORE3 = 0x1C3 ,
+    MON_SPU = 0x203,
+    MON_IOCU0_GDMA = 0x182,
+    MON_SHAOLIN_L2 = 0x249
+} busmon_vpe_id_t;
+
+typedef enum {
+    /*monitor mode config command*/
+    MONITOR_START = 0,
+    MCR0 = 0,
+    MCR1 = 1,
+    MCW0 = 2,
+    MCW1 = 3,
+    MIR0 = 4,
+    MIR1 = 5,
+    MIW0 = 6,
+    MIW1 = 7,
+    MONITOR_END = 7,
+    
+    /*latency mode config command*/
+    LATENCY_START = 16,
+    LCR0G = 16,
+    LCR1G = 17,
+    LCW0G = 18,
+    LCW1G= 19,
+    LCR0S = 20,
+    LCR1S = 21,
+    LCW0S = 22,
+    LCW1S = 23,
+    LIR0G = 24,
+    LIR1G = 25,
+    LIW0G = 26,
+    LIW1G= 27,
+    LIR0S = 28,
+    LIR1S = 29,
+    LIW0S = 30,
+    LIW1S = 31,
+    LATENCY_END = 31,
+
+    
+    /*invalid address mode config command*/
+    ADDR_START = 48,
+    ACR0G = 48,
+    ACR1G = 49,
+    ACW0G = 50,
+    ACW1G= 51,
+    ACR0S = 52,
+    ACR1S = 53,
+    ACW0S = 54,
+    ACW1S = 55,
+    AIR0G = 56,
+    AIR1G = 57,
+    AIW0G = 58,
+    AIW1G= 59,
+    AIR0S = 60,
+    AIR1S = 61,
+    AIW0S = 62,
+    AIW1S = 63,
+    ADDR_END = 63,
+
+    MON_CONFIG_START = 100,
+    STARTC = 100, /*start mdmcu busmon*/
+    STOPC = 101,  /*stop mdmcu busmon*/
+    STARTI = 102, /*start mdinfra busmon*/
+    STOPI = 103,  /*stop mdinfra busmon*/
+
+    MDMCU_HIS_BUF = 130,/*get mdmcu history buffer info*/
+    MDINFRA_HIS_BUF = 140,/*get mdinfra history buffer info*/
+
+    TRACE_CTL= 150, /*enable/disable busmon ELT trace*/
+
+    MDMCU_HIS_FILTER_CTL=160,/*enable/disable MDMCU busmon history buffer filter*/
+    MDINFRA_HIS_FILTER_CTL=170,/*enable/disable MDINFRA busmon history buffer filter*/
+   
+    MON_CONFIG_END = 170,
+
+    ADDRLOG_START = 200,
+    ENADDRLOG = 200, /*enable address logger*/
+    DISADDRLOG = 201,/*disable address logger*/
+    ADDRLOG_SWITCH_MOD = 210,/*switch address logger mode*/
+    ADDRLOG_END = 210,
+} busmon_at_config_t;
+
+typedef enum {
+    DISABLE_CTL = 0x0,
+    IP0_NON_OV_TRANS_NUM = 0x1,
+    IP0_OV_TRANS_NUM = 0x2,
+    IP0_NON_WGT_TRANS_CYC = 0x3,
+    IP0_WGT_TRANS_CYC = 0x4,
+    IP0_MAX_TRANS_CYC = 0x5,
+    IP0_MAX_OST_TRANS_NUM = 0x6,
+    IP0_CUR_OST_TRANS_NUM = 0x7,
+    IP0_TOTAL_TRANS_NUM = 0x8,
+    IP0_OST_TRANS_NUM = 0x9,
+    
+    IP1_NON_OV_TRANS_NUM = 0x11,
+    IP1_OV_TRANS_NUM = 0x12,
+    IP1_NON_WGT_TRANS_CYC = 0x13,
+    IP1_WGT_TRANS_CYC = 0x14,
+    IP1_MAX_TRANS_CYC = 0x15,
+    IP1_MAX_OST_TRANS_NUM = 0x16,
+    IP1_CUR_OST_TRANS_NUM = 0x17,
+    IP1_TOTAL_TRANS_NUM = 0x18,
+    IP1_OST_TRANS_NUM = 0x19
+}busmon_mon2gcr_sel;
+
+/*************************************************************************************************
+* Below is for Bus recorder 
+*************************************************************************************************/
+typedef enum {
+    BUSREC_MODE_NORMAL = 0,
+    BUSREC_MODE_TEST,
+} BUSREC_MODE;
+
+typedef enum {
+    BUSREC_GATE_NONE = 0,
+    BUSREC_GATE_RESP,
+    BUSREC_GATE_CMD,
+    BUSREC_GATE_ALL,
+} BUSREC_GATE;
+
+typedef enum {
+    BUSREC_HIS_FILTER_EN_DISABLE= 0,/*disable bus recorder history filter*/
+    BUSREC_HIS_FILTER_EN_ENABLE,/*enable bus recorder history filter*/
+} BUSREC_HIS_FILTER_EN;
+
+typedef enum {
+    BUSREC_HIS_REC_EN_DISABLE= 0,/*disable bus recorder history recorder*/
+    BUSREC_HIS_REC_EN_ENABLE,/*enable bus recorder history recorder*/
+} BUSREC_HIS_REC_EN;
+
+typedef enum {
+    BUSREC_MON_FORCE_BUSY_DISABLE = 0,/*disable bus monitor force busy*/
+    BUSREC_MON_FORCE_BUSY_ENABLE,/*enable bus monitor force busy*/
+} BUSREC_FORCE_BUSY;                      
+
+typedef enum {
+    BUSREC_MON_BUS_IDLE_MSK_DISABLE = 0,/*do not mask bus idle signal*/
+    BUSREC_MON_BUS_IDLE_MSK_ENABLE,/*mask bus idle signal*/
+} BUSREC_BUS_IDLE_MSK;  
+
+/*******************************************************************************
+ * Define data structures.
+ *******************************************************************************/
+typedef struct {
+    BUSREC_HIS_FILTER_EN mon_his_filter_en; /*enable disable history filter*/
+    kal_uint32 his_rec_entry_sel;/*history command entry select (8 history entry for each IP)*/
+    kal_uint32 rec_entry_sel;    /*current command entry select (32 current entry for each IP)*/
+    } drv_busrec_rec_obsrv_ip_ctrl;            
+
+typedef struct {
+    BUSREC_FORCE_BUSY mon_force_busy;/*enable/disable force busmon busy*/
+    BUSREC_BUS_IDLE_MSK mon_bus_idle_msk;/*enable/disable bus idle mask*/
+} drv_busrec_idle_ctrl;	
+
+/*AXImon IP configuration of Monitor mode*/
+typedef struct {
+    kal_bool start_sel;        /*0-axvalid; 1-axvalid&axready*/
+    kal_bool cnt_wrap_en_t;
+    drv_aximon_rwsel_t rwsel;
+    kal_bool all_master_enable;/*any transaction ID*/
+    kal_uint32 master_id;
+    kal_uint32 master_id_mask;
+    kal_uint32 vpe_id;    /*specific VPE ID*/
+    kal_uint32 vpe_id_mask;  
+    kal_uint32 ultra;     /*specific ULTRA*/
+    kal_uint32 ultra_mask;    
+    kal_uint32 addr;      /*address: only used in snap mode*/
+    kal_uint32 addr_mask; /*address mask, 0: check, 1: ignore. only used in snap mode*/
+    kal_uint32 axlen;
+    kal_uint32 axlen_mask;
+    kal_uint32 axsize;
+    kal_uint32 axsize_mask;
+} drv_aximon_mon_config_t;
+
+/*Configuration of Snap Mode*/
+typedef struct {
+    kal_bool start_sel;     /*0-axvalid; 1-axvalid&axready*/
+    kal_bool cnt_wrap_en_t; /* enable/disable performance counter wrap around*/
+    drv_aximon_rwsel_t rwsel;	
+    drv_busmon_trg_mode_t trg_mode; /*trigger mode*/
+    kal_bool all_master_enable; /*ALL Master should only use in Monitor mode*/
+    kal_bool data_enable; /*data target check at counting snap count*/
+    kal_uint32 mon_cnt;     /* count select */
+    kal_uint32 cycle_cnt;   /*max cycle, only use in cycle trigger mode*/
+    kal_uint32 master_id;   /*specific transaction ID */
+    kal_uint32 master_id_mask;
+    kal_uint32 vpe_id;      /*specific VPE ID*/
+    kal_uint32 vpe_id_mask;   
+    kal_uint32 ultra;       /*specific ULTRA */
+    kal_uint32 ultra_mask;
+    kal_uint32 addr;        /*address*/
+    kal_uint32 addr_mask;   /*address mask, 0: check, 1: ignore*/
+    kal_uint32 data;        /*data 0 32-bit of bus width*/
+    kal_uint32 data_mask;   /*data 0 mask 0: check, 1: ignore*/
+    kal_uint32 axlen;
+    kal_uint32 axlen_mask;
+    kal_uint32 axsize;
+    kal_uint32 axsize_mask;
+} drv_aximon_snp_config_t;
+
+/*Configuration of Snap Mode*/
+typedef struct {
+    kal_bool enable_seq_trg; /*TRUE=>sequencial mode, FALSE=>Concurrent mode*/
+    drv_busmon_mon_seq_check_mode_t seq_check_mode; /*START_ORDER_IP0_IP1/STOP_ORDER_IP0_IP1*/
+    drv_aximon_snp_config_t ip[BUSMON_IP_MAX];
+} drv_aximon_trg_config_t;
+
+/*Monitor Mode: Read-related information*/
+typedef struct {
+    kal_uint32 tot_bus_cyc;/*total bus cycle*/
+    kal_uint32 non_ov_trans_num;/*total transaction number*/
+    kal_uint32 ov_trans_num;
+    kal_uint32 non_wgt_trans_cyc;/*total transaction cycle*/
+    kal_uint32 wgt_trans_cyc;
+    kal_uint32 max_trans_cyc;/*max transaction cycle*/
+    kal_uint32 max_ost_trans_num;
+    kal_uint32 cur_ost_trans_num;/*current outstanding transaction number*/ 
+    kal_uint32 bus_util;/*bus utilization*/
+    kal_uint32 avg_xac_cyc;/*average transaction cycle*/
+} drv_aximon_mon_transaction_info_t;
+
+/*Snap Mode :Read-related informatin*/
+typedef struct {
+    kal_uint32 int_frc_val;/*the value of frc when interrupt occurs*/
+    kal_uint32 info0;  /*current AXI bus signal (burst, lock, cache, size...)*/
+    kal_uint32 info1;  /*current target id (QID),target match count*/
+    kal_uint32 info2;  /*snap target address*/
+    kal_uint32 info3;  /*data0&data1 strobe*/
+    kal_uint32 info4;  /*last data[31:0]*/
+    kal_uint32 info5;  /*last data[63:32]*/
+    kal_uint32 info6;  /*last data[95:64]*/
+    kal_uint32 info7;  /*last data[127:96]*/
+    kal_uint32 info8;  /*last second data[31:0]*/
+    kal_uint32 info9;  /*last second data[63:32]*/
+    kal_uint32 info10; /*last second data[95:64]*/
+    kal_uint32 info11; /*last second data[127:96]*/
+    kal_uint32 info12; /*VPE status*/
+} drv_aximon_snp_info_t;
+
+typedef struct{
+    kal_uint32 curr_id;   /*current transaction id*/
+    kal_uint32 curr_addr; /*current transaction addr*/
+    kal_uint32 curr_vpe;  /*current transaction vpe*/
+    kal_uint32 curr_ctrl; /*current transaction ctrl*/
+    kal_uint32 his_id;    /*history transaction id*/
+    kal_uint32 his_cmd;   /*history transaction cmd*/
+    kal_uint32 his_addr;  /*history transaction addr*/
+}drv_aximon_rec_hiscur_info;
+
+typedef struct{
+    kal_uint32 buff_cnt;
+ /*   kal_uint32 grp_cmd[GROUP_NUM];*/
+    kal_uint32 grp_addr[GROUP_NUM];
+    kal_uint32 grp_id[GROUP_NUM];
+}drv_aximon_rec_grp_info;
+
+typedef void (*busmon_intr_cb)(void);
+
+typedef struct {
+    kal_uint32 log_index;
+    kal_uint32 log_frc_count[MO_LATENCY_RECORD_NUM];
+    kal_uint32 log_max_trans_cycle[MO_LATENCY_RECORD_NUM];
+/*	kal_uint32 log_max_trans_frc[MO_LATENCY_RECORD_NUM]; */
+/*	kal_uint32 log_max_trans_addr[MO_LATENCY_RECORD_NUM]; */
+	kal_uint32 log_snap_info0[MO_LATENCY_RECORD_NUM];
+	kal_uint32 log_snap_info1[MO_LATENCY_RECORD_NUM];
+	kal_uint32 log_snap_info2[MO_LATENCY_RECORD_NUM];
+	kal_uint32 log_snap_info3[MO_LATENCY_RECORD_NUM];
+	kal_uint32 log_snap_info4[MO_LATENCY_RECORD_NUM];
+	kal_uint32 log_snap_info5[MO_LATENCY_RECORD_NUM];
+	kal_uint32 log_snap_info6[MO_LATENCY_RECORD_NUM];
+	kal_uint32 log_snap_info7[MO_LATENCY_RECORD_NUM];
+	kal_uint32 log_snap_info8[MO_LATENCY_RECORD_NUM];
+	kal_uint32 log_snap_info9[MO_LATENCY_RECORD_NUM];
+	kal_uint32 log_snap_info10[MO_LATENCY_RECORD_NUM];
+	kal_uint32 log_snap_info11[MO_LATENCY_RECORD_NUM];
+	kal_uint32 log_snap_info12[MO_LATENCY_RECORD_NUM];
+} aximon_ip_log_info_t;
+
+typedef struct{
+    aximon_ip_log_info_t ip[BUSMON_IP_MAX];
+}aximon_log_info_t;
+
+
+/*this struct is used to record the at comand that user input.*/
+typedef struct{
+    busmon_at_config_t at_config_g;
+    busmon_busid_t at_bus_id_g;
+    kal_uint32 at_addr_g;
+    kal_uint32 at_addr_msk_g;
+    kal_uint32 at_master_g;
+    kal_uint32 at_master_msk_g;
+    kal_uint32 at_vpe_g;
+    kal_uint32 at_vpe_msk_g;
+    kal_uint32 at_ultra_g;
+    kal_uint32 at_ultra_msk_g;
+    kal_uint32 at_data_latcy_g;
+    kal_uint32 at_data_msk_g;
+}drv_aximon_at_config;
+
+/*this struct is used to record registers value before entering dormant*/
+typedef struct{
+    kal_uint32 aximon_ctl_r;
+    kal_uint32 aximon_tst_r;
+    kal_uint32 aximon_intmsk_r;
+    kal_uint32 aximon_ip0_tg_r;
+    kal_uint32 aximon_ip0_tmr_r;
+    kal_uint32 aximon_ip0_id_r;
+    kal_uint32 aximon_ip0_vpe_r;
+    kal_uint32 aximon_ip0_addr_r;
+    kal_uint32 aximon_ip0_addrmsk_r;
+    kal_uint32 aximon_ip0_data_r;
+    kal_uint32 aximon_ip0_datamsk_r;
+    kal_uint32 aximon_ip0_constr_r;
+    kal_uint32 aximon_ip1_tg_r;
+    kal_uint32 aximon_ip1_tmr_r;
+    kal_uint32 aximon_ip1_id_r;
+    kal_uint32 aximon_ip1_vpe_r;
+    kal_uint32 aximon_ip1_addr_r;
+    kal_uint32 aximon_ip1_addrmsk_r;
+    kal_uint32 aximon_ip1_data_r;
+    kal_uint32 aximon_ip1_datamsk_r;
+    kal_uint32 aximon_ip1_constr_r;
+    kal_uint32 busrec_obsrv_ctrl_r;
+    kal_uint32 busrec_reg_log_ctr_r;
+    kal_uint32 busrec_reg_log_cg_dis_r;
+    kal_uint32 aximon_mon2gcr_ctl0_r;
+    kal_uint32 aximon_mon2gcr_ctl1_r;
+}drv_aximon_dormant_backup;
+
+typedef struct {
+   busmon_mon2gcr_sel cnt0_sel;
+   busmon_mon2gcr_sel cnt1_sel;
+   busmon_mon2gcr_sel cnt2_sel;
+   busmon_mon2gcr_sel cnt3_sel;
+   busmon_mon2gcr_sel cnt4_sel;
+   busmon_mon2gcr_sel cnt5_sel;
+} drv_aximon_mon2gcr_config_t;
+
+typedef struct{
+    kal_uint32 busrec_his_ip0_id[8];
+    kal_uint32 busrec_his_ip0_cmd[8];
+    kal_uint32 busrec_his_ip0_addr[8];
+    kal_uint32 busrec_his_ip1_id[8];
+    kal_uint32 busrec_his_ip1_cmd[8];
+    kal_uint32 busrec_his_ip1_addr[8];
+}drv_aximon_his;
+
+typedef struct{
+    kal_uint32 cnt[6];
+}drv_aximon_gcr_cnt;
+
+typedef struct{
+    kal_uint32 aximon_tg_dump_r;
+    kal_uint32 aximon_tmr_dump_r;
+    kal_uint32 aximon_id_dump_r;
+    kal_uint32 aximon_vpe_dump_r;
+    kal_uint32 aximon_addr_dump_r;
+    kal_uint32 aximon_addr_msk_dump_r;
+    kal_uint32 aximon_data_dump_r;
+    kal_uint32 aximon_data_msk_dump_r;
+    kal_uint32 axinmon_constr_dump_r;
+}drv_aximon_config_info;
+
+typedef struct{
+    kal_uint32 non_ov_trans_num_dump_r;
+    kal_uint32 ov_trans_num_dump_r;
+    kal_uint32 non_wgt_trans_cyc_dump_r;
+    kal_uint32 wgt_trans_cyc_dump_r;
+    kal_uint32 max_trans_cyc_dump_r;
+    kal_uint32 max_ost_trans_num_dump_r;
+    kal_uint32 cur_ost_trans_num_dump_r;
+}drv_aximon_mon_info;
+
+typedef struct{
+    kal_uint32 aximon_tst_dump_r;
+    kal_uint32 aximon_sts_dump_r;
+    kal_uint32 aximon_int_dump_r;
+    kal_uint32 aximon_int_msk_dump_r;
+
+	/*IP0 IP1 config info*/
+    drv_aximon_config_info config_info[BUSMON_IP_MAX];
+
+	/*monitor info and snap info*/
+    kal_uint32 tot_bus_sys_dump_r;
+	kal_uint32 int_frc_dump_r;
+	drv_aximon_mon_info mon_info[BUSMON_IP_MAX];
+	drv_aximon_snp_info_t snap_info[BUSMON_IP_MAX];
+		
+    kal_uint32 rec_obsrv_ctrl_r;
+	drv_aximon_rec_hiscur_info rec_info[BUSMON_IP_MAX];
+	
+    kal_uint32 log_ctl_dump_r;
+    kal_uint32 log_sts_dump_r;
+
+	kal_uint32 mon_curr_ip0_cmd_dump_r;
+	kal_uint32 mon_curr_ip1_cmd_dump_r;
+
+	drv_aximon_rec_grp_info rec_grp_info[BUSMON_IP_MAX];
+
+}drv_aximon_dump_r;
+
+/* ************************************************************************************************
+* 
+* AXIMon External Fucntion Declearation
+*
+**************************************************************************************************/
+void drv_busmon_lisr(kal_uint32 busmon_irq_id);
+
+/*************************************************************************
+ * DESCRIPTION
+ *	Bus monitor register lisr & callback function in trigger mode.
+ *
+ * PARAMETERS
+ *	 callback,busmon_irq_id
+ *
+ * RETURNS
+ *
+ * NOTE
+ *************************************************************************/
+void drv_busmon_set_trg_cb(busmon_intr_cb callback, kal_uint32 busmon_irq_id);
+
+ /*************************************************************************
+* DESCRIPTION
+*   Get BusMon base address
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*    base address
+*************************************************************************/
+kal_uint32 aximon_read_base_addr(drv_aximon_monid_t axi_mon_id);
+
+ /*************************************************************************
+* DESCRIPTION
+*   Config busmon layer.
+*
+* PARAMETERS
+*   axi_mon_id, bus_id
+*
+* RETURNS
+*     1     config success;
+*   -1     wrong bus monitor id;
+*   -2     select MDMCU busmon, wrong bus layer id in MDMCU busmon;
+*   -3     select MDINFRA busmon, wrong bus layer id in MDINFRA busmon;
+*   -4     bus monitor is started;
+*   -5     config layer is not equal with the value in AXIMON_TST register.
+*************************************************************************/
+kal_int32  aximon_set_busid(drv_aximon_monid_t axi_mon_id, busmon_busid_t bus_id);
+
+
+/*************************************************************************
+* DESCRIPTION
+*   Enable/Disable Speed Sim
+*
+* PARAMETERS
+*   axi_mon_id, enabled
+*
+* RETURNS
+*   NONE
+*************************************************************************/
+void aximon_set_speedsim(drv_aximon_monid_t axi_mon_id, kal_bool enabled);
+
+ /*************************************************************************
+* DESCRIPTION
+*   Whether clear some flag and registers when bus is idle.
+*	enabled = KAL_FALSE: not clear
+*	enabled = KAL_TRUE:  clear
+*
+* PARAMETERS
+*   axi_mon_id, enabled
+*
+* RETURNS
+*   NONE
+*************************************************************************/
+void aximon_set_clear_at_bus_idle(drv_aximon_monid_t axi_mon_id, kal_bool enabled);
+
+  /*************************************************************************
+ * DESCRIPTION
+ *  wait IP real enable
+ *
+ * PARAMETERS
+ *   axi_mon_id, mon_ip
+ *
+ * RETURNS
+ *   NONE
+ *************************************************************************/
+ void aximon_polling_IP_Real_Enable(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip);
+
+   /*************************************************************************
+ * DESCRIPTION
+ *	 disable = KAL_FALSE: enable clock gated, bus monitor can power down.
+ *	 disable = KAL_TURE: disable clock gated, bus monitor will not power down, this function maily for debug.
+ *
+ * PARAMETERS
+ *	 axi_mon_id, disable
+ *
+ * RETURNS
+ *
+ *
+ * NOTE
+ *  
+ *************************************************************************/
+ void aximon_set_disable_cg(drv_aximon_monid_t axi_mon_id, kal_bool disable);
+
+    /*************************************************************************
+* DESCRIPTION
+*   enable/disable bus monitor cycle count wrap.
+*   enabled = KAL_TRUE: enable bus monitor cycle count wrap.
+*   enabled = KAL_FALSE:  disable bus monitor cycle count wrap.
+*
+* PARAMETERS
+*   axi_mon_id, enabled
+*
+* RETURNS
+*   NONE
+*
+* NOTE
+*   
+*************************************************************************/
+void aximon_set_cyc_cnt_wrap_en(drv_aximon_monid_t axi_mon_id, kal_bool enabled);
+
+ /*************************************************************************
+* DESCRIPTION
+*   config busmon outstanding mode: 32/64
+*   enable_ost64 = KAL_TRUE: config busmon as 64 ost mode.
+*   enable_ost64 = KAL_FALSE: config busmon as 32 ost mode.
+*
+* PARAMETERS
+*   axi_mon_id, enable_ost64
+*
+* RETURNS
+*   NONE
+*
+*************************************************************************/
+void aximon_set_ost_mode(drv_aximon_monid_t axi_mon_id, kal_bool enable_ost64);
+
+ /*************************************************************************
+* DESCRIPTION
+*   select whicn time to input cmd to busrec. 
+*   start_sel = 0x0: axvalid.
+*   start_sel = 0x1: axvalid&axready.
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip,start_sel
+*
+* RETURNS
+*   NONE
+*   
+*************************************************************************/ 
+void aximon_ip_start_sel(drv_aximon_monid_t axi_mon_id,  drv_busmon_ip_t mon_ip, kal_uint32 start_sel );
+
+/*************************************************************************
+* DESCRIPTION
+*   enable/disable bus recorder history record.
+*   enabled = KAL_FALSE: disable bus recorder history record;
+*   enabled = KAL_TRUE:   enable bus recorder history record;
+*
+* PARAMETERS
+*   axi_mon_id, enabled
+*
+* RETURNS
+*   NONE
+*
+* NOTE
+*   
+*************************************************************************/
+void aximon_set_mon_his_rec_en(drv_aximon_monid_t axi_mon_id, kal_bool enabled);
+
+/*************************************************************************
+* DESCRIPTION
+*    set bus recorder abservation register
+*	obsrv_ip_ctrl->mon_his_filter_en = KAL_FALSE, bus recorder no need condition match when record history transaction command
+*	obsrv_ip_ctrl->mon_his_filter_en = KAL_TRUE , bus recorder need condition match when record history transaction command
+*    obsrv_ip_ctrl->his_rec_entry_sel (0-7), select history transaction command entry to observe
+*    obsrv_ip_ctrl->rec_entry_sel (0-31), select current transaction command entry to observe
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip, obsrv_ip_ctrl
+*
+* RETURNS
+*   NONE
+*
+* NOTE
+*   
+*************************************************************************/
+void aximon_set_mon_obsrv_entry(drv_aximon_monid_t axi_mon_id,  drv_busmon_ip_t mon_ip, 
+drv_busrec_rec_obsrv_ip_ctrl *obsrv_ip_ctrl);
+
+/*************************************************************************
+* DESCRIPTION
+*  config the busmon&bus idle signal
+*
+* PARAMETERS
+*   axi_mon_id;busrec_idle_ctrl;
+*
+* RETURNS
+*	
+*************************************************************************/
+void  aximon_set_idle_ctrl (drv_aximon_monid_t axi_mon_id, drv_busrec_idle_ctrl* busrec_idle_ctrl);
+
+/*************************************************************************
+* DESCRIPTION
+*  config the busmon2GCR register
+*
+* PARAMETERS
+*   axi_mon_id;gcr_ctl;
+*
+* RETURNS
+*	
+*************************************************************************/
+void aximon_set_mon2gcr_ctrl(drv_aximon_monid_t axi_mon_id, drv_aximon_mon2gcr_config_t* gcr_ctl);
+
+/*************************************************************************
+* DESCRIPTION
+*  Configure parameters used in Monitor Mode
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip, config
+*
+* RETURNS
+*   1  if the configuration applied
+*************************************************************************/
+kal_int32 aximon_set_monitor(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip, drv_aximon_mon_config_t *config);
+
+/*************************************************************************
+* DESCRIPTION
+*  Configure parametes used in Snapshot Mode
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip, config
+*
+* RETURNS
+*   1  if the configuration applied
+*************************************************************************/
+kal_int32 aximon_set_snap(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip, drv_aximon_snp_config_t *config);
+
+/*************************************************************************
+* DESCRIPTION
+*  Configure parameters in Sequential Trigger Mode
+*
+* PARAMETERS
+*   axi_mon_id, config
+*
+* RETURNS
+*   1   if the configuration applied
+*************************************************************************/
+kal_int32 aximon_set_sq_trg(drv_aximon_monid_t axi_mon_id, drv_aximon_trg_config_t *config);
+
+/*************************************************************************
+ * DESCRIPTION
+ *	Start bus monitor
+ *
+ * PARAMETERS
+ *	 axi_mon_id
+ *
+ * RETURNS
+ *
+ * NOTE
+ *	 BusMon clears the counts first.
+ *	 BusMon always waits for the on-going transaction finished
+ *	 before starting to update the counts.
+ *************************************************************************/
+ void aximon_start(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Stop bus monitor
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*
+* NOTE
+*   BusMon always waits for the on-going transaction finished
+*   before stopping to update the counts.
+*   Some counts stop to update once stopped received Some counts
+*   continues to update until all transactions fishished.
+*************************************************************************/
+void aximon_stop(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Enable interrupt
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*************************************************************************/
+void aximon_enable_interrupt(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Disable interrupt
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*************************************************************************/
+void aximon_disable_interrupt(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Clear interrupt
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*************************************************************************/
+void aximon_clear_interrupt(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Read-related Information in Monitor Mode
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip, info
+*
+* RETURNS
+*************************************************************************/
+void aximon_get_ip_transaction_info(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip, 
+drv_aximon_mon_transaction_info_t *info);
+
+/*************************************************************************
+* DESCRIPTION
+*  Get triggered information in Snapshot Mode
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip, info
+*
+* RETURNS
+*************************************************************************/
+void aximon_get_snap_info(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip, 
+drv_aximon_snp_info_t *info);
+
+/*************************************************************************
+* DESCRIPTION
+*  Read-related Information in Monitor Mode through GCR
+*
+* PARAMETERS
+*   axi_mon_id, gcr_cnt
+*
+* RETURNS
+*************************************************************************/
+void aximon_get_gcr_transaction_info(drv_aximon_monid_t axi_mon_id, 
+drv_aximon_gcr_cnt *gcr_cnt);
+
+/*************************************************************************
+* DESCRIPTION
+*  Get all transactions in history buffer.
+*
+* PARAMETERS
+*   axi_mon_id, aximon_his
+*
+* RETURNS
+*************************************************************************/
+void aximon_get_his_buf(drv_aximon_monid_t axi_mon_id,drv_aximon_his *aximon_his);
+
+/*************************************************************************
+* DESCRIPTION
+*  Polling the triggered status
+*
+* PARAMETERS
+*   axi_mon_id, max_count, ip0_state, ip1_state
+*
+* RETURNS
+*	KAL_TRUE  if the interrupt triggered
+*	KAL_FALSE if no  interrupt triggered
+*************************************************************************/
+kal_bool  aximon_poll_trigged(drv_aximon_monid_t axi_mon_id, kal_uint32 max_count, 
+drv_busmon_mon_state_t *ip0_state, drv_busmon_mon_state_t *ip1_state);
+
+/*************************************************************************
+* DESCRIPTION
+*  disable IP0 and IP1.
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*************************************************************************/
+void aximon_disable_both_ip(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Confirm the AXI Monitor is enable or not
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*************************************************************************/
+kal_bool  drv_busmon_is_started(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDINFRA busmon interrupt occurs in log mode. 
+*   After MDINFRA busmon interrupt occurs in log mode, just record the registers information and clear interrupt.
+*   The define as follows
+*      AXIMON_IP0_SNAP_INFO2: the address of target transaction in IP0;
+*      AXIMON_IP0_MAX_TRANS_CYC: tha max transaction cycle in IP0;
+*      AXIMON_IP0_SNAP_INFO0: transaction information in IP0;
+*      AXIMON_IP0_SNAP_INFO1: master id of target transaction in IP0.
+*
+*************************************************************************/
+void mdinfra_busmon_record(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDMCU busmon interrupt occurs in log mode. 
+*   After MDMCU busmon interrupt occurs in log mode, just record the registers information and clear interrupt.
+*   The define as follows
+*      AXIMON_IP0_SNAP_INFO2: the address of target transaction in IP0;
+*      AXIMON_IP0_MAX_TRANS_CYC: tha max transaction cycle in IP0;
+*      AXIMON_IP0_SNAP_INFO0: transaction information in IP0;
+*      AXIMON_IP0_SNAP_INFO1: master id of target transaction in IP0.
+*
+*************************************************************************/
+void mdmcu_busmon_record(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDINFRA busmon interrupt occurs in latency&ASSERT mode. 
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_MAX_TRANS_CYC: IP0 max transaction cycle;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdinfra_busmon_latency_assert(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDMCU busmon interrupt occurs in latency&ASSERT mode. 
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_MAX_TRANS_CYC: IP0 max transaction cycle;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdmcu_busmon_latency_assert(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDINFRA busmon interrupt occurs in address&ASSERT mode. 
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_SNAP_INFO0: IP0 transaction info;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdinfra_busmon_addr_assert(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDMCU busmon interrupt occurs in address&ASSERT mode. 
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_SNAP_INFO0: IP0 transaction info;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdmcu_busmon_addr_assert(void);
+
+void addrlog_enable();
+void addrlog_disable();
+void addrlog_switch_mode(kal_uint32 mode);
+void addrlog_pattern_gen_enable();
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called in init.c
+*   Default config profiling MO port latency(configure busmon layer after PWB), the default define as follows:  
+*       IP0 monitor MO port read transaction
+*       IP1 monitor MO port write transaction
+*   default monitoring all master, all address, all data.
+*   user can modifiy these parameters if need
+*
+*************************************************************************/
+void busmon_init(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function can be called in dormant_service.c.
+*   This function will be used to restore the value of busmon registers after modem come out from dormant.
+*
+*************************************************************************/
+void busmon_dormant_init(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function can be called in dormant_service.c
+*   This function will be called before entering dormant, used for saving the registers value of busmon.
+*
+*************************************************************************/
+void busmon_dormant_backup(void);
+
+/*************************************************************************
+* FUNCTION
+*  mdmcu_busmon_monitor_init
+*
+* DESCRIPTION
+*   This function can be called in busmon_init
+*   Default config monitor MO port, the default define as follows:  
+*       IP0 monitor MO port read transaction
+*       IP1 monitor MO port write transaction
+*   default monitoring all master,address filter from bank A -- bank F, all data
+*   user can modifiy these parameters if need
+*
+*************************************************************************/
+void mdmcu_busmon_monitor_init(void);
+
+/*************************************************************************
+* FUNCTION
+*  mdmcu_busmon_snap_init
+*
+* DESCRIPTION
+*   This function can be called in busmon_init.c
+*   Default config profiling MO port latency(configure busmon layer after PWB), the default define as follows:  
+*   IP0 monitor MO port read transaction
+*   IP1 monitor MO port write transaction
+*   default monitoring all master, all address, all data, the max cycle cnt is MCU2REG_READ_LIMITED_LATENCY_CNT(1us)
+*   user can modifiy these parameters if need
+*
+*************************************************************************/
+void mdmcu_busmon_snap_init(void);
+
+void mdinfra_busmon_snap_init(void);
+
+/*************************************************************************
+* FUNCTION
+*  mdinfra_busmon_monitor_init
+*
+* DESCRIPTION
+*   This function can be called in busmon_init.c
+*   Default config profiling mdinfra GDMA transaction, the default define as follows:  
+*   IP0 monitor GDMA read transaction
+*   IP1 monitor GDMA write transaction
+*   user can modifiy these parameters if need
+*
+*************************************************************************/
+void mdinfra_busmon_monitor_init(void);
+
+/*************************************************************************
+* FUNCTION
+*  busmon_ex_dump
+*
+* DESCRIPTION
+*   This function can be called in exception flow to dump busmon reg.
+*
+*************************************************************************/
+void busmon_ex_dump();
+
+/*************************************************************************
+* FUNCTION
+*  busmon_ex_dump
+*
+* DESCRIPTION
+*   This function can be called in exception flow to save busmon reg.
+*
+*************************************************************************/
+void busmon_ex_backup(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* FUNCTION
+*  busmon_ex_restart
+*
+* DESCRIPTION
+*   This function can be called in exception flow to restart busmon.
+*
+*************************************************************************/
+void busmon_ex_config(void);
+
+/*************************************************************************
+* FUNCTION
+*  busmon_get_avg_latency_and_xac_count
+*
+* DESCRIPTION
+*   USER call this function to get transaction information (not stop busmon)
+*   (i.e. APB average latency and non_wgt_trans_cycle, wgt_trans_cycle..)
+*     
+*   mon_info0 include read transaction info
+*   mon_info1 include write transaction info
+*
+*************************************************************************/
+void busmon_get_avg_latency_and_xac_count(drv_aximon_mon_transaction_info_t *mon_info0, 
+drv_aximon_mon_transaction_info_t *mon_info1);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_atcmd_config
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   bus_id - to select layer;
+*
+* DESCRIPTION
+*   This function is used for configuring bus monitor through AT command;
+*
+*************************************************************************/
+void aximon_atcmd_config(busmon_at_config_t at_config, busmon_busid_t at_bus_id, kal_uint32 at_addr, 
+    kal_uint32 at_addr_msk, kal_uint32 at_master, kal_uint32 at_master_msk, kal_uint32 at_vpe, 
+    kal_uint32 at_vpe_msk, kal_uint32 at_ultra, kal_uint32 at_ultra_msk, kal_uint32 at_data_latcy, kal_uint32 at_data_msk);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_at_config_monitor
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   at_bus_id - to select layer;
+*
+* DESCRIPTION
+*   config busmon monitor mode through AT command;
+*
+*************************************************************************/
+void aximon_at_config_monitor(busmon_at_config_t at_config, busmon_busid_t at_bus_id, 
+    kal_uint32 at_addr, kal_uint32 at_addr_msk, kal_uint32 at_master, kal_uint32 at_master_msk, kal_uint32 at_vpe, 
+    kal_uint32 at_vpe_msk, kal_uint32 at_ultra, kal_uint32 at_ultra_msk);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_at_config_latency
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   at_bus_id - to select layer;
+*
+* DESCRIPTION
+*   config busmon snap mode cycle trigger through AT command;
+*
+*************************************************************************/
+void aximon_at_config_latency (busmon_at_config_t at_config, busmon_busid_t at_bus_id, 
+    kal_uint32 at_addr, kal_uint32 at_addr_msk, kal_uint32 at_master, kal_uint32 at_master_msk, 
+    kal_uint32 at_vpe, kal_uint32 at_vpe_msk, kal_uint32 at_ultra, kal_uint32 at_ultra_msk, kal_uint32 at_data_latcy);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_at_config_addr
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   at_bus_id - to select layer;
+*
+* DESCRIPTION
+*   config busmon monitor mode through AT command;
+*
+*************************************************************************/
+void aximon_at_config_addr(busmon_at_config_t at_config, busmon_busid_t at_bus_id, 
+    kal_uint32 at_addr, kal_uint32 at_addr_msk, kal_uint32 at_master, kal_uint32 at_master_msk, kal_uint32 at_vpe, 
+    kal_uint32 at_vpe_msk, kal_uint32 at_ultra, kal_uint32 at_ultra_msk, kal_uint32 at_data_latcy, kal_uint32 at_data_msk);
+
+
+#endif /* end of __ASSEMBLER__ */
+#endif /* end of __DRV_BUSMON_H__ */
+ 
+ 
+
diff --git a/mcu/interface/driver/devdrv/busmon/md97p/busmon_reg.h b/mcu/interface/driver/devdrv/busmon/md97p/busmon_reg.h
new file mode 100644
index 0000000..1596ac5
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmon/md97p/busmon_reg.h
@@ -0,0 +1,631 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2013
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   busmon_reg.h
+ *
+ * Project:
+ * --------
+ *   MOLY
+ *
+ * Description:
+ * ------------
+ *   Busmon register definition
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 03 14 2019 hedy.han
+ * [MOLY00345970] [VMOLY.TRUNK]
+ * [VMOLY TRUNK][Gen97 Busmon][New Feature] Porting address logger driver and porting Petrus busmon New feature.
+ *
+ * 12 29 2018 hedy.han
+ * [MOLY00375594] [VMOLY.EVB.SEPT.DEV]
+ * [Gen97 Busmon] Fix enum (Busmon to GCR select value)
+ *
+ * 09 22 2018 hedy.han
+ * [MOLY00345970] [VMOLY.TRUNK]
+ * [New Feature]Gen97 busmon driver.
+ *
+ * 03 29 2018 hedy.han
+ * [MOLY00316943] [New feature][Address logger] Add address logger enable and disable function.
+ * [New feature][Address logger] add address logger enable and disable function.
+ *
+ * 03 12 2018 hedy.han
+ * [MOLY00312512] [UMOLYE TRUNK][GEN95][BUSMON][New Feature][AT command]
+ *
+ * 07 04 2017 liang.yan
+ * [MOLY00244793] [MT6295M]Bus monitor driver build error call for check in
+ * 	.Patch busmon change to MT6295 MP2 branch
+ *
+ * 06 09 2017 liang.yan
+ * [MOLY00244888] [ZION]Bus monitor driver build error call for check in
+ * 	
+ * 	[LR12A.MP1.5.RDIT]Merge ZION project defining
+ *
+ * 03 02 2017 liang.yan
+ * [MOLY00232074] [Change Feature][BIANCO]Adding busmon monitor MO port Latency feature
+ *
+ * 08 05 2016 liang.yan
+ * [MOLY00195782] [Change Feature]93 busmon driver update
+ *
+ * 03 30 2016 i-chun.liu
+ * [MOLY00171939] 93 Busmon check in
+ * busmon check in .
+ *
+ * 01 29 2016 i-chun.liu
+ * [MOLY00163360] Busmon driver update
+ * fix code defect for ahb_busmon.
+ *
+ * 08 17 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * bus monitor update for ELBRUS.
+ *
+ * 06 09 2015 i-chun.liu
+ * [MOLY00119728] JADE bring up call for check in  (MDCIRQ and Bus monitor )
+ * JADE PCORE BUSMON.
+ *
+ * 04 07 2015 i-chun.liu
+ * [MOLY00106215] TK6291 bus monitor driver update
+ * Pcore bus monitor driver update.
+ *
+ * 12 17 2014 i-chun.liu
+ * [MOLY00087840] Update Moly bus monitor driver for denali1
+ * Moly bus monitor driver update.
+ *
+ * 07 29 2014 brian.chiang
+ * [MOLY00070757] busmon drvier update
+ * Bus monitor driver enhancement
+ *
+ * 04 23 2014 brian.chiang
+ * [MOLY00063514] 6595 busmon driver
+ * 6595 busmon deriver porting
+ *
+ * 12 06 2013 vend_brian.chiang
+ * [MOLY00041938] Fix ATEST linking error
+ * Merge MT6595_E1_DEV  into MOLY trunk
+ *
+ * 03 29 2013 vend_hsientang.lee
+ * [MOLY00013013] Add Busmon driver
+ *
+ ****************************************************************************/
+
+#ifndef __BUSMON_REG_H__
+#define __BUSMON_REG_H__
+#include <reg_base.h>
+
+
+/* ************************************************************************************************
+* Below is for Bus Monitor Base Address
+************************************************************************************************ */
+#define BASE_DEBUGAPB_MDMCU_AXIMON0    (BASE_MADDR_MDPERI_MDDBGSYS + 0x38000) //0xA063 8000
+#define BASE_DEBUGAPB_MDINFRA_AXIMON0  (BASE_MADDR_MDPERI_MDDBGSYS + 0x08000) //0xA060 8000  
+#define BASE_ADDR_GCR_COUNTER          (GCR_CUSTOM_ADDR) //0x1F010000
+
+#if defined(DEBUG_APB)
+#define BASE_MADDR_MDMCU_AXIMON   BASE_DEBUGAPB_MDMCU_AXIMON0 //0xA063 8000
+#define BASE_MADDR_MDINFRA_AXIMON BASE_DEBUGAPB_MDINFRA_AXIMON0 //0xA060 8000 
+#else /* Normal APB */
+#define BASE_MADDR_MDMCU_AXIMON   BASE_MADDR_MDMCU_BUSMON //0xA031 0000
+#define BASE_MADDR_MDINFRA_AXIMON BASE_MADDR_MDINFRABUSMON //0xA042 0000
+#endif
+    
+/* ************************************************************************************************
+* Below is for Bus Monitor 
+************************************************************************************************ */
+/********************************Register Field ********************************/
+#define AXIMON_BASE (0)
+
+#define AXIMON_COD_VERSION (AXIMON_BASE + 0x0000)
+#define AXIMON_DMY_REG     (AXIMON_BASE + 0x0004)
+#define AXIMON_TST         (AXIMON_BASE + 0x0014)
+#define AXIMON_STS         (AXIMON_BASE + 0x0018)
+#define AXIMON_INT         (AXIMON_BASE + 0x0020)
+#define AXIMON_INT_MSK     (AXIMON_BASE + 0x0024)
+
+#define AXIMON_IP0_TG      (AXIMON_BASE + 0x0030)
+#define AXIMON_IP0_TMR     (AXIMON_BASE + 0x0034)
+#define AXIMON_IP0_ID_CTL  (AXIMON_BASE + 0x0040)
+#define AXIMON_IP0_VPE     (AXIMON_BASE + 0x0044)
+#define AXIMON_IP0_ADDR    (AXIMON_BASE + 0x0048)
+#define AXIMON_IP0_ADDRMSK (AXIMON_BASE + 0x004C)
+#define AXIMON_IP0_DATA    (AXIMON_BASE + 0x0050)
+#define AXIMON_IP0_DATAMSK (AXIMON_BASE + 0x0060)
+#define AXIMON_IP0_CONSTR  (AXIMON_BASE + 0x0064) /*Ultra length size config*/
+
+#define AXIMON_IP1_TG      (AXIMON_BASE + 0x0070)
+#define AXIMON_IP1_TMR     (AXIMON_BASE + 0x0074)
+#define AXIMON_IP1_ID_CTL  (AXIMON_BASE + 0x0080)
+#define AXIMON_IP1_VPE     (AXIMON_BASE + 0x0084)
+#define AXIMON_IP1_ADDR    (AXIMON_BASE + 0x0088)
+#define AXIMON_IP1_ADDRMSK (AXIMON_BASE + 0x008C)
+#define AXIMON_IP1_DATA    (AXIMON_BASE + 0x0090)
+#define AXIMON_IP1_DATAMSK (AXIMON_BASE + 0x00A0)
+#define AXIMON_IP1_CONSTR  (AXIMON_BASE + 0x00A4) /*Ultra length size config*/
+
+
+#define AXIMON_TOT_BUS_CYC (AXIMON_BASE + 0x0100)
+#define AXIMON_INT_FRC_VAL (AXIMON_BASE + 0x0104) /*Record FRC when INT*/
+
+#define AXIMON_IP0_NON_OV_TRANS_NUM  (AXIMON_BASE + 0x0200)
+#define AXIMON_IP0_OV_TRANS_NUM      (AXIMON_BASE + 0x0204)
+#define AXIMON_IP0_NON_WGT_TRANS_CYC (AXIMON_BASE + 0x0208)
+#define AXIMON_IP0_WGT_TRANS_CYC     (AXIMON_BASE + 0x020C)
+#define AXIMON_IP0_MAX_TRANS_CYC     (AXIMON_BASE + 0x0210)
+#define AXIMON_IP0_MAX_OST_TRANS_NUM (AXIMON_BASE + 0x0214)
+#define AXIMON_IP0_CUR_OST_TRANS_NUM (AXIMON_BASE + 0x0218)
+
+#define AXIMON_IP0_SNAP_INFO0  (AXIMON_BASE + 0x0220)
+#define AXIMON_IP0_SNAP_INFO1  (AXIMON_BASE + 0x0224)
+#define AXIMON_IP0_SNAP_INFO2  (AXIMON_BASE + 0x0228)
+#define AXIMON_IP0_SNAP_INFO3  (AXIMON_BASE + 0x022C)
+#define AXIMON_IP0_SNAP_INFO4  (AXIMON_BASE + 0x0230)
+#define AXIMON_IP0_SNAP_INFO5  (AXIMON_BASE + 0x0234)
+#define AXIMON_IP0_SNAP_INFO6  (AXIMON_BASE + 0x0238)
+#define AXIMON_IP0_SNAP_INFO7  (AXIMON_BASE + 0x023C)
+#define AXIMON_IP0_SNAP_INFO8  (AXIMON_BASE + 0x0240)
+#define AXIMON_IP0_SNAP_INFO9  (AXIMON_BASE + 0x0244)
+#define AXIMON_IP0_SNAP_INFO10 (AXIMON_BASE + 0x0248)
+#define AXIMON_IP0_SNAP_INFO11 (AXIMON_BASE + 0x024C)
+#define AXIMON_IP0_SNAP_INFO12 (AXIMON_BASE + 0x0250) /*Snap VPE status*/
+
+#define AXIMON_IP1_NON_OV_TRANS_NUM  (AXIMON_BASE + 0x0280)
+#define AXIMON_IP1_OV_TRANS_NUM      (AXIMON_BASE + 0x0284)
+#define AXIMON_IP1_NON_WGT_TRANS_CYC (AXIMON_BASE + 0x0288)
+#define AXIMON_IP1_WGT_TRANS_CYC     (AXIMON_BASE + 0x028C)
+#define AXIMON_IP1_MAX_TRANS_CYC     (AXIMON_BASE + 0x0290)
+#define AXIMON_IP1_MAX_OST_TRANS_NUM (AXIMON_BASE + 0x0294)
+#define AXIMON_IP1_CUR_OST_TRANS_NUM (AXIMON_BASE + 0x0298)
+
+#define AXIMON_IP1_SNAP_INFO0   (AXIMON_BASE + 0x02A0)
+#define AXIMON_IP1_SNAP_INFO1   (AXIMON_BASE + 0x02A4)
+#define AXIMON_IP1_SNAP_INFO2   (AXIMON_BASE + 0x02A8)
+#define AXIMON_IP1_SNAP_INFO3   (AXIMON_BASE + 0x02AC)
+#define AXIMON_IP1_SNAP_INFO4   (AXIMON_BASE + 0x02B0)
+#define AXIMON_IP1_SNAP_INFO5   (AXIMON_BASE + 0x02B4)
+#define AXIMON_IP1_SNAP_INFO6   (AXIMON_BASE + 0x02B8)
+#define AXIMON_IP1_SNAP_INFO7   (AXIMON_BASE + 0x02BC)
+#define AXIMON_IP1_SNAP_INFO8   (AXIMON_BASE + 0x02C0)
+#define AXIMON_IP1_SNAP_INFO9   (AXIMON_BASE + 0x02C4)
+#define AXIMON_IP1_SNAP_INFO10  (AXIMON_BASE + 0x02C8)
+#define AXIMON_IP1_SNAP_INFO11  (AXIMON_BASE + 0x02CC)
+#define AXIMON_IP1_SNAP_INFO12  (AXIMON_BASE + 0x02D0) /*Snap VPE status*/
+
+/********************************Register Offset Field ********************************/
+#define AXIMON_CFG_OFFSET      (0x0040) /*AXIMON_IPx_TG*/
+#define AXIMON_INFO_OFFSET     (0x0080) /*AXIMON_IPx_SNAP_INFO0*/
+
+#define AXIMON_IP_TG_OFFSET                (0x0030) /*AXIMON_IP0_TG - AXIMON_BASE*/
+#define AXIMON_IP_TMR_OFFSET               (0x0034) /*AXIMON_IP0_TMR_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_ID_CTL_OFFSET            (0x0040) /*AXIMON_IP0_ID_CTL_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_VPE_OFFSET               (0x0044) /*AXIMON_IP0_VPE_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_ADDR_OFFSET              (0x0048) /*AXIMON_IP0_ADDR_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_ADDRMSK_OFFSET           (0x004C) /*AXIMON_IP0_ADDRMSK_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_DATA_OFFSET              (0x0050) /*AXIMON_IP0_DATA_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_DATAMSK_OFFSET           (0x0060) /*AXIMON_IP0_DATAMSK_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_CONSTR_OFFSET            (0x0064) /*Ultra length size config*/
+
+#define AXIMON_IP_NON_OV_TRANS_NUM_OFFSET  (0x0200) /*AXIMON_IP0_NON_OV_TRANS_NUM_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_OV_TRANS_NUM_OFFSET      (0x0204) /*AXIMON_IP0_OV_TRANS_NUM_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_NON_WGT_TRANS_CYC_OFFSET (0x0208) /*AXIMON_IP0_NON_WGT_TRANS_CYC_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_WGT_TRANS_CYC_OFFSET     (0x020C) /*AXIMON_IP0_WGT_TRANS_CYC_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_MAX_TRANS_CYC_OFFSET     (0x0210) /*AXIMON_IP0_MAX_TRANS_CYC_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_MAX_OST_TRANS_NUM_OFFSET (0x0214) /*AXIMON_IP0_MAX_OST_TRANS_NUM_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_CUR_OST_TRANS_NUM        (0x0218) /*AXIMON_IP0_CUR_OST_TRANS_NUM - AXIMON_BASE*/
+
+#define AXIMON_IP_SNAP_INFO0_OFFSET  (0x0220) /*AXIMON_IP0_SNAP_INFO0_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO1_OFFSET  (0x0224) /*AXIMON_IP0_SNAP_INFO1_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO2_OFFSET  (0x0228) /*AXIMON_IP0_SNAP_INFO2_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO3_OFFSET  (0x022C) /*AXIMON_IP0_SNAP_INFO3_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO4_OFFSET  (0x0230) /*AXIMON_IP0_SNAP_INFO4_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO5_OFFSET  (0x0234) /*AXIMON_IP0_SNAP_INFO5_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO6_OFFSET  (0x0238) /*AXIMON_IP0_SNAP_INFO6_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO7_OFFSET  (0x023C) /*AXIMON_IP0_SNAP_INFO7_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO8_OFFSET  (0x0240) /*AXIMON_IP0_SNAP_INFO8_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO9_OFFSET  (0x0244) /*AXIMON_IP0_SNAP_INFO9_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO10_OFFSET (0x0248) /*AXIMON_IP0_SNAP_INFO10_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO11_OFFSET (0x024C) /*AXIMON_IP0_SNAP_INFO11_OFFSET - AXIMON_BASE*/
+#define AXIMON_IP_SNAP_INFO12_OFFSET (0x0250) /*AXIMON_IP0_SNAP_INFO12_OFFSET - AXIMON_BASE*/
+
+/******************************** Default Value ********************************/
+#define AXIMON_COD_VERSION_DEFAULT   (0x20180315)
+
+/******************************** Bit Field & Mask ********************************/
+/*register:AXIMON_TST*/
+#define AXIMON_TST_SEQ_TRG_MODE_MASK      (0x1)
+#define AXIMON_TST_SEQ_TRG_MODE_SHIFT     (0)
+#define AXIMON_TST_SEQ_CHECK_MODE_MASK    (0x1) /*default:1*/
+#define AXIMON_TST_SEQ_CHECK_MODE_SHIFT   (1)
+#define AXIMON_TST_DISABLE_CG_MASK        (0x1)
+#define AXIMON_TST_DISABLE_CG_SHIFT       (2)
+#define AXIMON_TST_CLEAR_AT_BUSIDLE_MASK  (0x1) /*default:1*/  
+#define AXIMON_TST_CLEAR_AT_BUSIDLE_SHIFT (3)
+#define AXIMON_TST_SPEED_SIM_MASK         (0x1)
+#define AXIMON_TST_SPEED_SIM_SHIFT        (8)
+#define AXIMON_TST_CYC_CNT_WRAP_EN_MASK   (0x1) /*default:1*/
+#define AXIMON_TST_CYC_CNT_WRAP_EN_SHIFT  (9)
+#define AXIMON_TST_MON_OST_MODE_MASK      (0x1) /*defaule:0; defeature in Petrus*/
+#define AXIMON_TST_MON_OST_MODE_SHIFT     (12)
+#define AXIMON_TST_LYR_AXI_SEL_MASK       (0xF)
+#define AXIMON_TST_LYR_AXI_SEL_SHIFT      (16)
+
+/*register:AXIMON_STS*/
+#define AXIMON_STS_STAT0_MASK               (0x3)
+#define AXIMON_STS_STAT0_SHIFT              (0)
+#define AXIMON_STS_STAT1_MASK               (0x3)
+#define AXIMON_STS_STAT1_SHIFT              (4)
+#define AXIMON_STS_IP0_CUR_OVERFLOW_MASK    (0x1)
+#define AXIMON_STS_IP0_CUR_OVERFLOW_SHIFT   (8)
+#define AXIMON_STS_IP0_CUR_UNDERFLOW_MASK   (0x1)
+#define AXIMON_STS_IP0_CUR_UNDERFLOW_SHIFT  (9)
+#define AXIMON_STS_IP1_CUR_OVERFLOW_MASK    (0x1)
+#define AXIMON_STS_IP1_CUR_OVERFLOW_SHIFT   (10)
+#define AXIMON_STS_IP1_CUR_UNDERFLOW_MASK   (0x1)
+#define AXIMON_STS_IP1_CUR_UNDERFLOW_SHIFT  (11)
+#define AXIMON_STS_IP0_HIS_OVERFLOW_MASK    (0x1)
+#define AXIMON_STS_IP0_HIS_OVERFLOW_SHIFT   (12)
+#define AXIMON_STS_IP0_HIS_UNDERFLOW_MASK   (0x1)
+#define AXIMON_STS_IP0_HIS_UNDERFLOW_SHIFT  (13)
+#define AXIMON_STS_IP1_HIS_OVERFLOW_MASK    (0x1)
+#define AXIMON_STS_IP1_HIS_OVERFLOW_SHIFT   (14)
+#define AXIMON_STS_IP1_HIS_UNDERFLOW_MASK   (0x1)
+#define AXIMON_STS_IP1_HIS_UNDERFLOW_SHIFT  (15)
+#define AXIMON_STS_IP0_CUR_ID_MISS_MASK     (0x1)
+#define AXIMON_STS_IP0_CUR_ID_MISS_SHIFT    (16)
+#define AXIMON_STS_IP1_CUR_ID_MISS_MASK     (0x1)
+#define AXIMON_STS_IP1_CUR_ID_MISS_SHIFT    (17)
+#define AXIMON_STS_IP0_HIS_ID_MISS_MASK     (0x1)
+#define AXIMON_STS_IP0_HIS_ID_MISS_SHIFT    (18)
+#define AXIMON_STS_IP1_HIS_ID_MISS_MASK     (0x1)
+#define AXIMON_STS_IP1_HIS_ID_MISS_SHIFT    (19)
+#define AXIMON_STS_IP_TRG_INT_MASK          (0x1)
+#define AXIMON_STS_IP_TRG_INT_SHIFT         (20)
+#define AXIMON_STS_MON_REALENABLE_MASK      (0x1)
+#define AXIMON_STS_MON_REALENABLE_SHIFT     (31)
+
+/*register:AXIMON_INT*/
+#define AXIMON_INT_MASK   (0x1)
+#define AXIMON_INT_SHIFT  (0)
+
+/*register:AXIMON_INT_MSK*/
+#define AXIMON_INT_MSK_MASK  (0x1)
+#define AXIMON_INT_MSK_SHIFT (0)
+
+/*register:AXIMON_IPx_TG*/
+#define AXIMON_TG_MON_START_SEL_MASK     (0x1)
+#define AXIMON_TG_MON_START_SEL_SHIFT    (0)
+#define AXIMON_TG_MON_CNT_WRAP_EN_MASK   (0x1) /*default value is 1*/
+#define AXIMON_TG_MON_CNT_WRAP_EN_SHIFT  (4) 
+#define AXIMON_TG_MON_RWSEL_MASK         (0x1)
+#define AXIMON_TG_MON_RWSEL_SHIFT        (8)
+#define AXIMON_TG_MON_MODE_MASK          (0x1) /*default value is 1*/
+#define AXIMON_TG_MON_MODE_SHIFT         (9)
+#define AXIMON_TG_MON_ENABLE_MASK        (0x1) /*default value is 1*/
+#define AXIMON_TG_MON_ENABLE_SHIFT       (10)
+#define AXIMON_TG_TRG_MODE_MASK          (0x1) /*default value is 0*/
+#define AXIMON_TG_TRG_MODE_SHIFT         (11)
+#define AXIMON_TG_MON_ALL_MST_MASK       (0x1) /*default value is 1*/
+#define AXIMON_TG_MON_ALL_MST_SHIFT      (12)
+#define AXIMON_TG_SNAP_DATA_ENABLE_MASK  (0x1) /*default value is 0*/
+#define AXIMON_TG_SNAP_DATA_ENABLE_SHIFT (13)
+#define AXIMON_TG_MON_CNT_MASK           (0xFFFF)
+#define AXIMON_TG_MON_CNT_SHIFT          (16)
+
+/*register:AXIMON_IPx_TMR*/
+#define AXIMON_TMR_MON_TRG_CYC_MASK      (0xFFFF)
+#define AXIMON_TMR_MON_TRG_CYC_SHIFT     (0)
+
+/*register:AXIMON_IPx_ID_CTL*/
+#define AXIMON_ID_MON_MASTER_MASK       (0x1FFF)
+#define AXIMON_ID_MON_MASTER_SHIFT      (0)
+#define AXIMON_ID_MON_MASTER_MSK_MASK   (0x1FFF)
+#define AXIMON_ID_MON_MASTER_MSK_SHIFT  (16)
+
+/*register:AXIMON_IPx_VPE*/
+#define AXIMON_VPE_MON_VPE_MASK       (0x3FFF)
+#define AXIMON_VPE_MON_VPE_SHIFT      (0)
+#define AXIMON_VPE_MON_VPE_MSK_MASK   (0x3FFF)
+#define AXIMON_VPE_MON_VPE_MSK_SHIFT  (16)
+
+/*register:AXIMON_IPx_CONSTR*/
+#define AXIMON_CONSTR_MON_ULTRA_MASK       (0x3)
+#define AXIMON_CONSTR_MON_ULTRA_SHIFT      (0)
+#define AXIMON_CONSTR_MON_ULTRA_MSK_MASK   (0x3)
+#define AXIMON_CONSTR_MON_ULTRA_MSK_SHIFT  (4)
+#define AXIMON_CONSTR_MON_LEN_MASK         (0xF)
+#define AXIMON_CONSTR_MON_LEN_SHIFT        (8)
+#define AXIMON_CONSTR_MON_LEN_MSK_MASK     (0xF)
+#define AXIMON_CONSTR_MON_LEN_MSK_SHIFT    (12)
+#define AXIMON_CONSTR_MON_SIZE_MASK        (0X7)
+#define AXIMON_CONSTR_MON_SIZE_SHIFT       (16)
+#define AXIMON_CONSTR_MON_SIZE_MSK_MASK    (0X7)
+#define AXIMON_CONSTR_MON_SIZE_MSK_SHIFT   (20)
+
+/*register:AXIMON_IPx_SNAP_INFO0*/
+#define AXIMON_SNAP_INFO0_LEN_MASK    (0xF)
+#define AXIMON_SNAP_INFO0_LEN_SHIFT   (0)
+#define AXIMON_SNAP_INFO0_SIZE_MASK   (0x7)
+#define AXIMON_SNAP_INFO0_SIZE_SHIFT  (4)
+#define AXIMON_SNAP_INFO0_ULTRA_MASK  (0x3)
+#define AXIMON_SNAP_INFO0_ULTRA_SHIFT (7)
+#define AXIMON_SNAP_INFO0_BURST_MASK  (0x3)
+#define AXIMON_SNAP_INFO0_BURST_SHIFT (9)
+#define AXIMON_SNAP_INFO0_LOCK_MASK   (0x3)
+#define AXIMON_SNAP_INFO0_LOCK_SHIFT  (11)
+#define AXIMON_SNAP_INFO0_CACHE_MASK  (0xF)
+#define AXIMON_SNAP_INFO0_CACHE_SHIFT (13)
+#define AXIMON_SNAP_INFO0_PROT_MASK   (0x7)
+#define AXIMON_SNAP_INFO0_PROT_SHIFT  (17)
+#define AXIMON_SNAP_INFO0_RESP_MASK   (0x3)
+#define AXIMON_SNAP_INFO0_RESP_SHIFT  (20)
+
+/*register:AXIMON_IPx_SNAP_INFO1*/
+#define AXIMON_SNAP_INFO1_QID_MASK  (0xFFFF)
+#define AXIMON_SNAP_INFO1_QID_SHIFT (0)
+#define AXIMON_SNAP_INFO1_CNT_MASK  (0xFFFF)
+#define AXIMON_SNAP_INFO1_CNT_SHIFT (16)
+
+#define AXIMON_SNAP_INFO3_STRB0_MASK  (0xFFFF)
+#define AXIMON_SNAP_INFO3_STRB0_SHIFT (0)
+#define AXIMON_SNAP_INFO3_STRB1_MASK  (0xFFFF)
+#define AXIMON_SNAP_INFO3_STRB1_SHIFT (16)
+
+#define AXIMON_MATCH_NONE (0xFFFFFFFF)
+#define AXIMON_MATCH_ALL  (0)
+
+/*************************** Register in AO Domain  ****************************/
+#define AXIMON_MDMCU_LAYER_SELECT   (BASE_MADDR_MDPERIMISC + 0x504) //0xA0060504
+#define AXIMON_MDINFRA_LAYER_SELECT (BASE_MADDR_MDPERIMISC + 0x500)  //0xA0060500
+
+#define AXIMON_BUSMON_LAYER_SEL_MASK  (0xF)
+#define AXIMON_BUSMON_LAYER_SEL_SHIFT (0x0)
+
+#define AXIMON_CTL_START_MASK  (0x1)
+#define AXIMON_CTL_START_SHIFT (16)
+
+/* ************************************************************************************************
+* Below is for Bus recorder 
+************************************************************************************************ */
+/******************************** Register Field ********************************/
+#define BUSREC_REG_RECORDER_CTL           (AXIMON_BASE + 0x400U)
+#define BUSREC_REG_RECORDER_TEST          (AXIMON_BASE + 0x404U)
+#define BUSREC_REG_MON_REC_OBSRV_CTRL     (AXIMON_BASE + 0x408U)
+
+#define BUSREC_REG_IP0_BUFF_CNT           (AXIMON_BASE + 0x500U)
+#define BUSREC_REG_MON_IP0_GRP_CMD_STS    (AXIMON_BASE + 0x504U)
+
+#define BUSREC_REG_IP1_BUFF_CNT           (AXIMON_BASE + 0x700U)
+#define BUSREC_REG_MON_IP1_GRP_CMD_STS    (AXIMON_BASE + 0x704U)
+
+#if defined(MT6297) /*BusRec address has changed in Pertus*/
+#define BUSREC_REG_IP0_GRP1_ID_STS        (AXIMON_BASE + 0x510U)
+#define BUSREC_REG_IP0_GRP1_ADDR_STS      (AXIMON_BASE + 0x514U)
+#define BUSREC_REG_IP0_GRP1_ID_STS_(n)    (AXIMON_BASE + 0x510U + (n) * 0x8)
+#define BUSREC_REG_IP0_GRP1_ADDR_STS_(n)  (AXIMON_BASE + 0x514U + (n) * 0x8)
+
+#define BUSREC_REG_IP1_GRP1_ID_STS        (AXIMON_BASE + 0x710U)
+#define BUSREC_REG_IP1_GRP1_ADDR_STS      (AXIMON_BASE + 0x714U) 
+#define BUSREC_REG_IP1_GRP1_ID_STS_(n)    (AXIMON_BASE + 0x710U + (n) * 0x8)
+#define BUSREC_REG_IP1_GRP1_ADDR_STS_(n)  (AXIMON_BASE + 0x714U + (n) * 0x8)
+
+#else 
+#define BUSREC_REG_IP0_GRP1_ID_STS        (AXIMON_BASE + 0xB00U)
+#define BUSREC_REG_IP0_GRP1_ADDR_STS      (AXIMON_BASE + 0xB04U)
+#define BUSREC_REG_IP0_GRP1_ID_STS_(n)    (AXIMON_BASE + 0xB00U + (n) * 0x8)
+#define BUSREC_REG_IP0_GRP1_ADDR_STS_(n)  (AXIMON_BASE + 0xB04U + (n) * 0x8)
+
+#define BUSREC_REG_IP1_GRP1_ID_STS        (AXIMON_BASE + 0xC00U)
+#define BUSREC_REG_IP1_GRP1_ADDR_STS      (AXIMON_BASE + 0xC04U) 
+#define BUSREC_REG_IP1_GRP1_ID_STS_(n)    (AXIMON_BASE + 0xC00U + (n) * 0x8)
+#define BUSREC_REG_IP1_GRP1_ADDR_STS_(n)  (AXIMON_BASE + 0xC04U + (n) * 0x8)
+#endif
+
+#define BUSREC_REG_CURR_IP0_ID_STS        (AXIMON_BASE + 0x820U)
+#define BUSREC_REG_CURR_IP0_ADDR_STS      (AXIMON_BASE + 0x824U)
+#define BUSREC_REG_CURR_IP0_VPE_STS       (AXIMON_BASE + 0x828U)
+#define BUSREC_REG_CURR_IP0_CTRL_STS      (AXIMON_BASE + 0x82CU)
+
+#define BUSREC_MON_IP0_GRP_HIS_ID_STS     (AXIMON_BASE + 0x830U)
+#define BUSREC_MON_IP0_GRP_HIS_CMD_STS    (AXIMON_BASE + 0x834U)
+#define BUSREC_MON_IP0_GRP_HIS_ADDR_STS   (AXIMON_BASE + 0x838U)
+
+#define BUSREC_REG_CURR_IP1_ID_STS        (AXIMON_BASE + 0x850U)
+#define BUSREC_REG_CURR_IP1_ADDR_STS      (AXIMON_BASE + 0x854U)
+#define BUSREC_REG_CURR_IP1_VPE_STS       (AXIMON_BASE + 0x858U)
+#define BUSREC_REG_CURR_IP1_CTRL_STS      (AXIMON_BASE + 0x85CU)
+
+#define BUSREC_MON_IP1_GRP_HIS_ID_STS     (AXIMON_BASE + 0x860U)
+#define BUSREC_MON_IP1_GRP_HIS_CMD_STS    (AXIMON_BASE + 0x864U)
+#define BUSREC_MON_IP1_GRP_HIS_ADDR_STS   (AXIMON_BASE + 0x868U)
+
+#define BUSREC_REG_LOG_CTL                (AXIMON_BASE + 0x900U)
+#define BUSREC_REG_LOG_STS                (AXIMON_BASE + 0x904U)
+#define BUSREC_REG_LOG_SW_FORCE_OUT       (AXIMON_BASE + 0x908U)
+#define BUSREC_REG_LOG_CG_DIS             (AXIMON_BASE + 0x90CU)
+#define BUSREC_REG_LOG_TEST_CTL           (AXIMON_BASE + 0x910U)
+
+#define BUSREC_MON_IDLE_CTRL              (AXIMON_BASE + 0x918U)
+
+#define BUSREC_MON_CURR_IP0_CMD_STS       (AXIMON_BASE + 0xA00U)
+#define BUSREC_MON_CURR_IP1_CMD_STS       (AXIMON_BASE + 0xA04U)
+
+#define BUSREC_MON_MON2GCR_CTL0           (AXIMON_BASE + 0xA10U)
+#define BUSREC_MON_MON2GCR_CTL1           (AXIMON_BASE + 0xA14U)
+#define BUSREC_MON_MON2GCR_CTL2           (AXIMON_BASE + 0xA18U)
+
+/*NOTE:this register not been defined in MT6297*/
+#define BUSREC_MON_SCAN_COV_DUM           (AXIMON_BASE + 0xF20U)
+
+/******************************** Bit Field & Mask ********************************/
+/*register:BUSREC_REG_RECORDER_CTL*/
+#define BUSREC_CTL_TEST_MODE_MASK     (0x1)
+#define BUSREC_CTL_TEST_MODE_SHIFT    (2)
+#define BUSREC_CTL_GATE_AR_MASK       (0x1)
+#define BUSREC_CTL_GATE_AR_SHIFT      (4)
+#define BUSREC_CTL_GATE_AW_MASK       (0x1)
+#define BUSREC_CTL_GATE_AW_SHIFT      (5)
+#define BUSREC_CTL_GATE_R_RESP_MASK   (0x1)
+#define BUSREC_CTL_GATE_R_RESP_SHIFT  (6)
+#define BUSREC_CTL_GATE_B_RESP_MASK   (0x1)
+#define BUSREC_CTL_GATE_B_RESP_SHIFT  (7)
+#define BUSREC_CTL_GATE_W_RESP_MASK   (0x1)
+#define BUSREC_CTL_GATE_W_RESP_SHIFT  (8)
+
+/*register:BUSREC_REG_RECORDER_TEST*/
+#define BUSREC_TEST_TRANS_ADD_MASK      (0x1)
+#define BUSREC_TEST_TRANS_ADD_SHIFT     (0)
+#define BUSREC_TEST_TRANS_ADD_ID_MASK   (0xFF)
+#define BUSREC_TEST_TRANS_ADD_ID_SHIFT  (8)
+#define BUSREC_TEST_TRANS_SUB_MASK      (0x1)
+#define BUSREC_TEST_TRANS_SUB_SHIFT     (16)
+#define BUSREC_TEST_TRANS_SUB_ID_MASK   (0xFF)
+#define BUSREC_TEST_TRANS_SUB_ID_SHIFT  (24)
+
+/*register:BUSREC_REG_MON_REC_OBSRV_CTRL*/
+#define BUSREC_IP0_MON_HIS_FILTER_EN_MASK   (0x1)
+#define BUSREC_IP0_MON_HIS_FILTER_EN_SHIFT  (0)
+#define BUSREC_IP0_HIS_REC_ENTRY_SEL_MASK   (0x7)
+#define BUSREC_IP0_HIS_REC_ENTRY_SEL_SHIFT  (4)
+#define BUSREC_IP0_REC_ENTRY_SEL_MASK       (0x3F) /*petrus busrec depth is 64*/
+#define BUSREC_IP0_REC_ENTRY_SEL_SHIFT      (8)
+#define BUSREC_IP1_MON_HIS_FILTER_EN_MASK   (0x1)
+#define BUSREC_IP1_MON_HIS_FILTER_EN_SHIFT  (16)
+#define BUSREC_IP1_HIS_REC_ENTRY_SEL_MASK   (0x7)
+#define BUSREC_IP1_HIS_REC_ENTRY_SEL_SHIFT  (20)
+#define BUSREC_IP1_REC_ENTRY_SEL_MASK       (0x3F)/*petrus busrec depth is 64*/
+#define BUSREC_IP1_REC_ENTRY_SEL_SHIFT      (24)
+#define BUSREC_MON_HIS_REC_EN_MASK          (0x1)
+#define BUSREC_MON_HIS_REC_EN_SHIFT         (31)
+
+/*register:BUSREC_REG_MON_IPx_GRP_CMD_STS*/
+#define BUSREC_GRP_CMD_AXLEN_MASK     (0XF)
+#define BUSREC_GRP_CMD_AXLEN_SHIFT    (0)
+#define BUSREC_GRP_CMD_AXSIZE_MASK    (0X7)
+#define BUSREC_GRP_CMD_AXSIZE_SHIFT   (4)
+#define BUSREC_GRP_CMD_AXULTRA_MASK   (0X3)
+#define BUSREC_GRP_CMD_AXULTRA_SHIFT  (7)
+#define BUSREC_GRP_CMD_AXBURST_MASK   (0X3)
+#define BUSREC_GRP_CMD_AXBURST_SHIFT  (9)
+#define BUSREC_GRP_CMD_AXLOCK_MASK    (0X3)
+#define BUSREC_GRP_CMD_AXLOCK_SHIFT   (11)
+#define BUSREC_GRP_CMD_AXCACHE_MASK   (0XF)
+#define BUSREC_GRP_CMD_AXCACHE_SHIFT  (13)
+#define BUSREC_GRP_CMD_AXPORT_MASK    (0X7)
+#define BUSREC_GRP_CMD_AXPORT_SHIFT   (17)
+#define BUSREC_GRP_CMD_AXMATCH_MASK   (0X1)
+#define BUSREC_GRP_CMD_AXMATCH_SHIFT  (20)
+
+/*register:BUSREC_MON_IP1_GRP_HIS_ID_STS*/
+#define BUSREC_HIS_ID_AXID_MASK    (0XFFFFF)
+#define BUSREC_HIS_ID_AXID_SHIFT   (0)
+#define BUSREC_HIS_ID_AXVPE_MASK   (0XFFFFF)
+#define BUSREC_HIS_ID_AXVPE_SHIFT  (16)
+
+/*register:BUSREC_MON_IPx_GRP_HIS_CMD_STS*/
+#define BUSREC_HIS_CMD_AXLEN_MASK     (0XF)
+#define BUSREC_HIS_CMD_AXLEN_SHIFT    (0)
+#define BUSREC_HIS_CMD_AXSIZE_MASK    (0X7)
+#define BUSREC_HIS_CMD_AXSIZE_SHIFT   (4)
+#define BUSREC_HIS_CMD_AXULTRA_MASK   (0X3)
+#define BUSREC_HIS_CMD_AXULTRA_SHIFT  (7)
+#define BUSREC_HIS_CMD_AXBURST_MASK   (0X3)
+#define BUSREC_HIS_CMD_AXBURST_SHIFT  (9)
+#define BUSREC_HIS_CMD_AXLOCK_MASK    (0X3)
+#define BUSREC_HIS_CMD_AXLOCK_SHIFT   (11)
+#define BUSREC_HIS_CMD_AXCACHE_MASK   (0XF)
+#define BUSREC_HIS_CMD_AXCACHE_SHIFT  (13)
+#define BUSREC_HIS_CMD_AXPORT_MASK    (0X7)
+#define BUSREC_HIS_CMD_AXPORT_SHIFT   (17)	
+#define BUSREC_HIS_CMD_AXMATCH_MASK   (0X1)
+#define BUSREC_HIS_CMD_AXMATCH_SHIFT  (20)	
+
+/*register:BUSREC_MON_IDLE_CTRL*/
+#define BUSREC_MON_FORCE_BUSY_MASK    (0x1)
+#define BUSREC_MON_FORCE_BUSY_SHIFT   (0)
+#define BUSREC_MON_BUS_IDLE_MSK_MASK  (0x1)
+#define BUSREC_MON_BUS_IDLE_MSK_SHIFT (16)
+
+/*register:BUSREC_MON_MON2GCR_CTL0*/
+#define BUSREC_MON2GCR_CNT0_MASK   (0x1F)
+#define BUSREC_MON2GCR_CNT0_SHIFT  (0)
+#define BUSREC_MON2GCR_CNT1_MASK   (0x1F)
+#define BUSREC_MON2GCR_CNT1_SHIFT  (8)
+#define BUSREC_MON2GCR_CNT2_MASK   (0x1F)
+#define BUSREC_MON2GCR_CNT2_SHIFT  (16)
+
+/*register:BUSREC_MON_MON2GCR_CTL2*/
+#define BUSREC_MON2GCR_STAGE_SEL_MASK   (0x1)
+#define BUSREC_MON2GCR_STAGE_SEL_SHIFT  (0)
+
+#define BUSREC_LOG_EN_MASK              (0x1)
+#define BUSREC_LOG_EN_SHIFT             (0)
+#define BUSREC_LOG_MODE_SEL_MASK        (0x1)
+#define BUSREC_LOG_MODE_SEL_SHIFT       (4)
+#define BUSREC_LOG_DATA_MODE_SEL_MASK   (0x1)
+#define BUSREC_LOG_DATA_MODE_SEL_SHIFT  (12)
+#define BUSREC_LOG_IP0_ATID_MASK        (0x7F)
+#define BUSREC_LOG_IP0_ATID_SHIFT       (16)
+#define BUSREC_LOG_IP1_ATID_MASK        (0x7F)
+#define BUSREC_LOG_IP1_ATID_SHIFT       (24)
+#define BUSREC_LOG_ACLK_CG_DIS_MASK     (0x3)
+#define BUSREC_LOG_ACLK_CG_DIS_SHIFT    (0)
+#define BUSREC_LOG_TEST_CTL_MASK        (0x3)
+#define BUSREC_LOG_TEST_CTL_SHIFT       (0)
+
+/******************************** GCR Register Field ********************************/
+#define MDMCU_BUSMON_CNT0    (BASE_ADDR_GCR_COUNTER + 0xc0)
+#define MDMCU_BUSMON_CNT1    (BASE_ADDR_GCR_COUNTER + 0xc4)
+#define MDMCU_BUSMON_CNT2    (BASE_ADDR_GCR_COUNTER + 0xc8)
+#define MDMCU_BUSMON_CNT3    (BASE_ADDR_GCR_COUNTER + 0xcc)
+#define MDMCU_BUSMON_CNT4    (BASE_ADDR_GCR_COUNTER + 0xd0)
+#define MDMCU_BUSMON_CNT5    (BASE_ADDR_GCR_COUNTER + 0xd4)
+
+#define MDINFRA_BUSMON_CNT0  (BASE_ADDR_GCR_COUNTER + 0xe0)
+#define MDINFRA_BUSMON_CNT1  (BASE_ADDR_GCR_COUNTER + 0xe4)
+#define MDINFRA_BUSMON_CNT2  (BASE_ADDR_GCR_COUNTER + 0xe8)
+#define MDINFRA_BUSMON_CNT3  (BASE_ADDR_GCR_COUNTER + 0xec)
+#define MDINFRA_BUSMON_CNT4  (BASE_ADDR_GCR_COUNTER + 0xf0)
+#define MDINFRA_BUSMON_CNT5  (BASE_ADDR_GCR_COUNTER + 0xf4)
+
+#define MD_BUSMON_CNT_OFFSET (MDINFRA_BUSMON_CNT0 -MDMCU_BUSMON_CNT0)
+
+#endif /* end of __BUSMON_REG_H__ */
+
diff --git a/mcu/interface/driver/devdrv/busmon/md97p/drv_busmon.h b/mcu/interface/driver/devdrv/busmon/md97p/drv_busmon.h
new file mode 100644
index 0000000..431f147
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmon/md97p/drv_busmon.h
@@ -0,0 +1,1353 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   drv_busmon.h
+ *
+ * Project:
+ * --------
+ *   MOLY
+ *
+ * Description:
+ * ------------
+ *   Header file for Bus monitor control
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 03 14 2019 hedy.han
+ * [MOLY00345970] [VMOLY.TRUNK]
+ * [VMOLY TRUNK][Gen97 Busmon][New Feature] Porting address logger driver and porting Petrus busmon New feature.
+ *
+ * 12 30 2018 hedy.han
+ * [MOLY00375594] [VMOLY.EVB.SEPT.DEV]
+ * [gen97 busmon] fix building warning
+ *
+ * 12 29 2018 hedy.han
+ * [MOLY00375594] [VMOLY.EVB.SEPT.DEV]
+ * [Gen97 Busmon] Fix enum (Busmon to GCR select value)
+ *
+ * 11 07 2018 hedy.han
+ * [MOLY00345970] [VMOLY.TRUNK]
+ * [Gen97 Busmon] Change IRQ group from hardcode to macro define.
+ *
+ * 09 22 2018 hedy.han
+ * [MOLY00345970] [VMOLY.TRUNK]
+ * [New Feature]Gen97 busmon driver.
+ *
+ * 08 06 2018 hedy.han
+ * [MOLY00344260] [Gen95 Busmon][LR13.R0.MP] Remove assert and backup address logger in dormant backup.
+ * [Gen95Busmon][LR13.R0.MP][Delete Assert] delete assert as customer's ask; backup address logger register.
+ *
+ * 04 26 2018 hedy.han
+ * [MOLY00322462] [UMOLYE][HISR] Remove some HISRs and move them to related LISRs
+ * [Busmon Hisr]Delete Busmon HISR.
+ *
+ * 03 29 2018 hedy.han
+ * [MOLY00316943] [New feature][Address logger] Add address logger enable and disable function.
+ * [New feature][Address logger] add address logger enable and disable function.
+ *
+ * 03 12 2018 hedy.han
+ * [MOLY00312512] [UMOLYE TRUNK][GEN95][BUSMON][New Feature][AT command]
+ *
+ * 07 04 2017 liang.yan
+ * [MOLY00244793] [MT6295M]Bus monitor driver build error call for check in
+ * 	.Patch busmon change to MT6295 MP2 branch
+ *
+ * 06 09 2017 liang.yan
+ * [MOLY00244888] [ZION]Bus monitor driver build error call for check in
+ * 	
+ * 	[LR12A.MP1.5.RDIT]Merge ZION project defining
+ *
+ * 06 06 2017 liang.yan
+ * [MOLY00248491] [MT6763][Gen93][System Service][MDCIRQ] Debugging code for GPT IRQ not entered issue
+ * 	[LR12A]Rollback the bus monitor configuration for MDCIRQ issue
+ *
+ * 05 15 2017 yen-chun.liu
+ * [MOLY00248491] [MT6763][Gen93][System Service][MDCIRQ] Debugging code for GPT IRQ not entered issue
+ * busmon debug code for MDCIRQ.
+ *
+ * 05 10 2017 liang.yan
+ * [MOLY00242841] [SE2 Internal CR][Bianco][N1] Kernel API Dump,0,0,99,/data/core/,1,,EMI MPU,Fri Apr 14 23:02:16 CST 2017 @ 2017-04-14 23:02:16.77644,1,2372648
+ * 	Remove busmon debug code for MPU violation in TRUNK
+ *
+ * 05 05 2017 liang.yan
+ * [MOLY00242841] [SE2 Internal CR][Bianco][N1] Kernel API Dump,0,0,99,/data/core/,1,,EMI MPU,Fri Apr 14 23:02:16 CST 2017 @ 2017-04-14 23:02:16.77644,1,2372648
+ * 	[TRUNK]Add MDINFRA busmon debug for mpu violation
+ *
+ * 05 03 2017 liang.yan
+ * [MOLY00242841] [SE2 Internal CR][Bianco][N1] Kernel API Dump,0,0,99,/data/core/,1,,EMI MPU,Fri Apr 14 23:02:16 CST 2017 @ 2017-04-14 23:02:16.77644,1,2372648
+ * 	[TRUNK]bus monitor mo debug for MPU violation
+ *
+ * 05 02 2017 liang.yan
+ * [MOLY00244750] [System Service][MDGDMA][MT6763] Update GDMA debug log for DDL fail.
+ * 	Change MDMCU/MDINFRA busmon parking layer to default point
+ *
+ * 04 25 2017 liang.yan
+ * [MOLY00245013] [BIANCO][MT6763][RDIT][PHONE][Overnight][HQ][MTBF][Lab][Ericsson]Externel (EE) [Others] MD long time no response
+ * 	[TRUNK]Change MDMCU busmon parking layer to MCU2EMI
+ *
+ * 04 14 2017 liang.yan
+ * [MOLY00241937] [VTF_SMT][MT6293][SMT][Bianco][MT6763]Externel (EE),0,0,99,/data/core/,1,modem,md1:(USIP0_USIP0),[ASSERT] file:md32/usip/common/service/loader/src/loader.c line:1086 when overnight cal(1/601times)
+ * 	[UMOLYA]Change mdinfra busmon parking layer after MI
+ *
+ * 03 30 2017 liang.yan
+ * [MOLY00238383] [Change Feature][BUSMON]Change MDMCU busmon parking to PWB
+ *
+ * 03 15 2017 liang.yan
+ * [MOLY00235447] [Change Feature][SS][BUSMON]Add busmon profiling API for user
+ *
+ * 03 02 2017 liang.yan
+ * [MOLY00232074] [Change Feature][BIANCO]Adding busmon monitor MO port Latency feature
+ *
+ * 02 13 2017 i-chun.liu
+ * [MOLY00228094] [Bianco][Bringup] DEV patch back
+ * merge back busmon MO port setting.
+ *
+ * 02 03 2017 i-chun.liu
+ * [MOLY00227643] [Bianco Bring-up][Gen93/INIT/BUSMON] Change MDMCU BUSMON to MO port at init stage.
+ * Change MDMCU BUSMON to MO port at init stage.
+ *
+ * 08 05 2016 liang.yan
+ * [MOLY00195782] [Change Feature]93 busmon driver update
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * workaround for CIRQ driver.
+ *
+ * 03 30 2016 i-chun.liu
+ * [MOLY00171939] 93 Busmon check in
+ * busmon check in .
+ *
+ * 10 07 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * Update bus monitor IRQ code for ELBRUS.
+ *
+ * 08 17 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * bus monitor update for ELBRUS.
+ *
+ * 06 09 2015 i-chun.liu
+ * [MOLY00119728] JADE bring up call for check in  (MDCIRQ and Bus monitor )
+ * JADE PCORE BUSMON.
+ *
+ * 04 07 2015 i-chun.liu
+ * [MOLY00106215] TK6291 bus monitor driver update
+ * pcore busmonitor driver update to prevent modis build fail.
+ *
+ * 04 07 2015 i-chun.liu
+ * [MOLY00106215] TK6291 bus monitor driver update
+ * Pcore bus monitor driver update.
+ *
+ * 07 29 2014 brian.chiang
+ * [MOLY00070757] busmon drvier update
+ * Bus monitor driver enhancement
+ *
+ * 04 23 2014 brian.chiang
+ * [MOLY00063514] 6595 busmon driver
+ * 6595 busmon deriver porting
+ *
+ * 02 21 2014 i-chun.liu
+ * [MOLY00057041] Solve MT6290 bus monitor driver API bug
+ * bus monitor bug
+ *
+ * 05 31 2013 vend_hsientang.lee
+ * [MOLY00024631] Update busmon driver
+ * Use non-post-write to get accurate counter
+ *
+ * 03 29 2013 vend_hsientang.lee
+ * [MOLY00013013] Add Busmon driver
+ *
+ ****************************************************************************/
+
+#ifndef __DRV_BUSMON_H__
+#define __DRV_BUSMON_H__
+
+#if defined(__ASSEMBLER__)
+.macro BUSMON_PRE_CONFIG
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+.endm BUSMON_PRE_CONFIG
+#else
+
+#include "kal_public_defs.h"
+#include "irqid.h"
+#include "busmon_reg.h"
+
+/*******************************************************************************
+ * MACRO DEFINE
+*******************************************************************************/
+#define MO_LATENCY_RECORD_NUM 0x20
+#define AXIMON_TOTAL_AT_CONFIG 0x20
+#define HIS_BUF_ENTRY 0x8
+#define AXIMON_GCR_NUM 0x6
+
+/*
+*  Define 15us which is the max latency time from mcu to apb read access
+*  MT6297: Busmon clock is fixed at 208M for MDMCU busmon and MDINFRA busmon.
+*  Petrus : Busmon clock is fixed at 216.7M for MDMCU busmon and MDINFRA busmon.  
+*/
+#if defined(MT6297)
+#define MCU2REG_LIMITED_LATENCY_CNT_MDMCU 0xC30
+#define MCU2REG_LIMITED_LATENCY_CNT_MDINFRA 0xC30	
+#else
+#define MCU2REG_LIMITED_LATENCY_CNT_MDMCU 0xCB2
+#define MCU2REG_LIMITED_LATENCY_CNT_MDINFRA 0xCB2
+#endif
+
+#define MDMCUSYS_BUSMON_IRQID MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define MDPERISYS_BUSMON_IRQID MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define MD_BUSMON_IRQID_NUM 2
+
+/* Register field manipulation macro */
+#define EXTRACT_REG_FIELD_VAL(field_val, field_name)      (((field_val) >> (field_name##_SHIFT)) & (field_name##_MASK))
+#define EXPAND_REG_FIELD_VAL(field_val, field_name)       (((field_val) & (field_name##_MASK)) << (field_name##_SHIFT))
+#define CLEAR_REG_FIELD(reg_val, field_name)              ((reg_val) & (~((field_name##_MASK) << (field_name##_SHIFT))))
+#define SET_REG_FIELD_VAL(reg_val, field_val, field_name) (CLEAR_REG_FIELD(reg_val, field_name) | EXPAND_REG_FIELD_VAL(field_val, field_name))
+
+/*******************************************************************************
+ * Below for bus monitor
+ *******************************************************************************/
+typedef enum {
+    MONID_MDMCU_AXIMON = 0, 
+    MONID_MDINFRA_AXIMON,    
+    MONID_MDAXI_MAX
+} drv_aximon_monid_t;
+
+/*Busmon layer select id*/
+typedef enum {
+    /*MD MCU*/
+    BUSMON_BUSID_MDMCUSYS_START = 0UL,    
+    BUSMON_BUSID_MDMCU_MM = BUSMON_BUSID_MDMCUSYS_START,
+    BUSMON_BUSID_MDMCU_MO = 1,
+    BUSMON_BUSID_AF_MO_PWB = 2,/*default value*/
+    BUSMON_BUSID_AF_MO_PWB_MI = 3,
+    BUSMON_BUSID_MDMCU2EMI_AF_MI_BF_GALS = 4,
+    BUSMON_BUSID_RAKE_BRP_BRAM_INR = 5,
+    BUSMON_BUSID_FE_MDINFRA_BF_SI = 6,
+    BUSMON_BUSID_MDMCU2MCORE_BF_IDDWZ = 7,
+    BUSMON_BUSID_MDMCU2AP = 8,
+    BUSMON_BUSID_AF_MM_PWB = 9,
+    BUSMON_BUSID_USIP = 10,
+
+    #if defined (MT6297)
+    BUSMON_BUSID_MDMCUSYS_END = 11,
+    /*MD INFRA*/
+    BUSMON_BUSID_MDINFRA_START = 0,   
+    BUSMON_BUSID_MDINFRA_EMI_A = BUSMON_BUSID_MDINFRA_START,
+    BUSMON_BUSID_MDINFRA_EMI_B = 1,/*default value*/
+    #else
+    BUSMON_BUSID_USIP2L1APB = 11,
+    BUSMON_BUSID_MDMCUSYS_END = 12,
+    /*MD INFRA*/
+    BUSMON_BUSID_MDINFRA_START = 0, 
+    /*NOTE:no layer0 here.*/
+    BUSMON_BUSID_MDINFRA_EMI = 1,/*default value*/
+    #endif
+    
+    BUSMON_BUSID_MDINFRA_MDMCU = 2, 
+    BUSMON_BUSID_MDINFRA_AP = 3,
+    BUSMON_BUSID_MDINFRA_END = 4
+} busmon_busid_t;  
+
+typedef enum {
+    BUSMON_MON_DISABLE = 0,
+    BUSMON_MON_ENABLE
+} drv_busmon_active_t;
+
+typedef enum {
+    BUSMON_MON_STATE_INACTIVE = 0,
+    BUSMON_MON_STATE_ACTIVE
+} drv_busmon_mon_state_t;
+
+typedef enum {
+    BUSMON_IP0 = 0,
+    BUSMON_IP1,
+    BUSMON_IP_MAX
+} drv_busmon_ip_t;
+
+typedef enum {
+    IP_IDLE = 0,
+    IP_REAL_ENABLE,
+    IP_STOP
+} busmon_ip_status_t;
+
+typedef enum {
+    AXIMON_RWSEL_WRITE = 0,
+    AXIMON_RWSEL_READ,
+    AXIMON_RWSEL_MAX
+} drv_aximon_rwsel_t;
+
+typedef enum {
+    START_ORDER_IP0_IP1= 0,
+    STOP_ORDER_IP0_IP1,
+    ORDER_IP0_IP1_MAX  
+} drv_busmon_mon_seq_check_mode_t;
+
+typedef enum {
+    BUSMON_TG_MON_MODE_SNAP = 0,
+    BUSMON_TG_MON_MODE_MONITOR,
+    BUSMON_TG_MON_MODE_MAX
+} drv_busmon_tg_mon_mode_t;
+
+/*Busmon Trigger Mode*/
+typedef enum {
+    BUSMON_TRG_ADDRDATA,
+    BUSMON_TRG_CYCLE,
+    BUSMON_TRG_MAX
+} drv_busmon_trg_mode_t;
+
+typedef enum {
+    MON_VPE_0 = 0x10,   
+    MON_VPE_1 = 0x20,
+    MON_VPE_2 = 0x30,
+    MON_VPE_3 = 0x50,
+    MON_VPE_4 = 0x60,
+    MON_VPE_5 = 0x70,
+    MON_VPE_6 = 0x90,
+    MON_VPE_7 = 0xa0,
+    MON_VPE_8 = 0xb0,
+    MON_VPE_9 = 0xd0,
+    MON_VPE_10 = 0xe0,
+    MON_VPE_11 = 0xf0,
+    MON_SFU_CORE0 = 0x103 ,
+    MON_SFU_CORE1 = 0x143 ,
+    MON_SFU_CORE2 = 0x183 ,
+    MON_SFU_CORE3 = 0x1C3 ,
+    MON_SPU = 0x203,
+    MON_IOCU0_GDMA = 0x182,
+    MON_SHAOLIN_L2 = 0x249
+} busmon_vpe_id_t;
+
+typedef enum {
+    /*monitor mode config command*/
+    MONITOR_START = 0,
+    MCR0 = 0,
+    MCR1 = 1,
+    MCW0 = 2,
+    MCW1 = 3,
+    MIR0 = 4,
+    MIR1 = 5,
+    MIW0 = 6,
+    MIW1 = 7,
+    MONITOR_END = 7,
+    
+    /*latency mode config command*/
+    LATENCY_START = 16,
+    LCR0G = 16,
+    LCR1G = 17,
+    LCW0G = 18,
+    LCW1G= 19,
+    LCR0S = 20,
+    LCR1S = 21,
+    LCW0S = 22,
+    LCW1S = 23,
+    LIR0G = 24,
+    LIR1G = 25,
+    LIW0G = 26,
+    LIW1G= 27,
+    LIR0S = 28,
+    LIR1S = 29,
+    LIW0S = 30,
+    LIW1S = 31,
+    LATENCY_END = 31,
+
+    
+    /*invalid address mode config command*/
+    ADDR_START = 48,
+    ACR0G = 48,
+    ACR1G = 49,
+    ACW0G = 50,
+    ACW1G= 51,
+    ACR0S = 52,
+    ACR1S = 53,
+    ACW0S = 54,
+    ACW1S = 55,
+    AIR0G = 56,
+    AIR1G = 57,
+    AIW0G = 58,
+    AIW1G= 59,
+    AIR0S = 60,
+    AIR1S = 61,
+    AIW0S = 62,
+    AIW1S = 63,
+    ADDR_END = 63,
+
+    MON_CONFIG_START = 100,
+    STARTC = 100, /*start mdmcu busmon*/
+    STOPC = 101,  /*stop mdmcu busmon*/
+    STARTI = 102, /*start mdinfra busmon*/
+    STOPI = 103,  /*stop mdinfra busmon*/
+
+    MDMCU_HIS_BUF = 130,/*get mdmcu history buffer info*/
+    MDINFRA_HIS_BUF = 140,/*get mdinfra history buffer info*/
+
+    TRACE_CTL= 150, /*enable/disable busmon ELT trace*/
+
+    MDMCU_HIS_FILTER_CTL=160,/*enable/disable MDMCU busmon history buffer filter*/
+    MDINFRA_HIS_FILTER_CTL=170,/*enable/disable MDINFRA busmon history buffer filter*/
+   
+    MON_CONFIG_END = 170,
+
+    ADDRLOG_START = 200,
+    ENADDRLOG = 200, /*enable address logger*/
+    DISADDRLOG = 201,/*disable address logger*/
+    ADDRLOG_SWITCH_MOD = 210,/*switch address logger mode*/
+    ADDRLOG_END = 210,
+} busmon_at_config_t;
+
+typedef enum {
+    DISABLE_CTL = 0x0,
+    IP0_NON_OV_TRANS_NUM = 0x1,
+    IP0_OV_TRANS_NUM = 0x2,
+    IP0_NON_WGT_TRANS_CYC = 0x3,
+    IP0_WGT_TRANS_CYC = 0x4,
+    IP0_MAX_TRANS_CYC = 0x5,
+    IP0_MAX_OST_TRANS_NUM = 0x6,
+    IP0_CUR_OST_TRANS_NUM = 0x7,
+    IP0_TOTAL_TRANS_NUM = 0x8,
+    IP0_OST_TRANS_NUM = 0x9,
+    
+    IP1_NON_OV_TRANS_NUM = 0x11,
+    IP1_OV_TRANS_NUM = 0x12,
+    IP1_NON_WGT_TRANS_CYC = 0x13,
+    IP1_WGT_TRANS_CYC = 0x14,
+    IP1_MAX_TRANS_CYC = 0x15,
+    IP1_MAX_OST_TRANS_NUM = 0x16,
+    IP1_CUR_OST_TRANS_NUM = 0x17,
+    IP1_TOTAL_TRANS_NUM = 0x18,
+    IP1_OST_TRANS_NUM = 0x19
+}busmon_mon2gcr_sel;
+
+/*************************************************************************************************
+* Below is for Bus recorder 
+*************************************************************************************************/
+typedef enum {
+    BUSREC_MODE_NORMAL = 0,
+    BUSREC_MODE_TEST,
+} BUSREC_MODE;
+
+typedef enum {
+    BUSREC_GATE_NONE = 0,
+    BUSREC_GATE_RESP,
+    BUSREC_GATE_CMD,
+    BUSREC_GATE_ALL,
+} BUSREC_GATE;
+
+typedef enum {
+    BUSREC_HIS_FILTER_EN_DISABLE= 0,/*disable bus recorder history filter*/
+    BUSREC_HIS_FILTER_EN_ENABLE,/*enable bus recorder history filter*/
+} BUSREC_HIS_FILTER_EN;
+
+typedef enum {
+    BUSREC_HIS_REC_EN_DISABLE= 0,/*disable bus recorder history recorder*/
+    BUSREC_HIS_REC_EN_ENABLE,/*enable bus recorder history recorder*/
+} BUSREC_HIS_REC_EN;
+
+typedef enum {
+    BUSREC_MON_FORCE_BUSY_DISABLE = 0,/*disable bus monitor force busy*/
+    BUSREC_MON_FORCE_BUSY_ENABLE,/*enable bus monitor force busy*/
+} BUSREC_FORCE_BUSY;                      
+
+typedef enum {
+    BUSREC_MON_BUS_IDLE_MSK_DISABLE = 0,/*do not mask bus idle signal*/
+    BUSREC_MON_BUS_IDLE_MSK_ENABLE,/*mask bus idle signal*/
+} BUSREC_BUS_IDLE_MSK;  
+
+/*******************************************************************************
+ * Define data structures.
+ *******************************************************************************/
+typedef struct {
+    BUSREC_HIS_FILTER_EN mon_his_filter_en; /*enable/disable history filter*/
+    kal_uint32 his_rec_entry_sel;/*history command entry select (8 history entry for each IP)*/
+    kal_uint32 rec_entry_sel;    /*current command entry select (32 current entry for each IP)*/
+    } drv_busrec_rec_obsrv_ip_ctrl;            
+
+typedef struct {
+    BUSREC_FORCE_BUSY mon_force_busy;/*enable/disable force busmon busy*/
+    BUSREC_BUS_IDLE_MSK mon_bus_idle_msk;/*enable/disable bus idle mask*/
+} drv_busrec_idle_ctrl;	
+
+/*AXImon IP configuration of Monitor mode*/
+typedef struct {
+    kal_bool start_sel;        /*0-axvalid; 1-axvalid&axready*/
+    kal_bool cnt_wrap_en_t;
+    drv_aximon_rwsel_t rwsel;
+    kal_bool all_master_enable;/*any transaction ID*/
+    kal_uint32 master_id;
+    kal_uint32 master_id_mask;
+    kal_uint32 vpe_id;    /*specific VPE ID*/
+    kal_uint32 vpe_id_mask;  
+    kal_uint32 ultra;     /*specific ULTRA*/
+    kal_uint32 ultra_mask;    
+    kal_uint32 addr;      /*address: only used in snap mode*/
+    kal_uint32 addr_mask; /*address mask, 0: check, 1: ignore. only used in snap mode*/
+    kal_uint32 axlen;
+    kal_uint32 axlen_mask;
+    kal_uint32 axsize;
+    kal_uint32 axsize_mask;
+} drv_aximon_mon_config_t;
+
+/*Configuration of Snap Mode*/
+typedef struct {
+    kal_bool start_sel;     /*0-axvalid; 1-axvalid&axready*/
+    kal_bool cnt_wrap_en_t; /* enable/disable performance counter wrap around*/
+    drv_aximon_rwsel_t rwsel;	
+    drv_busmon_trg_mode_t trg_mode; /*trigger mode*/
+    kal_bool all_master_enable; /*ALL Master should only use in Monitor mode*/
+    kal_bool   data_enable; /*data target check at counting snap count*/
+    kal_uint32 mon_cnt;     /* count select */
+    kal_uint32 cycle_cnt;   /*max cycle, only use in cycle trigger mode*/
+    kal_uint32 master_id;   /*specific transaction ID */
+    kal_uint32 master_id_mask;
+    kal_uint32 vpe_id;      /*specific VPE ID*/
+    kal_uint32 vpe_id_mask;   
+    kal_uint32 ultra;       /*specific ULTRA */
+    kal_uint32 ultra_mask;
+    kal_uint32 addr;        /*address*/
+    kal_uint32 addr_mask;   /*address mask, 0: check, 1: ignore*/
+    kal_uint32 data;        /*data 0 32-bit of bus width*/
+    kal_uint32 data_mask;   /*data 0 mask 0: check, 1: ignore*/
+    kal_uint32 axlen;
+    kal_uint32 axlen_mask;
+    kal_uint32 axsize;
+    kal_uint32 axsize_mask;
+} drv_aximon_snp_config_t;
+
+/*Configuration of Snap Mode*/
+typedef struct {
+    kal_bool enable_seq_trg; /*TRUE=>sequencial mode, FALSE=>Concurrent mode*/
+    drv_busmon_mon_seq_check_mode_t seq_check_mode; /*START_ORDER_IP0_IP1/STOP_ORDER_IP0_IP1*/
+    drv_aximon_snp_config_t ip[BUSMON_IP_MAX];
+} drv_aximon_trg_config_t;
+
+/*Monitor Mode: Read-related information*/
+typedef struct {
+    kal_uint32 tot_bus_cyc;/*total bus cycle*/
+    kal_uint32 non_ov_trans_num;/*total transaction number*/
+    kal_uint32 ov_trans_num;
+    kal_uint32 non_wgt_trans_cyc;/*total transaction cycle*/
+    kal_uint32 wgt_trans_cyc;
+    kal_uint32 max_trans_cyc;/*max transaction cycle*/
+    kal_uint32 max_ost_trans_num;
+    kal_uint32 cur_ost_trans_num;/*current outstanding transaction number*/ 
+    kal_uint32 bus_util;/*bus utilization*/
+    kal_uint32 avg_xac_cyc;/*average transaction cycle*/
+} drv_aximon_mon_transaction_info_t;
+
+/*Snap Mode :Read-related informatin*/
+typedef struct {
+    kal_uint32 int_frc_val;/*the value of frc when interrupt occurs*/
+    kal_uint32 info0;  /*current AXI bus signal (burst, lock, cache, size...)*/
+    kal_uint32 info1;  /*current target id (QID),target match count*/
+    kal_uint32 info2;  /*snap target address*/
+    kal_uint32 info3;  /*data0&data1 strobe*/
+    kal_uint32 info4;  /*last data[31:0]*/
+    kal_uint32 info5;  /*last data[63:32]*/
+    kal_uint32 info6;  /*last data[95:64]*/
+    kal_uint32 info7;  /*last data[127:96]*/
+    kal_uint32 info8;  /*last second data[31:0]*/
+    kal_uint32 info9;  /*last second data[63:32]*/
+    kal_uint32 info10; /*last second data[95:64]*/
+    kal_uint32 info11; /*last second data[127:96]*/
+    kal_uint32 info12; /*VPE status*/
+} drv_aximon_snp_info_t;
+
+/*Sequential Mode*/
+typedef struct {
+   drv_aximon_snp_info_t ip[BUSMON_IP_MAX];
+} drv_aximon_trg_info_t;
+
+typedef struct{
+    kal_uint32 curr_id;   /*current transaction id*/
+    kal_uint32 curr_addr; /*current transaction addr*/
+    kal_uint32 curr_vpe;  /*current transaction vpe*/
+    kal_uint32 curr_ctrl; /*current transaction ctrl*/
+    kal_uint32 his_id;    /*history transaction id*/
+    kal_uint32 his_cmd;   /*history transaction cmd*/
+    kal_uint32 his_addr;  /*history transaction addr*/
+}drv_aximon_rec_hiscur_info;
+
+typedef struct{
+    kal_uint32 buff_cnt;
+    kal_uint32 grp_cmd;
+    kal_uint32 grp_addr[32];
+    kal_uint32 grp_id[32];
+}drv_aximon_rec_grp_info;
+
+typedef void (*busmon_intr_cb)(void);
+
+typedef struct {
+    kal_uint32 log_index;
+    kal_uint32 log_frc_count[MO_LATENCY_RECORD_NUM];
+    kal_uint32 log_max_trans_cycle[MO_LATENCY_RECORD_NUM];
+    kal_uint32 log_address[MO_LATENCY_RECORD_NUM];
+    kal_uint32 log_data_vpe[MO_LATENCY_RECORD_NUM];
+    kal_uint32 log_master_id[MO_LATENCY_RECORD_NUM];
+} aximon_log_info_t;
+
+/*this struct is used to record the at comand that user input.*/
+typedef struct{
+    busmon_at_config_t at_config_g;
+    busmon_busid_t at_bus_id_g;
+    kal_uint32 at_addr_g;
+    kal_uint32 at_addr_msk_g;
+    kal_uint32 at_master_g;
+    kal_uint32 at_master_msk_g;
+    kal_uint32 at_vpe_g;
+    kal_uint32 at_vpe_msk_g;
+    kal_uint32 at_ultra_g;
+    kal_uint32 at_ultra_msk_g;
+    kal_uint32 at_data_latcy_g;
+    kal_uint32 at_data_msk_g;
+}drv_aximon_at_config;
+
+/*this struct is used to record registers value before entering dormant*/
+typedef struct{
+    kal_uint32 aximon_ctl_r;
+    kal_uint32 aximon_tst_r;
+    kal_uint32 aximon_intmsk_r;
+    kal_uint32 aximon_ip0_tg_r;
+    kal_uint32 aximon_ip0_tmr_r;
+    kal_uint32 aximon_ip0_id_r;
+    kal_uint32 aximon_ip0_vpe_r;
+    kal_uint32 aximon_ip0_addr_r;
+    kal_uint32 aximon_ip0_addrmsk_r;
+    kal_uint32 aximon_ip0_data_r;
+    kal_uint32 aximon_ip0_datamsk_r;
+    kal_uint32 aximon_ip0_constr_r;
+    kal_uint32 aximon_ip1_tg_r;
+    kal_uint32 aximon_ip1_tmr_r;
+    kal_uint32 aximon_ip1_id_r;
+    kal_uint32 aximon_ip1_vpe_r;
+    kal_uint32 aximon_ip1_addr_r;
+    kal_uint32 aximon_ip1_addrmsk_r;
+    kal_uint32 aximon_ip1_data_r;
+    kal_uint32 aximon_ip1_datamsk_r;
+    kal_uint32 aximon_ip1_constr_r;
+    kal_uint32 busrec_obsrv_ctrl_r;
+    kal_uint32 busrec_reg_log_ctr_r;
+    kal_uint32 busrec_reg_log_cg_dis_r;
+    kal_uint32 aximon_mon2gcr_ctl0_r;
+    kal_uint32 aximon_mon2gcr_ctl1_r;
+    }drv_aximon_dormant_backup;
+
+typedef struct {
+   busmon_mon2gcr_sel cnt0_sel;
+   busmon_mon2gcr_sel cnt1_sel;
+   busmon_mon2gcr_sel cnt2_sel;
+   busmon_mon2gcr_sel cnt3_sel;
+   busmon_mon2gcr_sel cnt4_sel;
+   busmon_mon2gcr_sel cnt5_sel;
+} drv_aximon_mon2gcr_config_t;
+
+typedef struct{
+    kal_uint32 busrec_his_ip0_id[8];
+    kal_uint32 busrec_his_ip0_cmd[8];
+    kal_uint32 busrec_his_ip0_addr[8];
+    kal_uint32 busrec_his_ip1_id[8];
+    kal_uint32 busrec_his_ip1_cmd[8];
+    kal_uint32 busrec_his_ip1_addr[8];
+}drv_aximon_his;
+
+typedef struct{
+    kal_uint32 cnt[6];
+}drv_aximon_gcr_cnt;
+
+/* ************************************************************************************************
+* 
+* AXIMon External Fucntion Declearation
+*
+**************************************************************************************************/
+void drv_busmon_lisr(kal_uint32 busmon_irq_id);
+
+/*************************************************************************
+ * DESCRIPTION
+ *	Bus monitor register lisr & callback function in trigger mode.
+ *
+ * PARAMETERS
+ *	 callback,busmon_irq_id
+ *
+ * RETURNS
+ *
+ * NOTE
+ *************************************************************************/
+void drv_busmon_set_trg_cb(busmon_intr_cb callback, kal_uint32 busmon_irq_id);
+
+ /*************************************************************************
+* DESCRIPTION
+*   Get BusMon base address
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*    base address
+*************************************************************************/
+kal_uint32 aximon_read_base_addr(drv_aximon_monid_t axi_mon_id);
+
+ /*************************************************************************
+* DESCRIPTION
+*   Config busmon layer.
+*
+* PARAMETERS
+*   axi_mon_id, bus_id
+*
+* RETURNS
+*     1     config success;
+*   -1     wrong bus monitor id;
+*   -2     select MDMCU busmon, wrong bus layer id in MDMCU busmon;
+*   -3     select MDINFRA busmon, wrong bus layer id in MDINFRA busmon;
+*   -4     bus monitor is started;
+*   -5     config layer is not equal with the value in AXIMON_TST register.
+*************************************************************************/
+kal_int32  aximon_set_busid(drv_aximon_monid_t axi_mon_id, busmon_busid_t bus_id);
+
+
+/*************************************************************************
+* DESCRIPTION
+*   Enable/Disable Speed Sim
+*
+* PARAMETERS
+*   axi_mon_id, enabled
+*
+* RETURNS
+*   NONE
+*************************************************************************/
+void aximon_set_speedsim(drv_aximon_monid_t axi_mon_id, kal_bool enabled);
+
+ /*************************************************************************
+* DESCRIPTION
+*   Whether clear some flag and registers when bus is idle.
+*	enabled = KAL_FALSE: not clear
+*	enabled = KAL_TRUE:  clear
+*
+* PARAMETERS
+*   axi_mon_id, enabled
+*
+* RETURNS
+*   NONE
+*************************************************************************/
+void aximon_set_clear_at_bus_idle(drv_aximon_monid_t axi_mon_id, kal_bool enabled);
+
+  /*************************************************************************
+ * DESCRIPTION
+ *  wait IP real enable
+ *
+ * PARAMETERS
+ *   axi_mon_id, mon_ip
+ *
+ * RETURNS
+ *   NONE
+ *************************************************************************/
+ void aximon_polling_IP_Real_Enable(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip);
+
+   /*************************************************************************
+ * DESCRIPTION
+ *	 disable = KAL_FALSE: enable clock gated, bus monitor can power down.
+ *	 disable = KAL_TURE: disable clock gated, bus monitor will not power down, this function maily for debug.
+ *
+ * PARAMETERS
+ *	 axi_mon_id, disable
+ *
+ * RETURNS
+ *
+ *
+ * NOTE
+ *  
+ *************************************************************************/
+ void aximon_set_disable_cg(drv_aximon_monid_t axi_mon_id, kal_bool disable);
+
+    /*************************************************************************
+* DESCRIPTION
+*   enable/disable bus monitor cycle count wrap.
+*   enabled = KAL_TRUE: enable bus monitor cycle count wrap.
+*   enabled = KAL_FALSE:  disable bus monitor cycle count wrap.
+*
+* PARAMETERS
+*   axi_mon_id, enabled
+*
+* RETURNS
+*   NONE
+*
+* NOTE
+*   
+*************************************************************************/
+void aximon_set_cyc_cnt_wrap_en(drv_aximon_monid_t axi_mon_id, kal_bool enabled);
+
+ /*************************************************************************
+* DESCRIPTION
+*   config busmon outstanding mode: 32/64
+*   enable_ost64 = KAL_TRUE: config busmon as 64 ost mode.
+*   enable_ost64 = KAL_FALSE: config busmon as 32 ost mode.
+*
+* PARAMETERS
+*   axi_mon_id, enable_ost64
+*
+* RETURNS
+*   NONE
+*
+*************************************************************************/
+void aximon_set_ost_mode(drv_aximon_monid_t axi_mon_id, kal_bool enable_ost64);
+
+ /*************************************************************************
+* DESCRIPTION
+*   select whicn time to input cmd to busrec. 
+*   start_sel = 0x0: axvalid.
+*   start_sel = 0x1: axvalid&axready.
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip,start_sel
+*
+* RETURNS
+*   NONE
+*   
+*************************************************************************/ 
+void aximon_ip_start_sel(drv_aximon_monid_t axi_mon_id,  drv_busmon_ip_t mon_ip, kal_uint32 start_sel );
+
+/*************************************************************************
+* DESCRIPTION
+*   enable/disable bus recorder history record.
+*   enabled = KAL_FALSE: disable bus recorder history record;
+*   enabled = KAL_TRUE:   enable bus recorder history record;
+*
+* PARAMETERS
+*   axi_mon_id, enabled
+*
+* RETURNS
+*   NONE
+*
+* NOTE
+*   
+*************************************************************************/
+void aximon_set_mon_his_rec_en(drv_aximon_monid_t axi_mon_id, kal_bool enabled);
+
+/*************************************************************************
+* DESCRIPTION
+*    set bus recorder abservation register
+*	obsrv_ip_ctrl->mon_his_filter_en = KAL_FALSE, bus recorder no need condition match when record history transaction command
+*	obsrv_ip_ctrl->mon_his_filter_en = KAL_TRUE , bus recorder need condition match when record history transaction command
+*    obsrv_ip_ctrl->his_rec_entry_sel (0-7), select history transaction command entry to observe
+*    obsrv_ip_ctrl->rec_entry_sel (0-31), select current transaction command entry to observe
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip, obsrv_ip_ctrl
+*
+* RETURNS
+*   NONE
+*
+* NOTE
+*   
+*************************************************************************/
+void aximon_set_mon_obsrv_entry(drv_aximon_monid_t axi_mon_id,  drv_busmon_ip_t mon_ip, 
+drv_busrec_rec_obsrv_ip_ctrl *obsrv_ip_ctrl);
+
+/*************************************************************************
+* DESCRIPTION
+*  config the busmon&bus idle signal
+*
+* PARAMETERS
+*   axi_mon_id;busrec_idle_ctrl;
+*
+* RETURNS
+*	
+*************************************************************************/
+void  aximon_set_idle_ctrl (drv_aximon_monid_t axi_mon_id, drv_busrec_idle_ctrl* busrec_idle_ctrl);
+
+/*************************************************************************
+* DESCRIPTION
+*  config the busmon2GCR register
+*
+* PARAMETERS
+*   axi_mon_id;gcr_ctl;
+*
+* RETURNS
+*	
+*************************************************************************/
+void aximon_set_mon2gcr_ctrl(drv_aximon_monid_t axi_mon_id, drv_aximon_mon2gcr_config_t* gcr_ctl);
+
+/*************************************************************************
+* DESCRIPTION
+*  Configure parameters used in Monitor Mode
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip, config
+*
+* RETURNS
+*   1  if the configuration applied
+*************************************************************************/
+kal_int32 aximon_set_monitor(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip, drv_aximon_mon_config_t *config);
+
+/*************************************************************************
+* DESCRIPTION
+*  Configure parametes used in Snapshot Mode
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip, config
+*
+* RETURNS
+*   1  if the configuration applied
+*************************************************************************/
+kal_int32 aximon_set_snap(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip, drv_aximon_snp_config_t *config);
+
+/*************************************************************************
+* DESCRIPTION
+*  Configure parameters in Sequential Trigger Mode
+*
+* PARAMETERS
+*   axi_mon_id, config
+*
+* RETURNS
+*   1   if the configuration applied
+*************************************************************************/
+kal_int32 aximon_set_sq_trg(drv_aximon_monid_t axi_mon_id, drv_aximon_trg_config_t *config);
+
+/*************************************************************************
+ * DESCRIPTION
+ *	Start bus monitor
+ *
+ * PARAMETERS
+ *	 axi_mon_id
+ *
+ * RETURNS
+ *
+ * NOTE
+ *	 BusMon clears the counts first.
+ *	 BusMon always waits for the on-going transaction finished
+ *	 before starting to update the counts.
+ *************************************************************************/
+ void aximon_start(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Stop bus monitor
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*
+* NOTE
+*   BusMon always waits for the on-going transaction finished
+*   before stopping to update the counts.
+*   Some counts stop to update once stopped received Some counts
+*   continues to update until all transactions fishished.
+*************************************************************************/
+void aximon_stop(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Enable interrupt
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*************************************************************************/
+void aximon_enable_interrupt(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Disable interrupt
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*************************************************************************/
+void aximon_disable_interrupt(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Clear interrupt
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*************************************************************************/
+void aximon_clear_interrupt(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Read-related Information in Monitor Mode
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip, info
+*
+* RETURNS
+*************************************************************************/
+void aximon_get_ip_transaction_info(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip, 
+drv_aximon_mon_transaction_info_t *info);
+
+/*************************************************************************
+* DESCRIPTION
+*  Get triggered information in Snapshot Mode
+*
+* PARAMETERS
+*   axi_mon_id, mon_ip, info
+*
+* RETURNS
+*************************************************************************/
+void aximon_get_snap_info(drv_aximon_monid_t axi_mon_id, drv_busmon_ip_t mon_ip, 
+drv_aximon_snp_info_t *info);
+
+/*************************************************************************
+* DESCRIPTION
+*  Read-related Information in Monitor Mode through GCR
+*
+* PARAMETERS
+*   axi_mon_id, gcr_cnt
+*
+* RETURNS
+*************************************************************************/
+void aximon_get_gcr_transaction_info(drv_aximon_monid_t axi_mon_id, 
+drv_aximon_gcr_cnt *gcr_cnt);
+
+/*************************************************************************
+* DESCRIPTION
+*  Get all transactions in history buffer.
+*
+* PARAMETERS
+*   axi_mon_id, aximon_his
+*
+* RETURNS
+*************************************************************************/
+void aximon_get_his_buf(drv_aximon_monid_t axi_mon_id,drv_aximon_his *aximon_his);
+
+/*************************************************************************
+* DESCRIPTION
+*  Polling the triggered status
+*
+* PARAMETERS
+*   axi_mon_id, max_count, ip0_state, ip1_state
+*
+* RETURNS
+*	KAL_TRUE  if the interrupt triggered
+*	KAL_FALSE if no  interrupt triggered
+*************************************************************************/
+kal_bool  aximon_poll_trigged(drv_aximon_monid_t axi_mon_id, kal_uint32 max_count, 
+drv_busmon_mon_state_t *ip0_state, drv_busmon_mon_state_t *ip1_state);
+
+/*************************************************************************
+* DESCRIPTION
+*  disable IP0 and IP1.
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*************************************************************************/
+void aximon_disable_both_ip(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*  Confirm the AXI Monitor is enable or not
+*
+* PARAMETERS
+*   axi_mon_id
+*
+* RETURNS
+*************************************************************************/
+kal_bool  drv_busmon_is_started(drv_aximon_monid_t axi_mon_id);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDINFRA busmon interrupt occurs in log mode. 
+*   After MDINFRA busmon interrupt occurs in log mode, just record the registers information and clear interrupt.
+*   The define as follows
+*      AXIMON_IP0_SNAP_INFO2: the address of target transaction in IP0;
+*      AXIMON_IP0_MAX_TRANS_CYC: tha max transaction cycle in IP0;
+*      AXIMON_IP0_SNAP_INFO0: transaction information in IP0;
+*      AXIMON_IP0_SNAP_INFO1: master id of target transaction in IP0.
+*
+*************************************************************************/
+void mdinfra_busmon_record(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDMCU busmon interrupt occurs in log mode. 
+*   After MDMCU busmon interrupt occurs in log mode, just record the registers information and clear interrupt.
+*   The define as follows
+*      AXIMON_IP0_SNAP_INFO2: the address of target transaction in IP0;
+*      AXIMON_IP0_MAX_TRANS_CYC: tha max transaction cycle in IP0;
+*      AXIMON_IP0_SNAP_INFO0: transaction information in IP0;
+*      AXIMON_IP0_SNAP_INFO1: master id of target transaction in IP0.
+*
+*************************************************************************/
+void mdmcu_busmon_record(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDINFRA busmon interrupt occurs in latency&ASSERT mode. 
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_MAX_TRANS_CYC: IP0 max transaction cycle;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdinfra_busmon_latency_assert(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDMCU busmon interrupt occurs in latency&ASSERT mode. 
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_MAX_TRANS_CYC: IP0 max transaction cycle;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdmcu_busmon_latency_assert(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDINFRA busmon interrupt occurs in address&ASSERT mode. 
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_SNAP_INFO0: IP0 transaction info;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdinfra_busmon_addr_assert(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called when MDMCU busmon interrupt occurs in address&ASSERT mode. 
+*   When interrupt occurs, this function will show the information of the registers as below and assert:
+*      AXIMON_IP0_SNAP_INFO0: IP0 transaction info;
+*      AXIMON_IP0_SNAP_INFO2: IP0 snap address;
+*      AXIMON_IP1_SNAP_INFO2: IP1 snap address.
+*
+*************************************************************************/
+void mdmcu_busmon_addr_assert(void);
+
+void addrlog_enable();
+void addrlog_disable();
+void addrlog_switch_mode(kal_uint32 mode);
+void addrlog_pattern_gen_enable();
+
+/*************************************************************************
+* DESCRIPTION
+*   This function will be called in init.c
+*   Default config profiling MO port latency(configure busmon layer after PWB), the default define as follows:  
+*       IP0 monitor MO port read transaction
+*       IP1 monitor MO port write transaction
+*   default monitoring all master, all address, all data.
+*   user can modifiy these parameters if need
+*
+*************************************************************************/
+void busmon_init(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function can be called in dormant_service.c.
+*   This function will be used to restore the value of busmon registers after modem come out from dormant.
+*
+*************************************************************************/
+void busmon_dormant_init(void);
+
+/*************************************************************************
+* DESCRIPTION
+*   This function can be called in dormant_service.c
+*   This function will be called before entering dormant, used for saving the registers value of busmon.
+*
+*************************************************************************/
+void busmon_dormant_backup(void);
+
+/*************************************************************************
+* FUNCTION
+*  mdmcu_busmon_monitor_init
+*
+* DESCRIPTION
+*   This function can be called in busmon_init
+*   Default config monitor MO port, the default define as follows:  
+*       IP0 monitor MO port read transaction
+*       IP1 monitor MO port write transaction
+*   default monitoring all master,address filter from bank A -- bank F, all data
+*   user can modifiy these parameters if need
+*
+*************************************************************************/
+void mdmcu_busmon_monitor_init(void);
+
+/*************************************************************************
+* FUNCTION
+*  mdmcu_busmon_snap_init
+*
+* DESCRIPTION
+*   This function can be called in busmon_init.c
+*   Default config profiling MO port latency(configure busmon layer after PWB), the default define as follows:  
+*   IP0 monitor MO port read transaction
+*   IP1 monitor MO port write transaction
+*   default monitoring all master, all address, all data, the max cycle cnt is MCU2REG_READ_LIMITED_LATENCY_CNT(1us)
+*   user can modifiy these parameters if need
+*
+*************************************************************************/
+void mdmcu_busmon_snap_init(void);
+
+void mdinfra_busmon_snap_init(void);
+
+/*************************************************************************
+* FUNCTION
+*  mdinfra_busmon_monitor_init
+*
+* DESCRIPTION
+*   This function can be called in busmon_init.c
+*   Default config profiling mdinfra GDMA transaction, the default define as follows:  
+*   IP0 monitor GDMA read transaction
+*   IP1 monitor GDMA write transaction
+*   user can modifiy these parameters if need
+*
+*************************************************************************/
+void mdinfra_busmon_monitor_init(void);
+
+
+/*************************************************************************
+* FUNCTION
+*  busmon_get_avg_latency_and_xac_count
+*
+* DESCRIPTION
+*   USER call this function to get transaction information (not stop busmon)
+*   (i.e. APB average latency and non_wgt_trans_cycle, wgt_trans_cycle..)
+*     
+*   mon_info0 include read transaction info
+*   mon_info1 include write transaction info
+*
+*************************************************************************/
+void busmon_get_avg_latency_and_xac_count(drv_aximon_mon_transaction_info_t *mon_info0, 
+drv_aximon_mon_transaction_info_t *mon_info1);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_atcmd_config
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   bus_id - to select layer;
+*
+* DESCRIPTION
+*   This function is used for configuring bus monitor through AT command;
+*
+*************************************************************************/
+void aximon_atcmd_config(busmon_at_config_t at_config, busmon_busid_t at_bus_id, kal_uint32 at_addr, 
+    kal_uint32 at_addr_msk, kal_uint32 at_master, kal_uint32 at_master_msk, kal_uint32 at_vpe, 
+    kal_uint32 at_vpe_msk, kal_uint32 at_ultra, kal_uint32 at_ultra_msk, kal_uint32 at_data_latcy, kal_uint32 at_data_msk);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_at_config_monitor
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   at_bus_id - to select layer;
+*
+* DESCRIPTION
+*   config busmon monitor mode through AT command;
+*
+*************************************************************************/
+void aximon_at_config_monitor(busmon_at_config_t at_config, busmon_busid_t at_bus_id, 
+    kal_uint32 at_addr, kal_uint32 at_addr_msk, kal_uint32 at_master, kal_uint32 at_master_msk, kal_uint32 at_vpe, 
+    kal_uint32 at_vpe_msk, kal_uint32 at_ultra, kal_uint32 at_ultra_msk);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_at_config_latency
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   at_bus_id - to select layer;
+*
+* DESCRIPTION
+*   config busmon snap mode cycle trigger through AT command;
+*
+*************************************************************************/
+void aximon_at_config_latency (busmon_at_config_t at_config, busmon_busid_t at_bus_id, 
+    kal_uint32 at_addr, kal_uint32 at_addr_msk, kal_uint32 at_master, kal_uint32 at_master_msk, 
+    kal_uint32 at_vpe, kal_uint32 at_vpe_msk, kal_uint32 at_ultra, kal_uint32 at_ultra_msk, kal_uint32 at_data_latcy);
+
+/*************************************************************************
+* FUNCTION
+*  aximon_at_config_addr
+*
+* PARAMETERS
+*   at_config - to select mode/busmon id/busmon ip_id/read or write transaction. also can select assert or log in snap mode;
+*   at_bus_id - to select layer;
+*
+* DESCRIPTION
+*   config busmon monitor mode through AT command;
+*
+*************************************************************************/
+void aximon_at_config_addr(busmon_at_config_t at_config, busmon_busid_t at_bus_id, 
+    kal_uint32 at_addr, kal_uint32 at_addr_msk, kal_uint32 at_master, kal_uint32 at_master_msk, kal_uint32 at_vpe, 
+    kal_uint32 at_vpe_msk, kal_uint32 at_ultra, kal_uint32 at_ultra_msk, kal_uint32 at_data_latcy, kal_uint32 at_data_msk);
+
+
+#endif /* end of __ASSEMBLER__ */
+#endif /* end of __DRV_BUSMON_H__ */
+ 
+ 
+
diff --git a/mcu/interface/driver/devdrv/busmpu/busmpu.h b/mcu/interface/driver/devdrv/busmpu/busmpu.h
new file mode 100644
index 0000000..d2cb878
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmpu/busmpu.h
@@ -0,0 +1,171 @@
+#ifndef __BUSMPU_H__
+#define __BUSMPU_H__
+
+/*****************************************************************************
+
+ *                       Symbol/Type Definition                              *
+
+ *****************************************************************************/
+#if defined(__MD97__) || defined(__MD97P__)
+
+#include "gen97_busmpu.h"
+
+#else
+
+typedef enum BUSMPU_REGION_ATTRIBUTE_T
+{
+    BUSMPU_RO                          = 0x0,
+    BUSMPU_RW                          = 0x1,
+    BUSMON_PERMISSION_MAX
+}BUSMPU_PERMISSION_TYPE;
+
+typedef kal_uint32 FIELD;
+
+/**
+ * 0x00 : MPU_IOCU_CTRL
+ */
+typedef union {
+    struct {
+        FIELD iocu_err_trig_mode    : 1;
+        FIELD iocu_vio_clr          : 1;
+        FIELD iocu_vio_info_clr     : 1;
+        FIELD iocu_domain_int_en    : 1;
+        FIELD iocu_align_int_en     : 1;
+        FIELD rsv_5                 : 27;
+    } Bits;
+    FIELD Raw;
+} busmpu_iocu_int_ctrl, *pbusmpu_iocu_int_ctrl;
+
+/**
+ * 0x04 : MPU_EMI_CTRL
+ */
+typedef union {
+    struct {
+        FIELD emi_err_trig_mode : 1;
+        FIELD emi_vio_clr       : 1;
+        FIELD emi_vio_info_clr  : 1;
+        FIELD emi_domain_int_en : 1;
+        FIELD rsv_4             : 28;
+    } Bits;
+    FIELD Raw;
+} busmpu_emi_int_ctrl, *pbusmpu_emi_int_ctrl;
+
+/**
+ * 0x10 : MPU_IRQ_STATUS
+ */
+typedef union {
+    struct {
+        FIELD iocu_wt_domain    : 1;
+        FIELD iocu_rd_domain    : 1;
+        FIELD iocu_wt_align     : 1;
+        FIELD iocu_rd_align     : 1;
+        FIELD iocu_int_status   : 1;
+        FIELD emi_wt_domain     : 1;
+        FIELD emi_rd_domain     : 1;
+        FIELD emi_int_status    : 1;
+        FIELD rsv_8             : 24;
+    } Bits;
+    FIELD Raw;
+} busmpu_irq_status, *pbusmpu_irq_status;
+
+/**
+ * 0x20 : MPU_IOCU_VIO_DATA0
+ */
+typedef union {
+    struct {
+        FIELD iocu_addr     : 32;
+    } Bits;
+    FIELD Raw;
+} busmpu_iocu_vio_addr, *pbusmpu_iocu_vio_addr;
+
+/**
+ * 0x24 : MPU_IOCU_VIO_DATA1
+ */
+typedef union {
+    struct {
+        FIELD iocu_id       : 12;
+        FIELD iocu_domain   : 3;
+        FIELD iocu_ro       : 1;
+        FIELD iocu_region   : 5;
+        FIELD iocu_burst    : 2;
+        FIELD iocu_size     : 3;
+        FIELD iocu_len      : 4;
+        FIELD rsv_30        : 2;
+    } Bits;
+    FIELD Raw;
+} busmpu_iocu_vio_info, *pbusmpu_iocu_vio_info;
+
+/**
+ * 0x28 : MPU_EMI_VIO_DATA0
+ */
+typedef union {
+    struct {
+        FIELD emi_addr      : 32;
+    } Bits;
+    FIELD Raw;
+} busmpu_emi_vio_addr, *pbusmpu_emi_vio_addr;
+
+/**
+ * 0x2C : MPU_EMI_VIO_DATA1
+ */
+typedef union {
+    struct {
+        FIELD emi_id        : 12;
+        FIELD emi_domain    : 3;
+        FIELD emi_ro        : 1;
+        FIELD emi_region    : 8;
+        FIELD rsv_24        : 8;
+    } Bits;
+    FIELD Raw;
+} busmpu_emi_vio_info, *pbusmpu_emi_vio_info;
+
+/**
+ * 0x30 : MPU_EMI_VIO_DATA2
+ */
+typedef union {
+    struct {
+        FIELD emi_user      : 12;
+        FIELD rsv_12        : 20;
+    } Bits;
+    FIELD Raw;
+} busmpu_emi_vio_user, *pbusmpu_emi_vio_user;
+
+typedef volatile struct {
+    busmpu_iocu_int_ctrl    iocu_ctrl;  // 0000
+    busmpu_emi_int_ctrl     emi_ctrl;   // 0004
+    FIELD                   rsv_0008[2];    // 0008..000C
+    busmpu_irq_status       irq_status;     // 0010
+    FIELD                   rsv_0014[3];    // 0014..001C
+    busmpu_iocu_vio_addr    iocu_vio_addr;  // 0020
+    busmpu_iocu_vio_info    iocu_vio_info;  // 0024
+    busmpu_emi_vio_addr     emi_vio_addr;   // 0028
+    busmpu_emi_vio_info     emi_vio_info;   // 002C
+    busmpu_emi_vio_user     emi_vio_user;   // 0030
+} busmpu_reg, *pbusmpu_reg;
+
+typedef struct {
+    busmpu_iocu_vio_addr    addr;
+    busmpu_iocu_vio_info    info;
+} busmpu_iocu_vio_data, busmpu_mdinfra_error_info_st;
+
+typedef struct {
+    busmpu_emi_vio_addr     addr;
+    busmpu_emi_vio_info     info;
+    busmpu_emi_vio_user     user;
+} busmpu_emi_vio_data, busmpu_mdmcu_error_info_st;
+
+extern kal_bool busmpu_mdinfra_dump_err(void);
+extern kal_bool busmpu_mdmcu_dump_err(void);
+extern kal_bool busmpu_dump_irq_sts(void);
+extern void busmpu_init(void);
+extern volatile busmpu_emi_vio_data busmpu_emi_err;
+extern volatile busmpu_iocu_vio_data busmpu_iocu_err;
+extern volatile busmpu_irq_status busmpu_irq_sts;
+void drv_iocu_lisr(kal_uint32 v);
+void iocu_align_init(void);
+void drv_rmpu_lisr(kal_uint32 v);
+void rmpu_md_init(void);
+
+#endif /*#if defined(__MD97__)*/
+#endif /*__BUSMPU_H__*/
+
diff --git a/mcu/interface/driver/devdrv/busmpu/gen97_busmpu.h b/mcu/interface/driver/devdrv/busmpu/gen97_busmpu.h
new file mode 100644
index 0000000..3c3b11f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmpu/gen97_busmpu.h
@@ -0,0 +1,173 @@
+#ifndef __GEN97_BUSMPU_H__
+#define __GEN97_BUSMPU_H__
+
+#if defined(MT6297) || defined(CHIP10992)
+#define EMIMPU_MD2AP_INFODUMP_ENABLE
+#endif
+
+/*****************************************************************************
+ *                       Symbol/Type Definition                              *
+ *****************************************************************************/
+typedef kal_uint32 FIELD;
+
+/**
+ * 0x00 : MPU_IOCU_CTRL
+ */
+typedef union {
+    struct {
+        FIELD reg_mpu_iocu_disable               : 1; //default:1 (RW)
+        FIELD reg_mpu_iocu_bank2_default_pms     : 2; //default:3 (RW)
+        FIELD reg_mpu_iocu_bank3_default_pms     : 2; //default:3 (RW)
+        FIELD reg_mpu_iocu_bank9f_default_pms    : 2; //default:3 (RW)
+        FIELD reg_mpu_iocu_err_trig_mode         : 1; //default:0 (RW)
+        FIELD reg_mpu_iocu_vio_clr               : 1; //default:0 (W1C)
+        FIELD reg_mpu_iocu_vio_info_clr          : 1; //default:0 (W1C)
+        FIELD reg_mpu_iocu_int_en                : 1; //default:1 (RW)
+        FIELD reg_mpu_iocu_align_int_en          : 1; //default:0 (RW)
+        FIELD reg_mpu_ctrl_update                : 1; //default:0 (WP)
+        FIELD reg_mpu_algin_rule_sel             : 1; //default:0 (RW)
+        FIELD reg_mpu_iocu_int_msk               : 1; //default:1 (RW)
+        FIELD reg_mpu_unused                     : 16;
+        FIELD reg_speed_sim                      : 1; //default:0 (RW) 
+    } Bits;
+    FIELD Raw;
+} busmpu_iocu_ctrl, *pbusmpu_iocu_ctrl;
+
+/**
+ * 0x04 : MPU_IOCU_IRQ_STS
+ */
+typedef union {
+    struct {
+        FIELD o_vio_mpu_iocu_wt          : 1; //default:0 (RU)
+        FIELD o_vio_mpu_iocu_rd          : 1; //default:0 (RU)
+        FIELD o_vio_mpu_iocu_wt_align    : 1; //default:0 (RU)
+        FIELD o_vio_mpu_iocu_rd_align    : 1; //default:0 (RU)
+        FIELD o_vio_mpu_iocu_int_status  : 1; //default:0 (RU)
+        FIELD o_vio_mpu_iocu_id          : 12;//default:0 (RU) 
+        FIELD o_vio_mpu_iocu_ro          : 1; //default:0 (RU)
+        FIELD o_vio_mpu_iocu_region      : 5; //default:0 (RU)
+        FIELD o_vio_mpu_iocu_burst       : 2; //default:0 (RU)
+        FIELD o_vio_mpu_iocu_size        : 3; //default:0 (RU)
+        FIELD o_vio_mpu_iocu_len         : 4; //default:0 (RU)
+    } Bits;
+    FIELD Raw;
+} busmpu_irq_status, *pbusmpu_irq_status;
+
+/**
+ * 0x8 : MPU_IOCU_VIO_ADDR
+ */
+typedef union {
+    struct {
+        FIELD iocu_vio_addr     : 32; //default:0 (RU)
+    } Bits;
+    FIELD Raw;
+} busmpu_iocu_vio_addr, *pbusmpu_iocu_vio_addr;
+
+typedef struct {
+        busmpu_iocu_vio_addr addr;
+} busmpu_iocu_vio_data, busmpu_mdinfra_error_info_st;
+
+typedef volatile struct {
+    busmpu_iocu_ctrl        iocu_ctrl;  // 0000
+} busmpu_reg, *pbusmpu_reg;
+
+typedef struct{
+    kal_uint32 axi_id;
+    kal_uint32 port_id;
+    kal_uint32 vio_addr;
+    kal_uint32 wt_vio;
+    kal_uint32 rd_vio;
+} emimpu_vio_info_debug;
+
+
+typedef struct{
+    kal_uint32 mpus;
+    kal_uint32 mput;
+    kal_uint32 mput_2;
+    emimpu_vio_info_debug emimpu_info_debug;
+} emimpu_vio_info;
+
+//init RMPU & busmpu @HWDInitialization
+extern void rmpu_md_init(void);
+
+//dump busmpu info called by exception handler
+extern kal_bool busmpu_mdinfra_dump_err(void);
+extern kal_bool busmpu_dump_irq_sts(void);
+extern volatile busmpu_iocu_vio_data busmpu_iocu_err;
+extern volatile busmpu_irq_status busmpu_irq_sts;
+#if defined(EMIMPU_MD2AP_INFODUMP_ENABLE)
+extern volatile emimpu_vio_info emimpu_vio_dump;
+#endif
+
+//for bank2 wb
+extern void busmpu_wb_permission(kal_uint32 start_addr, kal_uint32 end_addr, kal_uint32 mask_filter, kal_uint32 busid);
+
+//bank2
+extern kal_uint32 IOCU2_00_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_00_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_01_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_01_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_02_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_02_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_03_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_03_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_04_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_04_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_05_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_05_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_06_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_06_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_07_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_07_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_08_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_08_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_09_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_09_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_10_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_10_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_11_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_11_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_12_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_12_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_13_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_13_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_14_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_14_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU2_15_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU2_15_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+
+//bank3
+extern kal_uint32 IOCU3_00_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_00_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_01_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_01_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_02_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_02_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_03_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_03_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_04_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_04_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_05_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_05_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_06_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_06_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_07_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_07_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_08_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_08_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_09_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_09_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_10_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_10_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_11_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_11_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_12_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_12_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_13_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_13_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_14_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_14_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+extern kal_uint32 IOCU3_15_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb(void);
+extern kal_uint32 IOCU3_15_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb(void);
+#endif /*__GEN97_BUSMPU_H__*/
+
diff --git a/mcu/interface/driver/devdrv/busmpu/gen97_busmpu_config.h b/mcu/interface/driver/devdrv/busmpu/gen97_busmpu_config.h
new file mode 100644
index 0000000..57e213c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmpu/gen97_busmpu_config.h
@@ -0,0 +1,11 @@
+//user need to register busmpu channel for valid usage
+
+//define BUSMPU_CONFIG(entry_index, start_addr, end_addr, bus_id, mask_filter, permission, user_name)
+//addr>=start_addr & addr <= end_addr
+//bus id table http://mtkteams.mediatek.inc/sites/WCT/CD1/DE1_DE2/Shared%20Documents/U3G_U4G%20modemsys/MT6297/Bus/BUS%20ID/97%20MD%20ID%20table.xlsx
+//permission: 0 (R/W), 2 (RO), 3 (NA)
+//
+BUSMPU_CONFIG(0, IOCU2_00_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb, IOCU2_00_NON_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb, 0, 0x7E0, 2, wei-hao.kuo)
+BUSMPU_CONFIG(1, IOCU3_01_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb, IOCU3_01_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb, 0, 0x7E0, 0, wei-hao.kuo)
+BUSMPU_CONFIG(2, IOCU3_02_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_start_cb, IOCU3_02_READ_WRITE_ALLOC_MCURW_HWRW_C_ALIGNED_ZI_end_cb, 0x4C8, 0x10, 0, SJ.cheng)
+
diff --git a/mcu/interface/driver/devdrv/busmpu/gen97_busmpu_master_config.h b/mcu/interface/driver/devdrv/busmpu/gen97_busmpu_master_config.h
new file mode 100644
index 0000000..f0c1734
--- /dev/null
+++ b/mcu/interface/driver/devdrv/busmpu/gen97_busmpu_master_config.h
@@ -0,0 +1,208 @@
+//Auto-dispatch List for Busmpu violation issue
+
+// define BUSMPU_MASTER_SRC(master_name, master_mdinfra_src_id, master_mdinfra_src_id_dontcare_mask, master_src_name, master_src_pic, dispatch_function_name) 
+// please only modify master_src_name, master_src_pic and dispatch_function_name for changeing SW PIC.
+// Other field do not modified.
+// Make sure your registered function could be built pass in every load flavor.
+// Otherwise you should use correct option
+
+BUSMPU_MASTER_BEGIN(NRL2, 0x000)
+#if (defined(__NR_RAT__)||defined(__LTE_RAT__)) && defined(__MTK_TARGET__) 
+BUSMPU_MASTER_SRC(NRL2, 0b001000, 0b0, dl_decphr_qp__5g_pre_loader__qcache, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b001001, 0b0, dl_decphr_qp__5g_pre_loader__rdma, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b001010, 0b0, lted1_qp__pre_loader, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b001011, 0b0, lted1_rdma__pre_loader, "Chi-Yen", dpcopro_desc_tbl_restore)
+
+BUSMPU_MASTER_SRC(NRL2, 0b010000, 0b0, nrul_cphr_qp__cotf_cc0, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b010001, 0b0, nrul_cphr_qp__cotf_cc1, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b010010, 0b0, nrul_cphr_cc_gen0_rdma, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b010011, 0b0, nrul_cphr_cc_gen1_rdma, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b010100, 0b0, nrul_cphr_qp__jump_cotf_cc0, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b010101, 0b0, nrul_cphr_qp__jump_cotf_cc1, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b011000, 0b0, nrul_cphr_qp__ul_arbi_qp, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b011001, 0b0, nrul_cphr_qp__ul_retx_rdma, "Chi-Yen", dpcopro_desc_tbl_restore)
+
+BUSMPU_MASTER_SRC(NRL2, 0b100000, 0b0, ul_lhif_qp, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b100001, 0b0, ul_lhif_rdma, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b101000, 0b0, qch_dma, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b101001, 0b0, qch_qp, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b110000, 0b0, mmu_tlb, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b111000, 0b0, ipf, "Chi-Yen", dpcopro_desc_tbl_restore)
+
+BUSMPU_MASTER_SRC(NRL2, 0b000000, 0b1, dl_upp_wdma, "Wei-Hao", upp_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b001000, 0b1, dl_decphr_wdma, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b010000, 0b10, nrul_cphr_cc_gen0_wdma, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b010001, 0b10, nrul_cphr_cc_gen1_wdma, "Yi-Chih", dpc_5g_cipher_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b011000, 0b1, ul_retx_wdma, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b100000, 0b1, ul_lhif_wdma, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b101000, 0b1, ltedl_lmac_wdma, "Wei-Hao", upp_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b110000, 0b1, gen95_wdma, "Chi-Yen", dpcopro_desc_tbl_restore)
+BUSMPU_MASTER_SRC(NRL2, 0b111000, 0b111, gen95_lite_wdma, "NO_OWNER", drv_iocu_lisr)
+#endif
+BUSMPU_MASTER_END(NRL2)
+
+BUSMPU_MASTER_BEGIN(RXDBRP_NR, 0x100)
+#if (defined(__NR_RAT__)||defined(__LTE_RAT__)) && defined(__MTK_TARGET__) 
+// BUSMPU_MASTER_SRC(RXDBRP_NR, 0b001, 0b0, nr_do, "tzu-han hsu", nr_pdsch_dbrp_hw_init)
+// BUSMPU_MASTER_SRC(RXDBRP_NR, 0b000, 0b10, nr_harq, "tzu-han hsu", nr_pdsch_dbrp_hw_init)
+#endif
+BUSMPU_MASTER_END(RXDBRP_NR)
+
+BUSMPU_MASTER_BEGIN(MCORE,0x200)
+BUSMPU_MASTER_SRC(MCORE, 0b1100000, 0b1100000, btdma, "Po-Sheng Wang", BTDMA_SW_Enable_Ungate_Signal)
+#if defined(__MD97__)
+BUSMPU_MASTER_SRC(MCORE, 0b0000010, 0b0, mcore0_pmu, "Terry.liao", DSP_BUS_Ultra_Config)
+BUSMPU_MASTER_SRC(MCORE, 0b0000110, 0b0, mcore1_pmu, "Terry.liao", DSP_BUS_Ultra_Config)
+BUSMPU_MASTER_SRC(MCORE, 0b0000011, 0b1111100, mcore, "Tzu-Ching Lin", DSP_BUS_Ultra_Config)
+BUSMPU_MASTER_SRC(MCORE, 0b0000001, 0b0, vcore_pmu, "Terry.liao", DSP_BUS_Ultra_Config)
+#endif
+BUSMPU_MASTER_END(MCORE)
+
+BUSMPU_MASTER_BEGIN(FE,0x300)
+#if !defined(__MAUI_BASIC__)
+BUSMPU_MASTER_SRC(FE, 0b1100000, 0b0, Md2gsys_md2g, "Jason Huang", idma_load_Genral)
+BUSMPU_MASTER_SRC(FE, 0b1000000, 0b0, Dfesys_rxdfe_xdma, "Owen Hsieh", MML1_RXDFE_D2D_DMA_TRIG) 
+#endif
+BUSMPU_MASTER_SRC(FE, 0b1000010, 0b0, Dfesys_mrsg_dbg1, "HS Yang", drv_iocu_lisr/*TBD*/) 
+BUSMPU_MASTER_SRC(FE, 0b1000100, 0b0, Dfesys_mrsg_dbg0, "HS Yang", drv_iocu_lisr/*TBD*/) 
+#if !defined(__MAUI_BASIC__)
+BUSMPU_MASTER_SRC(FE, 0b1000110, 0b0, Dfesys_tpc_xdma, "Rick-YH Lin", MML1_TPC_Cfg_Hw_Dma)
+#if defined(__UMTS_TDD128_MODE__)
+BUSMPU_MASTER_SRC(FE, 0b1001010, 0b0, Dfesys_txbsrp, "Yanhai Xuan", TxHwInit)
+#endif
+#endif
+
+BUSMPU_MASTER_SRC(FE, 0b1001100, 0b0, Dfesys_CoS_0, "Sen Chang", cos_mpu_violation)
+BUSMPU_MASTER_SRC(FE, 0b1001101, 0b0, Dfesys_CoS_1, "Sen Chang", cos_mpu_violation)
+BUSMPU_MASTER_SRC(FE, 0b1001110, 0b0, Dfesys_tpc_nr_txsrp, "NO_OWNER", drv_iocu_lisr/*TBD*/)
+
+#if !defined(__MAUI_BASIC__)
+BUSMPU_MASTER_SRC(FE, 0b1010000, 0b0, Dfesys_D_GDMA_5_HP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1010001, 0b0, Dfesys_D_GDMA_4_HP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1010010, 0b0, Dfesys_D_GDMA_3_HP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1010011, 0b0, Dfesys_D_GDMA_2_HP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1010100, 0b0, Dfesys_D_GDMA_1_HP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1010101, 0b0, Dfesys_D_GDMA_0_HP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1010110, 0b0, Dfesys_D_GDMA_5_LP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1010111, 0b0, Dfesys_D_GDMA_4_LP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1011000, 0b0, Dfesys_D_GDMA_3_LP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1011001, 0b0, Dfesys_D_GDMA_2_LP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1011010, 0b0, Dfesys_D_GDMA_1_LP, "Borchiang Huang", MML1_D_Gdma_Trig)
+BUSMPU_MASTER_SRC(FE, 0b1011011, 0b0, Dfesys_D_GDMA_0_LP, "Borchiang Huang", MML1_D_Gdma_Trig)
+
+BUSMPU_MASTER_SRC(FE, 0b0100010, 0b0, cssys_CNWDMA, "Roy yu", EL1D_CS_Main_Init)
+BUSMPU_MASTER_SRC(FE, 0b0100001, 0b0, cssys_CSH, "Roy yu", EL1D_CS_Main_Init)
+BUSMPU_MASTER_SRC(FE, 0b0100000, 0b0, cssys_DCXO, "Roy yu", EL1D_CS_Main_Init)
+#endif
+
+#if (defined(__NR_RAT__) && defined(__MTK_TARGET__))
+BUSMPU_MASTER_SRC(FE, 0b0000000, 0b0, cssys_nr_cs_nr, "WY chou", NL1_MPC_Api_Drv_Cs_Irq_Handle)
+BUSMPU_MASTER_SRC(FE, 0b0000001, 0b0, cm_nr_Cm_nr, "Wesley Fang", NL1_MPC_Api_Drv_Cm_Handle_Error_Irq)
+#endif
+#if (defined(__NR_RAT__)||defined(__LTE_RAT__)) && defined(__MTK_TARGET__) 
+// BUSMPU_MASTER_SRC(FE, 0b0000010, 0b0, rxtfc_nr_Rxtfc_nr, "Leo Wu", nr_rxtfc_init)
+// BUSMPU_MASTER_SRC(FE, 0b0000011, 0b0, rxtdb_nr_Rxtdb_nr, "Leo Wu", nr_rxtfc_init)
+#endif
+#if !defined(__MAUI_BASIC__)
+// Confirmed with owner that the SW is migrated from Shaolin to DSP MCORE.
+// BUSMPU_MASTER_SRC(FE, 0b0000100, 0b0, tx_nr_Txnr_cc0, "Cheng-Long Wu", NL1_TX_MCU_Api_Init)
+// BUSMPU_MASTER_SRC(FE, 0b0001100, 0b0, tx_nr_Txnr_cc1, "Cheng-Long Wu", NL1_TX_MCU_Api_Init)
+#endif
+BUSMPU_MASTER_END(FE)
+
+BUSMPU_MASTER_BEGIN(BIGRAM0,0x400)
+BUSMPU_MASTER_SRC(BIGRAM0, 0b001, 0b0, Bigramsys_0_br_dma, "TBD", drv_iocu_lisr/*TBD*/)
+BUSMPU_MASTER_END(BIGRAM0)
+
+BUSMPU_MASTER_BEGIN(RXBRP0,0x500)
+#if defined(__IS_EL1D_CONFIG_BUS_PRE_FETCH__)
+BUSMPU_MASTER_SRC(RXBRP0, 0b00000, 0b0, brp0_harq_r, "Sophia Huang", EL1D_RxHwCtrl_Set_Lte_Harq_Bus_Config)
+BUSMPU_MASTER_SRC(RXBRP0, 0b00100, 0b0, brp0_harq_r1, "Sophia Huang", EL1D_RxHwCtrl_Set_Lte_Harq_Bus_Config)
+BUSMPU_MASTER_SRC(RXBRP0, 0b00001, 0b0, brp0_harq_w, "Sophia Huang", EL1D_RxHwCtrl_Set_Lte_Harq_Bus_Config)
+BUSMPU_MASTER_SRC(RXBRP0, 0b00101, 0b0, brp0_harq_w1, "Sophia Huang", EL1D_RxHwCtrl_Set_Lte_Harq_Bus_Config)
+BUSMPU_MASTER_SRC(RXBRP0, 0b00111, 0b0, brp0_tbo, "Sophia Huang", EL1D_RxHwCtrl_Set_Lte_Harq_Bus_Config)
+BUSMPU_MASTER_SRC(RXBRP0, 0b00011, 0b0, brp0_vtb, "Sophia Huang", EL1D_RxHwCtrl_Set_Lte_Harq_Bus_Config)
+#endif
+BUSMPU_MASTER_END(RXBRP0)
+
+BUSMPU_MASTER_BEGIN(ABM,0x600)
+BUSMPU_MASTER_SRC(ABM, 0b001, 0b0, Shaolin_ABM0, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_SRC(ABM, 0b011, 0b0, Shaolin_ABM1, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_SRC(ABM, 0b101, 0b0, Shaolin_ABM2, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_SRC(ABM, 0b111, 0b0, Shaolin_ABM3, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_SRC(ABM, 0b000, 0b0, IA_ABM0, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_SRC(ABM, 0b010, 0b0, IA_ABM1, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_SRC(ABM, 0b100, 0b0, IA_ABM2, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_SRC(ABM, 0b110, 0b0, IA_ABM3, "Wade Huang", ASM_InitSetting)
+BUSMPU_MASTER_END(ABM)
+
+BUSMPU_MASTER_BEGIN(LOG_TOP_MCU,0x700)
+#if defined(__MTK_TARGET__)
+BUSMPU_MASTER_SRC(LOG_TOP_MCU, 0b000, 0b0, log_top_mcu_normal, "Guan-Ren Chen", logseq_drv_init)
+BUSMPU_MASTER_SRC(LOG_TOP_MCU, 0b101, 0b0, log_top_mcu_onemand, "Guan-Ren Chen", logseq_drv_init)
+#endif
+BUSMPU_MASTER_END(LOG_TOP_MCU)
+
+BUSMPU_MASTER_BEGIN(LOG_TOP_DSP4G,0x800)
+#if defined(__MTK_TARGET__)
+BUSMPU_MASTER_SRC(LOG_TOP_DSP4G, 0b000, 0b0, log_top_dsp4g_normal, "Guan-Ren Chen", logseq_drv_init)
+BUSMPU_MASTER_SRC(LOG_TOP_DSP4G, 0b101, 0b0, log_top_dsp4g_onemand, "Guan-Ren Chen", logseq_drv_init)
+#endif
+BUSMPU_MASTER_END(LOG_TOP_DSP4G)
+
+BUSMPU_MASTER_BEGIN(LOG_TOP_DSP5G,0x900)
+#if defined(__MTK_TARGET__)
+BUSMPU_MASTER_SRC(LOG_TOP_DSP5G, 0b000, 0b0, log_top_dsp5g_normal, "Guan-Ren Chen", logseq_drv_init)
+BUSMPU_MASTER_SRC(LOG_TOP_DSP5G, 0b101, 0b0, log_top_dsp5g_onemand, "Guan-Ren Chen", logseq_drv_init)
+#endif
+BUSMPU_MASTER_END(LOG_TOP_DSP5G)
+
+BUSMPU_MASTER_BEGIN(TRACE_TOP,0x1000)
+#if defined(__SCC_SIB_SUPPORT__)
+BUSMPU_MASTER_SRC(TRACE_TOP, 0b00, 0b0, trace_top, "Globe.Yan", drv_tracetop_capture_start_EMI)
+#endif
+BUSMPU_MASTER_END(TRACE_TOP)
+
+BUSMPU_MASTER_BEGIN(PPPHA,0x1100)
+#if defined(__MTK_TARGET__) && defined(__CDMA2000_RAT__)
+BUSMPU_MASTER_SRC(PPPHA, 0b0, 0b0, pppha, "Stun Wu", HlpPppHaRegInit)
+#endif
+BUSMPU_MASTER_END(PPPHA)
+
+BUSMPU_MASTER_BEGIN(GDMA,0x1200)
+BUSMPU_MASTER_SRC(GDMA, 0b0000, 0b0, channel_0, "Minni.Li", drv_gdma_set_config)
+BUSMPU_MASTER_SRC(GDMA, 0b0001, 0b0, channel_1, "Minni.Li", drv_gdma_set_config)
+BUSMPU_MASTER_SRC(GDMA, 0b0010, 0b0, channel_2, "Minni.Li", drv_gdma_set_config)
+BUSMPU_MASTER_SRC(GDMA, 0b0011, 0b0, channel_3, "Minni.Li", drv_gdma_set_config)
+BUSMPU_MASTER_SRC(GDMA, 0b0100, 0b0, channel_4, "Minni.Li", drv_gdma_set_config)
+BUSMPU_MASTER_SRC(GDMA, 0b0101, 0b0, channel_5, "Minni.Li", drv_gdma_set_config)
+BUSMPU_MASTER_SRC(GDMA, 0b0110, 0b0, channel_6, "Minni.Li", drv_gdma_set_config)
+
+BUSMPU_MASTER_SRC(GDMA, 0b1000, 0b0, channel_8, "Bernie.chang", L1sim_Cmd_Layer_MTK)
+BUSMPU_MASTER_SRC(GDMA, 0b1001, 0b0, channel_9, "Bernie.chang", L1sim_Cmd_Layer_MTK)
+
+BUSMPU_MASTER_SRC(GDMA, 0b1010, 0b0, channel_10, "Yao.Xue", UART_DriverInit )
+BUSMPU_MASTER_SRC(GDMA, 0b1011, 0b0, channel_11, "Yao.Xue", UART_DriverInit )
+BUSMPU_MASTER_END(GDMA)
+
+
+/* master_name
+*/
+BUSMPU_MASTER(NRL2)
+BUSMPU_MASTER(RXDBRP_NR)
+BUSMPU_MASTER(MCORE)
+BUSMPU_MASTER(FE)
+BUSMPU_MASTER(BIGRAM0)
+BUSMPU_MASTER(RXBRP0)
+// BUSMPU_MASTER(BIGRAM1)
+// BUSMPU_MASTER(RXBRP1)
+BUSMPU_MASTER(ABM)
+BUSMPU_MASTER(LOG_TOP_MCU)
+BUSMPU_MASTER(LOG_TOP_DSP4G)
+BUSMPU_MASTER(LOG_TOP_DSP5G)
+BUSMPU_MASTER(TRACE_TOP)
+BUSMPU_MASTER(PPPHA)
+// BUSMPU_MASTER(IPSEC)
+BUSMPU_MASTER(GDMA)
+// BUSMPU_MASTER(DBGSYS)
+// BUSMPU_MASTER(AP)
diff --git a/mcu/interface/driver/devdrv/cirq/dummy.txt.txt b/mcu/interface/driver/devdrv/cirq/dummy.txt.txt
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/dummy.txt.txt
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl.h
new file mode 100644
index 0000000..ad8c4c3
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl.h
@@ -0,0 +1,909 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *   Common type and structure definition for MediaTek GSM/GPRS software
+ *
+ * Author:
+ * -------
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _INTRCTRL_H
+#define _INTRCTRL_H
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "mips_ia_utils_public.h"
+#include "us_timer.h"
+
+#if defined(MT6763)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6763.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6763 MDSYS."
+#endif
+#endif
+
+#if defined(MT6739)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6739.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6739 MDSYS."
+#endif
+#endif
+
+#if defined(MT6771)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6771.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6771 MDSYS."
+#endif
+#endif
+
+#if defined(MT6765)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6765.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6765 MDSYS."
+#endif
+#endif
+
+#if defined(MT6761)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6761.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6761 MDSYS."
+#endif
+#endif
+
+/*******************************************************************************
+ * Declarations and Definitions
+ *******************************************************************************/
+
+#define EDGE_SENSITIVE           KAL_TRUE
+#define LEVEL_SENSITIVE          KAL_FALSE
+
+#define IRQ_NOT_LISR_CONTEXT     (0xFFFF)
+
+#if defined(__CIRQ_MASK_REG_NR_1_NEW__) || defined(__CIRQ_MASK_REG_NR_2_NEW__) || defined(__CIRQ_MASK_REG_NR_3_NEW__) || defined(__CIRQ_MASK_REG_NR_4_NEW__) || defined(__CIRQ_MASK_REG_NR_5_NEW__)
+#define __CIRQ_DESIGN_NEW__
+#endif
+
+typedef struct CIRQ_MASK_VALUE_STRUCT
+{
+    kal_uint32 irq_mask[8]; 
+} CIRQ_MASK_VALUE_T;
+
+typedef struct MIPSGIC_IRQ_MASK_VALUE_STRUCT
+{
+#if defined(__MIPSGIC_MASK_REG_NR_2_NEW__)
+    kal_uint32 irq_mask0;
+    kal_uint32 irq_mask1;
+#else
+    kal_uint32 irq_maskl;
+    kal_uint32 irq_maskh;
+#endif
+} MIPSGIC_IRQ_MASK_VALUE_T;
+
+typedef struct MIPSGIC_IRQ_SEN_VALUE_STRUCT
+{
+#if defined(__MIPSGIC_MASK_REG_NR_2_NEW__)
+    kal_uint32 irq_sen0;
+    kal_uint32 irq_sen1;
+#else
+    kal_uint32 irq_maskl;
+    kal_uint32 irq_maskh;
+#endif
+} MIPSGIC_IRQ_SEN_VALUE_T;
+
+
+/* To enable SW Trigger Interrupt for new BB chips
+   Need to modify 3 files
+   1. add a file intrCtrl_MTxxxx_SW_Handler.h
+   2. add an entry on intrCtrl_SW_Handler.h
+   3. modify IRQ_SetSWRegister & IRQ_ResetSWRegister to support BB Chips on intrCtrl.c  */
+#if defined(__ENABLE_SW_TRIGGER_INTERRUPT__)
+typedef enum
+{
+#define X_SW_HANDLE_CONST(a, b, c) a=(b),
+#include "intrCtrl_SW_Handle.h"
+#undef X_SW_HANDLE_CONST
+    SW_HANDLE_END
+} SW_CODE_HANDLE;
+
+#define Activate_LISR(code) MDCIRQ_Activate_LISR(code)
+#define Deactivate_LISR(code) MDCIRQ_Deactivate_LISR(code)
+
+extern void MDCIRQ_Activate_LISR(SW_CODE_HANDLE code);
+extern void MDCIRQ_Deactivate_LISR(SW_CODE_HANDLE code);
+extern const kal_uint8 SW_Code_Handle2Code[NUM_IRQ_SOURCES];
+
+/* Use to translate the mapping between software handler to hardware interrupt code */
+#define SW_code_handle2code(a)  (a)
+
+extern kal_uint32 SW_INT_Counter[NUM_IRQ_SOURCES];
+
+#endif /* __ENABLE_SW_TRIGGER_INTERRUPT__ */
+
+
+#define IRQClearInt(vector) MDCIRQ_IRQClearInt(vector)
+#define IRQMask(vector) MDCIRQ_IRQMask(vector)
+#define IRQUnmask(vector) MDCIRQ_IRQUnmask(vector)
+#define IRQSensitivity(vector, e) MDCIRQ_IRQSensitivity(vector, e)
+#define IRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code) MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code)
+
+
+
+extern kal_uint32 SaveAndSetIRQMask(void);
+extern void RestoreIRQMask(kal_uint32);
+extern void MDCIRQ_IRQClearInt(kal_uint8);
+extern void MDCIRQ_IRQMask(kal_uint8);
+extern void MDCIRQ_IRQUnmask(kal_uint8);
+extern void MDCIRQ_IRQSensitivity(kal_uint8, kal_bool);
+extern void initINTR(void);
+extern kal_uint32 IRQMask_Status(kal_uint8 code);
+extern kal_uint32 IRQ_Status(void);
+extern kal_bool MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(kal_uint32 VPE, kal_uint32 code);
+
+
+#define IRQ_Register_LISR(code, lisr, description) \
+    MDCIRQ_IRQ_Register_LISR(code, (void*)lisr, description)
+extern void MDCIRQ_IRQ_Register_LISR(kal_uint32 code, void (*reg_lisr)(kal_uint32 vector), char* description);
+//extern void IRQ_Register_LISR(kal_uint32 code, void (*reg_lisr)(kal_uint32 vector), char* description);
+
+extern void initVPEIRQ(void);
+
+#if !defined(__SINGLE_CORE__)
+extern kal_uint32 sst_dhl_irq_count[4];
+extern kal_uint32 sst_dhl_irq_caller[4];
+extern kal_uint32 DHLIrqCounter[4];
+#else
+extern kal_uint32 sst_dhl_irq_count[2];
+extern kal_uint32 sst_dhl_irq_caller[2];
+extern kal_uint32 DHLIrqCounter[2];
+#endif
+extern kal_int32 INC_Initialize_State;
+
+/***********************************
+NOTE:
+1. below API is only for L2 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define __IRQ_LOCK_WITHOUT_CHECK__
+//#define __NESTED_DI_CHECK__
+
+#if defined(__L2_LOGGING_IRQ_LOC__)
+#if defined(__IRQ_LOCK_WITHOUT_CHECK__) && defined(__MIPS_IA__)
+#if defined(__NESTED_DI_CHECK__)
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+    kal_uint32 vpe_num = 0;\
+    miu_mt_dmt();\
+    __asm__ __volatile__\
+    (\
+        "di %0\n\t"\
+        "ehb\n\t"\
+        :"=&r"(oldmask), "=&r"(newmask)\
+        :\
+        :"$31","memory"\
+    );\
+    oldmask &= 0x1;\
+    vpe_num = miu_get_current_vpe_id();\
+    sst_dhl_irq_count[vpe_num]++;\
+    sst_dhl_irq_caller[vpe_num] = (kal_uint32)__builtin_return_address(0);\
+    DHLIrqCounter[vpe_num] = ust_get_current_time();\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+    kal_uint32 tmp=1;\
+    sst_dhl_irq_count[miu_get_current_vpe_id()]--;\
+    __asm__ __volatile__\
+    (\
+        "bne %0, %1, END\n\t"\
+        "ei\n\t"\
+        "ehb\n\t"\
+        "END:emt\n\t"\
+        "ehb\n\t"\
+        :\
+        :"r"(oldmask), "r"(tmp)\
+        :"memory"\
+    );\
+} while(0)
+#else
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+    miu_mt_dmt();\
+    __asm__ __volatile__\
+    (\
+        "di %0\n\t"\
+        "ehb\n\t"\
+        :"=&r"(oldmask), "=&r"(newmask)\
+        :\
+        :"$31","memory"\
+    );\
+    oldmask &= 0x1;\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+    kal_uint32 tmp=1;\
+    __asm__ __volatile__\
+    (\
+        "bne %0, %1, END\n\t"\
+        "ei\n\t"\
+        "ehb\n\t"\
+        "END:emt\n\t"\
+        "ehb\n\t"\
+        :\
+        :"r"(oldmask), "r"(tmp)\
+        :"memory"\
+    );\
+} while(0)
+#endif
+
+#else
+
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{ \
+	oldmask = kal_hrt_SaveAndSetIRQMask(); \
+}while(0);
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{ \
+	kal_hrt_RestoreIRQMask(oldmask); \
+}while(0);
+
+#endif
+#endif
+
+#endif /* _INTRCTRL_H */
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_ELBRUS.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_ELBRUS.h
new file mode 100644
index 0000000..1973c88
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_ELBRUS.h
@@ -0,0 +1,896 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_ELBRUS.h
+ *
+ * Project:
+ * --------
+ *   TATAKA
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ 
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_ELBRUS_H__
+#define __INTRCTRL_ELBRUS_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES          (256)
+
+#define	IRQ_OST_CODE          	                         MD_IRQID_OST          
+#define	IRQ_MDINFRA_BUSMON_CODE                          MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define	IRQ_LMAC_RAR_CODE                       	 MD_IRQID_LMAC_RAR     
+#define	IRQ_LMAC_EAR_CODE     	                         MD_IRQID_LMAC_EAR     
+#define	IRQ_MDWDT_CODE        	                         MD_IRQID_MDWDT        
+//#define	IRQ_NFI_CODE          	                         MD_IRQID_NFI          
+#define	IRQ_L2COPRO_CODE      	                         MD_IRQID_L2COPRO      
+#define	IRQ_GPTM1_CODE        	                         MD_IRQID_GPTM1        
+#define	IRQ_GPTM2_CODE        	                         MD_IRQID_GPTM2        
+#define	IRQ_GPTM3_CODE        	                         MD_IRQID_GPTM3        
+#define	IRQ_GPTM4_CODE        	                         MD_IRQID_GPTM4        
+#define	IRQ_GPTM5_CODE       	                         MD_IRQID_GPTM5       
+#define	IRQ_GPTM6_CODE       	                         MD_IRQID_GPTM6       
+#define	IRQ_UART_MD0_CODE    	                         MD_IRQID_UART_MD0    
+#define	IRQ_UART_MD1_CODE    	                         MD_IRQID_UART_MD1    
+#define	IRQ_MDMCU_BUSMON_CODE	                         MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define	IRQ_I2C_0_CODE       	                         MD_IRQID_I2C_0       
+#define	IRQ_USIM0_CODE       	                         MD_IRQID_USIM0       
+#define	IRQ_USIM1_CODE       	                         MD_IRQID_USIM1       
+#define	IRQ_UART_MD2_CODE    	                         MD_IRQID_UART_MD2    
+#define	IRQ_MDGDMA0_CODE     	                         MD_IRQID_MDGDMA0     
+#define	IRQ_MDGDMA1_CODE     	                         MD_IRQID_MDGDMA1     
+#define	IRQ_MDGDMA2_CODE     	                         MD_IRQID_MDGDMA2     
+#define	IRQ_MDGDMA3_CODE     	                         MD_IRQID_MDGDMA3     
+#define	IRQ_EINT0_CODE       	                         MD_IRQID_EINT0       
+#define	IRQ_EINT1_CODE       	                         MD_IRQID_EINT1       
+#define	IRQ_EINT2_CODE       	                         MD_IRQID_EINT2       
+#define	IRQ_EINT3_CODE       	                         MD_IRQID_EINT3       
+#define	IRQ_EINT_SHARE_CODE  	                         MD_IRQID_EINT_SHARE  
+#define	IRQ_BUS_ERR_CODE     	                         MD_IRQID_BUS_ERR     
+#define	IRQ_TOPSM_CODE       	                         MD_IRQID_TOPSM       
+#define	IRQ_DEM_TRIG_PS_CODE	                         MD_IRQID_DEM_TRIG_PS_INT_LE
+#define	IRQ_C2K_ST_SLOT_CODE	                         MD_IRQID_C2K_ST_SLOT_INT
+#define	IRQ_C2K_ST_HALF_SLOT_CODE	                 MD_IRQID_C2K_ST_HALF_SLOT_INT
+#define	IRQ_C2K_MPDU_CODE	                         MD_IRQID_C2K_MPDU_INT
+#define	IRQ_C2K_M2C_DAT_WRDY_CODE	                 MD_IRQID_C2K_M2C_DAT_WRDY_INT
+#define	IRQ_C2K_M2C_CTL_WRDY_CODE	                 MD_IRQID_C2K_M2C_CTL_WRDY_INT
+#define	IRQ_C2K_M2C_FST_WRDY_CODE	                 MD_IRQID_C2K_M2C_FST_WRDY_INT
+#define	IRQ_C2K_NIRQ_CODE	                         MD_IRQID_C2K_NIRQ
+//#define	IRQ_PMU_CODE          	                         MD_IRQID_PMU          
+#define	IRQ_ECT_CODE          	                         MD_IRQID_ECT          
+//#define	IRQ_PS_L1_WDT_CODE    	                         MD_IRQID_PS_L1_WDT_INT    
+#define	IRQ_PTP_THERM_CODE	                         MD_IRQID_PTP_THERM_INT_INT
+#define	IRQ_CLDMA_CODE        	                         MD_IRQID_CLDMA        
+#define	IRQ_MDINFRA_ABM_CODE	                         MD_IRQID_MDINFRA_ABM_INT
+#define	IRQ_MDLITE_GPTM_CODE	                         MD_IRQID_MDLITE_GPTM_INT
+#define	IRQ_AP2MD_PCCIF_CODE	                         MD_IRQID_AP2MD_PCCIF_IRQ
+#define	IRQ_PCCIF_AP_MD_CODE	                         MD_IRQID_PCCIF_AP_MD
+#define	IRQ_CCIF2_MD_CODE	                         MD_IRQID_CCIF2_MD_IRQ
+#define	IRQ_CCIF2_MD_EVENT_CODE	                         MD_IRQID_CCIF2_MD_EVENT
+//#define	IRQ_SPI_CODE         	                         MD_IRQID_SPI         
+#define	IRQ_MDINFRA_ABM_ERROR_CODE	                 MD_IRQID_MDINFRA_ABM_ERROR_INT
+#define	IRQ_USB3_CODE        	                         MD_IRQID_USB3        
+//#define	IRQ_SDIO_CODE        	                         MD_IRQID_SDIO        
+#define	IRQ_MSDC0_CODE       	                         MD_IRQID_MSDC0       
+#define	IRQ_EHPI0_CODE       	                         MD_IRQID_EHPI0       
+//#define	IRQ_RTC_CODE         	                         MD_IRQID_RTC         
+//#define	IRQ_SOE_CODE         	                         MD_IRQID_SOE         
+#define	IRQ_MSDC1_CODE       	                         MD_IRQID_MSDC1       
+//#define	IRQ_PFC_LV_CODE  	                         MD_IRQID_PFC_INT_LV  
+//#define	IRQ_AUXACD_CODE      	                         MD_IRQID_AUXACD      
+//#define	IRQ_LED_CODE         	                         MD_IRQID_LED         
+#define	IRQ_BT_CVSD_CODE       	                         MD_IRQID_BT_CVSD       
+#define	IRQ_ELMTOP_IOCU_CODE	                         MD_IRQID_ELMTOP_IOCU_IRQ
+#define	IRQ_ELMTOP_EMI_CODE	                         MD_IRQID_ELMTOP_EMI_IRQ
+#define	IRQ_ULSR_CODE	                                 MD_IRQID_ULS_INTR
+#define	IRQ_SHARE_D12MINT1_CODE	                         MD_IRQID_SHARE_D12MINT1
+#define	IRQ_SHARE_D12MINT2_CODE           	         MD_IRQID_SHARE_D12MINT2           
+#define	IRQ_SHARE_D12MINT3_CODE           	         MD_IRQID_SHARE_D12MINT3           
+//#define	IRQ_LTE_TIMER_EMAC_SF_TICK_CODE   	         MD_IRQID_LTE_TIMER_EMAC_SF_TICK   
+#define	IRQ_IRDBG_MCU_CODE	                         MD_IRQID_IRDBG_MCU_INT
+#define	IRQ_LTE_MODEMSYS_TRACE_CODE	                 MD_IRQID_LTE_MODEMSYS_TRACE_IRQ
+#define	IRQ_SI_CM_ERR_CODE	                         MD_IRQID_SI_CM_ERR
+#define	IRQ_L1SYS_SLV_DECERR_LEVEL_CODE	             MD_IRQ_ID_L1SYS_SLV_DECERR_IRQ_LEVEL
+#define	IRQ_ABM_CODE	                                 MD_IRQID_ABM_INT
+#define	IRQ_ABM_ERROR_CODE	                         MD_IRQID_ABM_ERROR_INT
+#define	IRQ_MO_WERR_CODE	                         MD_IRQID_MO_WERR_INT
+#define	IRQ_BC_CODE	                                 MD_IRQID_BC_IRQ
+#define	IRQ_UEA_UIA_CODE	                         MD_IRQID_UEA_UIA_IRQ
+#define	IRQ_UPA_ACC_CODE	                         MD_IRQID_UPA_ACC_IRQ
+#define	IRQ_DPA_ACC_CODE	                         MD_IRQID_DPA_ACC_IRQ
+#define	IRQ_C2K_MD_0_CODE	                         MD_IRQID_C2K_MD_INT_0
+#define	IRQ_C2K_MD_1_CODE	                         MD_IRQID_C2K_MD_INT_1
+#define	IRQ_C2K_MD_2_CODE	                         MD_IRQID_C2K_MD_INT_2
+#define	IRQ_C2K_MD_3_CODE	                         MD_IRQID_C2K_MD_INT_3
+#define	IRQ_C2K_L1_0_CODE	                         MD_IRQID_C2K_L1_INT_0
+#define	IRQ_C2K_L1_1_CODE	                         MD_IRQID_C2K_L1_INT_1
+#define	IRQ_C2K_L1_2_CODE	                         MD_IRQID_C2K_L1_INT_2
+#define	IRQ_C2K_L1_3_CODE	                         MD_IRQID_C2K_L1_INT_3
+#define	IRQ_C2K_L1_4_CODE	                         MD_IRQID_C2K_L1_INT_4
+#define	IRQ_C2K_L1_5_CODE	                         MD_IRQID_C2K_L1_INT_5
+#define	IRQ_C2K_L1_6_CODE	                         MD_IRQID_C2K_L1_INT_6
+#define	IRQ_C2K_L1_7_CODE	                         MD_IRQID_C2K_L1_INT_7
+#define	IRQ_PB0_PM_CNTRSAT_0_CODE	                 MD_IRQID_PB0_PM_CNTRSAT_INT_0
+#define	IRQ_PB0_PM_CNTRSAT_1_CODE	                 MD_IRQID_PB0_PM_CNTRSAT_INT_1
+#define	IRQ_PB1_PM_CNTRSAT_0_CODE	                 MD_IRQID_PB1_PM_CNTRSAT_INT_0
+#define	IRQ_PB1_PM_CNTRSAT_1_CODE	                 MD_IRQID_PB1_PM_CNTRSAT_INT_1
+#define	IRQ_PB2_PM_CNTRSAT_0_CODE	                 MD_IRQID_PB2_PM_CNTRSAT_INT_0
+#define	IRQ_PB2_PM_CNTRSAT_1_CODE	                 MD_IRQID_PB2_PM_CNTRSAT_INT_1
+#define	IRQ_PB3_PM_CNTRSAT_0_CODE	                 MD_IRQID_PB3_PM_CNTRSAT_INT_0
+#define	IRQ_PB3_PM_CNTRSAT_1_CODE	                 MD_IRQID_PB3_PM_CNTRSAT_INT_1
+#define	IRQ_PTP_FSM_CODE	                         MD_IRQID_PTP_FSM_INT
+#define	IRQ_PTP_SLPCTL_EVENT_CODE	                 MD_IRQID_PTP_SLPCTL_EVENT
+#define	IRQ_PCCIF_MDMCU0_CODE	                         MD_IRQID_PCCIF_MDMCU0_IRQ
+#define	IRQ_PCCIF_MDMCU1_CODE	                         MD_IRQID_PCCIF_MDMCU1_IRQ
+#define	IRQ_ELM_DMA_CODE	                         MD_IRQID_ELM_DMA_IRQ
+#define	IRQ_ELM_L1_CODE	                                 MD_IRQID_ELM_L1_IRQ
+#define	IRQ_MDCIRQ_LV_CODE	                         MD_IRQID_MDCIRQ_IRQ_LV
+#define	IRQ_LOGGDMA0_LV_CODE	                         MD_IRQID_LOGGDMA_IRQ0_LV
+#define	IRQ_SOE_LV_CODE	                                 MD_IRQID_SOE_INT_LV
+#define	IRQ_TRACE_CODE	                                 MD_IRQID_TRACE_INT
+#define	IRQ_SPM2MD_DVFS_MDPERISYS_CODE	                 MD_IRQID_SPM2MD_DVFS_MDPERISYS
+#define	IRQ_SI_CM_PCINT_CODE	                         MD_IRQID_SI_CM_PCINT
+#define	IRQ_MDMCU_MACRO_BUS_CODE	                 MD_IRQID_MDMCU_MACRO_BUS_INT
+#define	IRQ_MDMCU_PERI_BUS_CODE	                         MD_IRQID_MDMCU_PERI_BUS_INT
+#define	IRQ_MM_WERR_CODE	                         MD_IRQID_MM_WERR_INT
+#define	IRQ_PLL_GEARHP_RDY_CODE	                         MD_IRQID_PLL_GEARHP_RDY
+#define	IRQ_DCXO_RDY_WO_ACK_CODE	                 MD_IRQID_DCXO_RDY_WO_ACK_IRQ
+#define	IRQ_PLL_REQ_WO_DCXO_CODE	                 MD_IRQID_PLL_REQ_WO_DCXO_IRQ
+#define	IRQ_TOP_PLL_DSNS_CODE	                         MD_IRQID_TOP_PLL_DSNS_IRQ
+#define	IRQ_BRP_BRP_CMIF_M2C_0_CODE	                 MD_IRQID_BRP_BRP_CMIF_M2C_IRQ_0
+#define	IRQ_BRP_BRP_CMIF_M2C_1_CODE	                 MD_IRQID_BRP_BRP_CMIF_M2C_IRQ_1
+#define	IRQ_BRP_BRP_CMIF_M2C_2_CODE	                 MD_IRQID_BRP_BRP_CMIF_M2C_IRQ_2
+#define	IRQ_CMP_CMTDB_CODE	                         MD_IRQID_CMP_CMTDB_IRQ
+#define	IRQ_CS_SRAM_CTRL_CODE	                         MD_IRQID_CS_SRAM_CTRL_IRQ
+#define	IRQ_CSTXB_FDD_CS_CODE	                         MD_IRQID_CSTXB_FDD_CS_IRQ
+#define	IRQ_CSTXB_TDD_CS_CODE	                         MD_IRQID_CSTXB_TDD_CS_IRQ
+#define	IRQ_DFE0_CMIF_M2C_0_CODE	                 MD_IRQID_DFE0_CMIF_M2C_IRQ_0
+#define	IRQ_DFE0_CMIF_M2C_1_CODE	                 MD_IRQID_DFE0_CMIF_M2C_IRQ_1
+#define	IRQ_DFE0_CMIF_M2C_2_CODE	                 MD_IRQID_DFE0_CMIF_M2C_IRQ_2
+#define	IRQ_DFE0_PCC_TOP_0_FULL_CODE	                 MD_IRQID_DFE0_PCC_TOP_0_FULL_IRQ
+#define	IRQ_DFE0_PCC_TOP_1_FULL_CODE	                 MD_IRQID_DFE0_PCC_TOP_1_FULL_IRQ
+#define	IRQ_DFE0_RXDFEIF_L_CODE	                         MD_IRQID_DFE0_RXDFEIF_L_IRQ
+#define	IRQ_DFE0_TCU_L1D_1_CODE	                         MD_IRQID_DFE0_TCU_L1D_1_IRQ
+#define	IRQ_DFE0_TCU_L1D_2_CODE	                         MD_IRQID_DFE0_TCU_L1D_2_IRQ
+#define	IRQ_DFE1_CMIF_M2C_0_CODE	                 MD_IRQID_DFE1_CMIF_M2C_IRQ_0
+#define	IRQ_DFE1_CMIF_M2C_1_CODE	                 MD_IRQID_DFE1_CMIF_M2C_IRQ_1
+#define	IRQ_DFE1_CMIF_M2C_2_CODE	                 MD_IRQID_DFE1_CMIF_M2C_IRQ_2
+#define	IRQ_DFE1_PCC_TOP_0_FULL_CODE	                 MD_IRQID_DFE1_PCC_TOP_0_FULL_IRQ
+#define	IRQ_DFE1_PCC_TOP_1_FULL_CODE	                 MD_IRQID_DFE1_PCC_TOP_1_FULL_IRQ
+#define	IRQ_DFE1_RXDFEIF_L_CODE	                         MD_IRQID_DFE1_RXDFEIF_L_IRQ
+#define	IRQ_L1GDMA_CODE	                                 MD_IRQID_GDMA_IRQ
+#define	IRQ_ICC_DSP_0_CODE	                         MD_IRQID_ICC_DSP_IRQ_0
+#define	IRQ_ICC_DSP_1_CODE	                         MD_IRQID_ICC_DSP_IRQ_1
+#define	IRQ_ICC_SRAM_CTRL_CODE	                         MD_IRQID_ICC_SRAM_CTRL_IRQ
+#define	IRQ_IDC_PM_CODE	                                 MD_IRQID_IDC_PM_INT
+#define	IRQ_IDC_UART_CODE	                         MD_IRQID_IDC_UART_IRQ
+#define	IRQ_IMC_DSP_0_CODE	                         MD_IRQID_IMC_DSP_IRQ_0
+#define	IRQ_IMC_DSP_1_CODE	                         MD_IRQID_IMC_DSP_IRQ_1
+#define	IRQ_IMC_MMU_0_CODE	                         MD_IRQID_IMC_MMU_IRQ_0
+#define	IRQ_IMC_MMU_1_CODE	                         MD_IRQID_IMC_MMU_IRQ_1
+#define	IRQ_IMC_RXDMP_CODE	                         MD_IRQID_IMC_RXDMP_IRQ
+#define	IRQ_IMC_RXTDB_CODE	                         MD_IRQID_IMC_RXTDB_IRQ
+#define	IRQ_IMC_SRAM_CTRL_CODE	                         MD_IRQID_IMC_SRAM_CTRL_IRQ
+#define	IRQ_INR_RAKE_CMIF_M2C_0_CODE	                 MD_IRQID_INR_RAKE_CMIF_M2C_IRQ_0
+#define	IRQ_INR_RAKE_CMIF_M2C_1_CODE	                 MD_IRQID_INR_RAKE_CMIF_M2C_IRQ_1
+#define	IRQ_INR_TD1_BRP_DMA_CODE	                 MD_IRQID_INR_TD1_BRP_DMA_IRQ
+#define	IRQ_INR_TD1_CSCE_CODE	                         MD_IRQID_INR_TD1_CSCE_IRQ
+#define	IRQ_INR_TD1_DFE_BRG_CODE	                 MD_IRQID_INR_TD1_DFE_BRG_IRQ
+#define	IRQ_INR_TD1_JDA_CODE	                         MD_IRQID_INR_TD1_JDA_IRQ
+#define	IRQ_INR_TD1_PP_CODE	                         MD_IRQID_INR_TD1_PP_IRQ
+#define	IRQ_INR_TD2_BRP_DMA_CODE	                 MD_IRQID_INR_TD2_BRP_DMA_IRQ
+#define	IRQ_INR_TD2_CSCE_CODE	                         MD_IRQID_INR_TD2_CSCE_IRQ
+#define	IRQ_INR_TD2_DFE_BRG_CODE	                 MD_IRQID_INR_TD2_DFE_BRG_IRQ
+#define	IRQ_INR_TD2_JDA_CODE	                         MD_IRQID_INR_TD2_JDA_IRQ
+#define	IRQ_TD2_PP_CODE	                                 MD_IRQID_TD2_PP_IRQ
+#define	IRQ_L1_LTE_SLEEP_CODE	                         MD_IRQID_L1_LTE_SLEEP_IRQ
+#define	IRQ_L1M_PHY_LTMR_INFORM_DONE0_CODE	         MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define	IRQ_L1M_PHY_LTMR_INFORM_DONE1_CODE	         MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define	IRQ_L1M_PHY_LTMR_0_CODE	                         MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define	IRQ_L1M_PHY_LTMR_1_CODE	                         MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define	IRQ_L1M_PHY_LTMR_2_CODE	                         MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define	IRQ_L1M_PHY_LTMR_3_CODE	                         MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define	IRQ_L1M_PHY_LTMR_4_CODE	                         MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define	IRQ_L1M_PHY_LTMR_5_CODE	                         MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define	IRQ_L1M_PHY_LTMR_6_CODE	                         MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define	IRQ_L1M_PHY_LTMR_7_CODE	                         MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define	IRQ_LTEL1_CS_CODE	                         MD_IRQID_LTEL1_CS_IRQ
+#define	IRQ_LTXB0_BSI_L_AB_CODE	                         MD_IRQID_LTXB0_BSI_L_AB_IRQ
+#define	IRQ_LTXB0_BSI_L_C_CODE	                         MD_IRQID_LTXB0_BSI_L_C_IRQ
+#define	IRQ_LTXB0_BSI_L_D_CODE	                         MD_IRQID_LTXB0_BSI_L_D_IRQ
+#define	IRQ_LTXB0_TXENC_ERROR_CODE	                 MD_IRQID_LTXB0_TXENC_ERROR_IRQ
+#define	IRQ_LTXB1_BSI_L_AB_CODE	                         MD_IRQID_LTXB1_BSI_L_AB_IRQ
+#define	IRQ_LTXB1_BSI_L_C_CODE	                         MD_IRQID_LTXB1_BSI_L_C_IRQ
+#define	IRQ_LTXB1_BSI_L_D_CODE	                         MD_IRQID_LTXB1_BSI_L_D_IRQ
+#define	IRQ_LTXB1_TXENC_ERROR_CODE	                 MD_IRQID_LTXB1_TXENC_ERROR_IRQ
+#define	IRQ_MMU_SRAM_CTRL_CODE	                         MD_IRQID_MMU_SRAM_CTRL_IRQ
+#define	IRQ_MPC_DSP_0_CODE	                         MD_IRQID_MPC_DSP_IRQ_0
+#define	IRQ_MPC_DSP_1_CODE	                         MD_IRQID_MPC_DSP_IRQ_1
+#define	IRQ_MPC_SRAM_CTRL_CODE	                         MD_IRQID_MPC_SRAM_CTRL_IRQ
+#define	IRQ_TDMA_CTIRQ1_CODE	                         MD_IRQID_TDMA_CTIRQ1
+#define	IRQ_TDMA_CTIRQ2_CODE	                         MD_IRQID_TDMA_CTIRQ2
+#define	IRQ_TDMA_CTIRQ3_CODE	                         MD_IRQID_TDMA_CTIRQ3
+#define	IRQ_L1_LTE_WAKEUP_CODE	                         MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define	IRQ_FREQM_CODE	                                 MD_IRQID_FREQM_IRQ
+#define	IRQ_MDL1_TOPSM_CODE	                         MD_IRQID_MDL1_TOPSM_IRQ
+#define	IRQ_RTR_FRAME_CODE	                         MD_IRQID_RTR_FRAME_IRQ
+#define	IRQ_RTR_SLT_CODE	                         MD_IRQID_RTR_SLT_IRQ
+#define	IRQ_WTIMER_CODE	                                 MD_IRQID_WTIMER_IRQ
+#define	IRQ_TDD_WAKEUP_CODE	                         MD_IRQID_TDD_WAKEUP_IRQ
+#define	IRQ_TDMA_WAKEUP_CODE	                         MD_IRQID_TDMA_WAKEUP_IRQ
+#define	IRQ_MODEML1_DVFS_CODE	                         MD_IRQID_MODEML1_DVFS_IRQ
+#define	IRQ_MODEML1_DVFS_MIPS_DVS_CODE	                 MD_IRQID_MODEML1_DVFS_MIPS_DVS_IRQ
+#define	IRQ_SW_LISR1_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_0
+#define	IRQ_SW_LISR2_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_1
+#define	IRQ_SW_LISR3_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_2
+#define	IRQ_SW_LISR4_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_3
+#define	IRQ_SW_LISR5_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_4
+#define	IRQ_SW_LISR6_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_5
+#define	IRQ_SW_LISR7_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_6
+#define	IRQ_SW_LISR8_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_7
+#define	IRQ_SW_LISR9_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_8
+#define	IRQ_SW_LISR10_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_9
+#define	IRQ_SW_LISR11_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_10
+#define	IRQ_SW_LISR12_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_11
+#define	IRQ_SW_LISR13_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_12
+#define	IRQ_SW_LISR14_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_13
+#define	IRQ_SW_LISR15_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_14
+#define	IRQ_SW_LISR16_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_15
+#define	IRQ_SW_LISR17_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_16
+#define	IRQ_SW_LISR18_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_17
+#define	IRQ_SW_LISR19_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_18
+#define	IRQ_SW_LISR20_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_19
+#define	IRQ_SW_LISR21_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_20
+#define	IRQ_SW_LISR22_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_21
+#define	IRQ_SW_LISR23_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_22
+#define	IRQ_SW_LISR24_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_23
+#define	IRQ_SW_LISR25_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_24
+#define	IRQ_SW_LISR26_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_25
+#define	IRQ_SW_LISR27_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_26
+#define	IRQ_SW_LISR28_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_27
+#define	IRQ_SW_LISR29_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_28
+#define	IRQ_SW_LISR30_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_29
+#define	IRQ_SW_LISR31_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_30
+#define	IRQ_SW_LISR32_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_31
+#define	IRQ_SW_LISR33_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_32
+#define	IRQ_SW_LISR34_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_33
+#define	IRQ_SW_LISR35_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_34
+#define	IRQ_SW_LISR36_CODE	                         MD_IRQID_SW_TRIGGER_RESERVED_35
+#define	IRQ_RESERVED_FOR_CC_IRQ_0_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_0
+#define	IRQ_RESERVED_FOR_CC_IRQ_1_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_1
+#define	IRQ_RESERVED_FOR_CC_IRQ_2_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_2
+#define	IRQ_RESERVED_FOR_CC_IRQ_3_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_3
+#define	IRQ_RESERVED_FOR_CC_IRQ_4_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_4
+#define	IRQ_RESERVED_FOR_CC_IRQ_5_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_5
+#define	IRQ_RESERVED_FOR_CC_IRQ_6_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_6
+#define	IRQ_RESERVED_FOR_CC_IRQ_7_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_7
+#define	IRQ_RESERVED_FOR_CC_IRQ_8_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_8
+#define	IRQ_RESERVED_FOR_CC_IRQ_9_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_9
+#define	IRQ_RESERVED_FOR_CC_IRQ_10_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_10
+#define	IRQ_RESERVED_FOR_CC_IRQ_11_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_11
+#define	IRQ_RESERVED_FOR_CC_IRQ_12_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_12
+#define	IRQ_RESERVED_FOR_CC_IRQ_13_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_13
+#define	IRQ_RESERVED_FOR_CC_IRQ_14_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_14
+#define	IRQ_RESERVED_FOR_CC_IRQ_15_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_15
+#define	IRQ_RESERVED_FOR_CC_IRQ_16_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_16
+#define	IRQ_RESERVED_FOR_CC_IRQ_17_CODE	                 MD_IRQID_RESERVED_FOR_CC_IRQ_17
+#define	IRQ_L1_GPTM1_CODE	                         MD_IRQID_L1_GPTM1
+#define	IRQ_L1_GPTM2_CODE	                         MD_IRQID_L1_GPTM2
+#define	IRQ_L1_GPTM3_CODE	                         MD_IRQID_L1_GPTM3
+#define	IRQ_L1_GPTM4_CODE	                         MD_IRQID_L1_GPTM4
+#define	IRQ_L1_GPTM5_CODE	                         MD_IRQID_L1_GPTM5
+#define	IRQ_L1_GPTM6_CODE	                         MD_IRQID_L1_GPTM6
+#define	IRQ_L1LITE_GPTM_CODE	                         MD_IRQID_L1LITE_GPTM_INT
+#define	IRQ_PPC_CIRQ_CODE	                         MD_IRQID_PPC_CIRQ
+
+/*                          
+ * Define IRQ selection register assignment
+ */                         
+#define IRQSel()
+//#define INVALID_ISR_ID           (0xFF)
+
+#define INTERRUPT_PRIORITY_LIST \
+/*  0 ~  7 */ 127,   6, 127,  11, 127,   7, 127, 127, \
+/*  8 ~ 15 */ 127, 127, 127, 127, 127, 127, 127,   6, \
+/* 16 ~ 23 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 24 ~ 31 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 32 ~ 39 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 40 ~ 47 */ 127,   7,   7,   6, 127,   7, 127, 127, \
+/* 48 ~ 55 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 56 ~ 63 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 64 ~ 71 */ 127, 127, 127, 127, 127, 127,  73, 127, \
+/* 72 ~ 79 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 80 ~ 87 */  81,  80,  83,  82, 127, 127, 127, 127, \
+/* 88 ~ 95 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 96 ~103 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*104 ~111 */  79,   7, 127, 127, 127, 127, 127, 127, \
+/*112 ~119 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*120 ~127 */ 127, 127, 127,  76,  58,  29,  60,   6, \
+/*128 ~135 */  38,  32,  62,  62,  62, 127, 127, 127, \
+/*136 ~143 */  33,  33,  62,  62,  62, 127, 127, 127, \
+/*144 ~151 */ 127,  40,   6,   6, 127, 127,  36,   6, \
+/*152 ~159 */ 127, 127,  56,  60,   6,  75,  34,  43, \
+/*160 ~167 */  34,  38,  44,  59,  43,  34,  38,  44, \
+/*168 ~175 */  59,  54,  52,  53,  37,  37,  50,  46, \
+/*176 ~183 */  48,  49,  50,  29,  57,  76,  77, 127, \
+/*184 ~191 */  61,  76, 127, 127,  61,   6,  42,   6, \
+/*192 ~199 */   6,  66,  67,  65,  28,  72,  71,  74, \
+/*200 ~207 */  31,  26,  27,  63,  25,   7,  69,  68, \
+/*208 ~215 */  70,  14,  15,  55,  69,  70, 127,  11, \
+/*216 ~223 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*224 ~231 */ 127,  53,  68,   6, 127, 127,  78,  64, \
+/*232 ~239 */  78,  78,  68,  32,  47,  30,  13,  71, \
+/*240 ~247 */  65,  65,  12,  11,  10,  25, 127, 127, \
+/*248 ~255 */ 127, 127, 127, 127, 127, 127, 127, 127,
+
+
+#define INTERRUPT_GROUP_LIST \
+	/*	0 ~  7 */  0, 14,  4,  5, 14,  0,  4, 10, \
+	/*	8 ~ 15 */ 10, 10, 10, 10, 10, 10, 10, 14, \
+	/* 16 ~ 23 */ 10, 10, 10, 16, 10, 10, 10,  0, \
+	/* 24 ~ 31 */  7, 10, 10, 10, 10, 10,  0,  0, \
+	/* 32 ~ 39 */ 10, 10, 10, 10, 10, 10, 10, 10, \
+	/* 40 ~ 47 */ 10,  2,  4, 14, 10,  0, 10,  0, \
+	/* 48 ~ 55 */ 10, 10, 10, 10, 10, 10,  0, 10, \
+	/* 56 ~ 63 */ 10, 10, 10, 10, 10, 10, 10, 10, \
+	/* 64 ~ 71 */ 10,  0, 10, 10, 10,  1,  0, 12, \
+	/* 72 ~ 79 */ 10, 10, 10, 10, 10,  0,  0, 10, \
+	/* 80 ~ 87 */  4,  4,  4,  4,  0,  0, 10, 10, \
+	/* 88 ~ 95 */ 10, 10, 10, 10, 10, 10, 10, 10, \
+	/* 96 ~103 */ 10, 10, 10, 10, 10, 10, 10, 10, \
+	/*104 ~111 */  0,  0, 10,  7, 10, 10, 10, 10, \
+	/*112 ~119 */ 10,  0, 10, 10, 10, 10, 10, 13, \
+	/*120 ~127 */ 10, 10, 10,  1,  1, 10, 10, 14, \
+	/*128 ~135 */  1, 10,  1,  0,  0,  0,  0, 10, \
+	/*136 ~143 */ 10, 10,  1,  0,  0,  0,  0, 10, \
+	/*144 ~151 */ 10,  3, 14, 14, 10, 10,  3, 14, \
+	/*152 ~159 */ 10, 10, 10, 10, 14,  1,  1, 10, \
+	/*160 ~167 */ 10, 10, 10, 10, 10, 10, 10, 10, \
+	/*168 ~175 */ 10,  3,  1,  3,  1,  1,  3,  5, \
+	/*176 ~183 */  1,  1,  3,  1,  0, 10, 10, 10, \
+	/*184 ~191 */  1, 10, 10, 10,  1, 14,  1, 14, \
+	/*192 ~199 */ 14,  1,  1,  1,  3,  0,  0,  1, \
+	/*200 ~207 */  1,  1, 10,  1,  0,  1,  1,  1, \
+	/*208 ~215 */  1,  5,  5,  1,  1,  1, 10,  5, \
+	/*216 ~223 */  0,  1,  2,  3,  4,  5,  6,  6, \
+	/*224 ~231 */  7, 15,  1, 13,  1, 13,  0,  0, \
+	/*232 ~239 */  0,  0,  1,  1,  1,  1,  4,  4, \
+	/*240 ~247 */  5,  5,  5,  5,  5,  4, 10, 10, \
+	/*248 ~255 */  7,  7, 10, 10, 10, 10, 10,  0, 
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+        0xFD, 0xFD ,0xFD, 0xFD, 0xFD, 0xFD ,0xFD, 0xFD, \
+        0xFD, 0xFD ,0xFD, 0xFD, 0xFD, 0xFD ,0xFD, 0xFD, \
+        0xFD, 0xFD ,0xFD, 0xFD, 0xFD, 0xFD ,0xFD, 0xFD, \
+        0xFD, 0xFD ,0xFD, 0xFD, 0xFD, 0xFD ,0xFD, 0xFD,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+	/* Group0(0) */                0xFE, \
+	/* Group1(1) */                0xFD, \
+	/* Group2(2) */                0xFB, \
+	/* Group3(3) */                0xF7, \
+	/* Group4(4) */                0xEF, \
+	/* Group5(5) */                0xDF, \
+	/* Group6(6) */                0xBF, \
+	/* Group7(7) */                0x7F, \
+	/* Group8(0,2) */              0xFA, \
+	/* Group9(0,2,4) */            0xEA, \
+	/* Group10(0,2,4,6) */         0xAA, \
+	/* Group11(0,4) */             0xEE, \
+	/* Group12(0,6) */             0xBE, \
+	/* Group13(0,1,2,3,4,5,6) */   0x80, \
+	/* Group14(0,1,2,3,4,5,6,7)*/  0x00, \
+	/* Group15(1,3) */             0xF5, \
+	/* Group16(0,2,4,6,7) */       0x2A, \
+	/* Group17 */ 0xFF, \
+	/* Group18 */ 0xFF, \
+	/* Group19 */ 0xFF, \
+	/* Group20 */ 0xFF, \
+	/* Group21 */ 0xFF, \
+	/* Group22 */ 0xFF, \
+	/* Group23 */ 0xFF, \
+	/* Group24 */ 0xFF, \
+	/* Group25 */ 0xFF, \
+	/* Group26 */ 0xFF, \
+	/* Group27 */ 0xFF, \
+	/* Group28 */ 0xFF, \
+	/* Group29 */ 0xFF, \
+	/* Group30 */ 0xFF, \
+	/* Group31 */ 0xFF,
+#endif
+
+#define NMI_GROUP_M2V_LIST \
+	/* Group0(0) */                0x00, \
+	/* Group1(1) */                0xFF, \
+	/* Group2(2) */                0xFF, \
+	/* Group3(3) */                0xFF, 
+
+#define INTERRUPT_BROADCAST_TYPE \
+	/*  0-31 */                0xE180807F, \
+	/* 32-63 */                0x0040AE00, \
+	/* 64-95 */                0x003FF0E2, \
+	/* 96-127 */               0x98760B00, \
+	/* 128-159 */              0x70CE7C7D, \
+	/* 160-191 */              0xF11FFE00, \
+	/* 192-223 */              0xFFBFFBFF, \
+	/* 224-255 */              0x833FFFFF, 
+
+#define INTERRUPT_TYPE \
+	/*  0-31 */                0x00000000, \
+	/* 32-63 */                0x00000000, \
+	/* 64-95 */                0x00000000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x00000000, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000, 
+
+#define INTERRUPT_HRT_MT \
+	/*  0-31 */                0x00000000, \
+	/* 32-63 */                0x00000000, \
+	/* 64-95 */                0x00000000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x00063000, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000, 
+
+
+#define INTERRUPT_TIMING_THRESHOLD \
+	/*	VPE0 */  60,\
+	/*	VPE1 */  60,\
+	/*	VPE2 */  60,\
+	/*	VPE3 */  60,\
+	/*	VPE4 */  60,\
+	/*	VPE5 */  60,\
+	/*	VPE6 */  60,\
+	/*	VPE7 */  60,
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+    #error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+#define __ENABLE_SWGIC_TRIGGER_INTERRUPT__
+
+//#define EINT_TOTAL_CHANNEL 16
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+
+/*********************************************************************
+                         GIC configuration
+**********************************************************************/
+#define NUM_GIC_SOURCES          (64)
+
+#define GIC_OS_priority 0
+#define GIC_DUMMY_priority 1 
+#define GIC_INT_priority 3
+#define GIC_INT_EX_priority 4
+#define GIC_NONE_priority 64
+
+#define GIC_IRQ_TYPE 0 
+#define GIC_NMI_TYPE 1
+#define GIC_YQ_TYPE 2
+#define GIC_UNDEF_TYPE 3
+
+
+#define VPE0_NMI_CODE MD_GICID_VPE0NMI 
+#define VPE1_NMI_CODE MD_GICID_VPE1NMI 
+#define VPE2_NMI_CODE MD_GICID_VPE2NMI 
+#define VPE3_NMI_CODE MD_GICID_VPE3NMI 
+#define VPE4_NMI_CODE MD_GICID_VPE4NMI 
+#define VPE5_NMI_CODE MD_GICID_VPE5NMI 
+#define VPE6_NMI_CODE MD_GICID_VPE6NMI 
+#define VPE7_NMI_CODE MD_GICID_VPE7NMI 
+
+#define VPE0_OS_IPI_CODE MD_GICID_VPE0WEDGE 
+#define VPE1_OS_IPI_CODE MD_GICID_VPE1WEDGE 
+#define VPE2_OS_IPI_CODE MD_GICID_VPE2WEDGE 
+#define VPE3_OS_IPI_CODE MD_GICID_VPE3WEDGE 
+#define VPE4_OS_IPI_CODE MD_GICID_VPE4WEDGE 
+#define VPE5_OS_IPI_CODE MD_GICID_VPE5WEDGE 
+#define VPE6_OS_IPI_CODE MD_GICID_VPE6WEDGE 
+#define VPE7_OS_IPI_CODE MD_GICID_VPE7WEDGE
+
+#define GICID_RESERVED0_CODE  MD_GICID_RESERVED0 
+#define GICID_RESERVED1_CODE  MD_GICID_RESERVED1 
+#define GICID_RESERVED2_CODE  MD_GICID_RESERVED2 
+#define GICID_RESERVED3_CODE  MD_GICID_RESERVED3 
+#define GICID_RESERVED4_CODE  MD_GICID_RESERVED4 
+#define GICID_RESERVED5_CODE  MD_GICID_RESERVED5
+#define GICID_RESERVED6_CODE  MD_GICID_RESERVED6 
+#define GICID_RESERVED7_CODE  MD_GICID_RESERVED7 
+
+
+#define GIC_PRIORITY_LIST \
+/*  0 ~  7 */  3,  3,  3,  3,  3,  3,  3,  3, \
+/*  8 ~ 15 */  4,  4,  4,  4,  4,  4,  4,  4, \
+/* 16 ~ 23 */  0,  0,  0,  0,  0,  0,  0,  0, \
+/* 24 ~ 31 */  0,  1,  2,  3,  8,  9, 10, 11, \
+/* 32 ~ 39 */  0,  1,  2,  3,  8,  9, 10, 11, \
+/* 40 ~ 47 */  0,  1,  2,  3,  8,  9, 10, 11, \
+/* 48 ~ 55 */  0,  1,  2,  3,  8,  9, 10, 11, \
+/* 56 ~ 63 */  1,  1 , 1, 64, 64, 64, 64, 64, \
+
+#define GIC_TYPE_LIST \
+/*	0 ~  7 */  0,  0,  0,  0,  0,  0,  0,  0, \
+/*	8 ~ 15 */  0,  0,  0,  0,  0,  0,  0,  0, \
+/* 16 ~ 23 */  0,  0,  0,  0,  0,  0,  0,  0, \
+/* 24 ~ 31 */  2,  2,  2,  2,  2,  2,  2,  2, \
+/* 32 ~ 39 */  2,  2,  2,  2,  2,  2,  2,  2, \
+/* 40 ~ 47 */  2,  2,  2,  2,  2,  2,  2,  2, \
+/* 48 ~ 55 */  2,  2,  2,  2,  2,  2,  2,  2, \
+/* 56 ~ 63 */  0 , 0,  0,  3,  3,  3,  3,  3, \
+
+#define GIC_MAP2VPE_LIST \
+/*	0 ~  7 */  0,  1,  2,  3,  4,  5,  6,  7, \
+/*	8 ~ 15 */  0,  1,  2,  3,  4,  5,  6,  7, \
+/* 16 ~ 23 */  0,  1,  2,  3,  4,  5,  6,  7, \
+/* 24 ~ 31 */  0,  0,  0,  0,  1,  1,  1,  1, \
+/* 32 ~ 39 */  2,  2,  2,  2,  3,  3,  3,  3, \
+/* 40 ~ 47 */  4,  4,  4,  4,  5,  5,  5,  5, \
+/* 48 ~ 55 */  6,  6,  6,  6,  7,  7,  7,  7, \
+/* 56 ~ 63 */  0,  2,  4,  8,  8,  8,  8,  8, \
+
+
+typedef enum
+{
+   VPE_STATUS_TASK_L     = 0,
+   VPE_STATUS_TASK_H     = 1,
+   VPE_STATUS_HISR       = 2, 
+   VPE_STATUS_LISR       = 3,
+} VPE_STATUS;
+
+#if (MAX_GIC_NUM<=64)
+#define __MIPSGIC_MASK_REG_NR_2_NEW__
+#else
+    #error "Unsupport mask number"
+#endif
+
+
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_OST = IRQ_OST_CODE,          
+    IRQ_MDINFRA_BUSMON = IRQ_MDINFRA_BUSMON_CODE,
+    IRQ_LMAC_RAR = IRQ_LMAC_RAR_CODE,     
+    IRQ_LMAC_EAR = IRQ_LMAC_EAR_CODE,     
+    IRQ_MDWDT = IRQ_MDWDT_CODE,        
+    IRQ_L2COPRO = IRQ_L2COPRO_CODE,      
+    IRQ_GPTM1 = IRQ_GPTM1_CODE,        
+    IRQ_GPTM2 = IRQ_GPTM2_CODE,        
+    IRQ_GPTM3 = IRQ_GPTM3_CODE,        
+    IRQ_GPTM4 = IRQ_GPTM4_CODE,        
+    IRQ_GPTM5 = IRQ_GPTM5_CODE,       
+    IRQ_GPTM6 = IRQ_GPTM6_CODE,       
+    IRQ_UART_MD0 = IRQ_UART_MD0_CODE,    
+    IRQ_UART_MD1 = IRQ_UART_MD1_CODE,    
+    IRQ_MDMCU_BUSMON = IRQ_MDMCU_BUSMON_CODE,
+    IRQ_I2C_0 = IRQ_I2C_0_CODE,       
+    IRQ_USIM0 = IRQ_USIM0_CODE,       
+    IRQ_USIM1 = IRQ_USIM1_CODE,       
+    IRQ_UART_MD2 = IRQ_UART_MD2_CODE,    
+    IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,     
+    IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,     
+    IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,     
+    IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,     
+    IRQ_EINT0 = IRQ_EINT0_CODE,       
+    IRQ_EINT1 = IRQ_EINT1_CODE,       
+    IRQ_EINT2 = IRQ_EINT2_CODE,       
+    IRQ_EINT3 = IRQ_EINT3_CODE,       
+    IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,  
+    IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,     
+    IRQ_TOPSM = IRQ_TOPSM_CODE,       
+    IRQ_DEM_TRIG_PS = IRQ_DEM_TRIG_PS_CODE,
+    IRQ_C2K_ST_SLOT = IRQ_C2K_ST_SLOT_CODE,
+    IRQ_C2K_ST_HALF_SLOT = IRQ_C2K_ST_HALF_SLOT_CODE,
+    IRQ_C2K_MPDU = IRQ_C2K_MPDU_CODE,
+    IRQ_C2K_M2C_DAT_WRDY = IRQ_C2K_M2C_DAT_WRDY_CODE,
+    IRQ_C2K_M2C_CTL_WRDY = IRQ_C2K_M2C_CTL_WRDY_CODE,
+    IRQ_C2K_M2C_FST_WRDY = IRQ_C2K_M2C_FST_WRDY_CODE,
+    IRQ_C2K_NIRQ = IRQ_C2K_NIRQ_CODE,
+    IRQ_ECT = IRQ_ECT_CODE,    
+    IRQ_PTP_THERM = IRQ_PTP_THERM_CODE,
+    IRQ_CLDMA = IRQ_CLDMA_CODE,        
+    IRQ_MDINFRA_ABM = IRQ_MDINFRA_ABM_CODE,
+    IRQ_MDLITE_GPTM = IRQ_MDLITE_GPTM_CODE,
+    IRQ_AP2MD_PCCIF = IRQ_AP2MD_PCCIF_CODE,
+    IRQ_PCCIF_AP_MD = IRQ_PCCIF_AP_MD_CODE,
+    IRQ_CCIF2_MD = IRQ_CCIF2_MD_CODE,
+    IRQ_CCIF2_MD_EVENT = IRQ_CCIF2_MD_EVENT_CODE,      
+    IRQ_MDINFRA_ABM_ERROR = IRQ_MDINFRA_ABM_ERROR_CODE,
+    IRQ_USB3 = IRQ_USB3_CODE,     
+    IRQ_MSDC0 = IRQ_MSDC0_CODE,       
+    IRQ_EHPI0 = IRQ_EHPI0_CODE,       
+    IRQ_MSDC1 = IRQ_MSDC1_CODE,  
+    IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,       
+    IRQ_ELMTOP_IOCU = IRQ_ELMTOP_IOCU_CODE,
+    IRQ_ELMTOP_EMI = IRQ_ELMTOP_EMI_CODE,
+    IRQ_ULSR = IRQ_ULSR_CODE,
+    IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+    IRQ_SHARE_D12MINT2 = IRQ_SHARE_D12MINT2_CODE,           
+    IRQ_SHARE_D12MINT3 = IRQ_SHARE_D12MINT3_CODE,
+    IRQ_IRDBG_MCU = IRQ_IRDBG_MCU_CODE,
+    IRQ_LTE_MODEMSYS_TRACE = IRQ_LTE_MODEMSYS_TRACE_CODE,
+    IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+    IRQ_L1SYS_SLV_DECERR_LEVEL = IRQ_L1SYS_SLV_DECERR_LEVEL_CODE,
+    IRQ_ABM = IRQ_ABM_CODE,
+    IRQ_ABM_ERROR = IRQ_ABM_ERROR_CODE,
+    IRQ_MO_WERR = IRQ_MO_WERR_CODE,
+    IRQ_BC = IRQ_BC_CODE,
+    IRQ_UEA_UIA = IRQ_UEA_UIA_CODE,
+    IRQ_UPA_ACC = IRQ_UPA_ACC_CODE,
+    IRQ_DPA_ACC = IRQ_DPA_ACC_CODE,
+    IRQ_C2K_MD_0 = IRQ_C2K_MD_0_CODE,
+    IRQ_C2K_MD_1 = IRQ_C2K_MD_1_CODE,
+    IRQ_C2K_MD_2 = IRQ_C2K_MD_2_CODE,
+    IRQ_C2K_MD_3 = IRQ_C2K_MD_3_CODE,
+    IRQ_C2K_L1_0 = IRQ_C2K_L1_0_CODE,
+    IRQ_C2K_L1_1 = IRQ_C2K_L1_1_CODE,
+    IRQ_C2K_L1_2 = IRQ_C2K_L1_2_CODE,
+    IRQ_C2K_L1_3 = IRQ_C2K_L1_3_CODE,
+    IRQ_C2K_L1_4 = IRQ_C2K_L1_4_CODE,
+    IRQ_C2K_L1_5 = IRQ_C2K_L1_5_CODE,
+    IRQ_C2K_L1_6 = IRQ_C2K_L1_6_CODE,
+    IRQ_C2K_L1_7 = IRQ_C2K_L1_7_CODE,
+    IRQ_PB0_PM_CNTRSAT_0 = IRQ_PB0_PM_CNTRSAT_0_CODE,
+    IRQ_PB0_PM_CNTRSAT_1 = IRQ_PB0_PM_CNTRSAT_1_CODE,
+    IRQ_PB1_PM_CNTRSAT_0 = IRQ_PB1_PM_CNTRSAT_0_CODE,
+    IRQ_PB1_PM_CNTRSAT_1 = IRQ_PB1_PM_CNTRSAT_1_CODE,
+    IRQ_PB2_PM_CNTRSAT_0 = IRQ_PB2_PM_CNTRSAT_0_CODE,
+    IRQ_PB2_PM_CNTRSAT_1 = IRQ_PB2_PM_CNTRSAT_1_CODE,
+    IRQ_PB3_PM_CNTRSAT_0 = IRQ_PB3_PM_CNTRSAT_0_CODE,
+    IRQ_PB3_PM_CNTRSAT_1 = IRQ_PB3_PM_CNTRSAT_1_CODE,
+    IRQ_PTP_FSM = IRQ_PTP_FSM_CODE,
+    IRQ_PTP_SLPCTL_EVENT = IRQ_PTP_SLPCTL_EVENT_CODE,
+    IRQ_PCCIF_MDMCU0 = IRQ_PCCIF_MDMCU0_CODE,
+    IRQ_PCCIF_MDMCU1 = IRQ_PCCIF_MDMCU1_CODE,
+    IRQ_ELM_DMA = IRQ_ELM_DMA_CODE,
+    IRQ_ELM_L1 = IRQ_ELM_L1_CODE,
+    IRQ_MDCIRQ_LV = IRQ_MDCIRQ_LV_CODE,
+    IRQ_LOGGDMA0_LV = IRQ_LOGGDMA0_LV_CODE,
+    IRQ_SOE_LV = IRQ_SOE_LV_CODE,
+    IRQ_TRACE = IRQ_TRACE_CODE,
+    IRQ_SPM2MD_DVFS_MDPERISYS = IRQ_SPM2MD_DVFS_MDPERISYS_CODE,
+    IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+    IRQ_MDMCU_MACRO_BUS = IRQ_MDMCU_MACRO_BUS_CODE,
+    IRQ_MDMCU_PERI_BUS = IRQ_MDMCU_PERI_BUS_CODE,
+    IRQ_MM_WERR = IRQ_MM_WERR_CODE,
+    IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+    IRQ_DCXO_RDY_WO_ACK = IRQ_DCXO_RDY_WO_ACK_CODE,
+    IRQ_PLL_REQ_WO_DCXO = IRQ_PLL_REQ_WO_DCXO_CODE,
+    IRQ_TOP_PLL_DSNS = IRQ_TOP_PLL_DSNS_CODE,
+    IRQ_BRP_BRP_CMIF_M2C_0 = IRQ_BRP_BRP_CMIF_M2C_0_CODE,
+    IRQ_BRP_BRP_CMIF_M2C_1 = IRQ_BRP_BRP_CMIF_M2C_1_CODE,
+    IRQ_BRP_BRP_CMIF_M2C_2 = IRQ_BRP_BRP_CMIF_M2C_2_CODE,
+    IRQ_CMP_CMTDB = IRQ_CMP_CMTDB_CODE,
+    IRQ_CS_SRAM_CTRL = IRQ_CS_SRAM_CTRL_CODE,
+    IRQ_CSTXB_FDD_CS = IRQ_CSTXB_FDD_CS_CODE,
+    IRQ_CSTXB_TDD_CS = IRQ_CSTXB_TDD_CS_CODE,
+    IRQ_DFE0_CMIF_M2C_0 = IRQ_DFE0_CMIF_M2C_0_CODE,
+    IRQ_DFE0_CMIF_M2C_1 = IRQ_DFE0_CMIF_M2C_1_CODE,
+    IRQ_DFE0_CMIF_M2C_2 = IRQ_DFE0_CMIF_M2C_2_CODE,
+    IRQ_DFE0_PCC_TOP_0_FULL = IRQ_DFE0_PCC_TOP_0_FULL_CODE,
+    IRQ_DFE0_PCC_TOP_1_FULL = IRQ_DFE0_PCC_TOP_1_FULL_CODE,
+    IRQ_DFE0_RXDFEIF_L = IRQ_DFE0_RXDFEIF_L_CODE,
+    IRQ_DFE0_TCU_L1D_1 = IRQ_DFE0_TCU_L1D_1_CODE,
+    IRQ_DFE0_TCU_L1D_2 = IRQ_DFE0_TCU_L1D_2_CODE,
+    IRQ_DFE1_CMIF_M2C_0 = IRQ_DFE1_CMIF_M2C_0_CODE,
+    IRQ_DFE1_CMIF_M2C_1 = IRQ_DFE1_CMIF_M2C_1_CODE,
+    IRQ_DFE1_CMIF_M2C_2 = IRQ_DFE1_CMIF_M2C_2_CODE,
+    IRQ_DFE1_PCC_TOP_0_FULL = IRQ_DFE1_PCC_TOP_0_FULL_CODE,
+    IRQ_DFE1_PCC_TOP_1_FULL = IRQ_DFE1_PCC_TOP_1_FULL_CODE,
+    IRQ_DFE1_RXDFEIF_L = IRQ_DFE1_RXDFEIF_L_CODE,
+    IRQ_L1GDMA = IRQ_L1GDMA_CODE,
+    IRQ_ICC_DSP_0 = IRQ_ICC_DSP_0_CODE,
+    IRQ_ICC_DSP_1 = IRQ_ICC_DSP_1_CODE,
+    IRQ_ICC_SRAM_CTRL = IRQ_ICC_SRAM_CTRL_CODE,
+    IRQ_IDC_PM = IRQ_IDC_PM_CODE,
+    IRQ_IDC_UART = IRQ_IDC_UART_CODE,
+    IRQ_IMC_DSP_0 = IRQ_IMC_DSP_0_CODE,
+    IRQ_IMC_DSP_1 = IRQ_IMC_DSP_1_CODE,
+    IRQ_IMC_MMU_0 = IRQ_IMC_MMU_0_CODE,
+    IRQ_IMC_MMU_1 = IRQ_IMC_MMU_1_CODE,
+    IRQ_IMC_RXDMP = IRQ_IMC_RXDMP_CODE,
+    IRQ_IMC_RXTDB = IRQ_IMC_RXTDB_CODE,
+    IRQ_IMC_SRAM_CTRL = IRQ_IMC_SRAM_CTRL_CODE,
+    IRQ_INR_RAKE_CMIF_M2C_0 = IRQ_INR_RAKE_CMIF_M2C_0_CODE,
+    IRQ_INR_RAKE_CMIF_M2C_1 = IRQ_INR_RAKE_CMIF_M2C_1_CODE,
+    IRQ_INR_TD1_BRP_DMA = IRQ_INR_TD1_BRP_DMA_CODE,
+    IRQ_INR_TD1_CSCE = IRQ_INR_TD1_CSCE_CODE,
+    IRQ_INR_TD1_DFE_BRG = IRQ_INR_TD1_DFE_BRG_CODE,
+    IRQ_INR_TD1_JDA = IRQ_INR_TD1_JDA_CODE,
+    IRQ_INR_TD1_PP = IRQ_INR_TD1_PP_CODE,
+    IRQ_INR_TD2_BRP_DMA = IRQ_INR_TD2_BRP_DMA_CODE,
+    IRQ_INR_TD2_CSCE = IRQ_INR_TD2_CSCE_CODE,
+    IRQ_INR_TD2_DFE_BRG = IRQ_INR_TD2_DFE_BRG_CODE,
+    IRQ_INR_TD2_JDA = IRQ_INR_TD2_JDA_CODE,
+    IRQ_TD2_PP = IRQ_TD2_PP_CODE,
+    IRQ_L1_LTE_SLEEP = IRQ_L1_LTE_SLEEP_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE0 = IRQ_L1M_PHY_LTMR_INFORM_DONE0_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE1 = IRQ_L1M_PHY_LTMR_INFORM_DONE1_CODE,
+    IRQ_L1M_PHY_LTMR_0 = IRQ_L1M_PHY_LTMR_0_CODE,
+    IRQ_L1M_PHY_LTMR_1 = IRQ_L1M_PHY_LTMR_1_CODE,
+    IRQ_L1M_PHY_LTMR_2 = IRQ_L1M_PHY_LTMR_2_CODE,
+    IRQ_L1M_PHY_LTMR_3 = IRQ_L1M_PHY_LTMR_3_CODE,
+    IRQ_L1M_PHY_LTMR_4 = IRQ_L1M_PHY_LTMR_4_CODE,
+    IRQ_L1M_PHY_LTMR_5 = IRQ_L1M_PHY_LTMR_5_CODE,
+    IRQ_L1M_PHY_LTMR_6 = IRQ_L1M_PHY_LTMR_6_CODE,
+    IRQ_L1M_PHY_LTMR_7 = IRQ_L1M_PHY_LTMR_7_CODE,
+    IRQ_LTEL1_CS = IRQ_LTEL1_CS_CODE,
+    IRQ_LTXB0_BSI_L_AB = IRQ_LTXB0_BSI_L_AB_CODE,
+    IRQ_LTXB0_BSI_L_C = IRQ_LTXB0_BSI_L_C_CODE,
+    IRQ_LTXB0_BSI_L_D = IRQ_LTXB0_BSI_L_D_CODE,
+    IRQ_LTXB0_TXENC_ERROR = IRQ_LTXB0_TXENC_ERROR_CODE,
+    IRQ_LTXB1_BSI_L_AB = IRQ_LTXB1_BSI_L_AB_CODE,
+    IRQ_LTXB1_BSI_L_C = IRQ_LTXB1_BSI_L_C_CODE,
+    IRQ_LTXB1_BSI_L_D = IRQ_LTXB1_BSI_L_D_CODE,
+    IRQ_LTXB1_TXENC_ERROR = IRQ_LTXB1_TXENC_ERROR_CODE,
+    IRQ_MMU_SRAM_CTRL = IRQ_MMU_SRAM_CTRL_CODE,
+    IRQ_MPC_DSP_0 = IRQ_MPC_DSP_0_CODE,
+    IRQ_MPC_DSP_1 = IRQ_MPC_DSP_1_CODE,
+    IRQ_MPC_SRAM_CTRL = IRQ_MPC_SRAM_CTRL_CODE,
+    IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+    IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+    IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+    IRQ_L1_LTE_WAKEUP = IRQ_L1_LTE_WAKEUP_CODE,
+    IRQ_FREQM = IRQ_FREQM_CODE,
+    IRQ_MDL1_TOPSM = IRQ_MDL1_TOPSM_CODE,
+    IRQ_RTR_FRAME = IRQ_RTR_FRAME_CODE,
+    IRQ_RTR_SLT = IRQ_RTR_SLT_CODE,
+    IRQ_WTIMER = IRQ_WTIMER_CODE,
+    IRQ_TDD_WAKEUP = IRQ_TDD_WAKEUP_CODE,
+    IRQ_TDMA_WAKEUP = IRQ_TDMA_WAKEUP_CODE,
+    IRQ_MODEML1_DVFS = IRQ_MODEML1_DVFS_CODE,
+    IRQ_MODEML1_DVFS_MIPS_DVS = IRQ_MODEML1_DVFS_MIPS_DVS_CODE,
+    IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+    IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+    IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+    IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+    IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+    IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+    IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+    IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+    IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+    IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+    IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+    IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+    IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+    IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+    IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+    IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+    IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+    IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+    IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+    IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+    IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+    IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+    IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+    IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+    IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+    IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+    IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+    IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+    IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+    IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+    IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+    IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+    IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+    IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+    IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+    IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_0 = IRQ_RESERVED_FOR_CC_IRQ_0_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_1 = IRQ_RESERVED_FOR_CC_IRQ_1_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_2 = IRQ_RESERVED_FOR_CC_IRQ_2_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_3 = IRQ_RESERVED_FOR_CC_IRQ_3_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_4 = IRQ_RESERVED_FOR_CC_IRQ_4_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_5 = IRQ_RESERVED_FOR_CC_IRQ_5_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_6 = IRQ_RESERVED_FOR_CC_IRQ_6_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_7 = IRQ_RESERVED_FOR_CC_IRQ_7_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_8 = IRQ_RESERVED_FOR_CC_IRQ_8_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_9 = IRQ_RESERVED_FOR_CC_IRQ_9_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_10 = IRQ_RESERVED_FOR_CC_IRQ_10_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_11 = IRQ_RESERVED_FOR_CC_IRQ_11_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_12 = IRQ_RESERVED_FOR_CC_IRQ_12_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_13 = IRQ_RESERVED_FOR_CC_IRQ_13_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_14 = IRQ_RESERVED_FOR_CC_IRQ_14_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_15 = IRQ_RESERVED_FOR_CC_IRQ_15_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_16 = IRQ_RESERVED_FOR_CC_IRQ_16_CODE,
+    IRQ_RESERVED_FOR_CC_IRQ_17 = IRQ_RESERVED_FOR_CC_IRQ_17_CODE,
+    IRQ_L1_GPTM1 = IRQ_L1_GPTM1_CODE,
+    IRQ_L1_GPTM2 = IRQ_L1_GPTM2_CODE,
+    IRQ_L1_GPTM3 = IRQ_L1_GPTM3_CODE,
+    IRQ_L1_GPTM4 = IRQ_L1_GPTM4_CODE,
+    IRQ_L1_GPTM5 = IRQ_L1_GPTM5_CODE,
+    IRQ_L1_GPTM6 = IRQ_L1_GPTM6_CODE,
+    IRQ_L1LITE_GPTM = IRQ_L1LITE_GPTM_CODE,
+    IRQ_PPC_CIRQ = IRQ_PPC_CIRQ_CODE,
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+    GIC_OS = GIC_OS_priority,
+    GIC_DUMMY = GIC_DUMMY_priority,
+    GIC_INT = GIC_INT_priority,
+    GIC_INT_EX = GIC_INT_EX_priority,
+};
+
+
+#endif /* end of __INTRCTRL_ELBRUS_H__ */
+
+    
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_ELBRUS_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_ELBRUS_SW_Handle.h
new file mode 100644
index 0000000..749eeeb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_ELBRUS_SW_Handle.h
@@ -0,0 +1,217 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_ELBRUS_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   ELBRUS
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+   __CR4__ User:
+      SW_TRIGGER_CODE1 = Max Weng
+      SW_TRIGGER_CODE2 = Max Weng
+      SW_TRIGGER_CODE3 = Max Weng
+      SW_TRIGGER_CODE4 = Max Weng
+      SW_TRIGGER_CODE5 = Max Weng
+      SW_TRIGGER_CODE6 = Chuansheng Zhang
+      SW_TRIGGER_CODE7 = Chuansheng Zhang
+      SW_TRIGGER_CODE8 = Chuansheng Zhang
+      SW_TRIGGER_CODE9 = Ivan Hu
+      SW_TRIGGER_CODE10 = Kathie Ho
+      SW_TRIGGER_CODE11 = Dennis Chueh
+      SW_TRIGGER_CODE12 = Dennis Chueh
+      SW_TRIGGER_CODE13 = Dennis Chueh
+      SW_TRIGGER_CODE14 = Dennis Chueh
+      SW_TRIGGER_CODE15 = Dennis Chueh
+      SW_TRIGGER_CODE16 = Dennis Chueh
+      SW_TRIGGER_CODE17 = Dennis Chueh
+      SW_TRIGGER_CODE18 = Crilit Tu
+      SW_TRIGGER_CODE19 = Crilit Tu
+      SW_TRIGGER_CODE20 = Yung-Chang Chen
+      SW_TRIGGER_CODE21 = Chuansheng Zhang
+      SW_TRIGGER_CODE22 = Crilit Tu (exception usage)
+      SW_TRIGGER_CODE23 = Carl Kao (ADT)
+      SW_TRIGGER_CODE24 = Qmei Yang (exception usage)
+      SW_TRIGGER_CODE25-42 = Jun-Ying Huang (CCIRQ)
+      SW_TRIGGER_CODE43 = HC Yang (dummy lisr)
+      SW_TRIGGER_CODE44 = HC Yang (dummy lisr)
+      SW_TRIGGER_CODE45 = HC Yang (dummy lisr)
+      SW_TRIGGER_CODE46 =
+      SW_TRIGGER_CODE47 =
+      SW_TRIGGER_CODE48 =
+      SW_TRIGGER_CODE49 =
+      SW_TRIGGER_CODE50 =
+      SW_TRIGGER_CODE51 =
+      SW_TRIGGER_CODE52 =
+      SW_TRIGGER_CODE53 =
+      SW_TRIGGER_CODE54 =
+ */
+#if (defined(__CR4__) || defined(__MIPS_IA__))
+//SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_RESERVED_FOR_CC_IRQ_0_CODE, IRQ_RESERVED_FOR_CC_IRQ_0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_RESERVED_FOR_CC_IRQ_1_CODE, IRQ_RESERVED_FOR_CC_IRQ_1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_RESERVED_FOR_CC_IRQ_2_CODE, IRQ_RESERVED_FOR_CC_IRQ_2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_RESERVED_FOR_CC_IRQ_3_CODE, IRQ_RESERVED_FOR_CC_IRQ_3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_RESERVED_FOR_CC_IRQ_4_CODE, IRQ_RESERVED_FOR_CC_IRQ_4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_RESERVED_FOR_CC_IRQ_5_CODE, IRQ_RESERVED_FOR_CC_IRQ_5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_RESERVED_FOR_CC_IRQ_6_CODE, IRQ_RESERVED_FOR_CC_IRQ_6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_RESERVED_FOR_CC_IRQ_7_CODE, IRQ_RESERVED_FOR_CC_IRQ_7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_RESERVED_FOR_CC_IRQ_8_CODE, IRQ_RESERVED_FOR_CC_IRQ_8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_RESERVED_FOR_CC_IRQ_9_CODE, IRQ_RESERVED_FOR_CC_IRQ_9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_RESERVED_FOR_CC_IRQ_10_CODE, IRQ_RESERVED_FOR_CC_IRQ_10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_RESERVED_FOR_CC_IRQ_11_CODE, IRQ_RESERVED_FOR_CC_IRQ_11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_RESERVED_FOR_CC_IRQ_12_CODE, IRQ_RESERVED_FOR_CC_IRQ_12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_RESERVED_FOR_CC_IRQ_13_CODE, IRQ_RESERVED_FOR_CC_IRQ_13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_RESERVED_FOR_CC_IRQ_14_CODE, IRQ_RESERVED_FOR_CC_IRQ_14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_RESERVED_FOR_CC_IRQ_15_CODE, IRQ_RESERVED_FOR_CC_IRQ_15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_RESERVED_FOR_CC_IRQ_16_CODE, IRQ_RESERVED_FOR_CC_IRQ_16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_RESERVED_FOR_CC_IRQ_17_CODE, IRQ_RESERVED_FOR_CC_IRQ_17_CODE)
+
+#else
+#error "No CPU version select. Need to specify CPU version in project ELBRUS for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6739.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6739.h
new file mode 100644
index 0000000..761d9c2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6739.h
@@ -0,0 +1,784 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6739.h
+ *
+ * Project:
+ * --------
+ *   TATAKA
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6739_H__
+#define __INTRCTRL_MT6739_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES          (256)
+
+#define 	IRQ_SHARE_D12MINT1_CODE	 MD_IRQID_SHARE_D12MINT1
+#define 	IRQ_IRDBG_MCU_INT_CODE	 MD_IRQID_IRDBG_MCU_INT
+#define 	IRQ_TDMA_CTIRQ1_CODE	 MD_IRQID_TDMA_CTIRQ1
+#define 	IRQ_TDMA_CTIRQ2_CODE	 MD_IRQID_TDMA_CTIRQ2
+#define 	IRQ_TDMA_CTIRQ3_CODE	 MD_IRQID_TDMA_CTIRQ3
+#define 	IRQ_CSSYS_FDD_CS_IRQ_CODE	 MD_IRQID_CSSYS_FDD_CS_IRQ
+#define 	IRQ_CSSYS_TDD_CS_IRQ_CODE	 MD_IRQID_CSSYS_TDD_CS_IRQ
+#define 	IRQ_CSSYS_LTE_CS_IRQ_CODE	 MD_IRQID_CSSYS_LTE_CS_IRQ
+#define 	IRQ_CSSYS_1X_CS_IRQ_CODE	 MD_IRQID_CSSYS_1X_CS_IRQ
+#define 	IRQ_CSSYS_DO_CS_IRQ_CODE	 MD_IRQID_CSSYS_DO_CS_IRQ
+#define 	IRQ_MDWDT_CODE	 MD_IRQID_MDWDT
+#define 	IRQ_UART_MD0_CODE	 MD_IRQID_UART_MD0
+#define 	IRQ_UART_MD1_CODE	 MD_IRQID_UART_MD1
+#define 	IRQ_OST_CODE	 MD_IRQID_OST
+#define 	IRQ_USIM0_CODE	 MD_IRQID_USIM0
+#define 	IRQ_USIM1_CODE	 MD_IRQID_USIM1
+#define 	IRQ_TOPSM_CODE	 MD_IRQID_TOPSM
+#define 	IRQ_MDGDMA0_CODE	 MD_IRQID_MDGDMA0
+#define 	IRQ_MDGDMA1_CODE	 MD_IRQID_MDGDMA1
+#define 	IRQ_MDGDMA2_CODE	 MD_IRQID_MDGDMA2
+#define 	IRQ_MDGDMA3_CODE	 MD_IRQID_MDGDMA3
+#define 	IRQ_EINT0_CODE	 MD_IRQID_EINT0
+#define 	IRQ_EINT1_CODE	 MD_IRQID_EINT1
+#define 	IRQ_EINT2_CODE	 MD_IRQID_EINT2
+#define 	IRQ_EINT_SHARE_CODE	 MD_IRQID_EINT_SHARE
+#define 	IRQ_BUS_ERR_CODE	 MD_IRQID_BUS_ERR
+#define 	IRQ_TXBRP0_CODE	 MD_IRQID_TXBRP0
+#define 	IRQ_TXBRP1_CODE	 MD_IRQID_TXBRP1
+#define 	IRQ_TXCRP_CODE	 MD_IRQID_TXCRP
+#define 	IRQ_MML2_HRT_CODE	 MD_IRQ_ID_MML2_HRT
+#define 	IRQ_MML2_NOTIF_CODE	 MD_IRQ_ID_MML2_NOTIF
+#define 	IRQ_MML2_EXCEP_CODE	 MD_IRQ_ID_MML2_EXCEP
+#define 	IRQ_DEM_TRIG_PS_INT_LE_CODE	 MD_IRQID_DEM_TRIG_PS_INT_LE
+#define 	IRQ_ECT_CODE	 MD_IRQID_ECT
+#define 	IRQ_PTP_THERM_INT_INT_CODE	 MD_IRQID_PTP_THERM_INT_INT
+#define 	IRQ_CLDMA_CODE	 MD_IRQID_CLDMA
+#define 	IRQ_MDINFRA_BUSMON_MATCH_STS_CODE	 MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define 	IRQ_ELM_DMA_IRQ_CODE	 MD_IRQID_ELM_DMA_IRQ
+#define 	IRQ_SOE_CODE	 MD_IRQID_SOE
+#define 	IRQ_ULSP_LOG_MD_INT_CODE	 MD_IRQID_ULSP_LOG_MD_INT
+#define 	IRQ_ULSP_LOG_DSP_INT_CODE	 MD_IRQID_ULSP_LOG_DSP_INT
+#define 	IRQ_USIP0_0_CODE	 MD_IRQID_USIP0_0
+#define 	IRQ_USIP1_0_CODE	 MD_IRQID_USIP1_0
+#define 	IRQ_USIP2_0_CODE	 MD_IRQID_USIP2_0
+#define 	IRQ_USIP3_0_CODE	 MD_IRQID_USIP3_0
+#define 	IRQ_USIP0_1_CODE	 MD_IRQID_USIP0_1
+#define 	IRQ_USIP1_1_CODE	 MD_IRQID_USIP1_1
+#define 	IRQ_USIP2_1_CODE	 MD_IRQID_USIP2_1
+#define 	IRQ_USIP3_1_CODE	 MD_IRQID_USIP3_1
+#define 	IRQ_SI_CM_ERR_CODE	 MD_IRQID_SI_CM_ERR
+#define 	IRQ_ABM_INT_CODE	 MD_IRQID_ABM_INT
+#define 	IRQ_ABM_ERROR_INT_CODE	 MD_IRQID_ABM_ERROR_INT
+#define 	IRQ_MDMCU_BUSMON_MATCH_STS_CODE	 MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define 	IRQ_ELMTOP_EMI_IRQ_CODE	 MD_IRQID_ELMTOP_EMI_IRQ
+#define 	IRQ_PPPHA_ENC0_INT_CODE	 MD_IRQID_PPPHA_ENC0_INT
+#define 	IRQ_PPPHA_ENC1_INT_CODE	 MD_IRQID_PPPHA_ENC1_INT
+#define 	IRQ_PPPHA_DEC0_INT_CODE	 MD_IRQID_PPPHA_DEC0_INT
+#define 	IRQ_PPPHA_DEC1_INT_CODE	 MD_IRQID_PPPHA_DEC1_INT
+#define 	IRQ_PTP_FSM_INT_CODE	 MD_IRQID_PTP_FSM_INT
+#define 	IRQ_PTP_SLPCTL_EVENT_CODE	 MD_IRQID_PTP_SLPCTL_EVENT
+#define 	IRQ_IEBIT_CHECK_IRQ0_CODE	 MD_IRQID_IEBIT_CHECK_IRQ0
+#define 	IRQ_IEBIT_CHECK_IRQ1_CODE	 MD_IRQID_IEBIT_CHECK_IRQ1
+#define 	IRQ_IEBIT_CHECK_IRQ2_CODE	 MD_IRQID_IEBIT_CHECK_IRQ2
+#define 	IRQ_IEBIT_CHECK_IRQ3_CODE	 MD_IRQID_IEBIT_CHECK_IRQ3
+#define 	IRQ_MDCIRQ_WDT0_CODE	 MD_IRQID_MDCIRQ_WDT0
+#define 	IRQ_MDCIRQ_WDT1_CODE	 MD_IRQID_MDCIRQ_WDT1
+#define 	IRQ_TRACE_INT_CODE	 MD_IRQID_TRACE_INT
+#define 	IRQ_SI_CM_PCINT_CODE	 MD_IRQID_SI_CM_PCINT
+#define 	IRQ_PLL_GEARHP_RDY_CODE	 MD_IRQID_PLL_GEARHP_RDY
+#define 	IRQ_DCXO_RDY_WO_ACK_IRQ_CODE	 MD_IRQID_DCXO_RDY_WO_ACK_IRQ
+#define 	IRQ_REQ_ABNORM_IRQ_CODE	 MD_IRQID_REQ_ABNORM_IRQ
+#define 	IRQ_TOP_PLL_DSNS_IRQ_CODE	 MD_IRQID_TOP_PLL_DSNS_IRQ
+#define 	IRQ_BT_CVSD_CODE	 MD_IRQID_BT_CVSD
+#define 	IRQ_SSUSB_USB_MCU_CODE	 MD_IRQID_SSUSB_USB_MCU
+#define 	IRQ_SSUSB_DEV_CODE	 MD_IRQID_SSUSB_DEV
+#define 	IRQ_AP2MD_DVFS_BLOCK_ELM_CODE	 MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define 	IRQ_AP2MD_CCIF0_0_CODE	 MD_IRQID_AP2MD_CCIF0_0
+#define 	IRQ_AP2MD_CCIF0_1_CODE	 MD_IRQID_AP2MD_CCIF0_1
+#define 	IRQ_AP2MD_CCIF1_0_CODE	 MD_IRQID_AP2MD_CCIF1_0
+#define 	IRQ_AP2MD_CCIF1_1_CODE	 MD_IRQID_AP2MD_CCIF1_1
+#define 	IRQ_RXDFE_RXK_READBACK_CODE	 MD_IRQID_RXDFE_RXK_READBACK
+#define 	IRQ_BR_DMA_IRQ_CODE	 MD_IRQID_BR_DMA_IRQ
+#define 	IRQ_IDC_PM_INT_CODE	 MD_IRQID_IDC_PM_INT
+#define 	IRQ_IDC_UART_IRQ_CODE	 MD_IRQID_IDC_UART_IRQ
+#define 	IRQ_MDRTT_CODE	 MD_IRQID_MDRTT
+#define 	IRQ_MDEVDO_CODE	 MD_IRQID_MDEVDO
+#define 	IRQ_MDM2C_U3G_CODE	 MD_IRQID_MDM2C_U3G
+#define 	IRQ_MDDFE_DUMP_CODE	 MD_IRQID_MDDFE_DUMP
+#define 	IRQ_RAKE_CMIF_M2C_IRQ_0_CODE	 MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define 	IRQ_RAKE_CMIF_M2C_IRQ_1_CODE	 MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define 	IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE	 MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define 	IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE	 MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define 	IRQ_RAKE_CMIF_PD_DO_IRQ_CODE	 MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define 	IRQ_BIGRAM_IRQ_CODE	 MD_IRQID_BIGRAM_IRQ
+#define 	IRQ_BR_BDGE_IRQ_CODE	 MD_IRQID_BR_BDGE_IRQ
+#define 	IRQ_L1_LTE_SLEEP_IRQ_CODE	 MD_IRQID_L1_LTE_SLEEP_IRQ
+#define 	IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE	 MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define 	IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE	 MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define 	IRQ_L1M_PHY_LTMR_IRQ_0_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define 	IRQ_L1M_PHY_LTMR_IRQ_1_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define 	IRQ_L1M_PHY_LTMR_IRQ_2_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define 	IRQ_L1M_PHY_LTMR_IRQ_3_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define 	IRQ_L1M_PHY_LTMR_IRQ_4_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define 	IRQ_L1M_PHY_LTMR_IRQ_5_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define 	IRQ_L1M_PHY_LTMR_IRQ_6_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define 	IRQ_L1M_PHY_LTMR_IRQ_7_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define 	IRQ_L1_LTE_WAKEUP_IRQ_CODE	 MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define 	IRQ_MDL1_TOPSM_IRQ_CODE	 MD_IRQID_MDL1_TOPSM_IRQ
+#define 	IRQ_TDD_WAKEUP_IRQ_CODE	 MD_IRQID_TDD_WAKEUP_IRQ
+#define 	IRQ_TDD_TIMER_L1D_1_IRQ_CODE	 MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define 	IRQ_TDD_TIMER_L1D_2_IRQ_CODE	 MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define 	IRQ_RTR_FRAME_IRQ_CODE	 MD_IRQID_RTR_FRAME_IRQ
+#define 	IRQ_RTR_SLT_0_IRQ_CODE	 MD_IRQID_RTR_SLT_0_IRQ
+#define 	IRQ_RTR_SLT_1_IRQ_CODE	 MD_IRQID_RTR_SLT_1_IRQ
+#define 	IRQ_FDD_SLP_IRQ_CODE	 MD_IRQID_FDD_SLP_IRQ
+#define 	IRQ_TDMA_WAKEUP_IRQ_CODE	 MD_IRQID_TDMA_WAKEUP_IRQ
+#define 	IRQ_MD_DVFS_CTRL_IRQ_CODE	 MD_IRQID_MD_DVFS_CTRL_IRQ
+#define 	IRQ_BSI_MM_I_IRQ_RFIC_CODE	 MD_IRQID_BSI_MM_I_IRQ_RFIC
+#define 	IRQ_BSI_MM_I_IRQ_MIPI_CODE	 MD_IRQID_BSI_MM_I_IRQ_MIPI
+#define 	IRQ_ST1X_CPINT_CODE	 MD_IRQID_ST1X_CPINT
+#define 	IRQ_ST1x_HALF_CPINT_CODE	 MD_IRQID_ST1x_HALF_CPINT
+#define 	IRQ_ST1x_CFG_CPINT_CODE	 MD_IRQID_ST1x_CFG_CPINT
+#define 	IRQ_ST1x_WAKEUP_IRQ_CODE	 MD_IRQID_ST1x_WAKEUP_IRQ
+#define 	IRQ_STDO_CPINT_CODE	 MD_IRQID_STDO_CPINT
+#define 	IRQ_STDO_HALF_CPINT_CODE	 MD_IRQID_STDO_HALF_CPINT
+#define 	IRQ_STDO_CFG_CPINT_CODE	 MD_IRQID_STDO_CFG_CPINT
+#define 	IRQ_STDO_WAKEUP_IRQ_CODE	 MD_IRQID_STDO_WAKEUP_IRQ
+#define 	IRQ_FREQM_IRQ_CODE	 MD_IRQID_FREQM_IRQ
+#define 	IRQ_SPM2MD_DVFS_MDPERISYS_CODE	 MD_IRQID_SPM2MD_DVFS_MDPERISYS
+#define 	IRQ_TXDFE_BB_IRQ_CODE	 MD_IRQID_TXDFE_BB_IRQ
+#define 	IRQ_PCC_TOP_FULL_IRQ_CODE	 MD_IRQID_PCC_TOP_FULL_IRQ
+#define 	IRQ_GPTM1_CODE	 MD_IRQID_GPTM1
+#define 	IRQ_GPTM2_CODE	 MD_IRQID_GPTM2
+#define 	IRQ_GPTM3_CODE	 MD_IRQID_GPTM3
+#define 	IRQ_GPTM4_CODE	 MD_IRQID_GPTM4
+#define 	IRQ_GPTM5_CODE	 MD_IRQID_GPTM5
+#define 	IRQ_GPTM6_CODE	 MD_IRQID_GPTM6
+#define 	IRQ_GPTM7_CODE	 MD_IRQID_GPTM7
+#define 	IRQ_GPTM8_CODE	 MD_IRQID_GPTM8
+#define 	IRQ_GPTM9_CODE	 MD_IRQID_GPTM9
+#define 	IRQ_GPTM10_CODE	 MD_IRQID_GPTM10
+#define 	IRQ_GPTM11_CODE	 MD_IRQID_GPTM11
+#define 	IRQ_BUSMPU_IRQ_CODE	 MD_IRQID_BUSMPU_IRQ
+#define 	IRQ_SW_LISR1_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_0
+#define 	IRQ_SW_LISR2_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_1
+#define 	IRQ_SW_LISR3_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_2
+#define 	IRQ_SW_LISR4_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_3
+#define 	IRQ_SW_LISR5_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_4
+#define 	IRQ_SW_LISR6_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_5
+#define 	IRQ_SW_LISR7_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_6
+#define 	IRQ_SW_LISR8_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_7
+#define 	IRQ_SW_LISR9_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_8
+#define 	IRQ_SW_LISR10_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_9
+#define 	IRQ_SW_LISR11_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_10
+#define 	IRQ_SW_LISR12_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_11
+#define 	IRQ_SW_LISR13_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_12
+#define 	IRQ_SW_LISR14_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_13
+#define 	IRQ_SW_LISR15_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_14
+#define 	IRQ_SW_LISR16_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_15
+#define 	IRQ_SW_LISR17_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_16
+#define 	IRQ_SW_LISR18_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_17
+#define 	IRQ_SW_LISR19_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_18
+#define 	IRQ_SW_LISR20_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_19
+#define 	IRQ_SW_LISR21_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_20
+#define 	IRQ_SW_LISR22_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_21
+#define 	IRQ_SW_LISR23_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_22
+#define 	IRQ_SW_LISR24_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_23
+#define 	IRQ_SW_LISR25_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_24
+#define 	IRQ_SW_LISR26_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_25
+#define 	IRQ_SW_LISR27_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_26
+#define 	IRQ_SW_LISR28_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_27
+#define 	IRQ_SW_LISR29_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_28
+#define 	IRQ_SW_LISR30_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_29
+#define 	IRQ_SW_LISR31_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_30
+#define 	IRQ_SW_LISR32_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_31
+#define 	IRQ_SW_LISR33_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_32
+#define 	IRQ_SW_LISR34_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_33
+#define 	IRQ_SW_LISR35_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_34
+#define 	IRQ_SW_LISR36_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_35
+#define 	IRQ_SW_LISR37_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_36
+#define 	IRQ_SW_LISR38_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_37
+#define 	IRQ_SW_LISR39_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_38
+#define 	IRQ_SW_LISR40_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_39
+#define 	IRQ_SW_LISR41_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_40
+#define 	IRQ_SW_LISR42_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_41
+#define 	IRQ_SW_LISR43_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_42
+#define 	IRQ_SW_LISR44_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_43
+#define 	IRQ_SW_LISR45_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_44
+#define 	IRQ_SW_LISR46_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_45
+#define 	IRQ_SW_LISR47_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_46
+#define 	IRQ_SW_LISR48_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_47
+#define 	IRQ_SW_LISR49_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_48
+#define 	IRQ_SW_LISR50_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_49
+#define 	IRQ_SW_LISR51_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_50
+#define 	IRQ_SW_LISR52_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_51
+#define 	IRQ_SW_LISR53_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_52
+#define 	IRQ_SW_LISR54_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_53
+#define 	IRQ_SW_LISR55_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_54
+#define 	IRQ_SW_LISR56_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_55
+#define 	IRQ_SW_LISR57_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_56
+#define 	IRQ_SW_LISR58_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_57
+#define 	IRQ_SW_LISR59_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_58
+#define 	IRQ_SW_LISR60_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_59
+#define 	IRQ_SW_LISR61_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_60
+#define 	IRQ_SW_LISR62_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_61
+#define 	IRQ_SW_LISR63_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_62
+#define 	IRQ_SW_LISR64_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_63
+#define     MCU_BUS_DECERR_CODE  MD_IRQID_MCU_BUS_DECERR
+#define     GIC0_FDCInt_CODE  MD_IRQID_GIC0_FDCInt
+#define     GIC0_FDCInt_1_CODE  MD_IRQID_GIC0_FDCInt_1
+#define     GIC0_PCInt_CODE  MD_IRQID_GIC0_PCInt
+#define     GIC0_PCInt_1_CODE  MD_IRQID_GIC0_PCInt_1
+#define     GIC0_TimerInt_CODE  MD_IRQID_GIC0_TimerInt
+#define     GIC0_TimerInt_1_CODE  MD_IRQID_GIC0_TimerInt_1
+#define     GIC1_FDCInt_CODE  MD_IRQID_GIC1_FDCInt
+#define     GIC1_FDCInt_1_CODE  MD_IRQID_GIC1_FDCInt_1
+#define     GIC1_PCInt_CODE  MD_IRQID_GIC1_PCInt
+#define     GIC1_PCInt_1_CODE  MD_IRQID_GIC1_PCInt_1
+#define     GIC1_TimerInt_CODE  MD_IRQID_GIC1_TimerInt
+#define     GIC1_TimerInt_1_CODE  MD_IRQID_GIC1_TimerInt_1
+#define     IRQ_EINT3_CODE  MD_IRQID_EINT3
+#define     MCUMMU_INT_CODE  MD_IRQID_MCUMMU_INT
+#define     SPRAM_DECERR_CODE  MD_IRQID_IA_DECERR
+#define     RMPU_CTIREIGIN_CODE  MD_IRQID_RMPU_CTIREIGIN
+#define     MDSM_CORE_PWR_CTRL_CODE  MD_IRQID_MDSM_CORE_PWR_CTRL
+#define     AP2MD_MSDC0_CODE  MD_IRQID_AP2MD_MSDC0
+
+
+
+/*
+ * Define IRQ selection register assignment
+ */
+#define IRQSel()
+//#define INVALID_ISR_ID           (0xFF)
+
+#define INTERRUPT_PRIORITY_LIST \
+/*  0 ~  7 */  69, 127,  67,  68,  66,  38,  32,  61, \
+/*  8 ~ 15 */  88,  78, 127, 127, 127, 127, 127, 127, \
+/* 16 ~ 23 */ 127, 110,  42, 127, 127, 127, 127, 127, \
+/* 24 ~ 31 */ 127, 127,  64, 127, 127, 123, 124, 122, \
+/* 32 ~ 39 */ 127,   6,   7, 127,   6, 127, 127, 127, \
+/* 40 ~ 47 */ 127,  71,  41,  39,  62,  45, 127, 127, \
+/* 48 ~ 55 */ 127, 127, 127, 127, 127, 127, 117, 118, \
+/* 56 ~ 63 */ 119, 120, 126, 127,   6,   6,   6,   6, \
+/* 64 ~ 71 */ 110, 110, 127, 127, 127, 127, 127, 127, \
+/* 72 ~ 79 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 80 ~ 87 */  45, 127, 127, 127,  56,  54, 127, 115, \
+/* 88 ~ 95 */  58,  36,  55,  33,  86,   6,   6,  51, \
+/* 96 ~103 */  40,  47,  30, 127,  46,  43,  43,  43, \
+/*104 ~111 */  46,  44,  28,  86,  27,  34,  35, 110, \
+/*112 ~119 */  31,  49,  26,  64,  25, 127, 127,  59, \
+/*120 ~127 */ 110,  58,  29,  59,  59,  58,  29,  90, \
+/*128 ~135 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*136 ~143 */  70,  77,  44, 127, 127, 127, 127, 127, \
+/*144 ~151 */ 110, 127, 110,   7,   7,  76,  71,  77, \
+/*152 ~159 */  50,  51,  52,  79,  76,  77,  39,  72, \
+/*160 ~167 */  74,  75,  48, 127, 127,  63,   8, 127, \
+/*168 ~175 */ 110, 127, 110, 110,   6, 127, 127, 127, \
+/*176 ~183 */  75,  75, 127, 127,   7, 111,   7, 111, \
+/*184 ~191 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*192 ~199 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*200 ~207 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*208 ~215 */ 127, 110, 127, 110, 127, 110, 127, 110, \
+/*216 ~223 */ 127, 110, 127, 110, 127, 127, 127,   6, \
+/*224 ~231 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*232 ~239 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*240 ~247 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*248 ~255 */ 127, 127, 127, 127, 127, 127, 127, 127,
+
+#if defined(__ESL_MASE__)
+
+/* for OS ICC
+   IRQ_SW_LISR1_CODE
+   IRQ_SW_LISR2_CODE
+   IRQ_SW_LISR3_CODE
+   IRQ_SW_LISR4_CODE
+*/
+#define INTERRUPT_GROUP_LIST \
+	/*	0 ~  7 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*	8 ~ 15 */  0,  0,  0,  1,  0,  0,  0,  0, \
+	/* 16 ~ 23 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 24 ~ 31 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 32 ~ 39 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 40 ~ 47 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 48 ~ 55 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 56 ~ 63 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 64 ~ 71 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 72 ~ 79 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 80 ~ 87 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 88 ~ 95 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 96 ~103 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*104 ~111 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*112 ~119 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*120 ~127 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*128 ~135 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*136 ~143 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*144 ~151 */  1,  2,  3,  0,  0,  0,  0,  0, \
+	/*152 ~159 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*160 ~167 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*168 ~175 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*176 ~183 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*184 ~191 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*192 ~199 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*200 ~207 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*208 ~215 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*216 ~223 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*224 ~231 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*232 ~239 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*240 ~247 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*248 ~255 */  0,  0,  0,  0,  0,  0,  0,  0
+#else  /* __ESL_MASE__*/ 
+#define INTERRUPT_GROUP_LIST \
+	/*  0 ~  7 */  1,  4,  1,  1,  1,  1,  1,  0, \
+	/*  8 ~ 15 */  1,  1, 17,  4,  4,  0,  4,  4, \
+	/* 16 ~ 23 */  4,  1,  1,  4,  4,  4,  4,  4, \
+	/* 24 ~ 31 */  4,  4,  1,  4,  4,  4,  4,  4, \
+	/* 32 ~ 39 */  0,  5,  0,  4,  5,  4,  4,  4, \
+	/* 40 ~ 47 */  4,  0,  1,  1,  1,  3,  4,  4, \
+	/* 48 ~ 55 */  4,  4,  0,  0,  4,  4,  4,  4, \
+	/* 56 ~ 63 */  4,  4,  4,  4,  5,  5,  5,  5, \
+	/* 64 ~ 71 */  1,  3,  0,  4,  4,  4,  4,  4, \
+	/* 72 ~ 79 */  4,  4,  4,  4,  4,  5,  4,  4, \
+	/* 80 ~ 87 */  3,  4,  4,  0,  1,  1,  4,  4, \
+	/* 88 ~ 95 */  1,  1,  1,  1,  1,  5,  5,  3, \
+	/* 96 ~103 */  1,  3,  1,  4,  3,  1,  1,  1, \
+	/*104 ~111 */  3,  3,  3,  0,  1,  1,  1,  1, \
+	/*112 ~119 */  1,  3,  1,  1,  0,  4,  4,  1, \
+	/*120 ~127 */  1,  1,  1,  1,  1,  1,  1,  0, \
+	/*128 ~135 */  4,  4,  0,  4,  4,  4,  4,  4, \
+	/*136 ~143 */  1,  1,  3,  4,  4,  4,  4,  0, \
+	/*144 ~151 */  1,  2,  3,  0,  2,  1,  1,  1, \
+	/*152 ~159 */  3,  1,  3,  1,  1,  1,  1,  1, \
+	/*160 ~167 */  1,  1,  6,  5,  4,  1,  0,  0, \
+	/*168 ~175 */  1,  2,  3,  1,  5, 16,  0,  2, \
+	/*176 ~183 */  1,  1,  0,  2,  0,  1,  2,  3, \
+	/*184 ~191 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*192 ~199 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*200 ~207 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*208 ~215 */  0,  1,  0,  1,  0,  1,  2,  3, \
+	/*216 ~223 */  2,  3,  2,  3,  4,  4,  4,  4, \
+	/*224 ~231 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*232 ~239 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*240 ~247 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*248 ~255 */  4,  4,  4,  4,  4,  4,  4,  4
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+	/* Group0(0) */                0xE, \
+	/* Group1(1) */                0xD, \
+	/* Group2(2) */                0xB, \
+	/* Group3(3) */                0x7, \
+	/* Group4(0,2) */              0xA, \
+	/* Group5(0,1,2,3) */          0x0, \
+	/* Group6(1,3) */              0x5, \
+	/* Group7 */                   0xF, \
+	/* Group8 */                   0xF, \
+	/* Group9 */                   0xF, \
+	/* Group10 */                  0xF, \
+	/* Group11 */                  0xF, \
+	/* Group12 */                  0xF, \
+	/* Group13 */                  0xF, \
+	/* Group14*/                   0xF, \
+	/* Group15 */                  0xF,
+#endif
+
+#define NMI_GROUP_M2V_LIST \
+	/* Group0(exception usage) */  0xF, \
+	/* Group1 */                   0x0,
+
+#if defined(__MDCIRQ_WAIT_MODE_ENABLE__)
+#define INTERRUPT_BROADCAST_TYPE \
+	/*  0-31 */                0x040627FD, \
+	/* 32-63 */                0xF00C3E17, \
+	/* 64-95 */                0xFF392007, \
+	/* 96-127 */               0xFF9FFFF7, \
+	/* 128-159 */              0xFFFF8704, \
+	/* 160-191 */              0x00FFDFFF, \
+	/* 192-223 */              0x0FFF0000, \
+	/* 224-255 */              0x00000000,
+#else
+#define INTERRUPT_BROADCAST_TYPE \
+	/*  0-31 */                0x00000400, \
+	/* 32-63 */                0xF0000012, \
+	/* 64-95 */                0x60002000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x0000101C, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000,
+#endif
+
+#define INTERRUPT_TYPE \
+	/*  0-31 */                0x00000400, \
+	/* 32-63 */                0x00000000, \
+	/* 64-95 */                0x00000000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x00002000, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000,
+
+#define INTERRUPT_HRT_MT \
+	/*  0-31 */                0x00000000, \
+	/* 32-63 */                0x00000000, \
+	/* 64-95 */                0x00000000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x00000000, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000,
+
+
+#define INTERRUPT_TIMING_THRESHOLD \
+	/*	VPE0 */  0xFFFFFFFF,\
+	/*	VPE1 */  0xFFFFFFFF,\
+	/*	VPE2 */  0xFFFFFFFF,\
+	/*	VPE3 */  0xFFFFFFFF,
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+//#define EINT_TOTAL_CHANNEL 16
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+    VPE_STATUS_DORMANT           = 0,
+    VPE_STATUS_LISR_HIGHEST      = 1,
+    VPE_STATUS_LISR_LOWEST       = 127,
+    VPE_STATUS_HISR_TASK_HIGHEST = 128,
+    VPE_STATUS_HISR_TASK_LOWEST  = 386, 
+    VPE_STATUS_END               = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+    IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+    IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+    IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+    IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+    IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+    IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+    IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+    IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+    IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+    IRQ_MDWDT = IRQ_MDWDT_CODE,
+    IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+    IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+    IRQ_OST = IRQ_OST_CODE,
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+    IRQ_USIM1 = IRQ_USIM1_CODE,
+    IRQ_TOPSM = IRQ_TOPSM_CODE,
+    IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+    IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+    IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+    IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+    IRQ_EINT0 = IRQ_EINT0_CODE,
+    IRQ_EINT1 = IRQ_EINT1_CODE,
+    IRQ_EINT2 = IRQ_EINT2_CODE,
+    IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+    IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+    IRQ_TXBRP0 = IRQ_TXBRP0_CODE,
+    IRQ_TXBRP1 = IRQ_TXBRP1_CODE,
+    IRQ_TXCRP = IRQ_TXCRP_CODE,
+    IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+    IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+    IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+    IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+    IRQ_ECT = IRQ_ECT_CODE,
+    IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+    IRQ_CLDMA = IRQ_CLDMA_CODE,
+    IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+    IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+    IRQ_SOE = IRQ_SOE_CODE,
+    IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+    IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+    IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+    IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+    IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+    IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+    IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+    IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+    IRQ_USIP2_1 = IRQ_USIP2_1_CODE,
+    IRQ_USIP3_1 = IRQ_USIP3_1_CODE,
+    IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+    IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+    IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+    IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+    IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+    IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+    IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+    IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+    IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+    IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+    IRQ_PTP_SLPCTL_EVENT = IRQ_PTP_SLPCTL_EVENT_CODE,
+    IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+    IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+    IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+    IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+    IRQ_MDCIRQ_WDT0 = IRQ_MDCIRQ_WDT0_CODE,
+    IRQ_MDCIRQ_WDT1 = IRQ_MDCIRQ_WDT1_CODE,
+    IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+    IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+    IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+    IRQ_DCXO_RDY_WO_ACK_IRQ = IRQ_DCXO_RDY_WO_ACK_IRQ_CODE,
+    IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+    IRQ_TOP_PLL_DSNS_IRQ = IRQ_TOP_PLL_DSNS_IRQ_CODE,
+    IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+    IRQ_SSUSB_USB_MCU = IRQ_SSUSB_USB_MCU_CODE,
+    IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+    IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+    IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+    IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+    IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+    IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+    IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+    IRQ_BR_DMA_IRQ = IRQ_BR_DMA_IRQ_CODE,
+    IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+    IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+    IRQ_MDRTT = IRQ_MDRTT_CODE,
+    IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+    IRQ_MDM2C_U3G = IRQ_MDM2C_U3G_CODE,
+    IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+    IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+    IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+    IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+    IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+    IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+    IRQ_MDL1_TOPSM_IRQ = IRQ_MDL1_TOPSM_IRQ_CODE,
+    IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+    IRQ_RTR_FRAME_IRQ = IRQ_RTR_FRAME_IRQ_CODE,
+    IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+    IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+    IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+    IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+    IRQ_MD_DVFS_CTRL_IRQ = IRQ_MD_DVFS_CTRL_IRQ_CODE,
+    IRQ_BSI_MM_I_IRQ_RFIC = IRQ_BSI_MM_I_IRQ_RFIC_CODE,
+    IRQ_BSI_MM_I_IRQ_MIPI = IRQ_BSI_MM_I_IRQ_MIPI_CODE,
+    IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+    IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+    IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+    IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+    IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+    IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+    IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+    IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+    IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+    IRQ_SPM2MD_DVFS_MDPERISYS = IRQ_SPM2MD_DVFS_MDPERISYS_CODE,
+    IRQ_TXDFE_BB_IRQ = IRQ_TXDFE_BB_IRQ_CODE,
+    IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+    IRQ_GPTM1 = IRQ_GPTM1_CODE,
+    IRQ_GPTM2 = IRQ_GPTM2_CODE,
+    IRQ_GPTM3 = IRQ_GPTM3_CODE,
+    IRQ_GPTM4 = IRQ_GPTM4_CODE,
+    IRQ_GPTM5 = IRQ_GPTM5_CODE,
+    IRQ_GPTM6 = IRQ_GPTM6_CODE,
+    IRQ_GPTM7 = IRQ_GPTM7_CODE,
+    IRQ_GPTM8 = IRQ_GPTM8_CODE,
+    IRQ_GPTM9 = IRQ_GPTM9_CODE,
+    IRQ_GPTM10 = IRQ_GPTM10_CODE,
+    IRQ_GPTM11 = IRQ_GPTM11_CODE,
+    IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+    IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+    IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+    IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+    IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+    IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+    IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+    IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+    IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+    IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+    IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+    IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+    IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+    IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+    IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+    IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+    IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+    IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+    IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+    IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+    IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+    IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+    IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+    IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+    IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+    IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+    IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+    IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+    IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+    IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+    IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+    IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+    IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+    IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+    IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+    IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+    IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+    IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+    IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+    IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+    IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+    IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+    IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+    IRQ_SW_LISR43 = IRQ_SW_LISR43_CODE,
+    IRQ_SW_LISR44 = IRQ_SW_LISR44_CODE,
+    IRQ_SW_LISR45 = IRQ_SW_LISR45_CODE,
+    IRQ_SW_LISR46 = IRQ_SW_LISR46_CODE,
+    IRQ_SW_LISR47 = IRQ_SW_LISR47_CODE,
+    IRQ_SW_LISR48 = IRQ_SW_LISR48_CODE,
+    IRQ_SW_LISR49 = IRQ_SW_LISR49_CODE,
+    IRQ_SW_LISR50 = IRQ_SW_LISR50_CODE,
+    IRQ_SW_LISR51 = IRQ_SW_LISR51_CODE,
+    IRQ_SW_LISR52 = IRQ_SW_LISR52_CODE,
+    IRQ_SW_LISR53 = IRQ_SW_LISR53_CODE,
+    IRQ_SW_LISR54 = IRQ_SW_LISR54_CODE,
+    IRQ_SW_LISR55 = IRQ_SW_LISR55_CODE,
+    IRQ_SW_LISR56 = IRQ_SW_LISR56_CODE,
+    IRQ_SW_LISR57 = IRQ_SW_LISR57_CODE,
+    IRQ_SW_LISR58 = IRQ_SW_LISR58_CODE,
+    IRQ_SW_LISR59 = IRQ_SW_LISR59_CODE,
+    IRQ_SW_LISR60 = IRQ_SW_LISR60_CODE,
+    IRQ_SW_LISR61 = IRQ_SW_LISR61_CODE,
+    IRQ_SW_LISR62 = IRQ_SW_LISR62_CODE,
+    IRQ_SW_LISR63 = IRQ_SW_LISR63_CODE,
+    IRQ_SW_LISR64 = IRQ_SW_LISR64_CODE,
+    MCU_BUS_DECERR = MCU_BUS_DECERR_CODE,
+    GIC0_FDCInt = GIC0_FDCInt_CODE,
+    GIC0_FDCInt_1 = GIC0_FDCInt_1_CODE,
+    GIC0_PCInt = GIC0_PCInt_CODE,
+    GIC0_PCInt_1 = GIC0_PCInt_1_CODE,
+    GIC0_TimerInt = GIC0_TimerInt_CODE,
+    GIC0_TimerInt_1 = GIC0_TimerInt_1_CODE,
+    GIC1_FDCInt = GIC1_FDCInt_CODE,
+    GIC1_FDCInt_1 = GIC1_FDCInt_1_CODE,
+    GIC1_PCInt = GIC1_PCInt_CODE,
+    GIC1_PCInt_1 = GIC1_PCInt_1_CODE,
+    GIC1_TimerInt = GIC1_TimerInt_CODE,
+    GIC1_TimerInt_1 = GIC1_TimerInt_1_CODE,
+    IRQ_EINT3 = IRQ_EINT3_CODE,
+    MCUMMU_INT = MCUMMU_INT_CODE,
+    SPRAM_DECERR = SPRAM_DECERR_CODE,
+    RMPU_CTIREIGIN = RMPU_CTIREIGIN_CODE,
+    MDSM_CORE_PWR_CTRL = MDSM_CORE_PWR_CTRL_CODE,
+    AP2MD_MSDC0 = AP2MD_MSDC0_CODE 
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+    GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+
+#endif /* end of __INTRCTRL_MT6739_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6739_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6739_SW_Handle.h
new file mode 100644
index 0000000..0d69b67
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6739_SW_Handle.h
@@ -0,0 +1,290 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6739_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   MT6739
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 10 2017 yen-chun.liu
+ * [MOLY00270029] [System Service][KAL] Gen93 dummy LISR APIs
+ * dummy LISR driver code.
+ *
+ * 08 03 2017 yen-chun.liu
+ * [MOLY00267971] [SWLA] New Snapshot API for Robust Modem Feature
+ * 2 new SW IRQ for SWLA.
+ *
+ * 06 13 2017 yen-chun.liu
+ * [MOLY00244660] [MT6739][Gen93][System Service][MDCIRQ] Compile option for ZION(MT6739)
+ * .
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE1 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE2 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE3 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE4 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE5 = HC Yang
+      SW_TRIGGER_CODE6 = HC Yang
+      SW_TRIGGER_CODE7 = Max Weng
+      SW_TRIGGER_CODE8 = Max Weng
+      SW_TRIGGER_CODE9 = Max Weng
+      SW_TRIGGER_CODE10 = Max Weng
+      SW_TRIGGER_CODE11 = Max Weng
+      SW_TRIGGER_CODE12 = Max Weng
+      SW_TRIGGER_CODE13 = Zengling Jin
+      SW_TRIGGER_CODE14 = Zengling Jin
+      SW_TRIGGER_CODE15 = Zengling Jin
+      SW_TRIGGER_CODE16 = Chuansheng Zhang
+      SW_TRIGGER_CODE17 = Chuansheng Zhang
+      SW_TRIGGER_CODE18 = Chuansheng Zhang
+      SW_TRIGGER_CODE19 = Chuansheng Zhang
+      SW_TRIGGER_CODE20 = Huei-Ya Chang
+      SW_TRIGGER_CODE21 = Qmei Yang
+      SW_TRIGGER_CODE22 = Tee-Yuen Chun
+      SW_TRIGGER_CODE23 = Yuni Chang
+      SW_TRIGGER_CODE24 = SY Yeh
+      SW_TRIGGER_CODE25 = Owen Ho
+      SW_TRIGGER_CODE26 = Owen Ho
+      SW_TRIGGER_CODE27 = Owen Ho
+      SW_TRIGGER_CODE28 = Owen Ho
+      SW_TRIGGER_CODE29 = Carl Kao
+      SW_TRIGGER_CODE30 = Wade Huang
+      SW_TRIGGER_CODE31 = Woody kuo
+      SW_TRIGGER_CODE32 = Jun-Ying Huang
+      SW_TRIGGER_CODE33 = Jun-Ying Huang
+      SW_TRIGGER_CODE34 = Weimin Zeng
+      SW_TRIGGER_CODE35 = Weimin Zeng
+      SW_TRIGGER_CODE36 = HW Jheng
+      SW_TRIGGER_CODE37 = HW Jheng
+      SW_TRIGGER_CODE38 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE39 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE40 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE41 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE42 = 
+      SW_TRIGGER_CODE43 = 
+      SW_TRIGGER_CODE44 = 
+      SW_TRIGGER_CODE45 = 
+      SW_TRIGGER_CODE46 = 
+      SW_TRIGGER_CODE47 = 
+      SW_TRIGGER_CODE48 = 
+      SW_TRIGGER_CODE49 = 
+      SW_TRIGGER_CODE50 = 
+      SW_TRIGGER_CODE51 = 
+      SW_TRIGGER_CODE52 = 
+      SW_TRIGGER_CODE53 = 
+      SW_TRIGGER_CODE54 = 
+      SW_TRIGGER_CODE55 = 
+      SW_TRIGGER_CODE56 = 
+      SW_TRIGGER_CODE57 = 
+      SW_TRIGGER_CODE58 = 
+      SW_TRIGGER_CODE59 = 
+      SW_TRIGGER_CODE60 = 
+      SW_TRIGGER_CODE61 = 
+      SW_TRIGGER_CODE62 = 
+      SW_TRIGGER_CODE63 = 
+      SW_TRIGGER_CODE64 = 
+  */
+#if (defined(__MIPS_IA__))
+
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
+
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6739 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6761.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6761.h
new file mode 100644
index 0000000..5550b1a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6761.h
@@ -0,0 +1,784 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6761.h
+ *
+ * Project:
+ * --------
+ *   TATAKA
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6761_H__
+#define __INTRCTRL_MT6761_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES          (256)
+
+#define 	IRQ_SHARE_D12MINT1_CODE	 MD_IRQID_SHARE_D12MINT1
+#define 	IRQ_IRDBG_MCU_INT_CODE	 MD_IRQID_IRDBG_MCU_INT
+#define 	IRQ_TDMA_CTIRQ1_CODE	 MD_IRQID_TDMA_CTIRQ1
+#define 	IRQ_TDMA_CTIRQ2_CODE	 MD_IRQID_TDMA_CTIRQ2
+#define 	IRQ_TDMA_CTIRQ3_CODE	 MD_IRQID_TDMA_CTIRQ3
+#define 	IRQ_CSSYS_FDD_CS_IRQ_CODE	 MD_IRQID_CSSYS_FDD_CS_IRQ
+#define 	IRQ_CSSYS_TDD_CS_IRQ_CODE	 MD_IRQID_CSSYS_TDD_CS_IRQ
+#define 	IRQ_CSSYS_LTE_CS_IRQ_CODE	 MD_IRQID_CSSYS_LTE_CS_IRQ
+#define 	IRQ_CSSYS_1X_CS_IRQ_CODE	 MD_IRQID_CSSYS_1X_CS_IRQ
+#define 	IRQ_CSSYS_DO_CS_IRQ_CODE	 MD_IRQID_CSSYS_DO_CS_IRQ
+#define 	IRQ_MDWDT_CODE	 MD_IRQID_MDWDT
+#define 	IRQ_UART_MD0_CODE	 MD_IRQID_UART_MD0
+#define 	IRQ_UART_MD1_CODE	 MD_IRQID_UART_MD1
+#define 	IRQ_OST_CODE	 MD_IRQID_OST
+#define 	IRQ_USIM0_CODE	 MD_IRQID_USIM0
+#define 	IRQ_USIM1_CODE	 MD_IRQID_USIM1
+#define 	IRQ_TOPSM_CODE	 MD_IRQID_TOPSM
+#define 	IRQ_MDGDMA0_CODE	 MD_IRQID_MDGDMA0
+#define 	IRQ_MDGDMA1_CODE	 MD_IRQID_MDGDMA1
+#define 	IRQ_MDGDMA2_CODE	 MD_IRQID_MDGDMA2
+#define 	IRQ_MDGDMA3_CODE	 MD_IRQID_MDGDMA3
+#define 	IRQ_EINT0_CODE	 MD_IRQID_EINT0
+#define 	IRQ_EINT1_CODE	 MD_IRQID_EINT1
+#define 	IRQ_EINT2_CODE	 MD_IRQID_EINT2
+#define 	IRQ_EINT_SHARE_CODE	 MD_IRQID_EINT_SHARE
+#define 	IRQ_BUS_ERR_CODE	 MD_IRQID_BUS_ERR
+#define 	IRQ_TXBRP0_CODE	 MD_IRQID_TXBRP0
+#define 	IRQ_TXBRP1_CODE	 MD_IRQID_TXBRP1
+#define 	IRQ_TXCRP_CODE	 MD_IRQID_TXCRP
+#define 	IRQ_MML2_HRT_CODE	 MD_IRQ_ID_MML2_HRT
+#define 	IRQ_MML2_NOTIF_CODE	 MD_IRQ_ID_MML2_NOTIF
+#define 	IRQ_MML2_EXCEP_CODE	 MD_IRQ_ID_MML2_EXCEP
+#define 	IRQ_DEM_TRIG_PS_INT_LE_CODE	 MD_IRQID_DEM_TRIG_PS_INT_LE
+#define 	IRQ_ECT_CODE	 MD_IRQID_ECT
+#define 	IRQ_PTP_THERM_INT_INT_CODE	 MD_IRQID_PTP_THERM_INT_INT
+#define 	IRQ_CLDMA_CODE	 MD_IRQID_CLDMA
+#define 	IRQ_MDINFRA_BUSMON_MATCH_STS_CODE	 MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define 	IRQ_ELM_DMA_IRQ_CODE	 MD_IRQID_ELM_DMA_IRQ
+#define 	IRQ_SOE_CODE	 MD_IRQID_SOE
+#define 	IRQ_ULSP_LOG_MD_INT_CODE	 MD_IRQID_ULSP_LOG_MD_INT
+#define 	IRQ_ULSP_LOG_DSP_INT_CODE	 MD_IRQID_ULSP_LOG_DSP_INT
+#define 	IRQ_USIP0_0_CODE	 MD_IRQID_USIP0_0
+#define 	IRQ_USIP1_0_CODE	 MD_IRQID_USIP1_0
+#define 	IRQ_USIP2_0_CODE	 MD_IRQID_USIP2_0
+#define 	IRQ_USIP3_0_CODE	 MD_IRQID_USIP3_0
+#define 	IRQ_USIP0_1_CODE	 MD_IRQID_USIP0_1
+#define 	IRQ_USIP1_1_CODE	 MD_IRQID_USIP1_1
+#define 	IRQ_AP2MD_CCIF2_0_CODE	 MD_IRQID_AP2MD_CCIF2_0
+#define 	IRQ_USIP3_1_CODE	 MD_IRQID_USIP3_1
+#define 	IRQ_SI_CM_ERR_CODE	 MD_IRQID_SI_CM_ERR
+#define 	IRQ_ABM_INT_CODE	 MD_IRQID_ABM_INT
+#define 	IRQ_ABM_ERROR_INT_CODE	 MD_IRQID_ABM_ERROR_INT
+#define 	IRQ_MDMCU_BUSMON_MATCH_STS_CODE	 MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define 	IRQ_ELMTOP_EMI_IRQ_CODE	 MD_IRQID_ELMTOP_EMI_IRQ
+#define 	IRQ_PPPHA_ENC0_INT_CODE	 MD_IRQID_PPPHA_ENC0_INT
+#define 	IRQ_PPPHA_ENC1_INT_CODE	 MD_IRQID_PPPHA_ENC1_INT
+#define 	IRQ_PPPHA_DEC0_INT_CODE	 MD_IRQID_PPPHA_DEC0_INT
+#define 	IRQ_PPPHA_DEC1_INT_CODE	 MD_IRQID_PPPHA_DEC1_INT
+#define 	IRQ_PTP_FSM_INT_CODE	 MD_IRQID_PTP_FSM_INT
+#define 	IRQ_PTP_SLPCTL_EVENT_CODE	 MD_IRQID_PTP_SLPCTL_EVENT
+#define 	IRQ_IEBIT_CHECK_IRQ0_CODE	 MD_IRQID_IEBIT_CHECK_IRQ0
+#define 	IRQ_IEBIT_CHECK_IRQ1_CODE	 MD_IRQID_IEBIT_CHECK_IRQ1
+#define 	IRQ_IEBIT_CHECK_IRQ2_CODE	 MD_IRQID_IEBIT_CHECK_IRQ2
+#define 	IRQ_IEBIT_CHECK_IRQ3_CODE	 MD_IRQID_IEBIT_CHECK_IRQ3
+#define 	IRQ_MDCIRQ_WDT0_CODE	 MD_IRQID_MDCIRQ_WDT0
+#define 	IRQ_MDCIRQ_WDT1_CODE	 MD_IRQID_MDCIRQ_WDT1
+#define 	IRQ_TRACE_INT_CODE	 MD_IRQID_TRACE_INT
+#define 	IRQ_SI_CM_PCINT_CODE	 MD_IRQID_SI_CM_PCINT
+#define 	IRQ_PLL_GEARHP_RDY_CODE	 MD_IRQID_PLL_GEARHP_RDY
+#define 	IRQ_DCXO_RDY_WO_ACK_IRQ_CODE	 MD_IRQID_DCXO_RDY_WO_ACK_IRQ
+#define 	IRQ_REQ_ABNORM_IRQ_CODE	 MD_IRQID_REQ_ABNORM_IRQ
+#define 	IRQ_TOP_PLL_DSNS_IRQ_CODE	 MD_IRQID_TOP_PLL_DSNS_IRQ
+#define 	IRQ_BT_CVSD_CODE	 MD_IRQID_BT_CVSD
+#define 	IRQ_SSUSB_USB_MCU_CODE	 MD_IRQID_SSUSB_USB_MCU
+#define 	IRQ_SSUSB_DEV_CODE	 MD_IRQID_SSUSB_DEV
+#define 	IRQ_AP2MD_DVFS_BLOCK_ELM_CODE	 MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define 	IRQ_AP2MD_CCIF0_0_CODE	 MD_IRQID_AP2MD_CCIF0_0
+#define 	IRQ_AP2MD_CCIF0_1_CODE	 MD_IRQID_AP2MD_CCIF0_1
+#define 	IRQ_AP2MD_CCIF1_0_CODE	 MD_IRQID_AP2MD_CCIF1_0
+#define 	IRQ_AP2MD_CCIF1_1_CODE	 MD_IRQID_AP2MD_CCIF1_1
+#define 	IRQ_RXDFE_RXK_READBACK_CODE	 MD_IRQID_RXDFE_RXK_READBACK
+#define 	IRQ_BR_DMA_IRQ_CODE	 MD_IRQID_BR_DMA_IRQ
+#define 	IRQ_IDC_PM_INT_CODE	 MD_IRQID_IDC_PM_INT
+#define 	IRQ_IDC_UART_IRQ_CODE	 MD_IRQID_IDC_UART_IRQ
+#define 	IRQ_MDRTT_CODE	 MD_IRQID_MDRTT
+#define 	IRQ_MDEVDO_CODE	 MD_IRQID_MDEVDO
+#define 	IRQ_MDM2C_U3G_CODE	 MD_IRQID_MDM2C_U3G
+#define 	IRQ_MDDFE_DUMP_CODE	 MD_IRQID_MDDFE_DUMP
+#define 	IRQ_RAKE_CMIF_M2C_IRQ_0_CODE	 MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define 	IRQ_RAKE_CMIF_M2C_IRQ_1_CODE	 MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define 	IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE	 MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define 	IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE	 MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define 	IRQ_RAKE_CMIF_PD_DO_IRQ_CODE	 MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define 	IRQ_BIGRAM_IRQ_CODE	 MD_IRQID_BIGRAM_IRQ
+#define 	IRQ_BR_BDGE_IRQ_CODE	 MD_IRQID_BR_BDGE_IRQ
+#define 	IRQ_L1_LTE_SLEEP_IRQ_CODE	 MD_IRQID_L1_LTE_SLEEP_IRQ
+#define 	IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE	 MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define 	IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE	 MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define 	IRQ_L1M_PHY_LTMR_IRQ_0_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define 	IRQ_L1M_PHY_LTMR_IRQ_1_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define 	IRQ_L1M_PHY_LTMR_IRQ_2_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define 	IRQ_L1M_PHY_LTMR_IRQ_3_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define 	IRQ_L1M_PHY_LTMR_IRQ_4_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define 	IRQ_L1M_PHY_LTMR_IRQ_5_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define 	IRQ_L1M_PHY_LTMR_IRQ_6_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define 	IRQ_L1M_PHY_LTMR_IRQ_7_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define 	IRQ_L1_LTE_WAKEUP_IRQ_CODE	 MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define 	IRQ_MDL1_TOPSM_IRQ_CODE	 MD_IRQID_MDL1_TOPSM_IRQ
+#define 	IRQ_TDD_WAKEUP_IRQ_CODE	 MD_IRQID_TDD_WAKEUP_IRQ
+#define 	IRQ_TDD_TIMER_L1D_1_IRQ_CODE	 MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define 	IRQ_TDD_TIMER_L1D_2_IRQ_CODE	 MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define 	IRQ_RTR_FRAME_IRQ_CODE	 MD_IRQID_RTR_FRAME_IRQ
+#define 	IRQ_RTR_SLT_0_IRQ_CODE	 MD_IRQID_RTR_SLT_0_IRQ
+#define 	IRQ_RTR_SLT_1_IRQ_CODE	 MD_IRQID_RTR_SLT_1_IRQ
+#define 	IRQ_FDD_SLP_IRQ_CODE	 MD_IRQID_FDD_SLP_IRQ
+#define 	IRQ_TDMA_WAKEUP_IRQ_CODE	 MD_IRQID_TDMA_WAKEUP_IRQ
+#define 	IRQ_MD_DVFS_CTRL_IRQ_CODE	 MD_IRQID_MD_DVFS_CTRL_IRQ
+#define 	IRQ_BSI_MM_I_IRQ_RFIC_CODE	 MD_IRQID_BSI_MM_I_IRQ_RFIC
+#define 	IRQ_BSI_MM_I_IRQ_MIPI_CODE	 MD_IRQID_BSI_MM_I_IRQ_MIPI
+#define 	IRQ_ST1X_CPINT_CODE	 MD_IRQID_ST1X_CPINT
+#define 	IRQ_ST1x_HALF_CPINT_CODE	 MD_IRQID_ST1x_HALF_CPINT
+#define 	IRQ_ST1x_CFG_CPINT_CODE	 MD_IRQID_ST1x_CFG_CPINT
+#define 	IRQ_ST1x_WAKEUP_IRQ_CODE	 MD_IRQID_ST1x_WAKEUP_IRQ
+#define 	IRQ_STDO_CPINT_CODE	 MD_IRQID_STDO_CPINT
+#define 	IRQ_STDO_HALF_CPINT_CODE	 MD_IRQID_STDO_HALF_CPINT
+#define 	IRQ_STDO_CFG_CPINT_CODE	 MD_IRQID_STDO_CFG_CPINT
+#define 	IRQ_STDO_WAKEUP_IRQ_CODE	 MD_IRQID_STDO_WAKEUP_IRQ
+#define 	IRQ_FREQM_IRQ_CODE	 MD_IRQID_FREQM_IRQ
+#define 	IRQ_SPM2MD_DVFS_MDPERISYS_CODE	 MD_IRQID_SPM2MD_DVFS_MDPERISYS
+#define 	IRQ_TXDFE_BB_IRQ_CODE	 MD_IRQID_TXDFE_BB_IRQ
+#define 	IRQ_PCC_TOP_FULL_IRQ_CODE	 MD_IRQID_PCC_TOP_FULL_IRQ
+#define 	IRQ_GPTM1_CODE	 MD_IRQID_GPTM1
+#define 	IRQ_GPTM2_CODE	 MD_IRQID_GPTM2
+#define 	IRQ_GPTM3_CODE	 MD_IRQID_GPTM3
+#define 	IRQ_GPTM4_CODE	 MD_IRQID_GPTM4
+#define 	IRQ_GPTM5_CODE	 MD_IRQID_GPTM5
+#define 	IRQ_GPTM6_CODE	 MD_IRQID_GPTM6
+#define 	IRQ_GPTM7_CODE	 MD_IRQID_GPTM7
+#define 	IRQ_GPTM8_CODE	 MD_IRQID_GPTM8
+#define 	IRQ_GPTM9_CODE	 MD_IRQID_GPTM9
+#define 	IRQ_GPTM10_CODE	 MD_IRQID_GPTM10
+#define 	IRQ_GPTM11_CODE	 MD_IRQID_GPTM11
+#define 	IRQ_BUSMPU_IRQ_CODE	 MD_IRQID_BUSMPU_IRQ
+#define 	IRQ_SW_LISR1_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_0
+#define 	IRQ_SW_LISR2_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_1
+#define 	IRQ_SW_LISR3_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_2
+#define 	IRQ_SW_LISR4_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_3
+#define 	IRQ_SW_LISR5_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_4
+#define 	IRQ_SW_LISR6_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_5
+#define 	IRQ_SW_LISR7_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_6
+#define 	IRQ_SW_LISR8_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_7
+#define 	IRQ_SW_LISR9_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_8
+#define 	IRQ_SW_LISR10_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_9
+#define 	IRQ_SW_LISR11_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_10
+#define 	IRQ_SW_LISR12_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_11
+#define 	IRQ_SW_LISR13_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_12
+#define 	IRQ_SW_LISR14_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_13
+#define 	IRQ_SW_LISR15_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_14
+#define 	IRQ_SW_LISR16_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_15
+#define 	IRQ_SW_LISR17_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_16
+#define 	IRQ_SW_LISR18_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_17
+#define 	IRQ_SW_LISR19_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_18
+#define 	IRQ_SW_LISR20_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_19
+#define 	IRQ_SW_LISR21_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_20
+#define 	IRQ_SW_LISR22_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_21
+#define 	IRQ_SW_LISR23_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_22
+#define 	IRQ_SW_LISR24_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_23
+#define 	IRQ_SW_LISR25_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_24
+#define 	IRQ_SW_LISR26_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_25
+#define 	IRQ_SW_LISR27_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_26
+#define 	IRQ_SW_LISR28_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_27
+#define 	IRQ_SW_LISR29_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_28
+#define 	IRQ_SW_LISR30_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_29
+#define 	IRQ_SW_LISR31_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_30
+#define 	IRQ_SW_LISR32_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_31
+#define 	IRQ_SW_LISR33_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_32
+#define 	IRQ_SW_LISR34_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_33
+#define 	IRQ_SW_LISR35_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_34
+#define 	IRQ_SW_LISR36_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_35
+#define 	IRQ_SW_LISR37_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_36
+#define 	IRQ_SW_LISR38_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_37
+#define 	IRQ_SW_LISR39_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_38
+#define 	IRQ_SW_LISR40_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_39
+#define 	IRQ_SW_LISR41_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_40
+#define 	IRQ_SW_LISR42_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_41
+#define 	IRQ_SW_LISR43_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_42
+#define 	IRQ_SW_LISR44_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_43
+#define 	IRQ_SW_LISR45_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_44
+#define 	IRQ_SW_LISR46_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_45
+#define 	IRQ_SW_LISR47_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_46
+#define 	IRQ_SW_LISR48_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_47
+#define 	IRQ_SW_LISR49_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_48
+#define 	IRQ_SW_LISR50_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_49
+#define 	IRQ_SW_LISR51_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_50
+#define 	IRQ_SW_LISR52_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_51
+#define 	IRQ_SW_LISR53_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_52
+#define 	IRQ_SW_LISR54_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_53
+#define 	IRQ_SW_LISR55_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_54
+#define 	IRQ_SW_LISR56_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_55
+#define 	IRQ_SW_LISR57_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_56
+#define 	IRQ_SW_LISR58_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_57
+#define 	IRQ_SW_LISR59_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_58
+#define 	IRQ_SW_LISR60_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_59
+#define 	IRQ_SW_LISR61_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_60
+#define 	IRQ_SW_LISR62_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_61
+#define 	IRQ_SW_LISR63_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_62
+#define 	IRQ_SW_LISR64_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_63
+#define     MCU_BUS_DECERR_CODE  MD_IRQID_MCU_BUS_DECERR
+#define     GIC0_FDCInt_CODE  MD_IRQID_GIC0_FDCInt
+#define     GIC0_FDCInt_1_CODE  MD_IRQID_GIC0_FDCInt_1
+#define     GIC0_PCInt_CODE  MD_IRQID_GIC0_PCInt
+#define     GIC0_PCInt_1_CODE  MD_IRQID_GIC0_PCInt_1
+#define     GIC0_TimerInt_CODE  MD_IRQID_GIC0_TimerInt
+#define     GIC0_TimerInt_1_CODE  MD_IRQID_GIC0_TimerInt_1
+#define     GIC1_FDCInt_CODE  MD_IRQID_GIC1_FDCInt
+#define     GIC1_FDCInt_1_CODE  MD_IRQID_GIC1_FDCInt_1
+#define     GIC1_PCInt_CODE  MD_IRQID_GIC1_PCInt
+#define     GIC1_PCInt_1_CODE  MD_IRQID_GIC1_PCInt_1
+#define     GIC1_TimerInt_CODE  MD_IRQID_GIC1_TimerInt
+#define     GIC1_TimerInt_1_CODE  MD_IRQID_GIC1_TimerInt_1
+#define     IRQ_EINT3_CODE  MD_IRQID_EINT3
+#define     MCUMMU_INT_CODE  MD_IRQID_MCUMMU_INT
+#define     SPRAM_DECERR_CODE  MD_IRQID_IA_DECERR
+#define     RMPU_CTIREIGIN_CODE  MD_IRQID_RMPU_CTIREIGIN
+#define     MDSM_CORE_PWR_CTRL_CODE  MD_IRQID_MDSM_CORE_PWR_CTRL
+#define     AP2MD_MSDC0_CODE  MD_IRQID_AP2MD_MSDC0
+
+
+
+/*
+ * Define IRQ selection register assignment
+ */
+#define IRQSel()
+//#define INVALID_ISR_ID           (0xFF)
+
+#define INTERRUPT_PRIORITY_LIST \
+/*  0 ~  7 */  69, 127,  67,  68,  66,  38,  32,  61, \
+/*  8 ~ 15 */  88,  78, 127, 127, 127, 127, 127, 127, \
+/* 16 ~ 23 */ 127, 110,  42, 127, 127, 127, 127, 127, \
+/* 24 ~ 31 */ 127, 127,  64, 127, 127, 123, 124, 122, \
+/* 32 ~ 39 */ 127,   6,   7, 127,   6, 127, 127, 127, \
+/* 40 ~ 47 */ 127,  71,  41,  39,  62,  45, 127, 127, \
+/* 48 ~ 55 */ 127, 127, 127, 127, 127, 127, 117, 118, \
+/* 56 ~ 63 */ 119, 120, 126, 127,   6,   6,   6,   6, \
+/* 64 ~ 71 */ 110, 110, 127, 127, 127, 127, 127, 127, \
+/* 72 ~ 79 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 80 ~ 87 */  45, 127, 127, 127,  56,  54, 127, 115, \
+/* 88 ~ 95 */  58,  36,  55,  33,  86,   6,   6,  51, \
+/* 96 ~103 */  40,  47,  30, 127,  46,  43,  43,  43, \
+/*104 ~111 */  46,  44,  28,  86,  27,  34,  35, 110, \
+/*112 ~119 */  31,  49,  26,  64,  25, 127, 127,  59, \
+/*120 ~127 */ 110,  58,  29,  59,  59,  58,  29,  90, \
+/*128 ~135 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*136 ~143 */  70,  77,  44, 127, 127, 127, 127, 127, \
+/*144 ~151 */ 110, 127, 110,   7,   7,  76,  71,  77, \
+/*152 ~159 */  50,  51,  52,  79,  76,  77,  39,  72, \
+/*160 ~167 */  74,  75,  48, 127, 127,  63,   8, 127, \
+/*168 ~175 */ 110, 127, 110, 110,   6, 127, 127, 127, \
+/*176 ~183 */  75,  75, 127, 127,   7, 111,   7, 111, \
+/*184 ~191 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*192 ~199 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*200 ~207 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*208 ~215 */ 127, 110, 127, 110, 127, 110, 127, 110, \
+/*216 ~223 */ 127, 110, 127, 110, 127, 127, 127,   6, \
+/*224 ~231 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*232 ~239 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*240 ~247 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*248 ~255 */ 127, 127, 127, 127, 127, 127, 127, 127,
+
+#if defined(__ESL_MASE__)
+
+/* for OS ICC
+   IRQ_SW_LISR1_CODE
+   IRQ_SW_LISR2_CODE
+   IRQ_SW_LISR3_CODE
+   IRQ_SW_LISR4_CODE
+*/
+#define INTERRUPT_GROUP_LIST \
+	/*	0 ~  7 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*	8 ~ 15 */  0,  0,  0,  1,  0,  0,  0,  0, \
+	/* 16 ~ 23 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 24 ~ 31 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 32 ~ 39 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 40 ~ 47 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 48 ~ 55 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 56 ~ 63 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 64 ~ 71 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 72 ~ 79 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 80 ~ 87 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 88 ~ 95 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 96 ~103 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*104 ~111 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*112 ~119 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*120 ~127 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*128 ~135 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*136 ~143 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*144 ~151 */  1,  2,  3,  0,  0,  0,  0,  0, \
+	/*152 ~159 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*160 ~167 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*168 ~175 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*176 ~183 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*184 ~191 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*192 ~199 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*200 ~207 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*208 ~215 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*216 ~223 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*224 ~231 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*232 ~239 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*240 ~247 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*248 ~255 */  0,  0,  0,  0,  0,  0,  0,  0
+#else  /* __ESL_MASE__*/ 
+#define INTERRUPT_GROUP_LIST \
+	/*  0 ~  7 */  1,  4,  1,  1,  1,  1,  1,  0, \
+	/*  8 ~ 15 */  1,  1, 17,  4,  4,  0,  4,  4, \
+	/* 16 ~ 23 */  4,  1,  1,  4,  4,  4,  4,  4, \
+	/* 24 ~ 31 */  4,  4,  1,  4,  4,  4,  4,  4, \
+	/* 32 ~ 39 */  0,  5,  0,  4,  5,  4,  4,  4, \
+	/* 40 ~ 47 */  4,  0,  1,  1,  1,  3,  4,  4, \
+	/* 48 ~ 55 */  4,  4,  0,  0,  4,  4,  4,  4, \
+	/* 56 ~ 63 */  4,  4,  4,  4,  5,  5,  5,  5, \
+	/* 64 ~ 71 */  1,  3,  0,  4,  4,  4,  4,  4, \
+	/* 72 ~ 79 */  4,  4,  4,  4,  4,  5,  4,  4, \
+	/* 80 ~ 87 */  3,  4,  4,  0,  1,  1,  4,  4, \
+	/* 88 ~ 95 */  1,  1,  1,  1,  1,  5,  5,  3, \
+	/* 96 ~103 */  1,  3,  1,  4,  3,  1,  1,  1, \
+	/*104 ~111 */  3,  3,  3,  0,  1,  1,  1,  1, \
+	/*112 ~119 */  1,  3,  1,  1,  0,  4,  4,  1, \
+	/*120 ~127 */  1,  1,  1,  1,  1,  1,  1,  0, \
+	/*128 ~135 */  4,  4,  0,  4,  4,  4,  4,  4, \
+	/*136 ~143 */  1,  1,  3,  4,  4,  4,  4,  0, \
+	/*144 ~151 */  1,  2,  3,  0,  2,  1,  1,  1, \
+	/*152 ~159 */  3,  1,  3,  1,  1,  1,  1,  1, \
+	/*160 ~167 */  1,  1,  6,  5,  4,  1,  0,  0, \
+	/*168 ~175 */  1,  2,  3,  1,  5, 16,  0,  2, \
+	/*176 ~183 */  1,  1,  0,  2,  0,  1,  2,  3, \
+	/*184 ~191 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*192 ~199 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*200 ~207 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*208 ~215 */  0,  1,  0,  1,  0,  1,  2,  3, \
+	/*216 ~223 */  2,  3,  2,  3,  4,  4,  4,  4, \
+	/*224 ~231 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*232 ~239 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*240 ~247 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*248 ~255 */  4,  4,  4,  4,  4,  4,  4,  4
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+	/* Group0(0) */                0xE, \
+	/* Group1(1) */                0xD, \
+	/* Group2(2) */                0xB, \
+	/* Group3(3) */                0x7, \
+	/* Group4(0,2) */              0xA, \
+	/* Group5(0,1,2,3) */          0x0, \
+	/* Group6(1,3) */              0x5, \
+	/* Group7 */                   0xF, \
+	/* Group8 */                   0xF, \
+	/* Group9 */                   0xF, \
+	/* Group10 */                  0xF, \
+	/* Group11 */                  0xF, \
+	/* Group12 */                  0xF, \
+	/* Group13 */                  0xF, \
+	/* Group14*/                   0xF, \
+	/* Group15 */                  0xF,
+#endif
+
+#define NMI_GROUP_M2V_LIST \
+	/* Group0(exception usage) */  0xF, \
+	/* Group1 */                   0x0,
+
+#if defined(__MDCIRQ_WAIT_MODE_ENABLE__)
+#define INTERRUPT_BROADCAST_TYPE \
+	/*  0-31 */                0x040627FD, \
+	/* 32-63 */                0xF00C3E17, \
+	/* 64-95 */                0xFF392007, \
+	/* 96-127 */               0xFF9FFFF7, \
+	/* 128-159 */              0xFFFF8704, \
+	/* 160-191 */              0x00FFDFFF, \
+	/* 192-223 */              0x0FFF0000, \
+	/* 224-255 */              0x00000000,
+#else
+#define INTERRUPT_BROADCAST_TYPE \
+	/*  0-31 */                0x00000400, \
+	/* 32-63 */                0xF0000012, \
+	/* 64-95 */                0x60002000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x0000101C, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000,
+#endif
+
+#define INTERRUPT_TYPE \
+	/*  0-31 */                0x00000400, \
+	/* 32-63 */                0x00000000, \
+	/* 64-95 */                0x00000000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x00002000, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000,
+
+#define INTERRUPT_HRT_MT \
+	/*  0-31 */                0x00000000, \
+	/* 32-63 */                0x00000000, \
+	/* 64-95 */                0x00000000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x00000000, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000,
+
+
+#define INTERRUPT_TIMING_THRESHOLD \
+	/*	VPE0 */  0xFFFFFFFF,\
+	/*	VPE1 */  0xFFFFFFFF,\
+	/*	VPE2 */  0xFFFFFFFF,\
+	/*	VPE3 */  0xFFFFFFFF,
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+//#define EINT_TOTAL_CHANNEL 16
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+    VPE_STATUS_DORMANT           = 0,
+    VPE_STATUS_LISR_HIGHEST      = 1,
+    VPE_STATUS_LISR_LOWEST       = 127,
+    VPE_STATUS_HISR_TASK_HIGHEST = 128,
+    VPE_STATUS_HISR_TASK_LOWEST  = 386, 
+    VPE_STATUS_END               = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+    IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+    IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+    IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+    IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+    IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+    IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+    IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+    IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+    IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+    IRQ_MDWDT = IRQ_MDWDT_CODE,
+    IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+    IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+    IRQ_OST = IRQ_OST_CODE,
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+    IRQ_USIM1 = IRQ_USIM1_CODE,
+    IRQ_TOPSM = IRQ_TOPSM_CODE,
+    IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+    IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+    IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+    IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+    IRQ_EINT0 = IRQ_EINT0_CODE,
+    IRQ_EINT1 = IRQ_EINT1_CODE,
+    IRQ_EINT2 = IRQ_EINT2_CODE,
+    IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+    IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+    IRQ_TXBRP0 = IRQ_TXBRP0_CODE,
+    IRQ_TXBRP1 = IRQ_TXBRP1_CODE,
+    IRQ_TXCRP = IRQ_TXCRP_CODE,
+    IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+    IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+    IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+    IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+    IRQ_ECT = IRQ_ECT_CODE,
+    IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+    IRQ_CLDMA = IRQ_CLDMA_CODE,
+    IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+    IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+    IRQ_SOE = IRQ_SOE_CODE,
+    IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+    IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+    IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+    IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+    IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+    IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+    IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+    IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+    IRQ_AP2MD_CCIF2_0 = IRQ_AP2MD_CCIF2_0_CODE,
+    IRQ_USIP3_1 = IRQ_USIP3_1_CODE,
+    IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+    IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+    IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+    IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+    IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+    IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+    IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+    IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+    IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+    IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+    IRQ_PTP_SLPCTL_EVENT = IRQ_PTP_SLPCTL_EVENT_CODE,
+    IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+    IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+    IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+    IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+    IRQ_MDCIRQ_WDT0 = IRQ_MDCIRQ_WDT0_CODE,
+    IRQ_MDCIRQ_WDT1 = IRQ_MDCIRQ_WDT1_CODE,
+    IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+    IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+    IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+    IRQ_DCXO_RDY_WO_ACK_IRQ = IRQ_DCXO_RDY_WO_ACK_IRQ_CODE,
+    IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+    IRQ_TOP_PLL_DSNS_IRQ = IRQ_TOP_PLL_DSNS_IRQ_CODE,
+    IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+    IRQ_SSUSB_USB_MCU = IRQ_SSUSB_USB_MCU_CODE,
+    IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+    IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+    IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+    IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+    IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+    IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+    IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+    IRQ_BR_DMA_IRQ = IRQ_BR_DMA_IRQ_CODE,
+    IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+    IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+    IRQ_MDRTT = IRQ_MDRTT_CODE,
+    IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+    IRQ_MDM2C_U3G = IRQ_MDM2C_U3G_CODE,
+    IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+    IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+    IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+    IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+    IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+    IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+    IRQ_MDL1_TOPSM_IRQ = IRQ_MDL1_TOPSM_IRQ_CODE,
+    IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+    IRQ_RTR_FRAME_IRQ = IRQ_RTR_FRAME_IRQ_CODE,
+    IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+    IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+    IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+    IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+    IRQ_MD_DVFS_CTRL_IRQ = IRQ_MD_DVFS_CTRL_IRQ_CODE,
+    IRQ_BSI_MM_I_IRQ_RFIC = IRQ_BSI_MM_I_IRQ_RFIC_CODE,
+    IRQ_BSI_MM_I_IRQ_MIPI = IRQ_BSI_MM_I_IRQ_MIPI_CODE,
+    IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+    IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+    IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+    IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+    IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+    IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+    IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+    IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+    IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+    IRQ_SPM2MD_DVFS_MDPERISYS = IRQ_SPM2MD_DVFS_MDPERISYS_CODE,
+    IRQ_TXDFE_BB_IRQ = IRQ_TXDFE_BB_IRQ_CODE,
+    IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+    IRQ_GPTM1 = IRQ_GPTM1_CODE,
+    IRQ_GPTM2 = IRQ_GPTM2_CODE,
+    IRQ_GPTM3 = IRQ_GPTM3_CODE,
+    IRQ_GPTM4 = IRQ_GPTM4_CODE,
+    IRQ_GPTM5 = IRQ_GPTM5_CODE,
+    IRQ_GPTM6 = IRQ_GPTM6_CODE,
+    IRQ_GPTM7 = IRQ_GPTM7_CODE,
+    IRQ_GPTM8 = IRQ_GPTM8_CODE,
+    IRQ_GPTM9 = IRQ_GPTM9_CODE,
+    IRQ_GPTM10 = IRQ_GPTM10_CODE,
+    IRQ_GPTM11 = IRQ_GPTM11_CODE,
+    IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+    IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+    IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+    IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+    IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+    IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+    IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+    IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+    IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+    IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+    IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+    IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+    IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+    IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+    IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+    IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+    IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+    IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+    IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+    IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+    IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+    IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+    IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+    IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+    IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+    IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+    IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+    IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+    IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+    IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+    IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+    IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+    IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+    IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+    IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+    IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+    IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+    IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+    IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+    IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+    IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+    IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+    IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+    IRQ_SW_LISR43 = IRQ_SW_LISR43_CODE,
+    IRQ_SW_LISR44 = IRQ_SW_LISR44_CODE,
+    IRQ_SW_LISR45 = IRQ_SW_LISR45_CODE,
+    IRQ_SW_LISR46 = IRQ_SW_LISR46_CODE,
+    IRQ_SW_LISR47 = IRQ_SW_LISR47_CODE,
+    IRQ_SW_LISR48 = IRQ_SW_LISR48_CODE,
+    IRQ_SW_LISR49 = IRQ_SW_LISR49_CODE,
+    IRQ_SW_LISR50 = IRQ_SW_LISR50_CODE,
+    IRQ_SW_LISR51 = IRQ_SW_LISR51_CODE,
+    IRQ_SW_LISR52 = IRQ_SW_LISR52_CODE,
+    IRQ_SW_LISR53 = IRQ_SW_LISR53_CODE,
+    IRQ_SW_LISR54 = IRQ_SW_LISR54_CODE,
+    IRQ_SW_LISR55 = IRQ_SW_LISR55_CODE,
+    IRQ_SW_LISR56 = IRQ_SW_LISR56_CODE,
+    IRQ_SW_LISR57 = IRQ_SW_LISR57_CODE,
+    IRQ_SW_LISR58 = IRQ_SW_LISR58_CODE,
+    IRQ_SW_LISR59 = IRQ_SW_LISR59_CODE,
+    IRQ_SW_LISR60 = IRQ_SW_LISR60_CODE,
+    IRQ_SW_LISR61 = IRQ_SW_LISR61_CODE,
+    IRQ_SW_LISR62 = IRQ_SW_LISR62_CODE,
+    IRQ_SW_LISR63 = IRQ_SW_LISR63_CODE,
+    IRQ_SW_LISR64 = IRQ_SW_LISR64_CODE,
+    MCU_BUS_DECERR = MCU_BUS_DECERR_CODE,
+    GIC0_FDCInt = GIC0_FDCInt_CODE,
+    GIC0_FDCInt_1 = GIC0_FDCInt_1_CODE,
+    GIC0_PCInt = GIC0_PCInt_CODE,
+    GIC0_PCInt_1 = GIC0_PCInt_1_CODE,
+    GIC0_TimerInt = GIC0_TimerInt_CODE,
+    GIC0_TimerInt_1 = GIC0_TimerInt_1_CODE,
+    GIC1_FDCInt = GIC1_FDCInt_CODE,
+    GIC1_FDCInt_1 = GIC1_FDCInt_1_CODE,
+    GIC1_PCInt = GIC1_PCInt_CODE,
+    GIC1_PCInt_1 = GIC1_PCInt_1_CODE,
+    GIC1_TimerInt = GIC1_TimerInt_CODE,
+    GIC1_TimerInt_1 = GIC1_TimerInt_1_CODE,
+    IRQ_EINT3 = IRQ_EINT3_CODE,
+    MCUMMU_INT = MCUMMU_INT_CODE,
+    SPRAM_DECERR = SPRAM_DECERR_CODE,
+    RMPU_CTIREIGIN = RMPU_CTIREIGIN_CODE,
+    MDSM_CORE_PWR_CTRL = MDSM_CORE_PWR_CTRL_CODE,
+    AP2MD_MSDC0 = AP2MD_MSDC0_CODE 
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+    GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+
+#endif /* end of __INTRCTRL_MT6761_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6761_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6761_SW_Handle.h
new file mode 100644
index 0000000..b6b12ed
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6761_SW_Handle.h
@@ -0,0 +1,290 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6761_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   MT6761
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 10 2017 yen-chun.liu
+ * [MOLY00270029] [System Service][KAL] Gen93 dummy LISR APIs
+ * dummy LISR driver.
+ *
+ * 08 03 2017 yen-chun.liu
+ * [MOLY00267971] [SWLA] New Snapshot API for Robust Modem Feature
+ * 2 new SW interrupt for SWLA.
+ *
+ * 06 13 2017 yen-chun.liu
+ * [MOLY00244660] [MT6739][Gen93][System Service][MDCIRQ] Compile option for ZION(MT6739)
+ * .
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE1 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE2 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE3 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE4 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE5 = HC Yang
+      SW_TRIGGER_CODE6 = HC Yang
+      SW_TRIGGER_CODE7 = Max Weng
+      SW_TRIGGER_CODE8 = Max Weng
+      SW_TRIGGER_CODE9 = Max Weng
+      SW_TRIGGER_CODE10 = Max Weng
+      SW_TRIGGER_CODE11 = Max Weng
+      SW_TRIGGER_CODE12 = Max Weng
+      SW_TRIGGER_CODE13 = Zengling Jin
+      SW_TRIGGER_CODE14 = Zengling Jin
+      SW_TRIGGER_CODE15 = Zengling Jin
+      SW_TRIGGER_CODE16 = Chuansheng Zhang
+      SW_TRIGGER_CODE17 = Chuansheng Zhang
+      SW_TRIGGER_CODE18 = Chuansheng Zhang
+      SW_TRIGGER_CODE19 = Chuansheng Zhang
+      SW_TRIGGER_CODE20 = Huei-Ya Chang
+      SW_TRIGGER_CODE21 = Qmei Yang
+      SW_TRIGGER_CODE22 = Tee-Yuen Chun
+      SW_TRIGGER_CODE23 = Yuni Chang
+      SW_TRIGGER_CODE24 = SY Yeh
+      SW_TRIGGER_CODE25 = Owen Ho
+      SW_TRIGGER_CODE26 = Owen Ho
+      SW_TRIGGER_CODE27 = Owen Ho
+      SW_TRIGGER_CODE28 = Owen Ho
+      SW_TRIGGER_CODE29 = Carl Kao
+      SW_TRIGGER_CODE30 = Wade Huang
+      SW_TRIGGER_CODE31 = Woody kuo
+      SW_TRIGGER_CODE32 = Jun-Ying Huang
+      SW_TRIGGER_CODE33 = Jun-Ying Huang
+      SW_TRIGGER_CODE34 = Weimin Zeng
+      SW_TRIGGER_CODE35 = Weimin Zeng
+      SW_TRIGGER_CODE36 = HW Jheng
+      SW_TRIGGER_CODE37 = HW Jheng
+      SW_TRIGGER_CODE38 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE39 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE40 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE41 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE42 = 
+      SW_TRIGGER_CODE43 = 
+      SW_TRIGGER_CODE44 = 
+      SW_TRIGGER_CODE45 = 
+      SW_TRIGGER_CODE46 = 
+      SW_TRIGGER_CODE47 = 
+      SW_TRIGGER_CODE48 = 
+      SW_TRIGGER_CODE49 = 
+      SW_TRIGGER_CODE50 = 
+      SW_TRIGGER_CODE51 = 
+      SW_TRIGGER_CODE52 = 
+      SW_TRIGGER_CODE53 = 
+      SW_TRIGGER_CODE54 = 
+      SW_TRIGGER_CODE55 = 
+      SW_TRIGGER_CODE56 = 
+      SW_TRIGGER_CODE57 = 
+      SW_TRIGGER_CODE58 = 
+      SW_TRIGGER_CODE59 = 
+      SW_TRIGGER_CODE60 = 
+      SW_TRIGGER_CODE61 = 
+      SW_TRIGGER_CODE62 = 
+      SW_TRIGGER_CODE63 = 
+      SW_TRIGGER_CODE64 = 
+  */
+#if (defined(__MIPS_IA__))
+
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
+
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6761 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6763.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6763.h
new file mode 100644
index 0000000..4fbe1f6
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6763.h
@@ -0,0 +1,784 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6763.h
+ *
+ * Project:
+ * --------
+ *   TATAKA
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6763_H__
+#define __INTRCTRL_MT6763_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES          (256)
+
+#define 	IRQ_SHARE_D12MINT1_CODE	 MD_IRQID_SHARE_D12MINT1
+#define 	IRQ_IRDBG_MCU_INT_CODE	 MD_IRQID_IRDBG_MCU_INT
+#define 	IRQ_TDMA_CTIRQ1_CODE	 MD_IRQID_TDMA_CTIRQ1
+#define 	IRQ_TDMA_CTIRQ2_CODE	 MD_IRQID_TDMA_CTIRQ2
+#define 	IRQ_TDMA_CTIRQ3_CODE	 MD_IRQID_TDMA_CTIRQ3
+#define 	IRQ_CSSYS_FDD_CS_IRQ_CODE	 MD_IRQID_CSSYS_FDD_CS_IRQ
+#define 	IRQ_CSSYS_TDD_CS_IRQ_CODE	 MD_IRQID_CSSYS_TDD_CS_IRQ
+#define 	IRQ_CSSYS_LTE_CS_IRQ_CODE	 MD_IRQID_CSSYS_LTE_CS_IRQ
+#define 	IRQ_CSSYS_1X_CS_IRQ_CODE	 MD_IRQID_CSSYS_1X_CS_IRQ
+#define 	IRQ_CSSYS_DO_CS_IRQ_CODE	 MD_IRQID_CSSYS_DO_CS_IRQ
+#define 	IRQ_MDWDT_CODE	 MD_IRQID_MDWDT
+#define 	IRQ_UART_MD0_CODE	 MD_IRQID_UART_MD0
+#define 	IRQ_UART_MD1_CODE	 MD_IRQID_UART_MD1
+#define 	IRQ_OST_CODE	 MD_IRQID_OST
+#define 	IRQ_USIM0_CODE	 MD_IRQID_USIM0
+#define 	IRQ_USIM1_CODE	 MD_IRQID_USIM1
+#define 	IRQ_TOPSM_CODE	 MD_IRQID_TOPSM
+#define 	IRQ_MDGDMA0_CODE	 MD_IRQID_MDGDMA0
+#define 	IRQ_MDGDMA1_CODE	 MD_IRQID_MDGDMA1
+#define 	IRQ_MDGDMA2_CODE	 MD_IRQID_MDGDMA2
+#define 	IRQ_MDGDMA3_CODE	 MD_IRQID_MDGDMA3
+#define 	IRQ_EINT0_CODE	 MD_IRQID_EINT0
+#define 	IRQ_EINT1_CODE	 MD_IRQID_EINT1
+#define 	IRQ_EINT2_CODE	 MD_IRQID_EINT2
+#define 	IRQ_EINT_SHARE_CODE	 MD_IRQID_EINT_SHARE
+#define 	IRQ_BUS_ERR_CODE	 MD_IRQID_BUS_ERR
+#define 	IRQ_TXBRP0_CODE	 MD_IRQID_TXBRP0
+#define 	IRQ_TXBRP1_CODE	 MD_IRQID_TXBRP1
+#define 	IRQ_TXCRP_CODE	 MD_IRQID_TXCRP
+#define 	IRQ_MML2_HRT_CODE	 MD_IRQ_ID_MML2_HRT
+#define 	IRQ_MML2_NOTIF_CODE	 MD_IRQ_ID_MML2_NOTIF
+#define 	IRQ_MML2_EXCEP_CODE	 MD_IRQ_ID_MML2_EXCEP
+#define 	IRQ_DEM_TRIG_PS_INT_LE_CODE	 MD_IRQID_DEM_TRIG_PS_INT_LE
+#define 	IRQ_ECT_CODE	 MD_IRQID_ECT
+#define 	IRQ_PTP_THERM_INT_INT_CODE	 MD_IRQID_PTP_THERM_INT_INT
+#define 	IRQ_CLDMA_CODE	 MD_IRQID_CLDMA
+#define 	IRQ_MDINFRA_BUSMON_MATCH_STS_CODE	 MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define 	IRQ_ELM_DMA_IRQ_CODE	 MD_IRQID_ELM_DMA_IRQ
+#define 	IRQ_SOE_CODE	 MD_IRQID_SOE
+#define 	IRQ_ULSP_LOG_MD_INT_CODE	 MD_IRQID_ULSP_LOG_MD_INT
+#define 	IRQ_ULSP_LOG_DSP_INT_CODE	 MD_IRQID_ULSP_LOG_DSP_INT
+#define 	IRQ_USIP0_0_CODE	 MD_IRQID_USIP0_0
+#define 	IRQ_USIP1_0_CODE	 MD_IRQID_USIP1_0
+#define 	IRQ_USIP2_0_CODE	 MD_IRQID_USIP2_0
+#define 	IRQ_USIP3_0_CODE	 MD_IRQID_USIP3_0
+#define 	IRQ_USIP0_1_CODE	 MD_IRQID_USIP0_1
+#define 	IRQ_USIP1_1_CODE	 MD_IRQID_USIP1_1
+#define 	IRQ_USIP2_1_CODE	 MD_IRQID_USIP2_1
+#define 	IRQ_USIP3_1_CODE	 MD_IRQID_USIP3_1
+#define 	IRQ_SI_CM_ERR_CODE	 MD_IRQID_SI_CM_ERR
+#define 	IRQ_ABM_INT_CODE	 MD_IRQID_ABM_INT
+#define 	IRQ_ABM_ERROR_INT_CODE	 MD_IRQID_ABM_ERROR_INT
+#define 	IRQ_MDMCU_BUSMON_MATCH_STS_CODE	 MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define 	IRQ_ELMTOP_EMI_IRQ_CODE	 MD_IRQID_ELMTOP_EMI_IRQ
+#define 	IRQ_PPPHA_ENC0_INT_CODE	 MD_IRQID_PPPHA_ENC0_INT
+#define 	IRQ_PPPHA_ENC1_INT_CODE	 MD_IRQID_PPPHA_ENC1_INT
+#define 	IRQ_PPPHA_DEC0_INT_CODE	 MD_IRQID_PPPHA_DEC0_INT
+#define 	IRQ_PPPHA_DEC1_INT_CODE	 MD_IRQID_PPPHA_DEC1_INT
+#define 	IRQ_PTP_FSM_INT_CODE	 MD_IRQID_PTP_FSM_INT
+#define 	IRQ_PTP_SLPCTL_EVENT_CODE	 MD_IRQID_PTP_SLPCTL_EVENT
+#define 	IRQ_IEBIT_CHECK_IRQ0_CODE	 MD_IRQID_IEBIT_CHECK_IRQ0
+#define 	IRQ_IEBIT_CHECK_IRQ1_CODE	 MD_IRQID_IEBIT_CHECK_IRQ1
+#define 	IRQ_IEBIT_CHECK_IRQ2_CODE	 MD_IRQID_IEBIT_CHECK_IRQ2
+#define 	IRQ_IEBIT_CHECK_IRQ3_CODE	 MD_IRQID_IEBIT_CHECK_IRQ3
+#define 	IRQ_MDCIRQ_WDT0_CODE	 MD_IRQID_MDCIRQ_WDT0
+#define 	IRQ_MDCIRQ_WDT1_CODE	 MD_IRQID_MDCIRQ_WDT1
+#define 	IRQ_TRACE_INT_CODE	 MD_IRQID_TRACE_INT
+#define 	IRQ_SI_CM_PCINT_CODE	 MD_IRQID_SI_CM_PCINT
+#define 	IRQ_PLL_GEARHP_RDY_CODE	 MD_IRQID_PLL_GEARHP_RDY
+#define 	IRQ_DCXO_RDY_WO_ACK_IRQ_CODE	 MD_IRQID_DCXO_RDY_WO_ACK_IRQ
+#define 	IRQ_REQ_ABNORM_IRQ_CODE	 MD_IRQID_REQ_ABNORM_IRQ
+#define 	IRQ_TOP_PLL_DSNS_IRQ_CODE	 MD_IRQID_TOP_PLL_DSNS_IRQ
+#define 	IRQ_BT_CVSD_CODE	 MD_IRQID_BT_CVSD
+#define 	IRQ_SSUSB_USB_MCU_CODE	 MD_IRQID_SSUSB_USB_MCU
+#define 	IRQ_SSUSB_DEV_CODE	 MD_IRQID_SSUSB_DEV
+#define 	IRQ_AP2MD_DVFS_BLOCK_ELM_CODE	 MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define 	IRQ_AP2MD_CCIF0_0_CODE	 MD_IRQID_AP2MD_CCIF0_0
+#define 	IRQ_AP2MD_CCIF0_1_CODE	 MD_IRQID_AP2MD_CCIF0_1
+#define 	IRQ_AP2MD_CCIF1_0_CODE	 MD_IRQID_AP2MD_CCIF1_0
+#define 	IRQ_AP2MD_CCIF1_1_CODE	 MD_IRQID_AP2MD_CCIF1_1
+#define 	IRQ_RXDFE_RXK_READBACK_CODE	 MD_IRQID_RXDFE_RXK_READBACK
+#define 	IRQ_BR_DMA_IRQ_CODE	 MD_IRQID_BR_DMA_IRQ
+#define 	IRQ_IDC_PM_INT_CODE	 MD_IRQID_IDC_PM_INT
+#define 	IRQ_IDC_UART_IRQ_CODE	 MD_IRQID_IDC_UART_IRQ
+#define 	IRQ_MDRTT_CODE	 MD_IRQID_MDRTT
+#define 	IRQ_MDEVDO_CODE	 MD_IRQID_MDEVDO
+#define 	IRQ_MDM2C_U3G_CODE	 MD_IRQID_MDM2C_U3G
+#define 	IRQ_MDDFE_DUMP_CODE	 MD_IRQID_MDDFE_DUMP
+#define 	IRQ_RAKE_CMIF_M2C_IRQ_0_CODE	 MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define 	IRQ_RAKE_CMIF_M2C_IRQ_1_CODE	 MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define 	IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE	 MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define 	IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE	 MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define 	IRQ_RAKE_CMIF_PD_DO_IRQ_CODE	 MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define 	IRQ_BIGRAM_IRQ_CODE	 MD_IRQID_BIGRAM_IRQ
+#define 	IRQ_BR_BDGE_IRQ_CODE	 MD_IRQID_BR_BDGE_IRQ
+#define 	IRQ_L1_LTE_SLEEP_IRQ_CODE	 MD_IRQID_L1_LTE_SLEEP_IRQ
+#define 	IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE	 MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define 	IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE	 MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define 	IRQ_L1M_PHY_LTMR_IRQ_0_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define 	IRQ_L1M_PHY_LTMR_IRQ_1_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define 	IRQ_L1M_PHY_LTMR_IRQ_2_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define 	IRQ_L1M_PHY_LTMR_IRQ_3_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define 	IRQ_L1M_PHY_LTMR_IRQ_4_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define 	IRQ_L1M_PHY_LTMR_IRQ_5_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define 	IRQ_L1M_PHY_LTMR_IRQ_6_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define 	IRQ_L1M_PHY_LTMR_IRQ_7_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define 	IRQ_L1_LTE_WAKEUP_IRQ_CODE	 MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define 	IRQ_MDL1_TOPSM_IRQ_CODE	 MD_IRQID_MDL1_TOPSM_IRQ
+#define 	IRQ_TDD_WAKEUP_IRQ_CODE	 MD_IRQID_TDD_WAKEUP_IRQ
+#define 	IRQ_TDD_TIMER_L1D_1_IRQ_CODE	 MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define 	IRQ_TDD_TIMER_L1D_2_IRQ_CODE	 MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define 	IRQ_RTR_FRAME_IRQ_CODE	 MD_IRQID_RTR_FRAME_IRQ
+#define 	IRQ_RTR_SLT_0_IRQ_CODE	 MD_IRQID_RTR_SLT_0_IRQ
+#define 	IRQ_RTR_SLT_1_IRQ_CODE	 MD_IRQID_RTR_SLT_1_IRQ
+#define 	IRQ_FDD_SLP_IRQ_CODE	 MD_IRQID_FDD_SLP_IRQ
+#define 	IRQ_TDMA_WAKEUP_IRQ_CODE	 MD_IRQID_TDMA_WAKEUP_IRQ
+#define 	IRQ_MD_DVFS_CTRL_IRQ_CODE	 MD_IRQID_MD_DVFS_CTRL_IRQ
+#define 	IRQ_BSI_MM_I_IRQ_RFIC_CODE	 MD_IRQID_BSI_MM_I_IRQ_RFIC
+#define 	IRQ_BSI_MM_I_IRQ_MIPI_CODE	 MD_IRQID_BSI_MM_I_IRQ_MIPI
+#define 	IRQ_ST1X_CPINT_CODE	 MD_IRQID_ST1X_CPINT
+#define 	IRQ_ST1x_HALF_CPINT_CODE	 MD_IRQID_ST1x_HALF_CPINT
+#define 	IRQ_ST1x_CFG_CPINT_CODE	 MD_IRQID_ST1x_CFG_CPINT
+#define 	IRQ_ST1x_WAKEUP_IRQ_CODE	 MD_IRQID_ST1x_WAKEUP_IRQ
+#define 	IRQ_STDO_CPINT_CODE	 MD_IRQID_STDO_CPINT
+#define 	IRQ_STDO_HALF_CPINT_CODE	 MD_IRQID_STDO_HALF_CPINT
+#define 	IRQ_STDO_CFG_CPINT_CODE	 MD_IRQID_STDO_CFG_CPINT
+#define 	IRQ_STDO_WAKEUP_IRQ_CODE	 MD_IRQID_STDO_WAKEUP_IRQ
+#define 	IRQ_FREQM_IRQ_CODE	 MD_IRQID_FREQM_IRQ
+#define 	IRQ_SPM2MD_DVFS_MDPERISYS_CODE	 MD_IRQID_SPM2MD_DVFS_MDPERISYS
+#define 	IRQ_TXDFE_BB_IRQ_CODE	 MD_IRQID_TXDFE_BB_IRQ
+#define 	IRQ_PCC_TOP_FULL_IRQ_CODE	 MD_IRQID_PCC_TOP_FULL_IRQ
+#define 	IRQ_GPTM1_CODE	 MD_IRQID_GPTM1
+#define 	IRQ_GPTM2_CODE	 MD_IRQID_GPTM2
+#define 	IRQ_GPTM3_CODE	 MD_IRQID_GPTM3
+#define 	IRQ_GPTM4_CODE	 MD_IRQID_GPTM4
+#define 	IRQ_GPTM5_CODE	 MD_IRQID_GPTM5
+#define 	IRQ_GPTM6_CODE	 MD_IRQID_GPTM6
+#define 	IRQ_GPTM7_CODE	 MD_IRQID_GPTM7
+#define 	IRQ_GPTM8_CODE	 MD_IRQID_GPTM8
+#define 	IRQ_GPTM9_CODE	 MD_IRQID_GPTM9
+#define 	IRQ_GPTM10_CODE	 MD_IRQID_GPTM10
+#define 	IRQ_GPTM11_CODE	 MD_IRQID_GPTM11
+#define 	IRQ_BUSMPU_IRQ_CODE	 MD_IRQID_BUSMPU_IRQ
+#define 	IRQ_SW_LISR1_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_0
+#define 	IRQ_SW_LISR2_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_1
+#define 	IRQ_SW_LISR3_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_2
+#define 	IRQ_SW_LISR4_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_3
+#define 	IRQ_SW_LISR5_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_4
+#define 	IRQ_SW_LISR6_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_5
+#define 	IRQ_SW_LISR7_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_6
+#define 	IRQ_SW_LISR8_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_7
+#define 	IRQ_SW_LISR9_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_8
+#define 	IRQ_SW_LISR10_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_9
+#define 	IRQ_SW_LISR11_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_10
+#define 	IRQ_SW_LISR12_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_11
+#define 	IRQ_SW_LISR13_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_12
+#define 	IRQ_SW_LISR14_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_13
+#define 	IRQ_SW_LISR15_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_14
+#define 	IRQ_SW_LISR16_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_15
+#define 	IRQ_SW_LISR17_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_16
+#define 	IRQ_SW_LISR18_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_17
+#define 	IRQ_SW_LISR19_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_18
+#define 	IRQ_SW_LISR20_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_19
+#define 	IRQ_SW_LISR21_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_20
+#define 	IRQ_SW_LISR22_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_21
+#define 	IRQ_SW_LISR23_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_22
+#define 	IRQ_SW_LISR24_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_23
+#define 	IRQ_SW_LISR25_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_24
+#define 	IRQ_SW_LISR26_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_25
+#define 	IRQ_SW_LISR27_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_26
+#define 	IRQ_SW_LISR28_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_27
+#define 	IRQ_SW_LISR29_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_28
+#define 	IRQ_SW_LISR30_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_29
+#define 	IRQ_SW_LISR31_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_30
+#define 	IRQ_SW_LISR32_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_31
+#define 	IRQ_SW_LISR33_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_32
+#define 	IRQ_SW_LISR34_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_33
+#define 	IRQ_SW_LISR35_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_34
+#define 	IRQ_SW_LISR36_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_35
+#define 	IRQ_SW_LISR37_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_36
+#define 	IRQ_SW_LISR38_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_37
+#define 	IRQ_SW_LISR39_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_38
+#define 	IRQ_SW_LISR40_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_39
+#define 	IRQ_SW_LISR41_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_40
+#define 	IRQ_SW_LISR42_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_41
+#define 	IRQ_SW_LISR43_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_42
+#define 	IRQ_SW_LISR44_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_43
+#define 	IRQ_SW_LISR45_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_44
+#define 	IRQ_SW_LISR46_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_45
+#define 	IRQ_SW_LISR47_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_46
+#define 	IRQ_SW_LISR48_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_47
+#define 	IRQ_SW_LISR49_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_48
+#define 	IRQ_SW_LISR50_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_49
+#define 	IRQ_SW_LISR51_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_50
+#define 	IRQ_SW_LISR52_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_51
+#define 	IRQ_SW_LISR53_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_52
+#define 	IRQ_SW_LISR54_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_53
+#define 	IRQ_SW_LISR55_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_54
+#define 	IRQ_SW_LISR56_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_55
+#define 	IRQ_SW_LISR57_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_56
+#define 	IRQ_SW_LISR58_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_57
+#define 	IRQ_SW_LISR59_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_58
+#define 	IRQ_SW_LISR60_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_59
+#define 	IRQ_SW_LISR61_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_60
+#define 	IRQ_SW_LISR62_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_61
+#define 	IRQ_SW_LISR63_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_62
+#define 	IRQ_SW_LISR64_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_63
+#define     MCU_BUS_DECERR_CODE  MD_IRQID_MCU_BUS_DECERR
+#define     GIC0_FDCInt_CODE  MD_IRQID_GIC0_FDCInt
+#define     GIC0_FDCInt_1_CODE  MD_IRQID_GIC0_FDCInt_1
+#define     GIC0_PCInt_CODE  MD_IRQID_GIC0_PCInt
+#define     GIC0_PCInt_1_CODE  MD_IRQID_GIC0_PCInt_1
+#define     GIC0_TimerInt_CODE  MD_IRQID_GIC0_TimerInt
+#define     GIC0_TimerInt_1_CODE  MD_IRQID_GIC0_TimerInt_1
+#define     GIC1_FDCInt_CODE  MD_IRQID_GIC1_FDCInt
+#define     GIC1_FDCInt_1_CODE  MD_IRQID_GIC1_FDCInt_1
+#define     GIC1_PCInt_CODE  MD_IRQID_GIC1_PCInt
+#define     GIC1_PCInt_1_CODE  MD_IRQID_GIC1_PCInt_1
+#define     GIC1_TimerInt_CODE  MD_IRQID_GIC1_TimerInt
+#define     GIC1_TimerInt_1_CODE  MD_IRQID_GIC1_TimerInt_1
+#define     IRQ_EINT3_CODE  MD_IRQID_EINT3
+#define     MCUMMU_INT_CODE  MD_IRQID_MCUMMU_INT
+#define     SPRAM_DECERR_CODE  MD_IRQID_IA_DECERR
+#define     RMPU_CTIREIGIN_CODE  MD_IRQID_RMPU_CTIREIGIN
+#define     MDSM_CORE_PWR_CTRL_CODE  MD_IRQID_MDSM_CORE_PWR_CTRL
+#define     AP2MD_MSDC0_CODE  MD_IRQID_AP2MD_MSDC0
+
+
+
+/*
+ * Define IRQ selection register assignment
+ */
+#define IRQSel()
+//#define INVALID_ISR_ID           (0xFF)
+
+#define INTERRUPT_PRIORITY_LIST \
+/*  0 ~  7 */  69, 127,  67,  68,  66,  38,  32,  61, \
+/*  8 ~ 15 */  88,  78, 127, 127, 127, 127, 127, 127, \
+/* 16 ~ 23 */ 127, 110,  42, 127, 127, 127, 127, 127, \
+/* 24 ~ 31 */ 127, 127,  64, 127, 127, 123, 124, 122, \
+/* 32 ~ 39 */ 127,   6,   7, 127,   6, 127, 127, 127, \
+/* 40 ~ 47 */ 127,  71,  41,  39,  62,  45, 127, 127, \
+/* 48 ~ 55 */ 127, 127, 127, 127, 127, 127, 117, 118, \
+/* 56 ~ 63 */ 119, 120, 126, 127,   6,   6,   6,   6, \
+/* 64 ~ 71 */ 110, 110, 127, 127, 127, 127, 127, 127, \
+/* 72 ~ 79 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 80 ~ 87 */  45, 127, 127, 127,  56,  54, 127, 115, \
+/* 88 ~ 95 */  58,  36,  55,  33,  86,   6,   6,  51, \
+/* 96 ~103 */  40,  47,  30, 127,  46,  43,  43,  43, \
+/*104 ~111 */  46,  44,  28,  86,  27,  34,  35, 110, \
+/*112 ~119 */  31,  49,  26,  64,  25, 127, 127,  59, \
+/*120 ~127 */ 110,  58,  29,  59,  59,  58,  29,  90, \
+/*128 ~135 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*136 ~143 */  70,  77,  44, 127, 127, 127, 127, 127, \
+/*144 ~151 */ 110, 127, 110,   7,   7,  76,  71,  77, \
+/*152 ~159 */  50,  51,  52,  79,  76,  77,  39,  72, \
+/*160 ~167 */  74,  75,  48, 127, 127,  63,   8, 127, \
+/*168 ~175 */ 110, 127, 110, 110,   6, 127, 127, 127, \
+/*176 ~183 */  75,  75, 127, 127,   7, 111,   7, 111, \
+/*184 ~191 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*192 ~199 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*200 ~207 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*208 ~215 */ 127, 110, 127, 110, 127, 110, 127, 110, \
+/*216 ~223 */ 127, 110, 127, 110, 127, 127, 127,   6, \
+/*224 ~231 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*232 ~239 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*240 ~247 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*248 ~255 */ 127, 127, 127, 127, 127, 127, 127, 127,
+
+#if defined(__ESL_MASE__)
+
+/* for OS ICC
+   IRQ_SW_LISR1_CODE
+   IRQ_SW_LISR2_CODE
+   IRQ_SW_LISR3_CODE
+   IRQ_SW_LISR4_CODE
+*/
+#define INTERRUPT_GROUP_LIST \
+	/*	0 ~  7 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*	8 ~ 15 */  0,  0,  0,  1,  0,  0,  0,  0, \
+	/* 16 ~ 23 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 24 ~ 31 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 32 ~ 39 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 40 ~ 47 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 48 ~ 55 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 56 ~ 63 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 64 ~ 71 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 72 ~ 79 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 80 ~ 87 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 88 ~ 95 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 96 ~103 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*104 ~111 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*112 ~119 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*120 ~127 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*128 ~135 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*136 ~143 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*144 ~151 */  1,  2,  3,  0,  0,  0,  0,  0, \
+	/*152 ~159 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*160 ~167 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*168 ~175 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*176 ~183 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*184 ~191 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*192 ~199 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*200 ~207 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*208 ~215 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*216 ~223 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*224 ~231 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*232 ~239 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*240 ~247 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*248 ~255 */  0,  0,  0,  0,  0,  0,  0,  0
+#else  /* __ESL_MASE__*/ 
+#define INTERRUPT_GROUP_LIST \
+	/*  0 ~  7 */  1,  4,  1,  1,  1,  1,  1,  0, \
+	/*  8 ~ 15 */  1,  1, 17,  4,  4,  0,  4,  4, \
+	/* 16 ~ 23 */  4,  1,  1,  4,  4,  4,  4,  4, \
+	/* 24 ~ 31 */  4,  4,  1,  4,  4,  4,  4,  4, \
+	/* 32 ~ 39 */  0,  5,  0,  4,  5,  4,  4,  4, \
+	/* 40 ~ 47 */  4,  0,  1,  1,  1,  3,  4,  4, \
+	/* 48 ~ 55 */  4,  4,  0,  0,  4,  4,  4,  4, \
+	/* 56 ~ 63 */  4,  4,  4,  4,  5,  5,  5,  5, \
+	/* 64 ~ 71 */  1,  3,  0,  4,  4,  4,  4,  4, \
+	/* 72 ~ 79 */  4,  4,  4,  4,  4,  5,  4,  4, \
+	/* 80 ~ 87 */  3,  4,  4,  0,  1,  1,  4,  4, \
+	/* 88 ~ 95 */  1,  1,  1,  1,  1,  5,  5,  3, \
+	/* 96 ~103 */  1,  3,  1,  4,  3,  1,  1,  1, \
+	/*104 ~111 */  3,  3,  3,  0,  1,  1,  1,  1, \
+	/*112 ~119 */  1,  3,  1,  1,  0,  4,  4,  1, \
+	/*120 ~127 */  1,  1,  1,  1,  1,  1,  1,  0, \
+	/*128 ~135 */  4,  4,  0,  4,  4,  4,  4,  4, \
+	/*136 ~143 */  1,  1,  3,  4,  4,  4,  4,  0, \
+	/*144 ~151 */  1,  2,  3,  0,  2,  1,  1,  1, \
+	/*152 ~159 */  3,  1,  3,  1,  1,  1,  1,  1, \
+	/*160 ~167 */  1,  1,  6,  5,  4,  1,  0,  0, \
+	/*168 ~175 */  1,  2,  3,  1,  5, 16,  0,  2, \
+	/*176 ~183 */  1,  1,  0,  2,  0,  1,  2,  3, \
+	/*184 ~191 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*192 ~199 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*200 ~207 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*208 ~215 */  0,  1,  0,  1,  0,  1,  2,  3, \
+	/*216 ~223 */  2,  3,  2,  3,  4,  4,  4,  4, \
+	/*224 ~231 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*232 ~239 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*240 ~247 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*248 ~255 */  4,  4,  4,  4,  4,  4,  4,  4
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+	/* Group0(0) */                0xE, \
+	/* Group1(1) */                0xD, \
+	/* Group2(2) */                0xB, \
+	/* Group3(3) */                0x7, \
+	/* Group4(0,2) */              0xA, \
+	/* Group5(0,1,2,3) */          0x0, \
+	/* Group6(1,3) */              0x5, \
+	/* Group7 */                   0xF, \
+	/* Group8 */                   0xF, \
+	/* Group9 */                   0xF, \
+	/* Group10 */                  0xF, \
+	/* Group11 */                  0xF, \
+	/* Group12 */                  0xF, \
+	/* Group13 */                  0xF, \
+	/* Group14*/                   0xF, \
+	/* Group15 */                  0xF,
+#endif
+
+#define NMI_GROUP_M2V_LIST \
+	/* Group0(exception usage) */  0xF, \
+	/* Group1 */                   0x0,
+
+#if defined(__MDCIRQ_WAIT_MODE_ENABLE__)
+#define INTERRUPT_BROADCAST_TYPE \
+	/*  0-31 */                0x040627FD, \
+	/* 32-63 */                0xF00C3E17, \
+	/* 64-95 */                0xFF392007, \
+	/* 96-127 */               0xFF9FFFF7, \
+	/* 128-159 */              0xFFFF8704, \
+	/* 160-191 */              0x00FFDFFF, \
+	/* 192-223 */              0x0FFF0000, \
+	/* 224-255 */              0x00000000,
+#else
+#define INTERRUPT_BROADCAST_TYPE \
+	/*  0-31 */                0x00000400, \
+	/* 32-63 */                0xF0000012, \
+	/* 64-95 */                0x60002000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x0000101C, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000,
+#endif
+
+#define INTERRUPT_TYPE \
+	/*  0-31 */                0x00000400, \
+	/* 32-63 */                0x00000000, \
+	/* 64-95 */                0x00000000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x00002000, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000,
+
+#define INTERRUPT_HRT_MT \
+	/*  0-31 */                0x00000000, \
+	/* 32-63 */                0x00000000, \
+	/* 64-95 */                0x00000000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x00000000, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000,
+
+
+#define INTERRUPT_TIMING_THRESHOLD \
+	/*	VPE0 */  0xFFFFFFFF,\
+	/*	VPE1 */  0xFFFFFFFF,\
+	/*	VPE2 */  0xFFFFFFFF,\
+	/*	VPE3 */  0xFFFFFFFF,
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+//#define EINT_TOTAL_CHANNEL 16
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+    VPE_STATUS_DORMANT           = 0,
+    VPE_STATUS_LISR_HIGHEST      = 1,
+    VPE_STATUS_LISR_LOWEST       = 127,
+    VPE_STATUS_HISR_TASK_HIGHEST = 128,
+    VPE_STATUS_HISR_TASK_LOWEST  = 386, 
+    VPE_STATUS_END               = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+    IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+    IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+    IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+    IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+    IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+    IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+    IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+    IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+    IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+    IRQ_MDWDT = IRQ_MDWDT_CODE,
+    IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+    IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+    IRQ_OST = IRQ_OST_CODE,
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+    IRQ_USIM1 = IRQ_USIM1_CODE,
+    IRQ_TOPSM = IRQ_TOPSM_CODE,
+    IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+    IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+    IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+    IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+    IRQ_EINT0 = IRQ_EINT0_CODE,
+    IRQ_EINT1 = IRQ_EINT1_CODE,
+    IRQ_EINT2 = IRQ_EINT2_CODE,
+    IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+    IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+    IRQ_TXBRP0 = IRQ_TXBRP0_CODE,
+    IRQ_TXBRP1 = IRQ_TXBRP1_CODE,
+    IRQ_TXCRP = IRQ_TXCRP_CODE,
+    IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+    IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+    IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+    IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+    IRQ_ECT = IRQ_ECT_CODE,
+    IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+    IRQ_CLDMA = IRQ_CLDMA_CODE,
+    IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+    IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+    IRQ_SOE = IRQ_SOE_CODE,
+    IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+    IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+    IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+    IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+    IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+    IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+    IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+    IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+    IRQ_USIP2_1 = IRQ_USIP2_1_CODE,
+    IRQ_USIP3_1 = IRQ_USIP3_1_CODE,
+    IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+    IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+    IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+    IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+    IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+    IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+    IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+    IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+    IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+    IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+    IRQ_PTP_SLPCTL_EVENT = IRQ_PTP_SLPCTL_EVENT_CODE,
+    IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+    IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+    IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+    IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+    IRQ_MDCIRQ_WDT0 = IRQ_MDCIRQ_WDT0_CODE,
+    IRQ_MDCIRQ_WDT1 = IRQ_MDCIRQ_WDT1_CODE,
+    IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+    IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+    IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+    IRQ_DCXO_RDY_WO_ACK_IRQ = IRQ_DCXO_RDY_WO_ACK_IRQ_CODE,
+    IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+    IRQ_TOP_PLL_DSNS_IRQ = IRQ_TOP_PLL_DSNS_IRQ_CODE,
+    IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+    IRQ_SSUSB_USB_MCU = IRQ_SSUSB_USB_MCU_CODE,
+    IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+    IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+    IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+    IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+    IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+    IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+    IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+    IRQ_BR_DMA_IRQ = IRQ_BR_DMA_IRQ_CODE,
+    IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+    IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+    IRQ_MDRTT = IRQ_MDRTT_CODE,
+    IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+    IRQ_MDM2C_U3G = IRQ_MDM2C_U3G_CODE,
+    IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+    IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+    IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+    IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+    IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+    IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+    IRQ_MDL1_TOPSM_IRQ = IRQ_MDL1_TOPSM_IRQ_CODE,
+    IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+    IRQ_RTR_FRAME_IRQ = IRQ_RTR_FRAME_IRQ_CODE,
+    IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+    IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+    IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+    IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+    IRQ_MD_DVFS_CTRL_IRQ = IRQ_MD_DVFS_CTRL_IRQ_CODE,
+    IRQ_BSI_MM_I_IRQ_RFIC = IRQ_BSI_MM_I_IRQ_RFIC_CODE,
+    IRQ_BSI_MM_I_IRQ_MIPI = IRQ_BSI_MM_I_IRQ_MIPI_CODE,
+    IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+    IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+    IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+    IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+    IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+    IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+    IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+    IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+    IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+    IRQ_SPM2MD_DVFS_MDPERISYS = IRQ_SPM2MD_DVFS_MDPERISYS_CODE,
+    IRQ_TXDFE_BB_IRQ = IRQ_TXDFE_BB_IRQ_CODE,
+    IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+    IRQ_GPTM1 = IRQ_GPTM1_CODE,
+    IRQ_GPTM2 = IRQ_GPTM2_CODE,
+    IRQ_GPTM3 = IRQ_GPTM3_CODE,
+    IRQ_GPTM4 = IRQ_GPTM4_CODE,
+    IRQ_GPTM5 = IRQ_GPTM5_CODE,
+    IRQ_GPTM6 = IRQ_GPTM6_CODE,
+    IRQ_GPTM7 = IRQ_GPTM7_CODE,
+    IRQ_GPTM8 = IRQ_GPTM8_CODE,
+    IRQ_GPTM9 = IRQ_GPTM9_CODE,
+    IRQ_GPTM10 = IRQ_GPTM10_CODE,
+    IRQ_GPTM11 = IRQ_GPTM11_CODE,
+    IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+    IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+    IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+    IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+    IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+    IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+    IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+    IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+    IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+    IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+    IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+    IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+    IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+    IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+    IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+    IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+    IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+    IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+    IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+    IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+    IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+    IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+    IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+    IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+    IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+    IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+    IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+    IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+    IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+    IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+    IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+    IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+    IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+    IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+    IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+    IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+    IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+    IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+    IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+    IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+    IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+    IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+    IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+    IRQ_SW_LISR43 = IRQ_SW_LISR43_CODE,
+    IRQ_SW_LISR44 = IRQ_SW_LISR44_CODE,
+    IRQ_SW_LISR45 = IRQ_SW_LISR45_CODE,
+    IRQ_SW_LISR46 = IRQ_SW_LISR46_CODE,
+    IRQ_SW_LISR47 = IRQ_SW_LISR47_CODE,
+    IRQ_SW_LISR48 = IRQ_SW_LISR48_CODE,
+    IRQ_SW_LISR49 = IRQ_SW_LISR49_CODE,
+    IRQ_SW_LISR50 = IRQ_SW_LISR50_CODE,
+    IRQ_SW_LISR51 = IRQ_SW_LISR51_CODE,
+    IRQ_SW_LISR52 = IRQ_SW_LISR52_CODE,
+    IRQ_SW_LISR53 = IRQ_SW_LISR53_CODE,
+    IRQ_SW_LISR54 = IRQ_SW_LISR54_CODE,
+    IRQ_SW_LISR55 = IRQ_SW_LISR55_CODE,
+    IRQ_SW_LISR56 = IRQ_SW_LISR56_CODE,
+    IRQ_SW_LISR57 = IRQ_SW_LISR57_CODE,
+    IRQ_SW_LISR58 = IRQ_SW_LISR58_CODE,
+    IRQ_SW_LISR59 = IRQ_SW_LISR59_CODE,
+    IRQ_SW_LISR60 = IRQ_SW_LISR60_CODE,
+    IRQ_SW_LISR61 = IRQ_SW_LISR61_CODE,
+    IRQ_SW_LISR62 = IRQ_SW_LISR62_CODE,
+    IRQ_SW_LISR63 = IRQ_SW_LISR63_CODE,
+    IRQ_SW_LISR64 = IRQ_SW_LISR64_CODE,
+    MCU_BUS_DECERR = MCU_BUS_DECERR_CODE,
+    GIC0_FDCInt = GIC0_FDCInt_CODE,
+    GIC0_FDCInt_1 = GIC0_FDCInt_1_CODE,
+    GIC0_PCInt = GIC0_PCInt_CODE,
+    GIC0_PCInt_1 = GIC0_PCInt_1_CODE,
+    GIC0_TimerInt = GIC0_TimerInt_CODE,
+    GIC0_TimerInt_1 = GIC0_TimerInt_1_CODE,
+    GIC1_FDCInt = GIC1_FDCInt_CODE,
+    GIC1_FDCInt_1 = GIC1_FDCInt_1_CODE,
+    GIC1_PCInt = GIC1_PCInt_CODE,
+    GIC1_PCInt_1 = GIC1_PCInt_1_CODE,
+    GIC1_TimerInt = GIC1_TimerInt_CODE,
+    GIC1_TimerInt_1 = GIC1_TimerInt_1_CODE,
+    IRQ_EINT3 = IRQ_EINT3_CODE,
+    MCUMMU_INT = MCUMMU_INT_CODE,
+    SPRAM_DECERR = SPRAM_DECERR_CODE,
+    RMPU_CTIREIGIN = RMPU_CTIREIGIN_CODE,
+    MDSM_CORE_PWR_CTRL = MDSM_CORE_PWR_CTRL_CODE,
+    AP2MD_MSDC0 = AP2MD_MSDC0_CODE 
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+    GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+
+#endif /* end of __INTRCTRL_MT6763_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6763_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6763_SW_Handle.h
new file mode 100644
index 0000000..b080c51
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6763_SW_Handle.h
@@ -0,0 +1,290 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6763_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   MT6763
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 10 2017 yen-chun.liu
+ * [MOLY00270029] [System Service][KAL] Gen93 dummy LISR APIs
+ * dummy LISR driver code.
+ *
+ * 08 03 2017 yen-chun.liu
+ * [MOLY00267971] [SWLA] New Snapshot API for Robust Modem Feature
+ * 2 new SW IRQ for SWLA.
+ *
+ * 05 05 2017 yen-chun.liu
+ * [MOLY00246656] [BIANCO][MT6763][RDIT][C2K][SRLTE][Try run][SIM1: CTC][4]MOD_NIL, , TRACE_ERROR, [DSP-inner] Assert fail: Line 1417 Code 0x13 0xb000000 0x12 Filename: md32/usip/inner/modem/lte/lte_scheduler/src/lte_scheduler.c
+ * change IRQ priority of GDMA and one more SW trigger IRQ request.
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE1 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE2 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE3 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE4 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE5 = HC Yang
+      SW_TRIGGER_CODE6 = HC Yang
+      SW_TRIGGER_CODE7 = Max Weng
+      SW_TRIGGER_CODE8 = Max Weng
+      SW_TRIGGER_CODE9 = Max Weng
+      SW_TRIGGER_CODE10 = Max Weng
+      SW_TRIGGER_CODE11 = Max Weng
+      SW_TRIGGER_CODE12 = Max Weng
+      SW_TRIGGER_CODE13 = Zengling Jin
+      SW_TRIGGER_CODE14 = Zengling Jin
+      SW_TRIGGER_CODE15 = Zengling Jin
+      SW_TRIGGER_CODE16 = Chuansheng Zhang
+      SW_TRIGGER_CODE17 = Chuansheng Zhang
+      SW_TRIGGER_CODE18 = Chuansheng Zhang
+      SW_TRIGGER_CODE19 = Chuansheng Zhang
+      SW_TRIGGER_CODE20 = Huei-Ya Chang
+      SW_TRIGGER_CODE21 = Qmei Yang
+      SW_TRIGGER_CODE22 = Tee-Yuen Chun
+      SW_TRIGGER_CODE23 = Yuni Chang
+      SW_TRIGGER_CODE24 = SY Yeh
+      SW_TRIGGER_CODE25 = Owen Ho
+      SW_TRIGGER_CODE26 = Owen Ho
+      SW_TRIGGER_CODE27 = Owen Ho
+      SW_TRIGGER_CODE28 = Owen Ho
+      SW_TRIGGER_CODE29 = Carl Kao
+      SW_TRIGGER_CODE30 = Wade Huang
+      SW_TRIGGER_CODE31 = Woody kuo
+      SW_TRIGGER_CODE32 = Jun-Ying Huang
+      SW_TRIGGER_CODE33 = Jun-Ying Huang
+      SW_TRIGGER_CODE34 = Weimin Zeng
+      SW_TRIGGER_CODE35 = Weimin Zeng
+      SW_TRIGGER_CODE36 = HW Jheng
+      SW_TRIGGER_CODE37 = HW Jheng
+      SW_TRIGGER_CODE38 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE39 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE40 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE41 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE42 = 
+      SW_TRIGGER_CODE43 = 
+      SW_TRIGGER_CODE44 = 
+      SW_TRIGGER_CODE45 = 
+      SW_TRIGGER_CODE46 = 
+      SW_TRIGGER_CODE47 = 
+      SW_TRIGGER_CODE48 = 
+      SW_TRIGGER_CODE49 = 
+      SW_TRIGGER_CODE50 = 
+      SW_TRIGGER_CODE51 = 
+      SW_TRIGGER_CODE52 = 
+      SW_TRIGGER_CODE53 = 
+      SW_TRIGGER_CODE54 = 
+      SW_TRIGGER_CODE55 = 
+      SW_TRIGGER_CODE56 = 
+      SW_TRIGGER_CODE57 = 
+      SW_TRIGGER_CODE58 = 
+      SW_TRIGGER_CODE59 = 
+      SW_TRIGGER_CODE60 = 
+      SW_TRIGGER_CODE61 = 
+      SW_TRIGGER_CODE62 = 
+      SW_TRIGGER_CODE63 = 
+      SW_TRIGGER_CODE64 = 
+  */
+#if (defined(__MIPS_IA__))
+
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
+
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6763 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6765.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6765.h
new file mode 100644
index 0000000..274d812
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6765.h
@@ -0,0 +1,784 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6765.h
+ *
+ * Project:
+ * --------
+ *   TATAKA
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6765_H__
+#define __INTRCTRL_MT6765_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES          (256)
+
+#define 	IRQ_SHARE_D12MINT1_CODE	 MD_IRQID_SHARE_D12MINT1
+#define 	IRQ_IRDBG_MCU_INT_CODE	 MD_IRQID_IRDBG_MCU_INT
+#define 	IRQ_TDMA_CTIRQ1_CODE	 MD_IRQID_TDMA_CTIRQ1
+#define 	IRQ_TDMA_CTIRQ2_CODE	 MD_IRQID_TDMA_CTIRQ2
+#define 	IRQ_TDMA_CTIRQ3_CODE	 MD_IRQID_TDMA_CTIRQ3
+#define 	IRQ_CSSYS_FDD_CS_IRQ_CODE	 MD_IRQID_CSSYS_FDD_CS_IRQ
+#define 	IRQ_CSSYS_TDD_CS_IRQ_CODE	 MD_IRQID_CSSYS_TDD_CS_IRQ
+#define 	IRQ_CSSYS_LTE_CS_IRQ_CODE	 MD_IRQID_CSSYS_LTE_CS_IRQ
+#define 	IRQ_CSSYS_1X_CS_IRQ_CODE	 MD_IRQID_CSSYS_1X_CS_IRQ
+#define 	IRQ_CSSYS_DO_CS_IRQ_CODE	 MD_IRQID_CSSYS_DO_CS_IRQ
+#define 	IRQ_MDWDT_CODE	 MD_IRQID_MDWDT
+#define 	IRQ_UART_MD0_CODE	 MD_IRQID_UART_MD0
+#define 	IRQ_UART_MD1_CODE	 MD_IRQID_UART_MD1
+#define 	IRQ_OST_CODE	 MD_IRQID_OST
+#define 	IRQ_USIM0_CODE	 MD_IRQID_USIM0
+#define 	IRQ_USIM1_CODE	 MD_IRQID_USIM1
+#define 	IRQ_TOPSM_CODE	 MD_IRQID_TOPSM
+#define 	IRQ_MDGDMA0_CODE	 MD_IRQID_MDGDMA0
+#define 	IRQ_MDGDMA1_CODE	 MD_IRQID_MDGDMA1
+#define 	IRQ_MDGDMA2_CODE	 MD_IRQID_MDGDMA2
+#define 	IRQ_MDGDMA3_CODE	 MD_IRQID_MDGDMA3
+#define 	IRQ_EINT0_CODE	 MD_IRQID_EINT0
+#define 	IRQ_EINT1_CODE	 MD_IRQID_EINT1
+#define 	IRQ_EINT2_CODE	 MD_IRQID_EINT2
+#define 	IRQ_EINT_SHARE_CODE	 MD_IRQID_EINT_SHARE
+#define 	IRQ_BUS_ERR_CODE	 MD_IRQID_BUS_ERR
+#define 	IRQ_TXBRP0_CODE	 MD_IRQID_TXBRP0
+#define 	IRQ_TXBRP1_CODE	 MD_IRQID_TXBRP1
+#define 	IRQ_TXCRP_CODE	 MD_IRQID_TXCRP
+#define 	IRQ_MML2_HRT_CODE	 MD_IRQ_ID_MML2_HRT
+#define 	IRQ_MML2_NOTIF_CODE	 MD_IRQ_ID_MML2_NOTIF
+#define 	IRQ_MML2_EXCEP_CODE	 MD_IRQ_ID_MML2_EXCEP
+#define 	IRQ_DEM_TRIG_PS_INT_LE_CODE	 MD_IRQID_DEM_TRIG_PS_INT_LE
+#define 	IRQ_ECT_CODE	 MD_IRQID_ECT
+#define 	IRQ_PTP_THERM_INT_INT_CODE	 MD_IRQID_PTP_THERM_INT_INT
+#define 	IRQ_CLDMA_CODE	 MD_IRQID_CLDMA
+#define 	IRQ_MDINFRA_BUSMON_MATCH_STS_CODE	 MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define 	IRQ_ELM_DMA_IRQ_CODE	 MD_IRQID_ELM_DMA_IRQ
+#define 	IRQ_SOE_CODE	 MD_IRQID_SOE
+#define 	IRQ_ULSP_LOG_MD_INT_CODE	 MD_IRQID_ULSP_LOG_MD_INT
+#define 	IRQ_ULSP_LOG_DSP_INT_CODE	 MD_IRQID_ULSP_LOG_DSP_INT
+#define 	IRQ_USIP0_0_CODE	 MD_IRQID_USIP0_0
+#define 	IRQ_USIP1_0_CODE	 MD_IRQID_USIP1_0
+#define 	IRQ_USIP2_0_CODE	 MD_IRQID_USIP2_0
+#define 	IRQ_USIP3_0_CODE	 MD_IRQID_USIP3_0
+#define 	IRQ_USIP0_1_CODE	 MD_IRQID_USIP0_1
+#define 	IRQ_USIP1_1_CODE	 MD_IRQID_USIP1_1
+#define 	IRQ_AP2MD_CCIF2_0_CODE	 MD_IRQID_AP2MD_CCIF2_0
+#define 	IRQ_USIP3_1_CODE	 MD_IRQID_USIP3_1
+#define 	IRQ_SI_CM_ERR_CODE	 MD_IRQID_SI_CM_ERR
+#define 	IRQ_ABM_INT_CODE	 MD_IRQID_ABM_INT
+#define 	IRQ_ABM_ERROR_INT_CODE	 MD_IRQID_ABM_ERROR_INT
+#define 	IRQ_MDMCU_BUSMON_MATCH_STS_CODE	 MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define 	IRQ_ELMTOP_EMI_IRQ_CODE	 MD_IRQID_ELMTOP_EMI_IRQ
+#define 	IRQ_PPPHA_ENC0_INT_CODE	 MD_IRQID_PPPHA_ENC0_INT
+#define 	IRQ_PPPHA_ENC1_INT_CODE	 MD_IRQID_PPPHA_ENC1_INT
+#define 	IRQ_PPPHA_DEC0_INT_CODE	 MD_IRQID_PPPHA_DEC0_INT
+#define 	IRQ_PPPHA_DEC1_INT_CODE	 MD_IRQID_PPPHA_DEC1_INT
+#define 	IRQ_PTP_FSM_INT_CODE	 MD_IRQID_PTP_FSM_INT
+#define 	IRQ_PTP_SLPCTL_EVENT_CODE	 MD_IRQID_PTP_SLPCTL_EVENT
+#define 	IRQ_IEBIT_CHECK_IRQ0_CODE	 MD_IRQID_IEBIT_CHECK_IRQ0
+#define 	IRQ_IEBIT_CHECK_IRQ1_CODE	 MD_IRQID_IEBIT_CHECK_IRQ1
+#define 	IRQ_IEBIT_CHECK_IRQ2_CODE	 MD_IRQID_IEBIT_CHECK_IRQ2
+#define 	IRQ_IEBIT_CHECK_IRQ3_CODE	 MD_IRQID_IEBIT_CHECK_IRQ3
+#define 	IRQ_MDCIRQ_WDT0_CODE	 MD_IRQID_MDCIRQ_WDT0
+#define 	IRQ_MDCIRQ_WDT1_CODE	 MD_IRQID_MDCIRQ_WDT1
+#define 	IRQ_TRACE_INT_CODE	 MD_IRQID_TRACE_INT
+#define 	IRQ_SI_CM_PCINT_CODE	 MD_IRQID_SI_CM_PCINT
+#define 	IRQ_PLL_GEARHP_RDY_CODE	 MD_IRQID_PLL_GEARHP_RDY
+#define 	IRQ_DCXO_RDY_WO_ACK_IRQ_CODE	 MD_IRQID_DCXO_RDY_WO_ACK_IRQ
+#define 	IRQ_REQ_ABNORM_IRQ_CODE	 MD_IRQID_REQ_ABNORM_IRQ
+#define 	IRQ_TOP_PLL_DSNS_IRQ_CODE	 MD_IRQID_TOP_PLL_DSNS_IRQ
+#define 	IRQ_BT_CVSD_CODE	 MD_IRQID_BT_CVSD
+#define 	IRQ_SSUSB_USB_MCU_CODE	 MD_IRQID_SSUSB_USB_MCU
+#define 	IRQ_SSUSB_DEV_CODE	 MD_IRQID_SSUSB_DEV
+#define 	IRQ_AP2MD_DVFS_BLOCK_ELM_CODE	 MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define 	IRQ_AP2MD_CCIF0_0_CODE	 MD_IRQID_AP2MD_CCIF0_0
+#define 	IRQ_AP2MD_CCIF0_1_CODE	 MD_IRQID_AP2MD_CCIF0_1
+#define 	IRQ_AP2MD_CCIF1_0_CODE	 MD_IRQID_AP2MD_CCIF1_0
+#define 	IRQ_AP2MD_CCIF1_1_CODE	 MD_IRQID_AP2MD_CCIF1_1
+#define 	IRQ_RXDFE_RXK_READBACK_CODE	 MD_IRQID_RXDFE_RXK_READBACK
+#define 	IRQ_BR_DMA_IRQ_CODE	 MD_IRQID_BR_DMA_IRQ
+#define 	IRQ_IDC_PM_INT_CODE	 MD_IRQID_IDC_PM_INT
+#define 	IRQ_IDC_UART_IRQ_CODE	 MD_IRQID_IDC_UART_IRQ
+#define 	IRQ_MDRTT_CODE	 MD_IRQID_MDRTT
+#define 	IRQ_MDEVDO_CODE	 MD_IRQID_MDEVDO
+#define 	IRQ_MDM2C_U3G_CODE	 MD_IRQID_MDM2C_U3G
+#define 	IRQ_MDDFE_DUMP_CODE	 MD_IRQID_MDDFE_DUMP
+#define 	IRQ_RAKE_CMIF_M2C_IRQ_0_CODE	 MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define 	IRQ_RAKE_CMIF_M2C_IRQ_1_CODE	 MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define 	IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE	 MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define 	IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE	 MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define 	IRQ_RAKE_CMIF_PD_DO_IRQ_CODE	 MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define 	IRQ_BIGRAM_IRQ_CODE	 MD_IRQID_BIGRAM_IRQ
+#define 	IRQ_BR_BDGE_IRQ_CODE	 MD_IRQID_BR_BDGE_IRQ
+#define 	IRQ_L1_LTE_SLEEP_IRQ_CODE	 MD_IRQID_L1_LTE_SLEEP_IRQ
+#define 	IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE	 MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define 	IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE	 MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define 	IRQ_L1M_PHY_LTMR_IRQ_0_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define 	IRQ_L1M_PHY_LTMR_IRQ_1_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define 	IRQ_L1M_PHY_LTMR_IRQ_2_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define 	IRQ_L1M_PHY_LTMR_IRQ_3_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define 	IRQ_L1M_PHY_LTMR_IRQ_4_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define 	IRQ_L1M_PHY_LTMR_IRQ_5_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define 	IRQ_L1M_PHY_LTMR_IRQ_6_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define 	IRQ_L1M_PHY_LTMR_IRQ_7_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define 	IRQ_L1_LTE_WAKEUP_IRQ_CODE	 MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define 	IRQ_MDL1_TOPSM_IRQ_CODE	 MD_IRQID_MDL1_TOPSM_IRQ
+#define 	IRQ_TDD_WAKEUP_IRQ_CODE	 MD_IRQID_TDD_WAKEUP_IRQ
+#define 	IRQ_TDD_TIMER_L1D_1_IRQ_CODE	 MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define 	IRQ_TDD_TIMER_L1D_2_IRQ_CODE	 MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define 	IRQ_RTR_FRAME_IRQ_CODE	 MD_IRQID_RTR_FRAME_IRQ
+#define 	IRQ_RTR_SLT_0_IRQ_CODE	 MD_IRQID_RTR_SLT_0_IRQ
+#define 	IRQ_RTR_SLT_1_IRQ_CODE	 MD_IRQID_RTR_SLT_1_IRQ
+#define 	IRQ_FDD_SLP_IRQ_CODE	 MD_IRQID_FDD_SLP_IRQ
+#define 	IRQ_TDMA_WAKEUP_IRQ_CODE	 MD_IRQID_TDMA_WAKEUP_IRQ
+#define 	IRQ_MD_DVFS_CTRL_IRQ_CODE	 MD_IRQID_MD_DVFS_CTRL_IRQ
+#define 	IRQ_BSI_MM_I_IRQ_RFIC_CODE	 MD_IRQID_BSI_MM_I_IRQ_RFIC
+#define 	IRQ_BSI_MM_I_IRQ_MIPI_CODE	 MD_IRQID_BSI_MM_I_IRQ_MIPI
+#define 	IRQ_ST1X_CPINT_CODE	 MD_IRQID_ST1X_CPINT
+#define 	IRQ_ST1x_HALF_CPINT_CODE	 MD_IRQID_ST1x_HALF_CPINT
+#define 	IRQ_ST1x_CFG_CPINT_CODE	 MD_IRQID_ST1x_CFG_CPINT
+#define 	IRQ_ST1x_WAKEUP_IRQ_CODE	 MD_IRQID_ST1x_WAKEUP_IRQ
+#define 	IRQ_STDO_CPINT_CODE	 MD_IRQID_STDO_CPINT
+#define 	IRQ_STDO_HALF_CPINT_CODE	 MD_IRQID_STDO_HALF_CPINT
+#define 	IRQ_STDO_CFG_CPINT_CODE	 MD_IRQID_STDO_CFG_CPINT
+#define 	IRQ_STDO_WAKEUP_IRQ_CODE	 MD_IRQID_STDO_WAKEUP_IRQ
+#define 	IRQ_FREQM_IRQ_CODE	 MD_IRQID_FREQM_IRQ
+#define 	IRQ_SPM2MD_DVFS_MDPERISYS_CODE	 MD_IRQID_SPM2MD_DVFS_MDPERISYS
+#define 	IRQ_TXDFE_BB_IRQ_CODE	 MD_IRQID_TXDFE_BB_IRQ
+#define 	IRQ_PCC_TOP_FULL_IRQ_CODE	 MD_IRQID_PCC_TOP_FULL_IRQ
+#define 	IRQ_GPTM1_CODE	 MD_IRQID_GPTM1
+#define 	IRQ_GPTM2_CODE	 MD_IRQID_GPTM2
+#define 	IRQ_GPTM3_CODE	 MD_IRQID_GPTM3
+#define 	IRQ_GPTM4_CODE	 MD_IRQID_GPTM4
+#define 	IRQ_GPTM5_CODE	 MD_IRQID_GPTM5
+#define 	IRQ_GPTM6_CODE	 MD_IRQID_GPTM6
+#define 	IRQ_GPTM7_CODE	 MD_IRQID_GPTM7
+#define 	IRQ_GPTM8_CODE	 MD_IRQID_GPTM8
+#define 	IRQ_GPTM9_CODE	 MD_IRQID_GPTM9
+#define 	IRQ_GPTM10_CODE	 MD_IRQID_GPTM10
+#define 	IRQ_GPTM11_CODE	 MD_IRQID_GPTM11
+#define 	IRQ_BUSMPU_IRQ_CODE	 MD_IRQID_BUSMPU_IRQ
+#define 	IRQ_SW_LISR1_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_0
+#define 	IRQ_SW_LISR2_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_1
+#define 	IRQ_SW_LISR3_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_2
+#define 	IRQ_SW_LISR4_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_3
+#define 	IRQ_SW_LISR5_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_4
+#define 	IRQ_SW_LISR6_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_5
+#define 	IRQ_SW_LISR7_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_6
+#define 	IRQ_SW_LISR8_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_7
+#define 	IRQ_SW_LISR9_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_8
+#define 	IRQ_SW_LISR10_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_9
+#define 	IRQ_SW_LISR11_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_10
+#define 	IRQ_SW_LISR12_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_11
+#define 	IRQ_SW_LISR13_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_12
+#define 	IRQ_SW_LISR14_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_13
+#define 	IRQ_SW_LISR15_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_14
+#define 	IRQ_SW_LISR16_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_15
+#define 	IRQ_SW_LISR17_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_16
+#define 	IRQ_SW_LISR18_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_17
+#define 	IRQ_SW_LISR19_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_18
+#define 	IRQ_SW_LISR20_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_19
+#define 	IRQ_SW_LISR21_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_20
+#define 	IRQ_SW_LISR22_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_21
+#define 	IRQ_SW_LISR23_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_22
+#define 	IRQ_SW_LISR24_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_23
+#define 	IRQ_SW_LISR25_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_24
+#define 	IRQ_SW_LISR26_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_25
+#define 	IRQ_SW_LISR27_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_26
+#define 	IRQ_SW_LISR28_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_27
+#define 	IRQ_SW_LISR29_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_28
+#define 	IRQ_SW_LISR30_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_29
+#define 	IRQ_SW_LISR31_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_30
+#define 	IRQ_SW_LISR32_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_31
+#define 	IRQ_SW_LISR33_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_32
+#define 	IRQ_SW_LISR34_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_33
+#define 	IRQ_SW_LISR35_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_34
+#define 	IRQ_SW_LISR36_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_35
+#define 	IRQ_SW_LISR37_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_36
+#define 	IRQ_SW_LISR38_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_37
+#define 	IRQ_SW_LISR39_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_38
+#define 	IRQ_SW_LISR40_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_39
+#define 	IRQ_SW_LISR41_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_40
+#define 	IRQ_SW_LISR42_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_41
+#define 	IRQ_SW_LISR43_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_42
+#define 	IRQ_SW_LISR44_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_43
+#define 	IRQ_SW_LISR45_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_44
+#define 	IRQ_SW_LISR46_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_45
+#define 	IRQ_SW_LISR47_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_46
+#define 	IRQ_SW_LISR48_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_47
+#define 	IRQ_SW_LISR49_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_48
+#define 	IRQ_SW_LISR50_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_49
+#define 	IRQ_SW_LISR51_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_50
+#define 	IRQ_SW_LISR52_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_51
+#define 	IRQ_SW_LISR53_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_52
+#define 	IRQ_SW_LISR54_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_53
+#define 	IRQ_SW_LISR55_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_54
+#define 	IRQ_SW_LISR56_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_55
+#define 	IRQ_SW_LISR57_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_56
+#define 	IRQ_SW_LISR58_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_57
+#define 	IRQ_SW_LISR59_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_58
+#define 	IRQ_SW_LISR60_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_59
+#define 	IRQ_SW_LISR61_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_60
+#define 	IRQ_SW_LISR62_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_61
+#define 	IRQ_SW_LISR63_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_62
+#define 	IRQ_SW_LISR64_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_63
+#define     MCU_BUS_DECERR_CODE  MD_IRQID_MCU_BUS_DECERR
+#define     GIC0_FDCInt_CODE  MD_IRQID_GIC0_FDCInt
+#define     GIC0_FDCInt_1_CODE  MD_IRQID_GIC0_FDCInt_1
+#define     GIC0_PCInt_CODE  MD_IRQID_GIC0_PCInt
+#define     GIC0_PCInt_1_CODE  MD_IRQID_GIC0_PCInt_1
+#define     GIC0_TimerInt_CODE  MD_IRQID_GIC0_TimerInt
+#define     GIC0_TimerInt_1_CODE  MD_IRQID_GIC0_TimerInt_1
+#define     GIC1_FDCInt_CODE  MD_IRQID_GIC1_FDCInt
+#define     GIC1_FDCInt_1_CODE  MD_IRQID_GIC1_FDCInt_1
+#define     GIC1_PCInt_CODE  MD_IRQID_GIC1_PCInt
+#define     GIC1_PCInt_1_CODE  MD_IRQID_GIC1_PCInt_1
+#define     GIC1_TimerInt_CODE  MD_IRQID_GIC1_TimerInt
+#define     GIC1_TimerInt_1_CODE  MD_IRQID_GIC1_TimerInt_1
+#define     IRQ_EINT3_CODE  MD_IRQID_EINT3
+#define     MCUMMU_INT_CODE  MD_IRQID_MCUMMU_INT
+#define     SPRAM_DECERR_CODE  MD_IRQID_IA_DECERR
+#define     RMPU_CTIREIGIN_CODE  MD_IRQID_RMPU_CTIREIGIN
+#define     MDSM_CORE_PWR_CTRL_CODE  MD_IRQID_MDSM_CORE_PWR_CTRL
+#define     AP2MD_MSDC0_CODE  MD_IRQID_AP2MD_MSDC0
+
+
+
+/*
+ * Define IRQ selection register assignment
+ */
+#define IRQSel()
+//#define INVALID_ISR_ID           (0xFF)
+
+#define INTERRUPT_PRIORITY_LIST \
+/*  0 ~  7 */  69, 127,  67,  68,  66,  38,  32,  61, \
+/*  8 ~ 15 */  88,  78, 127, 127, 127, 127, 127, 127, \
+/* 16 ~ 23 */ 127, 110,  42, 127, 127, 127, 127, 127, \
+/* 24 ~ 31 */ 127, 127,  64, 127, 127, 123, 124, 122, \
+/* 32 ~ 39 */ 127,   6,   7, 127,   6, 127, 127, 127, \
+/* 40 ~ 47 */ 127,  71,  41,  39,  62,  45, 127, 127, \
+/* 48 ~ 55 */ 127, 127, 127, 127, 127, 127, 117, 118, \
+/* 56 ~ 63 */ 119, 120, 126, 127,   6,   6,   6,   6, \
+/* 64 ~ 71 */ 110, 110, 127, 127, 127, 127, 127, 127, \
+/* 72 ~ 79 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 80 ~ 87 */  45, 127, 127, 127,  56,  54, 127, 115, \
+/* 88 ~ 95 */  58,  36,  55,  33,  86,   6,   6,  51, \
+/* 96 ~103 */  40,  47,  30, 127,  46,  43,  43,  43, \
+/*104 ~111 */  46,  44,  28,  86,  27,  34,  35, 110, \
+/*112 ~119 */  31,  49,  26,  64,  25, 127, 127,  59, \
+/*120 ~127 */ 110,  58,  29,  59,  59,  58,  29,  90, \
+/*128 ~135 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*136 ~143 */  70,  77,  44, 127, 127, 127, 127, 127, \
+/*144 ~151 */ 110, 127, 110,   7,   7,  76,  71,  77, \
+/*152 ~159 */  50,  51,  52,  79,  76,  77,  39,  72, \
+/*160 ~167 */  74,  75,  48, 127, 127,  63,   8, 127, \
+/*168 ~175 */ 110, 127, 110, 110,   6, 127, 127, 127, \
+/*176 ~183 */  75,  75, 127, 127,   7, 111,   7, 111, \
+/*184 ~191 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*192 ~199 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*200 ~207 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*208 ~215 */ 127, 110, 127, 110, 127, 110, 127, 110, \
+/*216 ~223 */ 127, 110, 127, 110, 127, 127, 127,   6, \
+/*224 ~231 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*232 ~239 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*240 ~247 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*248 ~255 */ 127, 127, 127, 127, 127, 127, 127, 127,
+
+#if defined(__ESL_MASE__)
+
+/* for OS ICC
+   IRQ_SW_LISR1_CODE
+   IRQ_SW_LISR2_CODE
+   IRQ_SW_LISR3_CODE
+   IRQ_SW_LISR4_CODE
+*/
+#define INTERRUPT_GROUP_LIST \
+	/*	0 ~  7 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*	8 ~ 15 */  0,  0,  0,  1,  0,  0,  0,  0, \
+	/* 16 ~ 23 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 24 ~ 31 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 32 ~ 39 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 40 ~ 47 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 48 ~ 55 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 56 ~ 63 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 64 ~ 71 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 72 ~ 79 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 80 ~ 87 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 88 ~ 95 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 96 ~103 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*104 ~111 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*112 ~119 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*120 ~127 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*128 ~135 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*136 ~143 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*144 ~151 */  1,  2,  3,  0,  0,  0,  0,  0, \
+	/*152 ~159 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*160 ~167 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*168 ~175 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*176 ~183 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*184 ~191 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*192 ~199 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*200 ~207 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*208 ~215 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*216 ~223 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*224 ~231 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*232 ~239 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*240 ~247 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*248 ~255 */  0,  0,  0,  0,  0,  0,  0,  0
+#else  /* __ESL_MASE__*/ 
+#define INTERRUPT_GROUP_LIST \
+	/*  0 ~  7 */  1,  4,  1,  1,  1,  1,  1,  0, \
+	/*  8 ~ 15 */  1,  1, 17,  4,  4,  0,  4,  4, \
+	/* 16 ~ 23 */  4,  1,  1,  4,  4,  4,  4,  4, \
+	/* 24 ~ 31 */  4,  4,  1,  4,  4,  4,  4,  4, \
+	/* 32 ~ 39 */  0,  5,  0,  4,  5,  4,  4,  4, \
+	/* 40 ~ 47 */  4,  0,  1,  1,  1,  3,  4,  4, \
+	/* 48 ~ 55 */  4,  4,  0,  0,  4,  4,  4,  4, \
+	/* 56 ~ 63 */  4,  4,  4,  4,  5,  5,  5,  5, \
+	/* 64 ~ 71 */  1,  3,  0,  4,  4,  4,  4,  4, \
+	/* 72 ~ 79 */  4,  4,  4,  4,  4,  5,  4,  4, \
+	/* 80 ~ 87 */  3,  4,  4,  0,  1,  1,  4,  4, \
+	/* 88 ~ 95 */  1,  1,  1,  1,  1,  5,  5,  3, \
+	/* 96 ~103 */  1,  3,  1,  4,  3,  1,  1,  1, \
+	/*104 ~111 */  3,  3,  3,  0,  1,  1,  1,  1, \
+	/*112 ~119 */  1,  3,  1,  1,  0,  4,  4,  1, \
+	/*120 ~127 */  1,  1,  1,  1,  1,  1,  1,  0, \
+	/*128 ~135 */  4,  4,  0,  4,  4,  4,  4,  4, \
+	/*136 ~143 */  1,  1,  3,  4,  4,  4,  4,  0, \
+	/*144 ~151 */  1,  2,  3,  0,  2,  1,  1,  1, \
+	/*152 ~159 */  3,  1,  3,  1,  1,  1,  1,  1, \
+	/*160 ~167 */  1,  1,  6,  5,  4,  1,  0,  0, \
+	/*168 ~175 */  1,  2,  3,  1,  5, 16,  0,  2, \
+	/*176 ~183 */  1,  1,  0,  2,  0,  1,  2,  3, \
+	/*184 ~191 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*192 ~199 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*200 ~207 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*208 ~215 */  0,  1,  0,  1,  0,  1,  2,  3, \
+	/*216 ~223 */  2,  3,  2,  3,  4,  4,  4,  4, \
+	/*224 ~231 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*232 ~239 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*240 ~247 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*248 ~255 */  4,  4,  4,  4,  4,  4,  4,  4
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+	/* Group0(0) */                0xE, \
+	/* Group1(1) */                0xD, \
+	/* Group2(2) */                0xB, \
+	/* Group3(3) */                0x7, \
+	/* Group4(0,2) */              0xA, \
+	/* Group5(0,1,2,3) */          0x0, \
+	/* Group6(1,3) */              0x5, \
+	/* Group7 */                   0xF, \
+	/* Group8 */                   0xF, \
+	/* Group9 */                   0xF, \
+	/* Group10 */                  0xF, \
+	/* Group11 */                  0xF, \
+	/* Group12 */                  0xF, \
+	/* Group13 */                  0xF, \
+	/* Group14*/                   0xF, \
+	/* Group15 */                  0xF,
+#endif
+
+#define NMI_GROUP_M2V_LIST \
+	/* Group0(exception usage) */  0xF, \
+	/* Group1 */                   0x0,
+
+#if defined(__MDCIRQ_WAIT_MODE_ENABLE__)
+#define INTERRUPT_BROADCAST_TYPE \
+	/*  0-31 */                0x040627FD, \
+	/* 32-63 */                0xF00C3E17, \
+	/* 64-95 */                0xFF392007, \
+	/* 96-127 */               0xFF9FFFF7, \
+	/* 128-159 */              0xFFFF8704, \
+	/* 160-191 */              0x00FFDFFF, \
+	/* 192-223 */              0x0FFF0000, \
+	/* 224-255 */              0x00000000,
+#else
+#define INTERRUPT_BROADCAST_TYPE \
+	/*  0-31 */                0x00000400, \
+	/* 32-63 */                0xF0000012, \
+	/* 64-95 */                0x60002000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x0000101C, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000,
+#endif
+
+#define INTERRUPT_TYPE \
+	/*  0-31 */                0x00000400, \
+	/* 32-63 */                0x00000000, \
+	/* 64-95 */                0x00000000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x00002000, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000,
+
+#define INTERRUPT_HRT_MT \
+	/*  0-31 */                0x00000000, \
+	/* 32-63 */                0x00000000, \
+	/* 64-95 */                0x00000000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x00000000, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000,
+
+
+#define INTERRUPT_TIMING_THRESHOLD \
+	/*	VPE0 */  0xFFFFFFFF,\
+	/*	VPE1 */  0xFFFFFFFF,\
+	/*	VPE2 */  0xFFFFFFFF,\
+	/*	VPE3 */  0xFFFFFFFF,
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+//#define EINT_TOTAL_CHANNEL 16
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+    VPE_STATUS_DORMANT           = 0,
+    VPE_STATUS_LISR_HIGHEST      = 1,
+    VPE_STATUS_LISR_LOWEST       = 127,
+    VPE_STATUS_HISR_TASK_HIGHEST = 128,
+    VPE_STATUS_HISR_TASK_LOWEST  = 386, 
+    VPE_STATUS_END               = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+    IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+    IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+    IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+    IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+    IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+    IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+    IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+    IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+    IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+    IRQ_MDWDT = IRQ_MDWDT_CODE,
+    IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+    IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+    IRQ_OST = IRQ_OST_CODE,
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+    IRQ_USIM1 = IRQ_USIM1_CODE,
+    IRQ_TOPSM = IRQ_TOPSM_CODE,
+    IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+    IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+    IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+    IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+    IRQ_EINT0 = IRQ_EINT0_CODE,
+    IRQ_EINT1 = IRQ_EINT1_CODE,
+    IRQ_EINT2 = IRQ_EINT2_CODE,
+    IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+    IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+    IRQ_TXBRP0 = IRQ_TXBRP0_CODE,
+    IRQ_TXBRP1 = IRQ_TXBRP1_CODE,
+    IRQ_TXCRP = IRQ_TXCRP_CODE,
+    IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+    IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+    IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+    IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+    IRQ_ECT = IRQ_ECT_CODE,
+    IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+    IRQ_CLDMA = IRQ_CLDMA_CODE,
+    IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+    IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+    IRQ_SOE = IRQ_SOE_CODE,
+    IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+    IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+    IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+    IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+    IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+    IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+    IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+    IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+    IRQ_AP2MD_CCIF2_0 = IRQ_AP2MD_CCIF2_0_CODE,
+    IRQ_USIP3_1 = IRQ_USIP3_1_CODE,
+    IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+    IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+    IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+    IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+    IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+    IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+    IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+    IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+    IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+    IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+    IRQ_PTP_SLPCTL_EVENT = IRQ_PTP_SLPCTL_EVENT_CODE,
+    IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+    IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+    IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+    IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+    IRQ_MDCIRQ_WDT0 = IRQ_MDCIRQ_WDT0_CODE,
+    IRQ_MDCIRQ_WDT1 = IRQ_MDCIRQ_WDT1_CODE,
+    IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+    IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+    IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+    IRQ_DCXO_RDY_WO_ACK_IRQ = IRQ_DCXO_RDY_WO_ACK_IRQ_CODE,
+    IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+    IRQ_TOP_PLL_DSNS_IRQ = IRQ_TOP_PLL_DSNS_IRQ_CODE,
+    IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+    IRQ_SSUSB_USB_MCU = IRQ_SSUSB_USB_MCU_CODE,
+    IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+    IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+    IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+    IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+    IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+    IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+    IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+    IRQ_BR_DMA_IRQ = IRQ_BR_DMA_IRQ_CODE,
+    IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+    IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+    IRQ_MDRTT = IRQ_MDRTT_CODE,
+    IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+    IRQ_MDM2C_U3G = IRQ_MDM2C_U3G_CODE,
+    IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+    IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+    IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+    IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+    IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+    IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+    IRQ_MDL1_TOPSM_IRQ = IRQ_MDL1_TOPSM_IRQ_CODE,
+    IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+    IRQ_RTR_FRAME_IRQ = IRQ_RTR_FRAME_IRQ_CODE,
+    IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+    IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+    IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+    IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+    IRQ_MD_DVFS_CTRL_IRQ = IRQ_MD_DVFS_CTRL_IRQ_CODE,
+    IRQ_BSI_MM_I_IRQ_RFIC = IRQ_BSI_MM_I_IRQ_RFIC_CODE,
+    IRQ_BSI_MM_I_IRQ_MIPI = IRQ_BSI_MM_I_IRQ_MIPI_CODE,
+    IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+    IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+    IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+    IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+    IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+    IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+    IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+    IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+    IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+    IRQ_SPM2MD_DVFS_MDPERISYS = IRQ_SPM2MD_DVFS_MDPERISYS_CODE,
+    IRQ_TXDFE_BB_IRQ = IRQ_TXDFE_BB_IRQ_CODE,
+    IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+    IRQ_GPTM1 = IRQ_GPTM1_CODE,
+    IRQ_GPTM2 = IRQ_GPTM2_CODE,
+    IRQ_GPTM3 = IRQ_GPTM3_CODE,
+    IRQ_GPTM4 = IRQ_GPTM4_CODE,
+    IRQ_GPTM5 = IRQ_GPTM5_CODE,
+    IRQ_GPTM6 = IRQ_GPTM6_CODE,
+    IRQ_GPTM7 = IRQ_GPTM7_CODE,
+    IRQ_GPTM8 = IRQ_GPTM8_CODE,
+    IRQ_GPTM9 = IRQ_GPTM9_CODE,
+    IRQ_GPTM10 = IRQ_GPTM10_CODE,
+    IRQ_GPTM11 = IRQ_GPTM11_CODE,
+    IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+    IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+    IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+    IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+    IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+    IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+    IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+    IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+    IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+    IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+    IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+    IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+    IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+    IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+    IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+    IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+    IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+    IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+    IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+    IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+    IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+    IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+    IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+    IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+    IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+    IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+    IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+    IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+    IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+    IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+    IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+    IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+    IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+    IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+    IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+    IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+    IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+    IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+    IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+    IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+    IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+    IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+    IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+    IRQ_SW_LISR43 = IRQ_SW_LISR43_CODE,
+    IRQ_SW_LISR44 = IRQ_SW_LISR44_CODE,
+    IRQ_SW_LISR45 = IRQ_SW_LISR45_CODE,
+    IRQ_SW_LISR46 = IRQ_SW_LISR46_CODE,
+    IRQ_SW_LISR47 = IRQ_SW_LISR47_CODE,
+    IRQ_SW_LISR48 = IRQ_SW_LISR48_CODE,
+    IRQ_SW_LISR49 = IRQ_SW_LISR49_CODE,
+    IRQ_SW_LISR50 = IRQ_SW_LISR50_CODE,
+    IRQ_SW_LISR51 = IRQ_SW_LISR51_CODE,
+    IRQ_SW_LISR52 = IRQ_SW_LISR52_CODE,
+    IRQ_SW_LISR53 = IRQ_SW_LISR53_CODE,
+    IRQ_SW_LISR54 = IRQ_SW_LISR54_CODE,
+    IRQ_SW_LISR55 = IRQ_SW_LISR55_CODE,
+    IRQ_SW_LISR56 = IRQ_SW_LISR56_CODE,
+    IRQ_SW_LISR57 = IRQ_SW_LISR57_CODE,
+    IRQ_SW_LISR58 = IRQ_SW_LISR58_CODE,
+    IRQ_SW_LISR59 = IRQ_SW_LISR59_CODE,
+    IRQ_SW_LISR60 = IRQ_SW_LISR60_CODE,
+    IRQ_SW_LISR61 = IRQ_SW_LISR61_CODE,
+    IRQ_SW_LISR62 = IRQ_SW_LISR62_CODE,
+    IRQ_SW_LISR63 = IRQ_SW_LISR63_CODE,
+    IRQ_SW_LISR64 = IRQ_SW_LISR64_CODE,
+    MCU_BUS_DECERR = MCU_BUS_DECERR_CODE,
+    GIC0_FDCInt = GIC0_FDCInt_CODE,
+    GIC0_FDCInt_1 = GIC0_FDCInt_1_CODE,
+    GIC0_PCInt = GIC0_PCInt_CODE,
+    GIC0_PCInt_1 = GIC0_PCInt_1_CODE,
+    GIC0_TimerInt = GIC0_TimerInt_CODE,
+    GIC0_TimerInt_1 = GIC0_TimerInt_1_CODE,
+    GIC1_FDCInt = GIC1_FDCInt_CODE,
+    GIC1_FDCInt_1 = GIC1_FDCInt_1_CODE,
+    GIC1_PCInt = GIC1_PCInt_CODE,
+    GIC1_PCInt_1 = GIC1_PCInt_1_CODE,
+    GIC1_TimerInt = GIC1_TimerInt_CODE,
+    GIC1_TimerInt_1 = GIC1_TimerInt_1_CODE,
+    IRQ_EINT3 = IRQ_EINT3_CODE,
+    MCUMMU_INT = MCUMMU_INT_CODE,
+    SPRAM_DECERR = SPRAM_DECERR_CODE,
+    RMPU_CTIREIGIN = RMPU_CTIREIGIN_CODE,
+    MDSM_CORE_PWR_CTRL = MDSM_CORE_PWR_CTRL_CODE,
+    AP2MD_MSDC0 = AP2MD_MSDC0_CODE 
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+    GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+
+#endif /* end of __INTRCTRL_MT6765_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6765_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6765_SW_Handle.h
new file mode 100644
index 0000000..dcb848d
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6765_SW_Handle.h
@@ -0,0 +1,290 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6765_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   MT6765
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 10 2017 yen-chun.liu
+ * [MOLY00270029] [System Service][KAL] Gen93 dummy LISR APIs
+ * dummy LISR driver.
+ *
+ * 08 03 2017 yen-chun.liu
+ * [MOLY00267971] [SWLA] New Snapshot API for Robust Modem Feature
+ * 2 new SW interrupt for SWLA.
+ *
+ * 06 13 2017 yen-chun.liu
+ * [MOLY00244660] [MT6739][Gen93][System Service][MDCIRQ] Compile option for ZION(MT6739)
+ * .
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE1 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE2 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE3 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE4 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE5 = HC Yang
+      SW_TRIGGER_CODE6 = HC Yang
+      SW_TRIGGER_CODE7 = Max Weng
+      SW_TRIGGER_CODE8 = Max Weng
+      SW_TRIGGER_CODE9 = Max Weng
+      SW_TRIGGER_CODE10 = Max Weng
+      SW_TRIGGER_CODE11 = Max Weng
+      SW_TRIGGER_CODE12 = Max Weng
+      SW_TRIGGER_CODE13 = Zengling Jin
+      SW_TRIGGER_CODE14 = Zengling Jin
+      SW_TRIGGER_CODE15 = Zengling Jin
+      SW_TRIGGER_CODE16 = Chuansheng Zhang
+      SW_TRIGGER_CODE17 = Chuansheng Zhang
+      SW_TRIGGER_CODE18 = Chuansheng Zhang
+      SW_TRIGGER_CODE19 = Chuansheng Zhang
+      SW_TRIGGER_CODE20 = Huei-Ya Chang
+      SW_TRIGGER_CODE21 = Qmei Yang
+      SW_TRIGGER_CODE22 = Tee-Yuen Chun
+      SW_TRIGGER_CODE23 = Yuni Chang
+      SW_TRIGGER_CODE24 = SY Yeh
+      SW_TRIGGER_CODE25 = Owen Ho
+      SW_TRIGGER_CODE26 = Owen Ho
+      SW_TRIGGER_CODE27 = Owen Ho
+      SW_TRIGGER_CODE28 = Owen Ho
+      SW_TRIGGER_CODE29 = Carl Kao
+      SW_TRIGGER_CODE30 = Wade Huang
+      SW_TRIGGER_CODE31 = Woody kuo
+      SW_TRIGGER_CODE32 = Jun-Ying Huang
+      SW_TRIGGER_CODE33 = Jun-Ying Huang
+      SW_TRIGGER_CODE34 = Weimin Zeng
+      SW_TRIGGER_CODE35 = Weimin Zeng
+      SW_TRIGGER_CODE36 = HW Jheng
+      SW_TRIGGER_CODE37 = HW Jheng
+      SW_TRIGGER_CODE38 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE39 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE40 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE41 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE42 = 
+      SW_TRIGGER_CODE43 = 
+      SW_TRIGGER_CODE44 = 
+      SW_TRIGGER_CODE45 = 
+      SW_TRIGGER_CODE46 = 
+      SW_TRIGGER_CODE47 = 
+      SW_TRIGGER_CODE48 = 
+      SW_TRIGGER_CODE49 = 
+      SW_TRIGGER_CODE50 = 
+      SW_TRIGGER_CODE51 = 
+      SW_TRIGGER_CODE52 = 
+      SW_TRIGGER_CODE53 = 
+      SW_TRIGGER_CODE54 = 
+      SW_TRIGGER_CODE55 = 
+      SW_TRIGGER_CODE56 = 
+      SW_TRIGGER_CODE57 = 
+      SW_TRIGGER_CODE58 = 
+      SW_TRIGGER_CODE59 = 
+      SW_TRIGGER_CODE60 = 
+      SW_TRIGGER_CODE61 = 
+      SW_TRIGGER_CODE62 = 
+      SW_TRIGGER_CODE63 = 
+      SW_TRIGGER_CODE64 = 
+  */
+#if (defined(__MIPS_IA__))
+
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
+
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6765 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6771.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6771.h
new file mode 100644
index 0000000..e488ff6
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6771.h
@@ -0,0 +1,784 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6771.h
+ *
+ * Project:
+ * --------
+ *   TATAKA
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6771_H__
+#define __INTRCTRL_MT6771_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES          (256)
+
+#define 	IRQ_SHARE_D12MINT1_CODE	 MD_IRQID_SHARE_D12MINT1
+#define 	IRQ_IRDBG_MCU_INT_CODE	 MD_IRQID_IRDBG_MCU_INT
+#define 	IRQ_TDMA_CTIRQ1_CODE	 MD_IRQID_TDMA_CTIRQ1
+#define 	IRQ_TDMA_CTIRQ2_CODE	 MD_IRQID_TDMA_CTIRQ2
+#define 	IRQ_TDMA_CTIRQ3_CODE	 MD_IRQID_TDMA_CTIRQ3
+#define 	IRQ_CSSYS_FDD_CS_IRQ_CODE	 MD_IRQID_CSSYS_FDD_CS_IRQ
+#define 	IRQ_CSSYS_TDD_CS_IRQ_CODE	 MD_IRQID_CSSYS_TDD_CS_IRQ
+#define 	IRQ_CSSYS_LTE_CS_IRQ_CODE	 MD_IRQID_CSSYS_LTE_CS_IRQ
+#define 	IRQ_CSSYS_1X_CS_IRQ_CODE	 MD_IRQID_CSSYS_1X_CS_IRQ
+#define 	IRQ_CSSYS_DO_CS_IRQ_CODE	 MD_IRQID_CSSYS_DO_CS_IRQ
+#define 	IRQ_MDWDT_CODE	 MD_IRQID_MDWDT
+#define 	IRQ_UART_MD0_CODE	 MD_IRQID_UART_MD0
+#define 	IRQ_UART_MD1_CODE	 MD_IRQID_UART_MD1
+#define 	IRQ_OST_CODE	 MD_IRQID_OST
+#define 	IRQ_USIM0_CODE	 MD_IRQID_USIM0
+#define 	IRQ_USIM1_CODE	 MD_IRQID_USIM1
+#define 	IRQ_TOPSM_CODE	 MD_IRQID_TOPSM
+#define 	IRQ_MDGDMA0_CODE	 MD_IRQID_MDGDMA0
+#define 	IRQ_MDGDMA1_CODE	 MD_IRQID_MDGDMA1
+#define 	IRQ_MDGDMA2_CODE	 MD_IRQID_MDGDMA2
+#define 	IRQ_MDGDMA3_CODE	 MD_IRQID_MDGDMA3
+#define 	IRQ_EINT0_CODE	 MD_IRQID_EINT0
+#define 	IRQ_EINT1_CODE	 MD_IRQID_EINT1
+#define 	IRQ_EINT2_CODE	 MD_IRQID_EINT2
+#define 	IRQ_EINT_SHARE_CODE	 MD_IRQID_EINT_SHARE
+#define 	IRQ_BUS_ERR_CODE	 MD_IRQID_BUS_ERR
+#define 	IRQ_TXBRP0_CODE	 MD_IRQID_TXBRP0
+#define 	IRQ_TXBRP1_CODE	 MD_IRQID_TXBRP1
+#define 	IRQ_TXCRP_CODE	 MD_IRQID_TXCRP
+#define 	IRQ_MML2_HRT_CODE	 MD_IRQ_ID_MML2_HRT
+#define 	IRQ_MML2_NOTIF_CODE	 MD_IRQ_ID_MML2_NOTIF
+#define 	IRQ_MML2_EXCEP_CODE	 MD_IRQ_ID_MML2_EXCEP
+#define 	IRQ_DEM_TRIG_PS_INT_LE_CODE	 MD_IRQID_DEM_TRIG_PS_INT_LE
+#define 	IRQ_ECT_CODE	 MD_IRQID_ECT
+#define 	IRQ_PTP_THERM_INT_INT_CODE	 MD_IRQID_PTP_THERM_INT_INT
+#define 	IRQ_CLDMA_CODE	 MD_IRQID_CLDMA
+#define 	IRQ_MDINFRA_BUSMON_MATCH_STS_CODE	 MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define 	IRQ_ELM_DMA_IRQ_CODE	 MD_IRQID_ELM_DMA_IRQ
+#define 	IRQ_SOE_CODE	 MD_IRQID_SOE
+#define 	IRQ_ULSP_LOG_MD_INT_CODE	 MD_IRQID_ULSP_LOG_MD_INT
+#define 	IRQ_ULSP_LOG_DSP_INT_CODE	 MD_IRQID_ULSP_LOG_DSP_INT
+#define 	IRQ_USIP0_0_CODE	 MD_IRQID_USIP0_0
+#define 	IRQ_USIP1_0_CODE	 MD_IRQID_USIP1_0
+#define 	IRQ_USIP2_0_CODE	 MD_IRQID_USIP2_0
+#define 	IRQ_USIP3_0_CODE	 MD_IRQID_USIP3_0
+#define 	IRQ_USIP0_1_CODE	 MD_IRQID_USIP0_1
+#define 	IRQ_USIP1_1_CODE	 MD_IRQID_USIP1_1
+#define 	IRQ_AP2MD_CCIF2_0_CODE	 MD_IRQID_AP2MD_CCIF2_0
+#define 	IRQ_USIP3_1_CODE	 MD_IRQID_USIP3_1
+#define 	IRQ_SI_CM_ERR_CODE	 MD_IRQID_SI_CM_ERR
+#define 	IRQ_ABM_INT_CODE	 MD_IRQID_ABM_INT
+#define 	IRQ_ABM_ERROR_INT_CODE	 MD_IRQID_ABM_ERROR_INT
+#define 	IRQ_MDMCU_BUSMON_MATCH_STS_CODE	 MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define 	IRQ_ELMTOP_EMI_IRQ_CODE	 MD_IRQID_ELMTOP_EMI_IRQ
+#define 	IRQ_PPPHA_ENC0_INT_CODE	 MD_IRQID_PPPHA_ENC0_INT
+#define 	IRQ_PPPHA_ENC1_INT_CODE	 MD_IRQID_PPPHA_ENC1_INT
+#define 	IRQ_PPPHA_DEC0_INT_CODE	 MD_IRQID_PPPHA_DEC0_INT
+#define 	IRQ_PPPHA_DEC1_INT_CODE	 MD_IRQID_PPPHA_DEC1_INT
+#define 	IRQ_PTP_FSM_INT_CODE	 MD_IRQID_PTP_FSM_INT
+#define 	IRQ_PTP_SLPCTL_EVENT_CODE	 MD_IRQID_PTP_SLPCTL_EVENT
+#define 	IRQ_IEBIT_CHECK_IRQ0_CODE	 MD_IRQID_IEBIT_CHECK_IRQ0
+#define 	IRQ_IEBIT_CHECK_IRQ1_CODE	 MD_IRQID_IEBIT_CHECK_IRQ1
+#define 	IRQ_IEBIT_CHECK_IRQ2_CODE	 MD_IRQID_IEBIT_CHECK_IRQ2
+#define 	IRQ_IEBIT_CHECK_IRQ3_CODE	 MD_IRQID_IEBIT_CHECK_IRQ3
+#define 	IRQ_MDCIRQ_WDT0_CODE	 MD_IRQID_MDCIRQ_WDT0
+#define 	IRQ_MDCIRQ_WDT1_CODE	 MD_IRQID_MDCIRQ_WDT1
+#define 	IRQ_TRACE_INT_CODE	 MD_IRQID_TRACE_INT
+#define 	IRQ_SI_CM_PCINT_CODE	 MD_IRQID_SI_CM_PCINT
+#define 	IRQ_PLL_GEARHP_RDY_CODE	 MD_IRQID_PLL_GEARHP_RDY
+#define 	IRQ_DCXO_RDY_WO_ACK_IRQ_CODE	 MD_IRQID_DCXO_RDY_WO_ACK_IRQ
+#define 	IRQ_REQ_ABNORM_IRQ_CODE	 MD_IRQID_REQ_ABNORM_IRQ
+#define 	IRQ_TOP_PLL_DSNS_IRQ_CODE	 MD_IRQID_TOP_PLL_DSNS_IRQ
+#define 	IRQ_BT_CVSD_CODE	 MD_IRQID_BT_CVSD
+#define 	IRQ_SSUSB_USB_MCU_CODE	 MD_IRQID_SSUSB_USB_MCU
+#define 	IRQ_SSUSB_DEV_CODE	 MD_IRQID_SSUSB_DEV
+#define 	IRQ_AP2MD_DVFS_BLOCK_ELM_CODE	 MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define 	IRQ_AP2MD_CCIF0_0_CODE	 MD_IRQID_AP2MD_CCIF0_0
+#define 	IRQ_AP2MD_CCIF0_1_CODE	 MD_IRQID_AP2MD_CCIF0_1
+#define 	IRQ_AP2MD_CCIF1_0_CODE	 MD_IRQID_AP2MD_CCIF1_0
+#define 	IRQ_AP2MD_CCIF1_1_CODE	 MD_IRQID_AP2MD_CCIF1_1
+#define 	IRQ_RXDFE_RXK_READBACK_CODE	 MD_IRQID_RXDFE_RXK_READBACK
+#define 	IRQ_BR_DMA_IRQ_CODE	 MD_IRQID_BR_DMA_IRQ
+#define 	IRQ_IDC_PM_INT_CODE	 MD_IRQID_IDC_PM_INT
+#define 	IRQ_IDC_UART_IRQ_CODE	 MD_IRQID_IDC_UART_IRQ
+#define 	IRQ_MDRTT_CODE	 MD_IRQID_MDRTT
+#define 	IRQ_MDEVDO_CODE	 MD_IRQID_MDEVDO
+#define 	IRQ_MDM2C_U3G_CODE	 MD_IRQID_MDM2C_U3G
+#define 	IRQ_MDDFE_DUMP_CODE	 MD_IRQID_MDDFE_DUMP
+#define 	IRQ_RAKE_CMIF_M2C_IRQ_0_CODE	 MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define 	IRQ_RAKE_CMIF_M2C_IRQ_1_CODE	 MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define 	IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE	 MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define 	IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE	 MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define 	IRQ_RAKE_CMIF_PD_DO_IRQ_CODE	 MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define 	IRQ_BIGRAM_IRQ_CODE	 MD_IRQID_BIGRAM_IRQ
+#define 	IRQ_BR_BDGE_IRQ_CODE	 MD_IRQID_BR_BDGE_IRQ
+#define 	IRQ_L1_LTE_SLEEP_IRQ_CODE	 MD_IRQID_L1_LTE_SLEEP_IRQ
+#define 	IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE	 MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define 	IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE	 MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define 	IRQ_L1M_PHY_LTMR_IRQ_0_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define 	IRQ_L1M_PHY_LTMR_IRQ_1_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define 	IRQ_L1M_PHY_LTMR_IRQ_2_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define 	IRQ_L1M_PHY_LTMR_IRQ_3_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define 	IRQ_L1M_PHY_LTMR_IRQ_4_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define 	IRQ_L1M_PHY_LTMR_IRQ_5_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define 	IRQ_L1M_PHY_LTMR_IRQ_6_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define 	IRQ_L1M_PHY_LTMR_IRQ_7_CODE	 MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define 	IRQ_L1_LTE_WAKEUP_IRQ_CODE	 MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define 	IRQ_MDL1_TOPSM_IRQ_CODE	 MD_IRQID_MDL1_TOPSM_IRQ
+#define 	IRQ_TDD_WAKEUP_IRQ_CODE	 MD_IRQID_TDD_WAKEUP_IRQ
+#define 	IRQ_TDD_TIMER_L1D_1_IRQ_CODE	 MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define 	IRQ_TDD_TIMER_L1D_2_IRQ_CODE	 MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define 	IRQ_RTR_FRAME_IRQ_CODE	 MD_IRQID_RTR_FRAME_IRQ
+#define 	IRQ_RTR_SLT_0_IRQ_CODE	 MD_IRQID_RTR_SLT_0_IRQ
+#define 	IRQ_RTR_SLT_1_IRQ_CODE	 MD_IRQID_RTR_SLT_1_IRQ
+#define 	IRQ_FDD_SLP_IRQ_CODE	 MD_IRQID_FDD_SLP_IRQ
+#define 	IRQ_TDMA_WAKEUP_IRQ_CODE	 MD_IRQID_TDMA_WAKEUP_IRQ
+#define 	IRQ_MD_DVFS_CTRL_IRQ_CODE	 MD_IRQID_MD_DVFS_CTRL_IRQ
+#define 	IRQ_BSI_MM_I_IRQ_RFIC_CODE	 MD_IRQID_BSI_MM_I_IRQ_RFIC
+#define 	IRQ_BSI_MM_I_IRQ_MIPI_CODE	 MD_IRQID_BSI_MM_I_IRQ_MIPI
+#define 	IRQ_ST1X_CPINT_CODE	 MD_IRQID_ST1X_CPINT
+#define 	IRQ_ST1x_HALF_CPINT_CODE	 MD_IRQID_ST1x_HALF_CPINT
+#define 	IRQ_ST1x_CFG_CPINT_CODE	 MD_IRQID_ST1x_CFG_CPINT
+#define 	IRQ_ST1x_WAKEUP_IRQ_CODE	 MD_IRQID_ST1x_WAKEUP_IRQ
+#define 	IRQ_STDO_CPINT_CODE	 MD_IRQID_STDO_CPINT
+#define 	IRQ_STDO_HALF_CPINT_CODE	 MD_IRQID_STDO_HALF_CPINT
+#define 	IRQ_STDO_CFG_CPINT_CODE	 MD_IRQID_STDO_CFG_CPINT
+#define 	IRQ_STDO_WAKEUP_IRQ_CODE	 MD_IRQID_STDO_WAKEUP_IRQ
+#define 	IRQ_FREQM_IRQ_CODE	 MD_IRQID_FREQM_IRQ
+#define 	IRQ_SPM2MD_DVFS_MDPERISYS_CODE	 MD_IRQID_SPM2MD_DVFS_MDPERISYS
+#define 	IRQ_TXDFE_BB_IRQ_CODE	 MD_IRQID_TXDFE_BB_IRQ
+#define 	IRQ_PCC_TOP_FULL_IRQ_CODE	 MD_IRQID_PCC_TOP_FULL_IRQ
+#define 	IRQ_GPTM1_CODE	 MD_IRQID_GPTM1
+#define 	IRQ_GPTM2_CODE	 MD_IRQID_GPTM2
+#define 	IRQ_GPTM3_CODE	 MD_IRQID_GPTM3
+#define 	IRQ_GPTM4_CODE	 MD_IRQID_GPTM4
+#define 	IRQ_GPTM5_CODE	 MD_IRQID_GPTM5
+#define 	IRQ_GPTM6_CODE	 MD_IRQID_GPTM6
+#define 	IRQ_GPTM7_CODE	 MD_IRQID_GPTM7
+#define 	IRQ_GPTM8_CODE	 MD_IRQID_GPTM8
+#define 	IRQ_GPTM9_CODE	 MD_IRQID_GPTM9
+#define 	IRQ_GPTM10_CODE	 MD_IRQID_GPTM10
+#define 	IRQ_GPTM11_CODE	 MD_IRQID_GPTM11
+#define 	IRQ_BUSMPU_IRQ_CODE	 MD_IRQID_BUSMPU_IRQ
+#define 	IRQ_SW_LISR1_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_0
+#define 	IRQ_SW_LISR2_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_1
+#define 	IRQ_SW_LISR3_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_2
+#define 	IRQ_SW_LISR4_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_3
+#define 	IRQ_SW_LISR5_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_4
+#define 	IRQ_SW_LISR6_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_5
+#define 	IRQ_SW_LISR7_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_6
+#define 	IRQ_SW_LISR8_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_7
+#define 	IRQ_SW_LISR9_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_8
+#define 	IRQ_SW_LISR10_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_9
+#define 	IRQ_SW_LISR11_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_10
+#define 	IRQ_SW_LISR12_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_11
+#define 	IRQ_SW_LISR13_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_12
+#define 	IRQ_SW_LISR14_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_13
+#define 	IRQ_SW_LISR15_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_14
+#define 	IRQ_SW_LISR16_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_15
+#define 	IRQ_SW_LISR17_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_16
+#define 	IRQ_SW_LISR18_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_17
+#define 	IRQ_SW_LISR19_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_18
+#define 	IRQ_SW_LISR20_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_19
+#define 	IRQ_SW_LISR21_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_20
+#define 	IRQ_SW_LISR22_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_21
+#define 	IRQ_SW_LISR23_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_22
+#define 	IRQ_SW_LISR24_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_23
+#define 	IRQ_SW_LISR25_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_24
+#define 	IRQ_SW_LISR26_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_25
+#define 	IRQ_SW_LISR27_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_26
+#define 	IRQ_SW_LISR28_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_27
+#define 	IRQ_SW_LISR29_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_28
+#define 	IRQ_SW_LISR30_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_29
+#define 	IRQ_SW_LISR31_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_30
+#define 	IRQ_SW_LISR32_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_31
+#define 	IRQ_SW_LISR33_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_32
+#define 	IRQ_SW_LISR34_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_33
+#define 	IRQ_SW_LISR35_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_34
+#define 	IRQ_SW_LISR36_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_35
+#define 	IRQ_SW_LISR37_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_36
+#define 	IRQ_SW_LISR38_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_37
+#define 	IRQ_SW_LISR39_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_38
+#define 	IRQ_SW_LISR40_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_39
+#define 	IRQ_SW_LISR41_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_40
+#define 	IRQ_SW_LISR42_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_41
+#define 	IRQ_SW_LISR43_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_42
+#define 	IRQ_SW_LISR44_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_43
+#define 	IRQ_SW_LISR45_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_44
+#define 	IRQ_SW_LISR46_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_45
+#define 	IRQ_SW_LISR47_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_46
+#define 	IRQ_SW_LISR48_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_47
+#define 	IRQ_SW_LISR49_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_48
+#define 	IRQ_SW_LISR50_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_49
+#define 	IRQ_SW_LISR51_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_50
+#define 	IRQ_SW_LISR52_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_51
+#define 	IRQ_SW_LISR53_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_52
+#define 	IRQ_SW_LISR54_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_53
+#define 	IRQ_SW_LISR55_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_54
+#define 	IRQ_SW_LISR56_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_55
+#define 	IRQ_SW_LISR57_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_56
+#define 	IRQ_SW_LISR58_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_57
+#define 	IRQ_SW_LISR59_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_58
+#define 	IRQ_SW_LISR60_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_59
+#define 	IRQ_SW_LISR61_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_60
+#define 	IRQ_SW_LISR62_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_61
+#define 	IRQ_SW_LISR63_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_62
+#define 	IRQ_SW_LISR64_CODE	 MD_IRQID_SW_TRIGGER_RESERVED_63
+#define     MCU_BUS_DECERR_CODE  MD_IRQID_MCU_BUS_DECERR
+#define     GIC0_FDCInt_CODE  MD_IRQID_GIC0_FDCInt
+#define     GIC0_FDCInt_1_CODE  MD_IRQID_GIC0_FDCInt_1
+#define     GIC0_PCInt_CODE  MD_IRQID_GIC0_PCInt
+#define     GIC0_PCInt_1_CODE  MD_IRQID_GIC0_PCInt_1
+#define     GIC0_TimerInt_CODE  MD_IRQID_GIC0_TimerInt
+#define     GIC0_TimerInt_1_CODE  MD_IRQID_GIC0_TimerInt_1
+#define     GIC1_FDCInt_CODE  MD_IRQID_GIC1_FDCInt
+#define     GIC1_FDCInt_1_CODE  MD_IRQID_GIC1_FDCInt_1
+#define     GIC1_PCInt_CODE  MD_IRQID_GIC1_PCInt
+#define     GIC1_PCInt_1_CODE  MD_IRQID_GIC1_PCInt_1
+#define     GIC1_TimerInt_CODE  MD_IRQID_GIC1_TimerInt
+#define     GIC1_TimerInt_1_CODE  MD_IRQID_GIC1_TimerInt_1
+#define     IRQ_EINT3_CODE  MD_IRQID_EINT3
+#define     MCUMMU_INT_CODE  MD_IRQID_MCUMMU_INT
+#define     SPRAM_DECERR_CODE  MD_IRQID_IA_DECERR
+#define     RMPU_CTIREIGIN_CODE  MD_IRQID_RMPU_CTIREIGIN
+#define     MDSM_CORE_PWR_CTRL_CODE  MD_IRQID_MDSM_CORE_PWR_CTRL
+#define     AP2MD_MSDC0_CODE  MD_IRQID_AP2MD_MSDC0
+
+
+
+/*
+ * Define IRQ selection register assignment
+ */
+#define IRQSel()
+//#define INVALID_ISR_ID           (0xFF)
+
+#define INTERRUPT_PRIORITY_LIST \
+/*  0 ~  7 */  69, 127,  67,  68,  66,  38,  32,  61, \
+/*  8 ~ 15 */  88,  78, 127, 127, 127, 127, 127, 127, \
+/* 16 ~ 23 */ 127, 110,  42, 127, 127, 127, 127, 127, \
+/* 24 ~ 31 */ 127, 127,  64, 127, 127, 123, 124, 122, \
+/* 32 ~ 39 */ 127,   6,   7, 127,   6, 127, 127, 127, \
+/* 40 ~ 47 */ 127,  71,  41,  39,  62,  45, 127, 127, \
+/* 48 ~ 55 */ 127, 127, 127, 127, 127, 127, 117, 118, \
+/* 56 ~ 63 */ 119, 120, 126, 127,   6,   6,   6,   6, \
+/* 64 ~ 71 */ 110, 110, 127, 127, 127, 127, 127, 127, \
+/* 72 ~ 79 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/* 80 ~ 87 */  45, 127, 127, 127,  56,  54, 127, 115, \
+/* 88 ~ 95 */  58,  36,  55,  33,  86,   6,   6,  51, \
+/* 96 ~103 */  40,  47,  30, 127,  46,  43,  43,  43, \
+/*104 ~111 */  46,  44,  28,  86,  27,  34,  35, 110, \
+/*112 ~119 */  31,  49,  26,  64,  25, 127, 127,  59, \
+/*120 ~127 */ 110,  58,  29,  59,  59,  58,  29,  90, \
+/*128 ~135 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*136 ~143 */  70,  77,  44, 127, 127, 127, 127, 127, \
+/*144 ~151 */ 110, 127, 110,   7,   7,  76,  71,  77, \
+/*152 ~159 */  50,  51,  52,  79,  76,  77,  39,  72, \
+/*160 ~167 */  74,  75,  48, 127, 127,  63,   8, 127, \
+/*168 ~175 */ 110, 127, 110, 110,   6, 127, 127, 127, \
+/*176 ~183 */  75,  75, 127, 127,   7, 111,   7, 111, \
+/*184 ~191 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*192 ~199 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*200 ~207 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*208 ~215 */ 127, 110, 127, 110, 127, 110, 127, 110, \
+/*216 ~223 */ 127, 110, 127, 110, 127, 127, 127,   6, \
+/*224 ~231 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*232 ~239 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*240 ~247 */ 127, 127, 127, 127, 127, 127, 127, 127, \
+/*248 ~255 */ 127, 127, 127, 127, 127, 127, 127, 127,
+
+#if defined(__ESL_MASE__)
+
+/* for OS ICC
+   IRQ_SW_LISR1_CODE
+   IRQ_SW_LISR2_CODE
+   IRQ_SW_LISR3_CODE
+   IRQ_SW_LISR4_CODE
+*/
+#define INTERRUPT_GROUP_LIST \
+	/*	0 ~  7 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*	8 ~ 15 */  0,  0,  0,  1,  0,  0,  0,  0, \
+	/* 16 ~ 23 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 24 ~ 31 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 32 ~ 39 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 40 ~ 47 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 48 ~ 55 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 56 ~ 63 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 64 ~ 71 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 72 ~ 79 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 80 ~ 87 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 88 ~ 95 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 96 ~103 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*104 ~111 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*112 ~119 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*120 ~127 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*128 ~135 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*136 ~143 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*144 ~151 */  1,  2,  3,  0,  0,  0,  0,  0, \
+	/*152 ~159 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*160 ~167 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*168 ~175 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*176 ~183 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*184 ~191 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*192 ~199 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*200 ~207 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*208 ~215 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*216 ~223 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*224 ~231 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*232 ~239 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*240 ~247 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*248 ~255 */  0,  0,  0,  0,  0,  0,  0,  0
+#else  /* __ESL_MASE__*/ 
+#define INTERRUPT_GROUP_LIST \
+	/*  0 ~  7 */  1,  4,  1,  1,  1,  1,  1,  0, \
+	/*  8 ~ 15 */  1,  1, 17,  4,  4,  0,  4,  4, \
+	/* 16 ~ 23 */  4,  1,  1,  4,  4,  4,  4,  4, \
+	/* 24 ~ 31 */  4,  4,  1,  4,  4,  4,  4,  4, \
+	/* 32 ~ 39 */  0,  5,  0,  4,  5,  4,  4,  4, \
+	/* 40 ~ 47 */  4,  0,  1,  1,  1,  3,  4,  4, \
+	/* 48 ~ 55 */  4,  4,  0,  0,  4,  4,  4,  4, \
+	/* 56 ~ 63 */  4,  4,  4,  4,  5,  5,  5,  5, \
+	/* 64 ~ 71 */  1,  3,  0,  4,  4,  4,  4,  4, \
+	/* 72 ~ 79 */  4,  4,  4,  4,  4,  5,  4,  4, \
+	/* 80 ~ 87 */  3,  4,  4,  0,  1,  1,  4,  4, \
+	/* 88 ~ 95 */  1,  1,  1,  1,  1,  5,  5,  3, \
+	/* 96 ~103 */  1,  3,  1,  4,  3,  1,  1,  1, \
+	/*104 ~111 */  3,  3,  3,  0,  1,  1,  1,  1, \
+	/*112 ~119 */  1,  3,  1,  1,  0,  4,  4,  1, \
+	/*120 ~127 */  1,  1,  1,  1,  1,  1,  1,  0, \
+	/*128 ~135 */  4,  4,  0,  4,  4,  4,  4,  4, \
+	/*136 ~143 */  1,  1,  3,  4,  4,  4,  4,  0, \
+	/*144 ~151 */  1,  2,  3,  0,  2,  1,  1,  1, \
+	/*152 ~159 */  3,  1,  3,  1,  1,  1,  1,  1, \
+	/*160 ~167 */  1,  1,  6,  5,  4,  1,  0,  0, \
+	/*168 ~175 */  1,  2,  3,  1,  5, 16,  0,  2, \
+	/*176 ~183 */  1,  1,  0,  2,  0,  1,  2,  3, \
+	/*184 ~191 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*192 ~199 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*200 ~207 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*208 ~215 */  0,  1,  0,  1,  0,  1,  2,  3, \
+	/*216 ~223 */  2,  3,  2,  3,  4,  4,  4,  4, \
+	/*224 ~231 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*232 ~239 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*240 ~247 */  4,  4,  4,  4,  4,  4,  4,  4, \
+	/*248 ~255 */  4,  4,  4,  4,  4,  4,  4,  4
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+	/* Group0(0) */                0xE, \
+	/* Group1(1) */                0xD, \
+	/* Group2(2) */                0xB, \
+	/* Group3(3) */                0x7, \
+	/* Group4(0,2) */              0xA, \
+	/* Group5(0,1,2,3) */          0x0, \
+	/* Group6(1,3) */              0x5, \
+	/* Group7 */                   0xF, \
+	/* Group8 */                   0xF, \
+	/* Group9 */                   0xF, \
+	/* Group10 */                  0xF, \
+	/* Group11 */                  0xF, \
+	/* Group12 */                  0xF, \
+	/* Group13 */                  0xF, \
+	/* Group14*/                   0xF, \
+	/* Group15 */                  0xF,
+#endif
+
+#define NMI_GROUP_M2V_LIST \
+	/* Group0(exception usage) */  0xF, \
+	/* Group1 */                   0x0,
+
+#if defined(__MDCIRQ_WAIT_MODE_ENABLE__)
+#define INTERRUPT_BROADCAST_TYPE \
+	/*  0-31 */                0x040627FD, \
+	/* 32-63 */                0xF00C3E17, \
+	/* 64-95 */                0xFF392007, \
+	/* 96-127 */               0xFF9FFFF7, \
+	/* 128-159 */              0xFFFF8704, \
+	/* 160-191 */              0x00FFDFFF, \
+	/* 192-223 */              0x0FFF0000, \
+	/* 224-255 */              0x00000000,
+#else
+#define INTERRUPT_BROADCAST_TYPE \
+	/*  0-31 */                0x00000400, \
+	/* 32-63 */                0xF0000012, \
+	/* 64-95 */                0x60002000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x0000101C, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000,
+#endif
+
+#define INTERRUPT_TYPE \
+	/*  0-31 */                0x00000400, \
+	/* 32-63 */                0x00000000, \
+	/* 64-95 */                0x00000000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x00002000, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000,
+
+#define INTERRUPT_HRT_MT \
+	/*  0-31 */                0x00000000, \
+	/* 32-63 */                0x00000000, \
+	/* 64-95 */                0x00000000, \
+	/* 96-127 */               0x00000000, \
+	/* 128-159 */              0x00000000, \
+	/* 160-191 */              0x00000000, \
+	/* 192-223 */              0x00000000, \
+	/* 224-255 */              0x00000000,
+
+
+#define INTERRUPT_TIMING_THRESHOLD \
+	/*	VPE0 */  0xFFFFFFFF,\
+	/*	VPE1 */  0xFFFFFFFF,\
+	/*	VPE2 */  0xFFFFFFFF,\
+	/*	VPE3 */  0xFFFFFFFF,
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+//#define EINT_TOTAL_CHANNEL 16
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+    VPE_STATUS_DORMANT           = 0,
+    VPE_STATUS_LISR_HIGHEST      = 1,
+    VPE_STATUS_LISR_LOWEST       = 127,
+    VPE_STATUS_HISR_TASK_HIGHEST = 128,
+    VPE_STATUS_HISR_TASK_LOWEST  = 386, 
+    VPE_STATUS_END               = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+    IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+    IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+    IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+    IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+    IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+    IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+    IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+    IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+    IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+    IRQ_MDWDT = IRQ_MDWDT_CODE,
+    IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+    IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+    IRQ_OST = IRQ_OST_CODE,
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+    IRQ_USIM1 = IRQ_USIM1_CODE,
+    IRQ_TOPSM = IRQ_TOPSM_CODE,
+    IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+    IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+    IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+    IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+    IRQ_EINT0 = IRQ_EINT0_CODE,
+    IRQ_EINT1 = IRQ_EINT1_CODE,
+    IRQ_EINT2 = IRQ_EINT2_CODE,
+    IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+    IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+    IRQ_TXBRP0 = IRQ_TXBRP0_CODE,
+    IRQ_TXBRP1 = IRQ_TXBRP1_CODE,
+    IRQ_TXCRP = IRQ_TXCRP_CODE,
+    IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+    IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+    IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+    IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+    IRQ_ECT = IRQ_ECT_CODE,
+    IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+    IRQ_CLDMA = IRQ_CLDMA_CODE,
+    IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+    IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+    IRQ_SOE = IRQ_SOE_CODE,
+    IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+    IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+    IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+    IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+    IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+    IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+    IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+    IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+    IRQ_AP2MD_CCIF2_0 = IRQ_AP2MD_CCIF2_0_CODE,
+    IRQ_USIP3_1 = IRQ_USIP3_1_CODE,
+    IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+    IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+    IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+    IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+    IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+    IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+    IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+    IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+    IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+    IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+    IRQ_PTP_SLPCTL_EVENT = IRQ_PTP_SLPCTL_EVENT_CODE,
+    IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+    IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+    IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+    IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+    IRQ_MDCIRQ_WDT0 = IRQ_MDCIRQ_WDT0_CODE,
+    IRQ_MDCIRQ_WDT1 = IRQ_MDCIRQ_WDT1_CODE,
+    IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+    IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+    IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+    IRQ_DCXO_RDY_WO_ACK_IRQ = IRQ_DCXO_RDY_WO_ACK_IRQ_CODE,
+    IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+    IRQ_TOP_PLL_DSNS_IRQ = IRQ_TOP_PLL_DSNS_IRQ_CODE,
+    IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+    IRQ_SSUSB_USB_MCU = IRQ_SSUSB_USB_MCU_CODE,
+    IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+    IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+    IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+    IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+    IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+    IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+    IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+    IRQ_BR_DMA_IRQ = IRQ_BR_DMA_IRQ_CODE,
+    IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+    IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+    IRQ_MDRTT = IRQ_MDRTT_CODE,
+    IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+    IRQ_MDM2C_U3G = IRQ_MDM2C_U3G_CODE,
+    IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+    IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+    IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+    IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+    IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+    IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+    IRQ_MDL1_TOPSM_IRQ = IRQ_MDL1_TOPSM_IRQ_CODE,
+    IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+    IRQ_RTR_FRAME_IRQ = IRQ_RTR_FRAME_IRQ_CODE,
+    IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+    IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+    IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+    IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+    IRQ_MD_DVFS_CTRL_IRQ = IRQ_MD_DVFS_CTRL_IRQ_CODE,
+    IRQ_BSI_MM_I_IRQ_RFIC = IRQ_BSI_MM_I_IRQ_RFIC_CODE,
+    IRQ_BSI_MM_I_IRQ_MIPI = IRQ_BSI_MM_I_IRQ_MIPI_CODE,
+    IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+    IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+    IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+    IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+    IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+    IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+    IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+    IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+    IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+    IRQ_SPM2MD_DVFS_MDPERISYS = IRQ_SPM2MD_DVFS_MDPERISYS_CODE,
+    IRQ_TXDFE_BB_IRQ = IRQ_TXDFE_BB_IRQ_CODE,
+    IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+    IRQ_GPTM1 = IRQ_GPTM1_CODE,
+    IRQ_GPTM2 = IRQ_GPTM2_CODE,
+    IRQ_GPTM3 = IRQ_GPTM3_CODE,
+    IRQ_GPTM4 = IRQ_GPTM4_CODE,
+    IRQ_GPTM5 = IRQ_GPTM5_CODE,
+    IRQ_GPTM6 = IRQ_GPTM6_CODE,
+    IRQ_GPTM7 = IRQ_GPTM7_CODE,
+    IRQ_GPTM8 = IRQ_GPTM8_CODE,
+    IRQ_GPTM9 = IRQ_GPTM9_CODE,
+    IRQ_GPTM10 = IRQ_GPTM10_CODE,
+    IRQ_GPTM11 = IRQ_GPTM11_CODE,
+    IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+    IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+    IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+    IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+    IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+    IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+    IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+    IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+    IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+    IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+    IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+    IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+    IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+    IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+    IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+    IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+    IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+    IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+    IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+    IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+    IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+    IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+    IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+    IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+    IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+    IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+    IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+    IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+    IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+    IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+    IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+    IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+    IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+    IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+    IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+    IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+    IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+    IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+    IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+    IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+    IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+    IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+    IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+    IRQ_SW_LISR43 = IRQ_SW_LISR43_CODE,
+    IRQ_SW_LISR44 = IRQ_SW_LISR44_CODE,
+    IRQ_SW_LISR45 = IRQ_SW_LISR45_CODE,
+    IRQ_SW_LISR46 = IRQ_SW_LISR46_CODE,
+    IRQ_SW_LISR47 = IRQ_SW_LISR47_CODE,
+    IRQ_SW_LISR48 = IRQ_SW_LISR48_CODE,
+    IRQ_SW_LISR49 = IRQ_SW_LISR49_CODE,
+    IRQ_SW_LISR50 = IRQ_SW_LISR50_CODE,
+    IRQ_SW_LISR51 = IRQ_SW_LISR51_CODE,
+    IRQ_SW_LISR52 = IRQ_SW_LISR52_CODE,
+    IRQ_SW_LISR53 = IRQ_SW_LISR53_CODE,
+    IRQ_SW_LISR54 = IRQ_SW_LISR54_CODE,
+    IRQ_SW_LISR55 = IRQ_SW_LISR55_CODE,
+    IRQ_SW_LISR56 = IRQ_SW_LISR56_CODE,
+    IRQ_SW_LISR57 = IRQ_SW_LISR57_CODE,
+    IRQ_SW_LISR58 = IRQ_SW_LISR58_CODE,
+    IRQ_SW_LISR59 = IRQ_SW_LISR59_CODE,
+    IRQ_SW_LISR60 = IRQ_SW_LISR60_CODE,
+    IRQ_SW_LISR61 = IRQ_SW_LISR61_CODE,
+    IRQ_SW_LISR62 = IRQ_SW_LISR62_CODE,
+    IRQ_SW_LISR63 = IRQ_SW_LISR63_CODE,
+    IRQ_SW_LISR64 = IRQ_SW_LISR64_CODE,
+    MCU_BUS_DECERR = MCU_BUS_DECERR_CODE,
+    GIC0_FDCInt = GIC0_FDCInt_CODE,
+    GIC0_FDCInt_1 = GIC0_FDCInt_1_CODE,
+    GIC0_PCInt = GIC0_PCInt_CODE,
+    GIC0_PCInt_1 = GIC0_PCInt_1_CODE,
+    GIC0_TimerInt = GIC0_TimerInt_CODE,
+    GIC0_TimerInt_1 = GIC0_TimerInt_1_CODE,
+    GIC1_FDCInt = GIC1_FDCInt_CODE,
+    GIC1_FDCInt_1 = GIC1_FDCInt_1_CODE,
+    GIC1_PCInt = GIC1_PCInt_CODE,
+    GIC1_PCInt_1 = GIC1_PCInt_1_CODE,
+    GIC1_TimerInt = GIC1_TimerInt_CODE,
+    GIC1_TimerInt_1 = GIC1_TimerInt_1_CODE,
+    IRQ_EINT3 = IRQ_EINT3_CODE,
+    MCUMMU_INT = MCUMMU_INT_CODE,
+    SPRAM_DECERR = SPRAM_DECERR_CODE,
+    RMPU_CTIREIGIN = RMPU_CTIREIGIN_CODE,
+    MDSM_CORE_PWR_CTRL = MDSM_CORE_PWR_CTRL_CODE,
+    AP2MD_MSDC0 = AP2MD_MSDC0_CODE 
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+    GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+
+#endif /* end of __INTRCTRL_MT6771_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6771_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6771_SW_Handle.h
new file mode 100644
index 0000000..7acf2d4
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_MT6771_SW_Handle.h
@@ -0,0 +1,290 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6771_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   MT6771
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 10 2017 yen-chun.liu
+ * [MOLY00270029] [System Service][KAL] Gen93 dummy LISR APIs
+ * dummy LISR driver.
+ *
+ * 08 03 2017 yen-chun.liu
+ * [MOLY00267971] [SWLA] New Snapshot API for Robust Modem Feature
+ * 2 new SW interrupt for SWLA.
+ *
+ * 06 13 2017 yen-chun.liu
+ * [MOLY00244660] [MT6739][Gen93][System Service][MDCIRQ] Compile option for ZION(MT6739)
+ * .
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE1 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE2 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE3 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE4 = HC Yang (Cannot be modified due to OSIPI optimized to assembly)
+      SW_TRIGGER_CODE5 = HC Yang
+      SW_TRIGGER_CODE6 = HC Yang
+      SW_TRIGGER_CODE7 = Max Weng
+      SW_TRIGGER_CODE8 = Max Weng
+      SW_TRIGGER_CODE9 = Max Weng
+      SW_TRIGGER_CODE10 = Max Weng
+      SW_TRIGGER_CODE11 = Max Weng
+      SW_TRIGGER_CODE12 = Max Weng
+      SW_TRIGGER_CODE13 = Zengling Jin
+      SW_TRIGGER_CODE14 = Zengling Jin
+      SW_TRIGGER_CODE15 = Zengling Jin
+      SW_TRIGGER_CODE16 = Chuansheng Zhang
+      SW_TRIGGER_CODE17 = Chuansheng Zhang
+      SW_TRIGGER_CODE18 = Chuansheng Zhang
+      SW_TRIGGER_CODE19 = Chuansheng Zhang
+      SW_TRIGGER_CODE20 = Huei-Ya Chang
+      SW_TRIGGER_CODE21 = Qmei Yang
+      SW_TRIGGER_CODE22 = Tee-Yuen Chun
+      SW_TRIGGER_CODE23 = Yuni Chang
+      SW_TRIGGER_CODE24 = SY Yeh
+      SW_TRIGGER_CODE25 = Owen Ho
+      SW_TRIGGER_CODE26 = Owen Ho
+      SW_TRIGGER_CODE27 = Owen Ho
+      SW_TRIGGER_CODE28 = Owen Ho
+      SW_TRIGGER_CODE29 = Carl Kao
+      SW_TRIGGER_CODE30 = Wade Huang
+      SW_TRIGGER_CODE31 = Woody kuo
+      SW_TRIGGER_CODE32 = Jun-Ying Huang
+      SW_TRIGGER_CODE33 = Jun-Ying Huang
+      SW_TRIGGER_CODE34 = Weimin Zeng
+      SW_TRIGGER_CODE35 = Weimin Zeng
+      SW_TRIGGER_CODE36 = HW Jheng
+      SW_TRIGGER_CODE37 = HW Jheng
+      SW_TRIGGER_CODE38 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE39 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE40 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE41 = Ian-GF Huang (Cannot be modified due to activate dummy LISR driver code)
+      SW_TRIGGER_CODE42 = 
+      SW_TRIGGER_CODE43 = 
+      SW_TRIGGER_CODE44 = 
+      SW_TRIGGER_CODE45 = 
+      SW_TRIGGER_CODE46 = 
+      SW_TRIGGER_CODE47 = 
+      SW_TRIGGER_CODE48 = 
+      SW_TRIGGER_CODE49 = 
+      SW_TRIGGER_CODE50 = 
+      SW_TRIGGER_CODE51 = 
+      SW_TRIGGER_CODE52 = 
+      SW_TRIGGER_CODE53 = 
+      SW_TRIGGER_CODE54 = 
+      SW_TRIGGER_CODE55 = 
+      SW_TRIGGER_CODE56 = 
+      SW_TRIGGER_CODE57 = 
+      SW_TRIGGER_CODE58 = 
+      SW_TRIGGER_CODE59 = 
+      SW_TRIGGER_CODE60 = 
+      SW_TRIGGER_CODE61 = 
+      SW_TRIGGER_CODE62 = 
+      SW_TRIGGER_CODE63 = 
+      SW_TRIGGER_CODE64 = 
+  */
+#if (defined(__MIPS_IA__))
+
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
+
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6771 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_SW_Handle.h
new file mode 100644
index 0000000..023efdd
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/intrCtrl_SW_Handle.h
@@ -0,0 +1,212 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *   This file include the each BB chip software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/* Include Chip SW handler */
+
+#if defined(MT6763)
+   #include "intrCtrl_MT6763_SW_Handle.h"
+#endif
+
+#if defined(MT6739)
+   #include "intrCtrl_MT6739_SW_Handle.h"
+#endif
+
+#if defined(MT6771)
+   #include "intrCtrl_MT6771_SW_Handle.h"
+#endif
+
+#if defined(MT6765)
+   #include "intrCtrl_MT6765_SW_Handle.h"
+#endif
+
+#if defined(MT6761)
+   #include "intrCtrl_MT6761_SW_Handle.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/cirq/md93/irqid.h b/mcu/interface/driver/devdrv/cirq/md93/irqid.h
new file mode 100644
index 0000000..5213110
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/irqid.h
@@ -0,0 +1,23 @@
+#ifndef __IRQID_H__
+#define __IRQID_H__
+
+#if defined(MT6763)
+   #include "irqid_MT6763.h"
+#endif
+
+#if defined(MT6739)
+   #include "irqid_MT6739.h"
+#endif
+
+#if defined(MT6771)
+   #include "irqid_MT6771.h"
+#endif
+
+#if defined(MT6765)
+   #include "irqid_MT6765.h"
+#endif
+
+#if defined(MT6761)
+   #include "irqid_MT6761.h"
+#endif
+#endif /*end of __IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md93/irqid_ELBRUS.h b/mcu/interface/driver/devdrv/cirq/md93/irqid_ELBRUS.h
new file mode 100644
index 0000000..30fe5cb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/irqid_ELBRUS.h
@@ -0,0 +1,365 @@
+#ifndef __ELBRUS_IRQID_H__
+#define __ELBRUS_IRQID_H__
+
+
+//ELBURS MDCIRQ IRQID base on 0907
+#define MD_IRQID_OST          	0
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS	1
+#define MD_IRQID_LMAC_RAR     	2
+#define MD_IRQID_LMAC_EAR     	3
+#define MD_IRQID_MDWDT        	4
+//#define MD_IRQID_NFI          	5
+#define MD_IRQID_SW_TRIGGER_RESERVED_24	5
+#define MD_IRQID_L2COPRO      	6
+#define MD_IRQID_GPTM1        	7
+#define MD_IRQID_GPTM2        	8
+#define MD_IRQID_GPTM3        	9
+#define MD_IRQID_GPTM4        	10
+#define MD_IRQID_GPTM5       	11
+#define MD_IRQID_GPTM6       	12
+#define MD_IRQID_UART_MD0    	13
+#define MD_IRQID_UART_MD1    	14
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS	15
+#define MD_IRQID_I2C_0       	16
+#define MD_IRQID_USIM0       	17
+#define MD_IRQID_USIM1       	18
+#define MD_IRQID_UART_MD2    	19
+#define MD_IRQID_MDGDMA0     	20
+#define MD_IRQID_MDGDMA1     	21
+#define MD_IRQID_MDGDMA2     	22
+#define MD_IRQID_MDGDMA3     	23
+#define MD_IRQID_EINT0       	24
+#define MD_IRQID_EINT1       	25
+#define MD_IRQID_EINT2       	26
+#define MD_IRQID_EINT3       	27
+#define MD_IRQID_EINT_SHARE  	28
+#define MD_IRQID_BUS_ERR     	29
+#define MD_IRQID_TOPSM       	30
+#define MD_IRQID_DEM_TRIG_PS_INT_LE	31
+#define MD_IRQID_C2K_ST_SLOT_INT	32
+#define MD_IRQID_C2K_ST_HALF_SLOT_INT	33
+#define MD_IRQID_C2K_MPDU_INT	34
+#define MD_IRQID_C2K_M2C_DAT_WRDY_INT	35
+#define MD_IRQID_C2K_M2C_CTL_WRDY_INT	36
+#define MD_IRQID_C2K_M2C_FST_WRDY_INT	37
+#define MD_IRQID_C2K_NIRQ	38
+#define MD_IRQID_SW_TRIGGER_RESERVED_25	41
+//#define MD_IRQID_PMU          	42
+#define MD_IRQID_SW_TRIGGER_RESERVED_26	42
+#define MD_IRQID_ECT          	43
+//#define MD_IRQID_PS_L1_WDT_INT    	44
+#define MD_IRQID_SW_TRIGGER_RESERVED_27	44
+#define MD_IRQID_PTP_THERM_INT_INT	45
+#define MD_IRQID_CLDMA        	46
+#define MD_IRQID_MDINFRA_ABM_INT	47
+#define MD_IRQID_MDLITE_GPTM_INT	48
+#define MD_IRQID_AP2MD_PCCIF_IRQ	49
+#define MD_IRQID_PCCIF_AP_MD	50
+#define MD_IRQID_CCIF2_MD_IRQ	51
+#define MD_IRQID_CCIF2_MD_EVENT	52
+//#define MD_IRQID_SPI         	53
+#define MD_IRQID_SW_TRIGGER_RESERVED_28	53
+#define MD_IRQID_MDINFRA_ABM_ERROR_INT	54
+#define MD_IRQID_USB3        	55
+//#define MD_IRQID_SDIO        	56
+#define MD_IRQID_SW_TRIGGER_RESERVED_29	56
+#define MD_IRQID_MSDC0       	57
+#define MD_IRQID_EHPI0       	58
+//#define MD_IRQID_RTC         	59
+#define MD_IRQID_SW_TRIGGER_RESERVED_30	59
+//#define MD_IRQID_SOE         	60
+#define MD_IRQID_SW_TRIGGER_RESERVED_31	60
+#define MD_IRQID_MSDC1       	61
+//#define MD_IRQID_PFC_INT_LV  	62
+#define MD_IRQID_SW_TRIGGER_RESERVED_32	62
+//#define MD_IRQID_AUXACD      	63
+#define MD_IRQID_SW_TRIGGER_RESERVED_33	63
+//#define MD_IRQID_LED         	64
+#define MD_IRQID_SW_TRIGGER_RESERVED_34	64
+#define MD_IRQID_BT_CVSD       	65
+#define MD_IRQID_ELMTOP_IOCU_IRQ	66
+#define MD_IRQID_ELMTOP_EMI_IRQ	67
+#define MD_IRQID_ULS_INTR	68
+#define MD_IRQID_SHARE_D12MINT1	69
+#define MD_IRQID_SHARE_D12MINT2           	70
+#define MD_IRQID_SHARE_D12MINT3           	71
+//#define MD_IRQID_LTE_TIMER_EMAC_SF_TICK   	72
+#define MD_IRQID_SW_TRIGGER_RESERVED_35	72
+#define MD_IRQID_IRDBG_MCU_INT	73
+#define MD_IRQID_LTE_MODEMSYS_TRACE_IRQ	74
+#define MD_IRQID_SI_CM_ERR	75
+#define MD_IRQ_ID_L1SYS_SLV_DECERR_IRQ_LEVEL	76
+#define MD_IRQID_ABM_INT	77
+#define MD_IRQID_ABM_ERROR_INT	78
+#define MD_IRQID_MO_WERR_INT	79
+#define MD_IRQID_BC_IRQ	80
+#define MD_IRQID_UEA_UIA_IRQ	81
+#define MD_IRQID_UPA_ACC_IRQ	82
+#define MD_IRQID_DPA_ACC_IRQ	83
+#define MD_IRQID_C2K_MD_INT_0	84
+#define MD_IRQID_C2K_MD_INT_1	85
+#define MD_IRQID_C2K_MD_INT_2	86
+#define MD_IRQID_C2K_MD_INT_3	87
+#define MD_IRQID_C2K_L1_INT_0	88
+#define MD_IRQID_C2K_L1_INT_1	89
+#define MD_IRQID_C2K_L1_INT_2	90
+#define MD_IRQID_C2K_L1_INT_3	91
+#define MD_IRQID_C2K_L1_INT_4	92
+#define MD_IRQID_C2K_L1_INT_5	93
+#define MD_IRQID_C2K_L1_INT_6	94
+#define MD_IRQID_C2K_L1_INT_7	95
+#define MD_IRQID_PB0_PM_CNTRSAT_INT_0	96
+#define MD_IRQID_PB0_PM_CNTRSAT_INT_1	97
+#define MD_IRQID_PB1_PM_CNTRSAT_INT_0	98
+#define MD_IRQID_PB1_PM_CNTRSAT_INT_1	99
+#define MD_IRQID_PB2_PM_CNTRSAT_INT_0	100
+#define MD_IRQID_PB2_PM_CNTRSAT_INT_1	101
+#define MD_IRQID_PB3_PM_CNTRSAT_INT_0	102
+#define MD_IRQID_PB3_PM_CNTRSAT_INT_1	103
+#define MD_IRQID_PTP_FSM_INT	104
+#define MD_IRQID_PTP_SLPCTL_EVENT	105
+#define MD_IRQID_PCCIF_MDMCU0_IRQ	106
+#define MD_IRQID_PCCIF_MDMCU1_IRQ	107
+#define MD_IRQID_ELM_DMA_IRQ	108
+#define MD_IRQID_ELM_L1_IRQ	109
+#define MD_IRQID_MDCIRQ_IRQ_LV	110
+#define MD_IRQID_LOGGDMA_IRQ0_LV	111
+#define MD_IRQID_SOE_INT_LV	112
+#define MD_IRQID_TRACE_INT	113
+#define MD_IRQID_SPM2MD_DVFS_MDPERISYS	114
+#define MD_IRQID_SI_CM_PCINT	115
+#define MD_IRQID_MDMCU_MACRO_BUS_INT	116
+#define MD_IRQID_MDMCU_PERI_BUS_INT	117
+#define MD_IRQID_MM_WERR_INT	118
+#define MD_IRQID_PLL_GEARHP_RDY	119
+#define MD_IRQID_DCXO_RDY_WO_ACK_IRQ	120
+#define MD_IRQID_PLL_REQ_WO_DCXO_IRQ	121
+#define MD_IRQID_TOP_PLL_DSNS_IRQ	122
+#define MD_IRQID_BRP_BRP_CMIF_M2C_IRQ_0	123
+#define MD_IRQID_BRP_BRP_CMIF_M2C_IRQ_1	124
+#define MD_IRQID_BRP_BRP_CMIF_M2C_IRQ_2	125
+#define MD_IRQID_CMP_CMTDB_IRQ	126
+#define MD_IRQID_CS_SRAM_CTRL_IRQ	127
+#define MD_IRQID_CSTXB_FDD_CS_IRQ	128
+#define MD_IRQID_CSTXB_TDD_CS_IRQ	129
+#define MD_IRQID_DFE0_CMIF_M2C_IRQ_0	130
+#define MD_IRQID_DFE0_CMIF_M2C_IRQ_1	131
+#define MD_IRQID_DFE0_CMIF_M2C_IRQ_2	132
+#define MD_IRQID_DFE0_PCC_TOP_0_FULL_IRQ	133
+#define MD_IRQID_DFE0_PCC_TOP_1_FULL_IRQ	134
+#define MD_IRQID_DFE0_RXDFEIF_L_IRQ	135
+#define MD_IRQID_DFE0_TCU_L1D_1_IRQ	136
+#define MD_IRQID_DFE0_TCU_L1D_2_IRQ	137
+#define MD_IRQID_DFE1_CMIF_M2C_IRQ_0	138
+#define MD_IRQID_DFE1_CMIF_M2C_IRQ_1	139
+#define MD_IRQID_DFE1_CMIF_M2C_IRQ_2	140
+#define MD_IRQID_DFE1_PCC_TOP_0_FULL_IRQ	141
+#define MD_IRQID_DFE1_PCC_TOP_1_FULL_IRQ	142
+#define MD_IRQID_DFE1_RXDFEIF_L_IRQ	143
+#define MD_IRQID_GDMA_IRQ	144
+#define MD_IRQID_ICC_DSP_IRQ_0	145
+#define MD_IRQID_ICC_DSP_IRQ_1	146
+#define MD_IRQID_ICC_SRAM_CTRL_IRQ	147
+#define MD_IRQID_IDC_PM_INT	148
+#define MD_IRQID_IDC_UART_IRQ	149
+#define MD_IRQID_IMC_DSP_IRQ_0	150
+#define MD_IRQID_IMC_DSP_IRQ_1	151
+#define MD_IRQID_IMC_MMU_IRQ_0	152
+#define MD_IRQID_IMC_MMU_IRQ_1	153
+#define MD_IRQID_IMC_RXDMP_IRQ	154
+#define MD_IRQID_IMC_RXTDB_IRQ	155
+#define MD_IRQID_IMC_SRAM_CTRL_IRQ	156
+#define MD_IRQID_INR_RAKE_CMIF_M2C_IRQ_0	157
+#define MD_IRQID_INR_RAKE_CMIF_M2C_IRQ_1	158
+#define MD_IRQID_INR_TD1_BRP_DMA_IRQ	159
+#define MD_IRQID_INR_TD1_CSCE_IRQ	160
+#define MD_IRQID_INR_TD1_DFE_BRG_IRQ	161
+#define MD_IRQID_INR_TD1_JDA_IRQ	162
+#define MD_IRQID_INR_TD1_PP_IRQ	163
+#define MD_IRQID_INR_TD2_BRP_DMA_IRQ	164
+#define MD_IRQID_INR_TD2_CSCE_IRQ	165
+#define MD_IRQID_INR_TD2_DFE_BRG_IRQ	166
+#define MD_IRQID_INR_TD2_JDA_IRQ	167
+#define MD_IRQID_TD2_PP_IRQ	168
+#define MD_IRQID_L1_LTE_SLEEP_IRQ	169
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0	170
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1	171
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0	172
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1	173
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2	174
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3	175
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4	176
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5	177
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6	178
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7	179
+#define MD_IRQID_LTEL1_CS_IRQ	180
+#define MD_IRQID_LTXB0_BSI_L_AB_IRQ	181
+#define MD_IRQID_LTXB0_BSI_L_C_IRQ	182
+#define MD_IRQID_LTXB0_BSI_L_D_IRQ	183
+#define MD_IRQID_LTXB0_TXENC_ERROR_IRQ	184
+#define MD_IRQID_LTXB1_BSI_L_AB_IRQ	185
+#define MD_IRQID_LTXB1_BSI_L_C_IRQ	186
+#define MD_IRQID_LTXB1_BSI_L_D_IRQ	187
+#define MD_IRQID_LTXB1_TXENC_ERROR_IRQ	188
+#define MD_IRQID_MMU_SRAM_CTRL_IRQ	189
+#define MD_IRQID_MPC_DSP_IRQ_0	190
+#define MD_IRQID_MPC_DSP_IRQ_1	191
+#define MD_IRQID_MPC_SRAM_CTRL_IRQ	192
+#define MD_IRQID_TDMA_CTIRQ1	193
+#define MD_IRQID_TDMA_CTIRQ2	194
+#define MD_IRQID_TDMA_CTIRQ3	195
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ	196
+#define MD_IRQID_FREQM_IRQ	197
+#define MD_IRQID_MDL1_TOPSM_IRQ	198
+#define MD_IRQID_RTR_FRAME_IRQ	199
+#define MD_IRQID_RTR_SLT_IRQ	200
+#define MD_IRQID_WTIMER_IRQ	201
+#define MD_IRQID_TDD_WAKEUP_IRQ	202
+#define MD_IRQID_TDMA_WAKEUP_IRQ	203
+#define MD_IRQID_MODEML1_DVFS_IRQ	204
+#define MD_IRQID_MODEML1_DVFS_MIPS_DVS_IRQ	205
+#define MD_IRQID_SW_TRIGGER_RESERVED_0	206
+#define MD_IRQID_SW_TRIGGER_RESERVED_1	207
+#define MD_IRQID_SW_TRIGGER_RESERVED_2	208
+#define MD_IRQID_SW_TRIGGER_RESERVED_3	209
+#define MD_IRQID_SW_TRIGGER_RESERVED_4	210
+#define MD_IRQID_SW_TRIGGER_RESERVED_5	211
+#define MD_IRQID_SW_TRIGGER_RESERVED_6	212
+#define MD_IRQID_SW_TRIGGER_RESERVED_7	213
+#define MD_IRQID_SW_TRIGGER_RESERVED_8	214
+#define MD_IRQID_SW_TRIGGER_RESERVED_9	215
+#define MD_IRQID_SW_TRIGGER_RESERVED_10	216
+#define MD_IRQID_SW_TRIGGER_RESERVED_11	217
+#define MD_IRQID_SW_TRIGGER_RESERVED_12	218
+#define MD_IRQID_SW_TRIGGER_RESERVED_13	219
+#define MD_IRQID_SW_TRIGGER_RESERVED_14	220
+#define MD_IRQID_SW_TRIGGER_RESERVED_15	221
+#define MD_IRQID_SW_TRIGGER_RESERVED_16	222
+#define MD_IRQID_SW_TRIGGER_RESERVED_17	223
+#define MD_IRQID_SW_TRIGGER_RESERVED_18	224
+#define MD_IRQID_SW_TRIGGER_RESERVED_19	225
+#define MD_IRQID_SW_TRIGGER_RESERVED_20	226
+#define MD_IRQID_SW_TRIGGER_RESERVED_21	227
+#define MD_IRQID_SW_TRIGGER_RESERVED_22	228
+#define MD_IRQID_SW_TRIGGER_RESERVED_23	229
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_0	230
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_1	231
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_2	232
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_3	233
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_4	234
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_5	235
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_6	236
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_7	237
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_8	238
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_9	239
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_10	240
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_11	241
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_12	242
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_13	243
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_14	244
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_15	245
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_16	246
+#define MD_IRQID_RESERVED_FOR_CC_IRQ_17	247
+#define MD_IRQID_L1_GPTM1	248
+#define MD_IRQID_L1_GPTM2	249
+#define MD_IRQID_L1_GPTM3	250
+#define MD_IRQID_L1_GPTM4	251
+#define MD_IRQID_L1_GPTM5	252
+#define MD_IRQID_L1_GPTM6	253
+#define MD_IRQID_L1LITE_GPTM_INT	254
+#define MD_IRQID_PPC_CIRQ	255
+
+
+//GIC ID
+#define MD_GICID_VPE0IRQ 0 
+#define MD_GICID_VPE1IRQ 1 
+#define MD_GICID_VPE2IRQ 2 
+#define MD_GICID_VPE3IRQ 3 
+#define MD_GICID_VPE4IRQ 4 
+#define MD_GICID_VPE5IRQ 5 
+#define MD_GICID_VPE6IRQ 6 
+#define MD_GICID_VPE7IRQ 7 
+#define MD_GICID_VPE0NMI 8
+#define MD_GICID_VPE1NMI 9
+#define MD_GICID_VPE2NMI 10
+#define MD_GICID_VPE3NMI 11
+#define MD_GICID_VPE4NMI 12
+#define MD_GICID_VPE5NMI 13
+#define MD_GICID_VPE6NMI 14
+#define MD_GICID_VPE7NMI 15
+#define MD_GICID_VPE0WEDGE 16
+#define MD_GICID_VPE1WEDGE 17
+#define MD_GICID_VPE2WEDGE 18
+#define MD_GICID_VPE3WEDGE 19
+#define MD_GICID_VPE4WEDGE 20
+#define MD_GICID_VPE5WEDGE 21
+#define MD_GICID_VPE6WEDGE 22
+#define MD_GICID_VPE7WEDGE 23
+#define MD_GICID_VPE0YQ0 24
+#define MD_GICID_VPE0YQ1 25
+#define MD_GICID_VPE0YQ2 26
+#define MD_GICID_VPE0YQ3 27
+#define MD_GICID_VPE1YQ0 28
+#define MD_GICID_VPE1YQ1 29
+#define MD_GICID_VPE1YQ2 30
+#define MD_GICID_VPE1YQ3 31
+#define MD_GICID_VPE2YQ0 32
+#define MD_GICID_VPE2YQ1 33
+#define MD_GICID_VPE2YQ2 34
+#define MD_GICID_VPE2YQ3 35
+#define MD_GICID_VPE3YQ0 36
+#define MD_GICID_VPE3YQ1 37
+#define MD_GICID_VPE3YQ2 38
+#define MD_GICID_VPE3YQ3 39
+#define MD_GICID_VPE4YQ0 40
+#define MD_GICID_VPE4YQ1 41
+#define MD_GICID_VPE4YQ2 42
+#define MD_GICID_VPE4YQ3 43
+#define MD_GICID_VPE5YQ0 44
+#define MD_GICID_VPE5YQ1 45
+#define MD_GICID_VPE5YQ2 46
+#define MD_GICID_VPE5YQ3 47
+#define MD_GICID_VPE6YQ0 48
+#define MD_GICID_VPE6YQ1 49
+#define MD_GICID_VPE6YQ2 50
+#define MD_GICID_VPE6YQ3 51
+#define MD_GICID_VPE7YQ0 52
+#define MD_GICID_VPE7YQ1 53
+#define MD_GICID_VPE7YQ2 54
+#define MD_GICID_VPE7YQ3 55
+#define MD_GICID_RESERVED0 56
+#define MD_GICID_RESERVED1 57
+#define MD_GICID_RESERVED2 58
+#define MD_GICID_RESERVED3 59
+#define MD_GICID_RESERVED4 60
+#define MD_GICID_RESERVED5 61
+#define MD_GICID_RESERVED6 62
+#define MD_GICID_RESERVED7 63
+
+/*
+//#define TEST_VPE0_int_CODE  MD_IRQID_SW_TRIGGER_RESERVED_0
+#define TEST_VPE0_dummy_CODE    MD_IRQID_SW_TRIGGER_RESERVED_1
+#define TEST_VPE0_OS_CODE    MD_IRQID_SW_TRIGGER_RESERVED_2
+//#define TEST_VPE1_int_CODE  MD_IRQID_SW_TRIGGER_RESERVED_3
+//#define TEST_VPE1_dummy_CODE    MD_IRQID_SW_TRIGGER_RESERVED_4
+#define TEST_VPE1_OS_CODE    MD_IRQID_SW_TRIGGER_RESERVED_5
+//#define TEST_VPE2_int_CODE  MD_IRQID_SW_TRIGGER_RESERVED_6
+#define TEST_VPE2_dummy_CODE    MD_IRQID_SW_TRIGGER_RESERVED_7
+#define TEST_VPE2_OS_CODE    MD_IRQID_SW_TRIGGER_RESERVED_8
+//#define TEST_VPE3_int_CODE  MD_IRQID_SW_TRIGGER_RESERVED_9
+//#define TEST_VPE3_dummy_CODE    MD_IRQID_SW_TRIGGER_RESERVED_10
+#define TEST_VPE3_OS_CODE    MD_IRQID_SW_TRIGGER_RESERVED_11
+//#define TEST_VPE4_int_CODE  MD_IRQID_SW_TRIGGER_RESERVED_12
+#define TEST_VPE4_dummy_CODE    MD_IRQID_SW_TRIGGER_RESERVED_13
+#define TEST_VPE4_OS_CODE    MD_IRQID_SW_TRIGGER_RESERVED_14
+//#define TEST_VPE5_int_CODE  MD_IRQID_SW_TRIGGER_RESERVED_15
+//#define TEST_VPE5_dummy_CODE    MD_IRQID_SW_TRIGGER_RESERVED_16
+#define TEST_VPE5_OS_CODE    MD_IRQID_SW_TRIGGER_RESERVED_17
+//#define TEST_VPE6_int_CODE  MD_IRQID_SW_TRIGGER_RESERVED_18
+//#define TEST_VPE6_dummy_CODE    MD_IRQID_SW_TRIGGER_RESERVED_19
+#define TEST_VPE6_OS_CODE    MD_IRQID_SW_TRIGGER_RESERVED_20
+//#define TEST_VPE7_int_CODE  MD_IRQID_SW_TRIGGER_RESERVED_21
+//#define TEST_VPE7_dummy_CODE    MD_IRQID_SW_TRIGGER_RESERVED_22
+#define TEST_VPE7_OS_CODE    MD_IRQID_SW_TRIGGER_RESERVED_23
+*/
+#endif /*end of __ELBRUS_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6739.h b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6739.h
new file mode 100644
index 0000000..f464591
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6739.h
@@ -0,0 +1,245 @@
+#ifndef __MT6739_IRQID_H__
+#define __MT6739_IRQID_H__
+
+
+#define MD_IRQID_SHARE_D12MINT1	0
+#define MD_IRQID_IRDBG_MCU_INT	1
+#define MD_IRQID_TDMA_CTIRQ1	2
+#define MD_IRQID_TDMA_CTIRQ2	3
+#define MD_IRQID_TDMA_CTIRQ3	4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ	5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ	6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ	7
+#define MD_IRQID_CSSYS_1X_CS_IRQ	8
+#define MD_IRQID_CSSYS_DO_CS_IRQ	9
+#define MD_IRQID_MDWDT        	10
+#define MD_IRQID_UART_MD0    	11
+#define MD_IRQID_UART_MD1    	12
+#define MD_IRQID_OST          	13
+#define MD_IRQID_USIM0       	14
+#define MD_IRQID_USIM1       	15
+#define MD_IRQID_TOPSM       	16
+#define MD_IRQID_MDGDMA0     	17
+#define MD_IRQID_MDGDMA1     	18
+#define MD_IRQID_MDGDMA2     	19
+#define MD_IRQID_MDGDMA3     	20
+#define MD_IRQID_EINT0       	21
+#define MD_IRQID_EINT1       	22
+#define MD_IRQID_EINT2       	23
+#define MD_IRQID_EINT_SHARE  	24
+#define MD_IRQID_BUS_ERR     	25
+#define MD_IRQID_TXBRP0	26
+#define MD_IRQID_TXBRP1	27
+#define MD_IRQID_TXCRP	28
+#define MD_IRQ_ID_MML2_HRT	29
+#define MD_IRQ_ID_MML2_NOTIF	30
+#define MD_IRQ_ID_MML2_EXCEP	31
+#define MD_IRQID_DEM_TRIG_PS_INT_LE	32
+#define MD_IRQID_ECT          	33
+#define MD_IRQID_PTP_THERM_INT_INT	34
+#define MD_IRQID_CLDMA        	35
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS	36
+#define MD_IRQID_ELM_DMA_IRQ	37
+#define MD_IRQID_SOE         	38
+#define MD_IRQID_ULSP_LOG_MD_INT	39
+#define MD_IRQID_ULSP_LOG_DSP_INT	40
+#define MD_IRQID_USIP0_0	41
+#define MD_IRQID_USIP1_0	42
+#define MD_IRQID_USIP2_0	43
+#define MD_IRQID_USIP3_0	44
+#define MD_IRQID_USIP0_1	45
+#define MD_IRQID_USIP1_1	46
+#define MD_IRQID_USIP2_1	47
+#define MD_IRQID_USIP3_1	48
+#define MD_IRQID_SI_CM_ERR	49
+#define MD_IRQID_ABM_INT	50
+#define MD_IRQID_ABM_ERROR_INT	51
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS	52
+#define MD_IRQID_ELMTOP_EMI_IRQ	53
+#define MD_IRQID_PPPHA_ENC0_INT	54
+#define MD_IRQID_PPPHA_ENC1_INT	55
+#define MD_IRQID_PPPHA_DEC0_INT	56
+#define MD_IRQID_PPPHA_DEC1_INT	57
+#define MD_IRQID_PTP_FSM_INT	58
+#define MD_IRQID_PTP_SLPCTL_EVENT	59
+#define MD_IRQID_IEBIT_CHECK_IRQ0	60
+#define MD_IRQID_IEBIT_CHECK_IRQ1	61
+#define MD_IRQID_IEBIT_CHECK_IRQ2	62
+#define MD_IRQID_IEBIT_CHECK_IRQ3	63
+#define MD_IRQID_MDCIRQ_WDT0	64
+#define MD_IRQID_MDCIRQ_WDT1	65
+#define MD_IRQID_TRACE_INT	66
+#define MD_IRQID_SI_CM_PCINT	67
+#define MD_IRQID_PLL_GEARHP_RDY	68
+#define MD_IRQID_DCXO_RDY_WO_ACK_IRQ	69
+#define MD_IRQID_REQ_ABNORM_IRQ	70
+#define MD_IRQID_TOP_PLL_DSNS_IRQ	71
+#define MD_IRQID_BT_CVSD	72
+#define MD_IRQID_SSUSB_USB_MCU	73
+#define MD_IRQID_SSUSB_DEV	74
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM	75
+#define MD_IRQID_AP2MD_CCIF0_0	76
+#define MD_IRQID_AP2MD_CCIF0_1	77
+#define MD_IRQID_AP2MD_CCIF1_0	78
+#define MD_IRQID_AP2MD_CCIF1_1	79
+#define MD_IRQID_RXDFE_RXK_READBACK	80
+#define MD_IRQID_BR_DMA_IRQ	81
+#define MD_IRQID_IDC_PM_INT	82
+#define MD_IRQID_IDC_UART_IRQ	83
+#define MD_IRQID_MDRTT	84
+#define MD_IRQID_MDEVDO	85
+#define MD_IRQID_MDM2C_U3G	86
+#define MD_IRQID_MDDFE_DUMP	87
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0	88
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1	89
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ	90
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ	91
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ	92
+#define MD_IRQID_BIGRAM_IRQ	93
+#define MD_IRQID_BR_BDGE_IRQ	94
+#define MD_IRQID_L1_LTE_SLEEP_IRQ	95
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0	96
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1	97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0	98
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1	99
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2	100
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3	101
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4	102
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5	103
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6	104
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7	105
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ	106
+#define MD_IRQID_MDL1_TOPSM_IRQ	107
+#define MD_IRQID_TDD_WAKEUP_IRQ	108
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ	109
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ	110
+#define MD_IRQID_RTR_FRAME_IRQ	111
+#define MD_IRQID_RTR_SLT_0_IRQ	112
+#define MD_IRQID_RTR_SLT_1_IRQ	113
+#define MD_IRQID_FDD_SLP_IRQ	114
+#define MD_IRQID_TDMA_WAKEUP_IRQ	115
+#define MD_IRQID_MD_DVFS_CTRL_IRQ	116
+#define MD_IRQID_BSI_MM_I_IRQ_RFIC	117
+#define MD_IRQID_BSI_MM_I_IRQ_MIPI	118
+#define MD_IRQID_ST1X_CPINT	119
+#define MD_IRQID_ST1x_HALF_CPINT	120
+#define MD_IRQID_ST1x_CFG_CPINT	121
+#define MD_IRQID_ST1x_WAKEUP_IRQ	122
+#define MD_IRQID_STDO_CPINT	123
+#define MD_IRQID_STDO_HALF_CPINT	124
+#define MD_IRQID_STDO_CFG_CPINT	125
+#define MD_IRQID_STDO_WAKEUP_IRQ	126
+#define MD_IRQID_FREQM_IRQ	127
+#define MD_IRQID_SPM2MD_DVFS_MDPERISYS	128
+#define MD_IRQID_TXDFE_BB_IRQ	129
+#define MD_IRQID_PCC_TOP_FULL_IRQ	130
+#define MD_IRQID_GPTM1        	131
+#define MD_IRQID_GPTM2        	132
+#define MD_IRQID_GPTM3        	133
+#define MD_IRQID_GPTM4        	134
+#define MD_IRQID_GPTM5       	135
+#define MD_IRQID_GPTM6       	136
+#define MD_IRQID_GPTM7       	137
+#define MD_IRQID_GPTM8      	138
+#define MD_IRQID_GPTM9        	139
+#define MD_IRQID_GPTM10        	140
+#define MD_IRQID_GPTM11      	141
+#define MD_IRQID_BUSMPU_IRQ	142
+#define MD_IRQID_SW_TRIGGER_RESERVED_0	143
+#define MD_IRQID_SW_TRIGGER_RESERVED_1	144
+#define MD_IRQID_SW_TRIGGER_RESERVED_2	145
+#define MD_IRQID_SW_TRIGGER_RESERVED_3	146
+#define MD_IRQID_SW_TRIGGER_RESERVED_4	147
+#define MD_IRQID_SW_TRIGGER_RESERVED_5	148
+#define MD_IRQID_SW_TRIGGER_RESERVED_6	149
+#define MD_IRQID_SW_TRIGGER_RESERVED_7	150
+#define MD_IRQID_SW_TRIGGER_RESERVED_8	151
+#define MD_IRQID_SW_TRIGGER_RESERVED_9	152
+#define MD_IRQID_SW_TRIGGER_RESERVED_10	153
+#define MD_IRQID_SW_TRIGGER_RESERVED_11	154
+#define MD_IRQID_SW_TRIGGER_RESERVED_12	155
+#define MD_IRQID_SW_TRIGGER_RESERVED_13	156
+#define MD_IRQID_SW_TRIGGER_RESERVED_14	157
+#define MD_IRQID_SW_TRIGGER_RESERVED_15	158
+#define MD_IRQID_SW_TRIGGER_RESERVED_16	159
+#define MD_IRQID_SW_TRIGGER_RESERVED_17	160
+#define MD_IRQID_SW_TRIGGER_RESERVED_18	161
+#define MD_IRQID_SW_TRIGGER_RESERVED_19	162
+#define MD_IRQID_SW_TRIGGER_RESERVED_20	163
+#define MD_IRQID_SW_TRIGGER_RESERVED_21	164
+#define MD_IRQID_SW_TRIGGER_RESERVED_22	165
+#define MD_IRQID_SW_TRIGGER_RESERVED_23	166
+#define MD_IRQID_SW_TRIGGER_RESERVED_24	167
+#define MD_IRQID_SW_TRIGGER_RESERVED_25	168
+#define MD_IRQID_SW_TRIGGER_RESERVED_26	169
+#define MD_IRQID_SW_TRIGGER_RESERVED_27	170
+#define MD_IRQID_SW_TRIGGER_RESERVED_28	171
+#define MD_IRQID_SW_TRIGGER_RESERVED_29	172
+#define MD_IRQID_SW_TRIGGER_RESERVED_30	173
+#define MD_IRQID_SW_TRIGGER_RESERVED_31	174
+#define MD_IRQID_SW_TRIGGER_RESERVED_32	175
+#define MD_IRQID_SW_TRIGGER_RESERVED_33	176
+#define MD_IRQID_SW_TRIGGER_RESERVED_34	177
+#define MD_IRQID_SW_TRIGGER_RESERVED_35	178
+#define MD_IRQID_SW_TRIGGER_RESERVED_36	179
+#define MD_IRQID_SW_TRIGGER_RESERVED_37	180
+#define MD_IRQID_SW_TRIGGER_RESERVED_38	181
+#define MD_IRQID_SW_TRIGGER_RESERVED_39	182
+#define MD_IRQID_SW_TRIGGER_RESERVED_40	183
+#define MD_IRQID_SW_TRIGGER_RESERVED_41	184
+#define MD_IRQID_SW_TRIGGER_RESERVED_42	185
+#define MD_IRQID_SW_TRIGGER_RESERVED_43	186
+#define MD_IRQID_SW_TRIGGER_RESERVED_44	187
+#define MD_IRQID_SW_TRIGGER_RESERVED_45	188
+#define MD_IRQID_SW_TRIGGER_RESERVED_46	189
+#define MD_IRQID_SW_TRIGGER_RESERVED_47	190
+#define MD_IRQID_SW_TRIGGER_RESERVED_48	191
+#define MD_IRQID_SW_TRIGGER_RESERVED_49	192
+#define MD_IRQID_SW_TRIGGER_RESERVED_50	193
+#define MD_IRQID_SW_TRIGGER_RESERVED_51	194
+#define MD_IRQID_SW_TRIGGER_RESERVED_52	195
+#define MD_IRQID_SW_TRIGGER_RESERVED_53	196
+#define MD_IRQID_SW_TRIGGER_RESERVED_54	197
+#define MD_IRQID_SW_TRIGGER_RESERVED_55	198
+#define MD_IRQID_SW_TRIGGER_RESERVED_56	199
+#define MD_IRQID_SW_TRIGGER_RESERVED_57	200
+#define MD_IRQID_SW_TRIGGER_RESERVED_58	201
+#define MD_IRQID_SW_TRIGGER_RESERVED_59	202
+#define MD_IRQID_SW_TRIGGER_RESERVED_60	203
+#define MD_IRQID_SW_TRIGGER_RESERVED_61	204
+#define MD_IRQID_SW_TRIGGER_RESERVED_62	205
+#define MD_IRQID_SW_TRIGGER_RESERVED_63	206
+#define MD_IRQID_MCU_BUS_DECERR	207
+#define MD_IRQID_GIC0_FDCInt	208
+#define MD_IRQID_GIC0_FDCInt_1	209
+#define MD_IRQID_GIC0_PCInt	210
+#define MD_IRQID_GIC0_PCInt_1	211
+#define MD_IRQID_GIC0_TimerInt	212
+#define MD_IRQID_GIC0_TimerInt_1	213
+#define MD_IRQID_GIC1_FDCInt	214
+#define MD_IRQID_GIC1_FDCInt_1	215
+#define MD_IRQID_GIC1_PCInt	216
+#define MD_IRQID_GIC1_PCInt_1	217
+#define MD_IRQID_GIC1_TimerInt	218
+#define MD_IRQID_GIC1_TimerInt_1	219
+#define MD_IRQID_EINT3      	220
+#define MD_IRQID_MCUMMU_INT	221
+#define MD_IRQID_IA_DECERR	222
+#define MD_IRQID_RMPU_CTIREIGIN	223
+#define MD_IRQID_MDSM_CORE_PWR_CTRL	224
+#define MD_IRQID_AP2MD_MSDC0	225
+
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_SI_INT 5
+#define VPE_IRQID_CSC 6
+#define VPE_IRQID_END 7
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6739_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6761.h b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6761.h
new file mode 100644
index 0000000..f19e600
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6761.h
@@ -0,0 +1,245 @@
+#ifndef __MT6761_IRQID_H__
+#define __MT6761_IRQID_H__
+
+
+#define MD_IRQID_SHARE_D12MINT1	0
+#define MD_IRQID_IRDBG_MCU_INT	1
+#define MD_IRQID_TDMA_CTIRQ1	2
+#define MD_IRQID_TDMA_CTIRQ2	3
+#define MD_IRQID_TDMA_CTIRQ3	4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ	5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ	6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ	7
+#define MD_IRQID_CSSYS_1X_CS_IRQ	8
+#define MD_IRQID_CSSYS_DO_CS_IRQ	9
+#define MD_IRQID_MDWDT        	10
+#define MD_IRQID_UART_MD0    	11
+#define MD_IRQID_UART_MD1    	12
+#define MD_IRQID_OST          	13
+#define MD_IRQID_USIM0       	14
+#define MD_IRQID_USIM1       	15
+#define MD_IRQID_TOPSM       	16
+#define MD_IRQID_MDGDMA0     	17
+#define MD_IRQID_MDGDMA1     	18
+#define MD_IRQID_MDGDMA2     	19
+#define MD_IRQID_MDGDMA3     	20
+#define MD_IRQID_EINT0       	21
+#define MD_IRQID_EINT1       	22
+#define MD_IRQID_EINT2       	23
+#define MD_IRQID_EINT_SHARE  	24
+#define MD_IRQID_BUS_ERR     	25
+#define MD_IRQID_TXBRP0	26
+#define MD_IRQID_TXBRP1	27
+#define MD_IRQID_TXCRP	28
+#define MD_IRQ_ID_MML2_HRT	29
+#define MD_IRQ_ID_MML2_NOTIF	30
+#define MD_IRQ_ID_MML2_EXCEP	31
+#define MD_IRQID_DEM_TRIG_PS_INT_LE	32
+#define MD_IRQID_ECT          	33
+#define MD_IRQID_PTP_THERM_INT_INT	34
+#define MD_IRQID_CLDMA        	35
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS	36
+#define MD_IRQID_ELM_DMA_IRQ	37
+#define MD_IRQID_SOE         	38
+#define MD_IRQID_ULSP_LOG_MD_INT	39
+#define MD_IRQID_ULSP_LOG_DSP_INT	40
+#define MD_IRQID_USIP0_0	41
+#define MD_IRQID_USIP1_0	42
+#define MD_IRQID_USIP2_0	43
+#define MD_IRQID_USIP3_0	44
+#define MD_IRQID_USIP0_1	45
+#define MD_IRQID_USIP1_1	46
+#define MD_IRQID_AP2MD_CCIF2_0	47
+#define MD_IRQID_USIP3_1	48
+#define MD_IRQID_SI_CM_ERR	49
+#define MD_IRQID_ABM_INT	50
+#define MD_IRQID_ABM_ERROR_INT	51
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS	52
+#define MD_IRQID_ELMTOP_EMI_IRQ	53
+#define MD_IRQID_PPPHA_ENC0_INT	54
+#define MD_IRQID_PPPHA_ENC1_INT	55
+#define MD_IRQID_PPPHA_DEC0_INT	56
+#define MD_IRQID_PPPHA_DEC1_INT	57
+#define MD_IRQID_PTP_FSM_INT	58
+#define MD_IRQID_PTP_SLPCTL_EVENT	59
+#define MD_IRQID_IEBIT_CHECK_IRQ0	60
+#define MD_IRQID_IEBIT_CHECK_IRQ1	61
+#define MD_IRQID_IEBIT_CHECK_IRQ2	62
+#define MD_IRQID_IEBIT_CHECK_IRQ3	63
+#define MD_IRQID_MDCIRQ_WDT0	64
+#define MD_IRQID_MDCIRQ_WDT1	65
+#define MD_IRQID_TRACE_INT	66
+#define MD_IRQID_SI_CM_PCINT	67
+#define MD_IRQID_PLL_GEARHP_RDY	68
+#define MD_IRQID_DCXO_RDY_WO_ACK_IRQ	69
+#define MD_IRQID_REQ_ABNORM_IRQ	70
+#define MD_IRQID_TOP_PLL_DSNS_IRQ	71
+#define MD_IRQID_BT_CVSD	72
+#define MD_IRQID_SSUSB_USB_MCU	73
+#define MD_IRQID_SSUSB_DEV	74
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM	75
+#define MD_IRQID_AP2MD_CCIF0_0	76
+#define MD_IRQID_AP2MD_CCIF0_1	77
+#define MD_IRQID_AP2MD_CCIF1_0	78
+#define MD_IRQID_AP2MD_CCIF1_1	79
+#define MD_IRQID_RXDFE_RXK_READBACK	80
+#define MD_IRQID_BR_DMA_IRQ	81
+#define MD_IRQID_IDC_PM_INT	82
+#define MD_IRQID_IDC_UART_IRQ	83
+#define MD_IRQID_MDRTT	84
+#define MD_IRQID_MDEVDO	85
+#define MD_IRQID_MDM2C_U3G	86
+#define MD_IRQID_MDDFE_DUMP	87
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0	88
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1	89
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ	90
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ	91
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ	92
+#define MD_IRQID_BIGRAM_IRQ	93
+#define MD_IRQID_BR_BDGE_IRQ	94
+#define MD_IRQID_L1_LTE_SLEEP_IRQ	95
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0	96
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1	97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0	98
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1	99
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2	100
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3	101
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4	102
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5	103
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6	104
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7	105
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ	106
+#define MD_IRQID_MDL1_TOPSM_IRQ	107
+#define MD_IRQID_TDD_WAKEUP_IRQ	108
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ	109
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ	110
+#define MD_IRQID_RTR_FRAME_IRQ	111
+#define MD_IRQID_RTR_SLT_0_IRQ	112
+#define MD_IRQID_RTR_SLT_1_IRQ	113
+#define MD_IRQID_FDD_SLP_IRQ	114
+#define MD_IRQID_TDMA_WAKEUP_IRQ	115
+#define MD_IRQID_MD_DVFS_CTRL_IRQ	116
+#define MD_IRQID_BSI_MM_I_IRQ_RFIC	117
+#define MD_IRQID_BSI_MM_I_IRQ_MIPI	118
+#define MD_IRQID_ST1X_CPINT	119
+#define MD_IRQID_ST1x_HALF_CPINT	120
+#define MD_IRQID_ST1x_CFG_CPINT	121
+#define MD_IRQID_ST1x_WAKEUP_IRQ	122
+#define MD_IRQID_STDO_CPINT	123
+#define MD_IRQID_STDO_HALF_CPINT	124
+#define MD_IRQID_STDO_CFG_CPINT	125
+#define MD_IRQID_STDO_WAKEUP_IRQ	126
+#define MD_IRQID_FREQM_IRQ	127
+#define MD_IRQID_SPM2MD_DVFS_MDPERISYS	128
+#define MD_IRQID_TXDFE_BB_IRQ	129
+#define MD_IRQID_PCC_TOP_FULL_IRQ	130
+#define MD_IRQID_GPTM1        	131
+#define MD_IRQID_GPTM2        	132
+#define MD_IRQID_GPTM3        	133
+#define MD_IRQID_GPTM4        	134
+#define MD_IRQID_GPTM5       	135
+#define MD_IRQID_GPTM6       	136
+#define MD_IRQID_GPTM7       	137
+#define MD_IRQID_GPTM8      	138
+#define MD_IRQID_GPTM9        	139
+#define MD_IRQID_GPTM10        	140
+#define MD_IRQID_GPTM11      	141
+#define MD_IRQID_BUSMPU_IRQ	142
+#define MD_IRQID_SW_TRIGGER_RESERVED_0	143
+#define MD_IRQID_SW_TRIGGER_RESERVED_1	144
+#define MD_IRQID_SW_TRIGGER_RESERVED_2	145
+#define MD_IRQID_SW_TRIGGER_RESERVED_3	146
+#define MD_IRQID_SW_TRIGGER_RESERVED_4	147
+#define MD_IRQID_SW_TRIGGER_RESERVED_5	148
+#define MD_IRQID_SW_TRIGGER_RESERVED_6	149
+#define MD_IRQID_SW_TRIGGER_RESERVED_7	150
+#define MD_IRQID_SW_TRIGGER_RESERVED_8	151
+#define MD_IRQID_SW_TRIGGER_RESERVED_9	152
+#define MD_IRQID_SW_TRIGGER_RESERVED_10	153
+#define MD_IRQID_SW_TRIGGER_RESERVED_11	154
+#define MD_IRQID_SW_TRIGGER_RESERVED_12	155
+#define MD_IRQID_SW_TRIGGER_RESERVED_13	156
+#define MD_IRQID_SW_TRIGGER_RESERVED_14	157
+#define MD_IRQID_SW_TRIGGER_RESERVED_15	158
+#define MD_IRQID_SW_TRIGGER_RESERVED_16	159
+#define MD_IRQID_SW_TRIGGER_RESERVED_17	160
+#define MD_IRQID_SW_TRIGGER_RESERVED_18	161
+#define MD_IRQID_SW_TRIGGER_RESERVED_19	162
+#define MD_IRQID_SW_TRIGGER_RESERVED_20	163
+#define MD_IRQID_SW_TRIGGER_RESERVED_21	164
+#define MD_IRQID_SW_TRIGGER_RESERVED_22	165
+#define MD_IRQID_SW_TRIGGER_RESERVED_23	166
+#define MD_IRQID_SW_TRIGGER_RESERVED_24	167
+#define MD_IRQID_SW_TRIGGER_RESERVED_25	168
+#define MD_IRQID_SW_TRIGGER_RESERVED_26	169
+#define MD_IRQID_SW_TRIGGER_RESERVED_27	170
+#define MD_IRQID_SW_TRIGGER_RESERVED_28	171
+#define MD_IRQID_SW_TRIGGER_RESERVED_29	172
+#define MD_IRQID_SW_TRIGGER_RESERVED_30	173
+#define MD_IRQID_SW_TRIGGER_RESERVED_31	174
+#define MD_IRQID_SW_TRIGGER_RESERVED_32	175
+#define MD_IRQID_SW_TRIGGER_RESERVED_33	176
+#define MD_IRQID_SW_TRIGGER_RESERVED_34	177
+#define MD_IRQID_SW_TRIGGER_RESERVED_35	178
+#define MD_IRQID_SW_TRIGGER_RESERVED_36	179
+#define MD_IRQID_SW_TRIGGER_RESERVED_37	180
+#define MD_IRQID_SW_TRIGGER_RESERVED_38	181
+#define MD_IRQID_SW_TRIGGER_RESERVED_39	182
+#define MD_IRQID_SW_TRIGGER_RESERVED_40	183
+#define MD_IRQID_SW_TRIGGER_RESERVED_41	184
+#define MD_IRQID_SW_TRIGGER_RESERVED_42	185
+#define MD_IRQID_SW_TRIGGER_RESERVED_43	186
+#define MD_IRQID_SW_TRIGGER_RESERVED_44	187
+#define MD_IRQID_SW_TRIGGER_RESERVED_45	188
+#define MD_IRQID_SW_TRIGGER_RESERVED_46	189
+#define MD_IRQID_SW_TRIGGER_RESERVED_47	190
+#define MD_IRQID_SW_TRIGGER_RESERVED_48	191
+#define MD_IRQID_SW_TRIGGER_RESERVED_49	192
+#define MD_IRQID_SW_TRIGGER_RESERVED_50	193
+#define MD_IRQID_SW_TRIGGER_RESERVED_51	194
+#define MD_IRQID_SW_TRIGGER_RESERVED_52	195
+#define MD_IRQID_SW_TRIGGER_RESERVED_53	196
+#define MD_IRQID_SW_TRIGGER_RESERVED_54	197
+#define MD_IRQID_SW_TRIGGER_RESERVED_55	198
+#define MD_IRQID_SW_TRIGGER_RESERVED_56	199
+#define MD_IRQID_SW_TRIGGER_RESERVED_57	200
+#define MD_IRQID_SW_TRIGGER_RESERVED_58	201
+#define MD_IRQID_SW_TRIGGER_RESERVED_59	202
+#define MD_IRQID_SW_TRIGGER_RESERVED_60	203
+#define MD_IRQID_SW_TRIGGER_RESERVED_61	204
+#define MD_IRQID_SW_TRIGGER_RESERVED_62	205
+#define MD_IRQID_SW_TRIGGER_RESERVED_63	206
+#define MD_IRQID_MCU_BUS_DECERR	207
+#define MD_IRQID_GIC0_FDCInt	208
+#define MD_IRQID_GIC0_FDCInt_1	209
+#define MD_IRQID_GIC0_PCInt	210
+#define MD_IRQID_GIC0_PCInt_1	211
+#define MD_IRQID_GIC0_TimerInt	212
+#define MD_IRQID_GIC0_TimerInt_1	213
+#define MD_IRQID_GIC1_FDCInt	214
+#define MD_IRQID_GIC1_FDCInt_1	215
+#define MD_IRQID_GIC1_PCInt	216
+#define MD_IRQID_GIC1_PCInt_1	217
+#define MD_IRQID_GIC1_TimerInt	218
+#define MD_IRQID_GIC1_TimerInt_1	219
+#define MD_IRQID_EINT3      	220
+#define MD_IRQID_MCUMMU_INT	221
+#define MD_IRQID_IA_DECERR	222
+#define MD_IRQID_RMPU_CTIREIGIN	223
+#define MD_IRQID_MDSM_CORE_PWR_CTRL	224
+#define MD_IRQID_AP2MD_MSDC0	225
+
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_SI_INT 5
+#define VPE_IRQID_CSC 6
+#define VPE_IRQID_END 7
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6761_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6763.h b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6763.h
new file mode 100644
index 0000000..26e6300
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6763.h
@@ -0,0 +1,245 @@
+#ifndef __MT6763_IRQID_H__
+#define __MT6763_IRQID_H__
+
+
+#define MD_IRQID_SHARE_D12MINT1	0
+#define MD_IRQID_IRDBG_MCU_INT	1
+#define MD_IRQID_TDMA_CTIRQ1	2
+#define MD_IRQID_TDMA_CTIRQ2	3
+#define MD_IRQID_TDMA_CTIRQ3	4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ	5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ	6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ	7
+#define MD_IRQID_CSSYS_1X_CS_IRQ	8
+#define MD_IRQID_CSSYS_DO_CS_IRQ	9
+#define MD_IRQID_MDWDT        	10
+#define MD_IRQID_UART_MD0    	11
+#define MD_IRQID_UART_MD1    	12
+#define MD_IRQID_OST          	13
+#define MD_IRQID_USIM0       	14
+#define MD_IRQID_USIM1       	15
+#define MD_IRQID_TOPSM       	16
+#define MD_IRQID_MDGDMA0     	17
+#define MD_IRQID_MDGDMA1     	18
+#define MD_IRQID_MDGDMA2     	19
+#define MD_IRQID_MDGDMA3     	20
+#define MD_IRQID_EINT0       	21
+#define MD_IRQID_EINT1       	22
+#define MD_IRQID_EINT2       	23
+#define MD_IRQID_EINT_SHARE  	24
+#define MD_IRQID_BUS_ERR     	25
+#define MD_IRQID_TXBRP0	26
+#define MD_IRQID_TXBRP1	27
+#define MD_IRQID_TXCRP	28
+#define MD_IRQ_ID_MML2_HRT	29
+#define MD_IRQ_ID_MML2_NOTIF	30
+#define MD_IRQ_ID_MML2_EXCEP	31
+#define MD_IRQID_DEM_TRIG_PS_INT_LE	32
+#define MD_IRQID_ECT          	33
+#define MD_IRQID_PTP_THERM_INT_INT	34
+#define MD_IRQID_CLDMA        	35
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS	36
+#define MD_IRQID_ELM_DMA_IRQ	37
+#define MD_IRQID_SOE         	38
+#define MD_IRQID_ULSP_LOG_MD_INT	39
+#define MD_IRQID_ULSP_LOG_DSP_INT	40
+#define MD_IRQID_USIP0_0	41
+#define MD_IRQID_USIP1_0	42
+#define MD_IRQID_USIP2_0	43
+#define MD_IRQID_USIP3_0	44
+#define MD_IRQID_USIP0_1	45
+#define MD_IRQID_USIP1_1	46
+#define MD_IRQID_USIP2_1	47
+#define MD_IRQID_USIP3_1	48
+#define MD_IRQID_SI_CM_ERR	49
+#define MD_IRQID_ABM_INT	50
+#define MD_IRQID_ABM_ERROR_INT	51
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS	52
+#define MD_IRQID_ELMTOP_EMI_IRQ	53
+#define MD_IRQID_PPPHA_ENC0_INT	54
+#define MD_IRQID_PPPHA_ENC1_INT	55
+#define MD_IRQID_PPPHA_DEC0_INT	56
+#define MD_IRQID_PPPHA_DEC1_INT	57
+#define MD_IRQID_PTP_FSM_INT	58
+#define MD_IRQID_PTP_SLPCTL_EVENT	59
+#define MD_IRQID_IEBIT_CHECK_IRQ0	60
+#define MD_IRQID_IEBIT_CHECK_IRQ1	61
+#define MD_IRQID_IEBIT_CHECK_IRQ2	62
+#define MD_IRQID_IEBIT_CHECK_IRQ3	63
+#define MD_IRQID_MDCIRQ_WDT0	64
+#define MD_IRQID_MDCIRQ_WDT1	65
+#define MD_IRQID_TRACE_INT	66
+#define MD_IRQID_SI_CM_PCINT	67
+#define MD_IRQID_PLL_GEARHP_RDY	68
+#define MD_IRQID_DCXO_RDY_WO_ACK_IRQ	69
+#define MD_IRQID_REQ_ABNORM_IRQ	70
+#define MD_IRQID_TOP_PLL_DSNS_IRQ	71
+#define MD_IRQID_BT_CVSD	72
+#define MD_IRQID_SSUSB_USB_MCU	73
+#define MD_IRQID_SSUSB_DEV	74
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM	75
+#define MD_IRQID_AP2MD_CCIF0_0	76
+#define MD_IRQID_AP2MD_CCIF0_1	77
+#define MD_IRQID_AP2MD_CCIF1_0	78
+#define MD_IRQID_AP2MD_CCIF1_1	79
+#define MD_IRQID_RXDFE_RXK_READBACK	80
+#define MD_IRQID_BR_DMA_IRQ	81
+#define MD_IRQID_IDC_PM_INT	82
+#define MD_IRQID_IDC_UART_IRQ	83
+#define MD_IRQID_MDRTT	84
+#define MD_IRQID_MDEVDO	85
+#define MD_IRQID_MDM2C_U3G	86
+#define MD_IRQID_MDDFE_DUMP	87
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0	88
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1	89
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ	90
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ	91
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ	92
+#define MD_IRQID_BIGRAM_IRQ	93
+#define MD_IRQID_BR_BDGE_IRQ	94
+#define MD_IRQID_L1_LTE_SLEEP_IRQ	95
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0	96
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1	97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0	98
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1	99
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2	100
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3	101
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4	102
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5	103
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6	104
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7	105
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ	106
+#define MD_IRQID_MDL1_TOPSM_IRQ	107
+#define MD_IRQID_TDD_WAKEUP_IRQ	108
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ	109
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ	110
+#define MD_IRQID_RTR_FRAME_IRQ	111
+#define MD_IRQID_RTR_SLT_0_IRQ	112
+#define MD_IRQID_RTR_SLT_1_IRQ	113
+#define MD_IRQID_FDD_SLP_IRQ	114
+#define MD_IRQID_TDMA_WAKEUP_IRQ	115
+#define MD_IRQID_MD_DVFS_CTRL_IRQ	116
+#define MD_IRQID_BSI_MM_I_IRQ_RFIC	117
+#define MD_IRQID_BSI_MM_I_IRQ_MIPI	118
+#define MD_IRQID_ST1X_CPINT	119
+#define MD_IRQID_ST1x_HALF_CPINT	120
+#define MD_IRQID_ST1x_CFG_CPINT	121
+#define MD_IRQID_ST1x_WAKEUP_IRQ	122
+#define MD_IRQID_STDO_CPINT	123
+#define MD_IRQID_STDO_HALF_CPINT	124
+#define MD_IRQID_STDO_CFG_CPINT	125
+#define MD_IRQID_STDO_WAKEUP_IRQ	126
+#define MD_IRQID_FREQM_IRQ	127
+#define MD_IRQID_SPM2MD_DVFS_MDPERISYS	128
+#define MD_IRQID_TXDFE_BB_IRQ	129
+#define MD_IRQID_PCC_TOP_FULL_IRQ	130
+#define MD_IRQID_GPTM1        	131
+#define MD_IRQID_GPTM2        	132
+#define MD_IRQID_GPTM3        	133
+#define MD_IRQID_GPTM4        	134
+#define MD_IRQID_GPTM5       	135
+#define MD_IRQID_GPTM6       	136
+#define MD_IRQID_GPTM7       	137
+#define MD_IRQID_GPTM8      	138
+#define MD_IRQID_GPTM9        	139
+#define MD_IRQID_GPTM10        	140
+#define MD_IRQID_GPTM11      	141
+#define MD_IRQID_BUSMPU_IRQ	142
+#define MD_IRQID_SW_TRIGGER_RESERVED_0	143
+#define MD_IRQID_SW_TRIGGER_RESERVED_1	144
+#define MD_IRQID_SW_TRIGGER_RESERVED_2	145
+#define MD_IRQID_SW_TRIGGER_RESERVED_3	146
+#define MD_IRQID_SW_TRIGGER_RESERVED_4	147
+#define MD_IRQID_SW_TRIGGER_RESERVED_5	148
+#define MD_IRQID_SW_TRIGGER_RESERVED_6	149
+#define MD_IRQID_SW_TRIGGER_RESERVED_7	150
+#define MD_IRQID_SW_TRIGGER_RESERVED_8	151
+#define MD_IRQID_SW_TRIGGER_RESERVED_9	152
+#define MD_IRQID_SW_TRIGGER_RESERVED_10	153
+#define MD_IRQID_SW_TRIGGER_RESERVED_11	154
+#define MD_IRQID_SW_TRIGGER_RESERVED_12	155
+#define MD_IRQID_SW_TRIGGER_RESERVED_13	156
+#define MD_IRQID_SW_TRIGGER_RESERVED_14	157
+#define MD_IRQID_SW_TRIGGER_RESERVED_15	158
+#define MD_IRQID_SW_TRIGGER_RESERVED_16	159
+#define MD_IRQID_SW_TRIGGER_RESERVED_17	160
+#define MD_IRQID_SW_TRIGGER_RESERVED_18	161
+#define MD_IRQID_SW_TRIGGER_RESERVED_19	162
+#define MD_IRQID_SW_TRIGGER_RESERVED_20	163
+#define MD_IRQID_SW_TRIGGER_RESERVED_21	164
+#define MD_IRQID_SW_TRIGGER_RESERVED_22	165
+#define MD_IRQID_SW_TRIGGER_RESERVED_23	166
+#define MD_IRQID_SW_TRIGGER_RESERVED_24	167
+#define MD_IRQID_SW_TRIGGER_RESERVED_25	168
+#define MD_IRQID_SW_TRIGGER_RESERVED_26	169
+#define MD_IRQID_SW_TRIGGER_RESERVED_27	170
+#define MD_IRQID_SW_TRIGGER_RESERVED_28	171
+#define MD_IRQID_SW_TRIGGER_RESERVED_29	172
+#define MD_IRQID_SW_TRIGGER_RESERVED_30	173
+#define MD_IRQID_SW_TRIGGER_RESERVED_31	174
+#define MD_IRQID_SW_TRIGGER_RESERVED_32	175
+#define MD_IRQID_SW_TRIGGER_RESERVED_33	176
+#define MD_IRQID_SW_TRIGGER_RESERVED_34	177
+#define MD_IRQID_SW_TRIGGER_RESERVED_35	178
+#define MD_IRQID_SW_TRIGGER_RESERVED_36	179
+#define MD_IRQID_SW_TRIGGER_RESERVED_37	180
+#define MD_IRQID_SW_TRIGGER_RESERVED_38	181
+#define MD_IRQID_SW_TRIGGER_RESERVED_39	182
+#define MD_IRQID_SW_TRIGGER_RESERVED_40	183
+#define MD_IRQID_SW_TRIGGER_RESERVED_41	184
+#define MD_IRQID_SW_TRIGGER_RESERVED_42	185
+#define MD_IRQID_SW_TRIGGER_RESERVED_43	186
+#define MD_IRQID_SW_TRIGGER_RESERVED_44	187
+#define MD_IRQID_SW_TRIGGER_RESERVED_45	188
+#define MD_IRQID_SW_TRIGGER_RESERVED_46	189
+#define MD_IRQID_SW_TRIGGER_RESERVED_47	190
+#define MD_IRQID_SW_TRIGGER_RESERVED_48	191
+#define MD_IRQID_SW_TRIGGER_RESERVED_49	192
+#define MD_IRQID_SW_TRIGGER_RESERVED_50	193
+#define MD_IRQID_SW_TRIGGER_RESERVED_51	194
+#define MD_IRQID_SW_TRIGGER_RESERVED_52	195
+#define MD_IRQID_SW_TRIGGER_RESERVED_53	196
+#define MD_IRQID_SW_TRIGGER_RESERVED_54	197
+#define MD_IRQID_SW_TRIGGER_RESERVED_55	198
+#define MD_IRQID_SW_TRIGGER_RESERVED_56	199
+#define MD_IRQID_SW_TRIGGER_RESERVED_57	200
+#define MD_IRQID_SW_TRIGGER_RESERVED_58	201
+#define MD_IRQID_SW_TRIGGER_RESERVED_59	202
+#define MD_IRQID_SW_TRIGGER_RESERVED_60	203
+#define MD_IRQID_SW_TRIGGER_RESERVED_61	204
+#define MD_IRQID_SW_TRIGGER_RESERVED_62	205
+#define MD_IRQID_SW_TRIGGER_RESERVED_63	206
+#define MD_IRQID_MCU_BUS_DECERR	207
+#define MD_IRQID_GIC0_FDCInt	208
+#define MD_IRQID_GIC0_FDCInt_1	209
+#define MD_IRQID_GIC0_PCInt	210
+#define MD_IRQID_GIC0_PCInt_1	211
+#define MD_IRQID_GIC0_TimerInt	212
+#define MD_IRQID_GIC0_TimerInt_1	213
+#define MD_IRQID_GIC1_FDCInt	214
+#define MD_IRQID_GIC1_FDCInt_1	215
+#define MD_IRQID_GIC1_PCInt	216
+#define MD_IRQID_GIC1_PCInt_1	217
+#define MD_IRQID_GIC1_TimerInt	218
+#define MD_IRQID_GIC1_TimerInt_1	219
+#define MD_IRQID_EINT3      	220
+#define MD_IRQID_MCUMMU_INT	221
+#define MD_IRQID_IA_DECERR	222
+#define MD_IRQID_RMPU_CTIREIGIN	223
+#define MD_IRQID_MDSM_CORE_PWR_CTRL	224
+#define MD_IRQID_AP2MD_MSDC0	225
+
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_SI_INT 5
+#define VPE_IRQID_CSC 6
+#define VPE_IRQID_END 7
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6763_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6765.h b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6765.h
new file mode 100644
index 0000000..d4d7479
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6765.h
@@ -0,0 +1,245 @@
+#ifndef __MT6765_IRQID_H__
+#define __MT6765_IRQID_H__
+
+
+#define MD_IRQID_SHARE_D12MINT1	0
+#define MD_IRQID_IRDBG_MCU_INT	1
+#define MD_IRQID_TDMA_CTIRQ1	2
+#define MD_IRQID_TDMA_CTIRQ2	3
+#define MD_IRQID_TDMA_CTIRQ3	4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ	5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ	6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ	7
+#define MD_IRQID_CSSYS_1X_CS_IRQ	8
+#define MD_IRQID_CSSYS_DO_CS_IRQ	9
+#define MD_IRQID_MDWDT        	10
+#define MD_IRQID_UART_MD0    	11
+#define MD_IRQID_UART_MD1    	12
+#define MD_IRQID_OST          	13
+#define MD_IRQID_USIM0       	14
+#define MD_IRQID_USIM1       	15
+#define MD_IRQID_TOPSM       	16
+#define MD_IRQID_MDGDMA0     	17
+#define MD_IRQID_MDGDMA1     	18
+#define MD_IRQID_MDGDMA2     	19
+#define MD_IRQID_MDGDMA3     	20
+#define MD_IRQID_EINT0       	21
+#define MD_IRQID_EINT1       	22
+#define MD_IRQID_EINT2       	23
+#define MD_IRQID_EINT_SHARE  	24
+#define MD_IRQID_BUS_ERR     	25
+#define MD_IRQID_TXBRP0	26
+#define MD_IRQID_TXBRP1	27
+#define MD_IRQID_TXCRP	28
+#define MD_IRQ_ID_MML2_HRT	29
+#define MD_IRQ_ID_MML2_NOTIF	30
+#define MD_IRQ_ID_MML2_EXCEP	31
+#define MD_IRQID_DEM_TRIG_PS_INT_LE	32
+#define MD_IRQID_ECT          	33
+#define MD_IRQID_PTP_THERM_INT_INT	34
+#define MD_IRQID_CLDMA        	35
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS	36
+#define MD_IRQID_ELM_DMA_IRQ	37
+#define MD_IRQID_SOE         	38
+#define MD_IRQID_ULSP_LOG_MD_INT	39
+#define MD_IRQID_ULSP_LOG_DSP_INT	40
+#define MD_IRQID_USIP0_0	41
+#define MD_IRQID_USIP1_0	42
+#define MD_IRQID_USIP2_0	43
+#define MD_IRQID_USIP3_0	44
+#define MD_IRQID_USIP0_1	45
+#define MD_IRQID_USIP1_1	46
+#define MD_IRQID_AP2MD_CCIF2_0	47
+#define MD_IRQID_USIP3_1	48
+#define MD_IRQID_SI_CM_ERR	49
+#define MD_IRQID_ABM_INT	50
+#define MD_IRQID_ABM_ERROR_INT	51
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS	52
+#define MD_IRQID_ELMTOP_EMI_IRQ	53
+#define MD_IRQID_PPPHA_ENC0_INT	54
+#define MD_IRQID_PPPHA_ENC1_INT	55
+#define MD_IRQID_PPPHA_DEC0_INT	56
+#define MD_IRQID_PPPHA_DEC1_INT	57
+#define MD_IRQID_PTP_FSM_INT	58
+#define MD_IRQID_PTP_SLPCTL_EVENT	59
+#define MD_IRQID_IEBIT_CHECK_IRQ0	60
+#define MD_IRQID_IEBIT_CHECK_IRQ1	61
+#define MD_IRQID_IEBIT_CHECK_IRQ2	62
+#define MD_IRQID_IEBIT_CHECK_IRQ3	63
+#define MD_IRQID_MDCIRQ_WDT0	64
+#define MD_IRQID_MDCIRQ_WDT1	65
+#define MD_IRQID_TRACE_INT	66
+#define MD_IRQID_SI_CM_PCINT	67
+#define MD_IRQID_PLL_GEARHP_RDY	68
+#define MD_IRQID_DCXO_RDY_WO_ACK_IRQ	69
+#define MD_IRQID_REQ_ABNORM_IRQ	70
+#define MD_IRQID_TOP_PLL_DSNS_IRQ	71
+#define MD_IRQID_BT_CVSD	72
+#define MD_IRQID_SSUSB_USB_MCU	73
+#define MD_IRQID_SSUSB_DEV	74
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM	75
+#define MD_IRQID_AP2MD_CCIF0_0	76
+#define MD_IRQID_AP2MD_CCIF0_1	77
+#define MD_IRQID_AP2MD_CCIF1_0	78
+#define MD_IRQID_AP2MD_CCIF1_1	79
+#define MD_IRQID_RXDFE_RXK_READBACK	80
+#define MD_IRQID_BR_DMA_IRQ	81
+#define MD_IRQID_IDC_PM_INT	82
+#define MD_IRQID_IDC_UART_IRQ	83
+#define MD_IRQID_MDRTT	84
+#define MD_IRQID_MDEVDO	85
+#define MD_IRQID_MDM2C_U3G	86
+#define MD_IRQID_MDDFE_DUMP	87
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0	88
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1	89
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ	90
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ	91
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ	92
+#define MD_IRQID_BIGRAM_IRQ	93
+#define MD_IRQID_BR_BDGE_IRQ	94
+#define MD_IRQID_L1_LTE_SLEEP_IRQ	95
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0	96
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1	97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0	98
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1	99
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2	100
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3	101
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4	102
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5	103
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6	104
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7	105
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ	106
+#define MD_IRQID_MDL1_TOPSM_IRQ	107
+#define MD_IRQID_TDD_WAKEUP_IRQ	108
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ	109
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ	110
+#define MD_IRQID_RTR_FRAME_IRQ	111
+#define MD_IRQID_RTR_SLT_0_IRQ	112
+#define MD_IRQID_RTR_SLT_1_IRQ	113
+#define MD_IRQID_FDD_SLP_IRQ	114
+#define MD_IRQID_TDMA_WAKEUP_IRQ	115
+#define MD_IRQID_MD_DVFS_CTRL_IRQ	116
+#define MD_IRQID_BSI_MM_I_IRQ_RFIC	117
+#define MD_IRQID_BSI_MM_I_IRQ_MIPI	118
+#define MD_IRQID_ST1X_CPINT	119
+#define MD_IRQID_ST1x_HALF_CPINT	120
+#define MD_IRQID_ST1x_CFG_CPINT	121
+#define MD_IRQID_ST1x_WAKEUP_IRQ	122
+#define MD_IRQID_STDO_CPINT	123
+#define MD_IRQID_STDO_HALF_CPINT	124
+#define MD_IRQID_STDO_CFG_CPINT	125
+#define MD_IRQID_STDO_WAKEUP_IRQ	126
+#define MD_IRQID_FREQM_IRQ	127
+#define MD_IRQID_SPM2MD_DVFS_MDPERISYS	128
+#define MD_IRQID_TXDFE_BB_IRQ	129
+#define MD_IRQID_PCC_TOP_FULL_IRQ	130
+#define MD_IRQID_GPTM1        	131
+#define MD_IRQID_GPTM2        	132
+#define MD_IRQID_GPTM3        	133
+#define MD_IRQID_GPTM4        	134
+#define MD_IRQID_GPTM5       	135
+#define MD_IRQID_GPTM6       	136
+#define MD_IRQID_GPTM7       	137
+#define MD_IRQID_GPTM8      	138
+#define MD_IRQID_GPTM9        	139
+#define MD_IRQID_GPTM10        	140
+#define MD_IRQID_GPTM11      	141
+#define MD_IRQID_BUSMPU_IRQ	142
+#define MD_IRQID_SW_TRIGGER_RESERVED_0	143
+#define MD_IRQID_SW_TRIGGER_RESERVED_1	144
+#define MD_IRQID_SW_TRIGGER_RESERVED_2	145
+#define MD_IRQID_SW_TRIGGER_RESERVED_3	146
+#define MD_IRQID_SW_TRIGGER_RESERVED_4	147
+#define MD_IRQID_SW_TRIGGER_RESERVED_5	148
+#define MD_IRQID_SW_TRIGGER_RESERVED_6	149
+#define MD_IRQID_SW_TRIGGER_RESERVED_7	150
+#define MD_IRQID_SW_TRIGGER_RESERVED_8	151
+#define MD_IRQID_SW_TRIGGER_RESERVED_9	152
+#define MD_IRQID_SW_TRIGGER_RESERVED_10	153
+#define MD_IRQID_SW_TRIGGER_RESERVED_11	154
+#define MD_IRQID_SW_TRIGGER_RESERVED_12	155
+#define MD_IRQID_SW_TRIGGER_RESERVED_13	156
+#define MD_IRQID_SW_TRIGGER_RESERVED_14	157
+#define MD_IRQID_SW_TRIGGER_RESERVED_15	158
+#define MD_IRQID_SW_TRIGGER_RESERVED_16	159
+#define MD_IRQID_SW_TRIGGER_RESERVED_17	160
+#define MD_IRQID_SW_TRIGGER_RESERVED_18	161
+#define MD_IRQID_SW_TRIGGER_RESERVED_19	162
+#define MD_IRQID_SW_TRIGGER_RESERVED_20	163
+#define MD_IRQID_SW_TRIGGER_RESERVED_21	164
+#define MD_IRQID_SW_TRIGGER_RESERVED_22	165
+#define MD_IRQID_SW_TRIGGER_RESERVED_23	166
+#define MD_IRQID_SW_TRIGGER_RESERVED_24	167
+#define MD_IRQID_SW_TRIGGER_RESERVED_25	168
+#define MD_IRQID_SW_TRIGGER_RESERVED_26	169
+#define MD_IRQID_SW_TRIGGER_RESERVED_27	170
+#define MD_IRQID_SW_TRIGGER_RESERVED_28	171
+#define MD_IRQID_SW_TRIGGER_RESERVED_29	172
+#define MD_IRQID_SW_TRIGGER_RESERVED_30	173
+#define MD_IRQID_SW_TRIGGER_RESERVED_31	174
+#define MD_IRQID_SW_TRIGGER_RESERVED_32	175
+#define MD_IRQID_SW_TRIGGER_RESERVED_33	176
+#define MD_IRQID_SW_TRIGGER_RESERVED_34	177
+#define MD_IRQID_SW_TRIGGER_RESERVED_35	178
+#define MD_IRQID_SW_TRIGGER_RESERVED_36	179
+#define MD_IRQID_SW_TRIGGER_RESERVED_37	180
+#define MD_IRQID_SW_TRIGGER_RESERVED_38	181
+#define MD_IRQID_SW_TRIGGER_RESERVED_39	182
+#define MD_IRQID_SW_TRIGGER_RESERVED_40	183
+#define MD_IRQID_SW_TRIGGER_RESERVED_41	184
+#define MD_IRQID_SW_TRIGGER_RESERVED_42	185
+#define MD_IRQID_SW_TRIGGER_RESERVED_43	186
+#define MD_IRQID_SW_TRIGGER_RESERVED_44	187
+#define MD_IRQID_SW_TRIGGER_RESERVED_45	188
+#define MD_IRQID_SW_TRIGGER_RESERVED_46	189
+#define MD_IRQID_SW_TRIGGER_RESERVED_47	190
+#define MD_IRQID_SW_TRIGGER_RESERVED_48	191
+#define MD_IRQID_SW_TRIGGER_RESERVED_49	192
+#define MD_IRQID_SW_TRIGGER_RESERVED_50	193
+#define MD_IRQID_SW_TRIGGER_RESERVED_51	194
+#define MD_IRQID_SW_TRIGGER_RESERVED_52	195
+#define MD_IRQID_SW_TRIGGER_RESERVED_53	196
+#define MD_IRQID_SW_TRIGGER_RESERVED_54	197
+#define MD_IRQID_SW_TRIGGER_RESERVED_55	198
+#define MD_IRQID_SW_TRIGGER_RESERVED_56	199
+#define MD_IRQID_SW_TRIGGER_RESERVED_57	200
+#define MD_IRQID_SW_TRIGGER_RESERVED_58	201
+#define MD_IRQID_SW_TRIGGER_RESERVED_59	202
+#define MD_IRQID_SW_TRIGGER_RESERVED_60	203
+#define MD_IRQID_SW_TRIGGER_RESERVED_61	204
+#define MD_IRQID_SW_TRIGGER_RESERVED_62	205
+#define MD_IRQID_SW_TRIGGER_RESERVED_63	206
+#define MD_IRQID_MCU_BUS_DECERR	207
+#define MD_IRQID_GIC0_FDCInt	208
+#define MD_IRQID_GIC0_FDCInt_1	209
+#define MD_IRQID_GIC0_PCInt	210
+#define MD_IRQID_GIC0_PCInt_1	211
+#define MD_IRQID_GIC0_TimerInt	212
+#define MD_IRQID_GIC0_TimerInt_1	213
+#define MD_IRQID_GIC1_FDCInt	214
+#define MD_IRQID_GIC1_FDCInt_1	215
+#define MD_IRQID_GIC1_PCInt	216
+#define MD_IRQID_GIC1_PCInt_1	217
+#define MD_IRQID_GIC1_TimerInt	218
+#define MD_IRQID_GIC1_TimerInt_1	219
+#define MD_IRQID_EINT3      	220
+#define MD_IRQID_MCUMMU_INT	221
+#define MD_IRQID_IA_DECERR	222
+#define MD_IRQID_RMPU_CTIREIGIN	223
+#define MD_IRQID_MDSM_CORE_PWR_CTRL	224
+#define MD_IRQID_AP2MD_MSDC0	225
+
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_SI_INT 5
+#define VPE_IRQID_CSC 6
+#define VPE_IRQID_END 7
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6765_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6771.h b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6771.h
new file mode 100644
index 0000000..32bcbb4
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/irqid_MT6771.h
@@ -0,0 +1,245 @@
+#ifndef __MT6771_IRQID_H__
+#define __MT6771_IRQID_H__
+
+
+#define MD_IRQID_SHARE_D12MINT1	0
+#define MD_IRQID_IRDBG_MCU_INT	1
+#define MD_IRQID_TDMA_CTIRQ1	2
+#define MD_IRQID_TDMA_CTIRQ2	3
+#define MD_IRQID_TDMA_CTIRQ3	4
+#define MD_IRQID_CSSYS_FDD_CS_IRQ	5
+#define MD_IRQID_CSSYS_TDD_CS_IRQ	6
+#define MD_IRQID_CSSYS_LTE_CS_IRQ	7
+#define MD_IRQID_CSSYS_1X_CS_IRQ	8
+#define MD_IRQID_CSSYS_DO_CS_IRQ	9
+#define MD_IRQID_MDWDT        	10
+#define MD_IRQID_UART_MD0    	11
+#define MD_IRQID_UART_MD1    	12
+#define MD_IRQID_OST          	13
+#define MD_IRQID_USIM0       	14
+#define MD_IRQID_USIM1       	15
+#define MD_IRQID_TOPSM       	16
+#define MD_IRQID_MDGDMA0     	17
+#define MD_IRQID_MDGDMA1     	18
+#define MD_IRQID_MDGDMA2     	19
+#define MD_IRQID_MDGDMA3     	20
+#define MD_IRQID_EINT0       	21
+#define MD_IRQID_EINT1       	22
+#define MD_IRQID_EINT2       	23
+#define MD_IRQID_EINT_SHARE  	24
+#define MD_IRQID_BUS_ERR     	25
+#define MD_IRQID_TXBRP0	26
+#define MD_IRQID_TXBRP1	27
+#define MD_IRQID_TXCRP	28
+#define MD_IRQ_ID_MML2_HRT	29
+#define MD_IRQ_ID_MML2_NOTIF	30
+#define MD_IRQ_ID_MML2_EXCEP	31
+#define MD_IRQID_DEM_TRIG_PS_INT_LE	32
+#define MD_IRQID_ECT          	33
+#define MD_IRQID_PTP_THERM_INT_INT	34
+#define MD_IRQID_CLDMA        	35
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS	36
+#define MD_IRQID_ELM_DMA_IRQ	37
+#define MD_IRQID_SOE         	38
+#define MD_IRQID_ULSP_LOG_MD_INT	39
+#define MD_IRQID_ULSP_LOG_DSP_INT	40
+#define MD_IRQID_USIP0_0	41
+#define MD_IRQID_USIP1_0	42
+#define MD_IRQID_USIP2_0	43
+#define MD_IRQID_USIP3_0	44
+#define MD_IRQID_USIP0_1	45
+#define MD_IRQID_USIP1_1	46
+#define MD_IRQID_AP2MD_CCIF2_0	47
+#define MD_IRQID_USIP3_1	48
+#define MD_IRQID_SI_CM_ERR	49
+#define MD_IRQID_ABM_INT	50
+#define MD_IRQID_ABM_ERROR_INT	51
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS	52
+#define MD_IRQID_ELMTOP_EMI_IRQ	53
+#define MD_IRQID_PPPHA_ENC0_INT	54
+#define MD_IRQID_PPPHA_ENC1_INT	55
+#define MD_IRQID_PPPHA_DEC0_INT	56
+#define MD_IRQID_PPPHA_DEC1_INT	57
+#define MD_IRQID_PTP_FSM_INT	58
+#define MD_IRQID_PTP_SLPCTL_EVENT	59
+#define MD_IRQID_IEBIT_CHECK_IRQ0	60
+#define MD_IRQID_IEBIT_CHECK_IRQ1	61
+#define MD_IRQID_IEBIT_CHECK_IRQ2	62
+#define MD_IRQID_IEBIT_CHECK_IRQ3	63
+#define MD_IRQID_MDCIRQ_WDT0	64
+#define MD_IRQID_MDCIRQ_WDT1	65
+#define MD_IRQID_TRACE_INT	66
+#define MD_IRQID_SI_CM_PCINT	67
+#define MD_IRQID_PLL_GEARHP_RDY	68
+#define MD_IRQID_DCXO_RDY_WO_ACK_IRQ	69
+#define MD_IRQID_REQ_ABNORM_IRQ	70
+#define MD_IRQID_TOP_PLL_DSNS_IRQ	71
+#define MD_IRQID_BT_CVSD	72
+#define MD_IRQID_SSUSB_USB_MCU	73
+#define MD_IRQID_SSUSB_DEV	74
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM	75
+#define MD_IRQID_AP2MD_CCIF0_0	76
+#define MD_IRQID_AP2MD_CCIF0_1	77
+#define MD_IRQID_AP2MD_CCIF1_0	78
+#define MD_IRQID_AP2MD_CCIF1_1	79
+#define MD_IRQID_RXDFE_RXK_READBACK	80
+#define MD_IRQID_BR_DMA_IRQ	81
+#define MD_IRQID_IDC_PM_INT	82
+#define MD_IRQID_IDC_UART_IRQ	83
+#define MD_IRQID_MDRTT	84
+#define MD_IRQID_MDEVDO	85
+#define MD_IRQID_MDM2C_U3G	86
+#define MD_IRQID_MDDFE_DUMP	87
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0	88
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1	89
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ	90
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ	91
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ	92
+#define MD_IRQID_BIGRAM_IRQ	93
+#define MD_IRQID_BR_BDGE_IRQ	94
+#define MD_IRQID_L1_LTE_SLEEP_IRQ	95
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0	96
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1	97
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0	98
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1	99
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2	100
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3	101
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4	102
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5	103
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6	104
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7	105
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ	106
+#define MD_IRQID_MDL1_TOPSM_IRQ	107
+#define MD_IRQID_TDD_WAKEUP_IRQ	108
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ	109
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ	110
+#define MD_IRQID_RTR_FRAME_IRQ	111
+#define MD_IRQID_RTR_SLT_0_IRQ	112
+#define MD_IRQID_RTR_SLT_1_IRQ	113
+#define MD_IRQID_FDD_SLP_IRQ	114
+#define MD_IRQID_TDMA_WAKEUP_IRQ	115
+#define MD_IRQID_MD_DVFS_CTRL_IRQ	116
+#define MD_IRQID_BSI_MM_I_IRQ_RFIC	117
+#define MD_IRQID_BSI_MM_I_IRQ_MIPI	118
+#define MD_IRQID_ST1X_CPINT	119
+#define MD_IRQID_ST1x_HALF_CPINT	120
+#define MD_IRQID_ST1x_CFG_CPINT	121
+#define MD_IRQID_ST1x_WAKEUP_IRQ	122
+#define MD_IRQID_STDO_CPINT	123
+#define MD_IRQID_STDO_HALF_CPINT	124
+#define MD_IRQID_STDO_CFG_CPINT	125
+#define MD_IRQID_STDO_WAKEUP_IRQ	126
+#define MD_IRQID_FREQM_IRQ	127
+#define MD_IRQID_SPM2MD_DVFS_MDPERISYS	128
+#define MD_IRQID_TXDFE_BB_IRQ	129
+#define MD_IRQID_PCC_TOP_FULL_IRQ	130
+#define MD_IRQID_GPTM1        	131
+#define MD_IRQID_GPTM2        	132
+#define MD_IRQID_GPTM3        	133
+#define MD_IRQID_GPTM4        	134
+#define MD_IRQID_GPTM5       	135
+#define MD_IRQID_GPTM6       	136
+#define MD_IRQID_GPTM7       	137
+#define MD_IRQID_GPTM8      	138
+#define MD_IRQID_GPTM9        	139
+#define MD_IRQID_GPTM10        	140
+#define MD_IRQID_GPTM11      	141
+#define MD_IRQID_BUSMPU_IRQ	142
+#define MD_IRQID_SW_TRIGGER_RESERVED_0	143
+#define MD_IRQID_SW_TRIGGER_RESERVED_1	144
+#define MD_IRQID_SW_TRIGGER_RESERVED_2	145
+#define MD_IRQID_SW_TRIGGER_RESERVED_3	146
+#define MD_IRQID_SW_TRIGGER_RESERVED_4	147
+#define MD_IRQID_SW_TRIGGER_RESERVED_5	148
+#define MD_IRQID_SW_TRIGGER_RESERVED_6	149
+#define MD_IRQID_SW_TRIGGER_RESERVED_7	150
+#define MD_IRQID_SW_TRIGGER_RESERVED_8	151
+#define MD_IRQID_SW_TRIGGER_RESERVED_9	152
+#define MD_IRQID_SW_TRIGGER_RESERVED_10	153
+#define MD_IRQID_SW_TRIGGER_RESERVED_11	154
+#define MD_IRQID_SW_TRIGGER_RESERVED_12	155
+#define MD_IRQID_SW_TRIGGER_RESERVED_13	156
+#define MD_IRQID_SW_TRIGGER_RESERVED_14	157
+#define MD_IRQID_SW_TRIGGER_RESERVED_15	158
+#define MD_IRQID_SW_TRIGGER_RESERVED_16	159
+#define MD_IRQID_SW_TRIGGER_RESERVED_17	160
+#define MD_IRQID_SW_TRIGGER_RESERVED_18	161
+#define MD_IRQID_SW_TRIGGER_RESERVED_19	162
+#define MD_IRQID_SW_TRIGGER_RESERVED_20	163
+#define MD_IRQID_SW_TRIGGER_RESERVED_21	164
+#define MD_IRQID_SW_TRIGGER_RESERVED_22	165
+#define MD_IRQID_SW_TRIGGER_RESERVED_23	166
+#define MD_IRQID_SW_TRIGGER_RESERVED_24	167
+#define MD_IRQID_SW_TRIGGER_RESERVED_25	168
+#define MD_IRQID_SW_TRIGGER_RESERVED_26	169
+#define MD_IRQID_SW_TRIGGER_RESERVED_27	170
+#define MD_IRQID_SW_TRIGGER_RESERVED_28	171
+#define MD_IRQID_SW_TRIGGER_RESERVED_29	172
+#define MD_IRQID_SW_TRIGGER_RESERVED_30	173
+#define MD_IRQID_SW_TRIGGER_RESERVED_31	174
+#define MD_IRQID_SW_TRIGGER_RESERVED_32	175
+#define MD_IRQID_SW_TRIGGER_RESERVED_33	176
+#define MD_IRQID_SW_TRIGGER_RESERVED_34	177
+#define MD_IRQID_SW_TRIGGER_RESERVED_35	178
+#define MD_IRQID_SW_TRIGGER_RESERVED_36	179
+#define MD_IRQID_SW_TRIGGER_RESERVED_37	180
+#define MD_IRQID_SW_TRIGGER_RESERVED_38	181
+#define MD_IRQID_SW_TRIGGER_RESERVED_39	182
+#define MD_IRQID_SW_TRIGGER_RESERVED_40	183
+#define MD_IRQID_SW_TRIGGER_RESERVED_41	184
+#define MD_IRQID_SW_TRIGGER_RESERVED_42	185
+#define MD_IRQID_SW_TRIGGER_RESERVED_43	186
+#define MD_IRQID_SW_TRIGGER_RESERVED_44	187
+#define MD_IRQID_SW_TRIGGER_RESERVED_45	188
+#define MD_IRQID_SW_TRIGGER_RESERVED_46	189
+#define MD_IRQID_SW_TRIGGER_RESERVED_47	190
+#define MD_IRQID_SW_TRIGGER_RESERVED_48	191
+#define MD_IRQID_SW_TRIGGER_RESERVED_49	192
+#define MD_IRQID_SW_TRIGGER_RESERVED_50	193
+#define MD_IRQID_SW_TRIGGER_RESERVED_51	194
+#define MD_IRQID_SW_TRIGGER_RESERVED_52	195
+#define MD_IRQID_SW_TRIGGER_RESERVED_53	196
+#define MD_IRQID_SW_TRIGGER_RESERVED_54	197
+#define MD_IRQID_SW_TRIGGER_RESERVED_55	198
+#define MD_IRQID_SW_TRIGGER_RESERVED_56	199
+#define MD_IRQID_SW_TRIGGER_RESERVED_57	200
+#define MD_IRQID_SW_TRIGGER_RESERVED_58	201
+#define MD_IRQID_SW_TRIGGER_RESERVED_59	202
+#define MD_IRQID_SW_TRIGGER_RESERVED_60	203
+#define MD_IRQID_SW_TRIGGER_RESERVED_61	204
+#define MD_IRQID_SW_TRIGGER_RESERVED_62	205
+#define MD_IRQID_SW_TRIGGER_RESERVED_63	206
+#define MD_IRQID_MCU_BUS_DECERR	207
+#define MD_IRQID_GIC0_FDCInt	208
+#define MD_IRQID_GIC0_FDCInt_1	209
+#define MD_IRQID_GIC0_PCInt	210
+#define MD_IRQID_GIC0_PCInt_1	211
+#define MD_IRQID_GIC0_TimerInt	212
+#define MD_IRQID_GIC0_TimerInt_1	213
+#define MD_IRQID_GIC1_FDCInt	214
+#define MD_IRQID_GIC1_FDCInt_1	215
+#define MD_IRQID_GIC1_PCInt	216
+#define MD_IRQID_GIC1_PCInt_1	217
+#define MD_IRQID_GIC1_TimerInt	218
+#define MD_IRQID_GIC1_TimerInt_1	219
+#define MD_IRQID_EINT3      	220
+#define MD_IRQID_MCUMMU_INT	221
+#define MD_IRQID_IA_DECERR	222
+#define MD_IRQID_RMPU_CTIREIGIN	223
+#define MD_IRQID_MDSM_CORE_PWR_CTRL	224
+#define MD_IRQID_AP2MD_MSDC0	225
+
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_SI_INT 5
+#define VPE_IRQID_CSC 6
+#define VPE_IRQID_END 7
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6771_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md93/isrentry.h b/mcu/interface/driver/devdrv/cirq/md93/isrentry.h
new file mode 100644
index 0000000..2a4c711
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md93/isrentry.h
@@ -0,0 +1,192 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   isrentry.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*******************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2001
+*
+*******************************************************************************/
+
+#ifndef _ISRENTRY_H
+#define _ISRENTRY_H
+
+#include "kal_general_types.h"
+
+/*************************************************************************
+ * Define data structures.
+ *************************************************************************/
+
+enum { WKUP_TM_NAME_MAX = 8, WKUP_LOG_BUF_MAX = 100 };
+
+typedef struct 
+{
+   kal_uint32 vector;
+   void (*lisr_handler) (kal_uint32);
+   kal_char *description;
+} irqlisr_entry;
+
+typedef struct errorMenuType
+{
+   kal_uint32 irqMask;
+   kal_uint32 irqStatus;
+   kal_uint32 irqStatus2;
+   kal_uint32 fiqSelect;
+   kal_uint32 fiqControl;
+   kal_uint32 irqReturnAddr;
+   kal_uint32 fiqReturnAddr;
+} IntErrType;
+
+typedef struct wkup_intr_log_struct
+{
+   kal_uint32 irq;
+} wkup_intr_log_t;
+
+typedef struct wkup_intr_timer_struct
+{
+   kal_char *timer_name;
+} wkup_timer_log_t;
+
+
+/*************************************************************************
+ * Define function prototypes.
+ *************************************************************************/
+#define IRQ_Default_LISR MDCIRQ_IRQ_Default_LISR
+
+void MDCIRQ_IRQ_LISR_Init(void);
+void MDCIRQ_IRQ_Default_LISR(void);
+extern kal_int32 get_wkup_intr_log_buf(wkup_intr_log_t **buf, kal_uint32 *indx, kal_uint32 *max);
+extern kal_int32 get_wkup_timer_log_buf(wkup_timer_log_t **buf, kal_uint32 *indx, kal_uint32 *max);
+extern kal_int32 enable_wkup_log(void);
+
+#endif /* _ISRENTRY_H */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl.h
new file mode 100644
index 0000000..dbbfd6c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl.h
@@ -0,0 +1,324 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *   Common type and structure definition for MediaTek GSM/GPRS software
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _INTRCTRL_H
+#define _INTRCTRL_H
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "mips_ia_utils_public.h"
+#include "us_timer.h"
+#include "kal_public_api.h"
+
+#if defined(MT6295M)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6295M.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6295M MDSYS."
+#endif
+#endif
+
+#if defined(MT3967)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT3967.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT3967 MDSYS."
+#endif
+#endif
+
+#if defined(MT6779)
+#if defined(__MIPS_IA__)
+#include "intrCtrl_MT6779.h"
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6779 MDSYS."
+#endif
+#endif
+/*******************************************************************************
+ * Declarations and Definitions
+ *******************************************************************************/
+
+#define EDGE_SENSITIVE           KAL_TRUE
+#define LEVEL_SENSITIVE          KAL_FALSE
+
+#define IRQ_NOT_LISR_CONTEXT     (0xFFFF)
+
+#if defined(__CIRQ_MASK_REG_NR_1_NEW__) || defined(__CIRQ_MASK_REG_NR_2_NEW__) || defined(__CIRQ_MASK_REG_NR_3_NEW__) || defined(__CIRQ_MASK_REG_NR_4_NEW__) || defined(__CIRQ_MASK_REG_NR_5_NEW__)
+#define __CIRQ_DESIGN_NEW__
+#endif
+
+typedef struct CIRQ_MASK_VALUE_STRUCT
+{
+    kal_uint32 irq_mask[8]; 
+} CIRQ_MASK_VALUE_T;
+
+/* To enable SW Trigger Interrupt for new BB chips
+   Need to modify 3 files
+   1. add a file intrCtrl_MTxxxx_SW_Handler.h
+   2. add an entry on intrCtrl_SW_Handler.h
+   3. modify IRQ_SetSWRegister & IRQ_ResetSWRegister to support BB Chips on intrCtrl.c  */
+#if defined(__ENABLE_SW_TRIGGER_INTERRUPT__)
+typedef enum
+{
+#define X_SW_HANDLE_CONST(a, b, c) a=(b),
+#include "intrCtrl_SW_Handle.h"
+#undef X_SW_HANDLE_CONST
+    SW_HANDLE_END
+} SW_CODE_HANDLE;
+
+#define Activate_LISR(code) MDCIRQ_Activate_LISR(code)
+#define Deactivate_LISR(code) MDCIRQ_Deactivate_LISR(code)
+
+extern void MDCIRQ_Activate_LISR(SW_CODE_HANDLE code);
+extern void MDCIRQ_Deactivate_LISR(SW_CODE_HANDLE code);
+extern const kal_uint8 SW_Code_Handle2Code[NUM_IRQ_SOURCES];
+
+/* Use to translate the mapping between software handler to hardware interrupt code */
+#define SW_code_handle2code(a)  (a)
+
+extern kal_uint32 SW_INT_Counter[NUM_IRQ_SOURCES];
+
+#endif /* __ENABLE_SW_TRIGGER_INTERRUPT__ */
+
+
+#define IRQClearInt(vector) MDCIRQ_IRQClearInt(vector)
+#define IRQMask(vector) MDCIRQ_IRQMask(vector)
+#define IRQUnmask(vector) MDCIRQ_IRQUnmask(vector)
+#define IRQSensitivity(vector, e) MDCIRQ_IRQSensitivity(vector, e)
+#define IRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code) MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code)
+
+
+extern kal_uint32 SaveAndSetIRQMask(void);
+extern void RestoreIRQMask(kal_uint32);
+extern void MDCIRQ_IRQClearInt(kal_uint8);
+extern void MDCIRQ_IRQMask(kal_uint8);
+extern void MDCIRQ_IRQUnmask(kal_uint8);
+extern void MDCIRQ_IRQSensitivity(kal_uint8, kal_bool);
+extern void initINTR(void);
+extern kal_uint32 IRQMask_Status(kal_uint8 code);
+extern kal_uint32 IRQ_Status(void);
+extern kal_bool MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(kal_uint32 VPE, kal_uint32 code);
+
+
+#define IRQ_Register_LISR(code, lisr, description) \
+    MDCIRQ_IRQ_Register_LISR(code, (void*)lisr, description)
+extern void MDCIRQ_IRQ_Register_LISR(kal_uint32 code, void (*reg_lisr)(kal_uint32 vector), char* description);
+//extern void IRQ_Register_LISR(kal_uint32 code, void (*reg_lisr)(kal_uint32 vector), char* description);
+
+extern void initVPEIRQ(void);
+
+extern kal_uint32 sst_dhl_irq_count[];
+extern kal_uint32 sst_dhl_irq_caller[];
+extern kal_uint32 DHLIrqCounter[];
+
+extern kal_int32 INC_Initialize_State;
+
+typedef enum
+{
+#define IRQ_PRIORITY_CONST(a) a##_PRIORITY,
+#include "irqPriority.h"
+#undef IRQ_PRIORITY_CONST
+    IRQ_PRIORITY_END,
+    IRQ_NORMAL_DOMAIN_HRT_PRIORITY_THRESHOLD = IRQ_USIP1_1_CODE_PRIORITY + 1,
+} IRQ_PRIORITY;
+
+typedef enum {
+    MDCIRQ_To_BUS_Normal = 0x0,
+    MDCIRQ_To_BUS_PreUltra = 0x1,
+    MDCIRQ_To_BUS_Ultra =0x2,
+} MDCIRQ_Bus_QoS_Signal;
+
+/***********************************
+NOTE:
+1. below API is only for L1 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define IF_DI_OR_LISR()     (Ibit_Status()==0 || kal_if_lisr())
+
+/***********************************
+NOTE:
+1. below API is only for L2 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define __IRQ_LOCK_WITHOUT_CHECK__
+// #define __NESTED_DI_CHECK__
+
+#if defined(__L2_LOGGING_IRQ_LOC__)
+#if defined(__IRQ_LOCK_WITHOUT_CHECK__) && defined(__MIPS_IA__)
+#if defined(__NESTED_DI_CHECK__)
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+    kal_uint32 vpe_num = 0;\
+    miu_mt_dmt();\
+    __asm__ __volatile__\
+    (\
+        "di %0\n\t"\
+        "ehb\n\t"\
+        :"=&r"(oldmask), "=&r"(newmask)\
+        :\
+        :"$31","memory"\
+    );\
+    oldmask &= 0x1;\
+    vpe_num = miu_get_current_vpe_id();\
+    sst_dhl_irq_count[vpe_num]++;\
+    sst_dhl_irq_caller[vpe_num] = (kal_uint32)__builtin_return_address(0);\
+    DHLIrqCounter[vpe_num] = ust_get_current_time();\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+    kal_uint32 tmp=1;\
+    sst_dhl_irq_count[miu_get_current_vpe_id()]--;\
+    __asm__ __volatile__\
+    (\
+        "bne %0, %1, END\n\t"\
+        "ei\n\t"\
+        "ehb\n\t"\
+        "END:emt\n\t"\
+        "ehb\n\t"\
+        :\
+        :"r"(oldmask), "r"(tmp)\
+        :"memory"\
+    );\
+} while(0)
+#else
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+    miu_mt_dmt();\
+    __asm__ __volatile__\
+    (\
+        "di %0\n\t"\
+        "ehb\n\t"\
+        :"=&r"(oldmask), "=&r"(newmask)\
+        :\
+        :"$31","memory"\
+    );\
+    oldmask &= 0x1;\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+    kal_uint32 tmp=1;\
+    __asm__ __volatile__\
+    (\
+        "bne %0, %1, END\n\t"\
+        "ei\n\t"\
+        "ehb\n\t"\
+        "END:emt\n\t"\
+        "ehb\n\t"\
+        :\
+        :"r"(oldmask), "r"(tmp)\
+        :"memory"\
+    );\
+} while(0)
+#endif
+
+#else
+
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{ \
+	oldmask = kal_hrt_SaveAndSetIRQMask(); \
+}while(0);
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{ \
+	kal_hrt_RestoreIRQMask(oldmask); \
+}while(0);
+
+#endif
+#endif
+
+#endif /* _INTRCTRL_H */
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967.h
new file mode 100644
index 0000000..78924fc
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967.h
@@ -0,0 +1,664 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT3967.h
+ *
+ * Project:
+ * --------
+ *   TATAKA
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT3967_H__
+#define __INTRCTRL_MT3967_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+//#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES          (204)
+
+#define    IRQ_SHARE_D12MINT1_CODE                 MD_IRQID_SHARE_D12MINT1
+#define    IRQ_IRDBG_MCU_INT_CODE                  MD_IRQID_IRDBG_MCU_INT
+#define    IRQ_TDMA_CTIRQ1_CODE                    MD_IRQID_TDMA_CTIRQ1
+#define    IRQ_TDMA_CTIRQ2_CODE                    MD_IRQID_TDMA_CTIRQ2
+#define    IRQ_TDMA_CTIRQ3_CODE                    MD_IRQID_TDMA_CTIRQ3
+#define    IRQ_CSSYS_FDD_CS_IRQ_CODE               MD_IRQID_CSSYS_FDD_CS_IRQ
+#define    IRQ_CSSYS_TDD_CS_IRQ_CODE               MD_IRQID_CSSYS_TDD_CS_IRQ
+#define    IRQ_CSSYS_LTE_CS_IRQ_CODE               MD_IRQID_CSSYS_LTE_CS_IRQ
+#define    IRQ_CSSYS_1X_CS_IRQ_CODE                MD_IRQID_CSSYS_1X_CS_IRQ
+#define    IRQ_CSSYS_DO_CS_IRQ_CODE                MD_IRQID_CSSYS_DO_CS_IRQ
+#define    IRQ_MDWDT_CODE                          MD_IRQID_MDWDT        
+#define    IRQ_UART_MD0_CODE                       MD_IRQID_UART_MD0    
+#define    IRQ_UART_MD1_CODE                       MD_IRQID_UART_MD1    
+#define    IRQ_OST_CODE                            MD_IRQID_OST          
+#define    IRQ_USIM0_CODE                          MD_IRQID_USIM0       
+#define    IRQ_USIM1_CODE                          MD_IRQID_USIM1       
+#define    IRQ_MDGDMA0_CODE                        MD_IRQID_MDGDMA0     
+#define    IRQ_MDGDMA1_CODE                        MD_IRQID_MDGDMA1     
+#define    IRQ_MDGDMA2_CODE                        MD_IRQID_MDGDMA2     
+#define    IRQ_MDGDMA3_CODE                        MD_IRQID_MDGDMA3     
+#define    IRQ_EINT0_CODE                          MD_IRQID_EINT0       
+#define    IRQ_EINT1_CODE                          MD_IRQID_EINT1       
+#define    IRQ_EINT2_CODE                          MD_IRQID_EINT2       
+#define    IRQ_EINT_SHARE_CODE                     MD_IRQID_EINT_SHARE  
+#define    IRQ_BUS_ERR_CODE                        MD_IRQID_BUS_ERR     
+#define    IRQ_TXBSRP_CODE                         MD_IRQID_TXBSRP
+#define    IRQ_TXCRP_CODE                          MD_IRQID_TXCRP
+#define    IRQ_MML2_HRT_CODE                      MD_IRQ_ID_MML2_HRT
+#define    IRQ_MML2_NOTIF_CODE                    MD_IRQ_ID_MML2_NOTIF
+#define    IRQ_MML2_EXCEP_CODE                    MD_IRQ_ID_MML2_EXCEP
+#define    IRQ_DEM_TRIG_PS_INT_LE_CODE             MD_IRQID_DEM_TRIG_PS_INT_LE
+#define    IRQ_ECT_CODE                            MD_IRQID_ECT          
+#define    IRQ_PTP_THERM_INT_INT_CODE              MD_IRQID_PTP_THERM_INT_INT
+#define    IRQ_CLDMA_CODE                          MD_IRQID_CLDMA        
+#define    IRQ_MDINFRA_BUSMON_MATCH_STS_CODE       MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define    IRQ_ELM_DMA_IRQ_CODE                    MD_IRQID_ELM_DMA_IRQ
+#define    IRQ_SOE_CODE                            MD_IRQID_SOE         
+#define    IRQ_ULSP_LOG_MD_INT_CODE                MD_IRQID_ULSP_LOG_MD_INT
+#define    IRQ_ULSP_LOG_DSP_INT_CODE               MD_IRQID_ULSP_LOG_DSP_INT
+#define    IRQ_USIP0_0_CODE                        MD_IRQID_USIP0_0
+#define    IRQ_USIP1_0_CODE                        MD_IRQID_USIP1_0
+#define    IRQ_USIP2_0_CODE                        MD_IRQID_USIP2_0
+#define    IRQ_USIP3_0_CODE                        MD_IRQID_USIP3_0
+#define    IRQ_USIP0_1_CODE                        MD_IRQID_USIP0_1
+#define    IRQ_USIP1_1_CODE                        MD_IRQID_USIP1_1
+#define    IRQ_USIP2_1_CODE                        MD_IRQID_USIP2_1
+#define    IRQ_SI_CM_ERR_CODE                      MD_IRQID_SI_CM_ERR
+#define    IRQ_ABM_INT_CODE                        MD_IRQID_ABM_INT
+#define    IRQ_ABM_ERROR_INT_CODE                  MD_IRQID_ABM_ERROR_INT
+#define    IRQ_MDMCU_BUSMON_MATCH_STS_CODE         MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define    IRQ_ELMTOP_EMI_IRQ_CODE                 MD_IRQID_ELMTOP_EMI_IRQ
+#define    IRQ_PPPHA_ENC0_INT_CODE                 MD_IRQID_PPPHA_ENC0_INT
+#define    IRQ_PPPHA_ENC1_INT_CODE                 MD_IRQID_PPPHA_ENC1_INT
+#define    IRQ_PPPHA_DEC0_INT_CODE                 MD_IRQID_PPPHA_DEC0_INT
+#define    IRQ_PPPHA_DEC1_INT_CODE                 MD_IRQID_PPPHA_DEC1_INT
+#define    IRQ_PTP_FSM_INT_CODE                    MD_IRQID_PTP_FSM_INT
+#define    IRQ_IEBIT_CHECK_IRQ0_CODE               MD_IRQID_IEBIT_CHECK_IRQ0
+#define    IRQ_IEBIT_CHECK_IRQ1_CODE               MD_IRQID_IEBIT_CHECK_IRQ1
+#define    IRQ_IEBIT_CHECK_IRQ2_CODE               MD_IRQID_IEBIT_CHECK_IRQ2
+#define    IRQ_IEBIT_CHECK_IRQ3_CODE               MD_IRQID_IEBIT_CHECK_IRQ3
+#define    IRQ_IEBIT_CHECK_IRQ4_CODE               MD_IRQID_IEBIT_CHECK_IRQ4
+#define    IRQ_IEBIT_CHECK_IRQ5_CODE               MD_IRQID_IEBIT_CHECK_IRQ5
+#define    IRQ_TRACE_INT_CODE                      MD_IRQID_TRACE_INT
+#define    IRQ_SI_CM_PCINT_CODE                    MD_IRQID_SI_CM_PCINT
+#define    IRQ_PLL_GEARHP_RDY_CODE                 MD_IRQID_PLL_GEARHP_RDY
+#define    IRQ_MD_BUCK_CTRL_IRQ_CODE               MD_IRQID_MD_BUCK_CTRL_IRQ
+#define    IRQ_REQ_ABNORM_IRQ_CODE                 MD_IRQID_REQ_ABNORM_IRQ
+#define    IRQ_EINT3_CODE                          MD_IRQID_EINT3
+#define    IRQ_BT_CVSD_CODE                        MD_IRQID_BT_CVSD
+#define    IRQ_SSUSB_DEV_CODE                      MD_IRQID_SSUSB_DEV
+#define    IRQ_USB_MCU_CODE                        MD_IRQID_USB_MCU
+#define    IRQ_AP2MD_DVFS_BLOCK_ELM_CODE           MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define    IRQ_AP2MD_CCIF0_0_CODE                  MD_IRQID_AP2MD_CCIF0_0
+#define    IRQ_AP2MD_CCIF0_1_CODE                  MD_IRQID_AP2MD_CCIF0_1
+#define    IRQ_AP2MD_CCIF1_0_CODE                  MD_IRQID_AP2MD_CCIF1_0
+#define    IRQ_AP2MD_CCIF1_1_CODE                  MD_IRQID_AP2MD_CCIF1_1
+#define    IRQ_RXDFE_RXK_READBACK_CODE             MD_IRQID_RXDFE_RXK_READBACK
+#define    IRQ_IDC_PM_INT_CODE                     MD_IRQID_IDC_PM_INT
+#define    IRQ_IDC_UART_IRQ_CODE                   MD_IRQID_IDC_UART_IRQ
+#define    IRQ_MDRTT_CODE                          MD_IRQID_MDRTT
+#define    IRQ_MDEVDO_CODE                         MD_IRQID_MDEVDO
+#define    IRQ_RAKE_CMIF_M2C_IRQ_0_CODE            MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define    IRQ_RAKE_CMIF_M2C_IRQ_1_CODE            MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define    IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE           MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define    IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE           MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define    IRQ_RAKE_CMIF_PD_DO_IRQ_CODE            MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define    IRQ_BIGRAM_IRQ_CODE                     MD_IRQID_BIGRAM_IRQ
+#define    IRQ_BR_BDGE_IRQ_CODE                    MD_IRQID_BR_BDGE_IRQ
+#define    IRQ_L1_LTE_SLEEP_IRQ_CODE               MD_IRQID_L1_LTE_SLEEP_IRQ
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define    IRQ_L1M_PHY_LTMR_IRQ_0_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define    IRQ_L1M_PHY_LTMR_IRQ_1_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define    IRQ_L1M_PHY_LTMR_IRQ_2_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define    IRQ_L1M_PHY_LTMR_IRQ_3_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define    IRQ_L1M_PHY_LTMR_IRQ_4_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define    IRQ_L1M_PHY_LTMR_IRQ_5_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define    IRQ_L1M_PHY_LTMR_IRQ_6_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define    IRQ_L1M_PHY_LTMR_IRQ_7_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define    IRQ_L1_LTE_WAKEUP_IRQ_CODE              MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define    IRQ_TDD_WAKEUP_IRQ_CODE                 MD_IRQID_TDD_WAKEUP_IRQ
+#define    IRQ_TDD_TIMER_L1D_1_IRQ_CODE            MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define    IRQ_TDD_TIMER_L1D_2_IRQ_CODE            MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define    IRQ_RTR_SLT_0_IRQ_CODE                  MD_IRQID_RTR_SLT_0_IRQ
+#define    IRQ_RTR_SLT_1_IRQ_CODE                  MD_IRQID_RTR_SLT_1_IRQ
+#define    IRQ_FDD_SLP_IRQ_CODE                    MD_IRQID_FDD_SLP_IRQ
+#define    IRQ_TDMA_WAKEUP_IRQ_CODE                MD_IRQID_TDMA_WAKEUP_IRQ
+#define    IRQ_ST1X_CPINT_CODE                     MD_IRQID_ST1X_CPINT
+#define    IRQ_ST1x_HALF_CPINT_CODE                MD_IRQID_ST1x_HALF_CPINT
+#define    IRQ_ST1x_CFG_CPINT_CODE                 MD_IRQID_ST1x_CFG_CPINT
+#define    IRQ_ST1x_WAKEUP_IRQ_CODE                MD_IRQID_ST1x_WAKEUP_IRQ
+#define    IRQ_STDO_CPINT_CODE                     MD_IRQID_STDO_CPINT
+#define    IRQ_STDO_HALF_CPINT_CODE                MD_IRQID_STDO_HALF_CPINT
+#define    IRQ_STDO_CFG_CPINT_CODE                 MD_IRQID_STDO_CFG_CPINT
+#define    IRQ_STDO_WAKEUP_IRQ_CODE                MD_IRQID_STDO_WAKEUP_IRQ
+#define    IRQ_FREQM_IRQ_CODE                      MD_IRQID_FREQM_IRQ
+#define    IRQ_MDMCU_DVFS_CTRL_CODE                MD_IRQID_MDMCU_DVFS_CTRL
+#define    IRQ_PCC_TOP_FULL_IRQ_CODE               MD_IRQID_PCC_TOP_FULL_IRQ
+#define    IRQ_GPTM1_CODE                          MD_IRQID_GPTM1        
+#define    IRQ_GPTM2_CODE                          MD_IRQID_GPTM2        
+#define    IRQ_GPTM3_CODE                          MD_IRQID_GPTM3        
+#define    IRQ_GPTM4_CODE                          MD_IRQID_GPTM4        
+#define    IRQ_GPTM5_CODE                          MD_IRQID_GPTM5       
+#define    IRQ_GPTM6_CODE                          MD_IRQID_GPTM6       
+#define    IRQ_GPTM7_CODE                          MD_IRQID_GPTM7       
+#define    IRQ_GPTM8_CODE                          MD_IRQID_GPTM8      
+#define    IRQ_GPTM9_CODE                          MD_IRQID_GPTM9        
+#define    IRQ_GPTM10_CODE                         MD_IRQID_GPTM10        
+#define    IRQ_GPTM11_CODE                         MD_IRQID_GPTM11      
+#define    IRQ_BUSMPU_IRQ_CODE                     MD_IRQID_BUSMPU_IRQ
+#define    IRQ_MCU_BUS_DECERR_CODE                 MD_IRQID_MCU_BUS_DECERR
+#define    IRQ_MCUMMU_INT_CODE                     MD_IRQID_MCUMMU_INT
+#define    IRQ_IA_DECERR_CODE                      MD_IRQID_IA_DECERR
+#define    IRQ_RMPU_CTIREIGIN_CODE                 MD_IRQID_RMPU_CTIREIGIN
+#define    IRQ_AP2MD_MSDC0_CODE                    MD_IRQID_AP2MD_MSDC0
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define    IRQ_AP2MD_CCIF2_CODE                    MD_IRQID_AP2MD_CCIF2
+#define    IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE           MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define    IRQ_SPU_INT_CODE                        MD_IRQID_SPU_INT
+#define    IRQ_SDF_OVERFLOW_IRQ_CODE               MD_IRQID_SDF_OVERFLOW_IRQ
+#define    IRQ_MDDFE_DUMP_CODE                     MD_IRQID_MDDFE_DUMP
+#define    IRQ_AP2MD_CONN_CCIF_0_CODE              MD_IRQID_AP2MD_CONN_CCIF_0
+#define    IRQ_AP2MD_CONN_CCIF_1_CODE              MD_IRQID_AP2MD_CONN_CCIF_1
+#define    IRQ_I2C_TOP_INT_CODE                    MD_IRQID_I2C_TOP_INT
+#define    IRQ_SW_LISR0_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_0
+#define    IRQ_SW_LISR1_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_1
+#define    IRQ_SW_LISR2_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_2
+#define    IRQ_SW_LISR3_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_3
+#define    IRQ_SW_LISR4_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_4
+#define    IRQ_SW_LISR5_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_5
+#define    IRQ_SW_LISR6_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_6
+#define    IRQ_SW_LISR7_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_7
+#define    IRQ_SW_LISR8_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_8
+#define    IRQ_SW_LISR9_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_9
+#define    IRQ_SW_LISR10_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_10
+#define    IRQ_SW_LISR11_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_11
+#define    IRQ_SW_LISR12_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_12
+#define    IRQ_SW_LISR13_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_13
+#define    IRQ_SW_LISR14_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_14
+#define    IRQ_SW_LISR15_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_15
+#define    IRQ_SW_LISR16_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_16
+#define    IRQ_SW_LISR17_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_17
+#define    IRQ_SW_LISR18_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_18
+#define    IRQ_SW_LISR19_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_19
+#define    IRQ_SW_LISR20_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_20
+#define    IRQ_SW_LISR21_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_21
+#define    IRQ_SW_LISR22_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_22
+#define    IRQ_SW_LISR23_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_23
+#define    IRQ_SW_LISR24_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_24
+#define    IRQ_SW_LISR25_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_25
+#define    IRQ_SW_LISR26_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_26
+#define    IRQ_SW_LISR27_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_27
+#define    IRQ_SW_LISR28_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_28
+#define    IRQ_SW_LISR29_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_29
+#define    IRQ_SW_LISR30_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_30
+#define    IRQ_SW_LISR31_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_31
+#define    IRQ_SW_LISR32_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_32
+#define    IRQ_SW_LISR33_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_33
+#define    IRQ_SW_LISR34_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_34
+#define    IRQ_SW_LISR35_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_35
+#define    IRQ_SW_LISR36_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_36
+#define    IRQ_SW_LISR37_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_37
+#define    IRQ_SW_LISR38_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_38
+#define    IRQ_SW_LISR39_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_39
+#define    IRQ_SW_LISR40_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_40
+#define    IRQ_SW_LISR41_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_41
+#define    IRQ_SW_LISR42_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_42
+#define    IRQ_CONN2MD_PDMA_IRQ_CODE               MD_IRQID_CONN2MD_PDMA_IRQ
+#define    IRQ_DUMMY_PRIORITY_CODE_0               MD_IRQID_DUMMY_PRIORITY_IRQ_0
+#define    IRQ_DUMMY_PRIORITY_CODE_1               MD_IRQID_DUMMY_PRIORITY_IRQ_1
+#define    IRQ_DUMMY_PRIORITY_CODE_2               MD_IRQID_DUMMY_PRIORITY_IRQ_2
+#define    IRQ_DUMMY_PRIORITY_CODE_3               MD_IRQID_DUMMY_PRIORITY_IRQ_3
+#define    IRQ_DUMMY_PRIORITY_CODE_4               MD_IRQID_DUMMY_PRIORITY_IRQ_4
+#define    IRQ_DUMMY_PRIORITY_CODE_5               MD_IRQID_DUMMY_PRIORITY_IRQ_5
+#define    IRQ_DUMMY_PRIORITY_CODE_6               MD_IRQID_DUMMY_PRIORITY_IRQ_6
+#define    IRQ_DUMMY_PRIORITY_CODE_7               MD_IRQID_DUMMY_PRIORITY_IRQ_7
+#define    IRQ_DUMMY_PRIORITY_CODE_8               MD_IRQID_DUMMY_PRIORITY_IRQ_8
+#define    IRQ_DUMMY_PRIORITY_CODE_9               MD_IRQID_DUMMY_PRIORITY_IRQ_9
+#define    IRQ_DUMMY_PRIORITY_CODE_10              MD_IRQID_DUMMY_PRIORITY_IRQ_10
+
+/*
+ * Define IRQ selection register assignment
+ */
+#if defined(__ESL_MASE__)
+
+#define INTERRUPT_GROUP_LIST \
+	/*	0 ~  7 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*	8 ~ 15 */  0,  0,  0,  1,  0,  0,  0,  0, \
+	/* 16 ~ 23 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 24 ~ 31 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 32 ~ 39 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 40 ~ 47 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 48 ~ 55 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 56 ~ 63 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 64 ~ 71 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 72 ~ 79 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 80 ~ 87 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 88 ~ 95 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 96 ~103 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*104 ~111 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*112 ~119 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*120 ~127 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*128 ~135 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*136 ~143 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*144 ~151 */  1,  2,  3,  0,  0,  0,  0,  0, \
+	/*152 ~159 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*160 ~167 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*168 ~175 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*176 ~183 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*184 ~191 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*192 ~199 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*200 ~203 */  0,  0,  0,  0,
+#else  /* __ESL_MASE__*/ 
+#define INTERRUPT_GROUP_LIST \
+	/*  0 ~  7 */  1,  6,  1,  1,  1,  1,  1, 11, \
+	/*  8 ~ 15 */  6,  6,  7,  6,  6,  0,  6,  6, \
+	/* 16 ~ 23 */  6,  7,  6,  6,  6,  6,  6,  6, \
+	/* 24 ~ 31 */  7,  1,  6,  6,  6,  6,  6,  7, \
+	/* 32 ~ 39 */  6,  6,  6,  6,  6,  6,  6,  0, \
+	/* 40 ~ 47 */  3,  1,  1, 10, 10,  3,  6,  0, \
+	/* 48 ~ 55 */  0,  6,  6,  6,  6,  6,  6,  6, \
+	/* 56 ~ 63 */  0,  1,  2,  3,  4,  5,  6,  6, \
+	/* 64 ~ 71 */  6,  6,  0,  6,  6,  6,  6,  6, \
+	/* 72 ~ 79 */  6,  7,  6,  6,  1,  6,  6,  6, \
+	/* 80 ~ 87 */  1,  1,  1,  1,  1,  1,  7,  6, \
+	/* 88 ~ 95 */  3,  9, 12,  1,  1,  3,  1,  1, \
+	/* 96 ~103 */  1,  3,  1,  3,  1,  1,  1,  1, \
+	/*104 ~111 */  3,  1,  1,  1,  1,  1,  1,  1, \
+	/*112 ~119 */  1,  1,  1,  0,  6,  6,  6,  6, \
+	/*120 ~127 */  6,  6,  6,  1,  1,  7,  6,  6, \
+	/*128 ~135 */  6,  7,  7,  6,  6,  7,  6, 12, \
+	/*136 ~143 */ 12,  1,  3, 12, 11,  6,  7,  6, \
+	/*144 ~151 */  6,  1,  6,  6,  6,  1,  1,  1, \
+	/*152 ~159 */  3,  1,  3,  1,  1,  1,  1,  1, \
+	/*160 ~167 */  1,  1,  8,  7,  6,  8,  0,  0, \
+	/*168 ~175 */  2,  4,  7,  0,  2,  4,  1,  1, \
+	/*176 ~183 */  6,  6,  1,  6,  6,  6,  6,  0, \
+	/*184 ~191 */  1,  2,  3,  4,  5,  6,  6,  6, \
+	/*192 ~199 */  6,  6,  6,  6,  6,  6,  6,  6, \
+	/*200 ~203 */  6,  6,  6,  6,
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#if defined(__MD95_IS_2CORES__)
+#define INTERRUPT_GROUP_M2V_LIST \
+	/* Group0(0) */                0x3E, \
+	/* Group1(1) */                0x3D, \
+	/* Group2(2) */                0x3B, \
+	/* Group3(3) */                0x37, \
+	/* Group4 */                   0x3F, \
+	/* Group5 */                   0x3F, \
+	/* Group6(0,2) */              0x3A, \
+	/* Group7(0,1,2,3) */          0x30, \
+	/* Group8(1,3) */              0x35, \
+	/* Group9(0,1,2,3) */          0x30, \
+	/* Group10(2,3) */             0x33, \
+	/* Group11(0,2) */             0x3A, \
+	/* Group12(0,2,3) */           0x32, \
+	/* Group13 */                  0x3F, \
+	/* Group14 */                  0x3F, \
+	/* Group15 */                  0x3F,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+	/* Group0(0) */                0x3E, \
+	/* Group1(1) */                0x3D, \
+	/* Group2(2) */                0x3B, \
+	/* Group3(3) */                0x37, \
+	/* Group4(4) */                0x2F, \
+	/* Group5(5) */                0x1F, \
+	/* Group6(0,2,4) */            0x2A, \
+	/* Group7(0,1,2,3,4,5) */      0x00, \
+	/* Group8(1,3) */              0x35, \
+	/* Group9(0,1,2,3) */          0x30, \
+	/* Group10(2,3) */             0x33, \
+	/* Group11(0,2) */             0x3A, \
+	/* Group12(0,2,3) */           0x32, \
+	/* Group13 */                  0x3F, \
+	/* Group14 */                  0x3F, \
+	/* Group15 */                  0x3F,
+#endif
+#endif
+
+#define INTERRUPT_BROADCAST_TYPE \
+	/*  0 ~  7 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*  8 ~ 15 */  0,  0,  1,  0,  0,  0,  0,  0, \
+	/* 16 ~ 23 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 24 ~ 31 */  1,  0,  0,  0,  0,  0,  0,  1, \
+	/* 32 ~ 39 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 40 ~ 47 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 48 ~ 55 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 56 ~ 63 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 64 ~ 71 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 72 ~ 79 */  0,  1,  0,  0,  0,  0,  0,  0, \
+	/* 80 ~ 87 */  0,  0,  0,  0,  0,  0,  1,  0, \
+	/* 88 ~ 95 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 96 ~103 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*104 ~111 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*112 ~119 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*120 ~127 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*128 ~135 */  0,  1,  1,  0,  0,  0,  0,  0, \
+	/*136 ~143 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*144 ~151 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*152 ~159 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*160 ~167 */  0,  0,  1,  1,  0,  0,  0,  0, \
+	/*168 ~175 */  0,  0,  1,  0,  0,  0,  0,  0, \
+	/*176 ~183 */  1,  0,  0,  1,  0,  0,  0,  0, \
+	/*184 ~191 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*192 ~199 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*200 ~204 */  0,  0,  0,  0,
+
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+    VPE_STATUS_LISR_HIGHEST      = 0,
+    VPE_STATUS_LISR_LOWEST       = 204,
+    VPE_STATUS_HISR_TASK_HIGHEST = 256,
+    VPE_STATUS_HISR_TASK_LOWEST  = 511, 
+    VPE_STATUS_END               = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+    IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+    IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+    IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+    IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+    IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+    IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+    IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+    IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+    IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+    IRQ_MDWDT = IRQ_MDWDT_CODE,
+    IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+    IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+    IRQ_OST = IRQ_OST_CODE,
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+    IRQ_USIM1 = IRQ_USIM1_CODE,
+    IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+    IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+    IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+    IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+    IRQ_EINT0 = IRQ_EINT0_CODE,
+    IRQ_EINT1 = IRQ_EINT1_CODE,
+    IRQ_EINT2 = IRQ_EINT2_CODE,
+    IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+    IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+    IRQ_TXBSRP = IRQ_TXBSRP_CODE,
+    IRQ_TXCRP = IRQ_TXCRP_CODE,
+    IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+    IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+    IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+    IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+    IRQ_ECT = IRQ_ECT_CODE,
+    IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+    IRQ_CLDMA = IRQ_CLDMA_CODE,
+    IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+    IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+    IRQ_SOE = IRQ_SOE_CODE,
+    IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+    IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+    IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+    IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+    IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+    IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+    IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+    IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+    IRQ_USIP2_1 = IRQ_USIP2_1_CODE,
+    IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+    IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+    IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+    IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+    IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+    IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+    IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+    IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+    IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+    IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+    IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+    IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+    IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+    IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+    IRQ_IEBIT_CHECK_IRQ4 = IRQ_IEBIT_CHECK_IRQ4_CODE,
+    IRQ_IEBIT_CHECK_IRQ5 = IRQ_IEBIT_CHECK_IRQ5_CODE,
+    IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+    IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+    IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+    IRQ_MD_BUCK_CTRL_IRQ = IRQ_MD_BUCK_CTRL_IRQ_CODE,
+    IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+    IRQ_EINT3 = IRQ_EINT3_CODE,
+    IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+    IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+    IRQ_USB_MCU = IRQ_USB_MCU_CODE,
+    IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+    IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+    IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+    IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+    IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+    IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+    IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+    IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+    IRQ_MDRTT = IRQ_MDRTT_CODE,
+    IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+    IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+    IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+    IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+    IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+    IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+    IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+    IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+    IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+    IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+    IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+    IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+    IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+    IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+    IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+    IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+    IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+    IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+    IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+    IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+    IRQ_MDMCU_DVFS_CTRL = IRQ_MDMCU_DVFS_CTRL_CODE,
+    IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+    IRQ_GPTM1 = IRQ_GPTM1_CODE,
+    IRQ_GPTM2 = IRQ_GPTM2_CODE,
+    IRQ_GPTM3 = IRQ_GPTM3_CODE,
+    IRQ_GPTM4 = IRQ_GPTM4_CODE,
+    IRQ_GPTM5 = IRQ_GPTM5_CODE,
+    IRQ_GPTM6 = IRQ_GPTM6_CODE,
+    IRQ_GPTM7 = IRQ_GPTM7_CODE,
+    IRQ_GPTM8 = IRQ_GPTM8_CODE,
+    IRQ_GPTM9 = IRQ_GPTM9_CODE,
+    IRQ_GPTM10 = IRQ_GPTM10_CODE,
+    IRQ_GPTM11 = IRQ_GPTM11_CODE,
+    IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+    IRQ_MCU_BUS_DECERR = IRQ_MCU_BUS_DECERR_CODE,
+    IRQ_MCUMMU_INT = IRQ_MCUMMU_INT_CODE,
+    IRQ_IA_DECERR = IRQ_IA_DECERR_CODE,
+    IRQ_RMPU_CTIREIGIN = IRQ_RMPU_CTIREIGIN_CODE,
+    IRQ_AP2MD_MSDC0 = IRQ_AP2MD_MSDC0_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE,
+    IRQ_AP2MD_CCIF2 = IRQ_AP2MD_CCIF2_CODE,
+    IRQ_L1M_PHY_LTMR_SPU_IRQ = IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE,
+    IRQ_SPU_INT = IRQ_SPU_INT_CODE,
+    IRQ_SDF_OVERFLOW_IRQ = IRQ_SDF_OVERFLOW_IRQ_CODE,
+    IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+    IRQ_AP2MD_CONN_CCIF_0 = IRQ_AP2MD_CONN_CCIF_0_CODE,
+    IRQ_AP2MD_CONN_CCIF_1 = IRQ_AP2MD_CONN_CCIF_1_CODE,
+    IRQ_I2C_TOP_INT = IRQ_I2C_TOP_INT_CODE,
+    IRQ_SW_LISR0 = IRQ_SW_LISR0_CODE,
+    IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+    IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+    IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+    IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+    IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+    IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+    IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+    IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+    IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+    IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+    IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+    IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+    IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+    IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+    IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+    IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+    IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+    IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+    IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+    IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+    IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+    IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+    IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+    IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+    IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+    IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+    IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+    IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+    IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+    IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+    IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+    IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+    IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+    IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+    IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+    IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+    IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+    IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+    IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+    IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+    IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+    IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+    IRQ_CONN2MD_PDMA_IRQ = IRQ_CONN2MD_PDMA_IRQ_CODE,
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+    GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+#endif /* end of __INTRCTRL_MT3967_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967_SW_Handle.h
new file mode 100644
index 0000000..aa559c4
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT3967_SW_Handle.h
@@ -0,0 +1,254 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT3967_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   MT3967
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 13 2018 jimmy.hung
+ * [MOLY00338569] [Gen95][MDCIRQ][System Service] Update SW IRQ config
+ * For ALPS03983110 Copro power on issue.
+ *
+ * 04 19 2018 yen-chun.liu
+ * [MOLY00321364] [SWLA] Snapshot feature porting
+ * SW IRQ for SWLA.
+ *
+ * 02 21 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * new SWIRQ config for 4G wakeup control.
+ *
+ * 01 12 2018 yen-chun.liu
+ * [MOLY00301743] [Gen95][MDCIRQ][System Service] MDCIRQ driver development
+ * IRQ runtime config API.
+ *
+ * 05 03 2017 yen-chun.liu
+ * [MOLY00246635] [MT6295M][Gen95][System Service][MDCIRQ] Driver development for Gen95 MDCIRQ
+ * modification for interface folder.
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE0 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE1 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE2 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE3 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE4 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE5 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE6 = Zengling Jin
+      SW_TRIGGER_CODE7 = Zengling Jin
+      SW_TRIGGER_CODE8 = Zengling Jin
+      SW_TRIGGER_CODE9 = Cruze Yu
+      SW_TRIGGER_CODE10 = Cruze Yu
+      SW_TRIGGER_CODE11 = Cruze Yu
+      SW_TRIGGER_CODE12 = Cruze Yu
+      SW_TRIGGER_CODE13 = FI Chu, Charles Hsu
+      SW_TRIGGER_CODE14 = Woody Kuo
+      SW_TRIGGER_CODE15 = Carl Kao
+      SW_TRIGGER_CODE16 = Yuni Chang
+      SW_TRIGGER_CODE17 = SY Yeh
+      SW_TRIGGER_CODE18 = Owen Ho
+      SW_TRIGGER_CODE19 = Owen Ho
+      SW_TRIGGER_CODE20 = Owen Ho
+      SW_TRIGGER_CODE21 = Wade Huang
+      SW_TRIGGER_CODE22 = Jun-Ying Huang
+      SW_TRIGGER_CODE23 = Jun-Ying Huang
+      SW_TRIGGER_CODE24 = Jun-Ying Huang
+      SW_TRIGGER_CODE25 = Weimin Zeng
+      SW_TRIGGER_CODE26 = Weimin Zeng
+      SW_TRIGGER_CODE27 = Tee-Yuen Chun
+      SW_TRIGGER_CODE28 = YY Hsieh 
+      SW_TRIGGER_CODE29 = Kevin-KH Liu
+      SW_TRIGGER_CODE30 = HW Jheng
+      SW_TRIGGER_CODE31 = Nicole Hsu
+      SW_TRIGGER_CODE32 = 
+      SW_TRIGGER_CODE33 = 
+      SW_TRIGGER_CODE34 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE35 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE36 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE37 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE38 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE39 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE40 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+      SW_TRIGGER_CODE41 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+      SW_TRIGGER_CODE42 = Jimmy Hung(Reserved for system usage)
+  */
+#if (defined(__MIPS_IA__))
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+#else
+#error "No CPU version select. Need to specify CPU version in project MT3967 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M.h
new file mode 100644
index 0000000..e1b818c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M.h
@@ -0,0 +1,664 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6295M.h
+ *
+ * Project:
+ * --------
+ *   TATAKA
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6295M_H__
+#define __INTRCTRL_MT6295M_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+//#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES          (204)
+
+#define    IRQ_SHARE_D12MINT1_CODE                 MD_IRQID_SHARE_D12MINT1
+#define    IRQ_IRDBG_MCU_INT_CODE                  MD_IRQID_IRDBG_MCU_INT
+#define    IRQ_TDMA_CTIRQ1_CODE                    MD_IRQID_TDMA_CTIRQ1
+#define    IRQ_TDMA_CTIRQ2_CODE                    MD_IRQID_TDMA_CTIRQ2
+#define    IRQ_TDMA_CTIRQ3_CODE                    MD_IRQID_TDMA_CTIRQ3
+#define    IRQ_CSSYS_FDD_CS_IRQ_CODE               MD_IRQID_CSSYS_FDD_CS_IRQ
+#define    IRQ_CSSYS_TDD_CS_IRQ_CODE               MD_IRQID_CSSYS_TDD_CS_IRQ
+#define    IRQ_CSSYS_LTE_CS_IRQ_CODE               MD_IRQID_CSSYS_LTE_CS_IRQ
+#define    IRQ_CSSYS_1X_CS_IRQ_CODE                MD_IRQID_CSSYS_1X_CS_IRQ
+#define    IRQ_CSSYS_DO_CS_IRQ_CODE                MD_IRQID_CSSYS_DO_CS_IRQ
+#define    IRQ_MDWDT_CODE                          MD_IRQID_MDWDT        
+#define    IRQ_UART_MD0_CODE                       MD_IRQID_UART_MD0    
+#define    IRQ_UART_MD1_CODE                       MD_IRQID_UART_MD1    
+#define    IRQ_OST_CODE                            MD_IRQID_OST          
+#define    IRQ_USIM0_CODE                          MD_IRQID_USIM0       
+#define    IRQ_USIM1_CODE                          MD_IRQID_USIM1       
+#define    IRQ_MDGDMA0_CODE                        MD_IRQID_MDGDMA0     
+#define    IRQ_MDGDMA1_CODE                        MD_IRQID_MDGDMA1     
+#define    IRQ_MDGDMA2_CODE                        MD_IRQID_MDGDMA2     
+#define    IRQ_MDGDMA3_CODE                        MD_IRQID_MDGDMA3     
+#define    IRQ_EINT0_CODE                          MD_IRQID_EINT0       
+#define    IRQ_EINT1_CODE                          MD_IRQID_EINT1       
+#define    IRQ_EINT2_CODE                          MD_IRQID_EINT2       
+#define    IRQ_EINT_SHARE_CODE                     MD_IRQID_EINT_SHARE  
+#define    IRQ_BUS_ERR_CODE                        MD_IRQID_BUS_ERR     
+#define    IRQ_TXBSRP_CODE                         MD_IRQID_TXBSRP
+#define    IRQ_TXCRP_CODE                          MD_IRQID_TXCRP
+#define    IRQ_MML2_HRT_CODE                      MD_IRQ_ID_MML2_HRT
+#define    IRQ_MML2_NOTIF_CODE                    MD_IRQ_ID_MML2_NOTIF
+#define    IRQ_MML2_EXCEP_CODE                    MD_IRQ_ID_MML2_EXCEP
+#define    IRQ_DEM_TRIG_PS_INT_LE_CODE             MD_IRQID_DEM_TRIG_PS_INT_LE
+#define    IRQ_ECT_CODE                            MD_IRQID_ECT          
+#define    IRQ_PTP_THERM_INT_INT_CODE              MD_IRQID_PTP_THERM_INT_INT
+#define    IRQ_CLDMA_CODE                          MD_IRQID_CLDMA        
+#define    IRQ_MDINFRA_BUSMON_MATCH_STS_CODE       MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define    IRQ_ELM_DMA_IRQ_CODE                    MD_IRQID_ELM_DMA_IRQ
+#define    IRQ_SOE_CODE                            MD_IRQID_SOE         
+#define    IRQ_ULSP_LOG_MD_INT_CODE                MD_IRQID_ULSP_LOG_MD_INT
+#define    IRQ_ULSP_LOG_DSP_INT_CODE               MD_IRQID_ULSP_LOG_DSP_INT
+#define    IRQ_USIP0_0_CODE                        MD_IRQID_USIP0_0
+#define    IRQ_USIP1_0_CODE                        MD_IRQID_USIP1_0
+#define    IRQ_USIP2_0_CODE                        MD_IRQID_USIP2_0
+#define    IRQ_USIP3_0_CODE                        MD_IRQID_USIP3_0
+#define    IRQ_USIP0_1_CODE                        MD_IRQID_USIP0_1
+#define    IRQ_USIP1_1_CODE                        MD_IRQID_USIP1_1
+#define    IRQ_USIP2_1_CODE                        MD_IRQID_USIP2_1
+#define    IRQ_SI_CM_ERR_CODE                      MD_IRQID_SI_CM_ERR
+#define    IRQ_ABM_INT_CODE                        MD_IRQID_ABM_INT
+#define    IRQ_ABM_ERROR_INT_CODE                  MD_IRQID_ABM_ERROR_INT
+#define    IRQ_MDMCU_BUSMON_MATCH_STS_CODE         MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define    IRQ_ELMTOP_EMI_IRQ_CODE                 MD_IRQID_ELMTOP_EMI_IRQ
+#define    IRQ_PPPHA_ENC0_INT_CODE                 MD_IRQID_PPPHA_ENC0_INT
+#define    IRQ_PPPHA_ENC1_INT_CODE                 MD_IRQID_PPPHA_ENC1_INT
+#define    IRQ_PPPHA_DEC0_INT_CODE                 MD_IRQID_PPPHA_DEC0_INT
+#define    IRQ_PPPHA_DEC1_INT_CODE                 MD_IRQID_PPPHA_DEC1_INT
+#define    IRQ_PTP_FSM_INT_CODE                    MD_IRQID_PTP_FSM_INT
+#define    IRQ_IEBIT_CHECK_IRQ0_CODE               MD_IRQID_IEBIT_CHECK_IRQ0
+#define    IRQ_IEBIT_CHECK_IRQ1_CODE               MD_IRQID_IEBIT_CHECK_IRQ1
+#define    IRQ_IEBIT_CHECK_IRQ2_CODE               MD_IRQID_IEBIT_CHECK_IRQ2
+#define    IRQ_IEBIT_CHECK_IRQ3_CODE               MD_IRQID_IEBIT_CHECK_IRQ3
+#define    IRQ_IEBIT_CHECK_IRQ4_CODE               MD_IRQID_IEBIT_CHECK_IRQ4
+#define    IRQ_IEBIT_CHECK_IRQ5_CODE               MD_IRQID_IEBIT_CHECK_IRQ5
+#define    IRQ_TRACE_INT_CODE                      MD_IRQID_TRACE_INT
+#define    IRQ_SI_CM_PCINT_CODE                    MD_IRQID_SI_CM_PCINT
+#define    IRQ_PLL_GEARHP_RDY_CODE                 MD_IRQID_PLL_GEARHP_RDY
+#define    IRQ_MD_BUCK_CTRL_IRQ_CODE               MD_IRQID_MD_BUCK_CTRL_IRQ
+#define    IRQ_REQ_ABNORM_IRQ_CODE                 MD_IRQID_REQ_ABNORM_IRQ
+#define    IRQ_EINT3_CODE                          MD_IRQID_EINT3
+#define    IRQ_BT_CVSD_CODE                        MD_IRQID_BT_CVSD
+#define    IRQ_SSUSB_DEV_CODE                      MD_IRQID_SSUSB_DEV
+#define    IRQ_USB_MCU_CODE                        MD_IRQID_USB_MCU
+#define    IRQ_AP2MD_DVFS_BLOCK_ELM_CODE           MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define    IRQ_AP2MD_CCIF0_0_CODE                  MD_IRQID_AP2MD_CCIF0_0
+#define    IRQ_AP2MD_CCIF0_1_CODE                  MD_IRQID_AP2MD_CCIF0_1
+#define    IRQ_AP2MD_CCIF1_0_CODE                  MD_IRQID_AP2MD_CCIF1_0
+#define    IRQ_AP2MD_CCIF1_1_CODE                  MD_IRQID_AP2MD_CCIF1_1
+#define    IRQ_RXDFE_RXK_READBACK_CODE             MD_IRQID_RXDFE_RXK_READBACK
+#define    IRQ_IDC_PM_INT_CODE                     MD_IRQID_IDC_PM_INT
+#define    IRQ_IDC_UART_IRQ_CODE                   MD_IRQID_IDC_UART_IRQ
+#define    IRQ_MDRTT_CODE                          MD_IRQID_MDRTT
+#define    IRQ_MDEVDO_CODE                         MD_IRQID_MDEVDO
+#define    IRQ_RAKE_CMIF_M2C_IRQ_0_CODE            MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define    IRQ_RAKE_CMIF_M2C_IRQ_1_CODE            MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define    IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE           MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define    IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE           MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define    IRQ_RAKE_CMIF_PD_DO_IRQ_CODE            MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define    IRQ_BIGRAM_IRQ_CODE                     MD_IRQID_BIGRAM_IRQ
+#define    IRQ_BR_BDGE_IRQ_CODE                    MD_IRQID_BR_BDGE_IRQ
+#define    IRQ_L1_LTE_SLEEP_IRQ_CODE               MD_IRQID_L1_LTE_SLEEP_IRQ
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define    IRQ_L1M_PHY_LTMR_IRQ_0_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define    IRQ_L1M_PHY_LTMR_IRQ_1_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define    IRQ_L1M_PHY_LTMR_IRQ_2_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define    IRQ_L1M_PHY_LTMR_IRQ_3_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define    IRQ_L1M_PHY_LTMR_IRQ_4_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define    IRQ_L1M_PHY_LTMR_IRQ_5_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define    IRQ_L1M_PHY_LTMR_IRQ_6_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define    IRQ_L1M_PHY_LTMR_IRQ_7_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define    IRQ_L1_LTE_WAKEUP_IRQ_CODE              MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define    IRQ_TDD_WAKEUP_IRQ_CODE                 MD_IRQID_TDD_WAKEUP_IRQ
+#define    IRQ_TDD_TIMER_L1D_1_IRQ_CODE            MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define    IRQ_TDD_TIMER_L1D_2_IRQ_CODE            MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define    IRQ_RTR_SLT_0_IRQ_CODE                  MD_IRQID_RTR_SLT_0_IRQ
+#define    IRQ_RTR_SLT_1_IRQ_CODE                  MD_IRQID_RTR_SLT_1_IRQ
+#define    IRQ_FDD_SLP_IRQ_CODE                    MD_IRQID_FDD_SLP_IRQ
+#define    IRQ_TDMA_WAKEUP_IRQ_CODE                MD_IRQID_TDMA_WAKEUP_IRQ
+#define    IRQ_ST1X_CPINT_CODE                     MD_IRQID_ST1X_CPINT
+#define    IRQ_ST1x_HALF_CPINT_CODE                MD_IRQID_ST1x_HALF_CPINT
+#define    IRQ_ST1x_CFG_CPINT_CODE                 MD_IRQID_ST1x_CFG_CPINT
+#define    IRQ_ST1x_WAKEUP_IRQ_CODE                MD_IRQID_ST1x_WAKEUP_IRQ
+#define    IRQ_STDO_CPINT_CODE                     MD_IRQID_STDO_CPINT
+#define    IRQ_STDO_HALF_CPINT_CODE                MD_IRQID_STDO_HALF_CPINT
+#define    IRQ_STDO_CFG_CPINT_CODE                 MD_IRQID_STDO_CFG_CPINT
+#define    IRQ_STDO_WAKEUP_IRQ_CODE                MD_IRQID_STDO_WAKEUP_IRQ
+#define    IRQ_FREQM_IRQ_CODE                      MD_IRQID_FREQM_IRQ
+#define    IRQ_MDMCU_DVFS_CTRL_CODE                MD_IRQID_MDMCU_DVFS_CTRL
+#define    IRQ_PCC_TOP_FULL_IRQ_CODE               MD_IRQID_PCC_TOP_FULL_IRQ
+#define    IRQ_GPTM1_CODE                          MD_IRQID_GPTM1        
+#define    IRQ_GPTM2_CODE                          MD_IRQID_GPTM2        
+#define    IRQ_GPTM3_CODE                          MD_IRQID_GPTM3        
+#define    IRQ_GPTM4_CODE                          MD_IRQID_GPTM4        
+#define    IRQ_GPTM5_CODE                          MD_IRQID_GPTM5       
+#define    IRQ_GPTM6_CODE                          MD_IRQID_GPTM6       
+#define    IRQ_GPTM7_CODE                          MD_IRQID_GPTM7       
+#define    IRQ_GPTM8_CODE                          MD_IRQID_GPTM8      
+#define    IRQ_GPTM9_CODE                          MD_IRQID_GPTM9        
+#define    IRQ_GPTM10_CODE                         MD_IRQID_GPTM10        
+#define    IRQ_GPTM11_CODE                         MD_IRQID_GPTM11      
+#define    IRQ_BUSMPU_IRQ_CODE                     MD_IRQID_BUSMPU_IRQ
+#define    IRQ_MCU_BUS_DECERR_CODE                 MD_IRQID_MCU_BUS_DECERR
+#define    IRQ_MCUMMU_INT_CODE                     MD_IRQID_MCUMMU_INT
+#define    IRQ_IA_DECERR_CODE                      MD_IRQID_IA_DECERR
+#define    IRQ_RMPU_CTIREIGIN_CODE                 MD_IRQID_RMPU_CTIREIGIN
+#define    IRQ_AP2MD_MSDC0_CODE                    MD_IRQID_AP2MD_MSDC0
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define    IRQ_AP2MD_CCIF2_CODE                    MD_IRQID_AP2MD_CCIF2
+#define    IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE           MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define    IRQ_SPU_INT_CODE                        MD_IRQID_SPU_INT
+#define    IRQ_SDF_OVERFLOW_IRQ_CODE               MD_IRQID_SDF_OVERFLOW_IRQ
+#define    IRQ_MDDFE_DUMP_CODE                     MD_IRQID_MDDFE_DUMP
+#define    IRQ_AP2MD_CONN_CCIF_0_CODE              MD_IRQID_AP2MD_CONN_CCIF_0
+#define    IRQ_AP2MD_CONN_CCIF_1_CODE              MD_IRQID_AP2MD_CONN_CCIF_1
+#define    IRQ_I2C_TOP_INT_CODE                    MD_IRQID_I2C_TOP_INT
+#define    IRQ_SW_LISR0_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_0
+#define    IRQ_SW_LISR1_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_1
+#define    IRQ_SW_LISR2_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_2
+#define    IRQ_SW_LISR3_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_3
+#define    IRQ_SW_LISR4_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_4
+#define    IRQ_SW_LISR5_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_5
+#define    IRQ_SW_LISR6_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_6
+#define    IRQ_SW_LISR7_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_7
+#define    IRQ_SW_LISR8_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_8
+#define    IRQ_SW_LISR9_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_9
+#define    IRQ_SW_LISR10_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_10
+#define    IRQ_SW_LISR11_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_11
+#define    IRQ_SW_LISR12_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_12
+#define    IRQ_SW_LISR13_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_13
+#define    IRQ_SW_LISR14_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_14
+#define    IRQ_SW_LISR15_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_15
+#define    IRQ_SW_LISR16_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_16
+#define    IRQ_SW_LISR17_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_17
+#define    IRQ_SW_LISR18_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_18
+#define    IRQ_SW_LISR19_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_19
+#define    IRQ_SW_LISR20_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_20
+#define    IRQ_SW_LISR21_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_21
+#define    IRQ_SW_LISR22_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_22
+#define    IRQ_SW_LISR23_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_23
+#define    IRQ_SW_LISR24_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_24
+#define    IRQ_SW_LISR25_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_25
+#define    IRQ_SW_LISR26_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_26
+#define    IRQ_SW_LISR27_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_27
+#define    IRQ_SW_LISR28_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_28
+#define    IRQ_SW_LISR29_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_29
+#define    IRQ_SW_LISR30_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_30
+#define    IRQ_SW_LISR31_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_31
+#define    IRQ_SW_LISR32_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_32
+#define    IRQ_SW_LISR33_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_33
+#define    IRQ_SW_LISR34_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_34
+#define    IRQ_SW_LISR35_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_35
+#define    IRQ_SW_LISR36_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_36
+#define    IRQ_SW_LISR37_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_37
+#define    IRQ_SW_LISR38_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_38
+#define    IRQ_SW_LISR39_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_39
+#define    IRQ_SW_LISR40_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_40
+#define    IRQ_SW_LISR41_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_41
+#define    IRQ_SW_LISR42_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_42
+#define    IRQ_CONN2MD_PDMA_IRQ_CODE               MD_IRQID_CONN2MD_PDMA_IRQ
+#define    IRQ_DUMMY_PRIORITY_CODE_0               MD_IRQID_DUMMY_PRIORITY_IRQ_0
+#define    IRQ_DUMMY_PRIORITY_CODE_1               MD_IRQID_DUMMY_PRIORITY_IRQ_1
+#define    IRQ_DUMMY_PRIORITY_CODE_2               MD_IRQID_DUMMY_PRIORITY_IRQ_2
+#define    IRQ_DUMMY_PRIORITY_CODE_3               MD_IRQID_DUMMY_PRIORITY_IRQ_3
+#define    IRQ_DUMMY_PRIORITY_CODE_4               MD_IRQID_DUMMY_PRIORITY_IRQ_4
+#define    IRQ_DUMMY_PRIORITY_CODE_5               MD_IRQID_DUMMY_PRIORITY_IRQ_5
+#define    IRQ_DUMMY_PRIORITY_CODE_6               MD_IRQID_DUMMY_PRIORITY_IRQ_6
+#define    IRQ_DUMMY_PRIORITY_CODE_7               MD_IRQID_DUMMY_PRIORITY_IRQ_7
+#define    IRQ_DUMMY_PRIORITY_CODE_8               MD_IRQID_DUMMY_PRIORITY_IRQ_8
+#define    IRQ_DUMMY_PRIORITY_CODE_9               MD_IRQID_DUMMY_PRIORITY_IRQ_9
+#define    IRQ_DUMMY_PRIORITY_CODE_10              MD_IRQID_DUMMY_PRIORITY_IRQ_10
+
+/*
+ * Define IRQ selection register assignment
+ */
+#if defined(__ESL_MASE__)
+
+#define INTERRUPT_GROUP_LIST \
+	/*	0 ~  7 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*	8 ~ 15 */  0,  0,  0,  1,  0,  0,  0,  0, \
+	/* 16 ~ 23 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 24 ~ 31 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 32 ~ 39 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 40 ~ 47 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 48 ~ 55 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 56 ~ 63 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 64 ~ 71 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 72 ~ 79 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 80 ~ 87 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 88 ~ 95 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 96 ~103 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*104 ~111 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*112 ~119 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*120 ~127 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*128 ~135 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*136 ~143 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*144 ~151 */  1,  2,  3,  0,  0,  0,  0,  0, \
+	/*152 ~159 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*160 ~167 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*168 ~175 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*176 ~183 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*184 ~191 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*192 ~199 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*200 ~203 */  0,  0,  0,  0,
+#else  /* __ESL_MASE__*/ 
+#define INTERRUPT_GROUP_LIST \
+	/*  0 ~  7 */  1,  6,  1,  1,  1,  1,  1, 11, \
+	/*  8 ~ 15 */  6,  6,  7,  6,  6,  0,  6,  6, \
+	/* 16 ~ 23 */  6,  7,  6,  6,  6,  6,  6,  6, \
+	/* 24 ~ 31 */  7,  1,  6,  6,  6,  6,  6,  7, \
+	/* 32 ~ 39 */  6,  6,  6,  6,  6,  6,  6,  0, \
+	/* 40 ~ 47 */  3,  1,  1, 10, 10,  3,  6,  0, \
+	/* 48 ~ 55 */  0,  6,  6,  6,  6,  6,  6,  6, \
+	/* 56 ~ 63 */  0,  1,  2,  3,  4,  5,  6,  6, \
+	/* 64 ~ 71 */  6,  6,  0,  6,  6,  6,  6,  6, \
+	/* 72 ~ 79 */  6,  7,  6,  6,  1,  6,  6,  6, \
+	/* 80 ~ 87 */  1,  1,  1,  1,  1,  1,  7,  6, \
+	/* 88 ~ 95 */  3,  9, 12,  1,  1,  3,  1,  1, \
+	/* 96 ~103 */  1,  3,  1,  3,  1,  1,  1,  1, \
+	/*104 ~111 */  3,  1,  1,  1,  1,  1,  1,  1, \
+	/*112 ~119 */  1,  1,  1,  0,  6,  6,  6,  6, \
+	/*120 ~127 */  6,  6,  6,  1,  1,  3,  6,  6, \
+	/*128 ~135 */  6,  7,  7,  6,  6,  7,  6, 12, \
+	/*136 ~143 */ 12,  1,  3, 12, 11,  6,  7,  6, \
+	/*144 ~151 */  6,  1,  6,  6,  6,  1,  1,  1, \
+	/*152 ~159 */  3,  1,  3,  1,  1,  1,  1,  1, \
+	/*160 ~167 */  1,  1,  8,  7,  6,  8,  0,  0, \
+	/*168 ~175 */  2,  4,  7,  0,  2,  4,  1,  1, \
+	/*176 ~183 */  6,  6,  1,  6,  6,  6,  6,  0, \
+	/*184 ~191 */  1,  2,  3,  4,  5,  6,  6,  6, \
+	/*192 ~199 */  6,  6,  6,  6,  6,  6,  6,  6, \
+	/*200 ~203 */  6,  6,  6,  6,
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#if defined(__MD95_IS_2CORES__)
+#define INTERRUPT_GROUP_M2V_LIST \
+	/* Group0(0) */                0x3E, \
+	/* Group1(1) */                0x3D, \
+	/* Group2(2) */                0x3B, \
+	/* Group3(3) */                0x37, \
+	/* Group4 */                   0x3F, \
+	/* Group5 */                   0x3F, \
+	/* Group6(0,2) */              0x3A, \
+	/* Group7(0,1,2,3) */          0x30, \
+	/* Group8(1,3) */              0x35, \
+	/* Group9(0,1,2,3) */          0x30, \
+	/* Group10(2,3) */             0x33, \
+	/* Group11(0,2) */             0x3A, \
+	/* Group12(0,2,3) */           0x32, \
+	/* Group13 */                  0x3F, \
+	/* Group14 */                  0x3F, \
+	/* Group15 */                  0x3F,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+	/* Group0(0) */                0x3E, \
+	/* Group1(1) */                0x3D, \
+	/* Group2(2) */                0x3B, \
+	/* Group3(3) */                0x37, \
+	/* Group4(4) */                0x2F, \
+	/* Group5(5) */                0x1F, \
+	/* Group6(0,2,4) */            0x2A, \
+	/* Group7(0,1,2,3,4,5) */      0x00, \
+	/* Group8(1,3) */              0x35, \
+	/* Group9(0,1,2,3) */          0x30, \
+	/* Group10(2,3) */             0x33, \
+	/* Group11(0,2) */             0x3A, \
+	/* Group12(0,2,3) */           0x32, \
+	/* Group13 */                  0x3F, \
+	/* Group14 */                  0x3F, \
+	/* Group15 */                  0x3F,
+#endif
+#endif
+
+#define INTERRUPT_BROADCAST_TYPE \
+	/*  0 ~  7 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*  8 ~ 15 */  0,  0,  1,  0,  0,  0,  0,  0, \
+	/* 16 ~ 23 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 24 ~ 31 */  1,  0,  0,  0,  0,  0,  0,  1, \
+	/* 32 ~ 39 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 40 ~ 47 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 48 ~ 55 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 56 ~ 63 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 64 ~ 71 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 72 ~ 79 */  0,  1,  0,  0,  0,  0,  0,  0, \
+	/* 80 ~ 87 */  0,  0,  0,  0,  0,  0,  1,  0, \
+	/* 88 ~ 95 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 96 ~103 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*104 ~111 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*112 ~119 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*120 ~127 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*128 ~135 */  0,  1,  1,  0,  0,  0,  0,  0, \
+	/*136 ~143 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*144 ~151 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*152 ~159 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*160 ~167 */  0,  0,  1,  1,  0,  0,  0,  0, \
+	/*168 ~175 */  0,  0,  1,  0,  0,  0,  0,  0, \
+	/*176 ~183 */  1,  0,  0,  1,  0,  0,  0,  0, \
+	/*184 ~191 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*192 ~199 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*200 ~204 */  0,  0,  0,  0,
+
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+    VPE_STATUS_LISR_HIGHEST      = 0,
+    VPE_STATUS_LISR_LOWEST       = 204,
+    VPE_STATUS_HISR_TASK_HIGHEST = 256,
+    VPE_STATUS_HISR_TASK_LOWEST  = 511, 
+    VPE_STATUS_END               = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+    IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+    IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+    IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+    IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+    IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+    IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+    IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+    IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+    IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+    IRQ_MDWDT = IRQ_MDWDT_CODE,
+    IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+    IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+    IRQ_OST = IRQ_OST_CODE,
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+    IRQ_USIM1 = IRQ_USIM1_CODE,
+    IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+    IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+    IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+    IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+    IRQ_EINT0 = IRQ_EINT0_CODE,
+    IRQ_EINT1 = IRQ_EINT1_CODE,
+    IRQ_EINT2 = IRQ_EINT2_CODE,
+    IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+    IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+    IRQ_TXBSRP = IRQ_TXBSRP_CODE,
+    IRQ_TXCRP = IRQ_TXCRP_CODE,
+    IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+    IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+    IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+    IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+    IRQ_ECT = IRQ_ECT_CODE,
+    IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+    IRQ_CLDMA = IRQ_CLDMA_CODE,
+    IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+    IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+    IRQ_SOE = IRQ_SOE_CODE,
+    IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+    IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+    IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+    IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+    IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+    IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+    IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+    IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+    IRQ_USIP2_1 = IRQ_USIP2_1_CODE,
+    IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+    IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+    IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+    IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+    IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+    IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+    IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+    IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+    IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+    IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+    IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+    IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+    IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+    IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+    IRQ_IEBIT_CHECK_IRQ4 = IRQ_IEBIT_CHECK_IRQ4_CODE,
+    IRQ_IEBIT_CHECK_IRQ5 = IRQ_IEBIT_CHECK_IRQ5_CODE,
+    IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+    IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+    IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+    IRQ_MD_BUCK_CTRL_IRQ = IRQ_MD_BUCK_CTRL_IRQ_CODE,
+    IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+    IRQ_EINT3 = IRQ_EINT3_CODE,
+    IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+    IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+    IRQ_USB_MCU = IRQ_USB_MCU_CODE,
+    IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+    IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+    IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+    IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+    IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+    IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+    IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+    IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+    IRQ_MDRTT = IRQ_MDRTT_CODE,
+    IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+    IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+    IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+    IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+    IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+    IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+    IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+    IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+    IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+    IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+    IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+    IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+    IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+    IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+    IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+    IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+    IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+    IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+    IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+    IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+    IRQ_MDMCU_DVFS_CTRL = IRQ_MDMCU_DVFS_CTRL_CODE,
+    IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+    IRQ_GPTM1 = IRQ_GPTM1_CODE,
+    IRQ_GPTM2 = IRQ_GPTM2_CODE,
+    IRQ_GPTM3 = IRQ_GPTM3_CODE,
+    IRQ_GPTM4 = IRQ_GPTM4_CODE,
+    IRQ_GPTM5 = IRQ_GPTM5_CODE,
+    IRQ_GPTM6 = IRQ_GPTM6_CODE,
+    IRQ_GPTM7 = IRQ_GPTM7_CODE,
+    IRQ_GPTM8 = IRQ_GPTM8_CODE,
+    IRQ_GPTM9 = IRQ_GPTM9_CODE,
+    IRQ_GPTM10 = IRQ_GPTM10_CODE,
+    IRQ_GPTM11 = IRQ_GPTM11_CODE,
+    IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+    IRQ_MCU_BUS_DECERR = IRQ_MCU_BUS_DECERR_CODE,
+    IRQ_MCUMMU_INT = IRQ_MCUMMU_INT_CODE,
+    IRQ_IA_DECERR = IRQ_IA_DECERR_CODE,
+    IRQ_RMPU_CTIREIGIN = IRQ_RMPU_CTIREIGIN_CODE,
+    IRQ_AP2MD_MSDC0 = IRQ_AP2MD_MSDC0_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE,
+    IRQ_AP2MD_CCIF2 = IRQ_AP2MD_CCIF2_CODE,
+    IRQ_L1M_PHY_LTMR_SPU_IRQ = IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE,
+    IRQ_SPU_INT = IRQ_SPU_INT_CODE,
+    IRQ_SDF_OVERFLOW_IRQ = IRQ_SDF_OVERFLOW_IRQ_CODE,
+    IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+    IRQ_AP2MD_CONN_CCIF_0 = IRQ_AP2MD_CONN_CCIF_0_CODE,
+    IRQ_AP2MD_CONN_CCIF_1 = IRQ_AP2MD_CONN_CCIF_1_CODE,
+    IRQ_I2C_TOP_INT = IRQ_I2C_TOP_INT_CODE,
+    IRQ_SW_LISR0 = IRQ_SW_LISR0_CODE,
+    IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+    IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+    IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+    IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+    IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+    IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+    IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+    IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+    IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+    IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+    IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+    IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+    IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+    IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+    IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+    IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+    IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+    IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+    IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+    IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+    IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+    IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+    IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+    IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+    IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+    IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+    IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+    IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+    IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+    IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+    IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+    IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+    IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+    IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+    IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+    IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+    IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+    IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+    IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+    IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+    IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+    IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+    IRQ_CONN2MD_PDMA_IRQ = IRQ_CONN2MD_PDMA_IRQ_CODE,
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+    GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+#endif /* end of __INTRCTRL_MT6295M_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M_SW_Handle.h
new file mode 100644
index 0000000..cb89e1e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6295M_SW_Handle.h
@@ -0,0 +1,254 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6295M_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   MT6295M
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 13 2018 jimmy.hung
+ * [MOLY00338569] [Gen95][MDCIRQ][System Service] Update SW IRQ config
+ * For ALPS03983110 Copro power on issue.
+ *
+ * 04 19 2018 yen-chun.liu
+ * [MOLY00321364] [SWLA] Snapshot feature porting
+ * SW IRQ for SWLA.
+ *
+ * 02 21 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * new SWIRQ config for 4G wakeup control.
+ *
+ * 01 12 2018 yen-chun.liu
+ * [MOLY00301743] [Gen95][MDCIRQ][System Service] MDCIRQ driver development
+ * IRQ runtime config API.
+ *
+ * 05 03 2017 yen-chun.liu
+ * [MOLY00246635] [MT6295M][Gen95][System Service][MDCIRQ] Driver development for Gen95 MDCIRQ
+ * modification for interface folder.
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE0 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE1 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE2 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE3 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE4 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE5 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE6 = Zengling Jin
+      SW_TRIGGER_CODE7 = Zengling Jin
+      SW_TRIGGER_CODE8 = Zengling Jin
+      SW_TRIGGER_CODE9 = Cruze Yu
+      SW_TRIGGER_CODE10 = Cruze Yu
+      SW_TRIGGER_CODE11 = Cruze Yu
+      SW_TRIGGER_CODE12 = Cruze Yu
+      SW_TRIGGER_CODE13 = FI Chu, Charles Hsu
+      SW_TRIGGER_CODE14 = Woody Kuo
+      SW_TRIGGER_CODE15 = Carl Kao
+      SW_TRIGGER_CODE16 = Yuni Chang
+      SW_TRIGGER_CODE17 = SY Yeh
+      SW_TRIGGER_CODE18 = Owen Ho
+      SW_TRIGGER_CODE19 = Owen Ho
+      SW_TRIGGER_CODE20 = Owen Ho
+      SW_TRIGGER_CODE21 = Wade Huang
+      SW_TRIGGER_CODE22 = Jun-Ying Huang
+      SW_TRIGGER_CODE23 = Jun-Ying Huang
+      SW_TRIGGER_CODE24 = Jun-Ying Huang
+      SW_TRIGGER_CODE25 = Weimin Zeng
+      SW_TRIGGER_CODE26 = Weimin Zeng
+      SW_TRIGGER_CODE27 = Tee-Yuen Chun
+      SW_TRIGGER_CODE28 = YY Hsieh 
+      SW_TRIGGER_CODE29 = Kevin-KH Liu
+      SW_TRIGGER_CODE30 = HW Jheng
+      SW_TRIGGER_CODE31 = Nicole Hsu
+      SW_TRIGGER_CODE32 = 
+      SW_TRIGGER_CODE33 = 
+      SW_TRIGGER_CODE34 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE35 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE36 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE37 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE38 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE39 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE40 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+      SW_TRIGGER_CODE41 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+      SW_TRIGGER_CODE42 = Jimmy Hung(Reserved for system usage)
+  */
+#if (defined(__MIPS_IA__))
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6295M for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779.h
new file mode 100644
index 0000000..b56a7eb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779.h
@@ -0,0 +1,666 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6779.h
+ *
+ * Project:
+ * --------
+ *   TATAKA
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6779_H__
+#define __INTRCTRL_MT6779_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+//#include "drv_features_gpt.h"
+//#include "drv_mdcirq.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+//#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES          (204)
+
+#define    IRQ_SHARE_D12MINT1_CODE                 MD_IRQID_SHARE_D12MINT1
+#define    IRQ_IRDBG_MCU_INT_CODE                  MD_IRQID_IRDBG_MCU_INT
+#define    IRQ_TDMA_CTIRQ1_CODE                    MD_IRQID_TDMA_CTIRQ1
+#define    IRQ_TDMA_CTIRQ2_CODE                    MD_IRQID_TDMA_CTIRQ2
+#define    IRQ_TDMA_CTIRQ3_CODE                    MD_IRQID_TDMA_CTIRQ3
+#define    IRQ_CSSYS_FDD_CS_IRQ_CODE               MD_IRQID_CSSYS_FDD_CS_IRQ
+#define    IRQ_CSSYS_TDD_CS_IRQ_CODE               MD_IRQID_CSSYS_TDD_CS_IRQ
+#define    IRQ_CSSYS_LTE_CS_IRQ_CODE               MD_IRQID_CSSYS_LTE_CS_IRQ
+#define    IRQ_CSSYS_1X_CS_IRQ_CODE                MD_IRQID_CSSYS_1X_CS_IRQ
+#define    IRQ_CSSYS_DO_CS_IRQ_CODE                MD_IRQID_CSSYS_DO_CS_IRQ
+#define    IRQ_MDWDT_CODE                          MD_IRQID_MDWDT        
+#define    IRQ_UART_MD0_CODE                       MD_IRQID_UART_MD0    
+#define    IRQ_UART_MD1_CODE                       MD_IRQID_UART_MD1    
+#define    IRQ_OST_CODE                            MD_IRQID_OST          
+#define    IRQ_USIM0_CODE                          MD_IRQID_USIM0       
+#define    IRQ_USIM1_CODE                          MD_IRQID_USIM1       
+#define    IRQ_MDGDMA0_CODE                        MD_IRQID_MDGDMA0     
+#define    IRQ_MDGDMA1_CODE                        MD_IRQID_MDGDMA1     
+#define    IRQ_MDGDMA2_CODE                        MD_IRQID_MDGDMA2     
+#define    IRQ_MDGDMA3_CODE                        MD_IRQID_MDGDMA3     
+#define    IRQ_EINT0_CODE                          MD_IRQID_EINT0       
+#define    IRQ_EINT1_CODE                          MD_IRQID_EINT1       
+#define    IRQ_EINT2_CODE                          MD_IRQID_EINT2       
+#define    IRQ_EINT_SHARE_CODE                     MD_IRQID_EINT_SHARE  
+#define    IRQ_BUS_ERR_CODE                        MD_IRQID_BUS_ERR     
+#define    IRQ_TXBSRP_CODE                         MD_IRQID_TXBSRP
+#define    IRQ_TXCRP_CODE                          MD_IRQID_TXCRP
+#define    IRQ_MML2_HRT_CODE                      MD_IRQ_ID_MML2_HRT
+#define    IRQ_MML2_NOTIF_CODE                    MD_IRQ_ID_MML2_NOTIF
+#define    IRQ_MML2_EXCEP_CODE                    MD_IRQ_ID_MML2_EXCEP
+#define    IRQ_DEM_TRIG_PS_INT_LE_CODE             MD_IRQID_DEM_TRIG_PS_INT_LE
+#define    IRQ_ECT_CODE                            MD_IRQID_ECT          
+#define    IRQ_PTP_THERM_INT_INT_CODE              MD_IRQID_PTP_THERM_INT_INT
+#define    IRQ_CLDMA_CODE                          MD_IRQID_CLDMA        
+#define    IRQ_MDINFRA_BUSMON_MATCH_STS_CODE       MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define    IRQ_ELM_DMA_IRQ_CODE                    MD_IRQID_ELM_DMA_IRQ
+#define    IRQ_SOE_CODE                            MD_IRQID_SOE         
+#define    IRQ_ULSP_LOG_MD_INT_CODE                MD_IRQID_ULSP_LOG_MD_INT
+#define    IRQ_ULSP_LOG_DSP_INT_CODE               MD_IRQID_ULSP_LOG_DSP_INT
+#define    IRQ_USIP0_0_CODE                        MD_IRQID_USIP0_0
+#define    IRQ_USIP1_0_CODE                        MD_IRQID_USIP1_0
+#define    IRQ_USIP2_0_CODE                        MD_IRQID_USIP2_0
+#define    IRQ_USIP3_0_CODE                        MD_IRQID_USIP3_0
+#define    IRQ_USIP0_1_CODE                        MD_IRQID_USIP0_1
+#define    IRQ_USIP1_1_CODE                        MD_IRQID_USIP1_1
+#define    IRQ_USIP2_1_CODE                        MD_IRQID_USIP2_1
+#define    IRQ_SI_CM_ERR_CODE                      MD_IRQID_SI_CM_ERR
+#define    IRQ_ABM_INT_CODE                        MD_IRQID_ABM_INT
+#define    IRQ_ABM_ERROR_INT_CODE                  MD_IRQID_ABM_ERROR_INT
+#define    IRQ_MDMCU_BUSMON_MATCH_STS_CODE         MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define    IRQ_ELMTOP_EMI_IRQ_CODE                 MD_IRQID_ELMTOP_EMI_IRQ
+#define    IRQ_PPPHA_ENC0_INT_CODE                 MD_IRQID_PPPHA_ENC0_INT
+#define    IRQ_PPPHA_ENC1_INT_CODE                 MD_IRQID_PPPHA_ENC1_INT
+#define    IRQ_PPPHA_DEC0_INT_CODE                 MD_IRQID_PPPHA_DEC0_INT
+#define    IRQ_PPPHA_DEC1_INT_CODE                 MD_IRQID_PPPHA_DEC1_INT
+#define    IRQ_PTP_FSM_INT_CODE                    MD_IRQID_PTP_FSM_INT
+#define    IRQ_IEBIT_CHECK_IRQ0_CODE               MD_IRQID_IEBIT_CHECK_IRQ0
+#define    IRQ_IEBIT_CHECK_IRQ1_CODE               MD_IRQID_IEBIT_CHECK_IRQ1
+#define    IRQ_IEBIT_CHECK_IRQ2_CODE               MD_IRQID_IEBIT_CHECK_IRQ2
+#define    IRQ_IEBIT_CHECK_IRQ3_CODE               MD_IRQID_IEBIT_CHECK_IRQ3
+#define    IRQ_IEBIT_CHECK_IRQ4_CODE               MD_IRQID_IEBIT_CHECK_IRQ4
+#define    IRQ_IEBIT_CHECK_IRQ5_CODE               MD_IRQID_IEBIT_CHECK_IRQ5
+#define    IRQ_TRACE_INT_CODE                      MD_IRQID_TRACE_INT
+#define    IRQ_SI_CM_PCINT_CODE                    MD_IRQID_SI_CM_PCINT
+#define    IRQ_PLL_GEARHP_RDY_CODE                 MD_IRQID_PLL_GEARHP_RDY
+#define    IRQ_MD_BUCK_CTRL_IRQ_CODE               MD_IRQID_MD_BUCK_CTRL_IRQ
+#define    IRQ_REQ_ABNORM_IRQ_CODE                 MD_IRQID_REQ_ABNORM_IRQ
+#define    IRQ_EINT3_CODE                          MD_IRQID_EINT3
+#define    IRQ_BT_CVSD_CODE                        MD_IRQID_BT_CVSD
+#define    IRQ_SSUSB_DEV_CODE                      MD_IRQID_SSUSB_DEV
+#define    IRQ_USB_MCU_CODE                        MD_IRQID_USB_MCU
+#define    IRQ_AP2MD_DVFS_BLOCK_ELM_CODE           MD_IRQID_AP2MD_DVFS_BLOCK_ELM
+#define    IRQ_AP2MD_CCIF0_0_CODE                  MD_IRQID_AP2MD_CCIF0_0
+#define    IRQ_AP2MD_CCIF0_1_CODE                  MD_IRQID_AP2MD_CCIF0_1
+#define    IRQ_AP2MD_CCIF1_0_CODE                  MD_IRQID_AP2MD_CCIF1_0
+#define    IRQ_AP2MD_CCIF1_1_CODE                  MD_IRQID_AP2MD_CCIF1_1
+#define    IRQ_RXDFE_RXK_READBACK_CODE             MD_IRQID_RXDFE_RXK_READBACK
+#define    IRQ_IDC_PM_INT_CODE                     MD_IRQID_IDC_PM_INT
+#define    IRQ_IDC_UART_IRQ_CODE                   MD_IRQID_IDC_UART_IRQ
+#define    IRQ_MDRTT_CODE                          MD_IRQID_MDRTT
+#define    IRQ_MDEVDO_CODE                         MD_IRQID_MDEVDO
+#define    IRQ_RAKE_CMIF_M2C_IRQ_0_CODE            MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define    IRQ_RAKE_CMIF_M2C_IRQ_1_CODE            MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define    IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE           MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define    IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE           MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define    IRQ_RAKE_CMIF_PD_DO_IRQ_CODE            MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define    IRQ_BIGRAM_IRQ_CODE                     MD_IRQID_BIGRAM_IRQ
+#define    IRQ_BR_BDGE_IRQ_CODE                    MD_IRQID_BR_BDGE_IRQ
+#define    IRQ_L1_LTE_SLEEP_IRQ_CODE               MD_IRQID_L1_LTE_SLEEP_IRQ
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define    IRQ_L1M_PHY_LTMR_IRQ_0_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define    IRQ_L1M_PHY_LTMR_IRQ_1_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define    IRQ_L1M_PHY_LTMR_IRQ_2_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define    IRQ_L1M_PHY_LTMR_IRQ_3_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define    IRQ_L1M_PHY_LTMR_IRQ_4_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define    IRQ_L1M_PHY_LTMR_IRQ_5_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define    IRQ_L1M_PHY_LTMR_IRQ_6_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define    IRQ_L1M_PHY_LTMR_IRQ_7_CODE             MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define    IRQ_L1_LTE_WAKEUP_IRQ_CODE              MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define    IRQ_TDD_WAKEUP_IRQ_CODE                 MD_IRQID_TDD_WAKEUP_IRQ
+#define    IRQ_TDD_TIMER_L1D_1_IRQ_CODE            MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define    IRQ_TDD_TIMER_L1D_2_IRQ_CODE            MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define    IRQ_RTR_SLT_0_IRQ_CODE                  MD_IRQID_RTR_SLT_0_IRQ
+#define    IRQ_RTR_SLT_1_IRQ_CODE                  MD_IRQID_RTR_SLT_1_IRQ
+#define    IRQ_FDD_SLP_IRQ_CODE                    MD_IRQID_FDD_SLP_IRQ
+#define    IRQ_TDMA_WAKEUP_IRQ_CODE                MD_IRQID_TDMA_WAKEUP_IRQ
+#define    IRQ_ST1X_CPINT_CODE                     MD_IRQID_ST1X_CPINT
+#define    IRQ_ST1x_HALF_CPINT_CODE                MD_IRQID_ST1x_HALF_CPINT
+#define    IRQ_ST1x_CFG_CPINT_CODE                 MD_IRQID_ST1x_CFG_CPINT
+#define    IRQ_ST1x_WAKEUP_IRQ_CODE                MD_IRQID_ST1x_WAKEUP_IRQ
+#define    IRQ_STDO_CPINT_CODE                     MD_IRQID_STDO_CPINT
+#define    IRQ_STDO_HALF_CPINT_CODE                MD_IRQID_STDO_HALF_CPINT
+#define    IRQ_STDO_CFG_CPINT_CODE                 MD_IRQID_STDO_CFG_CPINT
+#define    IRQ_STDO_WAKEUP_IRQ_CODE                MD_IRQID_STDO_WAKEUP_IRQ
+#define    IRQ_FREQM_IRQ_CODE                      MD_IRQID_FREQM_IRQ
+#define    IRQ_MDMCU_DVFS_CTRL_CODE                MD_IRQID_MDMCU_DVFS_CTRL
+#define    IRQ_PCC_TOP_FULL_IRQ_CODE               MD_IRQID_PCC_TOP_FULL_IRQ
+#define    IRQ_GPTM1_CODE                          MD_IRQID_GPTM1        
+#define    IRQ_GPTM2_CODE                          MD_IRQID_GPTM2        
+#define    IRQ_GPTM3_CODE                          MD_IRQID_GPTM3        
+#define    IRQ_GPTM4_CODE                          MD_IRQID_GPTM4        
+#define    IRQ_GPTM5_CODE                          MD_IRQID_GPTM5       
+#define    IRQ_GPTM6_CODE                          MD_IRQID_GPTM6       
+#define    IRQ_GPTM7_CODE                          MD_IRQID_GPTM7       
+#define    IRQ_GPTM8_CODE                          MD_IRQID_GPTM8      
+#define    IRQ_GPTM9_CODE                          MD_IRQID_GPTM9        
+#define    IRQ_GPTM10_CODE                         MD_IRQID_GPTM10        
+#define    IRQ_GPTM11_CODE                         MD_IRQID_GPTM11      
+#define    IRQ_BUSMPU_IRQ_CODE                     MD_IRQID_BUSMPU_IRQ
+#define    IRQ_MCU_BUS_DECERR_CODE                 MD_IRQID_MCU_BUS_DECERR
+#define    IRQ_MCUMMU_INT_CODE                     MD_IRQID_MCUMMU_INT
+#define    IRQ_IA_DECERR_CODE                      MD_IRQID_IA_DECERR
+#define    IRQ_RMPU_CTIREIGIN_CODE                 MD_IRQID_RMPU_CTIREIGIN
+#define    IRQ_AP2MD_MSDC0_CODE                    MD_IRQID_AP2MD_MSDC0
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE  MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define    IRQ_AP2MD_CCIF2_CODE                    MD_IRQID_AP2MD_CCIF2
+#define    IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE           MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define    IRQ_SPU_INT_CODE                        MD_IRQID_SPU_INT
+#define    IRQ_SDF_OVERFLOW_IRQ_CODE               MD_IRQID_SDF_OVERFLOW_IRQ
+#define    IRQ_MDDFE_DUMP_CODE                     MD_IRQID_MDDFE_DUMP
+#define    IRQ_AP2MD_CONN_CCIF_0_CODE              MD_IRQID_AP2MD_CONN_CCIF_0
+#define    IRQ_AP2MD_CONN_CCIF_1_CODE              MD_IRQID_AP2MD_CONN_CCIF_1
+#define    IRQ_I2C_TOP_INT_CODE                    MD_IRQID_I2C_TOP_INT
+#define    IRQ_SW_LISR0_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_0
+#define    IRQ_SW_LISR1_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_1
+#define    IRQ_SW_LISR2_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_2
+#define    IRQ_SW_LISR3_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_3
+#define    IRQ_SW_LISR4_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_4
+#define    IRQ_SW_LISR5_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_5
+#define    IRQ_SW_LISR6_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_6
+#define    IRQ_SW_LISR7_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_7
+#define    IRQ_SW_LISR8_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_8
+#define    IRQ_SW_LISR9_CODE                       MD_IRQID_SW_TRIGGER_RESERVED_9
+#define    IRQ_SW_LISR10_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_10
+#define    IRQ_SW_LISR11_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_11
+#define    IRQ_SW_LISR12_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_12
+#define    IRQ_SW_LISR13_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_13
+#define    IRQ_SW_LISR14_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_14
+#define    IRQ_SW_LISR15_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_15
+#define    IRQ_SW_LISR16_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_16
+#define    IRQ_SW_LISR17_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_17
+#define    IRQ_SW_LISR18_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_18
+#define    IRQ_SW_LISR19_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_19
+#define    IRQ_SW_LISR20_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_20
+#define    IRQ_SW_LISR21_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_21
+#define    IRQ_SW_LISR22_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_22
+#define    IRQ_SW_LISR23_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_23
+#define    IRQ_SW_LISR24_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_24
+#define    IRQ_SW_LISR25_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_25
+#define    IRQ_SW_LISR26_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_26
+#define    IRQ_SW_LISR27_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_27
+#define    IRQ_SW_LISR28_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_28
+#define    IRQ_SW_LISR29_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_29
+#define    IRQ_SW_LISR30_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_30
+#define    IRQ_SW_LISR31_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_31
+#define    IRQ_SW_LISR32_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_32
+#define    IRQ_SW_LISR33_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_33
+#define    IRQ_SW_LISR34_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_34
+#define    IRQ_SW_LISR35_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_35
+#define    IRQ_SW_LISR36_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_36
+#define    IRQ_SW_LISR37_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_37
+#define    IRQ_SW_LISR38_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_38
+#define    IRQ_SW_LISR39_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_39
+#define    IRQ_SW_LISR40_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_40
+#define    IRQ_SW_LISR41_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_41
+#define    IRQ_SW_LISR42_CODE                      MD_IRQID_SW_TRIGGER_RESERVED_42
+#define    IRQ_CONN2MD_PDMA_IRQ_CODE               MD_IRQID_CONN2MD_PDMA_IRQ
+#define    IRQ_CONN_BT_ISOCH_CODE                  MD_IRQID_CONN_BT_ISOCH
+#define    IRQ_AP2MD_UFS_CODE                      MD_IRQID_AP2MD_UFS
+#define    IRQ_DUMMY_PRIORITY_CODE_0               MD_IRQID_DUMMY_PRIORITY_IRQ_0
+#define    IRQ_DUMMY_PRIORITY_CODE_1               MD_IRQID_DUMMY_PRIORITY_IRQ_1
+#define    IRQ_DUMMY_PRIORITY_CODE_2               MD_IRQID_DUMMY_PRIORITY_IRQ_2
+#define    IRQ_DUMMY_PRIORITY_CODE_3               MD_IRQID_DUMMY_PRIORITY_IRQ_3
+#define    IRQ_DUMMY_PRIORITY_CODE_4               MD_IRQID_DUMMY_PRIORITY_IRQ_4
+#define    IRQ_DUMMY_PRIORITY_CODE_5               MD_IRQID_DUMMY_PRIORITY_IRQ_5
+#define    IRQ_DUMMY_PRIORITY_CODE_6               MD_IRQID_DUMMY_PRIORITY_IRQ_6
+#define    IRQ_DUMMY_PRIORITY_CODE_7               MD_IRQID_DUMMY_PRIORITY_IRQ_7
+#define    IRQ_DUMMY_PRIORITY_CODE_8               MD_IRQID_DUMMY_PRIORITY_IRQ_8
+
+/*
+ * Define IRQ selection register assignment
+ */
+#if defined(__ESL_MASE__)
+
+#define INTERRUPT_GROUP_LIST \
+	/*	0 ~  7 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*	8 ~ 15 */  0,  0,  0,  1,  0,  0,  0,  0, \
+	/* 16 ~ 23 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 24 ~ 31 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 32 ~ 39 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 40 ~ 47 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 48 ~ 55 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 56 ~ 63 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 64 ~ 71 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 72 ~ 79 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 80 ~ 87 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 88 ~ 95 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 96 ~103 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*104 ~111 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*112 ~119 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*120 ~127 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*128 ~135 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*136 ~143 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*144 ~151 */  1,  2,  3,  0,  0,  0,  0,  0, \
+	/*152 ~159 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*160 ~167 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*168 ~175 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*176 ~183 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*184 ~191 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*192 ~199 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*200 ~203 */  0,  0,  0,  0,
+#else  /* __ESL_MASE__*/ 
+#define INTERRUPT_GROUP_LIST \
+	/*  0 ~  7 */  1,  6,  1,  1,  1,  1,  1, 11, \
+	/*  8 ~ 15 */  6,  6,  7,  6,  6,  0,  6,  6, \
+	/* 16 ~ 23 */  6,  7,  6,  6,  6,  6,  6,  6, \
+	/* 24 ~ 31 */  7,  1,  6,  6,  6,  6,  6,  7, \
+	/* 32 ~ 39 */  6,  6,  6,  6,  6,  6,  6,  0, \
+	/* 40 ~ 47 */  3,  1,  1, 10, 10,  3,  6,  0, \
+	/* 48 ~ 55 */  0,  6,  6,  6,  6,  6,  6,  6, \
+	/* 56 ~ 63 */  0,  1,  2,  3,  4,  5,  6,  6, \
+	/* 64 ~ 71 */  6,  6,  0,  6,  6,  6,  6,  6, \
+	/* 72 ~ 79 */  6,  7,  6,  6,  1,  6,  6,  6, \
+	/* 80 ~ 87 */  1,  1,  1,  1,  1,  1,  7,  6, \
+	/* 88 ~ 95 */  3,  9, 12,  1,  1,  3,  1,  1, \
+	/* 96 ~103 */  1,  3,  1,  3,  1,  1,  1,  1, \
+	/*104 ~111 */  3,  1,  1,  1,  1,  1,  1,  1, \
+	/*112 ~119 */  1,  1,  1,  0,  6,  6,  6,  6, \
+	/*120 ~127 */  6,  6,  6,  1,  1,  7,  6,  6, \
+	/*128 ~135 */  6,  7,  7,  6,  6,  7,  6, 12, \
+	/*136 ~143 */ 12,  1,  3, 12, 11,  6,  7,  6, \
+	/*144 ~151 */  6,  1,  6,  6,  6,  1,  1,  1, \
+	/*152 ~159 */  3,  1,  3,  1,  1,  1,  1,  1, \
+	/*160 ~167 */  1,  1,  8,  7,  6,  8,  0,  0, \
+	/*168 ~175 */  2,  4,  7,  0,  2,  4,  1,  1, \
+	/*176 ~183 */  6,  6,  1,  6,  6,  6,  6,  0, \
+	/*184 ~191 */  1,  2,  3,  4,  5,  6,  6,  6, \
+	/*192 ~199 */  6,  6,  6,  6,  6,  6,  6,  6, \
+	/*200 ~203 */  6,  6,  6,  6,
+#endif /* __ESL_MASE__ */
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD, \
+        0xD, 0xD ,0xD, 0xD, 0xD, 0xD ,0xD, 0xD,
+#else
+#if defined(__MD95_IS_2CORES__)
+#define INTERRUPT_GROUP_M2V_LIST \
+	/* Group0(0) */                0x3E, \
+	/* Group1(1) */                0x3D, \
+	/* Group2(2) */                0x3B, \
+	/* Group3(3) */                0x37, \
+	/* Group4 */                   0x3F, \
+	/* Group5 */                   0x3F, \
+	/* Group6(0,2) */              0x3A, \
+	/* Group7(0,1,2,3) */          0x30, \
+	/* Group8(1,3) */              0x35, \
+	/* Group9(0,1,2,3) */          0x30, \
+	/* Group10(2,3) */             0x33, \
+	/* Group11(0,2) */             0x3A, \
+	/* Group12(0,2,3) */           0x32, \
+	/* Group13 */                  0x3F, \
+	/* Group14 */                  0x3F, \
+	/* Group15 */                  0x3F,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+	/* Group0(0) */                0x3E, \
+	/* Group1(1) */                0x3D, \
+	/* Group2(2) */                0x3B, \
+	/* Group3(3) */                0x37, \
+	/* Group4(4) */                0x2F, \
+	/* Group5(5) */                0x1F, \
+	/* Group6(0,2,4) */            0x2A, \
+	/* Group7(0,1,2,3,4,5) */      0x00, \
+	/* Group8(1,3) */              0x35, \
+	/* Group9(0,1,2,3) */          0x30, \
+	/* Group10(2,3) */             0x33, \
+	/* Group11(0,2) */             0x3A, \
+	/* Group12(0,2,3) */           0x32, \
+	/* Group13 */                  0x3F, \
+	/* Group14 */                  0x3F, \
+	/* Group15 */                  0x3F,
+#endif
+#endif
+
+#define INTERRUPT_BROADCAST_TYPE \
+	/*  0 ~  7 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*  8 ~ 15 */  0,  0,  1,  0,  0,  0,  0,  0, \
+	/* 16 ~ 23 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 24 ~ 31 */  1,  0,  0,  0,  0,  0,  0,  1, \
+	/* 32 ~ 39 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 40 ~ 47 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 48 ~ 55 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 56 ~ 63 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 64 ~ 71 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 72 ~ 79 */  0,  1,  0,  0,  0,  0,  0,  0, \
+	/* 80 ~ 87 */  0,  0,  0,  0,  0,  0,  1,  0, \
+	/* 88 ~ 95 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 96 ~103 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*104 ~111 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*112 ~119 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*120 ~127 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*128 ~135 */  0,  1,  1,  0,  0,  0,  0,  0, \
+	/*136 ~143 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*144 ~151 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*152 ~159 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*160 ~167 */  0,  0,  1,  1,  0,  0,  0,  0, \
+	/*168 ~175 */  0,  0,  1,  0,  0,  0,  0,  0, \
+	/*176 ~183 */  1,  0,  0,  1,  0,  0,  0,  0, \
+	/*184 ~191 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*192 ~199 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*200 ~204 */  0,  0,  0,  0,
+
+
+
+/*******************************************************************************
+ * Special for display on SWDBG - MCU profiling
+ *******************************************************************************/
+#if (MDCIRQ_MAX_ISR_NUM<=256)
+#define __CIRQ_MASK_REG_NR_8_NEW__
+#else
+#error "Unsupport mask number"
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+
+typedef enum
+{
+    VPE_STATUS_LISR_HIGHEST      = 0,
+    VPE_STATUS_LISR_LOWEST       = 204,
+    VPE_STATUS_HISR_TASK_HIGHEST = 256,
+    VPE_STATUS_HISR_TASK_LOWEST  = 511, 
+    VPE_STATUS_END               = 511,
+} VPE_STATUS;
+
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_SHARE_D12MINT1 = IRQ_SHARE_D12MINT1_CODE,
+    IRQ_IRDBG_MCU_INT = IRQ_IRDBG_MCU_INT_CODE,
+    IRQ_TDMA_CTIRQ1 = IRQ_TDMA_CTIRQ1_CODE,
+    IRQ_TDMA_CTIRQ2 = IRQ_TDMA_CTIRQ2_CODE,
+    IRQ_TDMA_CTIRQ3 = IRQ_TDMA_CTIRQ3_CODE,
+    IRQ_CSSYS_FDD_CS_IRQ = IRQ_CSSYS_FDD_CS_IRQ_CODE,
+    IRQ_CSSYS_TDD_CS_IRQ = IRQ_CSSYS_TDD_CS_IRQ_CODE,
+    IRQ_CSSYS_LTE_CS_IRQ = IRQ_CSSYS_LTE_CS_IRQ_CODE,
+    IRQ_CSSYS_1X_CS_IRQ = IRQ_CSSYS_1X_CS_IRQ_CODE,
+    IRQ_CSSYS_DO_CS_IRQ = IRQ_CSSYS_DO_CS_IRQ_CODE,
+    IRQ_MDWDT = IRQ_MDWDT_CODE,
+    IRQ_UART_MD0 = IRQ_UART_MD0_CODE,
+    IRQ_UART_MD1 = IRQ_UART_MD1_CODE,
+    IRQ_OST = IRQ_OST_CODE,
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+    IRQ_USIM1 = IRQ_USIM1_CODE,
+    IRQ_MDGDMA0 = IRQ_MDGDMA0_CODE,
+    IRQ_MDGDMA1 = IRQ_MDGDMA1_CODE,
+    IRQ_MDGDMA2 = IRQ_MDGDMA2_CODE,
+    IRQ_MDGDMA3 = IRQ_MDGDMA3_CODE,
+    IRQ_EINT0 = IRQ_EINT0_CODE,
+    IRQ_EINT1 = IRQ_EINT1_CODE,
+    IRQ_EINT2 = IRQ_EINT2_CODE,
+    IRQ_EINT_SHARE = IRQ_EINT_SHARE_CODE,
+    IRQ_BUS_ERR = IRQ_BUS_ERR_CODE,
+    IRQ_TXBSRP = IRQ_TXBSRP_CODE,
+    IRQ_TXCRP = IRQ_TXCRP_CODE,
+    IRQ_MML2_HRT = IRQ_MML2_HRT_CODE,
+    IRQ_MML2_NOTIF = IRQ_MML2_NOTIF_CODE,
+    IRQ_MML2_EXCEP = IRQ_MML2_EXCEP_CODE,
+    IRQ_DEM_TRIG_PS_INT_LE = IRQ_DEM_TRIG_PS_INT_LE_CODE,
+    IRQ_ECT = IRQ_ECT_CODE,
+    IRQ_PTP_THERM_INT_INT = IRQ_PTP_THERM_INT_INT_CODE,
+    IRQ_CLDMA = IRQ_CLDMA_CODE,
+    IRQ_MDINFRA_BUSMON_MATCH_STS = IRQ_MDINFRA_BUSMON_MATCH_STS_CODE,
+    IRQ_ELM_DMA_IRQ = IRQ_ELM_DMA_IRQ_CODE,
+    IRQ_SOE = IRQ_SOE_CODE,
+    IRQ_ULSP_LOG_MD_INT = IRQ_ULSP_LOG_MD_INT_CODE,
+    IRQ_ULSP_LOG_DSP_INT = IRQ_ULSP_LOG_DSP_INT_CODE,
+    IRQ_USIP0_0 = IRQ_USIP0_0_CODE,
+    IRQ_USIP1_0 = IRQ_USIP1_0_CODE,
+    IRQ_USIP2_0 = IRQ_USIP2_0_CODE,
+    IRQ_USIP3_0 = IRQ_USIP3_0_CODE,
+    IRQ_USIP0_1 = IRQ_USIP0_1_CODE,
+    IRQ_USIP1_1 = IRQ_USIP1_1_CODE,
+    IRQ_USIP2_1 = IRQ_USIP2_1_CODE,
+    IRQ_SI_CM_ERR = IRQ_SI_CM_ERR_CODE,
+    IRQ_ABM_INT = IRQ_ABM_INT_CODE,
+    IRQ_ABM_ERROR_INT = IRQ_ABM_ERROR_INT_CODE,
+    IRQ_MDMCU_BUSMON_MATCH_STS = IRQ_MDMCU_BUSMON_MATCH_STS_CODE,
+    IRQ_ELMTOP_EMI_IRQ = IRQ_ELMTOP_EMI_IRQ_CODE,
+    IRQ_PPPHA_ENC0_INT = IRQ_PPPHA_ENC0_INT_CODE,
+    IRQ_PPPHA_ENC1_INT = IRQ_PPPHA_ENC1_INT_CODE,
+    IRQ_PPPHA_DEC0_INT = IRQ_PPPHA_DEC0_INT_CODE,
+    IRQ_PPPHA_DEC1_INT = IRQ_PPPHA_DEC1_INT_CODE,
+    IRQ_PTP_FSM_INT = IRQ_PTP_FSM_INT_CODE,
+    IRQ_IEBIT_CHECK_IRQ0 = IRQ_IEBIT_CHECK_IRQ0_CODE,
+    IRQ_IEBIT_CHECK_IRQ1 = IRQ_IEBIT_CHECK_IRQ1_CODE,
+    IRQ_IEBIT_CHECK_IRQ2 = IRQ_IEBIT_CHECK_IRQ2_CODE,
+    IRQ_IEBIT_CHECK_IRQ3 = IRQ_IEBIT_CHECK_IRQ3_CODE,
+    IRQ_IEBIT_CHECK_IRQ4 = IRQ_IEBIT_CHECK_IRQ4_CODE,
+    IRQ_IEBIT_CHECK_IRQ5 = IRQ_IEBIT_CHECK_IRQ5_CODE,
+    IRQ_TRACE_INT = IRQ_TRACE_INT_CODE,
+    IRQ_SI_CM_PCINT = IRQ_SI_CM_PCINT_CODE,
+    IRQ_PLL_GEARHP_RDY = IRQ_PLL_GEARHP_RDY_CODE,
+    IRQ_MD_BUCK_CTRL_IRQ = IRQ_MD_BUCK_CTRL_IRQ_CODE,
+    IRQ_REQ_ABNORM_IRQ = IRQ_REQ_ABNORM_IRQ_CODE,
+    IRQ_EINT3 = IRQ_EINT3_CODE,
+    IRQ_BT_CVSD = IRQ_BT_CVSD_CODE,
+    IRQ_SSUSB_DEV = IRQ_SSUSB_DEV_CODE,
+    IRQ_USB_MCU = IRQ_USB_MCU_CODE,
+    IRQ_AP2MD_DVFS_BLOCK_ELM = IRQ_AP2MD_DVFS_BLOCK_ELM_CODE,
+    IRQ_AP2MD_CCIF0_0 = IRQ_AP2MD_CCIF0_0_CODE,
+    IRQ_AP2MD_CCIF0_1 = IRQ_AP2MD_CCIF0_1_CODE,
+    IRQ_AP2MD_CCIF1_0 = IRQ_AP2MD_CCIF1_0_CODE,
+    IRQ_AP2MD_CCIF1_1 = IRQ_AP2MD_CCIF1_1_CODE,
+    IRQ_RXDFE_RXK_READBACK = IRQ_RXDFE_RXK_READBACK_CODE,
+    IRQ_IDC_PM_INT = IRQ_IDC_PM_INT_CODE,
+    IRQ_IDC_UART_IRQ = IRQ_IDC_UART_IRQ_CODE,
+    IRQ_MDRTT = IRQ_MDRTT_CODE,
+    IRQ_MDEVDO = IRQ_MDEVDO_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_0 = IRQ_RAKE_CMIF_M2C_IRQ_0_CODE,
+    IRQ_RAKE_CMIF_M2C_IRQ_1 = IRQ_RAKE_CMIF_M2C_IRQ_1_CODE,
+    IRQ_RAKE_CMIF_FPC_1X_IRQ = IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_FOE_1X_IRQ = IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE,
+    IRQ_RAKE_CMIF_PD_DO_IRQ = IRQ_RAKE_CMIF_PD_DO_IRQ_CODE,
+    IRQ_BIGRAM_IRQ = IRQ_BIGRAM_IRQ_CODE,
+    IRQ_BR_BDGE_IRQ = IRQ_BR_BDGE_IRQ_CODE,
+    IRQ_L1_LTE_SLEEP_IRQ = IRQ_L1_LTE_SLEEP_IRQ_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_0 = IRQ_L1M_PHY_LTMR_IRQ_0_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_1 = IRQ_L1M_PHY_LTMR_IRQ_1_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_2 = IRQ_L1M_PHY_LTMR_IRQ_2_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_3 = IRQ_L1M_PHY_LTMR_IRQ_3_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_4 = IRQ_L1M_PHY_LTMR_IRQ_4_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_5 = IRQ_L1M_PHY_LTMR_IRQ_5_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_6 = IRQ_L1M_PHY_LTMR_IRQ_6_CODE,
+    IRQ_L1M_PHY_LTMR_IRQ_7 = IRQ_L1M_PHY_LTMR_IRQ_7_CODE,
+    IRQ_L1_LTE_WAKEUP_IRQ = IRQ_L1_LTE_WAKEUP_IRQ_CODE,
+    IRQ_TDD_WAKEUP_IRQ = IRQ_TDD_WAKEUP_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_1_IRQ = IRQ_TDD_TIMER_L1D_1_IRQ_CODE,
+    IRQ_TDD_TIMER_L1D_2_IRQ = IRQ_TDD_TIMER_L1D_2_IRQ_CODE,
+    IRQ_RTR_SLT_0_IRQ = IRQ_RTR_SLT_0_IRQ_CODE,
+    IRQ_RTR_SLT_1_IRQ = IRQ_RTR_SLT_1_IRQ_CODE,
+    IRQ_FDD_SLP_IRQ = IRQ_FDD_SLP_IRQ_CODE,
+    IRQ_TDMA_WAKEUP_IRQ = IRQ_TDMA_WAKEUP_IRQ_CODE,
+    IRQ_ST1X_CPINT = IRQ_ST1X_CPINT_CODE,
+    IRQ_ST1x_HALF_CPINT = IRQ_ST1x_HALF_CPINT_CODE,
+    IRQ_ST1x_CFG_CPINT = IRQ_ST1x_CFG_CPINT_CODE,
+    IRQ_ST1x_WAKEUP_IRQ = IRQ_ST1x_WAKEUP_IRQ_CODE,
+    IRQ_STDO_CPINT = IRQ_STDO_CPINT_CODE,
+    IRQ_STDO_HALF_CPINT = IRQ_STDO_HALF_CPINT_CODE,
+    IRQ_STDO_CFG_CPINT = IRQ_STDO_CFG_CPINT_CODE,
+    IRQ_STDO_WAKEUP_IRQ = IRQ_STDO_WAKEUP_IRQ_CODE,
+    IRQ_FREQM_IRQ = IRQ_FREQM_IRQ_CODE,
+    IRQ_MDMCU_DVFS_CTRL = IRQ_MDMCU_DVFS_CTRL_CODE,
+    IRQ_PCC_TOP_FULL_IRQ = IRQ_PCC_TOP_FULL_IRQ_CODE,
+    IRQ_GPTM1 = IRQ_GPTM1_CODE,
+    IRQ_GPTM2 = IRQ_GPTM2_CODE,
+    IRQ_GPTM3 = IRQ_GPTM3_CODE,
+    IRQ_GPTM4 = IRQ_GPTM4_CODE,
+    IRQ_GPTM5 = IRQ_GPTM5_CODE,
+    IRQ_GPTM6 = IRQ_GPTM6_CODE,
+    IRQ_GPTM7 = IRQ_GPTM7_CODE,
+    IRQ_GPTM8 = IRQ_GPTM8_CODE,
+    IRQ_GPTM9 = IRQ_GPTM9_CODE,
+    IRQ_GPTM10 = IRQ_GPTM10_CODE,
+    IRQ_GPTM11 = IRQ_GPTM11_CODE,
+    IRQ_BUSMPU_IRQ = IRQ_BUSMPU_IRQ_CODE,
+    IRQ_MCU_BUS_DECERR = IRQ_MCU_BUS_DECERR_CODE,
+    IRQ_MCUMMU_INT = IRQ_MCUMMU_INT_CODE,
+    IRQ_IA_DECERR = IRQ_IA_DECERR_CODE,
+    IRQ_RMPU_CTIREIGIN = IRQ_RMPU_CTIREIGIN_CODE,
+    IRQ_AP2MD_MSDC0 = IRQ_AP2MD_MSDC0_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE,
+    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7 = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE,
+    IRQ_AP2MD_CCIF2 = IRQ_AP2MD_CCIF2_CODE,
+    IRQ_L1M_PHY_LTMR_SPU_IRQ = IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE,
+    IRQ_SPU_INT = IRQ_SPU_INT_CODE,
+    IRQ_SDF_OVERFLOW_IRQ = IRQ_SDF_OVERFLOW_IRQ_CODE,
+    IRQ_MDDFE_DUMP = IRQ_MDDFE_DUMP_CODE,
+    IRQ_AP2MD_CONN_CCIF_0 = IRQ_AP2MD_CONN_CCIF_0_CODE,
+    IRQ_AP2MD_CONN_CCIF_1 = IRQ_AP2MD_CONN_CCIF_1_CODE,
+    IRQ_I2C_TOP_INT = IRQ_I2C_TOP_INT_CODE,
+    IRQ_SW_LISR0 = IRQ_SW_LISR0_CODE,
+    IRQ_SW_LISR1 = IRQ_SW_LISR1_CODE,
+    IRQ_SW_LISR2 = IRQ_SW_LISR2_CODE,
+    IRQ_SW_LISR3 = IRQ_SW_LISR3_CODE,
+    IRQ_SW_LISR4 = IRQ_SW_LISR4_CODE,
+    IRQ_SW_LISR5 = IRQ_SW_LISR5_CODE,
+    IRQ_SW_LISR6 = IRQ_SW_LISR6_CODE,
+    IRQ_SW_LISR7 = IRQ_SW_LISR7_CODE,
+    IRQ_SW_LISR8 = IRQ_SW_LISR8_CODE,
+    IRQ_SW_LISR9 = IRQ_SW_LISR9_CODE,
+    IRQ_SW_LISR10 = IRQ_SW_LISR10_CODE,
+    IRQ_SW_LISR11 = IRQ_SW_LISR11_CODE,
+    IRQ_SW_LISR12 = IRQ_SW_LISR12_CODE,
+    IRQ_SW_LISR13 = IRQ_SW_LISR13_CODE,
+    IRQ_SW_LISR14 = IRQ_SW_LISR14_CODE,
+    IRQ_SW_LISR15 = IRQ_SW_LISR15_CODE,
+    IRQ_SW_LISR16 = IRQ_SW_LISR16_CODE,
+    IRQ_SW_LISR17 = IRQ_SW_LISR17_CODE,
+    IRQ_SW_LISR18 = IRQ_SW_LISR18_CODE,
+    IRQ_SW_LISR19 = IRQ_SW_LISR19_CODE,
+    IRQ_SW_LISR20 = IRQ_SW_LISR20_CODE,
+    IRQ_SW_LISR21 = IRQ_SW_LISR21_CODE,
+    IRQ_SW_LISR22 = IRQ_SW_LISR22_CODE,
+    IRQ_SW_LISR23 = IRQ_SW_LISR23_CODE,
+    IRQ_SW_LISR24 = IRQ_SW_LISR24_CODE,
+    IRQ_SW_LISR25 = IRQ_SW_LISR25_CODE,
+    IRQ_SW_LISR26 = IRQ_SW_LISR26_CODE,
+    IRQ_SW_LISR27 = IRQ_SW_LISR27_CODE,
+    IRQ_SW_LISR28 = IRQ_SW_LISR28_CODE,
+    IRQ_SW_LISR29 = IRQ_SW_LISR29_CODE,
+    IRQ_SW_LISR30 = IRQ_SW_LISR30_CODE,
+    IRQ_SW_LISR31 = IRQ_SW_LISR31_CODE,
+    IRQ_SW_LISR32 = IRQ_SW_LISR32_CODE,
+    IRQ_SW_LISR33 = IRQ_SW_LISR33_CODE,
+    IRQ_SW_LISR34 = IRQ_SW_LISR34_CODE,
+    IRQ_SW_LISR35 = IRQ_SW_LISR35_CODE,
+    IRQ_SW_LISR36 = IRQ_SW_LISR36_CODE,
+    IRQ_SW_LISR37 = IRQ_SW_LISR37_CODE,
+    IRQ_SW_LISR38 = IRQ_SW_LISR38_CODE,
+    IRQ_SW_LISR39 = IRQ_SW_LISR39_CODE,
+    IRQ_SW_LISR40 = IRQ_SW_LISR40_CODE,
+    IRQ_SW_LISR41 = IRQ_SW_LISR41_CODE,
+    IRQ_SW_LISR42 = IRQ_SW_LISR42_CODE,
+    IRQ_CONN2MD_PDMA_IRQ = IRQ_CONN2MD_PDMA_IRQ_CODE,
+    IRQ_CONN_BT_ISOCH = IRQ_CONN_BT_ISOCH_CODE,
+    IRQ_AP2MD_UFS = IRQ_AP2MD_UFS_CODE,
+};
+
+enum GIC_Code_Def_MET_Enum
+{
+    GIC_END = 0,
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+};
+
+#endif /* end of __INTRCTRL_MT6779_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779_SW_Handle.h
new file mode 100644
index 0000000..7c5ac1e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_MT6779_SW_Handle.h
@@ -0,0 +1,254 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6779_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   MT6779
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 13 2018 jimmy.hung
+ * [MOLY00338569] [Gen95][MDCIRQ][System Service] Update SW IRQ config
+ * For ALPS03983110 Copro power on issue.
+ *
+ * 04 19 2018 yen-chun.liu
+ * [MOLY00321364] [SWLA] Snapshot feature porting
+ * SW IRQ for SWLA.
+ *
+ * 02 21 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * new SWIRQ config for 4G wakeup control.
+ *
+ * 01 12 2018 yen-chun.liu
+ * [MOLY00301743] [Gen95][MDCIRQ][System Service] MDCIRQ driver development
+ * IRQ runtime config API.
+ *
+ * 05 03 2017 yen-chun.liu
+ * [MOLY00246635] [MT6295M][Gen95][System Service][MDCIRQ] Driver development for Gen95 MDCIRQ
+ * modification for interface folder.
+ *
+ * 04 06 2017 yen-chun.liu
+ * [MOLY00239574] [System Service][MOLY Kernel Internal Request][Gen93] MDDBG Regression
+ * MDDBG SW IRQ config.
+ *
+ * 04 05 2017 yen-chun.liu
+ * [MOLY00231842] [System Software][CIRQ][Nucleus_V3] OS IPI
+ * MDCIRQ driver for OSIPI.
+ *
+ * 03 07 2017 yen-chun.liu
+ * [MOLY00194080] [System Service][MDCIRQ] 93 MDCIRQ interrupt config
+ * return SW trigger IRQ 164,165 back.
+ *
+ * 02 10 2017 i-chun.liu
+ * [MOLY00228017] [Bianco Bring-up][Gen93/CIRQ] Add TDS UMAC HRT SWLR
+ * Add TDS UMAC HRT SWLR.
+ *
+ * 01 06 2017 yen-chun.liu
+ * [MOLY00214957] [Gen93][System Service][MDCIRQ] Modify Gen93 MDCIRQ driver
+ * add SW trigger interrupt ID.
+ *
+ * 05 30 2016 i-chun.liu
+ * [MOLY00171836] 93 MDCIRQ driver implementation
+ * MDCIRQ driver implementation.
+ *
+ * 02 22 2016 i-chun.liu
+ * [MOLY00165445] [MT6292][FPGA][Phone Call][4G FDD][Critical] Information about spurious interrupt lost with SST exception flow
+ * MDCIRQ driver update.
+ * SW_TRIGGER_CODE43-SW_TRIGGER_CODE54 is in the start to prevent SW_HANDLE_END small than SW_TRIGGER_CODEX
+ *
+ * 02 04 2016 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * add CIRQ SW trigger interrupts .
+ *
+ * 10 26 2015 i-chun.liu
+ * [MOLY00140199] MT6292 MDCIRQ and GIC driver implementation
+ * MDCIRQ SW trigger driver update.
+ *
+ * 09 30 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for MT6763
+ * update ELBRUS IRQID table .
+ *
+ * 08 24 2015 i-chun.liu
+ * [MOLY00135941] UMOLY Trunk merge back for ELBRUS
+ * fixed CIRQ related build error for ELBRUS.
+ *
+ * 07 29 2014 linson.du
+ * [MOLY00070793] [TK6291]: CIRQ driver update
+ * irq id and prority update.
+ *
+ * 04 24 2014 da.wang
+ * [MOLY00062016] Fix build error of porting for TK6291
+ * Update internal PMU & SW LISR naming.
+ *
+ * 07 03 2013 chin-chieh.hung
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ * .
+ *
+ * 06 04 2013 mogens.christiansen
+ * [MOLY00024323] [MT7208][NW-UE SIM][MOLY Regression][TC 6.2.3.31] Assert fail: m14999.c line 1022
+ * Fixed SW interrupt mapping in UESIM project
+ *
+ * 05 24 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * fix UESIM config error in target build
+ *
+ * 05 23 2013 chin-chieh.hung
+ * [MOLY00023372] [MT6290][NW-UE SIM] UESIM MOLY Migration - UESIM related changes submission
+ * UESIM, cirq support
+ *
+ * 03 25 2013 chin-chieh.hung
+ * [MOLY00011352] [Driver] Update for common devdrv driver
+ * add sw trigger interrupts
+ *
+ * 02 04 2013 chin-chieh.hung
+ * [MOLY00009725] MT7208 rename to MT6290 - basic platform module
+ * chip rename:MT7208 to MT6290
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE0 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE1 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE2 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE3 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE4 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE5 = Ramakrishna Marrapu
+      SW_TRIGGER_CODE6 = Zengling Jin
+      SW_TRIGGER_CODE7 = Zengling Jin
+      SW_TRIGGER_CODE8 = Zengling Jin
+      SW_TRIGGER_CODE9 = Cruze Yu
+      SW_TRIGGER_CODE10 = Cruze Yu
+      SW_TRIGGER_CODE11 = Cruze Yu
+      SW_TRIGGER_CODE12 = Cruze Yu
+      SW_TRIGGER_CODE13 = FI Chu, Charles Hsu
+      SW_TRIGGER_CODE14 = Woody Kuo
+      SW_TRIGGER_CODE15 = Carl Kao
+      SW_TRIGGER_CODE16 = Yuni Chang
+      SW_TRIGGER_CODE17 = SY Yeh
+      SW_TRIGGER_CODE18 = Owen Ho
+      SW_TRIGGER_CODE19 = Owen Ho
+      SW_TRIGGER_CODE20 = Owen Ho
+      SW_TRIGGER_CODE21 = Wade Huang
+      SW_TRIGGER_CODE22 = Jun-Ying Huang
+      SW_TRIGGER_CODE23 = Jun-Ying Huang
+      SW_TRIGGER_CODE24 = Jun-Ying Huang
+      SW_TRIGGER_CODE25 = Weimin Zeng
+      SW_TRIGGER_CODE26 = Weimin Zeng
+      SW_TRIGGER_CODE27 = Tee-Yuen Chun
+      SW_TRIGGER_CODE28 = YY Hsieh 
+      SW_TRIGGER_CODE29 = Kevin-KH Liu
+      SW_TRIGGER_CODE30 = HW Jheng
+      SW_TRIGGER_CODE31 = Nicole Hsu
+      SW_TRIGGER_CODE32 = 
+      SW_TRIGGER_CODE33 = 
+      SW_TRIGGER_CODE34 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE35 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE36 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE37 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE38 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE39 = HC Yang(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE40 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+      SW_TRIGGER_CODE41 = Liang Yan(Reserved for Busmon IRQ runtime configuration. Can be release if needed)
+      SW_TRIGGER_CODE42 = Jimmy Hung(Reserved for system usage)
+  */
+#if (defined(__MIPS_IA__))
+
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+#else
+#error "No CPU version select. Need to specify CPU version in project MT6779 for MDSYS."
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_SW_Handle.h
new file mode 100644
index 0000000..ac6c23a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/intrCtrl_SW_Handle.h
@@ -0,0 +1,92 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *   This file include the each BB chip software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/* Include Chip SW handler */
+
+#if defined(MT6295M)
+   #include "intrCtrl_MT6295M_SW_Handle.h"
+#endif
+
+#if defined(MT3967)
+   #include "intrCtrl_MT3967_SW_Handle.h"
+#endif
+
+#if defined(MT6779)
+   #include "intrCtrl_MT6779_SW_Handle.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqPriority.h b/mcu/interface/driver/devdrv/cirq/md95/irqPriority.h
new file mode 100644
index 0000000..f932ab5
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqPriority.h
@@ -0,0 +1,11 @@
+#if defined(MT6295M)
+   #include "irqPriority_MT6295M.h"
+#endif
+
+#if defined(MT3967)
+   #include "irqPriority_MT3967.h"
+#endif
+
+#if defined(MT6779)
+   #include "irqPriority_MT6779.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT3967.h b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT3967.h
new file mode 100644
index 0000000..050f9d2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT3967.h
@@ -0,0 +1,204 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUS_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCU_BUS_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDDFE_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_RXK_READBACK_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_DEV_CODE)
+IRQ_PRIORITY_CONST(IRQ_USB_MCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BR_BDGE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCC_TOP_FULL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IA_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SPU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN2MD_PDMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_BUCK_CTRL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_DVFS_CTRL_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_0)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_1)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_2)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_7)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6295M.h b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6295M.h
new file mode 100644
index 0000000..1361e38
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6295M.h
@@ -0,0 +1,204 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUS_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCU_BUS_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDDFE_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_RXK_READBACK_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_DEV_CODE)
+IRQ_PRIORITY_CONST(IRQ_USB_MCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BR_BDGE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCC_TOP_FULL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IA_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SPU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN2MD_PDMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_BUCK_CTRL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_DVFS_CTRL_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_0)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_1)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_2)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_7)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6779.h b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6779.h
new file mode 100644
index 0000000..af6548f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqPriority_MT6779.h
@@ -0,0 +1,204 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUS_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCU_BUS_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDDFE_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_RXK_READBACK_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_DEV_CODE)
+IRQ_PRIORITY_CONST(IRQ_USB_MCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BR_BDGE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCC_TOP_FULL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IA_DECERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SPU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN2MD_PDMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_BUCK_CTRL_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_DVFS_CTRL_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_0)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_1)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_2)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_7)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqid.h b/mcu/interface/driver/devdrv/cirq/md95/irqid.h
new file mode 100644
index 0000000..eb8c5e1
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqid.h
@@ -0,0 +1,16 @@
+#ifndef __IRQID_H__
+#define __IRQID_H__
+
+#if defined(MT6295M)
+   #include "irqid_MT6295M.h"
+#endif
+
+#if defined(MT3967)
+   #include "irqid_MT3967.h"
+#endif
+
+#if defined(MT6779)
+   #include "irqid_MT6779.h"
+#endif
+
+#endif /*end of __IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqid_MT3967.h b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT3967.h
new file mode 100644
index 0000000..fa92526
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT3967.h
@@ -0,0 +1,222 @@
+#ifndef __MT3967_IRQID_H__
+#define __MT3967_IRQID_H__
+
+#define MD_IRQID_SHARE_D12MINT1                 0    
+#define MD_IRQID_IRDBG_MCU_INT                  1    
+#define MD_IRQID_TDMA_CTIRQ1                    2    
+#define MD_IRQID_TDMA_CTIRQ2                    3    
+#define MD_IRQID_TDMA_CTIRQ3                    4    
+#define MD_IRQID_CSSYS_FDD_CS_IRQ               5    
+#define MD_IRQID_CSSYS_TDD_CS_IRQ               6    
+#define MD_IRQID_CSSYS_LTE_CS_IRQ               7    
+#define MD_IRQID_CSSYS_1X_CS_IRQ                8    
+#define MD_IRQID_CSSYS_DO_CS_IRQ                9    
+#define MD_IRQID_MDWDT                          10    
+#define MD_IRQID_UART_MD0                       11    
+#define MD_IRQID_UART_MD1                       12    
+#define MD_IRQID_OST                            13    
+#define MD_IRQID_USIM0                          14    
+#define MD_IRQID_USIM1                          15    
+#define MD_IRQID_MDGDMA0                        16    
+#define MD_IRQID_MDGDMA1                        17    
+#define MD_IRQID_MDGDMA2                        18    
+#define MD_IRQID_MDGDMA3                        19    
+#define MD_IRQID_EINT0                          20    
+#define MD_IRQID_EINT1                          21    
+#define MD_IRQID_EINT2                          22    
+#define MD_IRQID_EINT_SHARE                     23    
+#define MD_IRQID_BUS_ERR                        24    
+#define MD_IRQID_TXBSRP                         25    
+#define MD_IRQID_TXCRP                          26    
+#define MD_IRQ_ID_MML2_HRT                      27    
+#define MD_IRQ_ID_MML2_NOTIF                    28    
+#define MD_IRQ_ID_MML2_EXCEP                    29    
+#define MD_IRQID_DEM_TRIG_PS_INT_LE             30    
+#define MD_IRQID_ECT                            31    
+#define MD_IRQID_PTP_THERM_INT_INT              32    
+#define MD_IRQID_CLDMA                          33    
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS       34    
+#define MD_IRQID_ELM_DMA_IRQ                    35    
+#define MD_IRQID_SOE                            36    
+#define MD_IRQID_ULSP_LOG_MD_INT                37    
+#define MD_IRQID_ULSP_LOG_DSP_INT               38    
+#define MD_IRQID_USIP0_0                        39    
+#define MD_IRQID_USIP1_0                        40    
+#define MD_IRQID_USIP2_0                        41    
+#define MD_IRQID_USIP3_0                        42    
+#define MD_IRQID_USIP0_1                        43    
+#define MD_IRQID_USIP1_1                        44    
+#define MD_IRQID_USIP2_1                        45    
+#define MD_IRQID_SI_CM_ERR                      46    
+#define MD_IRQID_ABM_INT                        47    
+#define MD_IRQID_ABM_ERROR_INT                  48    
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS         49    
+#define MD_IRQID_ELMTOP_EMI_IRQ                 50    
+#define MD_IRQID_PPPHA_ENC0_INT                 51    
+#define MD_IRQID_PPPHA_ENC1_INT                 52    
+#define MD_IRQID_PPPHA_DEC0_INT                 53    
+#define MD_IRQID_PPPHA_DEC1_INT                 54    
+#define MD_IRQID_PTP_FSM_INT                    55    
+#define MD_IRQID_IEBIT_CHECK_IRQ0               56    
+#define MD_IRQID_IEBIT_CHECK_IRQ1               57    
+#define MD_IRQID_IEBIT_CHECK_IRQ2               58    
+#define MD_IRQID_IEBIT_CHECK_IRQ3               59    
+#define MD_IRQID_IEBIT_CHECK_IRQ4               60    
+#define MD_IRQID_IEBIT_CHECK_IRQ5               61    
+#define MD_IRQID_TRACE_INT                      62    
+#define MD_IRQID_SI_CM_PCINT                    63    
+#define MD_IRQID_PLL_GEARHP_RDY                 64    
+#define MD_IRQID_MD_BUCK_CTRL_IRQ               65    
+#define MD_IRQID_REQ_ABNORM_IRQ                 66    
+#define MD_IRQID_EINT3                          67    
+#define MD_IRQID_BT_CVSD                        68    
+#define MD_IRQID_SSUSB_DEV                      69    
+#define MD_IRQID_USB_MCU                        70    
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM           71    
+#define MD_IRQID_AP2MD_CCIF0_0                  72    
+#define MD_IRQID_AP2MD_CCIF0_1                  73    
+#define MD_IRQID_AP2MD_CCIF1_0                  74    
+#define MD_IRQID_AP2MD_CCIF1_1                  75    
+#define MD_IRQID_RXDFE_RXK_READBACK             76    
+#define MD_IRQID_IDC_PM_INT                     77    
+#define MD_IRQID_IDC_UART_IRQ                   78    
+#define MD_IRQID_MDRTT                          79    
+#define MD_IRQID_MDEVDO                         80    
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0            81    
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1            82    
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ           83    
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ           84    
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ            85    
+#define MD_IRQID_BIGRAM_IRQ                     86    
+#define MD_IRQID_BR_BDGE_IRQ                    87    
+#define MD_IRQID_L1_LTE_SLEEP_IRQ               88    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0  89    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1  90    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0             91    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1             92    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2             93    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3             94    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4             95    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5             96    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6             97    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7             98    
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ              99    
+#define MD_IRQID_TDD_WAKEUP_IRQ                 100    
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ            101    
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ            102    
+#define MD_IRQID_RTR_SLT_0_IRQ                  103    
+#define MD_IRQID_RTR_SLT_1_IRQ                  104    
+#define MD_IRQID_FDD_SLP_IRQ                    105    
+#define MD_IRQID_TDMA_WAKEUP_IRQ                106    
+#define MD_IRQID_ST1X_CPINT                     107    
+#define MD_IRQID_ST1x_HALF_CPINT                108    
+#define MD_IRQID_ST1x_CFG_CPINT                 109    
+#define MD_IRQID_ST1x_WAKEUP_IRQ                110    
+#define MD_IRQID_STDO_CPINT                     111    
+#define MD_IRQID_STDO_HALF_CPINT                112    
+#define MD_IRQID_STDO_CFG_CPINT                 113    
+#define MD_IRQID_STDO_WAKEUP_IRQ                114    
+#define MD_IRQID_FREQM_IRQ                      115    
+#define MD_IRQID_MDMCU_DVFS_CTRL                116    
+#define MD_IRQID_PCC_TOP_FULL_IRQ               117    
+#define MD_IRQID_GPTM1                          118    
+#define MD_IRQID_GPTM2                          119    
+#define MD_IRQID_GPTM3                          120    
+#define MD_IRQID_GPTM4                          121    
+#define MD_IRQID_GPTM5                          122    
+#define MD_IRQID_GPTM6                          123    
+#define MD_IRQID_GPTM7                          124    
+#define MD_IRQID_GPTM8                          125    
+#define MD_IRQID_GPTM9                          126    
+#define MD_IRQID_GPTM10                         127    
+#define MD_IRQID_GPTM11                         128    
+#define MD_IRQID_BUSMPU_IRQ                     129    
+#define MD_IRQID_MCU_BUS_DECERR                 130    
+#define MD_IRQID_MCUMMU_INT                     131    
+#define MD_IRQID_IA_DECERR                      132    
+#define MD_IRQID_RMPU_CTIREIGIN                 133    
+#define MD_IRQID_AP2MD_MSDC0                    134    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2  135    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3  136    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4  137    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5  138    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6  139    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7  140    
+#define MD_IRQID_AP2MD_CCIF2                    141    
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ           142    
+#define MD_IRQID_SPU_INT                        143    
+#define MD_IRQID_SDF_OVERFLOW_IRQ               144    
+#define MD_IRQID_MDDFE_DUMP                     145    
+#define MD_IRQID_AP2MD_CONN_CCIF_0              146    
+#define MD_IRQID_AP2MD_CONN_CCIF_1              147    
+#define MD_IRQID_I2C_TOP_INT                    148    
+#define MD_IRQID_SW_TRIGGER_RESERVED_0          149
+#define MD_IRQID_SW_TRIGGER_RESERVED_1          150
+#define MD_IRQID_SW_TRIGGER_RESERVED_2          151
+#define MD_IRQID_SW_TRIGGER_RESERVED_3          152
+#define MD_IRQID_SW_TRIGGER_RESERVED_4          153
+#define MD_IRQID_SW_TRIGGER_RESERVED_5          154
+#define MD_IRQID_SW_TRIGGER_RESERVED_6          155
+#define MD_IRQID_SW_TRIGGER_RESERVED_7          156
+#define MD_IRQID_SW_TRIGGER_RESERVED_8          157
+#define MD_IRQID_SW_TRIGGER_RESERVED_9          158
+#define MD_IRQID_SW_TRIGGER_RESERVED_10         159
+#define MD_IRQID_SW_TRIGGER_RESERVED_11         160
+#define MD_IRQID_SW_TRIGGER_RESERVED_12         161
+#define MD_IRQID_SW_TRIGGER_RESERVED_13         162
+#define MD_IRQID_SW_TRIGGER_RESERVED_14         163
+#define MD_IRQID_SW_TRIGGER_RESERVED_15         164
+#define MD_IRQID_SW_TRIGGER_RESERVED_16         165
+#define MD_IRQID_SW_TRIGGER_RESERVED_17         166
+#define MD_IRQID_SW_TRIGGER_RESERVED_18         167
+#define MD_IRQID_SW_TRIGGER_RESERVED_19         168
+#define MD_IRQID_SW_TRIGGER_RESERVED_20         169
+#define MD_IRQID_SW_TRIGGER_RESERVED_21         170
+#define MD_IRQID_SW_TRIGGER_RESERVED_22         171
+#define MD_IRQID_SW_TRIGGER_RESERVED_23         172
+#define MD_IRQID_SW_TRIGGER_RESERVED_24         173
+#define MD_IRQID_SW_TRIGGER_RESERVED_25         174
+#define MD_IRQID_SW_TRIGGER_RESERVED_26         175
+#define MD_IRQID_SW_TRIGGER_RESERVED_27         176
+#define MD_IRQID_SW_TRIGGER_RESERVED_28         177
+#define MD_IRQID_SW_TRIGGER_RESERVED_29         178
+#define MD_IRQID_SW_TRIGGER_RESERVED_30         179
+#define MD_IRQID_SW_TRIGGER_RESERVED_31         180
+#define MD_IRQID_SW_TRIGGER_RESERVED_32         181
+#define MD_IRQID_SW_TRIGGER_RESERVED_33         182
+#define MD_IRQID_SW_TRIGGER_RESERVED_34         183
+#define MD_IRQID_SW_TRIGGER_RESERVED_35         184
+#define MD_IRQID_SW_TRIGGER_RESERVED_36         185
+#define MD_IRQID_SW_TRIGGER_RESERVED_37         186
+#define MD_IRQID_SW_TRIGGER_RESERVED_38         187
+#define MD_IRQID_SW_TRIGGER_RESERVED_39         188
+#define MD_IRQID_SW_TRIGGER_RESERVED_40         189
+#define MD_IRQID_SW_TRIGGER_RESERVED_41         190
+#define MD_IRQID_SW_TRIGGER_RESERVED_42         191
+#define MD_IRQID_CONN2MD_PDMA_IRQ               192
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_0           193
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_1           194
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_2           195
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_3           196
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_4           197
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_5           198
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_6           199
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_7           200
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_8           201
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_9           202
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_10          203
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT3967_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6295M.h b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6295M.h
new file mode 100644
index 0000000..241e08c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6295M.h
@@ -0,0 +1,222 @@
+#ifndef __MT6295M_IRQID_H__
+#define __MT6295M_IRQID_H__
+
+#define MD_IRQID_SHARE_D12MINT1                 0    
+#define MD_IRQID_IRDBG_MCU_INT                  1    
+#define MD_IRQID_TDMA_CTIRQ1                    2    
+#define MD_IRQID_TDMA_CTIRQ2                    3    
+#define MD_IRQID_TDMA_CTIRQ3                    4    
+#define MD_IRQID_CSSYS_FDD_CS_IRQ               5    
+#define MD_IRQID_CSSYS_TDD_CS_IRQ               6    
+#define MD_IRQID_CSSYS_LTE_CS_IRQ               7    
+#define MD_IRQID_CSSYS_1X_CS_IRQ                8    
+#define MD_IRQID_CSSYS_DO_CS_IRQ                9    
+#define MD_IRQID_MDWDT                          10    
+#define MD_IRQID_UART_MD0                       11    
+#define MD_IRQID_UART_MD1                       12    
+#define MD_IRQID_OST                            13    
+#define MD_IRQID_USIM0                          14    
+#define MD_IRQID_USIM1                          15    
+#define MD_IRQID_MDGDMA0                        16    
+#define MD_IRQID_MDGDMA1                        17    
+#define MD_IRQID_MDGDMA2                        18    
+#define MD_IRQID_MDGDMA3                        19    
+#define MD_IRQID_EINT0                          20    
+#define MD_IRQID_EINT1                          21    
+#define MD_IRQID_EINT2                          22    
+#define MD_IRQID_EINT_SHARE                     23    
+#define MD_IRQID_BUS_ERR                        24    
+#define MD_IRQID_TXBSRP                         25    
+#define MD_IRQID_TXCRP                          26    
+#define MD_IRQ_ID_MML2_HRT                      27    
+#define MD_IRQ_ID_MML2_NOTIF                    28    
+#define MD_IRQ_ID_MML2_EXCEP                    29    
+#define MD_IRQID_DEM_TRIG_PS_INT_LE             30    
+#define MD_IRQID_ECT                            31    
+#define MD_IRQID_PTP_THERM_INT_INT              32    
+#define MD_IRQID_CLDMA                          33    
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS       34    
+#define MD_IRQID_ELM_DMA_IRQ                    35    
+#define MD_IRQID_SOE                            36    
+#define MD_IRQID_ULSP_LOG_MD_INT                37    
+#define MD_IRQID_ULSP_LOG_DSP_INT               38    
+#define MD_IRQID_USIP0_0                        39    
+#define MD_IRQID_USIP1_0                        40    
+#define MD_IRQID_USIP2_0                        41    
+#define MD_IRQID_USIP3_0                        42    
+#define MD_IRQID_USIP0_1                        43    
+#define MD_IRQID_USIP1_1                        44    
+#define MD_IRQID_USIP2_1                        45    
+#define MD_IRQID_SI_CM_ERR                      46    
+#define MD_IRQID_ABM_INT                        47    
+#define MD_IRQID_ABM_ERROR_INT                  48    
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS         49    
+#define MD_IRQID_ELMTOP_EMI_IRQ                 50    
+#define MD_IRQID_PPPHA_ENC0_INT                 51    
+#define MD_IRQID_PPPHA_ENC1_INT                 52    
+#define MD_IRQID_PPPHA_DEC0_INT                 53    
+#define MD_IRQID_PPPHA_DEC1_INT                 54    
+#define MD_IRQID_PTP_FSM_INT                    55    
+#define MD_IRQID_IEBIT_CHECK_IRQ0               56    
+#define MD_IRQID_IEBIT_CHECK_IRQ1               57    
+#define MD_IRQID_IEBIT_CHECK_IRQ2               58    
+#define MD_IRQID_IEBIT_CHECK_IRQ3               59    
+#define MD_IRQID_IEBIT_CHECK_IRQ4               60    
+#define MD_IRQID_IEBIT_CHECK_IRQ5               61    
+#define MD_IRQID_TRACE_INT                      62    
+#define MD_IRQID_SI_CM_PCINT                    63    
+#define MD_IRQID_PLL_GEARHP_RDY                 64    
+#define MD_IRQID_MD_BUCK_CTRL_IRQ               65    
+#define MD_IRQID_REQ_ABNORM_IRQ                 66    
+#define MD_IRQID_EINT3                          67    
+#define MD_IRQID_BT_CVSD                        68    
+#define MD_IRQID_SSUSB_DEV                      69    
+#define MD_IRQID_USB_MCU                        70    
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM           71    
+#define MD_IRQID_AP2MD_CCIF0_0                  72    
+#define MD_IRQID_AP2MD_CCIF0_1                  73    
+#define MD_IRQID_AP2MD_CCIF1_0                  74    
+#define MD_IRQID_AP2MD_CCIF1_1                  75    
+#define MD_IRQID_RXDFE_RXK_READBACK             76    
+#define MD_IRQID_IDC_PM_INT                     77    
+#define MD_IRQID_IDC_UART_IRQ                   78    
+#define MD_IRQID_MDRTT                          79    
+#define MD_IRQID_MDEVDO                         80    
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0            81    
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1            82    
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ           83    
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ           84    
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ            85    
+#define MD_IRQID_BIGRAM_IRQ                     86    
+#define MD_IRQID_BR_BDGE_IRQ                    87    
+#define MD_IRQID_L1_LTE_SLEEP_IRQ               88    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0  89    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1  90    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0             91    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1             92    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2             93    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3             94    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4             95    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5             96    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6             97    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7             98    
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ              99    
+#define MD_IRQID_TDD_WAKEUP_IRQ                 100    
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ            101    
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ            102    
+#define MD_IRQID_RTR_SLT_0_IRQ                  103    
+#define MD_IRQID_RTR_SLT_1_IRQ                  104    
+#define MD_IRQID_FDD_SLP_IRQ                    105    
+#define MD_IRQID_TDMA_WAKEUP_IRQ                106    
+#define MD_IRQID_ST1X_CPINT                     107    
+#define MD_IRQID_ST1x_HALF_CPINT                108    
+#define MD_IRQID_ST1x_CFG_CPINT                 109    
+#define MD_IRQID_ST1x_WAKEUP_IRQ                110    
+#define MD_IRQID_STDO_CPINT                     111    
+#define MD_IRQID_STDO_HALF_CPINT                112    
+#define MD_IRQID_STDO_CFG_CPINT                 113    
+#define MD_IRQID_STDO_WAKEUP_IRQ                114    
+#define MD_IRQID_FREQM_IRQ                      115    
+#define MD_IRQID_MDMCU_DVFS_CTRL                116    
+#define MD_IRQID_PCC_TOP_FULL_IRQ               117    
+#define MD_IRQID_GPTM1                          118    
+#define MD_IRQID_GPTM2                          119    
+#define MD_IRQID_GPTM3                          120    
+#define MD_IRQID_GPTM4                          121    
+#define MD_IRQID_GPTM5                          122    
+#define MD_IRQID_GPTM6                          123    
+#define MD_IRQID_GPTM7                          124    
+#define MD_IRQID_GPTM8                          125    
+#define MD_IRQID_GPTM9                          126    
+#define MD_IRQID_GPTM10                         127    
+#define MD_IRQID_GPTM11                         128    
+#define MD_IRQID_BUSMPU_IRQ                     129    
+#define MD_IRQID_MCU_BUS_DECERR                 130    
+#define MD_IRQID_MCUMMU_INT                     131    
+#define MD_IRQID_IA_DECERR                      132    
+#define MD_IRQID_RMPU_CTIREIGIN                 133    
+#define MD_IRQID_AP2MD_MSDC0                    134    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2  135    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3  136    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4  137    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5  138    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6  139    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7  140    
+#define MD_IRQID_AP2MD_CCIF2                    141    
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ           142    
+#define MD_IRQID_SPU_INT                        143    
+#define MD_IRQID_SDF_OVERFLOW_IRQ               144    
+#define MD_IRQID_MDDFE_DUMP                     145    
+#define MD_IRQID_AP2MD_CONN_CCIF_0              146    
+#define MD_IRQID_AP2MD_CONN_CCIF_1              147    
+#define MD_IRQID_I2C_TOP_INT                    148    
+#define MD_IRQID_SW_TRIGGER_RESERVED_0          149
+#define MD_IRQID_SW_TRIGGER_RESERVED_1          150
+#define MD_IRQID_SW_TRIGGER_RESERVED_2          151
+#define MD_IRQID_SW_TRIGGER_RESERVED_3          152
+#define MD_IRQID_SW_TRIGGER_RESERVED_4          153
+#define MD_IRQID_SW_TRIGGER_RESERVED_5          154
+#define MD_IRQID_SW_TRIGGER_RESERVED_6          155
+#define MD_IRQID_SW_TRIGGER_RESERVED_7          156
+#define MD_IRQID_SW_TRIGGER_RESERVED_8          157
+#define MD_IRQID_SW_TRIGGER_RESERVED_9          158
+#define MD_IRQID_SW_TRIGGER_RESERVED_10         159
+#define MD_IRQID_SW_TRIGGER_RESERVED_11         160
+#define MD_IRQID_SW_TRIGGER_RESERVED_12         161
+#define MD_IRQID_SW_TRIGGER_RESERVED_13         162
+#define MD_IRQID_SW_TRIGGER_RESERVED_14         163
+#define MD_IRQID_SW_TRIGGER_RESERVED_15         164
+#define MD_IRQID_SW_TRIGGER_RESERVED_16         165
+#define MD_IRQID_SW_TRIGGER_RESERVED_17         166
+#define MD_IRQID_SW_TRIGGER_RESERVED_18         167
+#define MD_IRQID_SW_TRIGGER_RESERVED_19         168
+#define MD_IRQID_SW_TRIGGER_RESERVED_20         169
+#define MD_IRQID_SW_TRIGGER_RESERVED_21         170
+#define MD_IRQID_SW_TRIGGER_RESERVED_22         171
+#define MD_IRQID_SW_TRIGGER_RESERVED_23         172
+#define MD_IRQID_SW_TRIGGER_RESERVED_24         173
+#define MD_IRQID_SW_TRIGGER_RESERVED_25         174
+#define MD_IRQID_SW_TRIGGER_RESERVED_26         175
+#define MD_IRQID_SW_TRIGGER_RESERVED_27         176
+#define MD_IRQID_SW_TRIGGER_RESERVED_28         177
+#define MD_IRQID_SW_TRIGGER_RESERVED_29         178
+#define MD_IRQID_SW_TRIGGER_RESERVED_30         179
+#define MD_IRQID_SW_TRIGGER_RESERVED_31         180
+#define MD_IRQID_SW_TRIGGER_RESERVED_32         181
+#define MD_IRQID_SW_TRIGGER_RESERVED_33         182
+#define MD_IRQID_SW_TRIGGER_RESERVED_34         183
+#define MD_IRQID_SW_TRIGGER_RESERVED_35         184
+#define MD_IRQID_SW_TRIGGER_RESERVED_36         185
+#define MD_IRQID_SW_TRIGGER_RESERVED_37         186
+#define MD_IRQID_SW_TRIGGER_RESERVED_38         187
+#define MD_IRQID_SW_TRIGGER_RESERVED_39         188
+#define MD_IRQID_SW_TRIGGER_RESERVED_40         189
+#define MD_IRQID_SW_TRIGGER_RESERVED_41         190
+#define MD_IRQID_SW_TRIGGER_RESERVED_42         191
+#define MD_IRQID_CONN2MD_PDMA_IRQ               192
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_0           193
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_1           194
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_2           195
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_3           196
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_4           197
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_5           198
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_6           199
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_7           200
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_8           201
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_9           202
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_10          203
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6295M_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6779.h b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6779.h
new file mode 100644
index 0000000..db4fba9
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/irqid_MT6779.h
@@ -0,0 +1,222 @@
+#ifndef __MT6779_IRQID_H__
+#define __MT6779_IRQID_H__
+
+#define MD_IRQID_SHARE_D12MINT1                 0    
+#define MD_IRQID_IRDBG_MCU_INT                  1    
+#define MD_IRQID_TDMA_CTIRQ1                    2    
+#define MD_IRQID_TDMA_CTIRQ2                    3    
+#define MD_IRQID_TDMA_CTIRQ3                    4    
+#define MD_IRQID_CSSYS_FDD_CS_IRQ               5    
+#define MD_IRQID_CSSYS_TDD_CS_IRQ               6    
+#define MD_IRQID_CSSYS_LTE_CS_IRQ               7    
+#define MD_IRQID_CSSYS_1X_CS_IRQ                8    
+#define MD_IRQID_CSSYS_DO_CS_IRQ                9    
+#define MD_IRQID_MDWDT                          10    
+#define MD_IRQID_UART_MD0                       11    
+#define MD_IRQID_UART_MD1                       12    
+#define MD_IRQID_OST                            13    
+#define MD_IRQID_USIM0                          14    
+#define MD_IRQID_USIM1                          15    
+#define MD_IRQID_MDGDMA0                        16    
+#define MD_IRQID_MDGDMA1                        17    
+#define MD_IRQID_MDGDMA2                        18    
+#define MD_IRQID_MDGDMA3                        19    
+#define MD_IRQID_EINT0                          20    
+#define MD_IRQID_EINT1                          21    
+#define MD_IRQID_EINT2                          22    
+#define MD_IRQID_EINT_SHARE                     23    
+#define MD_IRQID_BUS_ERR                        24    
+#define MD_IRQID_TXBSRP                         25    
+#define MD_IRQID_TXCRP                          26    
+#define MD_IRQ_ID_MML2_HRT                      27    
+#define MD_IRQ_ID_MML2_NOTIF                    28    
+#define MD_IRQ_ID_MML2_EXCEP                    29    
+#define MD_IRQID_DEM_TRIG_PS_INT_LE             30    
+#define MD_IRQID_ECT                            31    
+#define MD_IRQID_PTP_THERM_INT_INT              32    
+#define MD_IRQID_CLDMA                          33    
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS       34    
+#define MD_IRQID_ELM_DMA_IRQ                    35    
+#define MD_IRQID_SOE                            36    
+#define MD_IRQID_ULSP_LOG_MD_INT                37    
+#define MD_IRQID_ULSP_LOG_DSP_INT               38    
+#define MD_IRQID_USIP0_0                        39    
+#define MD_IRQID_USIP1_0                        40    
+#define MD_IRQID_USIP2_0                        41    
+#define MD_IRQID_USIP3_0                        42    
+#define MD_IRQID_USIP0_1                        43    
+#define MD_IRQID_USIP1_1                        44    
+#define MD_IRQID_USIP2_1                        45    
+#define MD_IRQID_SI_CM_ERR                      46    
+#define MD_IRQID_ABM_INT                        47    
+#define MD_IRQID_ABM_ERROR_INT                  48    
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS         49    
+#define MD_IRQID_ELMTOP_EMI_IRQ                 50    
+#define MD_IRQID_PPPHA_ENC0_INT                 51    
+#define MD_IRQID_PPPHA_ENC1_INT                 52    
+#define MD_IRQID_PPPHA_DEC0_INT                 53    
+#define MD_IRQID_PPPHA_DEC1_INT                 54    
+#define MD_IRQID_PTP_FSM_INT                    55    
+#define MD_IRQID_IEBIT_CHECK_IRQ0               56    
+#define MD_IRQID_IEBIT_CHECK_IRQ1               57    
+#define MD_IRQID_IEBIT_CHECK_IRQ2               58    
+#define MD_IRQID_IEBIT_CHECK_IRQ3               59    
+#define MD_IRQID_IEBIT_CHECK_IRQ4               60    
+#define MD_IRQID_IEBIT_CHECK_IRQ5               61    
+#define MD_IRQID_TRACE_INT                      62    
+#define MD_IRQID_SI_CM_PCINT                    63    
+#define MD_IRQID_PLL_GEARHP_RDY                 64    
+#define MD_IRQID_MD_BUCK_CTRL_IRQ               65    
+#define MD_IRQID_REQ_ABNORM_IRQ                 66    
+#define MD_IRQID_EINT3                          67    
+#define MD_IRQID_BT_CVSD                        68    
+#define MD_IRQID_SSUSB_DEV                      69    
+#define MD_IRQID_USB_MCU                        70    
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM           71    
+#define MD_IRQID_AP2MD_CCIF0_0                  72    
+#define MD_IRQID_AP2MD_CCIF0_1                  73    
+#define MD_IRQID_AP2MD_CCIF1_0                  74    
+#define MD_IRQID_AP2MD_CCIF1_1                  75    
+#define MD_IRQID_RXDFE_RXK_READBACK             76    
+#define MD_IRQID_IDC_PM_INT                     77    
+#define MD_IRQID_IDC_UART_IRQ                   78    
+#define MD_IRQID_MDRTT                          79    
+#define MD_IRQID_MDEVDO                         80    
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0            81    
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1            82    
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ           83    
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ           84    
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ            85    
+#define MD_IRQID_BIGRAM_IRQ                     86    
+#define MD_IRQID_BR_BDGE_IRQ                    87    
+#define MD_IRQID_L1_LTE_SLEEP_IRQ               88    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0  89    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1  90    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0             91    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1             92    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2             93    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3             94    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4             95    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5             96    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6             97    
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7             98    
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ              99    
+#define MD_IRQID_TDD_WAKEUP_IRQ                 100    
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ            101    
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ            102    
+#define MD_IRQID_RTR_SLT_0_IRQ                  103    
+#define MD_IRQID_RTR_SLT_1_IRQ                  104    
+#define MD_IRQID_FDD_SLP_IRQ                    105    
+#define MD_IRQID_TDMA_WAKEUP_IRQ                106    
+#define MD_IRQID_ST1X_CPINT                     107    
+#define MD_IRQID_ST1x_HALF_CPINT                108    
+#define MD_IRQID_ST1x_CFG_CPINT                 109    
+#define MD_IRQID_ST1x_WAKEUP_IRQ                110    
+#define MD_IRQID_STDO_CPINT                     111    
+#define MD_IRQID_STDO_HALF_CPINT                112    
+#define MD_IRQID_STDO_CFG_CPINT                 113    
+#define MD_IRQID_STDO_WAKEUP_IRQ                114    
+#define MD_IRQID_FREQM_IRQ                      115    
+#define MD_IRQID_MDMCU_DVFS_CTRL                116    
+#define MD_IRQID_PCC_TOP_FULL_IRQ               117    
+#define MD_IRQID_GPTM1                          118    
+#define MD_IRQID_GPTM2                          119    
+#define MD_IRQID_GPTM3                          120    
+#define MD_IRQID_GPTM4                          121    
+#define MD_IRQID_GPTM5                          122    
+#define MD_IRQID_GPTM6                          123    
+#define MD_IRQID_GPTM7                          124    
+#define MD_IRQID_GPTM8                          125    
+#define MD_IRQID_GPTM9                          126    
+#define MD_IRQID_GPTM10                         127    
+#define MD_IRQID_GPTM11                         128    
+#define MD_IRQID_BUSMPU_IRQ                     129    
+#define MD_IRQID_MCU_BUS_DECERR                 130    
+#define MD_IRQID_MCUMMU_INT                     131    
+#define MD_IRQID_IA_DECERR                      132    
+#define MD_IRQID_RMPU_CTIREIGIN                 133    
+#define MD_IRQID_AP2MD_MSDC0                    134    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2  135    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3  136    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4  137    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5  138    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6  139    
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7  140    
+#define MD_IRQID_AP2MD_CCIF2                    141    
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ           142    
+#define MD_IRQID_SPU_INT                        143    
+#define MD_IRQID_SDF_OVERFLOW_IRQ               144    
+#define MD_IRQID_MDDFE_DUMP                     145    
+#define MD_IRQID_AP2MD_CONN_CCIF_0              146    
+#define MD_IRQID_AP2MD_CONN_CCIF_1              147    
+#define MD_IRQID_I2C_TOP_INT                    148    
+#define MD_IRQID_SW_TRIGGER_RESERVED_0          149
+#define MD_IRQID_SW_TRIGGER_RESERVED_1          150
+#define MD_IRQID_SW_TRIGGER_RESERVED_2          151
+#define MD_IRQID_SW_TRIGGER_RESERVED_3          152
+#define MD_IRQID_SW_TRIGGER_RESERVED_4          153
+#define MD_IRQID_SW_TRIGGER_RESERVED_5          154
+#define MD_IRQID_SW_TRIGGER_RESERVED_6          155
+#define MD_IRQID_SW_TRIGGER_RESERVED_7          156
+#define MD_IRQID_SW_TRIGGER_RESERVED_8          157
+#define MD_IRQID_SW_TRIGGER_RESERVED_9          158
+#define MD_IRQID_SW_TRIGGER_RESERVED_10         159
+#define MD_IRQID_SW_TRIGGER_RESERVED_11         160
+#define MD_IRQID_SW_TRIGGER_RESERVED_12         161
+#define MD_IRQID_SW_TRIGGER_RESERVED_13         162
+#define MD_IRQID_SW_TRIGGER_RESERVED_14         163
+#define MD_IRQID_SW_TRIGGER_RESERVED_15         164
+#define MD_IRQID_SW_TRIGGER_RESERVED_16         165
+#define MD_IRQID_SW_TRIGGER_RESERVED_17         166
+#define MD_IRQID_SW_TRIGGER_RESERVED_18         167
+#define MD_IRQID_SW_TRIGGER_RESERVED_19         168
+#define MD_IRQID_SW_TRIGGER_RESERVED_20         169
+#define MD_IRQID_SW_TRIGGER_RESERVED_21         170
+#define MD_IRQID_SW_TRIGGER_RESERVED_22         171
+#define MD_IRQID_SW_TRIGGER_RESERVED_23         172
+#define MD_IRQID_SW_TRIGGER_RESERVED_24         173
+#define MD_IRQID_SW_TRIGGER_RESERVED_25         174
+#define MD_IRQID_SW_TRIGGER_RESERVED_26         175
+#define MD_IRQID_SW_TRIGGER_RESERVED_27         176
+#define MD_IRQID_SW_TRIGGER_RESERVED_28         177
+#define MD_IRQID_SW_TRIGGER_RESERVED_29         178
+#define MD_IRQID_SW_TRIGGER_RESERVED_30         179
+#define MD_IRQID_SW_TRIGGER_RESERVED_31         180
+#define MD_IRQID_SW_TRIGGER_RESERVED_32         181
+#define MD_IRQID_SW_TRIGGER_RESERVED_33         182
+#define MD_IRQID_SW_TRIGGER_RESERVED_34         183
+#define MD_IRQID_SW_TRIGGER_RESERVED_35         184
+#define MD_IRQID_SW_TRIGGER_RESERVED_36         185
+#define MD_IRQID_SW_TRIGGER_RESERVED_37         186
+#define MD_IRQID_SW_TRIGGER_RESERVED_38         187
+#define MD_IRQID_SW_TRIGGER_RESERVED_39         188
+#define MD_IRQID_SW_TRIGGER_RESERVED_40         189
+#define MD_IRQID_SW_TRIGGER_RESERVED_41         190
+#define MD_IRQID_SW_TRIGGER_RESERVED_42         191
+#define MD_IRQID_CONN2MD_PDMA_IRQ               192
+#define MD_IRQID_CONN_BT_ISOCH                  193
+#define MD_IRQID_AP2MD_UFS                      194
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_0           195
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_1           196
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_2           197
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_3           198
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_4           199
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_5           200
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_6           201
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_7           202
+#define MD_IRQID_DUMMY_PRIORITY_IRQ_8           203
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6779_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md95/isrentry.h b/mcu/interface/driver/devdrv/cirq/md95/isrentry.h
new file mode 100644
index 0000000..7fa5cf2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md95/isrentry.h
@@ -0,0 +1,107 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   isrentry.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*******************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2001
+*
+*******************************************************************************/
+
+#ifndef _ISRENTRY_H
+#define _ISRENTRY_H
+
+#include "kal_general_types.h"
+
+/*************************************************************************
+ * Define data structures.
+ *************************************************************************/
+
+typedef struct 
+{
+   kal_uint32 vector;
+   void (*lisr_handler) (kal_uint32);
+   kal_char *description;
+} irqlisr_entry;
+
+/*************************************************************************
+ * Define function prototypes.
+ *************************************************************************/
+#define IRQ_Default_LISR MDCIRQ_IRQ_Default_LISR
+
+void MDCIRQ_IRQ_LISR_Init(void);
+void MDCIRQ_IRQ_Default_LISR(kal_uint32);
+
+
+#endif /* _ISRENTRY_H */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl.h
new file mode 100644
index 0000000..41328c2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl.h
@@ -0,0 +1,422 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *   Common type and structure definition for MediaTek GSM/GPRS software
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _INTRCTRL_H
+#define _INTRCTRL_H
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "mips_ia_utils_public.h"
+#include "us_timer.h"
+#include "kal_public_api.h"
+
+#if defined(MT6297)
+#include "intrCtrl_MT6297.h"
+#endif
+
+#if defined(MT6885)
+#include "intrCtrl_MT6885.h"
+#endif
+
+#if defined(MT6873)
+#include "intrCtrl_MT6873.h"
+#endif
+
+#if defined(MT6853)
+#include "intrCtrl_MT6853.h"
+#endif
+
+#if defined(MT6833)
+#include "intrCtrl_MT6833.h"
+#endif
+
+#if defined(MT6877)
+#include "intrCtrl_MT6877.h"
+#endif
+
+#if defined(CHIP10992)
+#include "intrCtrl_CHIP10992.h"
+#endif
+
+/*******************************************************************************
+ * Declarations and Definitions
+ *******************************************************************************/
+// CIRQ MPB Statistic Enable Option
+#if !defined(__MPB_DISABLE__)
+#define __MDCIRQ_MPB_PROFILE__
+#endif
+
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+#define EDGE_SENSITIVE           KAL_TRUE
+#define LEVEL_SENSITIVE          KAL_FALSE
+
+#define IRQ_NOT_LISR_CONTEXT     (0xFFFF)
+
+#if defined(__CIRQ_MASK_REG_NR_1_NEW__) || defined(__CIRQ_MASK_REG_NR_2_NEW__) || defined(__CIRQ_MASK_REG_NR_3_NEW__) || defined(__CIRQ_MASK_REG_NR_4_NEW__) || defined(__CIRQ_MASK_REG_NR_5_NEW__)
+#define __CIRQ_DESIGN_NEW__
+#endif
+
+typedef struct CIRQ_MASK_VALUE_STRUCT
+{
+    kal_uint32 irq_mask[12]; 
+} CIRQ_MASK_VALUE_T;
+
+/* To enable SW Trigger Interrupt for new BB chips
+   Need to modify 3 files
+   1. add a file intrCtrl_MTxxxx_SW_Handler.h
+   2. add an entry on intrCtrl_SW_Handler.h
+   3. modify IRQ_SetSWRegister & IRQ_ResetSWRegister to support BB Chips on intrCtrl.c  */
+#if defined(__ENABLE_SW_TRIGGER_INTERRUPT__)
+typedef enum
+{
+#define X_SW_HANDLE_CONST(a, b, c) a=(b),
+#include "intrCtrl_SW_Handle.h"
+#undef X_SW_HANDLE_CONST
+    SW_HANDLE_END
+} SW_CODE_HANDLE;
+
+#define Activate_LISR(code) MDCIRQ_Activate_LISR(code)
+#define Deactivate_LISR(code) MDCIRQ_Deactivate_LISR(code)
+
+extern void MDCIRQ_Activate_LISR(SW_CODE_HANDLE code);
+extern void MDCIRQ_Deactivate_LISR(SW_CODE_HANDLE code);
+extern void MDCIRQ_Activate_LISR_without_ITC(SW_CODE_HANDLE code);
+extern void MDCIRQ_Deactivate_LISR_without_ITC(SW_CODE_HANDLE code);
+extern const kal_uint16 SW_Code_Handle2Code[NUM_IRQ_SOURCES];
+
+/* Use to translate the mapping between software handler to hardware interrupt code */
+#define SW_code_handle2code(a)  (a)
+
+extern kal_uint32 SW_INT_Counter[NUM_IRQ_SOURCES];
+
+#endif /* __ENABLE_SW_TRIGGER_INTERRUPT__ */
+
+
+#define IRQClearInt(vector) MDCIRQ_IRQClearInt(vector)
+#define IRQMask(vector) MDCIRQ_IRQMask(vector)
+#define IRQUnmask(vector) MDCIRQ_IRQUnmask(vector)
+#define IRQSensitivity(vector, e) MDCIRQ_IRQSensitivity(vector, e)
+#define IRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code) MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code)
+
+
+extern kal_uint32 SaveAndSetIRQMask(void);
+extern void RestoreIRQMask(kal_uint32);
+extern void MDCIRQ_IRQClearInt(kal_uint16);
+extern void MDCIRQ_IRQMask(kal_uint16);
+extern void MDCIRQ_IRQUnmask(kal_uint16);
+extern void MDCIRQ_IRQSensitivity(kal_uint16, kal_bool);
+extern void initINTR(void);
+extern kal_uint32 IRQMask_Status(kal_uint16 code);
+extern kal_uint32 IRQ_Status(void);
+
+#if defined(__MAUI_BASIC__) || !defined(__MTK_TARGET__)
+#define IRQ_Register_LISR(code, lisr, description) \
+    MDCIRQ_IRQ_Register_LISR(code, (void*)lisr, description)
+extern void MDCIRQ_IRQ_Register_LISR(kal_uint16 code, void (*reg_lisr)(kal_uint32 vector), char* description);
+#endif
+
+#define NRIRQ_Affinity_Change_NSA() MDCIRQ_Runtime_Change_NRIRQ_Affinity_NSA()
+#define NRIRQ_Affinity_Change_SA() MDCIRQ_Runtime_Change_NRIRQ_Affinity_SA()
+extern void MDCIRQ_Runtime_Change_NRIRQ_Affinity_NSA();
+extern void MDCIRQ_Runtime_Change_NRIRQ_Affinity_SA();
+
+#define LTEIRQ_Affinity_Change_ENDC() MDCIRQ_Runtime_Change_LTEIRQ_Affinity_ENDC()
+#define LTEIRQ_Affinity_Change_LTEONLY() MDCIRQ_Runtime_Change_LTEIRQ_Affinity_LTEONLY()
+extern void MDCIRQ_Runtime_Change_LTEIRQ_Affinity_ENDC();
+extern void MDCIRQ_Runtime_Change_LTEIRQ_Affinity_LTEONLY();
+
+extern void initVPEIRQ(void);
+
+extern kal_uint32 sst_dhl_irq_count[];
+extern kal_uint32 sst_dhl_irq_caller[];
+extern kal_uint32 DHLIrqCounter[];
+
+extern kal_int32 INC_Initialize_State;
+
+typedef enum
+{
+#define IRQ_PRIORITY_CONST(a) a##_PRIORITY,
+#include "irqPriority.h"
+#undef IRQ_PRIORITY_CONST
+    IRQ_PRIORITY_END,
+#if defined __MIPS_I7200__
+    IRQ_HRT_PRIORITY_THRESHOLD = IRQ_SW_LISR40_CODE_PRIORITY + 1,
+    IRQ_EQUALLY_DISPATCH_PRIORITY_THRESHOLD = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE_PRIORITY,
+#else /* MT6297_IA */
+    IRQ_NORMAL_DOMAIN_HRT_PRIORITY_THRESHOLD = IRQ_SW_LISR40_CODE_PRIORITY + 1,
+#endif
+} IRQ_PRIORITY;
+
+typedef enum {
+    MDCIRQ_To_BUS_Normal = 0x0,
+    MDCIRQ_To_BUS_PreUltra = 0x1,
+    MDCIRQ_To_BUS_Ultra =0x2,
+} MDCIRQ_Bus_QoS_Signal;
+
+/***********************************
+NOTE:
+1. below API is only for L1 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define IF_DI_OR_LISR()     (Ibit_Status()==0 || kal_if_lisr())
+
+/***********************************
+NOTE:
+1. below API is only for L2 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define __IRQ_LOCK_WITHOUT_CHECK__
+// #define __NESTED_DI_CHECK__
+
+#if defined(__L2_LOGGING_IRQ_LOC__)
+#if defined(__IRQ_LOCK_WITHOUT_CHECK__) && (defined(__MIPS_IA__) || defined(__MIPS_I7200__))
+#if defined(__NESTED_DI_CHECK__) && !defined (__ESL_MASE_GEN97__)
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+    kal_uint32 vpe_num = 0;\
+    miu_mt_dmt();\
+    __asm__ __volatile__\
+    (\
+        "di %0\n\t"\
+        "ehb\n\t"\
+        :"=&r"(oldmask), "=&r"(newmask)\
+        :\
+        :"$31","memory"\
+    );\
+    oldmask &= 0x1;\
+    vpe_num = miu_get_current_vpe_id();\
+    sst_dhl_irq_count[vpe_num]++;\
+    sst_dhl_irq_caller[vpe_num] = (kal_uint32)__builtin_return_address(0);\
+    DHLIrqCounter[vpe_num] = ust_get_current_time();\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+    kal_uint32 tmp=1;\
+    sst_dhl_irq_count[miu_get_current_vpe_id()]--;\
+    __asm__ __volatile__\
+    (\
+        "bne %0, %1, END\n\t"\
+        "ei\n\t"\
+        "ehb\n\t"\
+        "END:emt\n\t"\
+        "ehb\n\t"\
+        :\
+        :"r"(oldmask), "r"(tmp)\
+        :"memory"\
+    );\
+} while(0)
+#else
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+    miu_mt_dmt();\
+    __asm__ __volatile__\
+    (\
+        "di %0\n\t"\
+        "ehb\n\t"\
+        :"=&r"(oldmask), "=&r"(newmask)\
+        :\
+        :"$31","memory"\
+    );\
+    oldmask &= 0x1;\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+    kal_uint32 tmp=1;\
+    __asm__ __volatile__\
+    (\
+        "bne %0, %1, END\n\t"\
+        "ei\n\t"\
+        "ehb\n\t"\
+        "END:emt\n\t"\
+        "ehb\n\t"\
+        :\
+        :"r"(oldmask), "r"(tmp)\
+        :"memory"\
+    );\
+} while(0)
+#endif
+
+#else
+
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{ \
+	oldmask = kal_hrt_SaveAndSetIRQMask(); \
+}while(0);
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{ \
+	kal_hrt_RestoreIRQMask(oldmask); \
+}while(0);
+
+#endif
+#endif
+
+#endif /* _INTRCTRL_H */
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_CHIP10992.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_CHIP10992.h
new file mode 100644
index 0000000..b25f0f9
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_CHIP10992.h
@@ -0,0 +1,564 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_CHIP10992.h
+ *
+ * Project:
+ * --------
+ *   CHIP10992
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_CHIP10992_H__
+#define __INTRCTRL_CHIP10992_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+
+#define NUM_IRQ_SOURCES          (368)
+
+/* CIRQ Interrupt Sources */
+#define    IRQ_USIM0_CODE                            MD_IRQID_USIM0
+#define    IRQ_USIM1_CODE                            MD_IRQID_USIM1
+#define    IRQ_TDMA_CTIRQ1_CODE                      MD_IRQID_TDMA_CTIRQ1
+#define    IRQ_TDMA_CTIRQ2_CODE                      MD_IRQID_TDMA_CTIRQ2
+#define    IRQ_TDMA_CTIRQ3_CODE                      MD_IRQID_TDMA_CTIRQ3
+#define    IRQ_TDMA_WAKEUP_IRQ_CODE                  MD_IRQID_TDMA_WAKEUP_IRQ
+#define    IRQ_OST_CODE                              MD_IRQID_OST
+#define    IRQ_MDRTT_CODE                            MD_IRQID_MDRTT
+#define    IRQ_MDEVDO_CODE                           MD_IRQID_MDEVDO
+#define    IRQ_ULSP_LOG_MCU_RT_INT_CODE              MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define    IRQ_ULSP_LOG_MCU_OD_INT_CODE              MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define    IRQ_ULSP_LOG_DSP4G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define    IRQ_ULSP_LOG_DSP4G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define    IRQ_ULSP_LOG_DSP5G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define    IRQ_ULSP_LOG_DSP5G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define    IRQ_SHARE_D12MINT1_CODE                   MD_IRQID_SHARE_D12MINT1
+#define    IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE        MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define    IRQ_AIRQ_SERDES_CODE                      MD_IRQID_AIRQ_SERDES
+#define    IRQ_AIRQ_COS_CODE                         MD_IRQID_AIRQ_COS
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define    IRQ_PPPHA_ENC0_INT_CODE                   MD_IRQID_PPPHA_ENC0_INT
+#define    IRQ_PPPHA_ENC1_INT_CODE                   MD_IRQID_PPPHA_ENC1_INT
+#define    IRQ_PPPHA_DEC0_INT_CODE                   MD_IRQID_PPPHA_DEC0_INT
+#define    IRQ_PPPHA_DEC1_INT_CODE                   MD_IRQID_PPPHA_DEC1_INT
+#define    IRQ_CS_NR_IRQ_CODE                        MD_IRQID_CS_NR_IRQ
+#define    IRQ_CS_NR_ERR_IRQ_CODE                    MD_IRQID_CS_NR_ERR_IRQ
+#define    IRQ_SDF_OVERFLOW_IRQ_CODE                 MD_IRQID_SDF_OVERFLOW_IRQ
+#define    IRQ_MCUMMU_INT_CODE                       MD_IRQID_MCUMMU_INT
+#define    IRQ_BIGRAM_0_IRQ_0_CODE                   MD_IRQID_BIGRAM_0_IRQ_0
+#define    IRQ_COS_PREP_INT_CODE                     MD_IRQID_COS_PREP_INT
+#define    IRQ_TRACE_INT_CODE                        MD_IRQID_TRACE_INT
+#define    IRQ_NR_TIMER_IRQ0_CODE                    MD_IRQID_NR_TIMER_IRQ0
+#define    IRQ_NR_TIMER_IRQ1_CODE                    MD_IRQID_NR_TIMER_IRQ1
+#define    IRQ_NR_TIMER_IRQ2_CODE                    MD_IRQID_NR_TIMER_IRQ2
+#define    IRQ_NR_TIMER_IRQ3_CODE                    MD_IRQID_NR_TIMER_IRQ3
+#define    IRQ_NR_TIMER_IRQ4_CODE                    MD_IRQID_NR_TIMER_IRQ4
+#define    IRQ_NR_TIMER_IRQ5_CODE                    MD_IRQID_NR_TIMER_IRQ5
+#define    IRQ_NR_TIMER_IRQ6_CODE                    MD_IRQID_NR_TIMER_IRQ6
+#define    IRQ_NR_TIMER_IRQ7_CODE                    MD_IRQID_NR_TIMER_IRQ7
+#define    IRQ_NR_TIMER_IRQ8_CODE                    MD_IRQID_NR_TIMER_IRQ8
+#define    IRQ_NR_TIMER_IRQ9_CODE                    MD_IRQID_NR_TIMER_IRQ9
+#define    IRQ_NR_TIMER_IRQ10_CODE                   MD_IRQID_NR_TIMER_IRQ10
+#define    IRQ_NR_TIMER_IRQ11_CODE                   MD_IRQID_NR_TIMER_IRQ11
+#define    IRQ_NR_TIMER_IRQ12_CODE                   MD_IRQID_NR_TIMER_IRQ12
+#define    IRQ_NR_TIMER_IRQ13_CODE                   MD_IRQID_NR_TIMER_IRQ13
+#define    IRQ_NR_TIMER_IRQ14_CODE                   MD_IRQID_NR_TIMER_IRQ14
+#define    IRQ_NR_TIMER_IRQ15_CODE                   MD_IRQID_NR_TIMER_IRQ15
+#define    IRQ_NR_TIMER_IRQ16_CODE                   MD_IRQID_NR_TIMER_IRQ16
+#define    IRQ_NR_TIMER_IRQ17_CODE                   MD_IRQID_NR_TIMER_IRQ17
+#define    IRQ_NR_TIMER_IRQ18_CODE                   MD_IRQID_NR_TIMER_IRQ18
+#define    IRQ_NR_TIMER_IRQ19_CODE                   MD_IRQID_NR_TIMER_IRQ19
+#define    IRQ_NR_TIMER_IRQ20_CODE                   MD_IRQID_NR_TIMER_IRQ20
+#define    IRQ_NR_TIMER_IRQ21_CODE                   MD_IRQID_NR_TIMER_IRQ21
+#define    IRQ_NR_TIMER_IRQ22_CODE                   MD_IRQID_NR_TIMER_IRQ22
+#define    IRQ_NR_TIMER_IRQ23_CODE                   MD_IRQID_NR_TIMER_IRQ23
+#define    IRQ_NR_TIMER_IRQ24_CODE                   MD_IRQID_NR_TIMER_IRQ24
+#define    IRQ_NR_TIMER_IRQ25_CODE                   MD_IRQID_NR_TIMER_IRQ25
+#define    IRQ_NR_TIMER_IRQ26_CODE                   MD_IRQID_NR_TIMER_IRQ26
+#define    IRQ_NR_TIMER_IRQ27_CODE                   MD_IRQID_NR_TIMER_IRQ27
+#define    IRQ_NR_TIMER_IRQ28_CODE                   MD_IRQID_NR_TIMER_IRQ28
+#define    IRQ_NR_TIMER_IRQ29_CODE                   MD_IRQID_NR_TIMER_IRQ29
+#define    IRQ_NR_TIMER_IRQ30_CODE                   MD_IRQID_NR_TIMER_IRQ30
+#define    IRQ_NR_TIMER_IRQ31_CODE                   MD_IRQID_NR_TIMER_IRQ31
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define    IRQ_NR_TIMER_CNTDN_IRQ0_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define    IRQ_NR_TIMER_CNTDN_IRQ1_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define    IRQ_NR_TIMER_CNTDN_IRQ2_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define    IRQ_NR_TIMER_CNTDN_IRQ3_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define    IRQ_NR_EVENTGEN_SPU_CODE                  MD_IRQID_NR_EVENTGEN_SPU
+#define    IRQ_SI_CM_ERR_CODE                        MD_IRQID_SI_CM_ERR
+#define    IRQ_SI_CM_PCINT_CODE                      MD_IRQID_SI_CM_PCINT
+#define    IRQ_MDM2C_U3G_CODE                        MD_IRQID_MDM2C_U3G
+#define    IRQ_RAKE_CMIF_M2C_IRQ_0_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define    IRQ_RAKE_CMIF_M2C_IRQ_1_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define    IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define    IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define    IRQ_RAKE_CMIF_PD_DO_IRQ_CODE              MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define    IRQ_MDMCU_BUSMON_MATCH_STS_CODE           MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define    IRQ_MDINFRA_BUSMON_MATCH_STS_CODE         MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define    IRQ_ELMTOP_EMI_IRQ_CODE                   MD_IRQID_ELMTOP_EMI_IRQ
+#define    IRQ_ELM_DMA_IRQ_CODE                      MD_IRQID_ELM_DMA_IRQ
+#define    IRQ_BUSMPU_IRQ_CODE                       MD_IRQID_BUSMPU_IRQ
+#define    IRQ_ST1X_CPINT_CODE                       MD_IRQID_ST1X_CPINT
+#define    IRQ_ST1x_HALF_CPINT_CODE                  MD_IRQID_ST1x_HALF_CPINT
+#define    IRQ_ST1x_CFG_CPINT_CODE                   MD_IRQID_ST1x_CFG_CPINT
+#define    IRQ_ST1x_WAKEUP_IRQ_CODE                  MD_IRQID_ST1x_WAKEUP_IRQ
+#define    IRQ_STDO_CPINT_CODE                       MD_IRQID_STDO_CPINT
+#define    IRQ_STDO_HALF_CPINT_CODE                  MD_IRQID_STDO_HALF_CPINT
+#define    IRQ_STDO_CFG_CPINT_CODE                   MD_IRQID_STDO_CFG_CPINT
+#define    IRQ_STDO_WAKEUP_IRQ_CODE                  MD_IRQID_STDO_WAKEUP_IRQ
+#define    IRQ_UART_MD0_CODE                         MD_IRQID_UART_MD0
+#define    IRQ_UART_MD1_CODE                         MD_IRQID_UART_MD1
+#define    IRQ_EINT0_CODE                            MD_IRQID_EINT0
+#define    IRQ_EINT1_CODE                            MD_IRQID_EINT1
+#define    IRQ_EINT2_CODE                            MD_IRQID_EINT2
+#define    IRQ_EINT3_CODE                            MD_IRQID_EINT3
+#define    IRQ_EINT_SHARE_CODE                       MD_IRQID_EINT_SHARE
+#define    IRQ_GPTM1_CODE                            MD_IRQID_GPTM1
+#define    IRQ_GPTM2_CODE                            MD_IRQID_GPTM2
+#define    IRQ_GPTM3_CODE                            MD_IRQID_GPTM3
+#define    IRQ_GPTM4_CODE                            MD_IRQID_GPTM4
+#define    IRQ_GPTM5_CODE                            MD_IRQID_GPTM5
+#define    IRQ_GPTM6_CODE                            MD_IRQID_GPTM6
+#define    IRQ_GPTM7_CODE                            MD_IRQID_GPTM7
+#define    IRQ_GPTM8_CODE                            MD_IRQID_GPTM8
+#define    IRQ_GPTM9_CODE                            MD_IRQID_GPTM9
+#define    IRQ_GPTM10_CODE                           MD_IRQID_GPTM10
+#define    IRQ_GPTM11_CODE                           MD_IRQID_GPTM11
+#define    IRQ_IDC_PM_INT_CODE                       MD_IRQID_IDC_PM_INT
+#define    IRQ_IDC_UART_IRQ_CODE                     MD_IRQID_IDC_UART_IRQ
+#define    IRQ_MDGDMA_FDMA5_CODE                     MD_IRQID_MDGDMA_FDMA5
+#define    IRQ_MDGDMA_FDMA6_CODE                     MD_IRQID_MDGDMA_FDMA6
+#define    IRQ_TDMA_CTIRQ4_CODE                      MD_IRQID_TDMA_CTIRQ4
+#define    IRQ_PDMA_CODE                             MD_IRQID_PDMA
+#define    IRQ_MDINFRA_BUS_DECERROR_CODE             MD_IRQID_MDINFRA_BUS_DECERROR
+#define    IRQ_I2C_TOP_INT_CODE                      MD_IRQID_I2C_TOP_INT
+#define    IRQ_SOE_CODE                              MD_IRQID_SOE
+#define    IRQ_ABM_INT_CODE                          MD_IRQID_ABM_INT
+#define    IRQ_ABM_ERROR_INT_CODE                    MD_IRQID_ABM_ERROR_INT
+#define    IRQ_USIP0_CODE                            MD_IRQID_USIP0
+#define    IRQ_USIP1_CODE                            MD_IRQID_USIP1
+#define    IRQ_USIP2_CODE                            MD_IRQID_USIP2
+#define    IRQ_USIP3_CODE                            MD_IRQID_USIP3
+#define    IRQ_USIP4_CODE                            MD_IRQID_USIP4
+#define    IRQ_USIP5_CODE                            MD_IRQID_USIP5
+#define    IRQ_USIP6_CODE                            MD_IRQID_USIP6
+#define    IRQ_USIP7_CODE                            MD_IRQID_USIP7
+#define    IRQ_USIP8_CODE                            MD_IRQID_USIP8
+#define    IRQ_USIP9_CODE                            MD_IRQID_USIP9
+#define    IRQ_USIP10_CODE                           MD_IRQID_USIP10
+#define    IRQ_USIP11_CODE                           MD_IRQID_USIP11
+#define    IRQ_USIP12_CODE                           MD_IRQID_USIP12
+#define    IRQ_USIP13_CODE                           MD_IRQID_USIP13
+#define    IRQ_TX_NR_CC0_IRQ_CODE                    MD_IRQID_TX_NR_CC0_IRQ
+#define    IRQ_TX_NR_CC1_IRQ_CODE                    MD_IRQID_TX_NR_CC1_IRQ
+#define    IRQ_TX_NR_ERR_CC_IRQ_CODE                 MD_IRQID_TX_NR_ERR_CC_IRQ
+#define    IRQ_MDMCU_SPU_IRQ_CODE                    MD_IRQID_MDMCU_SPU_IRQ
+#define    IRQ_DEM_TRIG_PS_INT_LE_CODE               MD_IRQID_DEM_TRIG_PS_INT_LE
+#define    IRQ_ECT_CODE                              MD_IRQID_ECT
+#define    IRQ_MDMCU_BUS_DECERR_IRQ_CODE             MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define    IRQ_MDMCU_OSTD_THROTTLE_CODE              MD_IRQID_MDMCU_OSTD_THROTTLE
+#define    IRQ_SHAOLIN_OSTD_THROTTLE_CODE            MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define    IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE         MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define    IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_AP2MD_CONN_WF_CCIF_0_CODE             MD_IRQID_AP2MD_CONN_WF_CCIF_0
+#define    IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_AP2MD_CONN_WF_CCIF_1_CODE             MD_IRQID_AP2MD_CONN_WF_CCIF_1
+#define    IRQ_MDWDT_CODE                            MD_IRQID_MDWDT
+#define    IRQ_MDGDMA_FDMA0_2_CODE                   MD_IRQID_MDGDMA_FDMA0_2
+#define    IRQ_MDGDMA_FDMA1_CODE                     MD_IRQID_MDGDMA_FDMA1
+#define    IRQ_MDGDMA_FDMA3_CODE                     MD_IRQID_MDGDMA_FDMA3
+#define    IRQ_MDGDMA_FDMA4_CODE                     MD_IRQID_MDGDMA_FDMA4
+#define    IRQ_MDGDMA_HDMA0_1_CODE                   MD_IRQID_MDGDMA_HDMA0_1
+#define    IRQ_MDGDMA_HDMA2_3_CODE                   MD_IRQID_MDGDMA_HDMA2_3
+#define    IRQ_AP2MD_CCIF0_0_CODE                    MD_IRQID_AP2MD_CCIF0_0
+#define    IRQ_AP2MD_CCIF0_1_CODE                    MD_IRQID_AP2MD_CCIF0_1
+#define    IRQ_AP2MD_CCIF1_0_CODE                    MD_IRQID_AP2MD_CCIF1_0
+#define    IRQ_AP2MD_CCIF1_1_CODE                    MD_IRQID_AP2MD_CCIF1_1
+#define    IRQ_IEBIT_CHECK_IRQ0_CODE                 MD_IRQID_IEBIT_CHECK_IRQ0
+#define    IRQ_IEBIT_CHECK_IRQ1_CODE                 MD_IRQID_IEBIT_CHECK_IRQ1
+#define    IRQ_IEBIT_CHECK_IRQ2_CODE                 MD_IRQID_IEBIT_CHECK_IRQ2
+#define    IRQ_IEBIT_CHECK_IRQ3_CODE                 MD_IRQID_IEBIT_CHECK_IRQ3
+#define    IRQ_IEBIT_CHECK_IRQ4_CODE                 MD_IRQID_IEBIT_CHECK_IRQ4
+#define    IRQ_IEBIT_CHECK_IRQ5_CODE                 MD_IRQID_IEBIT_CHECK_IRQ5
+#define    IRQ_IEBIT_CHECK_IRQ6_CODE                 MD_IRQID_IEBIT_CHECK_IRQ6
+#define    IRQ_IEBIT_CHECK_IRQ7_CODE                 MD_IRQID_IEBIT_CHECK_IRQ7
+#define    IRQ_IEBIT_CHECK_IRQ8_CODE                 MD_IRQID_IEBIT_CHECK_IRQ8
+#define    IRQ_IEBIT_CHECK_IRQ9_CODE                 MD_IRQID_IEBIT_CHECK_IRQ9
+#define    IRQ_IEBIT_CHECK_IRQ10_CODE                MD_IRQID_IEBIT_CHECK_IRQ10
+#define    IRQ_IEBIT_CHECK_IRQ11_CODE                MD_IRQID_IEBIT_CHECK_IRQ11
+#define    IRQ_NRL2_HRT_CODE                         MD_IRQID_NRL2_HRT
+#define    IRQ_NRL2_NOTIF_CODE                       MD_IRQID_NRL2_NOTIF
+#define    IRQ_NRL2_EXCEP_CODE                       MD_IRQID_NRL2_EXCEP
+#define    IRQ_NRL2_DPMAIF_MD_CODE                   MD_IRQID_NRL2_DPMAIF_MD
+#define    IRQ_RXDFE_IRQ0_CODE                       MD_IRQID_RXDFE_IRQ0
+#define    IRQ_IDC_UART_TX_FORCE_ON_CODE             MD_IRQID_IDC_UART_TX_FORCE_ON
+#define    IRQ_RXDFE_IRQ2_CODE                       MD_IRQID_RXDFE_IRQ2
+#define    IRQ_RXDFE_IRQ3_CODE                       MD_IRQID_RXDFE_IRQ3
+#define    IRQ_AP2MD_CONN_BGF_CCIF_0_CODE            MD_IRQID_AP2MD_CONN_BGF_CCIF_0
+#define    IRQ_MD_RXDFE_BB_DUMP_CODE                 MD_IRQID_MD_RXDFE_BB_DUMP
+#define    IRQ_AP2MD_CONN_BGF_CCIF_1_CODE            MD_IRQID_AP2MD_CONN_BGF_CCIF_1
+#define    IRQ_TXCRP_CODE                            MD_IRQID_TXCRP
+#define    IRQ_CM_NR_IRQ_CODE                        MD_IRQID_CM_NR_IRQ
+#define    IRQ_CM_NR_ERR_IRQ_CODE                    MD_IRQID_CM_NR_ERR_IRQ
+#define    IRQ_L1_LTE_SLEEP_IRQ_CODE                 MD_IRQID_L1_LTE_SLEEP_IRQ
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define    IRQ_D_GDMA_0_IRQ_CODE                     MD_IRQID_D_GDMA_0_IRQ
+#define    IRQ_D_GDMA_1_IRQ_CODE                     MD_IRQID_D_GDMA_1_IRQ
+#define    IRQ_D_GDMA_2_IRQ_CODE                     MD_IRQID_D_GDMA_2_IRQ
+#define    IRQ_D_GDMA_3_IRQ_CODE                     MD_IRQID_D_GDMA_3_IRQ
+#define    IRQ_D_GDMA_4_IRQ_CODE                     MD_IRQID_D_GDMA_4_IRQ
+#define    IRQ_D_GDMA_5_IRQ_CODE                     MD_IRQID_D_GDMA_5_IRQ
+#define    IRQ_PLL_GEARHP_RDY_CODE                   MD_IRQID_PLL_GEARHP_RDY
+#define    IRQ_REQ_ABNORM_IRQ_CODE                   MD_IRQID_REQ_ABNORM_IRQ
+#define    IRQ_NRL2_DPMAIF_MDMCU_CODE                MD_IRQID_NRL2_DPMAIF_MDMCU
+#define    IRQ_AP2MD_APWDT_IRQ_CODE                  MD_IRQID_AP2MD_APWDT_IRQ
+#define    IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE          MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ
+#define    IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE           MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ
+#define    IRQ_DUMMY_PRIORITY_CODE_5                 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define    IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE             MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define    IRQ_L1M_PHY_LTMR_IRQ_0_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define    IRQ_L1M_PHY_LTMR_IRQ_1_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define    IRQ_L1M_PHY_LTMR_IRQ_2_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define    IRQ_L1M_PHY_LTMR_IRQ_3_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define    IRQ_L1M_PHY_LTMR_IRQ_4_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define    IRQ_L1M_PHY_LTMR_IRQ_5_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define    IRQ_L1M_PHY_LTMR_IRQ_6_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define    IRQ_L1M_PHY_LTMR_IRQ_7_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define    IRQ_DUMMY_PRIORITY_CODE_6                 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define    IRQ_L1_LTE_WAKEUP_IRQ_CODE                MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define    IRQ_TDD_WAKEUP_IRQ_CODE                   MD_IRQID_TDD_WAKEUP_IRQ
+#define    IRQ_TDD_TIMER_L1D_1_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define    IRQ_TDD_TIMER_L1D_2_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define    IRQ_RTR_SLT_0_IRQ_CODE                    MD_IRQID_RTR_SLT_0_IRQ
+#define    IRQ_RTR_SLT_1_IRQ_CODE                    MD_IRQID_RTR_SLT_1_IRQ
+#define    IRQ_FDD_SLP_IRQ_CODE                      MD_IRQID_FDD_SLP_IRQ
+#define    IRQ_IRDBG_MCU_INT_CODE                    MD_IRQID_IRDBG_MCU_INT
+#define    IRQ_MD_DVFS_CTRL_IRQ_0_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define    IRQ_MD_DVFS_CTRL_IRQ_1_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define    IRQ_NR_SLP_WAKEUP_CODE                    MD_IRQID_NR_SLP_WAKEUP
+#define    IRQ_NR_SLP_SLEEP_CODE                     MD_IRQID_NR_SLP_SLEEP
+#define    IRQ_NR_TIMER_ERR_CODE                     MD_IRQID_NR_TIMER_ERR
+#define    IRQ_TXBSRP_CODE                           MD_IRQID_TXBSRP
+#define    IRQ_TXDFE_D_CODE                          MD_IRQID_TXDFE_D
+#define    IRQ_NR_EVENTGEN_ERR_CODE                  MD_IRQID_NR_EVENTGEN_ERR
+#define    IRQ_AIRQ_PAD_CODE                         MD_IRQID_AIRQ_PAD
+#define    IRQ_CSSYS_FDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_FDD_CS_IRQ
+#define    IRQ_CSSYS_TDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_TDD_CS_IRQ
+#define    IRQ_CSSYS_LTE_CS_IRQ_CODE                 MD_IRQID_CSSYS_LTE_CS_IRQ
+#define    IRQ_CSSYS_1X_CS_IRQ_CODE                  MD_IRQID_CSSYS_1X_CS_IRQ
+#define    IRQ_CSSYS_DO_CS_IRQ_CODE                  MD_IRQID_CSSYS_DO_CS_IRQ
+#define    IRQ_PCIE_INTERRUPT_OUT_CODE               MD_IRQID_PCIE_INTERRUPT_OUT
+#define    IRQ_UCNT_SCH_IRQ_CODE                     MD_IRQID_UCNT_SCH_IRQ
+#define    IRQ_UCNT_ERR_IRQ_CODE                     MD_IRQID_UCNT_ERR_IRQ
+#define    IRQ_UCNT_ADJ_IRQ_CODE                     MD_IRQID_UCNT_ADJ_IRQ
+#define    IRQ_SL_WAITSLEEP_CODE                     MD_IRQID_SL_WAITSLEEP
+#define    IRQ_PTP_THERM_INT_INT_CODE                MD_IRQID_PTP_THERM_INT_INT
+#define    IRQ_PTP_FSM_INT_CODE                      MD_IRQID_PTP_FSM_INT
+#define    IRQ_AP2MD_DAPC_CODE                       MD_IRQID_AP2MD_DAPC
+#define    IRQ_AP2MD_CCIF2_CODE                      MD_IRQID_AP2MD_CCIF2
+#define    IRQ_AP2MD_UFS_CODE                        MD_IRQID_AP2MD_UFS
+#define    IRQ_SSUSB_INTERRUPT_OUT_CODE              MD_IRQID_SSUSB_INTERRUPT_OUT
+#define    IRQ_AP2MD_MSDC0_CODE                      MD_IRQID_AP2MD_MSDC0
+#define    IRQ_MIPI_IRQ_CODE                         MD_IRQID_MIPI_IRQ
+#define    IRQ_CONN_BT_ISOCH_CODE                    MD_IRQID_CONN_BT_ISOCH
+#define    IRQ_RMPU_CTIREIGIN_CODE                   MD_IRQID_RMPU_CTIREIGIN
+#define    IRQ_FREQM_IRQ_CODE                        MD_IRQID_FREQM_IRQ
+#define    IRQ_BT_CVSD_CODE                          MD_IRQID_BT_CVSD
+#define    IRQ_SW_LISR0_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_0
+#define    IRQ_SW_LISR1_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_1
+#define    IRQ_SW_LISR2_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_2
+#define    IRQ_SW_LISR3_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_3
+#define    IRQ_SW_LISR4_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_4
+#define    IRQ_SW_LISR5_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_5
+#define    IRQ_SW_LISR6_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_6
+#define    IRQ_SW_LISR7_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_7
+#define    IRQ_SW_LISR8_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_8
+#define    IRQ_SW_LISR9_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_9
+#define    IRQ_SW_LISR10_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_10
+#define    IRQ_SW_LISR11_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_11
+#define    IRQ_SW_LISR12_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_12
+#define    IRQ_SW_LISR13_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_13
+#define    IRQ_SW_LISR14_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_14
+#define    IRQ_SW_LISR15_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_15
+#define    IRQ_SW_LISR16_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_16
+#define    IRQ_SW_LISR17_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_17
+#define    IRQ_SW_LISR18_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_18
+#define    IRQ_SW_LISR19_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_19
+#define    IRQ_SW_LISR20_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_20
+#define    IRQ_SW_LISR21_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_21
+#define    IRQ_SW_LISR22_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_22
+#define    IRQ_SW_LISR23_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_23
+#define    IRQ_SW_LISR24_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_24
+#define    IRQ_SW_LISR25_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_25
+#define    IRQ_SW_LISR26_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_26
+#define    IRQ_SW_LISR27_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_27
+#define    IRQ_SW_LISR28_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_28
+#define    IRQ_SW_LISR29_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_29
+#define    IRQ_SW_LISR30_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_30
+#define    IRQ_SW_LISR31_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_31
+#define    IRQ_SW_LISR32_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_32
+#define    IRQ_SW_LISR33_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_33
+#define    IRQ_SW_LISR34_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_34
+#define    IRQ_SW_LISR35_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_35
+#define    IRQ_SW_LISR36_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_36
+#define    IRQ_SW_LISR37_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_37
+#define    IRQ_SW_LISR38_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_38
+#define    IRQ_SW_LISR39_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_39
+#define    IRQ_SW_LISR40_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_40
+#define    IRQ_SW_LISR41_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_41
+#define    IRQ_SW_LISR42_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_42
+#define    IRQ_SW_LISR43_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_43
+#define    IRQ_SW_LISR44_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_44
+#define    IRQ_SW_LISR45_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_45
+#define    IRQ_SW_LISR46_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_46
+#define    IRQ_SW_LISR47_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_47
+#define    IRQ_SW_LISR48_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_48
+#define    IRQ_SW_LISR49_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_49
+#define    IRQ_SW_LISR50_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_50
+#define    IRQ_SW_LISR51_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_51
+#define    IRQ_SW_LISR52_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_52
+#define    IRQ_SW_LISR53_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_53
+#define    IRQ_SW_LISR54_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_54
+#define    IRQ_SW_LISR55_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_55
+#define    IRQ_SW_LISR56_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_56
+#define    IRQ_SW_LISR57_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_57
+#define    IRQ_SW_LISR58_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_58
+#define    IRQ_SW_LISR59_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_59
+#define    IRQ_SW_LISR60_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_60
+#define    IRQ_SW_LISR61_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_61
+#define    IRQ_SW_LISR62_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_62
+#define    IRQ_SW_LISR63_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_63
+#define    IRQ_SW_LISR64_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_64
+#define    IRQ_CLDMA0_MD_IRQ_CODE                    MD_IRQID_CLDMA0_MD_IRQ
+#define    IRQ_CLDMA1_MD_IRQ_CODE                    MD_IRQID_CLDMA1_MD_IRQ
+#define    IRQ_CLDMA2_MD_IRQ_CODE                    MD_IRQID_CLDMA2_MD_IRQ
+#define    IRQ_CLDMA3_MD_IRQ_CODE                    MD_IRQID_CLDMA3_MD_IRQ
+#define    IRQ_MHCCIF_SAP2USIP_IRQ_CODE              MD_IRQID_MHCCIF_SAP2USIP_IRQ
+#define    IRQ_MHCCIF_SAP2MDMCU_IRQ_CODE             MD_IRQID_MHCCIF_SAP2MDMCU_IRQ
+#define    IRQ_NFI_MD_CODE                           MD_IRQID_NFI_MD
+#define    IRQ_CLDMA1_AP_INT_PCIE_MD_CODE            MD_IRQID_CLDMA1_AP_INT_PCIE_MD
+#define    IRQ_CLDMA3_AP_INT_PCIE_MD_CODE            MD_IRQID_CLDMA3_AP_INT_PCIE_MD
+#define    IRQ_DUMMY_PRIORITY_CODE_17                MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define    IRQ_DUMMY_PRIORITY_CODE_18                MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define    IRQ_DUMMY_PRIORITY_CODE_19                MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define    IRQ_DUMMY_PRIORITY_CODE_20                MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define    IRQ_DUMMY_PRIORITY_CODE_21                MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define    IRQ_DUMMY_PRIORITY_CODE_22                MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define    IRQ_DUMMY_PRIORITY_CODE_23                MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define    IRQ_DUMMY_PRIORITY_CODE_24                MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define    IRQ_DUMMY_PRIORITY_CODE_25                MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define    IRQ_DUMMY_PRIORITY_CODE_26                MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define    IRQ_DUMMY_PRIORITY_CODE_27                MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define    IRQ_DUMMY_PRIORITY_CODE_28                MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define    IRQ_DUMMY_PRIORITY_CODE_29                MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define    IRQ_DUMMY_PRIORITY_CODE_30                MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define    IRQ_SW_MODIS_MASE_HMU_CODE                IRQ_DUMMY_PRIORITY_CODE_25
+#define    IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE         IRQ_DUMMY_PRIORITY_CODE_26
+#define    IRQ_SW_MODIS_MASE_NR_TXLISR_CODE          IRQ_DUMMY_PRIORITY_CODE_27
+#define    IRQ_L1_PAE_SW_LISR0                       IRQ_DUMMY_PRIORITY_CODE_28
+#define    IRQ_L1_PAE_SW_LISR1                       IRQ_DUMMY_PRIORITY_CODE_29
+#define    IRQ_L1_PAE_SW_LISR2                       IRQ_DUMMY_PRIORITY_CODE_30
+#endif 
+
+
+/* IRQ Affinity Group Definition */
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+    /* Group0(0) */                                                                             0xFFE, \
+    /* Group1(1) */                                                                             0xFFD, \
+    /* Group2(2) */                                                                             0xFFB, \
+    /* Group3(3) */                                                                             0xFF7, \
+    /* Group4(4) */                                                                             0xFEF, \
+    /* Group5(5) */                                                                             0xFDF, \
+    /* Group6(6) */                                                                             0xFBF, \
+    /* Group7(7) */                                                                             0xF7F, \
+    /* Group8(8) */                                                                             0xEFF, \
+    /* Group9(9) */                                                                             0xDFF, \
+    /* Group10(10) */                                                                           0xBFF, \
+    /* Group11(11) */                                                                           0x7FF, \
+    /* Group12(1,4) */                                                                          0xFED, \
+    /* Group13(0,1,2) */                                                                        0xFF8, \
+    /* Group14(3,6,9) */                                                                        0xDB7, \
+    /* Group15(0,3,6,9) */                                                                      0xDB6, \
+    /* Group16(3,4,6,7,9,10) */                                                                 0x927, \
+    /* Group17(0,1,2,3,4,6,7,9,10) */                                                           0x920, \
+    /* Group18(3,4,5,6,7,8,9,10,11) */                                                          0x007, \
+    /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */                                                    0x000, \
+    /* Group20(3,4,6,7,9,10)        -> Reserved for NR runtime change affinity */               0x927, \
+    /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */               0x007, \
+    /* Group22(2)                   -> Reserved for LTE runtime change affinity */              0xFFB, \
+    /* Group23(0,2,3,4,6,7,9,10)    -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */  0x922, \
+    /* Group24(3,6,7,9,10)          -> Temp solution for IRQ0xEE to not preempt NR RX IRQs */   0x937, \
+    /* Group25(0,3,5,6,7,8,9,11)    -> Workaround for Serdes HW bug */                          0x416, \
+    /* Group26(0,2,3,6,7,9,10)      -> Workaround for IRQ0x80 pending hard affinity HRT IRQs */ 0x932, \
+    /* Group27 */                                                                               0xFFF, \
+    /* Group28 */                                                                               0xFFF, \
+    /* Group29 */                                                                               0xFFF, \
+    /* Group30 */                                                                               0xFFF, \
+    /* Group31 */                                                                               0xFFF,
+#endif
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions - 
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0         0   //(0)
+#define IRQ_AFFINITY_GROUP_VPE1         1   //(1)
+#define IRQ_AFFINITY_GROUP_VPE2         2   //(2)
+#define IRQ_AFFINITY_GROUP_VPE3         3   //(3)
+#define IRQ_AFFINITY_GROUP_VPE4         4   //(4)
+#define IRQ_AFFINITY_GROUP_VPE5         5   //(5)
+#define IRQ_AFFINITY_GROUP_VPE6         6   //(6)
+#define IRQ_AFFINITY_GROUP_VPE7         7   //(7)
+#define IRQ_AFFINITY_GROUP_VPE8	        8   //(8)
+#define IRQ_AFFINITY_GROUP_VPE9         9   //(9)
+#define IRQ_AFFINITY_GROUP_VPE10        10  //(10)
+#define IRQ_AFFINITY_GROUP_VPE11        11  //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4     12  //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0    13  //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR    14  //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP   15  //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR       16  //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP      17  //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR      18  //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE      19  //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+#define MAX_NUM_TASKS          256
+#define MAX_HISR_PRIORITY      2
+
+typedef enum
+{
+    VPE_STATUS_LISR_HIGHEST      = 0,
+    VPE_STATUS_LISR_LOWEST       = 342,
+    VPE_STATUS_HISR_TASK_HIGHEST = 512,
+    VPE_STATUS_HISR_TASK_LOWEST  = VPE_STATUS_HISR_TASK_HIGHEST + MAX_NUM_TASKS + MAX_HISR_PRIORITY, 
+    VPE_STATUS_END               = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_CHIP10992_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_CHIP10992_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_CHIP10992_SW_Handle.h
new file mode 100644
index 0000000..504958f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_CHIP10992_SW_Handle.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_CHIP10992_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   CHIP10992
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE0  = Karthigeyan Reddy
+      SW_TRIGGER_CODE1  = Karthigeyan Reddy
+      SW_TRIGGER_CODE2  = Karthigeyan Reddy
+      SW_TRIGGER_CODE3  = Karthigeyan Reddy
+      SW_TRIGGER_CODE4  = Karthigeyan Reddy
+      SW_TRIGGER_CODE5  = Karthigeyan Reddy
+      SW_TRIGGER_CODE6  = Zengling Jin
+      SW_TRIGGER_CODE7  = Zengling Jin
+      SW_TRIGGER_CODE8  = Zengling Jin
+      SW_TRIGGER_CODE9  = Cruze Yu
+      SW_TRIGGER_CODE10 = Cruze Yu
+      SW_TRIGGER_CODE11 = Cruze Yu
+      SW_TRIGGER_CODE12 = Cruze Yu
+      SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+      SW_TRIGGER_CODE14 = HW Jheng
+      SW_TRIGGER_CODE15 = Frank Hu
+      SW_TRIGGER_CODE16 = KH Hsiao
+      SW_TRIGGER_CODE17 = Deepti Varadarajan
+      SW_TRIGGER_CODE18 = Owen Ho
+      SW_TRIGGER_CODE19 = Owen Ho
+      SW_TRIGGER_CODE20 = Owen Ho
+      SW_TRIGGER_CODE21 = Owen Ho
+      SW_TRIGGER_CODE22 = Jun-Ying Huang
+      SW_TRIGGER_CODE23 = Jun-Ying Huang
+      SW_TRIGGER_CODE24 = Jun-Ying Huang
+      SW_TRIGGER_CODE25 = Jun-Ying Huang
+      SW_TRIGGER_CODE26 = Wade Huang
+      SW_TRIGGER_CODE27 = Tee-Yuen Chun
+      SW_TRIGGER_CODE28 = YY Hsieh 
+      SW_TRIGGER_CODE29 = Hamilton Liang
+      SW_TRIGGER_CODE30 = HW Jheng
+      SW_TRIGGER_CODE31 = Weimin Zeng
+      SW_TRIGGER_CODE32 = Weimin Zeng
+      SW_TRIGGER_CODE33 = Jocobrian Chang
+      SW_TRIGGER_CODE34 = JiaHong Hsu
+      SW_TRIGGER_CODE35 = Cheng-Long Wu
+      SW_TRIGGER_CODE36 = Cheng-Long Wu
+      SW_TRIGGER_CODE37 = Jocobrian Chang
+      SW_TRIGGER_CODE38 = Jocobrian Chang
+      SW_TRIGGER_CODE39 = Jocobrian Chang
+      SW_TRIGGER_CODE40 = Shu-Wei Ho
+      SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+      SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+  */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6297.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6297.h
new file mode 100644
index 0000000..78b26fa
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6297.h
@@ -0,0 +1,801 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6297.h
+ *
+ * Project:
+ * --------
+ *   TATAKA
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6297_H__
+#define __INTRCTRL_MT6297_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+/* Wait mode enable define */
+//#define __MDCIRQ_WAIT_MODE_ENABLE__
+
+/*CIRQ Interrupt Sources*/
+
+#define NUM_IRQ_SOURCES          (368)
+
+#define    IRQ_USIM0_CODE                            MD_IRQID_USIM0       
+#define    IRQ_USIM1_CODE                            MD_IRQID_USIM1       
+#define    IRQ_TDMA_CTIRQ1_CODE                      MD_IRQID_TDMA_CTIRQ1
+#define    IRQ_TDMA_CTIRQ2_CODE                      MD_IRQID_TDMA_CTIRQ2
+#define    IRQ_TDMA_CTIRQ3_CODE                      MD_IRQID_TDMA_CTIRQ3
+#define    IRQ_TDMA_WAKEUP_IRQ_CODE                  MD_IRQID_TDMA_WAKEUP_IRQ
+#define    IRQ_OST_CODE                              MD_IRQID_OST          
+#define    IRQ_MDRTT_CODE                            MD_IRQID_MDRTT
+#define    IRQ_MDEVDO_CODE                           MD_IRQID_MDEVDO
+#define    IRQ_ULSP_LOG_MCU_RT_INT_CODE              MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define    IRQ_ULSP_LOG_MCU_OD_INT_CODE              MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define    IRQ_ULSP_LOG_DSP4G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define    IRQ_ULSP_LOG_DSP4G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define    IRQ_ULSP_LOG_DSP5G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define    IRQ_ULSP_LOG_DSP5G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define    IRQ_SHARE_D12MINT1_CODE                   MD_IRQID_SHARE_D12MINT1
+#define    IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE        MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define    IRQ_AIRQ_SERDES_CODE                      MD_IRQID_AIRQ_SERDES
+#define    IRQ_AIRQ_COS_CODE                         MD_IRQID_AIRQ_COS
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define    IRQ_PPPHA_ENC0_INT_CODE                   MD_IRQID_PPPHA_ENC0_INT
+#define    IRQ_PPPHA_ENC1_INT_CODE                   MD_IRQID_PPPHA_ENC1_INT
+#define    IRQ_PPPHA_DEC0_INT_CODE                   MD_IRQID_PPPHA_DEC0_INT
+#define    IRQ_PPPHA_DEC1_INT_CODE                   MD_IRQID_PPPHA_DEC1_INT
+#define    IRQ_CS_NR_IRQ_CODE                        MD_IRQID_CS_NR_IRQ
+#define    IRQ_CS_NR_ERR_IRQ_CODE                    MD_IRQID_CS_NR_ERR_IRQ
+#define    IRQ_SDF_OVERFLOW_IRQ_CODE                 MD_IRQID_SDF_OVERFLOW_IRQ
+#define    IRQ_MCUMMU_INT_CODE                       MD_IRQID_MCUMMU_INT
+#define    IRQ_BIGRAM_0_IRQ_0_CODE                   MD_IRQID_BIGRAM_0_IRQ_0
+#define    IRQ_COS_PREP_INT_CODE                     MD_IRQID_COS_PREP_INT
+#define    IRQ_TRACE_INT_CODE                        MD_IRQID_TRACE_INT
+#define    IRQ_NR_TIMER_IRQ0_CODE                    MD_IRQID_NR_TIMER_IRQ0
+#define    IRQ_NR_TIMER_IRQ1_CODE                    MD_IRQID_NR_TIMER_IRQ1
+#define    IRQ_NR_TIMER_IRQ2_CODE                    MD_IRQID_NR_TIMER_IRQ2
+#define    IRQ_NR_TIMER_IRQ3_CODE                    MD_IRQID_NR_TIMER_IRQ3
+#define    IRQ_NR_TIMER_IRQ4_CODE                    MD_IRQID_NR_TIMER_IRQ4
+#define    IRQ_NR_TIMER_IRQ5_CODE                    MD_IRQID_NR_TIMER_IRQ5
+#define    IRQ_NR_TIMER_IRQ6_CODE                    MD_IRQID_NR_TIMER_IRQ6
+#define    IRQ_NR_TIMER_IRQ7_CODE                    MD_IRQID_NR_TIMER_IRQ7
+#define    IRQ_NR_TIMER_IRQ8_CODE                    MD_IRQID_NR_TIMER_IRQ8
+#define    IRQ_NR_TIMER_IRQ9_CODE                    MD_IRQID_NR_TIMER_IRQ9
+#define    IRQ_NR_TIMER_IRQ10_CODE                   MD_IRQID_NR_TIMER_IRQ10
+#define    IRQ_NR_TIMER_IRQ11_CODE                   MD_IRQID_NR_TIMER_IRQ11
+#define    IRQ_NR_TIMER_IRQ12_CODE                   MD_IRQID_NR_TIMER_IRQ12
+#define    IRQ_NR_TIMER_IRQ13_CODE                   MD_IRQID_NR_TIMER_IRQ13
+#define    IRQ_NR_TIMER_IRQ14_CODE                   MD_IRQID_NR_TIMER_IRQ14
+#define    IRQ_NR_TIMER_IRQ15_CODE                   MD_IRQID_NR_TIMER_IRQ15
+#define    IRQ_NR_TIMER_IRQ16_CODE                   MD_IRQID_NR_TIMER_IRQ16
+#define    IRQ_NR_TIMER_IRQ17_CODE                   MD_IRQID_NR_TIMER_IRQ17
+#define    IRQ_NR_TIMER_IRQ18_CODE                   MD_IRQID_NR_TIMER_IRQ18
+#define    IRQ_NR_TIMER_IRQ19_CODE                   MD_IRQID_NR_TIMER_IRQ19
+#define    IRQ_NR_TIMER_IRQ20_CODE                   MD_IRQID_NR_TIMER_IRQ20
+#define    IRQ_NR_TIMER_IRQ21_CODE                   MD_IRQID_NR_TIMER_IRQ21
+#define    IRQ_NR_TIMER_IRQ22_CODE                   MD_IRQID_NR_TIMER_IRQ22
+#define    IRQ_NR_TIMER_IRQ23_CODE                   MD_IRQID_NR_TIMER_IRQ23
+#define    IRQ_NR_TIMER_IRQ24_CODE                   MD_IRQID_NR_TIMER_IRQ24
+#define    IRQ_NR_TIMER_IRQ25_CODE                   MD_IRQID_NR_TIMER_IRQ25
+#define    IRQ_NR_TIMER_IRQ26_CODE                   MD_IRQID_NR_TIMER_IRQ26
+#define    IRQ_NR_TIMER_IRQ27_CODE                   MD_IRQID_NR_TIMER_IRQ27
+#define    IRQ_NR_TIMER_IRQ28_CODE                   MD_IRQID_NR_TIMER_IRQ28
+#define    IRQ_NR_TIMER_IRQ29_CODE                   MD_IRQID_NR_TIMER_IRQ29
+#define    IRQ_NR_TIMER_IRQ30_CODE                   MD_IRQID_NR_TIMER_IRQ30
+#define    IRQ_NR_TIMER_IRQ31_CODE                   MD_IRQID_NR_TIMER_IRQ31
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define    IRQ_NR_TIMER_CNTDN_IRQ0_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define    IRQ_NR_TIMER_CNTDN_IRQ1_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define    IRQ_NR_TIMER_CNTDN_IRQ2_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define    IRQ_NR_TIMER_CNTDN_IRQ3_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define    IRQ_NR_EVENTGEN_SPU_CODE                  MD_IRQID_NR_EVENTGEN_SPU
+#define    IRQ_SI_CM_ERR_CODE                        MD_IRQID_SI_CM_ERR
+#define    IRQ_SI_CM_PCINT_CODE                      MD_IRQID_SI_CM_PCINT
+#define    IRQ_MDM2C_U3G_CODE                        MD_IRQID_MDM2C_U3G
+#define    IRQ_RAKE_CMIF_M2C_IRQ_0_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define    IRQ_RAKE_CMIF_M2C_IRQ_1_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define    IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define    IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define    IRQ_RAKE_CMIF_PD_DO_IRQ_CODE              MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define    IRQ_MDMCU_BUSMON_MATCH_STS_CODE           MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define    IRQ_MDINFRA_BUSMON_MATCH_STS_CODE         MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define    IRQ_ELMTOP_EMI_IRQ_CODE                   MD_IRQID_ELMTOP_EMI_IRQ
+#define    IRQ_ELM_DMA_IRQ_CODE                      MD_IRQID_ELM_DMA_IRQ
+#define    IRQ_BUSMPU_IRQ_CODE                       MD_IRQID_BUSMPU_IRQ
+#define    IRQ_ST1X_CPINT_CODE                       MD_IRQID_ST1X_CPINT
+#define    IRQ_ST1x_HALF_CPINT_CODE                  MD_IRQID_ST1x_HALF_CPINT
+#define    IRQ_ST1x_CFG_CPINT_CODE                   MD_IRQID_ST1x_CFG_CPINT
+#define    IRQ_ST1x_WAKEUP_IRQ_CODE                  MD_IRQID_ST1x_WAKEUP_IRQ
+#define    IRQ_STDO_CPINT_CODE                       MD_IRQID_STDO_CPINT
+#define    IRQ_STDO_HALF_CPINT_CODE                  MD_IRQID_STDO_HALF_CPINT
+#define    IRQ_STDO_CFG_CPINT_CODE                   MD_IRQID_STDO_CFG_CPINT
+#define    IRQ_STDO_WAKEUP_IRQ_CODE                  MD_IRQID_STDO_WAKEUP_IRQ
+#define    IRQ_UART_MD0_CODE                         MD_IRQID_UART_MD0    
+#define    IRQ_UART_MD1_CODE                         MD_IRQID_UART_MD1    
+#define    IRQ_EINT0_CODE                            MD_IRQID_EINT0       
+#define    IRQ_EINT1_CODE                            MD_IRQID_EINT1       
+#define    IRQ_EINT2_CODE                            MD_IRQID_EINT2       
+#define    IRQ_EINT3_CODE                            MD_IRQID_EINT3      
+#define    IRQ_EINT_SHARE_CODE                       MD_IRQID_EINT_SHARE  
+#define    IRQ_GPTM1_CODE                            MD_IRQID_GPTM1        
+#define    IRQ_GPTM2_CODE                            MD_IRQID_GPTM2        
+#define    IRQ_GPTM3_CODE                            MD_IRQID_GPTM3        
+#define    IRQ_GPTM4_CODE                            MD_IRQID_GPTM4        
+#define    IRQ_GPTM5_CODE                            MD_IRQID_GPTM5       
+#define    IRQ_GPTM6_CODE                            MD_IRQID_GPTM6       
+#define    IRQ_GPTM7_CODE                            MD_IRQID_GPTM7       
+#define    IRQ_GPTM8_CODE                            MD_IRQID_GPTM8      
+#define    IRQ_GPTM9_CODE                            MD_IRQID_GPTM9        
+#define    IRQ_GPTM10_CODE                           MD_IRQID_GPTM10        
+#define    IRQ_GPTM11_CODE                           MD_IRQID_GPTM11      
+#define    IRQ_IDC_PM_INT_CODE                       MD_IRQID_IDC_PM_INT
+#define    IRQ_IDC_UART_IRQ_CODE                     MD_IRQID_IDC_UART_IRQ
+#define    IRQ_DUMMY_PRIORITY_CODE_0                 MD_IRQID_DUMMY_PRIORITY_IRQ0
+#define    IRQ_CLDMA0_MD_IRQ_CODE                    MD_IRQID_CLDMA0_MD_IRQ
+#define    IRQ_DUMMY_PRIORITY_CODE_1                 MD_IRQID_DUMMY_PRIORITY_IRQ1
+#define    IRQ_CLDMA1_MD_IRQ_CODE                    MD_IRQID_CLDMA1_MD_IRQ
+#define    IRQ_MDINFRA_BUS_DECERROR_CODE             MD_IRQID_MDINFRA_BUS_DECERROR     
+#define    IRQ_I2C_TOP_INT_CODE                      MD_IRQID_I2C_TOP_INT
+#define    IRQ_SOE_CODE                              MD_IRQID_SOE         
+#define    IRQ_ABM_INT_CODE                          MD_IRQID_ABM_INT
+#define    IRQ_ABM_ERROR_INT_CODE                    MD_IRQID_ABM_ERROR_INT
+#define    IRQ_USIP0_CODE                            MD_IRQID_USIP0
+#define    IRQ_USIP1_CODE                            MD_IRQID_USIP1
+#define    IRQ_USIP2_CODE                            MD_IRQID_USIP2
+#define    IRQ_USIP3_CODE                            MD_IRQID_USIP3
+#define    IRQ_USIP4_CODE                            MD_IRQID_USIP4
+#define    IRQ_USIP5_CODE                            MD_IRQID_USIP5
+#define    IRQ_USIP6_CODE                            MD_IRQID_USIP6
+#define    IRQ_USIP7_CODE                            MD_IRQID_USIP7
+#define    IRQ_USIP8_CODE                            MD_IRQID_USIP8
+#define    IRQ_USIP9_CODE                            MD_IRQID_USIP9
+#define    IRQ_USIP10_CODE                           MD_IRQID_USIP10
+#define    IRQ_USIP11_CODE                           MD_IRQID_USIP11
+#define    IRQ_USIP12_CODE                           MD_IRQID_USIP12
+#define    IRQ_USIP13_CODE                           MD_IRQID_USIP13
+#define    IRQ_TX_NR_CC0_IRQ_CODE                    MD_IRQID_TX_NR_CC0_IRQ
+#define    IRQ_TX_NR_CC1_IRQ_CODE                    MD_IRQID_TX_NR_CC1_IRQ
+#define    IRQ_TX_NR_ERR_CC_IRQ_CODE                 MD_IRQID_TX_NR_ERR_CC_IRQ
+#define    IRQ_MDMCU_SPU_IRQ_CODE                    MD_IRQID_MDMCU_SPU_IRQ
+#define    IRQ_DEM_TRIG_PS_INT_LE_CODE               MD_IRQID_DEM_TRIG_PS_INT_LE
+#define    IRQ_ECT_CODE                              MD_IRQID_ECT
+#define    IRQ_MDMCU_BUS_DECERR_IRQ_CODE             MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define    IRQ_MDMCU_OSTD_THROTTLE_CODE              MD_IRQID_MDMCU_OSTD_THROTTLE
+#define    IRQ_SHAOLIN_OSTD_THROTTLE_CODE            MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define    IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE         MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define    IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_MCORE1_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_MCORE1_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_VCORE1_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_VCORE1_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_MDWDT_CODE                            MD_IRQID_MDWDT        
+#define    IRQ_MDGDMA0_CODE                          MD_IRQID_MDGDMA0     
+#define    IRQ_MDGDMA1_CODE                          MD_IRQID_MDGDMA1     
+#define    IRQ_MDGDMA2_CODE                          MD_IRQID_MDGDMA2     
+#define    IRQ_MDGDMA3_CODE                          MD_IRQID_MDGDMA3
+#define    IRQ_MDGDMA4_CODE                          MD_IRQID_MDGDMA4
+#define    IRQ_MDGDMA5_CODE                          MD_IRQID_MDGDMA5
+#define    IRQ_AP2MD_CCIF0_0_CODE                    MD_IRQID_AP2MD_CCIF0_0
+#define    IRQ_AP2MD_CCIF0_1_CODE                    MD_IRQID_AP2MD_CCIF0_1
+#define    IRQ_AP2MD_CCIF1_0_CODE                    MD_IRQID_AP2MD_CCIF1_0
+#define    IRQ_AP2MD_CCIF1_1_CODE                    MD_IRQID_AP2MD_CCIF1_1
+#define    IRQ_IEBIT_CHECK_IRQ0_CODE                 MD_IRQID_IEBIT_CHECK_IRQ0
+#define    IRQ_IEBIT_CHECK_IRQ1_CODE                 MD_IRQID_IEBIT_CHECK_IRQ1
+#define    IRQ_IEBIT_CHECK_IRQ2_CODE                 MD_IRQID_IEBIT_CHECK_IRQ2
+#define    IRQ_IEBIT_CHECK_IRQ3_CODE                 MD_IRQID_IEBIT_CHECK_IRQ3
+#define    IRQ_IEBIT_CHECK_IRQ4_CODE                 MD_IRQID_IEBIT_CHECK_IRQ4
+#define    IRQ_IEBIT_CHECK_IRQ5_CODE                 MD_IRQID_IEBIT_CHECK_IRQ5
+#define    IRQ_IEBIT_CHECK_IRQ6_CODE                 MD_IRQID_IEBIT_CHECK_IRQ6
+#define    IRQ_IEBIT_CHECK_IRQ7_CODE                 MD_IRQID_IEBIT_CHECK_IRQ7
+#define    IRQ_IEBIT_CHECK_IRQ8_CODE                 MD_IRQID_IEBIT_CHECK_IRQ8
+#define    IRQ_IEBIT_CHECK_IRQ9_CODE                 MD_IRQID_IEBIT_CHECK_IRQ9
+#define    IRQ_IEBIT_CHECK_IRQ10_CODE                MD_IRQID_IEBIT_CHECK_IRQ10
+#define    IRQ_IEBIT_CHECK_IRQ11_CODE                MD_IRQID_IEBIT_CHECK_IRQ11
+#define    IRQ_NRL2_HRT_CODE                         MD_IRQID_NRL2_HRT
+#define    IRQ_NRL2_NOTIF_CODE                       MD_IRQID_NRL2_NOTIF
+#define    IRQ_NRL2_EXCEP_CODE                       MD_IRQID_NRL2_EXCEP
+#define    IRQ_NRL2_DPMAIF_MD_CODE                   MD_IRQID_NRL2_DPMAIF_MD
+#define    IRQ_RXDFE_IRQ0_CODE                       MD_IRQID_RXDFE_IRQ0
+#define    IRQ_RXDFE_IRQ1_CODE                       MD_IRQID_RXDFE_IRQ1
+#define    IRQ_RXDFE_IRQ2_CODE                       MD_IRQID_RXDFE_IRQ2
+#define    IRQ_RXDFE_IRQ3_CODE                       MD_IRQID_RXDFE_IRQ3
+#define    IRQ_RXDFE_IRQ4_CODE                       MD_IRQID_RXDFE_IRQ4
+#define    IRQ_MD_RXDFE_BB_DUMP_CODE                 MD_IRQID_MD_RXDFE_BB_DUMP
+#define    IRQ_RXDFE_IRQ6_CODE                       MD_IRQID_RXDFE_IRQ6
+#define    IRQ_TXCRP_CODE                            MD_IRQID_TXCRP
+#define    IRQ_CM_NR_IRQ_CODE                        MD_IRQID_CM_NR_IRQ
+#define    IRQ_CM_NR_ERR_IRQ_CODE                    MD_IRQID_CM_NR_ERR_IRQ
+#define    IRQ_L1_LTE_SLEEP_IRQ_CODE                 MD_IRQID_L1_LTE_SLEEP_IRQ
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define    IRQ_D_GDMA_0_IRQ_CODE                     MD_IRQID_D_GDMA_0_IRQ
+#define    IRQ_D_GDMA_1_IRQ_CODE                     MD_IRQID_D_GDMA_1_IRQ
+#define    IRQ_D_GDMA_2_IRQ_CODE                     MD_IRQID_D_GDMA_2_IRQ
+#define    IRQ_D_GDMA_3_IRQ_CODE                     MD_IRQID_D_GDMA_3_IRQ
+#define    IRQ_D_GDMA_4_IRQ_CODE                     MD_IRQID_D_GDMA_4_IRQ
+#define    IRQ_D_GDMA_5_IRQ_CODE                     MD_IRQID_D_GDMA_5_IRQ
+#define    IRQ_PLL_GEARHP_RDY_CODE                   MD_IRQID_PLL_GEARHP_RDY
+#define    IRQ_REQ_ABNORM_IRQ_CODE                   MD_IRQID_REQ_ABNORM_IRQ
+#define    IRQ_NRL2_DPMAIF_MDMCU_CODE                MD_IRQID_NRL2_DPMAIF_MDMCU
+#define    IRQ_AP2MD_APWDT_IRQ_CODE                  MD_IRQID_AP2MD_APWDT_IRQ
+#define    IRQ_DUMMY_PRIORITY_CODE_3                 MD_IRQID_DUMMY_PRIORITY_IRQ3
+#define    IRQ_DUMMY_PRIORITY_CODE_4                 MD_IRQID_DUMMY_PRIORITY_IRQ4
+#define    IRQ_DUMMY_PRIORITY_CODE_5                 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define    IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE             MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define    IRQ_L1M_PHY_LTMR_IRQ_0_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define    IRQ_L1M_PHY_LTMR_IRQ_1_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define    IRQ_L1M_PHY_LTMR_IRQ_2_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define    IRQ_L1M_PHY_LTMR_IRQ_3_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define    IRQ_L1M_PHY_LTMR_IRQ_4_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define    IRQ_L1M_PHY_LTMR_IRQ_5_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define    IRQ_L1M_PHY_LTMR_IRQ_6_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define    IRQ_L1M_PHY_LTMR_IRQ_7_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define    IRQ_DUMMY_PRIORITY_CODE_6                 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define    IRQ_L1_LTE_WAKEUP_IRQ_CODE                MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define    IRQ_TDD_WAKEUP_IRQ_CODE                   MD_IRQID_TDD_WAKEUP_IRQ
+#define    IRQ_TDD_TIMER_L1D_1_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define    IRQ_TDD_TIMER_L1D_2_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define    IRQ_RTR_SLT_0_IRQ_CODE                    MD_IRQID_RTR_SLT_0_IRQ
+#define    IRQ_RTR_SLT_1_IRQ_CODE                    MD_IRQID_RTR_SLT_1_IRQ
+#define    IRQ_FDD_SLP_IRQ_CODE                      MD_IRQID_FDD_SLP_IRQ
+#define    IRQ_IRDBG_MCU_INT_CODE                    MD_IRQID_IRDBG_MCU_INT
+#define    IRQ_MD_DVFS_CTRL_IRQ_0_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define    IRQ_MD_DVFS_CTRL_IRQ_1_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define    IRQ_NR_SLP_WAKEUP_CODE                    MD_IRQID_NR_SLP_WAKEUP
+#define    IRQ_NR_SLP_SLEEP_CODE                     MD_IRQID_NR_SLP_SLEEP
+#define    IRQ_NR_TIMER_ERR_CODE                     MD_IRQID_NR_TIMER_ERR
+#define    IRQ_TXBSRP_CODE                           MD_IRQID_TXBSRP
+#define    IRQ_TXDFE_D_CODE                          MD_IRQID_TXDFE_D
+#define    IRQ_NR_EVENTGEN_ERR_CODE                  MD_IRQID_NR_EVENTGEN_ERR
+#define    IRQ_AIRQ_PAD_CODE                         MD_IRQID_AIRQ_PAD
+#define    IRQ_CSSYS_FDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_FDD_CS_IRQ
+#define    IRQ_CSSYS_TDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_TDD_CS_IRQ
+#define    IRQ_CSSYS_LTE_CS_IRQ_CODE                 MD_IRQID_CSSYS_LTE_CS_IRQ
+#define    IRQ_CSSYS_1X_CS_IRQ_CODE                  MD_IRQID_CSSYS_1X_CS_IRQ
+#define    IRQ_CSSYS_DO_CS_IRQ_CODE                  MD_IRQID_CSSYS_DO_CS_IRQ
+#define    IRQ_PCIE_INTERRUPT_OUT_CODE               MD_IRQID_PCIE_INTERRUPT_OUT
+#define    IRQ_UCNT_SCH_IRQ_CODE                     MD_IRQID_UCNT_SCH_IRQ
+#define    IRQ_UCNT_ADJ_IRQ_CODE                     MD_IRQID_UCNT_ADJ_IRQ
+#define    IRQ_UCNT_ERR_IRQ_CODE                     MD_IRQID_UCNT_ERR_IRQ
+#define    IRQ_NFI_MD_CODE                           MD_IRQID_NFI_MD
+#define    IRQ_PTP_THERM_INT_INT_CODE                MD_IRQID_PTP_THERM_INT_INT
+#define    IRQ_PTP_FSM_INT_CODE                      MD_IRQID_PTP_FSM_INT
+#define    IRQ_MHCCIF_SAP2USIP_IRQ_CODE              MD_IRQID_MHCCIF_SAP2USIP_IRQ
+#define    IRQ_MHCCIF_SAP2MDMCU_IRQ_CODE             MD_IRQID_MHCCIF_SAP2MDMCU_IRQ
+#define    IRQ_MUSB_INTERRUPT_OUT_CODE               MD_IRQID_MUSB_INTERRUPT_OUT
+#define    IRQ_SSUSB_INTERRUPT_OUT_CODE              MD_IRQID_SSUSB_INTERRUPT_OUT
+#define    IRQ_AP2MD_MSDC0_CODE                      MD_IRQID_AP2MD_MSDC0
+#define    IRQ_MIPI_READ_IRQ_CODE                    MD_IRQID_MIPI_READ_IRQ
+#define    IRQ_CLDMA2_MD_IRQ_CODE                    MD_IRQID_CLDMA2_MD_IRQ
+#define    IRQ_RMPU_CTIREIGIN_CODE                   MD_IRQID_RMPU_CTIREIGIN
+#define    IRQ_FREQM_IRQ_CODE                        MD_IRQID_FREQM_IRQ
+#define    IRQ_DUMMY_PRIORITY_CODE_7                 MD_IRQID_DUMMY_PRIORITY_IRQ7
+#define    IRQ_SW_LISR0_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_0
+#define    IRQ_SW_LISR1_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_1
+#define    IRQ_SW_LISR2_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_2
+#define    IRQ_SW_LISR3_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_3
+#define    IRQ_SW_LISR4_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_4
+#define    IRQ_SW_LISR5_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_5
+#define    IRQ_SW_LISR6_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_6
+#define    IRQ_SW_LISR7_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_7
+#define    IRQ_SW_LISR8_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_8
+#define    IRQ_SW_LISR9_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_9
+#define    IRQ_SW_LISR10_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_10
+#define    IRQ_SW_LISR11_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_11
+#define    IRQ_SW_LISR12_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_12
+#define    IRQ_SW_LISR13_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_13
+#define    IRQ_SW_LISR14_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_14
+#define    IRQ_SW_LISR15_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_15
+#define    IRQ_SW_LISR16_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_16
+#define    IRQ_SW_LISR17_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_17
+#define    IRQ_SW_LISR18_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_18
+#define    IRQ_SW_LISR19_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_19
+#define    IRQ_SW_LISR20_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_20
+#define    IRQ_SW_LISR21_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_21
+#define    IRQ_SW_LISR22_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_22
+#define    IRQ_SW_LISR23_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_23
+#define    IRQ_SW_LISR24_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_24
+#define    IRQ_SW_LISR25_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_25
+#define    IRQ_SW_LISR26_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_26
+#define    IRQ_SW_LISR27_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_27
+#define    IRQ_SW_LISR28_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_28
+#define    IRQ_SW_LISR29_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_29
+#define    IRQ_SW_LISR30_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_30
+#define    IRQ_SW_LISR31_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_31
+#define    IRQ_SW_LISR32_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_32
+#define    IRQ_SW_LISR33_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_33
+#define    IRQ_SW_LISR34_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_34
+#define    IRQ_SW_LISR35_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_35
+#define    IRQ_SW_LISR36_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_36
+#define    IRQ_SW_LISR37_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_37
+#define    IRQ_SW_LISR38_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_38
+#define    IRQ_SW_LISR39_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_39
+#define    IRQ_SW_LISR40_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_40
+#define    IRQ_SW_LISR41_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_41
+#define    IRQ_SW_LISR42_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_42
+#define    IRQ_SW_LISR43_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_43
+#define    IRQ_SW_LISR44_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_44
+#define    IRQ_SW_LISR45_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_45
+#define    IRQ_SW_LISR46_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_46
+#define    IRQ_SW_LISR47_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_47
+#define    IRQ_SW_LISR48_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_48
+#define    IRQ_SW_LISR49_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_49
+#define    IRQ_SW_LISR50_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_50
+#define    IRQ_SW_LISR51_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_51
+#define    IRQ_SW_LISR52_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_52
+#define    IRQ_SW_LISR53_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_53
+#define    IRQ_SW_LISR54_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_54
+#define    IRQ_SW_LISR55_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_55
+#define    IRQ_SW_LISR56_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_56
+#define    IRQ_SW_LISR57_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_57
+#define    IRQ_SW_LISR58_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_58
+#define    IRQ_SW_LISR59_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_59
+#define    IRQ_SW_LISR60_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_60
+#define    IRQ_SW_LISR61_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_61
+#define    IRQ_SW_LISR62_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_62
+#define    IRQ_SW_LISR63_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_63
+#define    IRQ_SW_LISR64_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_64
+#define    IRQ_DUMMY_PRIORITY_CODE_8                 MD_IRQID_DUMMY_PRIORITY_IRQ8
+#define    IRQ_DUMMY_PRIORITY_CODE_9                 MD_IRQID_DUMMY_PRIORITY_IRQ9
+#define    IRQ_DUMMY_PRIORITY_CODE_10                MD_IRQID_DUMMY_PRIORITY_IRQ10
+#define    IRQ_DUMMY_PRIORITY_CODE_11                MD_IRQID_DUMMY_PRIORITY_IRQ11
+#define    IRQ_DUMMY_PRIORITY_CODE_12                MD_IRQID_DUMMY_PRIORITY_IRQ12
+#define    IRQ_DUMMY_PRIORITY_CODE_13                MD_IRQID_DUMMY_PRIORITY_IRQ13
+#define    IRQ_DUMMY_PRIORITY_CODE_14                MD_IRQID_DUMMY_PRIORITY_IRQ14
+#define    IRQ_DUMMY_PRIORITY_CODE_15                MD_IRQID_DUMMY_PRIORITY_IRQ15
+#define    IRQ_DUMMY_PRIORITY_CODE_16                MD_IRQID_DUMMY_PRIORITY_IRQ16
+#define    IRQ_DUMMY_PRIORITY_CODE_17                MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define    IRQ_DUMMY_PRIORITY_CODE_18                MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define    IRQ_DUMMY_PRIORITY_CODE_19                MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define    IRQ_DUMMY_PRIORITY_CODE_20                MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define    IRQ_DUMMY_PRIORITY_CODE_21                MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define    IRQ_DUMMY_PRIORITY_CODE_22                MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define    IRQ_DUMMY_PRIORITY_CODE_23                MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define    IRQ_DUMMY_PRIORITY_CODE_24                MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define    IRQ_DUMMY_PRIORITY_CODE_25                MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define    IRQ_DUMMY_PRIORITY_CODE_26                MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define    IRQ_DUMMY_PRIORITY_CODE_27                MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define    IRQ_DUMMY_PRIORITY_CODE_28                MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define    IRQ_DUMMY_PRIORITY_CODE_29                MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define    IRQ_DUMMY_PRIORITY_CODE_30                MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define    IRQ_SW_MODIS_MASE_HMU_CODE                IRQ_DUMMY_PRIORITY_CODE_25
+#define    IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE         IRQ_DUMMY_PRIORITY_CODE_26
+#define    IRQ_SW_MODIS_MASE_NR_TXLISR_CODE          IRQ_DUMMY_PRIORITY_CODE_27
+#define    IRQ_L1_PAE_SW_LISR0                       IRQ_DUMMY_PRIORITY_CODE_28
+#define    IRQ_L1_PAE_SW_LISR1                       IRQ_DUMMY_PRIORITY_CODE_29
+#define    IRQ_L1_PAE_SW_LISR2                       IRQ_DUMMY_PRIORITY_CODE_30
+#endif 
+
+
+/*
+ * Define IRQ selection register assignment
+ */
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+
+#define INTERRUPT_GROUP_LIST \
+	/*  0 ~  7 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*  8 ~ 15 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 16 ~ 23 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 24 ~ 31 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 32 ~ 39 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 40 ~ 47 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 48 ~ 55 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 56 ~ 63 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 64 ~ 71 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 72 ~ 79 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 80 ~ 87 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 88 ~ 95 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/* 96 ~103 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*104 ~111 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*112 ~119 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*120 ~127 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*128 ~135 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*136 ~143 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*144 ~151 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*152 ~159 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*160 ~167 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*168 ~175 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*176 ~183 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*184 ~191 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*192 ~199 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*200 ~207 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*208 ~215 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*216 ~223 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*224 ~231 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*232 ~239 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*240 ~247 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*248 ~255 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*256 ~263 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*264 ~271 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*272 ~279 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*280 ~287 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*288 ~295 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*296 ~303 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*304 ~311 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*312 ~319 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*320 ~327 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*328 ~335 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*336 ~343 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*344 ~351 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*352 ~359 */  0,  0,  0,  0,  0,  0,  0,  0, \
+	/*360 ~367 */  0,  0,  0,  0,  0,  0,  1,  2
+
+#elif defined(__MD97_IS_2CORES__)
+
+#define INTERRUPT_GROUP_LIST \
+    /*  0 ~   7 */  7,  7,  1,  1,  1,  1,  0,  1, \
+    /*  8 ~  15 */  1,  7,  7,  7,  7,  7,  7,  1, \
+    /* 16 ~  23 */  0,  0,  0,  0,  0,  0,  0, 12, \
+    /* 24 ~  31 */ 12, 11, 12,  0,  0,  0,  0,  0, \
+    /* 32 ~  39 */  0,  7,  0, 12, 12,  7,  0,  0, \
+    /* 40 ~  47 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 48 ~  55 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 56 ~  63 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 64 ~  71 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 72 ~  79 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 80 ~  87 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 88 ~  95 */  0,  0,  0,  0,  0,  7,  0,  1, \
+    /* 96 ~ 103 */  1,  1,  1,  1,  1,  7,  7,  0, \
+    /*104 ~ 111 */  0,  0,  1,  1,  1,  1,  1,  1, \
+    /*112 ~ 119 */  1,  1,  7,  7,  7,  7,  7,  7, \
+    /*120 ~ 127 */  7,  7,  7,  7,  7,  7,  1,  1, \
+    /*128 ~ 135 */  7,  7,  7,  7,  0,  0,  0,  7, \
+    /*136 ~ 143 */  0,  7, 12,  7,  7,  0,  0,  0, \
+    /*144 ~ 151 */ 11,  1,  1, 11, 11, 11, 11, 11, \
+    /*152 ~ 159 */ 11, 11,  9,  1,  1,  0,  0,  0, \
+    /*160 ~ 167 */  0,  7, 12, 12, 12, 12,  0,  0, \
+    /*168 ~ 175 */  0,  0,  0, 12,  7,  8,  8,  8, \
+    /*176 ~ 183 */  7,  7,  7, 12,  7,  7,  0,  1, \
+    /*184 ~ 191 */  2,  3,  4,  5,  0,  0,  0,  0, \
+    /*192 ~ 199 */  0,  0, 12, 12, 12,  0,  0,  0, \
+    /*200 ~ 207 */ 12,  0,  0,  1,  0,  0,  0,  0, \
+    /*208 ~ 215 */  4, 11, 11, 11, 11,  1,  4,  7, \
+    /*216 ~ 223 */  7,  7, 12, 12, 12, 12, 12, 12, \
+    /*224 ~ 231 */  7,  7,  0, 12,  0,  0,  0,  0, \
+    /*232 ~ 239 */  6,  1,  4,  1,  1,  1,  4,  1, \
+    /*240 ~ 247 */  0,  4,  1,  1,  1,  1,  4,  1, \
+    /*248 ~ 255 */ 12,  7,  0,  0,  0,  0,  0,  0, \
+    /*256 ~ 263 */  0, 12,  1,  1,  7,  1,  1,  0, \
+    /*264 ~ 271 */ 12, 12, 12,  7,  7,  7,  0,  0, \
+    /*272 ~ 279 */  7,  7,  7, 12,  0, 12,  0,  0, \
+    /*280 ~ 287 */  1,  1,  1,  4,  1,  4,  1,  1, \
+    /*288 ~ 295 */  1,  1,  1,  1,  1,  1, 12,  0, \
+    /*296 ~ 303 */  8,  0,  0,  0,  0,  0,  0,  3, \
+    /*304 ~ 311 */  0,  0, 12,  0,  0,  1,  7,  1, \
+    /*312 ~ 319 */  1,  0,  0,  0,  0,  0,  0,  0, \
+    /*320 ~ 327 */ 10,  7,  7,  7,  7,  7,  7,  7, \
+    /*328 ~ 335 */  7,  7,  7,  7,  7,  0,  1,  2, \
+    /*336 ~ 343 */  3,  4,  5,  0,  0,  0,  0,  0, \
+    /*344 ~ 351 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*352 ~ 359 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*360 ~ 367 */  0,  0,  0,  0,  0,  0,  0,  0
+#else
+
+#define INTERRUPT_GROUP_LIST \
+    /*  0 ~   7 */ 15, 15,  1,  1,  1,  1,  0,  0, \
+    /*  8 ~  15 */  1, 15, 15, 15, 15, 15, 15,  1, \
+    /* 16 ~  23 */ 16, 16, 18, 18, 18, 18, 19, 19, \
+    /* 24 ~  31 */ 19, 17, 19, 15, 15, 15, 15, 16, \
+    /* 32 ~  39 */ 16, 15, 17, 19, 19, 15, 10, 16, \
+    /* 40 ~  47 */ 16, 14, 14, 14, 14, 14, 14, 14, \
+    /* 48 ~  55 */ 14, 14, 14, 14, 14, 14, 14, 14, \
+    /* 56 ~  63 */ 14, 14, 14, 14, 14, 14, 14, 14, \
+    /* 64 ~  71 */ 14, 14, 18, 14, 14, 14, 14, 16, \
+    /* 72 ~  79 */ 16, 16, 18, 18, 18, 18, 18, 18, \
+    /* 80 ~  87 */ 18, 14, 14, 14, 14, 14, 14, 14, \
+    /* 88 ~  95 */ 16, 16, 14, 14, 14, 19, 15,  1, \
+    /* 96 ~ 103 */  1,  1,  1,  1,  1, 15, 15, 15, \
+    /*104 ~ 111 */ 15, 15,  1,  1,  1,  1,  1,  1, \
+    /*112 ~ 119 */  1,  1, 15, 15, 15, 15, 15, 15, \
+    /*120 ~ 127 */ 15, 15, 15, 17, 15, 15, 17,  1, \
+    /*128 ~ 135 */ 15, 15, 15, 15,  0,  0,  0, 15, \
+    /*136 ~ 143 */  0, 15, 19, 15, 15, 15, 15,  0, \
+    /*144 ~ 151 */ 17,  1,  1, 17, 17, 17, 17, 17, \
+    /*152 ~ 159 */ 17, 17, 17,  1,  1, 18, 18, 18, \
+    /*160 ~ 167 */ 15, 15, 19, 19, 15, 15, 15, 15, \
+    /*168 ~ 175 */ 15, 15, 15, 19, 15, 17, 15, 17, \
+    /*176 ~ 183 */ 15, 15, 15, 19, 15, 15,  0,  1, \
+    /*184 ~ 191 */  2,  3,  4,  5,  6,  7,  8,  9, \
+    /*192 ~ 199 */ 10, 11, 17, 17, 17, 15, 17, 15, \
+    /*200 ~ 207 */ 15, 17, 15,  1, 15, 15, 16, 16, \
+    /*208 ~ 215 */ 17, 17, 17, 17, 17,  1,  4, 17, \
+    /*216 ~ 223 */ 17, 15, 19, 19, 19, 19, 19, 19, \
+    /*224 ~ 231 */ 15, 15, 15, 19,  0,  0,  0, 15, \
+    /*232 ~ 239 */ 13,  1,  4,  1,  1,  1,  4,  1, \
+    /*240 ~ 247 */  0,  4,  1,  1,  1,  1,  4,  1, \
+    /*248 ~ 255 */ 15, 15, 15, 10, 17, 14, 19, 18, \
+    /*256 ~ 263 */ 14, 19,  1,  1, 15,  1,  0, 15, \
+    /*264 ~ 271 */ 15, 15, 15, 15, 15, 15, 15, 15, \
+    /*272 ~ 279 */ 15, 15, 15, 19, 15, 19, 17,  0, \
+    /*280 ~ 287 */  1,  1,  1,  4,  1,  4,  1,  1, \
+    /*288 ~ 295 */  1,  1,  1,  1,  1, 12, 19, 15, \
+    /*296 ~ 303 */ 17,  0,  0,  3,  6,  9,  0,  3, \
+    /*304 ~ 311 */  6,  9, 19, 15, 15, 15, 15,  1, \
+    /*312 ~ 319 */  1, 16, 16, 18, 18, 16, 14, 14, \
+    /*320 ~ 327 */ 17, 19, 19, 15, 15, 15, 15, 15, \
+    /*328 ~ 335 */ 15, 15, 15, 15, 19,  0,  1,  2, \
+    /*336 ~ 343 */  3,  4,  5,  6,  7,  8,  9, 10, \
+    /*344 ~ 351 */ 11,  0,  0,  0,  0,  0,  0,  0, \
+    /*352 ~ 359 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*360 ~ 367 */  0,  0,  0,  0,  0,  0,  0,  0
+#endif
+
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#elif defined(__MD97_IS_2CORES__)
+#define INTERRUPT_GROUP_M2V_LIST \
+    /* Group0(0) */                             0xFFE, \
+    /* Group1(1) */                             0xFFD, \
+    /* Group2(2) */                             0xFFB, \
+    /* Group3(3) */                             0xFF7, \
+    /* Group4(4) */                             0xFEF, \
+    /* Group5(5) */                             0xFDF, \
+    /* Group6(0,1) */                           0xFFC, \
+    /* Group7(0,3) */                           0xFF6, \
+    /* Group8(1,4) */                           0xFED, \
+    /* Group9(3,4) */                           0xFE7, \
+    /* Group10(2,4,5) */                        0xFCB, \
+    /* Group11(0,1,3,4) */                      0xFE4, \
+    /* Group12(0,1,2,3,4,5) */                  0xFC0, \
+    /* Group13 */                               0xFFF, \
+    /* Group14 */                               0xFFF, \
+    /* Group15 */                               0xFFF, \
+    /* Group16 */                               0xFFF, \
+    /* Group17 */                               0xFFF, \
+    /* Group18 */                               0xFFF, \
+    /* Group19 */                               0xFFF, \
+    /* Group20 */                               0xFFF, \
+    /* Group21 */                               0xFFF, \
+    /* Group22 */                               0xFFF, \
+    /* Group23 */                               0xFFF, \
+    /* Group24 */                               0xFFF, \
+    /* Group25 */                               0xFFF, \
+    /* Group26 */                               0xFFF, \
+    /* Group27 */                               0xFFF, \
+    /* Group28 */                               0xFFF, \
+    /* Group29 */                               0xFFF, \
+    /* Group30 */                               0xFFF, \
+    /* Group31 */                               0xFFF,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+    /* Group0(0) */                                                                             0xFFE, \
+    /* Group1(1) */                                                                             0xFFD, \
+    /* Group2(2) */                                                                             0xFFB, \
+    /* Group3(3) */                                                                             0xFF7, \
+    /* Group4(4) */                                                                             0xFEF, \
+    /* Group5(5) */                                                                             0xFDF, \
+    /* Group6(6) */                                                                             0xFBF, \
+    /* Group7(7) */                                                                             0xF7F, \
+    /* Group8(8) */                                                                             0xEFF, \
+    /* Group9(9) */                                                                             0xDFF, \
+    /* Group10(10) */                                                                           0xBFF, \
+    /* Group11(11) */                                                                           0x7FF, \
+    /* Group12(1,4) */                                                                          0xFED, \
+    /* Group13(0,1,2) */                                                                        0xFF8, \
+    /* Group14(3,6,9) */                                                                        0xDB7, \
+    /* Group15(0,3,6,9) */                                                                      0xDB6, \
+    /* Group16(3,4,6,7,9,10) */                                                                 0x927, \
+    /* Group17(0,1,2,3,4,6,7,9,10) */                                                           0x920, \
+    /* Group18(3,4,5,6,7,8,9,10,11) */                                                          0x007, \
+    /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */                                                    0x000, \
+    /* Group20(3,4,6,7,9,10)        -> Reserved for NR runtime change affinity */               0x927, \
+    /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */               0x007, \
+    /* Group22(2)                   -> Reserved for LTE runtime change affinity */              0xFFB, \
+    /* Group23(0,2,3,4,6,7,9,10)    -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */  0x922, \
+    /* Group24(3,6,7,9,10)          -> Temp solution for IRQ0xEE to not preempt NR RX IRQs */   0x937, \
+    /* Group25 */                                                                               0xFFF, \
+    /* Group26 */                                                                               0xFFF, \
+    /* Group27 */                                                                               0xFFF, \
+    /* Group28 */                                                                               0xFFF, \
+    /* Group29 */                                                                               0xFFF, \
+    /* Group30 */                                                                               0xFFF, \
+    /* Group31 */                                                                               0xFFF,
+#endif
+
+#define INTERRUPT_BROADCAST_TYPE \
+    /*  0 ~   7 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*  8 ~  15 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 16 ~  23 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 24 ~  31 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 32 ~  39 */  0,  0,  0,  1,  0,  0,  0,  0, \
+    /* 40 ~  47 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 48 ~  55 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 56 ~  63 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 64 ~  71 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 72 ~  79 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 80 ~  87 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 88 ~  95 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /* 96 ~ 103 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*104 ~ 111 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*112 ~ 119 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*120 ~ 127 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*128 ~ 135 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*136 ~ 143 */  0,  0,  1,  0,  0,  0,  0,  0, \
+    /*144 ~ 151 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*152 ~ 159 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*160 ~ 167 */  0,  0,  1,  1,  1,  1,  0,  0, \
+    /*168 ~ 175 */  0,  0,  0,  1,  0,  0,  0,  0, \
+    /*176 ~ 183 */  0,  0,  0,  1,  0,  0,  0,  0, \
+    /*184 ~ 191 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*192 ~ 199 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*200 ~ 207 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*208 ~ 215 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*216 ~ 223 */  0,  0,  1,  1,  1,  1,  1,  1, \
+    /*224 ~ 231 */  0,  0,  0,  1,  0,  0,  0,  0, \
+    /*232 ~ 239 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*240 ~ 247 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*248 ~ 255 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*256 ~ 263 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*264 ~ 271 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*272 ~ 279 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*280 ~ 287 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*288 ~ 295 */  0,  0,  0,  0,  0,  1,  1,  0, \
+    /*296 ~ 303 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*304 ~ 311 */  0,  0,  1,  1,  0,  0,  1,  0, \
+    /*312 ~ 319 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*320 ~ 327 */  0,  1,  1,  0,  0,  0,  0,  0, \
+    /*328 ~ 335 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*336 ~ 343 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*344 ~ 351 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*352 ~ 359 */  0,  0,  0,  0,  0,  0,  0,  0, \
+    /*360 ~ 367 */  0,  0,  0,  0,  0,  0,  0,  0
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions - 
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0         0   //(0)
+#define IRQ_AFFINITY_GROUP_VPE1         1   //(1)
+#define IRQ_AFFINITY_GROUP_VPE2         2   //(2)
+#define IRQ_AFFINITY_GROUP_VPE3         3   //(3)
+#define IRQ_AFFINITY_GROUP_VPE4         4   //(4)
+#define IRQ_AFFINITY_GROUP_VPE5         5   //(5)
+#define IRQ_AFFINITY_GROUP_VPE6         6   //(6)
+#define IRQ_AFFINITY_GROUP_VPE7         7   //(7)
+#define IRQ_AFFINITY_GROUP_VPE8	        8   //(8)
+#define IRQ_AFFINITY_GROUP_VPE9         9   //(9)
+#define IRQ_AFFINITY_GROUP_VPE10        10  //(10)
+#define IRQ_AFFINITY_GROUP_VPE11        11  //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4     12  //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0    13  //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR    14  //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP   15  //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR       16  //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP      17  //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR      18  //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE      19  //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+#define MAX_NUM_TASKS          256
+#define MAX_HISR_PRIORITY      2
+
+typedef enum
+{
+    VPE_STATUS_LISR_HIGHEST      = 0,
+    VPE_STATUS_LISR_LOWEST       = 337,
+    VPE_STATUS_HISR_TASK_HIGHEST = 512,
+    VPE_STATUS_HISR_TASK_LOWEST  = VPE_STATUS_HISR_TASK_HIGHEST + MAX_NUM_TASKS + MAX_HISR_PRIORITY, 
+    VPE_STATUS_END               = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_MT6297_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6297_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6297_SW_Handle.h
new file mode 100644
index 0000000..9ab2495
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6297_SW_Handle.h
@@ -0,0 +1,226 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6297_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   MT6297
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 11 07 2018 chia-han.wu
+ * [MOLY00351302] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * 1. Reduce IRQ numbers from 372 to 368
+ * 2. Reduce YQ signals from 7 to 6
+ * 3. Define CRT Registers for Gen97
+ * 4. Raise TC priority in MIN_SAVE and reset TC priority according to IRQ priority in isrC_Main
+ * 5. Remove kal_if_hrt_domain and kal_if_chrt_domain and use kal_get_current_domain instead
+ * 6. Create drv_mdcirq_per_VPE_domain_type array to save all VPE's domain type 
+ * 7. Reinitialize di_tc in interrupt_preinit 
+ * 8. drv_mdcirq.c driver code modification
+ * 9. IRQ Configuration Settings according to Gen97_MDCIRQ_IRQ_Affinity_UserGuide
+ * 10. Remove redundant code
+ * 11. Bus monitor Runtime configure IRQ configuration settings
+ *
+ * 05 09 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * merge 97 MDCIRQ driver to UMOLYE.
+ *
+ * 05 08 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * check-in MDCIRQ driver for Gen97.
+ *
+ * 05 08 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * check-in MDCIRQ driver for Gen97.
+ *
+ * 03 07 2018 yen-chun.liu
+ * [MOLY00302569] [Gen97][MDCIRQ][System Service] MDCIRQ driver development
+ * fix build error.
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE0  = Karthigeyan Reddy
+      SW_TRIGGER_CODE1  = Karthigeyan Reddy
+      SW_TRIGGER_CODE2  = Karthigeyan Reddy
+      SW_TRIGGER_CODE3  = Karthigeyan Reddy
+      SW_TRIGGER_CODE4  = Karthigeyan Reddy
+      SW_TRIGGER_CODE5  = Karthigeyan Reddy
+      SW_TRIGGER_CODE6  = Zengling Jin
+      SW_TRIGGER_CODE7  = Zengling Jin
+      SW_TRIGGER_CODE8  = Zengling Jin
+      SW_TRIGGER_CODE9  = Cruze Yu
+      SW_TRIGGER_CODE10 = Cruze Yu
+      SW_TRIGGER_CODE11 = Cruze Yu
+      SW_TRIGGER_CODE12 = Cruze Yu
+      SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+      SW_TRIGGER_CODE14 = HW Jheng
+      SW_TRIGGER_CODE15 = Frank Hu
+      SW_TRIGGER_CODE16 = KH Hsiao
+      SW_TRIGGER_CODE17 = Deepti Varadarajan
+      SW_TRIGGER_CODE18 = Owen Ho
+      SW_TRIGGER_CODE19 = Owen Ho
+      SW_TRIGGER_CODE20 = Owen Ho
+      SW_TRIGGER_CODE21 = Owen Ho
+      SW_TRIGGER_CODE22 = Jun-Ying Huang
+      SW_TRIGGER_CODE23 = Jun-Ying Huang
+      SW_TRIGGER_CODE24 = Jun-Ying Huang
+      SW_TRIGGER_CODE25 = Jun-Ying Huang
+      SW_TRIGGER_CODE26 = Wade Huang
+      SW_TRIGGER_CODE27 = Tee-Yuen Chun
+      SW_TRIGGER_CODE28 = YY Hsieh 
+      SW_TRIGGER_CODE29 = Hamilton Liang
+      SW_TRIGGER_CODE30 = HW Jheng
+      SW_TRIGGER_CODE31 = Weimin Zeng
+      SW_TRIGGER_CODE32 = Weimin Zeng
+      SW_TRIGGER_CODE33 = Jocobrian Chang
+      SW_TRIGGER_CODE34 = JiaHong Hsu
+      SW_TRIGGER_CODE35 = Cheng-Long Wu
+      SW_TRIGGER_CODE36 = Cheng-Long Wu
+      SW_TRIGGER_CODE37 = Jocobrian Chang
+      SW_TRIGGER_CODE38 = Jocobrian Chang
+      SW_TRIGGER_CODE39 = Jocobrian Chang
+      SW_TRIGGER_CODE40 = Shu-Wei Ho
+      SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+      SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+  */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6833.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6833.h
new file mode 100644
index 0000000..0739c93
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6833.h
@@ -0,0 +1,564 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6833.h
+ *
+ * Project:
+ * --------
+ *   MT6833
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6833_H__
+#define __INTRCTRL_MT6833_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+
+#define NUM_IRQ_SOURCES          (368)
+
+/* CIRQ Interrupt Sources */
+#define    IRQ_USIM0_CODE                            MD_IRQID_USIM0
+#define    IRQ_USIM1_CODE                            MD_IRQID_USIM1
+#define    IRQ_TDMA_CTIRQ1_CODE                      MD_IRQID_TDMA_CTIRQ1
+#define    IRQ_TDMA_CTIRQ2_CODE                      MD_IRQID_TDMA_CTIRQ2
+#define    IRQ_TDMA_CTIRQ3_CODE                      MD_IRQID_TDMA_CTIRQ3
+#define    IRQ_TDMA_WAKEUP_IRQ_CODE                  MD_IRQID_TDMA_WAKEUP_IRQ
+#define    IRQ_OST_CODE                              MD_IRQID_OST
+#define    IRQ_MDRTT_CODE                            MD_IRQID_MDRTT
+#define    IRQ_MDEVDO_CODE                           MD_IRQID_MDEVDO
+#define    IRQ_ULSP_LOG_MCU_RT_INT_CODE              MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define    IRQ_ULSP_LOG_MCU_OD_INT_CODE              MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define    IRQ_ULSP_LOG_DSP4G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define    IRQ_ULSP_LOG_DSP4G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define    IRQ_ULSP_LOG_DSP5G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define    IRQ_ULSP_LOG_DSP5G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define    IRQ_SHARE_D12MINT1_CODE                   MD_IRQID_SHARE_D12MINT1
+#define    IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE        MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define    IRQ_AIRQ_SERDES_CODE                      MD_IRQID_AIRQ_SERDES
+#define    IRQ_AIRQ_COS_CODE                         MD_IRQID_AIRQ_COS
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define    IRQ_PPPHA_ENC0_INT_CODE                   MD_IRQID_PPPHA_ENC0_INT
+#define    IRQ_PPPHA_ENC1_INT_CODE                   MD_IRQID_PPPHA_ENC1_INT
+#define    IRQ_PPPHA_DEC0_INT_CODE                   MD_IRQID_PPPHA_DEC0_INT
+#define    IRQ_PPPHA_DEC1_INT_CODE                   MD_IRQID_PPPHA_DEC1_INT
+#define    IRQ_CS_NR_IRQ_CODE                        MD_IRQID_CS_NR_IRQ
+#define    IRQ_CS_NR_ERR_IRQ_CODE                    MD_IRQID_CS_NR_ERR_IRQ
+#define    IRQ_SDF_OVERFLOW_IRQ_CODE                 MD_IRQID_SDF_OVERFLOW_IRQ
+#define    IRQ_MCUMMU_INT_CODE                       MD_IRQID_MCUMMU_INT
+#define    IRQ_BIGRAM_0_IRQ_0_CODE                   MD_IRQID_BIGRAM_0_IRQ_0
+#define    IRQ_COS_PREP_INT_CODE                     MD_IRQID_COS_PREP_INT
+#define    IRQ_TRACE_INT_CODE                        MD_IRQID_TRACE_INT
+#define    IRQ_NR_TIMER_IRQ0_CODE                    MD_IRQID_NR_TIMER_IRQ0
+#define    IRQ_NR_TIMER_IRQ1_CODE                    MD_IRQID_NR_TIMER_IRQ1
+#define    IRQ_NR_TIMER_IRQ2_CODE                    MD_IRQID_NR_TIMER_IRQ2
+#define    IRQ_NR_TIMER_IRQ3_CODE                    MD_IRQID_NR_TIMER_IRQ3
+#define    IRQ_NR_TIMER_IRQ4_CODE                    MD_IRQID_NR_TIMER_IRQ4
+#define    IRQ_NR_TIMER_IRQ5_CODE                    MD_IRQID_NR_TIMER_IRQ5
+#define    IRQ_NR_TIMER_IRQ6_CODE                    MD_IRQID_NR_TIMER_IRQ6
+#define    IRQ_NR_TIMER_IRQ7_CODE                    MD_IRQID_NR_TIMER_IRQ7
+#define    IRQ_NR_TIMER_IRQ8_CODE                    MD_IRQID_NR_TIMER_IRQ8
+#define    IRQ_NR_TIMER_IRQ9_CODE                    MD_IRQID_NR_TIMER_IRQ9
+#define    IRQ_NR_TIMER_IRQ10_CODE                   MD_IRQID_NR_TIMER_IRQ10
+#define    IRQ_NR_TIMER_IRQ11_CODE                   MD_IRQID_NR_TIMER_IRQ11
+#define    IRQ_NR_TIMER_IRQ12_CODE                   MD_IRQID_NR_TIMER_IRQ12
+#define    IRQ_NR_TIMER_IRQ13_CODE                   MD_IRQID_NR_TIMER_IRQ13
+#define    IRQ_NR_TIMER_IRQ14_CODE                   MD_IRQID_NR_TIMER_IRQ14
+#define    IRQ_NR_TIMER_IRQ15_CODE                   MD_IRQID_NR_TIMER_IRQ15
+#define    IRQ_NR_TIMER_IRQ16_CODE                   MD_IRQID_NR_TIMER_IRQ16
+#define    IRQ_NR_TIMER_IRQ17_CODE                   MD_IRQID_NR_TIMER_IRQ17
+#define    IRQ_NR_TIMER_IRQ18_CODE                   MD_IRQID_NR_TIMER_IRQ18
+#define    IRQ_NR_TIMER_IRQ19_CODE                   MD_IRQID_NR_TIMER_IRQ19
+#define    IRQ_NR_TIMER_IRQ20_CODE                   MD_IRQID_NR_TIMER_IRQ20
+#define    IRQ_NR_TIMER_IRQ21_CODE                   MD_IRQID_NR_TIMER_IRQ21
+#define    IRQ_NR_TIMER_IRQ22_CODE                   MD_IRQID_NR_TIMER_IRQ22
+#define    IRQ_NR_TIMER_IRQ23_CODE                   MD_IRQID_NR_TIMER_IRQ23
+#define    IRQ_NR_TIMER_IRQ24_CODE                   MD_IRQID_NR_TIMER_IRQ24
+#define    IRQ_NR_TIMER_IRQ25_CODE                   MD_IRQID_NR_TIMER_IRQ25
+#define    IRQ_NR_TIMER_IRQ26_CODE                   MD_IRQID_NR_TIMER_IRQ26
+#define    IRQ_NR_TIMER_IRQ27_CODE                   MD_IRQID_NR_TIMER_IRQ27
+#define    IRQ_NR_TIMER_IRQ28_CODE                   MD_IRQID_NR_TIMER_IRQ28
+#define    IRQ_NR_TIMER_IRQ29_CODE                   MD_IRQID_NR_TIMER_IRQ29
+#define    IRQ_NR_TIMER_IRQ30_CODE                   MD_IRQID_NR_TIMER_IRQ30
+#define    IRQ_NR_TIMER_IRQ31_CODE                   MD_IRQID_NR_TIMER_IRQ31
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define    IRQ_NR_TIMER_CNTDN_IRQ0_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define    IRQ_NR_TIMER_CNTDN_IRQ1_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define    IRQ_NR_TIMER_CNTDN_IRQ2_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define    IRQ_NR_TIMER_CNTDN_IRQ3_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define    IRQ_NR_EVENTGEN_SPU_CODE                  MD_IRQID_NR_EVENTGEN_SPU
+#define    IRQ_SI_CM_ERR_CODE                        MD_IRQID_SI_CM_ERR
+#define    IRQ_SI_CM_PCINT_CODE                      MD_IRQID_SI_CM_PCINT
+#define    IRQ_MDM2C_U3G_CODE                        MD_IRQID_MDM2C_U3G
+#define    IRQ_RAKE_CMIF_M2C_IRQ_0_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define    IRQ_RAKE_CMIF_M2C_IRQ_1_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define    IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define    IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define    IRQ_RAKE_CMIF_PD_DO_IRQ_CODE              MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define    IRQ_MDMCU_BUSMON_MATCH_STS_CODE           MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define    IRQ_MDINFRA_BUSMON_MATCH_STS_CODE         MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define    IRQ_ELMTOP_EMI_IRQ_CODE                   MD_IRQID_ELMTOP_EMI_IRQ
+#define    IRQ_ELM_DMA_IRQ_CODE                      MD_IRQID_ELM_DMA_IRQ
+#define    IRQ_BUSMPU_IRQ_CODE                       MD_IRQID_BUSMPU_IRQ
+#define    IRQ_ST1X_CPINT_CODE                       MD_IRQID_ST1X_CPINT
+#define    IRQ_ST1x_HALF_CPINT_CODE                  MD_IRQID_ST1x_HALF_CPINT
+#define    IRQ_ST1x_CFG_CPINT_CODE                   MD_IRQID_ST1x_CFG_CPINT
+#define    IRQ_ST1x_WAKEUP_IRQ_CODE                  MD_IRQID_ST1x_WAKEUP_IRQ
+#define    IRQ_STDO_CPINT_CODE                       MD_IRQID_STDO_CPINT
+#define    IRQ_STDO_HALF_CPINT_CODE                  MD_IRQID_STDO_HALF_CPINT
+#define    IRQ_STDO_CFG_CPINT_CODE                   MD_IRQID_STDO_CFG_CPINT
+#define    IRQ_STDO_WAKEUP_IRQ_CODE                  MD_IRQID_STDO_WAKEUP_IRQ
+#define    IRQ_UART_MD0_CODE                         MD_IRQID_UART_MD0
+#define    IRQ_UART_MD1_CODE                         MD_IRQID_UART_MD1
+#define    IRQ_EINT0_CODE                            MD_IRQID_EINT0
+#define    IRQ_EINT1_CODE                            MD_IRQID_EINT1
+#define    IRQ_EINT2_CODE                            MD_IRQID_EINT2
+#define    IRQ_EINT3_CODE                            MD_IRQID_EINT3
+#define    IRQ_EINT_SHARE_CODE                       MD_IRQID_EINT_SHARE
+#define    IRQ_GPTM1_CODE                            MD_IRQID_GPTM1
+#define    IRQ_GPTM2_CODE                            MD_IRQID_GPTM2
+#define    IRQ_GPTM3_CODE                            MD_IRQID_GPTM3
+#define    IRQ_GPTM4_CODE                            MD_IRQID_GPTM4
+#define    IRQ_GPTM5_CODE                            MD_IRQID_GPTM5
+#define    IRQ_GPTM6_CODE                            MD_IRQID_GPTM6
+#define    IRQ_GPTM7_CODE                            MD_IRQID_GPTM7
+#define    IRQ_GPTM8_CODE                            MD_IRQID_GPTM8
+#define    IRQ_GPTM9_CODE                            MD_IRQID_GPTM9
+#define    IRQ_GPTM10_CODE                           MD_IRQID_GPTM10
+#define    IRQ_GPTM11_CODE                           MD_IRQID_GPTM11
+#define    IRQ_IDC_PM_INT_CODE                       MD_IRQID_IDC_PM_INT
+#define    IRQ_IDC_UART_IRQ_CODE                     MD_IRQID_IDC_UART_IRQ
+#define    IRQ_MDGDMA_FDMA5_CODE                     MD_IRQID_MDGDMA_FDMA5
+#define    IRQ_MDGDMA_FDMA6_CODE                     MD_IRQID_MDGDMA_FDMA6
+#define    IRQ_TDMA_CTIRQ4_CODE                      MD_IRQID_TDMA_CTIRQ4
+#define    IRQ_PDMA_CODE                             MD_IRQID_PDMA
+#define    IRQ_MDINFRA_BUS_DECERROR_CODE             MD_IRQID_MDINFRA_BUS_DECERROR
+#define    IRQ_I2C_TOP_INT_CODE                      MD_IRQID_I2C_TOP_INT
+#define    IRQ_SOE_CODE                              MD_IRQID_SOE
+#define    IRQ_ABM_INT_CODE                          MD_IRQID_ABM_INT
+#define    IRQ_ABM_ERROR_INT_CODE                    MD_IRQID_ABM_ERROR_INT
+#define    IRQ_USIP0_CODE                            MD_IRQID_USIP0
+#define    IRQ_USIP1_CODE                            MD_IRQID_USIP1
+#define    IRQ_USIP2_CODE                            MD_IRQID_USIP2
+#define    IRQ_USIP3_CODE                            MD_IRQID_USIP3
+#define    IRQ_USIP4_CODE                            MD_IRQID_USIP4
+#define    IRQ_USIP5_CODE                            MD_IRQID_USIP5
+#define    IRQ_USIP6_CODE                            MD_IRQID_USIP6
+#define    IRQ_USIP7_CODE                            MD_IRQID_USIP7
+#define    IRQ_USIP8_CODE                            MD_IRQID_USIP8
+#define    IRQ_USIP9_CODE                            MD_IRQID_USIP9
+#define    IRQ_USIP10_CODE                           MD_IRQID_USIP10
+#define    IRQ_USIP11_CODE                           MD_IRQID_USIP11
+#define    IRQ_USIP12_CODE                           MD_IRQID_USIP12
+#define    IRQ_USIP13_CODE                           MD_IRQID_USIP13
+#define    IRQ_TX_NR_CC0_IRQ_CODE                    MD_IRQID_TX_NR_CC0_IRQ
+#define    IRQ_TX_NR_CC1_IRQ_CODE                    MD_IRQID_TX_NR_CC1_IRQ
+#define    IRQ_TX_NR_ERR_CC_IRQ_CODE                 MD_IRQID_TX_NR_ERR_CC_IRQ
+#define    IRQ_MDMCU_SPU_IRQ_CODE                    MD_IRQID_MDMCU_SPU_IRQ
+#define    IRQ_DEM_TRIG_PS_INT_LE_CODE               MD_IRQID_DEM_TRIG_PS_INT_LE
+#define    IRQ_ECT_CODE                              MD_IRQID_ECT
+#define    IRQ_MDMCU_BUS_DECERR_IRQ_CODE             MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define    IRQ_MDMCU_OSTD_THROTTLE_CODE              MD_IRQID_MDMCU_OSTD_THROTTLE
+#define    IRQ_SHAOLIN_OSTD_THROTTLE_CODE            MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define    IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE         MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define    IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_AP2MD_CONN_WF_CCIF_0_CODE             MD_IRQID_AP2MD_CONN_WF_CCIF_0
+#define    IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_AP2MD_CONN_WF_CCIF_1_CODE             MD_IRQID_AP2MD_CONN_WF_CCIF_1
+#define    IRQ_MDWDT_CODE                            MD_IRQID_MDWDT
+#define    IRQ_MDGDMA_FDMA0_2_CODE                   MD_IRQID_MDGDMA_FDMA0_2
+#define    IRQ_MDGDMA_FDMA1_CODE                     MD_IRQID_MDGDMA_FDMA1
+#define    IRQ_MDGDMA_FDMA3_CODE                     MD_IRQID_MDGDMA_FDMA3
+#define    IRQ_MDGDMA_FDMA4_CODE                     MD_IRQID_MDGDMA_FDMA4
+#define    IRQ_MDGDMA_HDMA0_1_CODE                   MD_IRQID_MDGDMA_HDMA0_1
+#define    IRQ_MDGDMA_HDMA2_3_CODE                   MD_IRQID_MDGDMA_HDMA2_3
+#define    IRQ_AP2MD_CCIF0_0_CODE                    MD_IRQID_AP2MD_CCIF0_0
+#define    IRQ_AP2MD_CCIF0_1_CODE                    MD_IRQID_AP2MD_CCIF0_1
+#define    IRQ_AP2MD_CCIF1_0_CODE                    MD_IRQID_AP2MD_CCIF1_0
+#define    IRQ_AP2MD_CCIF1_1_CODE                    MD_IRQID_AP2MD_CCIF1_1
+#define    IRQ_IEBIT_CHECK_IRQ0_CODE                 MD_IRQID_IEBIT_CHECK_IRQ0
+#define    IRQ_IEBIT_CHECK_IRQ1_CODE                 MD_IRQID_IEBIT_CHECK_IRQ1
+#define    IRQ_IEBIT_CHECK_IRQ2_CODE                 MD_IRQID_IEBIT_CHECK_IRQ2
+#define    IRQ_IEBIT_CHECK_IRQ3_CODE                 MD_IRQID_IEBIT_CHECK_IRQ3
+#define    IRQ_IEBIT_CHECK_IRQ4_CODE                 MD_IRQID_IEBIT_CHECK_IRQ4
+#define    IRQ_IEBIT_CHECK_IRQ5_CODE                 MD_IRQID_IEBIT_CHECK_IRQ5
+#define    IRQ_IEBIT_CHECK_IRQ6_CODE                 MD_IRQID_IEBIT_CHECK_IRQ6
+#define    IRQ_IEBIT_CHECK_IRQ7_CODE                 MD_IRQID_IEBIT_CHECK_IRQ7
+#define    IRQ_IEBIT_CHECK_IRQ8_CODE                 MD_IRQID_IEBIT_CHECK_IRQ8
+#define    IRQ_IEBIT_CHECK_IRQ9_CODE                 MD_IRQID_IEBIT_CHECK_IRQ9
+#define    IRQ_IEBIT_CHECK_IRQ10_CODE                MD_IRQID_IEBIT_CHECK_IRQ10
+#define    IRQ_IEBIT_CHECK_IRQ11_CODE                MD_IRQID_IEBIT_CHECK_IRQ11
+#define    IRQ_NRL2_HRT_CODE                         MD_IRQID_NRL2_HRT
+#define    IRQ_NRL2_NOTIF_CODE                       MD_IRQID_NRL2_NOTIF
+#define    IRQ_NRL2_EXCEP_CODE                       MD_IRQID_NRL2_EXCEP
+#define    IRQ_NRL2_DPMAIF_MD_CODE                   MD_IRQID_NRL2_DPMAIF_MD
+#define    IRQ_RXDFE_IRQ0_CODE                       MD_IRQID_RXDFE_IRQ0
+#define    IRQ_IDC_UART_TX_FORCE_ON_CODE             MD_IRQID_IDC_UART_TX_FORCE_ON
+#define    IRQ_RXDFE_IRQ2_CODE                       MD_IRQID_RXDFE_IRQ2
+#define    IRQ_RXDFE_IRQ3_CODE                       MD_IRQID_RXDFE_IRQ3
+#define    IRQ_AP2MD_CONN_BGF_CCIF_0_CODE            MD_IRQID_AP2MD_CONN_BGF_CCIF_0
+#define    IRQ_MD_RXDFE_BB_DUMP_CODE                 MD_IRQID_MD_RXDFE_BB_DUMP
+#define    IRQ_AP2MD_CONN_BGF_CCIF_1_CODE            MD_IRQID_AP2MD_CONN_BGF_CCIF_1
+#define    IRQ_TXCRP_CODE                            MD_IRQID_TXCRP
+#define    IRQ_CM_NR_IRQ_CODE                        MD_IRQID_CM_NR_IRQ
+#define    IRQ_CM_NR_ERR_IRQ_CODE                    MD_IRQID_CM_NR_ERR_IRQ
+#define    IRQ_L1_LTE_SLEEP_IRQ_CODE                 MD_IRQID_L1_LTE_SLEEP_IRQ
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define    IRQ_D_GDMA_0_IRQ_CODE                     MD_IRQID_D_GDMA_0_IRQ
+#define    IRQ_D_GDMA_1_IRQ_CODE                     MD_IRQID_D_GDMA_1_IRQ
+#define    IRQ_D_GDMA_2_IRQ_CODE                     MD_IRQID_D_GDMA_2_IRQ
+#define    IRQ_D_GDMA_3_IRQ_CODE                     MD_IRQID_D_GDMA_3_IRQ
+#define    IRQ_D_GDMA_4_IRQ_CODE                     MD_IRQID_D_GDMA_4_IRQ
+#define    IRQ_D_GDMA_5_IRQ_CODE                     MD_IRQID_D_GDMA_5_IRQ
+#define    IRQ_PLL_GEARHP_RDY_CODE                   MD_IRQID_PLL_GEARHP_RDY
+#define    IRQ_REQ_ABNORM_IRQ_CODE                   MD_IRQID_REQ_ABNORM_IRQ
+#define    IRQ_NRL2_DPMAIF_MDMCU_CODE                MD_IRQID_NRL2_DPMAIF_MDMCU
+#define    IRQ_AP2MD_APWDT_IRQ_CODE                  MD_IRQID_AP2MD_APWDT_IRQ
+#define    IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE          MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ
+#define    IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE           MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ
+#define    IRQ_DUMMY_PRIORITY_CODE_5                 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define    IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE             MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define    IRQ_L1M_PHY_LTMR_IRQ_0_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define    IRQ_L1M_PHY_LTMR_IRQ_1_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define    IRQ_L1M_PHY_LTMR_IRQ_2_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define    IRQ_L1M_PHY_LTMR_IRQ_3_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define    IRQ_L1M_PHY_LTMR_IRQ_4_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define    IRQ_L1M_PHY_LTMR_IRQ_5_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define    IRQ_L1M_PHY_LTMR_IRQ_6_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define    IRQ_L1M_PHY_LTMR_IRQ_7_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define    IRQ_DUMMY_PRIORITY_CODE_6                 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define    IRQ_L1_LTE_WAKEUP_IRQ_CODE                MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define    IRQ_TDD_WAKEUP_IRQ_CODE                   MD_IRQID_TDD_WAKEUP_IRQ
+#define    IRQ_TDD_TIMER_L1D_1_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define    IRQ_TDD_TIMER_L1D_2_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define    IRQ_RTR_SLT_0_IRQ_CODE                    MD_IRQID_RTR_SLT_0_IRQ
+#define    IRQ_RTR_SLT_1_IRQ_CODE                    MD_IRQID_RTR_SLT_1_IRQ
+#define    IRQ_FDD_SLP_IRQ_CODE                      MD_IRQID_FDD_SLP_IRQ
+#define    IRQ_IRDBG_MCU_INT_CODE                    MD_IRQID_IRDBG_MCU_INT
+#define    IRQ_MD_DVFS_CTRL_IRQ_0_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define    IRQ_MD_DVFS_CTRL_IRQ_1_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define    IRQ_NR_SLP_WAKEUP_CODE                    MD_IRQID_NR_SLP_WAKEUP
+#define    IRQ_NR_SLP_SLEEP_CODE                     MD_IRQID_NR_SLP_SLEEP
+#define    IRQ_NR_TIMER_ERR_CODE                     MD_IRQID_NR_TIMER_ERR
+#define    IRQ_TXBSRP_CODE                           MD_IRQID_TXBSRP
+#define    IRQ_TXDFE_D_CODE                          MD_IRQID_TXDFE_D
+#define    IRQ_NR_EVENTGEN_ERR_CODE                  MD_IRQID_NR_EVENTGEN_ERR
+#define    IRQ_AIRQ_PAD_CODE                         MD_IRQID_AIRQ_PAD
+#define    IRQ_CSSYS_FDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_FDD_CS_IRQ
+#define    IRQ_CSSYS_TDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_TDD_CS_IRQ
+#define    IRQ_CSSYS_LTE_CS_IRQ_CODE                 MD_IRQID_CSSYS_LTE_CS_IRQ
+#define    IRQ_CSSYS_1X_CS_IRQ_CODE                  MD_IRQID_CSSYS_1X_CS_IRQ
+#define    IRQ_CSSYS_DO_CS_IRQ_CODE                  MD_IRQID_CSSYS_DO_CS_IRQ
+#define    IRQ_PCIE_INTERRUPT_OUT_CODE               MD_IRQID_PCIE_INTERRUPT_OUT
+#define    IRQ_UCNT_SCH_IRQ_CODE                     MD_IRQID_UCNT_SCH_IRQ
+#define    IRQ_UCNT_ERR_IRQ_CODE                     MD_IRQID_UCNT_ERR_IRQ
+#define    IRQ_UCNT_ADJ_IRQ_CODE                     MD_IRQID_UCNT_ADJ_IRQ
+#define    IRQ_SL_WAITSLEEP_CODE                     MD_IRQID_SL_WAITSLEEP
+#define    IRQ_PTP_THERM_INT_INT_CODE                MD_IRQID_PTP_THERM_INT_INT
+#define    IRQ_PTP_FSM_INT_CODE                      MD_IRQID_PTP_FSM_INT
+#define    IRQ_AP2MD_DAPC_CODE                       MD_IRQID_AP2MD_DAPC
+#define    IRQ_AP2MD_CCIF2_CODE                      MD_IRQID_AP2MD_CCIF2
+#define    IRQ_AP2MD_UFS_CODE                        MD_IRQID_AP2MD_UFS
+#define    IRQ_SSUSB_INTERRUPT_OUT_CODE              MD_IRQID_SSUSB_INTERRUPT_OUT
+#define    IRQ_AP2MD_MSDC0_CODE                      MD_IRQID_AP2MD_MSDC0
+#define    IRQ_MIPI_IRQ_CODE                         MD_IRQID_MIPI_IRQ
+#define    IRQ_CONN_BT_ISOCH_CODE                    MD_IRQID_CONN_BT_ISOCH
+#define    IRQ_RMPU_CTIREIGIN_CODE                   MD_IRQID_RMPU_CTIREIGIN
+#define    IRQ_FREQM_IRQ_CODE                        MD_IRQID_FREQM_IRQ
+#define    IRQ_BT_CVSD_CODE                          MD_IRQID_BT_CVSD
+#define    IRQ_SW_LISR0_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_0
+#define    IRQ_SW_LISR1_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_1
+#define    IRQ_SW_LISR2_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_2
+#define    IRQ_SW_LISR3_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_3
+#define    IRQ_SW_LISR4_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_4
+#define    IRQ_SW_LISR5_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_5
+#define    IRQ_SW_LISR6_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_6
+#define    IRQ_SW_LISR7_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_7
+#define    IRQ_SW_LISR8_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_8
+#define    IRQ_SW_LISR9_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_9
+#define    IRQ_SW_LISR10_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_10
+#define    IRQ_SW_LISR11_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_11
+#define    IRQ_SW_LISR12_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_12
+#define    IRQ_SW_LISR13_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_13
+#define    IRQ_SW_LISR14_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_14
+#define    IRQ_SW_LISR15_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_15
+#define    IRQ_SW_LISR16_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_16
+#define    IRQ_SW_LISR17_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_17
+#define    IRQ_SW_LISR18_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_18
+#define    IRQ_SW_LISR19_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_19
+#define    IRQ_SW_LISR20_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_20
+#define    IRQ_SW_LISR21_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_21
+#define    IRQ_SW_LISR22_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_22
+#define    IRQ_SW_LISR23_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_23
+#define    IRQ_SW_LISR24_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_24
+#define    IRQ_SW_LISR25_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_25
+#define    IRQ_SW_LISR26_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_26
+#define    IRQ_SW_LISR27_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_27
+#define    IRQ_SW_LISR28_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_28
+#define    IRQ_SW_LISR29_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_29
+#define    IRQ_SW_LISR30_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_30
+#define    IRQ_SW_LISR31_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_31
+#define    IRQ_SW_LISR32_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_32
+#define    IRQ_SW_LISR33_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_33
+#define    IRQ_SW_LISR34_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_34
+#define    IRQ_SW_LISR35_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_35
+#define    IRQ_SW_LISR36_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_36
+#define    IRQ_SW_LISR37_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_37
+#define    IRQ_SW_LISR38_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_38
+#define    IRQ_SW_LISR39_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_39
+#define    IRQ_SW_LISR40_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_40
+#define    IRQ_SW_LISR41_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_41
+#define    IRQ_SW_LISR42_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_42
+#define    IRQ_SW_LISR43_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_43
+#define    IRQ_SW_LISR44_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_44
+#define    IRQ_SW_LISR45_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_45
+#define    IRQ_SW_LISR46_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_46
+#define    IRQ_SW_LISR47_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_47
+#define    IRQ_SW_LISR48_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_48
+#define    IRQ_SW_LISR49_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_49
+#define    IRQ_SW_LISR50_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_50
+#define    IRQ_SW_LISR51_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_51
+#define    IRQ_SW_LISR52_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_52
+#define    IRQ_SW_LISR53_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_53
+#define    IRQ_SW_LISR54_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_54
+#define    IRQ_SW_LISR55_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_55
+#define    IRQ_SW_LISR56_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_56
+#define    IRQ_SW_LISR57_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_57
+#define    IRQ_SW_LISR58_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_58
+#define    IRQ_SW_LISR59_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_59
+#define    IRQ_SW_LISR60_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_60
+#define    IRQ_SW_LISR61_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_61
+#define    IRQ_SW_LISR62_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_62
+#define    IRQ_SW_LISR63_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_63
+#define    IRQ_SW_LISR64_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_64
+#define    IRQ_DUMMY_PRIORITY_CODE_8                 MD_IRQID_DUMMY_PRIORITY_IRQ8
+#define    IRQ_DUMMY_PRIORITY_CODE_9                 MD_IRQID_DUMMY_PRIORITY_IRQ9
+#define    IRQ_DUMMY_PRIORITY_CODE_10                MD_IRQID_DUMMY_PRIORITY_IRQ10
+#define    IRQ_DUMMY_PRIORITY_CODE_11                MD_IRQID_DUMMY_PRIORITY_IRQ11
+#define    IRQ_DUMMY_PRIORITY_CODE_12                MD_IRQID_DUMMY_PRIORITY_IRQ12
+#define    IRQ_DUMMY_PRIORITY_CODE_13                MD_IRQID_DUMMY_PRIORITY_IRQ13
+#define    IRQ_DUMMY_PRIORITY_CODE_14                MD_IRQID_DUMMY_PRIORITY_IRQ14
+#define    IRQ_DUMMY_PRIORITY_CODE_15                MD_IRQID_DUMMY_PRIORITY_IRQ15
+#define    IRQ_DUMMY_PRIORITY_CODE_16                MD_IRQID_DUMMY_PRIORITY_IRQ16
+#define    IRQ_DUMMY_PRIORITY_CODE_17                MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define    IRQ_DUMMY_PRIORITY_CODE_18                MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define    IRQ_DUMMY_PRIORITY_CODE_19                MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define    IRQ_DUMMY_PRIORITY_CODE_20                MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define    IRQ_DUMMY_PRIORITY_CODE_21                MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define    IRQ_DUMMY_PRIORITY_CODE_22                MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define    IRQ_DUMMY_PRIORITY_CODE_23                MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define    IRQ_DUMMY_PRIORITY_CODE_24                MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define    IRQ_DUMMY_PRIORITY_CODE_25                MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define    IRQ_DUMMY_PRIORITY_CODE_26                MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define    IRQ_DUMMY_PRIORITY_CODE_27                MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define    IRQ_DUMMY_PRIORITY_CODE_28                MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define    IRQ_DUMMY_PRIORITY_CODE_29                MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define    IRQ_DUMMY_PRIORITY_CODE_30                MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define    IRQ_SW_MODIS_MASE_HMU_CODE                IRQ_DUMMY_PRIORITY_CODE_25
+#define    IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE         IRQ_DUMMY_PRIORITY_CODE_26
+#define    IRQ_SW_MODIS_MASE_NR_TXLISR_CODE          IRQ_DUMMY_PRIORITY_CODE_27
+#define    IRQ_L1_PAE_SW_LISR0                       IRQ_DUMMY_PRIORITY_CODE_28
+#define    IRQ_L1_PAE_SW_LISR1                       IRQ_DUMMY_PRIORITY_CODE_29
+#define    IRQ_L1_PAE_SW_LISR2                       IRQ_DUMMY_PRIORITY_CODE_30
+#endif 
+
+
+/* IRQ Affinity Group Definition */
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+    /* Group0(0) */                                                                             0xFFE, \
+    /* Group1(1) */                                                                             0xFFD, \
+    /* Group2(2) */                                                                             0xFFB, \
+    /* Group3(3) */                                                                             0xFF7, \
+    /* Group4(4) */                                                                             0xFEF, \
+    /* Group5(5) */                                                                             0xFDF, \
+    /* Group6(6) */                                                                             0xFBF, \
+    /* Group7(7) */                                                                             0xF7F, \
+    /* Group8(8) */                                                                             0xEFF, \
+    /* Group9(9) */                                                                             0xDFF, \
+    /* Group10(10) */                                                                           0xBFF, \
+    /* Group11(11) */                                                                           0x7FF, \
+    /* Group12(1,4) */                                                                          0xFED, \
+    /* Group13(0,1,2) */                                                                        0xFF8, \
+    /* Group14(3,6,9) */                                                                        0xDB7, \
+    /* Group15(0,3,6,9) */                                                                      0xDB6, \
+    /* Group16(3,4,6,7,9,10) */                                                                 0x927, \
+    /* Group17(0,1,2,3,4,6,7,9,10) */                                                           0x920, \
+    /* Group18(3,4,5,6,7,8,9,10,11) */                                                          0x007, \
+    /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */                                                    0x000, \
+    /* Group20(3,4,6,7,9,10)        -> Reserved for NR runtime change affinity */               0x927, \
+    /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */               0x007, \
+    /* Group22(2)                   -> Reserved for LTE runtime change affinity */              0xFFB, \
+    /* Group23(0,2,3,4,6,7,9,10)    -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */  0x922, \
+    /* Group24(3,6,7,9,10)          -> Temp solution for IRQ0xEE to not preempt NR RX IRQs */   0x937, \
+    /* Group25(0,3,5,6,7,8,9,11)    -> Workaround for Serdes HW bug */                          0x416, \
+    /* Group26(0,2,3,6,7,9,10)      -> Workaround for IRQ0x80 pending hard affinity HRT IRQs */ 0x932, \
+    /* Group27 */                                                                               0xFFF, \
+    /* Group28 */                                                                               0xFFF, \
+    /* Group29 */                                                                               0xFFF, \
+    /* Group30 */                                                                               0xFFF, \
+    /* Group31 */                                                                               0xFFF,
+#endif
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions - 
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0         0   //(0)
+#define IRQ_AFFINITY_GROUP_VPE1         1   //(1)
+#define IRQ_AFFINITY_GROUP_VPE2         2   //(2)
+#define IRQ_AFFINITY_GROUP_VPE3         3   //(3)
+#define IRQ_AFFINITY_GROUP_VPE4         4   //(4)
+#define IRQ_AFFINITY_GROUP_VPE5         5   //(5)
+#define IRQ_AFFINITY_GROUP_VPE6         6   //(6)
+#define IRQ_AFFINITY_GROUP_VPE7         7   //(7)
+#define IRQ_AFFINITY_GROUP_VPE8	        8   //(8)
+#define IRQ_AFFINITY_GROUP_VPE9         9   //(9)
+#define IRQ_AFFINITY_GROUP_VPE10        10  //(10)
+#define IRQ_AFFINITY_GROUP_VPE11        11  //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4     12  //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0    13  //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR    14  //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP   15  //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR       16  //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP      17  //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR      18  //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE      19  //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+#define MAX_NUM_TASKS          256
+#define MAX_HISR_PRIORITY      2
+
+typedef enum
+{
+    VPE_STATUS_LISR_HIGHEST      = 0,
+    VPE_STATUS_LISR_LOWEST       = 342,
+    VPE_STATUS_HISR_TASK_HIGHEST = 512,
+    VPE_STATUS_HISR_TASK_LOWEST  = VPE_STATUS_HISR_TASK_HIGHEST + MAX_NUM_TASKS + MAX_HISR_PRIORITY, 
+    VPE_STATUS_END               = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_MT6833_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6833_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6833_SW_Handle.h
new file mode 100644
index 0000000..39efca2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6833_SW_Handle.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6833_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   MT6833
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE0  = Karthigeyan Reddy
+      SW_TRIGGER_CODE1  = Karthigeyan Reddy
+      SW_TRIGGER_CODE2  = Karthigeyan Reddy
+      SW_TRIGGER_CODE3  = Karthigeyan Reddy
+      SW_TRIGGER_CODE4  = Karthigeyan Reddy
+      SW_TRIGGER_CODE5  = Karthigeyan Reddy
+      SW_TRIGGER_CODE6  = Zengling Jin
+      SW_TRIGGER_CODE7  = Zengling Jin
+      SW_TRIGGER_CODE8  = Zengling Jin
+      SW_TRIGGER_CODE9  = Cruze Yu
+      SW_TRIGGER_CODE10 = Cruze Yu
+      SW_TRIGGER_CODE11 = Cruze Yu
+      SW_TRIGGER_CODE12 = Cruze Yu
+      SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+      SW_TRIGGER_CODE14 = HW Jheng
+      SW_TRIGGER_CODE15 = Frank Hu
+      SW_TRIGGER_CODE16 = KH Hsiao
+      SW_TRIGGER_CODE17 = Deepti Varadarajan
+      SW_TRIGGER_CODE18 = Owen Ho
+      SW_TRIGGER_CODE19 = Owen Ho
+      SW_TRIGGER_CODE20 = Owen Ho
+      SW_TRIGGER_CODE21 = Owen Ho
+      SW_TRIGGER_CODE22 = Jun-Ying Huang
+      SW_TRIGGER_CODE23 = Jun-Ying Huang
+      SW_TRIGGER_CODE24 = Jun-Ying Huang
+      SW_TRIGGER_CODE25 = Jun-Ying Huang
+      SW_TRIGGER_CODE26 = Wade Huang
+      SW_TRIGGER_CODE27 = Tee-Yuen Chun
+      SW_TRIGGER_CODE28 = YY Hsieh 
+      SW_TRIGGER_CODE29 = Hamilton Liang
+      SW_TRIGGER_CODE30 = HW Jheng
+      SW_TRIGGER_CODE31 = Weimin Zeng
+      SW_TRIGGER_CODE32 = Weimin Zeng
+      SW_TRIGGER_CODE33 = Jocobrian Chang
+      SW_TRIGGER_CODE34 = JiaHong Hsu
+      SW_TRIGGER_CODE35 = Cheng-Long Wu
+      SW_TRIGGER_CODE36 = Cheng-Long Wu
+      SW_TRIGGER_CODE37 = Jocobrian Chang
+      SW_TRIGGER_CODE38 = Jocobrian Chang
+      SW_TRIGGER_CODE39 = Jocobrian Chang
+      SW_TRIGGER_CODE40 = Shu-Wei Ho
+      SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+      SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+  */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6853.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6853.h
new file mode 100644
index 0000000..518e661
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6853.h
@@ -0,0 +1,564 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6853.h
+ *
+ * Project:
+ * --------
+ *   MT6853
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6853_H__
+#define __INTRCTRL_MT6853_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+
+#define NUM_IRQ_SOURCES          (368)
+
+/* CIRQ Interrupt Sources */
+#define    IRQ_USIM0_CODE                            MD_IRQID_USIM0
+#define    IRQ_USIM1_CODE                            MD_IRQID_USIM1
+#define    IRQ_TDMA_CTIRQ1_CODE                      MD_IRQID_TDMA_CTIRQ1
+#define    IRQ_TDMA_CTIRQ2_CODE                      MD_IRQID_TDMA_CTIRQ2
+#define    IRQ_TDMA_CTIRQ3_CODE                      MD_IRQID_TDMA_CTIRQ3
+#define    IRQ_TDMA_WAKEUP_IRQ_CODE                  MD_IRQID_TDMA_WAKEUP_IRQ
+#define    IRQ_OST_CODE                              MD_IRQID_OST
+#define    IRQ_MDRTT_CODE                            MD_IRQID_MDRTT
+#define    IRQ_MDEVDO_CODE                           MD_IRQID_MDEVDO
+#define    IRQ_ULSP_LOG_MCU_RT_INT_CODE              MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define    IRQ_ULSP_LOG_MCU_OD_INT_CODE              MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define    IRQ_ULSP_LOG_DSP4G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define    IRQ_ULSP_LOG_DSP4G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define    IRQ_ULSP_LOG_DSP5G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define    IRQ_ULSP_LOG_DSP5G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define    IRQ_SHARE_D12MINT1_CODE                   MD_IRQID_SHARE_D12MINT1
+#define    IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE        MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define    IRQ_AIRQ_SERDES_CODE                      MD_IRQID_AIRQ_SERDES
+#define    IRQ_AIRQ_COS_CODE                         MD_IRQID_AIRQ_COS
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define    IRQ_PPPHA_ENC0_INT_CODE                   MD_IRQID_PPPHA_ENC0_INT
+#define    IRQ_PPPHA_ENC1_INT_CODE                   MD_IRQID_PPPHA_ENC1_INT
+#define    IRQ_PPPHA_DEC0_INT_CODE                   MD_IRQID_PPPHA_DEC0_INT
+#define    IRQ_PPPHA_DEC1_INT_CODE                   MD_IRQID_PPPHA_DEC1_INT
+#define    IRQ_CS_NR_IRQ_CODE                        MD_IRQID_CS_NR_IRQ
+#define    IRQ_CS_NR_ERR_IRQ_CODE                    MD_IRQID_CS_NR_ERR_IRQ
+#define    IRQ_SDF_OVERFLOW_IRQ_CODE                 MD_IRQID_SDF_OVERFLOW_IRQ
+#define    IRQ_MCUMMU_INT_CODE                       MD_IRQID_MCUMMU_INT
+#define    IRQ_BIGRAM_0_IRQ_0_CODE                   MD_IRQID_BIGRAM_0_IRQ_0
+#define    IRQ_COS_PREP_INT_CODE                     MD_IRQID_COS_PREP_INT
+#define    IRQ_TRACE_INT_CODE                        MD_IRQID_TRACE_INT
+#define    IRQ_NR_TIMER_IRQ0_CODE                    MD_IRQID_NR_TIMER_IRQ0
+#define    IRQ_NR_TIMER_IRQ1_CODE                    MD_IRQID_NR_TIMER_IRQ1
+#define    IRQ_NR_TIMER_IRQ2_CODE                    MD_IRQID_NR_TIMER_IRQ2
+#define    IRQ_NR_TIMER_IRQ3_CODE                    MD_IRQID_NR_TIMER_IRQ3
+#define    IRQ_NR_TIMER_IRQ4_CODE                    MD_IRQID_NR_TIMER_IRQ4
+#define    IRQ_NR_TIMER_IRQ5_CODE                    MD_IRQID_NR_TIMER_IRQ5
+#define    IRQ_NR_TIMER_IRQ6_CODE                    MD_IRQID_NR_TIMER_IRQ6
+#define    IRQ_NR_TIMER_IRQ7_CODE                    MD_IRQID_NR_TIMER_IRQ7
+#define    IRQ_NR_TIMER_IRQ8_CODE                    MD_IRQID_NR_TIMER_IRQ8
+#define    IRQ_NR_TIMER_IRQ9_CODE                    MD_IRQID_NR_TIMER_IRQ9
+#define    IRQ_NR_TIMER_IRQ10_CODE                   MD_IRQID_NR_TIMER_IRQ10
+#define    IRQ_NR_TIMER_IRQ11_CODE                   MD_IRQID_NR_TIMER_IRQ11
+#define    IRQ_NR_TIMER_IRQ12_CODE                   MD_IRQID_NR_TIMER_IRQ12
+#define    IRQ_NR_TIMER_IRQ13_CODE                   MD_IRQID_NR_TIMER_IRQ13
+#define    IRQ_NR_TIMER_IRQ14_CODE                   MD_IRQID_NR_TIMER_IRQ14
+#define    IRQ_NR_TIMER_IRQ15_CODE                   MD_IRQID_NR_TIMER_IRQ15
+#define    IRQ_NR_TIMER_IRQ16_CODE                   MD_IRQID_NR_TIMER_IRQ16
+#define    IRQ_NR_TIMER_IRQ17_CODE                   MD_IRQID_NR_TIMER_IRQ17
+#define    IRQ_NR_TIMER_IRQ18_CODE                   MD_IRQID_NR_TIMER_IRQ18
+#define    IRQ_NR_TIMER_IRQ19_CODE                   MD_IRQID_NR_TIMER_IRQ19
+#define    IRQ_NR_TIMER_IRQ20_CODE                   MD_IRQID_NR_TIMER_IRQ20
+#define    IRQ_NR_TIMER_IRQ21_CODE                   MD_IRQID_NR_TIMER_IRQ21
+#define    IRQ_NR_TIMER_IRQ22_CODE                   MD_IRQID_NR_TIMER_IRQ22
+#define    IRQ_NR_TIMER_IRQ23_CODE                   MD_IRQID_NR_TIMER_IRQ23
+#define    IRQ_NR_TIMER_IRQ24_CODE                   MD_IRQID_NR_TIMER_IRQ24
+#define    IRQ_NR_TIMER_IRQ25_CODE                   MD_IRQID_NR_TIMER_IRQ25
+#define    IRQ_NR_TIMER_IRQ26_CODE                   MD_IRQID_NR_TIMER_IRQ26
+#define    IRQ_NR_TIMER_IRQ27_CODE                   MD_IRQID_NR_TIMER_IRQ27
+#define    IRQ_NR_TIMER_IRQ28_CODE                   MD_IRQID_NR_TIMER_IRQ28
+#define    IRQ_NR_TIMER_IRQ29_CODE                   MD_IRQID_NR_TIMER_IRQ29
+#define    IRQ_NR_TIMER_IRQ30_CODE                   MD_IRQID_NR_TIMER_IRQ30
+#define    IRQ_NR_TIMER_IRQ31_CODE                   MD_IRQID_NR_TIMER_IRQ31
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define    IRQ_NR_TIMER_CNTDN_IRQ0_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define    IRQ_NR_TIMER_CNTDN_IRQ1_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define    IRQ_NR_TIMER_CNTDN_IRQ2_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define    IRQ_NR_TIMER_CNTDN_IRQ3_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define    IRQ_NR_EVENTGEN_SPU_CODE                  MD_IRQID_NR_EVENTGEN_SPU
+#define    IRQ_SI_CM_ERR_CODE                        MD_IRQID_SI_CM_ERR
+#define    IRQ_SI_CM_PCINT_CODE                      MD_IRQID_SI_CM_PCINT
+#define    IRQ_MDM2C_U3G_CODE                        MD_IRQID_MDM2C_U3G
+#define    IRQ_RAKE_CMIF_M2C_IRQ_0_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define    IRQ_RAKE_CMIF_M2C_IRQ_1_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define    IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define    IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define    IRQ_RAKE_CMIF_PD_DO_IRQ_CODE              MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define    IRQ_MDMCU_BUSMON_MATCH_STS_CODE           MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define    IRQ_MDINFRA_BUSMON_MATCH_STS_CODE         MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define    IRQ_ELMTOP_EMI_IRQ_CODE                   MD_IRQID_ELMTOP_EMI_IRQ
+#define    IRQ_ELM_DMA_IRQ_CODE                      MD_IRQID_ELM_DMA_IRQ
+#define    IRQ_BUSMPU_IRQ_CODE                       MD_IRQID_BUSMPU_IRQ
+#define    IRQ_ST1X_CPINT_CODE                       MD_IRQID_ST1X_CPINT
+#define    IRQ_ST1x_HALF_CPINT_CODE                  MD_IRQID_ST1x_HALF_CPINT
+#define    IRQ_ST1x_CFG_CPINT_CODE                   MD_IRQID_ST1x_CFG_CPINT
+#define    IRQ_ST1x_WAKEUP_IRQ_CODE                  MD_IRQID_ST1x_WAKEUP_IRQ
+#define    IRQ_STDO_CPINT_CODE                       MD_IRQID_STDO_CPINT
+#define    IRQ_STDO_HALF_CPINT_CODE                  MD_IRQID_STDO_HALF_CPINT
+#define    IRQ_STDO_CFG_CPINT_CODE                   MD_IRQID_STDO_CFG_CPINT
+#define    IRQ_STDO_WAKEUP_IRQ_CODE                  MD_IRQID_STDO_WAKEUP_IRQ
+#define    IRQ_UART_MD0_CODE                         MD_IRQID_UART_MD0
+#define    IRQ_UART_MD1_CODE                         MD_IRQID_UART_MD1
+#define    IRQ_EINT0_CODE                            MD_IRQID_EINT0
+#define    IRQ_EINT1_CODE                            MD_IRQID_EINT1
+#define    IRQ_EINT2_CODE                            MD_IRQID_EINT2
+#define    IRQ_EINT3_CODE                            MD_IRQID_EINT3
+#define    IRQ_EINT_SHARE_CODE                       MD_IRQID_EINT_SHARE
+#define    IRQ_GPTM1_CODE                            MD_IRQID_GPTM1
+#define    IRQ_GPTM2_CODE                            MD_IRQID_GPTM2
+#define    IRQ_GPTM3_CODE                            MD_IRQID_GPTM3
+#define    IRQ_GPTM4_CODE                            MD_IRQID_GPTM4
+#define    IRQ_GPTM5_CODE                            MD_IRQID_GPTM5
+#define    IRQ_GPTM6_CODE                            MD_IRQID_GPTM6
+#define    IRQ_GPTM7_CODE                            MD_IRQID_GPTM7
+#define    IRQ_GPTM8_CODE                            MD_IRQID_GPTM8
+#define    IRQ_GPTM9_CODE                            MD_IRQID_GPTM9
+#define    IRQ_GPTM10_CODE                           MD_IRQID_GPTM10
+#define    IRQ_GPTM11_CODE                           MD_IRQID_GPTM11
+#define    IRQ_IDC_PM_INT_CODE                       MD_IRQID_IDC_PM_INT
+#define    IRQ_IDC_UART_IRQ_CODE                     MD_IRQID_IDC_UART_IRQ
+#define    IRQ_MDGDMA_FDMA5_CODE                     MD_IRQID_MDGDMA_FDMA5
+#define    IRQ_MDGDMA_FDMA6_CODE                     MD_IRQID_MDGDMA_FDMA6
+#define    IRQ_TDMA_CTIRQ4_CODE                      MD_IRQID_TDMA_CTIRQ4
+#define    IRQ_PDMA_CODE                             MD_IRQID_PDMA
+#define    IRQ_MDINFRA_BUS_DECERROR_CODE             MD_IRQID_MDINFRA_BUS_DECERROR
+#define    IRQ_I2C_TOP_INT_CODE                      MD_IRQID_I2C_TOP_INT
+#define    IRQ_SOE_CODE                              MD_IRQID_SOE
+#define    IRQ_ABM_INT_CODE                          MD_IRQID_ABM_INT
+#define    IRQ_ABM_ERROR_INT_CODE                    MD_IRQID_ABM_ERROR_INT
+#define    IRQ_USIP0_CODE                            MD_IRQID_USIP0
+#define    IRQ_USIP1_CODE                            MD_IRQID_USIP1
+#define    IRQ_USIP2_CODE                            MD_IRQID_USIP2
+#define    IRQ_USIP3_CODE                            MD_IRQID_USIP3
+#define    IRQ_USIP4_CODE                            MD_IRQID_USIP4
+#define    IRQ_USIP5_CODE                            MD_IRQID_USIP5
+#define    IRQ_USIP6_CODE                            MD_IRQID_USIP6
+#define    IRQ_USIP7_CODE                            MD_IRQID_USIP7
+#define    IRQ_USIP8_CODE                            MD_IRQID_USIP8
+#define    IRQ_USIP9_CODE                            MD_IRQID_USIP9
+#define    IRQ_USIP10_CODE                           MD_IRQID_USIP10
+#define    IRQ_USIP11_CODE                           MD_IRQID_USIP11
+#define    IRQ_USIP12_CODE                           MD_IRQID_USIP12
+#define    IRQ_USIP13_CODE                           MD_IRQID_USIP13
+#define    IRQ_TX_NR_CC0_IRQ_CODE                    MD_IRQID_TX_NR_CC0_IRQ
+#define    IRQ_TX_NR_CC1_IRQ_CODE                    MD_IRQID_TX_NR_CC1_IRQ
+#define    IRQ_TX_NR_ERR_CC_IRQ_CODE                 MD_IRQID_TX_NR_ERR_CC_IRQ
+#define    IRQ_MDMCU_SPU_IRQ_CODE                    MD_IRQID_MDMCU_SPU_IRQ
+#define    IRQ_DEM_TRIG_PS_INT_LE_CODE               MD_IRQID_DEM_TRIG_PS_INT_LE
+#define    IRQ_ECT_CODE                              MD_IRQID_ECT
+#define    IRQ_MDMCU_BUS_DECERR_IRQ_CODE             MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define    IRQ_MDMCU_OSTD_THROTTLE_CODE              MD_IRQID_MDMCU_OSTD_THROTTLE
+#define    IRQ_SHAOLIN_OSTD_THROTTLE_CODE            MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define    IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE         MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define    IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_AP2MD_CONN_WF_CCIF_0_CODE             MD_IRQID_AP2MD_CONN_WF_CCIF_0
+#define    IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_AP2MD_CONN_WF_CCIF_1_CODE             MD_IRQID_AP2MD_CONN_WF_CCIF_1
+#define    IRQ_MDWDT_CODE                            MD_IRQID_MDWDT
+#define    IRQ_MDGDMA_FDMA0_2_CODE                   MD_IRQID_MDGDMA_FDMA0_2
+#define    IRQ_MDGDMA_FDMA1_CODE                     MD_IRQID_MDGDMA_FDMA1
+#define    IRQ_MDGDMA_FDMA3_CODE                     MD_IRQID_MDGDMA_FDMA3
+#define    IRQ_MDGDMA_FDMA4_CODE                     MD_IRQID_MDGDMA_FDMA4
+#define    IRQ_MDGDMA_HDMA0_1_CODE                   MD_IRQID_MDGDMA_HDMA0_1
+#define    IRQ_MDGDMA_HDMA2_3_CODE                   MD_IRQID_MDGDMA_HDMA2_3
+#define    IRQ_AP2MD_CCIF0_0_CODE                    MD_IRQID_AP2MD_CCIF0_0
+#define    IRQ_AP2MD_CCIF0_1_CODE                    MD_IRQID_AP2MD_CCIF0_1
+#define    IRQ_AP2MD_CCIF1_0_CODE                    MD_IRQID_AP2MD_CCIF1_0
+#define    IRQ_AP2MD_CCIF1_1_CODE                    MD_IRQID_AP2MD_CCIF1_1
+#define    IRQ_IEBIT_CHECK_IRQ0_CODE                 MD_IRQID_IEBIT_CHECK_IRQ0
+#define    IRQ_IEBIT_CHECK_IRQ1_CODE                 MD_IRQID_IEBIT_CHECK_IRQ1
+#define    IRQ_IEBIT_CHECK_IRQ2_CODE                 MD_IRQID_IEBIT_CHECK_IRQ2
+#define    IRQ_IEBIT_CHECK_IRQ3_CODE                 MD_IRQID_IEBIT_CHECK_IRQ3
+#define    IRQ_IEBIT_CHECK_IRQ4_CODE                 MD_IRQID_IEBIT_CHECK_IRQ4
+#define    IRQ_IEBIT_CHECK_IRQ5_CODE                 MD_IRQID_IEBIT_CHECK_IRQ5
+#define    IRQ_IEBIT_CHECK_IRQ6_CODE                 MD_IRQID_IEBIT_CHECK_IRQ6
+#define    IRQ_IEBIT_CHECK_IRQ7_CODE                 MD_IRQID_IEBIT_CHECK_IRQ7
+#define    IRQ_IEBIT_CHECK_IRQ8_CODE                 MD_IRQID_IEBIT_CHECK_IRQ8
+#define    IRQ_IEBIT_CHECK_IRQ9_CODE                 MD_IRQID_IEBIT_CHECK_IRQ9
+#define    IRQ_IEBIT_CHECK_IRQ10_CODE                MD_IRQID_IEBIT_CHECK_IRQ10
+#define    IRQ_IEBIT_CHECK_IRQ11_CODE                MD_IRQID_IEBIT_CHECK_IRQ11
+#define    IRQ_NRL2_HRT_CODE                         MD_IRQID_NRL2_HRT
+#define    IRQ_NRL2_NOTIF_CODE                       MD_IRQID_NRL2_NOTIF
+#define    IRQ_NRL2_EXCEP_CODE                       MD_IRQID_NRL2_EXCEP
+#define    IRQ_NRL2_DPMAIF_MD_CODE                   MD_IRQID_NRL2_DPMAIF_MD
+#define    IRQ_RXDFE_IRQ0_CODE                       MD_IRQID_RXDFE_IRQ0
+#define    IRQ_IDC_UART_TX_FORCE_ON_CODE             MD_IRQID_IDC_UART_TX_FORCE_ON
+#define    IRQ_RXDFE_IRQ2_CODE                       MD_IRQID_RXDFE_IRQ2
+#define    IRQ_RXDFE_IRQ3_CODE                       MD_IRQID_RXDFE_IRQ3
+#define    IRQ_AP2MD_CONN_BGF_CCIF_0_CODE            MD_IRQID_AP2MD_CONN_BGF_CCIF_0
+#define    IRQ_MD_RXDFE_BB_DUMP_CODE                 MD_IRQID_MD_RXDFE_BB_DUMP
+#define    IRQ_AP2MD_CONN_BGF_CCIF_1_CODE            MD_IRQID_AP2MD_CONN_BGF_CCIF_1
+#define    IRQ_TXCRP_CODE                            MD_IRQID_TXCRP
+#define    IRQ_CM_NR_IRQ_CODE                        MD_IRQID_CM_NR_IRQ
+#define    IRQ_CM_NR_ERR_IRQ_CODE                    MD_IRQID_CM_NR_ERR_IRQ
+#define    IRQ_L1_LTE_SLEEP_IRQ_CODE                 MD_IRQID_L1_LTE_SLEEP_IRQ
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define    IRQ_D_GDMA_0_IRQ_CODE                     MD_IRQID_D_GDMA_0_IRQ
+#define    IRQ_D_GDMA_1_IRQ_CODE                     MD_IRQID_D_GDMA_1_IRQ
+#define    IRQ_D_GDMA_2_IRQ_CODE                     MD_IRQID_D_GDMA_2_IRQ
+#define    IRQ_D_GDMA_3_IRQ_CODE                     MD_IRQID_D_GDMA_3_IRQ
+#define    IRQ_D_GDMA_4_IRQ_CODE                     MD_IRQID_D_GDMA_4_IRQ
+#define    IRQ_D_GDMA_5_IRQ_CODE                     MD_IRQID_D_GDMA_5_IRQ
+#define    IRQ_PLL_GEARHP_RDY_CODE                   MD_IRQID_PLL_GEARHP_RDY
+#define    IRQ_REQ_ABNORM_IRQ_CODE                   MD_IRQID_REQ_ABNORM_IRQ
+#define    IRQ_NRL2_DPMAIF_MDMCU_CODE                MD_IRQID_NRL2_DPMAIF_MDMCU
+#define    IRQ_AP2MD_APWDT_IRQ_CODE                  MD_IRQID_AP2MD_APWDT_IRQ
+#define    IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE          MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ
+#define    IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE           MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ
+#define    IRQ_DUMMY_PRIORITY_CODE_5                 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define    IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE             MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define    IRQ_L1M_PHY_LTMR_IRQ_0_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define    IRQ_L1M_PHY_LTMR_IRQ_1_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define    IRQ_L1M_PHY_LTMR_IRQ_2_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define    IRQ_L1M_PHY_LTMR_IRQ_3_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define    IRQ_L1M_PHY_LTMR_IRQ_4_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define    IRQ_L1M_PHY_LTMR_IRQ_5_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define    IRQ_L1M_PHY_LTMR_IRQ_6_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define    IRQ_L1M_PHY_LTMR_IRQ_7_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define    IRQ_DUMMY_PRIORITY_CODE_6                 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define    IRQ_L1_LTE_WAKEUP_IRQ_CODE                MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define    IRQ_TDD_WAKEUP_IRQ_CODE                   MD_IRQID_TDD_WAKEUP_IRQ
+#define    IRQ_TDD_TIMER_L1D_1_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define    IRQ_TDD_TIMER_L1D_2_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define    IRQ_RTR_SLT_0_IRQ_CODE                    MD_IRQID_RTR_SLT_0_IRQ
+#define    IRQ_RTR_SLT_1_IRQ_CODE                    MD_IRQID_RTR_SLT_1_IRQ
+#define    IRQ_FDD_SLP_IRQ_CODE                      MD_IRQID_FDD_SLP_IRQ
+#define    IRQ_IRDBG_MCU_INT_CODE                    MD_IRQID_IRDBG_MCU_INT
+#define    IRQ_MD_DVFS_CTRL_IRQ_0_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define    IRQ_MD_DVFS_CTRL_IRQ_1_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define    IRQ_NR_SLP_WAKEUP_CODE                    MD_IRQID_NR_SLP_WAKEUP
+#define    IRQ_NR_SLP_SLEEP_CODE                     MD_IRQID_NR_SLP_SLEEP
+#define    IRQ_NR_TIMER_ERR_CODE                     MD_IRQID_NR_TIMER_ERR
+#define    IRQ_TXBSRP_CODE                           MD_IRQID_TXBSRP
+#define    IRQ_TXDFE_D_CODE                          MD_IRQID_TXDFE_D
+#define    IRQ_NR_EVENTGEN_ERR_CODE                  MD_IRQID_NR_EVENTGEN_ERR
+#define    IRQ_AIRQ_PAD_CODE                         MD_IRQID_AIRQ_PAD
+#define    IRQ_CSSYS_FDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_FDD_CS_IRQ
+#define    IRQ_CSSYS_TDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_TDD_CS_IRQ
+#define    IRQ_CSSYS_LTE_CS_IRQ_CODE                 MD_IRQID_CSSYS_LTE_CS_IRQ
+#define    IRQ_CSSYS_1X_CS_IRQ_CODE                  MD_IRQID_CSSYS_1X_CS_IRQ
+#define    IRQ_CSSYS_DO_CS_IRQ_CODE                  MD_IRQID_CSSYS_DO_CS_IRQ
+#define    IRQ_PCIE_INTERRUPT_OUT_CODE               MD_IRQID_PCIE_INTERRUPT_OUT
+#define    IRQ_UCNT_SCH_IRQ_CODE                     MD_IRQID_UCNT_SCH_IRQ
+#define    IRQ_UCNT_ERR_IRQ_CODE                     MD_IRQID_UCNT_ERR_IRQ
+#define    IRQ_UCNT_ADJ_IRQ_CODE                     MD_IRQID_UCNT_ADJ_IRQ
+#define    IRQ_SL_WAITSLEEP_CODE                     MD_IRQID_SL_WAITSLEEP
+#define    IRQ_PTP_THERM_INT_INT_CODE                MD_IRQID_PTP_THERM_INT_INT
+#define    IRQ_PTP_FSM_INT_CODE                      MD_IRQID_PTP_FSM_INT
+#define    IRQ_AP2MD_DAPC_CODE                       MD_IRQID_AP2MD_DAPC
+#define    IRQ_AP2MD_CCIF2_CODE                      MD_IRQID_AP2MD_CCIF2
+#define    IRQ_AP2MD_UFS_CODE                        MD_IRQID_AP2MD_UFS
+#define    IRQ_SSUSB_INTERRUPT_OUT_CODE              MD_IRQID_SSUSB_INTERRUPT_OUT
+#define    IRQ_AP2MD_MSDC0_CODE                      MD_IRQID_AP2MD_MSDC0
+#define    IRQ_MIPI_IRQ_CODE                         MD_IRQID_MIPI_IRQ
+#define    IRQ_CONN_BT_ISOCH_CODE                    MD_IRQID_CONN_BT_ISOCH
+#define    IRQ_RMPU_CTIREIGIN_CODE                   MD_IRQID_RMPU_CTIREIGIN
+#define    IRQ_FREQM_IRQ_CODE                        MD_IRQID_FREQM_IRQ
+#define    IRQ_BT_CVSD_CODE                          MD_IRQID_BT_CVSD
+#define    IRQ_SW_LISR0_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_0
+#define    IRQ_SW_LISR1_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_1
+#define    IRQ_SW_LISR2_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_2
+#define    IRQ_SW_LISR3_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_3
+#define    IRQ_SW_LISR4_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_4
+#define    IRQ_SW_LISR5_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_5
+#define    IRQ_SW_LISR6_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_6
+#define    IRQ_SW_LISR7_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_7
+#define    IRQ_SW_LISR8_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_8
+#define    IRQ_SW_LISR9_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_9
+#define    IRQ_SW_LISR10_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_10
+#define    IRQ_SW_LISR11_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_11
+#define    IRQ_SW_LISR12_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_12
+#define    IRQ_SW_LISR13_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_13
+#define    IRQ_SW_LISR14_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_14
+#define    IRQ_SW_LISR15_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_15
+#define    IRQ_SW_LISR16_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_16
+#define    IRQ_SW_LISR17_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_17
+#define    IRQ_SW_LISR18_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_18
+#define    IRQ_SW_LISR19_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_19
+#define    IRQ_SW_LISR20_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_20
+#define    IRQ_SW_LISR21_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_21
+#define    IRQ_SW_LISR22_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_22
+#define    IRQ_SW_LISR23_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_23
+#define    IRQ_SW_LISR24_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_24
+#define    IRQ_SW_LISR25_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_25
+#define    IRQ_SW_LISR26_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_26
+#define    IRQ_SW_LISR27_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_27
+#define    IRQ_SW_LISR28_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_28
+#define    IRQ_SW_LISR29_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_29
+#define    IRQ_SW_LISR30_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_30
+#define    IRQ_SW_LISR31_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_31
+#define    IRQ_SW_LISR32_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_32
+#define    IRQ_SW_LISR33_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_33
+#define    IRQ_SW_LISR34_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_34
+#define    IRQ_SW_LISR35_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_35
+#define    IRQ_SW_LISR36_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_36
+#define    IRQ_SW_LISR37_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_37
+#define    IRQ_SW_LISR38_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_38
+#define    IRQ_SW_LISR39_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_39
+#define    IRQ_SW_LISR40_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_40
+#define    IRQ_SW_LISR41_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_41
+#define    IRQ_SW_LISR42_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_42
+#define    IRQ_SW_LISR43_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_43
+#define    IRQ_SW_LISR44_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_44
+#define    IRQ_SW_LISR45_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_45
+#define    IRQ_SW_LISR46_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_46
+#define    IRQ_SW_LISR47_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_47
+#define    IRQ_SW_LISR48_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_48
+#define    IRQ_SW_LISR49_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_49
+#define    IRQ_SW_LISR50_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_50
+#define    IRQ_SW_LISR51_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_51
+#define    IRQ_SW_LISR52_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_52
+#define    IRQ_SW_LISR53_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_53
+#define    IRQ_SW_LISR54_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_54
+#define    IRQ_SW_LISR55_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_55
+#define    IRQ_SW_LISR56_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_56
+#define    IRQ_SW_LISR57_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_57
+#define    IRQ_SW_LISR58_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_58
+#define    IRQ_SW_LISR59_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_59
+#define    IRQ_SW_LISR60_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_60
+#define    IRQ_SW_LISR61_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_61
+#define    IRQ_SW_LISR62_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_62
+#define    IRQ_SW_LISR63_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_63
+#define    IRQ_SW_LISR64_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_64
+#define    IRQ_DUMMY_PRIORITY_CODE_8                 MD_IRQID_DUMMY_PRIORITY_IRQ8
+#define    IRQ_DUMMY_PRIORITY_CODE_9                 MD_IRQID_DUMMY_PRIORITY_IRQ9
+#define    IRQ_DUMMY_PRIORITY_CODE_10                MD_IRQID_DUMMY_PRIORITY_IRQ10
+#define    IRQ_DUMMY_PRIORITY_CODE_11                MD_IRQID_DUMMY_PRIORITY_IRQ11
+#define    IRQ_DUMMY_PRIORITY_CODE_12                MD_IRQID_DUMMY_PRIORITY_IRQ12
+#define    IRQ_DUMMY_PRIORITY_CODE_13                MD_IRQID_DUMMY_PRIORITY_IRQ13
+#define    IRQ_DUMMY_PRIORITY_CODE_14                MD_IRQID_DUMMY_PRIORITY_IRQ14
+#define    IRQ_DUMMY_PRIORITY_CODE_15                MD_IRQID_DUMMY_PRIORITY_IRQ15
+#define    IRQ_DUMMY_PRIORITY_CODE_16                MD_IRQID_DUMMY_PRIORITY_IRQ16
+#define    IRQ_DUMMY_PRIORITY_CODE_17                MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define    IRQ_DUMMY_PRIORITY_CODE_18                MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define    IRQ_DUMMY_PRIORITY_CODE_19                MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define    IRQ_DUMMY_PRIORITY_CODE_20                MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define    IRQ_DUMMY_PRIORITY_CODE_21                MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define    IRQ_DUMMY_PRIORITY_CODE_22                MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define    IRQ_DUMMY_PRIORITY_CODE_23                MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define    IRQ_DUMMY_PRIORITY_CODE_24                MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define    IRQ_DUMMY_PRIORITY_CODE_25                MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define    IRQ_DUMMY_PRIORITY_CODE_26                MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define    IRQ_DUMMY_PRIORITY_CODE_27                MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define    IRQ_DUMMY_PRIORITY_CODE_28                MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define    IRQ_DUMMY_PRIORITY_CODE_29                MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define    IRQ_DUMMY_PRIORITY_CODE_30                MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define    IRQ_SW_MODIS_MASE_HMU_CODE                IRQ_DUMMY_PRIORITY_CODE_25
+#define    IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE         IRQ_DUMMY_PRIORITY_CODE_26
+#define    IRQ_SW_MODIS_MASE_NR_TXLISR_CODE          IRQ_DUMMY_PRIORITY_CODE_27
+#define    IRQ_L1_PAE_SW_LISR0                       IRQ_DUMMY_PRIORITY_CODE_28
+#define    IRQ_L1_PAE_SW_LISR1                       IRQ_DUMMY_PRIORITY_CODE_29
+#define    IRQ_L1_PAE_SW_LISR2                       IRQ_DUMMY_PRIORITY_CODE_30
+#endif 
+
+
+/* IRQ Affinity Group Definition */
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+    /* Group0(0) */                                                                             0xFFE, \
+    /* Group1(1) */                                                                             0xFFD, \
+    /* Group2(2) */                                                                             0xFFB, \
+    /* Group3(3) */                                                                             0xFF7, \
+    /* Group4(4) */                                                                             0xFEF, \
+    /* Group5(5) */                                                                             0xFDF, \
+    /* Group6(6) */                                                                             0xFBF, \
+    /* Group7(7) */                                                                             0xF7F, \
+    /* Group8(8) */                                                                             0xEFF, \
+    /* Group9(9) */                                                                             0xDFF, \
+    /* Group10(10) */                                                                           0xBFF, \
+    /* Group11(11) */                                                                           0x7FF, \
+    /* Group12(1,4) */                                                                          0xFED, \
+    /* Group13(0,1,2) */                                                                        0xFF8, \
+    /* Group14(3,6,9) */                                                                        0xDB7, \
+    /* Group15(0,3,6,9) */                                                                      0xDB6, \
+    /* Group16(3,4,6,7,9,10) */                                                                 0x927, \
+    /* Group17(0,1,2,3,4,6,7,9,10) */                                                           0x920, \
+    /* Group18(3,4,5,6,7,8,9,10,11) */                                                          0x007, \
+    /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */                                                    0x000, \
+    /* Group20(3,4,6,7,9,10)        -> Reserved for NR runtime change affinity */               0x927, \
+    /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */               0x007, \
+    /* Group22(2)                   -> Reserved for LTE runtime change affinity */              0xFFB, \
+    /* Group23(0,2,3,4,6,7,9,10)    -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */  0x922, \
+    /* Group24(3,6,7,9,10)          -> Temp solution for IRQ0xEE to not preempt NR RX IRQs */   0x937, \
+    /* Group25(0,3,5,6,7,8,9,11)    -> Workaround for Serdes HW bug */                          0x416, \
+    /* Group26(0,2,3,6,7,9,10)      -> Workaround for IRQ0x80 pending hard affinity HRT IRQs */ 0x932, \
+    /* Group27 */                                                                               0xFFF, \
+    /* Group28 */                                                                               0xFFF, \
+    /* Group29 */                                                                               0xFFF, \
+    /* Group30 */                                                                               0xFFF, \
+    /* Group31 */                                                                               0xFFF,
+#endif
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions - 
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0         0   //(0)
+#define IRQ_AFFINITY_GROUP_VPE1         1   //(1)
+#define IRQ_AFFINITY_GROUP_VPE2         2   //(2)
+#define IRQ_AFFINITY_GROUP_VPE3         3   //(3)
+#define IRQ_AFFINITY_GROUP_VPE4         4   //(4)
+#define IRQ_AFFINITY_GROUP_VPE5         5   //(5)
+#define IRQ_AFFINITY_GROUP_VPE6         6   //(6)
+#define IRQ_AFFINITY_GROUP_VPE7         7   //(7)
+#define IRQ_AFFINITY_GROUP_VPE8	        8   //(8)
+#define IRQ_AFFINITY_GROUP_VPE9         9   //(9)
+#define IRQ_AFFINITY_GROUP_VPE10        10  //(10)
+#define IRQ_AFFINITY_GROUP_VPE11        11  //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4     12  //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0    13  //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR    14  //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP   15  //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR       16  //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP      17  //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR      18  //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE      19  //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+#define MAX_NUM_TASKS          256
+#define MAX_HISR_PRIORITY      2
+
+typedef enum
+{
+    VPE_STATUS_LISR_HIGHEST      = 0,
+    VPE_STATUS_LISR_LOWEST       = 342,
+    VPE_STATUS_HISR_TASK_HIGHEST = 512,
+    VPE_STATUS_HISR_TASK_LOWEST  = VPE_STATUS_HISR_TASK_HIGHEST + MAX_NUM_TASKS + MAX_HISR_PRIORITY, 
+    VPE_STATUS_END               = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_MT6853_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6853_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6853_SW_Handle.h
new file mode 100644
index 0000000..522593f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6853_SW_Handle.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6853_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   MT6853
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE0  = Karthigeyan Reddy
+      SW_TRIGGER_CODE1  = Karthigeyan Reddy
+      SW_TRIGGER_CODE2  = Karthigeyan Reddy
+      SW_TRIGGER_CODE3  = Karthigeyan Reddy
+      SW_TRIGGER_CODE4  = Karthigeyan Reddy
+      SW_TRIGGER_CODE5  = Karthigeyan Reddy
+      SW_TRIGGER_CODE6  = Zengling Jin
+      SW_TRIGGER_CODE7  = Zengling Jin
+      SW_TRIGGER_CODE8  = Zengling Jin
+      SW_TRIGGER_CODE9  = Cruze Yu
+      SW_TRIGGER_CODE10 = Cruze Yu
+      SW_TRIGGER_CODE11 = Cruze Yu
+      SW_TRIGGER_CODE12 = Cruze Yu
+      SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+      SW_TRIGGER_CODE14 = HW Jheng
+      SW_TRIGGER_CODE15 = Frank Hu
+      SW_TRIGGER_CODE16 = KH Hsiao
+      SW_TRIGGER_CODE17 = Deepti Varadarajan
+      SW_TRIGGER_CODE18 = Owen Ho
+      SW_TRIGGER_CODE19 = Owen Ho
+      SW_TRIGGER_CODE20 = Owen Ho
+      SW_TRIGGER_CODE21 = Owen Ho
+      SW_TRIGGER_CODE22 = Jun-Ying Huang
+      SW_TRIGGER_CODE23 = Jun-Ying Huang
+      SW_TRIGGER_CODE24 = Jun-Ying Huang
+      SW_TRIGGER_CODE25 = Jun-Ying Huang
+      SW_TRIGGER_CODE26 = Wade Huang
+      SW_TRIGGER_CODE27 = Tee-Yuen Chun
+      SW_TRIGGER_CODE28 = YY Hsieh 
+      SW_TRIGGER_CODE29 = Hamilton Liang
+      SW_TRIGGER_CODE30 = HW Jheng
+      SW_TRIGGER_CODE31 = Weimin Zeng
+      SW_TRIGGER_CODE32 = Weimin Zeng
+      SW_TRIGGER_CODE33 = Jocobrian Chang
+      SW_TRIGGER_CODE34 = JiaHong Hsu
+      SW_TRIGGER_CODE35 = Cheng-Long Wu
+      SW_TRIGGER_CODE36 = Cheng-Long Wu
+      SW_TRIGGER_CODE37 = Jocobrian Chang
+      SW_TRIGGER_CODE38 = Jocobrian Chang
+      SW_TRIGGER_CODE39 = Jocobrian Chang
+      SW_TRIGGER_CODE40 = Shu-Wei Ho
+      SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+      SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+  */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6873.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6873.h
new file mode 100644
index 0000000..ba872eb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6873.h
@@ -0,0 +1,564 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6873.h
+ *
+ * Project:
+ * --------
+ *   MT6873
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6873_H__
+#define __INTRCTRL_MT6873_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+
+#define NUM_IRQ_SOURCES          (368)
+
+/* CIRQ Interrupt Sources */
+#define    IRQ_USIM0_CODE                            MD_IRQID_USIM0
+#define    IRQ_USIM1_CODE                            MD_IRQID_USIM1
+#define    IRQ_TDMA_CTIRQ1_CODE                      MD_IRQID_TDMA_CTIRQ1
+#define    IRQ_TDMA_CTIRQ2_CODE                      MD_IRQID_TDMA_CTIRQ2
+#define    IRQ_TDMA_CTIRQ3_CODE                      MD_IRQID_TDMA_CTIRQ3
+#define    IRQ_TDMA_WAKEUP_IRQ_CODE                  MD_IRQID_TDMA_WAKEUP_IRQ
+#define    IRQ_OST_CODE                              MD_IRQID_OST
+#define    IRQ_MDRTT_CODE                            MD_IRQID_MDRTT
+#define    IRQ_MDEVDO_CODE                           MD_IRQID_MDEVDO
+#define    IRQ_ULSP_LOG_MCU_RT_INT_CODE              MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define    IRQ_ULSP_LOG_MCU_OD_INT_CODE              MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define    IRQ_ULSP_LOG_DSP4G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define    IRQ_ULSP_LOG_DSP4G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define    IRQ_ULSP_LOG_DSP5G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define    IRQ_ULSP_LOG_DSP5G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define    IRQ_SHARE_D12MINT1_CODE                   MD_IRQID_SHARE_D12MINT1
+#define    IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE        MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define    IRQ_AIRQ_SERDES_CODE                      MD_IRQID_AIRQ_SERDES
+#define    IRQ_AIRQ_COS_CODE                         MD_IRQID_AIRQ_COS
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define    IRQ_PPPHA_ENC0_INT_CODE                   MD_IRQID_PPPHA_ENC0_INT
+#define    IRQ_PPPHA_ENC1_INT_CODE                   MD_IRQID_PPPHA_ENC1_INT
+#define    IRQ_PPPHA_DEC0_INT_CODE                   MD_IRQID_PPPHA_DEC0_INT
+#define    IRQ_PPPHA_DEC1_INT_CODE                   MD_IRQID_PPPHA_DEC1_INT
+#define    IRQ_CS_NR_IRQ_CODE                        MD_IRQID_CS_NR_IRQ
+#define    IRQ_CS_NR_ERR_IRQ_CODE                    MD_IRQID_CS_NR_ERR_IRQ
+#define    IRQ_SDF_OVERFLOW_IRQ_CODE                 MD_IRQID_SDF_OVERFLOW_IRQ
+#define    IRQ_MCUMMU_INT_CODE                       MD_IRQID_MCUMMU_INT
+#define    IRQ_BIGRAM_0_IRQ_0_CODE                   MD_IRQID_BIGRAM_0_IRQ_0
+#define    IRQ_COS_PREP_INT_CODE                     MD_IRQID_COS_PREP_INT
+#define    IRQ_TRACE_INT_CODE                        MD_IRQID_TRACE_INT
+#define    IRQ_NR_TIMER_IRQ0_CODE                    MD_IRQID_NR_TIMER_IRQ0
+#define    IRQ_NR_TIMER_IRQ1_CODE                    MD_IRQID_NR_TIMER_IRQ1
+#define    IRQ_NR_TIMER_IRQ2_CODE                    MD_IRQID_NR_TIMER_IRQ2
+#define    IRQ_NR_TIMER_IRQ3_CODE                    MD_IRQID_NR_TIMER_IRQ3
+#define    IRQ_NR_TIMER_IRQ4_CODE                    MD_IRQID_NR_TIMER_IRQ4
+#define    IRQ_NR_TIMER_IRQ5_CODE                    MD_IRQID_NR_TIMER_IRQ5
+#define    IRQ_NR_TIMER_IRQ6_CODE                    MD_IRQID_NR_TIMER_IRQ6
+#define    IRQ_NR_TIMER_IRQ7_CODE                    MD_IRQID_NR_TIMER_IRQ7
+#define    IRQ_NR_TIMER_IRQ8_CODE                    MD_IRQID_NR_TIMER_IRQ8
+#define    IRQ_NR_TIMER_IRQ9_CODE                    MD_IRQID_NR_TIMER_IRQ9
+#define    IRQ_NR_TIMER_IRQ10_CODE                   MD_IRQID_NR_TIMER_IRQ10
+#define    IRQ_NR_TIMER_IRQ11_CODE                   MD_IRQID_NR_TIMER_IRQ11
+#define    IRQ_NR_TIMER_IRQ12_CODE                   MD_IRQID_NR_TIMER_IRQ12
+#define    IRQ_NR_TIMER_IRQ13_CODE                   MD_IRQID_NR_TIMER_IRQ13
+#define    IRQ_NR_TIMER_IRQ14_CODE                   MD_IRQID_NR_TIMER_IRQ14
+#define    IRQ_NR_TIMER_IRQ15_CODE                   MD_IRQID_NR_TIMER_IRQ15
+#define    IRQ_NR_TIMER_IRQ16_CODE                   MD_IRQID_NR_TIMER_IRQ16
+#define    IRQ_NR_TIMER_IRQ17_CODE                   MD_IRQID_NR_TIMER_IRQ17
+#define    IRQ_NR_TIMER_IRQ18_CODE                   MD_IRQID_NR_TIMER_IRQ18
+#define    IRQ_NR_TIMER_IRQ19_CODE                   MD_IRQID_NR_TIMER_IRQ19
+#define    IRQ_NR_TIMER_IRQ20_CODE                   MD_IRQID_NR_TIMER_IRQ20
+#define    IRQ_NR_TIMER_IRQ21_CODE                   MD_IRQID_NR_TIMER_IRQ21
+#define    IRQ_NR_TIMER_IRQ22_CODE                   MD_IRQID_NR_TIMER_IRQ22
+#define    IRQ_NR_TIMER_IRQ23_CODE                   MD_IRQID_NR_TIMER_IRQ23
+#define    IRQ_NR_TIMER_IRQ24_CODE                   MD_IRQID_NR_TIMER_IRQ24
+#define    IRQ_NR_TIMER_IRQ25_CODE                   MD_IRQID_NR_TIMER_IRQ25
+#define    IRQ_NR_TIMER_IRQ26_CODE                   MD_IRQID_NR_TIMER_IRQ26
+#define    IRQ_NR_TIMER_IRQ27_CODE                   MD_IRQID_NR_TIMER_IRQ27
+#define    IRQ_NR_TIMER_IRQ28_CODE                   MD_IRQID_NR_TIMER_IRQ28
+#define    IRQ_NR_TIMER_IRQ29_CODE                   MD_IRQID_NR_TIMER_IRQ29
+#define    IRQ_NR_TIMER_IRQ30_CODE                   MD_IRQID_NR_TIMER_IRQ30
+#define    IRQ_NR_TIMER_IRQ31_CODE                   MD_IRQID_NR_TIMER_IRQ31
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define    IRQ_NR_TIMER_CNTDN_IRQ0_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define    IRQ_NR_TIMER_CNTDN_IRQ1_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define    IRQ_NR_TIMER_CNTDN_IRQ2_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define    IRQ_NR_TIMER_CNTDN_IRQ3_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define    IRQ_NR_EVENTGEN_SPU_CODE                  MD_IRQID_NR_EVENTGEN_SPU
+#define    IRQ_SI_CM_ERR_CODE                        MD_IRQID_SI_CM_ERR
+#define    IRQ_SI_CM_PCINT_CODE                      MD_IRQID_SI_CM_PCINT
+#define    IRQ_MDM2C_U3G_CODE                        MD_IRQID_MDM2C_U3G
+#define    IRQ_RAKE_CMIF_M2C_IRQ_0_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define    IRQ_RAKE_CMIF_M2C_IRQ_1_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define    IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define    IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define    IRQ_RAKE_CMIF_PD_DO_IRQ_CODE              MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define    IRQ_MDMCU_BUSMON_MATCH_STS_CODE           MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define    IRQ_MDINFRA_BUSMON_MATCH_STS_CODE         MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define    IRQ_ELMTOP_EMI_IRQ_CODE                   MD_IRQID_ELMTOP_EMI_IRQ
+#define    IRQ_ELM_DMA_IRQ_CODE                      MD_IRQID_ELM_DMA_IRQ
+#define    IRQ_BUSMPU_IRQ_CODE                       MD_IRQID_BUSMPU_IRQ
+#define    IRQ_ST1X_CPINT_CODE                       MD_IRQID_ST1X_CPINT
+#define    IRQ_ST1x_HALF_CPINT_CODE                  MD_IRQID_ST1x_HALF_CPINT
+#define    IRQ_ST1x_CFG_CPINT_CODE                   MD_IRQID_ST1x_CFG_CPINT
+#define    IRQ_ST1x_WAKEUP_IRQ_CODE                  MD_IRQID_ST1x_WAKEUP_IRQ
+#define    IRQ_STDO_CPINT_CODE                       MD_IRQID_STDO_CPINT
+#define    IRQ_STDO_HALF_CPINT_CODE                  MD_IRQID_STDO_HALF_CPINT
+#define    IRQ_STDO_CFG_CPINT_CODE                   MD_IRQID_STDO_CFG_CPINT
+#define    IRQ_STDO_WAKEUP_IRQ_CODE                  MD_IRQID_STDO_WAKEUP_IRQ
+#define    IRQ_UART_MD0_CODE                         MD_IRQID_UART_MD0
+#define    IRQ_UART_MD1_CODE                         MD_IRQID_UART_MD1
+#define    IRQ_EINT0_CODE                            MD_IRQID_EINT0
+#define    IRQ_EINT1_CODE                            MD_IRQID_EINT1
+#define    IRQ_EINT2_CODE                            MD_IRQID_EINT2
+#define    IRQ_EINT3_CODE                            MD_IRQID_EINT3
+#define    IRQ_EINT_SHARE_CODE                       MD_IRQID_EINT_SHARE
+#define    IRQ_GPTM1_CODE                            MD_IRQID_GPTM1
+#define    IRQ_GPTM2_CODE                            MD_IRQID_GPTM2
+#define    IRQ_GPTM3_CODE                            MD_IRQID_GPTM3
+#define    IRQ_GPTM4_CODE                            MD_IRQID_GPTM4
+#define    IRQ_GPTM5_CODE                            MD_IRQID_GPTM5
+#define    IRQ_GPTM6_CODE                            MD_IRQID_GPTM6
+#define    IRQ_GPTM7_CODE                            MD_IRQID_GPTM7
+#define    IRQ_GPTM8_CODE                            MD_IRQID_GPTM8
+#define    IRQ_GPTM9_CODE                            MD_IRQID_GPTM9
+#define    IRQ_GPTM10_CODE                           MD_IRQID_GPTM10
+#define    IRQ_GPTM11_CODE                           MD_IRQID_GPTM11
+#define    IRQ_IDC_PM_INT_CODE                       MD_IRQID_IDC_PM_INT
+#define    IRQ_IDC_UART_IRQ_CODE                     MD_IRQID_IDC_UART_IRQ
+#define    IRQ_MDGDMA_FDMA5_CODE                     MD_IRQID_MDGDMA_FDMA5
+#define    IRQ_MDGDMA_FDMA6_CODE                     MD_IRQID_MDGDMA_FDMA6
+#define    IRQ_TDMA_CTIRQ4_CODE                      MD_IRQID_TDMA_CTIRQ4
+#define    IRQ_PDMA_CODE                             MD_IRQID_PDMA
+#define    IRQ_MDINFRA_BUS_DECERROR_CODE             MD_IRQID_MDINFRA_BUS_DECERROR
+#define    IRQ_I2C_TOP_INT_CODE                      MD_IRQID_I2C_TOP_INT
+#define    IRQ_SOE_CODE                              MD_IRQID_SOE
+#define    IRQ_ABM_INT_CODE                          MD_IRQID_ABM_INT
+#define    IRQ_ABM_ERROR_INT_CODE                    MD_IRQID_ABM_ERROR_INT
+#define    IRQ_USIP0_CODE                            MD_IRQID_USIP0
+#define    IRQ_USIP1_CODE                            MD_IRQID_USIP1
+#define    IRQ_USIP2_CODE                            MD_IRQID_USIP2
+#define    IRQ_USIP3_CODE                            MD_IRQID_USIP3
+#define    IRQ_USIP4_CODE                            MD_IRQID_USIP4
+#define    IRQ_USIP5_CODE                            MD_IRQID_USIP5
+#define    IRQ_USIP6_CODE                            MD_IRQID_USIP6
+#define    IRQ_USIP7_CODE                            MD_IRQID_USIP7
+#define    IRQ_USIP8_CODE                            MD_IRQID_USIP8
+#define    IRQ_USIP9_CODE                            MD_IRQID_USIP9
+#define    IRQ_USIP10_CODE                           MD_IRQID_USIP10
+#define    IRQ_USIP11_CODE                           MD_IRQID_USIP11
+#define    IRQ_USIP12_CODE                           MD_IRQID_USIP12
+#define    IRQ_USIP13_CODE                           MD_IRQID_USIP13
+#define    IRQ_TX_NR_CC0_IRQ_CODE                    MD_IRQID_TX_NR_CC0_IRQ
+#define    IRQ_TX_NR_CC1_IRQ_CODE                    MD_IRQID_TX_NR_CC1_IRQ
+#define    IRQ_TX_NR_ERR_CC_IRQ_CODE                 MD_IRQID_TX_NR_ERR_CC_IRQ
+#define    IRQ_MDMCU_SPU_IRQ_CODE                    MD_IRQID_MDMCU_SPU_IRQ
+#define    IRQ_DEM_TRIG_PS_INT_LE_CODE               MD_IRQID_DEM_TRIG_PS_INT_LE
+#define    IRQ_ECT_CODE                              MD_IRQID_ECT
+#define    IRQ_MDMCU_BUS_DECERR_IRQ_CODE             MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define    IRQ_MDMCU_OSTD_THROTTLE_CODE              MD_IRQID_MDMCU_OSTD_THROTTLE
+#define    IRQ_SHAOLIN_OSTD_THROTTLE_CODE            MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define    IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE         MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define    IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_AP2MD_CONN_WF_CCIF_0_CODE             MD_IRQID_AP2MD_CONN_WF_CCIF_0
+#define    IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_AP2MD_CONN_WF_CCIF_1_CODE             MD_IRQID_AP2MD_CONN_WF_CCIF_1
+#define    IRQ_MDWDT_CODE                            MD_IRQID_MDWDT
+#define    IRQ_MDGDMA_FDMA0_2_CODE                   MD_IRQID_MDGDMA_FDMA0_2
+#define    IRQ_MDGDMA_FDMA1_CODE                     MD_IRQID_MDGDMA_FDMA1
+#define    IRQ_MDGDMA_FDMA3_CODE                     MD_IRQID_MDGDMA_FDMA3
+#define    IRQ_MDGDMA_FDMA4_CODE                     MD_IRQID_MDGDMA_FDMA4
+#define    IRQ_MDGDMA_HDMA0_1_CODE                   MD_IRQID_MDGDMA_HDMA0_1
+#define    IRQ_MDGDMA_HDMA2_3_CODE                   MD_IRQID_MDGDMA_HDMA2_3
+#define    IRQ_AP2MD_CCIF0_0_CODE                    MD_IRQID_AP2MD_CCIF0_0
+#define    IRQ_AP2MD_CCIF0_1_CODE                    MD_IRQID_AP2MD_CCIF0_1
+#define    IRQ_AP2MD_CCIF1_0_CODE                    MD_IRQID_AP2MD_CCIF1_0
+#define    IRQ_AP2MD_CCIF1_1_CODE                    MD_IRQID_AP2MD_CCIF1_1
+#define    IRQ_IEBIT_CHECK_IRQ0_CODE                 MD_IRQID_IEBIT_CHECK_IRQ0
+#define    IRQ_IEBIT_CHECK_IRQ1_CODE                 MD_IRQID_IEBIT_CHECK_IRQ1
+#define    IRQ_IEBIT_CHECK_IRQ2_CODE                 MD_IRQID_IEBIT_CHECK_IRQ2
+#define    IRQ_IEBIT_CHECK_IRQ3_CODE                 MD_IRQID_IEBIT_CHECK_IRQ3
+#define    IRQ_IEBIT_CHECK_IRQ4_CODE                 MD_IRQID_IEBIT_CHECK_IRQ4
+#define    IRQ_IEBIT_CHECK_IRQ5_CODE                 MD_IRQID_IEBIT_CHECK_IRQ5
+#define    IRQ_IEBIT_CHECK_IRQ6_CODE                 MD_IRQID_IEBIT_CHECK_IRQ6
+#define    IRQ_IEBIT_CHECK_IRQ7_CODE                 MD_IRQID_IEBIT_CHECK_IRQ7
+#define    IRQ_IEBIT_CHECK_IRQ8_CODE                 MD_IRQID_IEBIT_CHECK_IRQ8
+#define    IRQ_IEBIT_CHECK_IRQ9_CODE                 MD_IRQID_IEBIT_CHECK_IRQ9
+#define    IRQ_IEBIT_CHECK_IRQ10_CODE                MD_IRQID_IEBIT_CHECK_IRQ10
+#define    IRQ_IEBIT_CHECK_IRQ11_CODE                MD_IRQID_IEBIT_CHECK_IRQ11
+#define    IRQ_NRL2_HRT_CODE                         MD_IRQID_NRL2_HRT
+#define    IRQ_NRL2_NOTIF_CODE                       MD_IRQID_NRL2_NOTIF
+#define    IRQ_NRL2_EXCEP_CODE                       MD_IRQID_NRL2_EXCEP
+#define    IRQ_NRL2_DPMAIF_MD_CODE                   MD_IRQID_NRL2_DPMAIF_MD
+#define    IRQ_RXDFE_IRQ0_CODE                       MD_IRQID_RXDFE_IRQ0
+#define    IRQ_IDC_UART_TX_FORCE_ON_CODE             MD_IRQID_IDC_UART_TX_FORCE_ON
+#define    IRQ_RXDFE_IRQ2_CODE                       MD_IRQID_RXDFE_IRQ2
+#define    IRQ_RXDFE_IRQ3_CODE                       MD_IRQID_RXDFE_IRQ3
+#define    IRQ_AP2MD_CONN_BGF_CCIF_0_CODE            MD_IRQID_AP2MD_CONN_BGF_CCIF_0
+#define    IRQ_MD_RXDFE_BB_DUMP_CODE                 MD_IRQID_MD_RXDFE_BB_DUMP
+#define    IRQ_AP2MD_CONN_BGF_CCIF_1_CODE            MD_IRQID_AP2MD_CONN_BGF_CCIF_1
+#define    IRQ_TXCRP_CODE                            MD_IRQID_TXCRP
+#define    IRQ_CM_NR_IRQ_CODE                        MD_IRQID_CM_NR_IRQ
+#define    IRQ_CM_NR_ERR_IRQ_CODE                    MD_IRQID_CM_NR_ERR_IRQ
+#define    IRQ_L1_LTE_SLEEP_IRQ_CODE                 MD_IRQID_L1_LTE_SLEEP_IRQ
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define    IRQ_D_GDMA_0_IRQ_CODE                     MD_IRQID_D_GDMA_0_IRQ
+#define    IRQ_D_GDMA_1_IRQ_CODE                     MD_IRQID_D_GDMA_1_IRQ
+#define    IRQ_D_GDMA_2_IRQ_CODE                     MD_IRQID_D_GDMA_2_IRQ
+#define    IRQ_D_GDMA_3_IRQ_CODE                     MD_IRQID_D_GDMA_3_IRQ
+#define    IRQ_D_GDMA_4_IRQ_CODE                     MD_IRQID_D_GDMA_4_IRQ
+#define    IRQ_D_GDMA_5_IRQ_CODE                     MD_IRQID_D_GDMA_5_IRQ
+#define    IRQ_PLL_GEARHP_RDY_CODE                   MD_IRQID_PLL_GEARHP_RDY
+#define    IRQ_REQ_ABNORM_IRQ_CODE                   MD_IRQID_REQ_ABNORM_IRQ
+#define    IRQ_NRL2_DPMAIF_MDMCU_CODE                MD_IRQID_NRL2_DPMAIF_MDMCU
+#define    IRQ_AP2MD_APWDT_IRQ_CODE                  MD_IRQID_AP2MD_APWDT_IRQ
+#define    IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE          MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ
+#define    IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE           MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ
+#define    IRQ_DUMMY_PRIORITY_CODE_5                 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define    IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE             MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define    IRQ_L1M_PHY_LTMR_IRQ_0_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define    IRQ_L1M_PHY_LTMR_IRQ_1_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define    IRQ_L1M_PHY_LTMR_IRQ_2_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define    IRQ_L1M_PHY_LTMR_IRQ_3_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define    IRQ_L1M_PHY_LTMR_IRQ_4_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define    IRQ_L1M_PHY_LTMR_IRQ_5_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define    IRQ_L1M_PHY_LTMR_IRQ_6_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define    IRQ_L1M_PHY_LTMR_IRQ_7_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define    IRQ_DUMMY_PRIORITY_CODE_6                 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define    IRQ_L1_LTE_WAKEUP_IRQ_CODE                MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define    IRQ_TDD_WAKEUP_IRQ_CODE                   MD_IRQID_TDD_WAKEUP_IRQ
+#define    IRQ_TDD_TIMER_L1D_1_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define    IRQ_TDD_TIMER_L1D_2_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define    IRQ_RTR_SLT_0_IRQ_CODE                    MD_IRQID_RTR_SLT_0_IRQ
+#define    IRQ_RTR_SLT_1_IRQ_CODE                    MD_IRQID_RTR_SLT_1_IRQ
+#define    IRQ_FDD_SLP_IRQ_CODE                      MD_IRQID_FDD_SLP_IRQ
+#define    IRQ_IRDBG_MCU_INT_CODE                    MD_IRQID_IRDBG_MCU_INT
+#define    IRQ_MD_DVFS_CTRL_IRQ_0_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define    IRQ_MD_DVFS_CTRL_IRQ_1_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define    IRQ_NR_SLP_WAKEUP_CODE                    MD_IRQID_NR_SLP_WAKEUP
+#define    IRQ_NR_SLP_SLEEP_CODE                     MD_IRQID_NR_SLP_SLEEP
+#define    IRQ_NR_TIMER_ERR_CODE                     MD_IRQID_NR_TIMER_ERR
+#define    IRQ_TXBSRP_CODE                           MD_IRQID_TXBSRP
+#define    IRQ_TXDFE_D_CODE                          MD_IRQID_TXDFE_D
+#define    IRQ_NR_EVENTGEN_ERR_CODE                  MD_IRQID_NR_EVENTGEN_ERR
+#define    IRQ_AIRQ_PAD_CODE                         MD_IRQID_AIRQ_PAD
+#define    IRQ_CSSYS_FDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_FDD_CS_IRQ
+#define    IRQ_CSSYS_TDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_TDD_CS_IRQ
+#define    IRQ_CSSYS_LTE_CS_IRQ_CODE                 MD_IRQID_CSSYS_LTE_CS_IRQ
+#define    IRQ_CSSYS_1X_CS_IRQ_CODE                  MD_IRQID_CSSYS_1X_CS_IRQ
+#define    IRQ_CSSYS_DO_CS_IRQ_CODE                  MD_IRQID_CSSYS_DO_CS_IRQ
+#define    IRQ_PCIE_INTERRUPT_OUT_CODE               MD_IRQID_PCIE_INTERRUPT_OUT
+#define    IRQ_UCNT_SCH_IRQ_CODE                     MD_IRQID_UCNT_SCH_IRQ
+#define    IRQ_UCNT_ERR_IRQ_CODE                     MD_IRQID_UCNT_ERR_IRQ
+#define    IRQ_UCNT_ADJ_IRQ_CODE                     MD_IRQID_UCNT_ADJ_IRQ
+#define    IRQ_SL_WAITSLEEP_CODE                     MD_IRQID_SL_WAITSLEEP
+#define    IRQ_PTP_THERM_INT_INT_CODE                MD_IRQID_PTP_THERM_INT_INT
+#define    IRQ_PTP_FSM_INT_CODE                      MD_IRQID_PTP_FSM_INT
+#define    IRQ_AP2MD_DAPC_CODE                       MD_IRQID_AP2MD_DAPC
+#define    IRQ_AP2MD_CCIF2_CODE                      MD_IRQID_AP2MD_CCIF2
+#define    IRQ_AP2MD_UFS_CODE                        MD_IRQID_AP2MD_UFS
+#define    IRQ_SSUSB_INTERRUPT_OUT_CODE              MD_IRQID_SSUSB_INTERRUPT_OUT
+#define    IRQ_AP2MD_MSDC0_CODE                      MD_IRQID_AP2MD_MSDC0
+#define    IRQ_MIPI_IRQ_CODE                         MD_IRQID_MIPI_IRQ
+#define    IRQ_CONN_BT_ISOCH_CODE                    MD_IRQID_CONN_BT_ISOCH
+#define    IRQ_RMPU_CTIREIGIN_CODE                   MD_IRQID_RMPU_CTIREIGIN
+#define    IRQ_FREQM_IRQ_CODE                        MD_IRQID_FREQM_IRQ
+#define    IRQ_BT_CVSD_CODE                          MD_IRQID_BT_CVSD
+#define    IRQ_SW_LISR0_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_0
+#define    IRQ_SW_LISR1_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_1
+#define    IRQ_SW_LISR2_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_2
+#define    IRQ_SW_LISR3_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_3
+#define    IRQ_SW_LISR4_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_4
+#define    IRQ_SW_LISR5_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_5
+#define    IRQ_SW_LISR6_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_6
+#define    IRQ_SW_LISR7_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_7
+#define    IRQ_SW_LISR8_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_8
+#define    IRQ_SW_LISR9_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_9
+#define    IRQ_SW_LISR10_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_10
+#define    IRQ_SW_LISR11_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_11
+#define    IRQ_SW_LISR12_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_12
+#define    IRQ_SW_LISR13_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_13
+#define    IRQ_SW_LISR14_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_14
+#define    IRQ_SW_LISR15_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_15
+#define    IRQ_SW_LISR16_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_16
+#define    IRQ_SW_LISR17_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_17
+#define    IRQ_SW_LISR18_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_18
+#define    IRQ_SW_LISR19_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_19
+#define    IRQ_SW_LISR20_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_20
+#define    IRQ_SW_LISR21_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_21
+#define    IRQ_SW_LISR22_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_22
+#define    IRQ_SW_LISR23_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_23
+#define    IRQ_SW_LISR24_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_24
+#define    IRQ_SW_LISR25_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_25
+#define    IRQ_SW_LISR26_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_26
+#define    IRQ_SW_LISR27_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_27
+#define    IRQ_SW_LISR28_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_28
+#define    IRQ_SW_LISR29_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_29
+#define    IRQ_SW_LISR30_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_30
+#define    IRQ_SW_LISR31_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_31
+#define    IRQ_SW_LISR32_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_32
+#define    IRQ_SW_LISR33_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_33
+#define    IRQ_SW_LISR34_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_34
+#define    IRQ_SW_LISR35_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_35
+#define    IRQ_SW_LISR36_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_36
+#define    IRQ_SW_LISR37_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_37
+#define    IRQ_SW_LISR38_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_38
+#define    IRQ_SW_LISR39_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_39
+#define    IRQ_SW_LISR40_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_40
+#define    IRQ_SW_LISR41_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_41
+#define    IRQ_SW_LISR42_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_42
+#define    IRQ_SW_LISR43_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_43
+#define    IRQ_SW_LISR44_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_44
+#define    IRQ_SW_LISR45_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_45
+#define    IRQ_SW_LISR46_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_46
+#define    IRQ_SW_LISR47_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_47
+#define    IRQ_SW_LISR48_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_48
+#define    IRQ_SW_LISR49_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_49
+#define    IRQ_SW_LISR50_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_50
+#define    IRQ_SW_LISR51_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_51
+#define    IRQ_SW_LISR52_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_52
+#define    IRQ_SW_LISR53_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_53
+#define    IRQ_SW_LISR54_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_54
+#define    IRQ_SW_LISR55_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_55
+#define    IRQ_SW_LISR56_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_56
+#define    IRQ_SW_LISR57_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_57
+#define    IRQ_SW_LISR58_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_58
+#define    IRQ_SW_LISR59_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_59
+#define    IRQ_SW_LISR60_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_60
+#define    IRQ_SW_LISR61_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_61
+#define    IRQ_SW_LISR62_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_62
+#define    IRQ_SW_LISR63_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_63
+#define    IRQ_SW_LISR64_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_64
+#define    IRQ_DUMMY_PRIORITY_CODE_8                 MD_IRQID_DUMMY_PRIORITY_IRQ8
+#define    IRQ_DUMMY_PRIORITY_CODE_9                 MD_IRQID_DUMMY_PRIORITY_IRQ9
+#define    IRQ_DUMMY_PRIORITY_CODE_10                MD_IRQID_DUMMY_PRIORITY_IRQ10
+#define    IRQ_DUMMY_PRIORITY_CODE_11                MD_IRQID_DUMMY_PRIORITY_IRQ11
+#define    IRQ_DUMMY_PRIORITY_CODE_12                MD_IRQID_DUMMY_PRIORITY_IRQ12
+#define    IRQ_DUMMY_PRIORITY_CODE_13                MD_IRQID_DUMMY_PRIORITY_IRQ13
+#define    IRQ_DUMMY_PRIORITY_CODE_14                MD_IRQID_DUMMY_PRIORITY_IRQ14
+#define    IRQ_DUMMY_PRIORITY_CODE_15                MD_IRQID_DUMMY_PRIORITY_IRQ15
+#define    IRQ_DUMMY_PRIORITY_CODE_16                MD_IRQID_DUMMY_PRIORITY_IRQ16
+#define    IRQ_DUMMY_PRIORITY_CODE_17                MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define    IRQ_DUMMY_PRIORITY_CODE_18                MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define    IRQ_DUMMY_PRIORITY_CODE_19                MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define    IRQ_DUMMY_PRIORITY_CODE_20                MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define    IRQ_DUMMY_PRIORITY_CODE_21                MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define    IRQ_DUMMY_PRIORITY_CODE_22                MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define    IRQ_DUMMY_PRIORITY_CODE_23                MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define    IRQ_DUMMY_PRIORITY_CODE_24                MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define    IRQ_DUMMY_PRIORITY_CODE_25                MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define    IRQ_DUMMY_PRIORITY_CODE_26                MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define    IRQ_DUMMY_PRIORITY_CODE_27                MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define    IRQ_DUMMY_PRIORITY_CODE_28                MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define    IRQ_DUMMY_PRIORITY_CODE_29                MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define    IRQ_DUMMY_PRIORITY_CODE_30                MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define    IRQ_SW_MODIS_MASE_HMU_CODE                IRQ_DUMMY_PRIORITY_CODE_25
+#define    IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE         IRQ_DUMMY_PRIORITY_CODE_26
+#define    IRQ_SW_MODIS_MASE_NR_TXLISR_CODE          IRQ_DUMMY_PRIORITY_CODE_27
+#define    IRQ_L1_PAE_SW_LISR0                       IRQ_DUMMY_PRIORITY_CODE_28
+#define    IRQ_L1_PAE_SW_LISR1                       IRQ_DUMMY_PRIORITY_CODE_29
+#define    IRQ_L1_PAE_SW_LISR2                       IRQ_DUMMY_PRIORITY_CODE_30
+#endif 
+
+
+/* IRQ Affinity Group Definition */
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+    /* Group0(0) */                                                                             0xFFE, \
+    /* Group1(1) */                                                                             0xFFD, \
+    /* Group2(2) */                                                                             0xFFB, \
+    /* Group3(3) */                                                                             0xFF7, \
+    /* Group4(4) */                                                                             0xFEF, \
+    /* Group5(5) */                                                                             0xFDF, \
+    /* Group6(6) */                                                                             0xFBF, \
+    /* Group7(7) */                                                                             0xF7F, \
+    /* Group8(8) */                                                                             0xEFF, \
+    /* Group9(9) */                                                                             0xDFF, \
+    /* Group10(10) */                                                                           0xBFF, \
+    /* Group11(11) */                                                                           0x7FF, \
+    /* Group12(1,4) */                                                                          0xFED, \
+    /* Group13(0,1,2) */                                                                        0xFF8, \
+    /* Group14(3,6,9) */                                                                        0xDB7, \
+    /* Group15(0,3,6,9) */                                                                      0xDB6, \
+    /* Group16(3,4,6,7,9,10) */                                                                 0x927, \
+    /* Group17(0,1,2,3,4,6,7,9,10) */                                                           0x920, \
+    /* Group18(3,4,5,6,7,8,9,10,11) */                                                          0x007, \
+    /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */                                                    0x000, \
+    /* Group20(3,4,6,7,9,10)        -> Reserved for NR runtime change affinity */               0x927, \
+    /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */               0x007, \
+    /* Group22(2)                   -> Reserved for LTE runtime change affinity */              0xFFB, \
+    /* Group23(0,2,3,4,6,7,9,10)    -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */  0x922, \
+    /* Group24(3,6,7,9,10)          -> Temp solution for IRQ0xEE to not preempt NR RX IRQs */   0x937, \
+    /* Group25(0,3,5,6,7,8,9,11)    -> Workaround for Serdes HW bug */                          0x416, \
+    /* Group26(0,2,3,6,7,9,10)      -> Workaround for IRQ0x80 pending hard affinity HRT IRQs */ 0x932, \
+    /* Group27 */                                                                               0xFFF, \
+    /* Group28 */                                                                               0xFFF, \
+    /* Group29 */                                                                               0xFFF, \
+    /* Group30 */                                                                               0xFFF, \
+    /* Group31 */                                                                               0xFFF,
+#endif
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions - 
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0         0   //(0)
+#define IRQ_AFFINITY_GROUP_VPE1         1   //(1)
+#define IRQ_AFFINITY_GROUP_VPE2         2   //(2)
+#define IRQ_AFFINITY_GROUP_VPE3         3   //(3)
+#define IRQ_AFFINITY_GROUP_VPE4         4   //(4)
+#define IRQ_AFFINITY_GROUP_VPE5         5   //(5)
+#define IRQ_AFFINITY_GROUP_VPE6         6   //(6)
+#define IRQ_AFFINITY_GROUP_VPE7         7   //(7)
+#define IRQ_AFFINITY_GROUP_VPE8	        8   //(8)
+#define IRQ_AFFINITY_GROUP_VPE9         9   //(9)
+#define IRQ_AFFINITY_GROUP_VPE10        10  //(10)
+#define IRQ_AFFINITY_GROUP_VPE11        11  //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4     12  //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0    13  //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR    14  //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP   15  //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR       16  //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP      17  //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR      18  //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE      19  //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+#define MAX_NUM_TASKS          256
+#define MAX_HISR_PRIORITY      2
+
+typedef enum
+{
+    VPE_STATUS_LISR_HIGHEST      = 0,
+    VPE_STATUS_LISR_LOWEST       = 342,
+    VPE_STATUS_HISR_TASK_HIGHEST = 512,
+    VPE_STATUS_HISR_TASK_LOWEST  = VPE_STATUS_HISR_TASK_HIGHEST + MAX_NUM_TASKS + MAX_HISR_PRIORITY, 
+    VPE_STATUS_END               = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_MT6873_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6873_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6873_SW_Handle.h
new file mode 100644
index 0000000..0b3881c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6873_SW_Handle.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6873_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   MT6873
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE0  = Karthigeyan Reddy
+      SW_TRIGGER_CODE1  = Karthigeyan Reddy
+      SW_TRIGGER_CODE2  = Karthigeyan Reddy
+      SW_TRIGGER_CODE3  = Karthigeyan Reddy
+      SW_TRIGGER_CODE4  = Karthigeyan Reddy
+      SW_TRIGGER_CODE5  = Karthigeyan Reddy
+      SW_TRIGGER_CODE6  = Zengling Jin
+      SW_TRIGGER_CODE7  = Zengling Jin
+      SW_TRIGGER_CODE8  = Zengling Jin
+      SW_TRIGGER_CODE9  = Cruze Yu
+      SW_TRIGGER_CODE10 = Cruze Yu
+      SW_TRIGGER_CODE11 = Cruze Yu
+      SW_TRIGGER_CODE12 = Cruze Yu
+      SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+      SW_TRIGGER_CODE14 = HW Jheng
+      SW_TRIGGER_CODE15 = Frank Hu
+      SW_TRIGGER_CODE16 = KH Hsiao
+      SW_TRIGGER_CODE17 = Deepti Varadarajan
+      SW_TRIGGER_CODE18 = Owen Ho
+      SW_TRIGGER_CODE19 = Owen Ho
+      SW_TRIGGER_CODE20 = Owen Ho
+      SW_TRIGGER_CODE21 = Owen Ho
+      SW_TRIGGER_CODE22 = Jun-Ying Huang
+      SW_TRIGGER_CODE23 = Jun-Ying Huang
+      SW_TRIGGER_CODE24 = Jun-Ying Huang
+      SW_TRIGGER_CODE25 = Jun-Ying Huang
+      SW_TRIGGER_CODE26 = Wade Huang
+      SW_TRIGGER_CODE27 = Tee-Yuen Chun
+      SW_TRIGGER_CODE28 = YY Hsieh 
+      SW_TRIGGER_CODE29 = Hamilton Liang
+      SW_TRIGGER_CODE30 = HW Jheng
+      SW_TRIGGER_CODE31 = Weimin Zeng
+      SW_TRIGGER_CODE32 = Weimin Zeng
+      SW_TRIGGER_CODE33 = Jocobrian Chang
+      SW_TRIGGER_CODE34 = JiaHong Hsu
+      SW_TRIGGER_CODE35 = Cheng-Long Wu
+      SW_TRIGGER_CODE36 = Cheng-Long Wu
+      SW_TRIGGER_CODE37 = Jocobrian Chang
+      SW_TRIGGER_CODE38 = Jocobrian Chang
+      SW_TRIGGER_CODE39 = Jocobrian Chang
+      SW_TRIGGER_CODE40 = Shu-Wei Ho
+      SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+      SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+  */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6877.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6877.h
new file mode 100644
index 0000000..e0b2360
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6877.h
@@ -0,0 +1,564 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6877.h
+ *
+ * Project:
+ * --------
+ *   MT6833
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6877_H__
+#define __INTRCTRL_MT6877_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+
+#define NUM_IRQ_SOURCES          (368)
+
+/* CIRQ Interrupt Sources */
+#define    IRQ_USIM0_CODE                            MD_IRQID_USIM0
+#define    IRQ_USIM1_CODE                            MD_IRQID_USIM1
+#define    IRQ_TDMA_CTIRQ1_CODE                      MD_IRQID_TDMA_CTIRQ1
+#define    IRQ_TDMA_CTIRQ2_CODE                      MD_IRQID_TDMA_CTIRQ2
+#define    IRQ_TDMA_CTIRQ3_CODE                      MD_IRQID_TDMA_CTIRQ3
+#define    IRQ_TDMA_WAKEUP_IRQ_CODE                  MD_IRQID_TDMA_WAKEUP_IRQ
+#define    IRQ_OST_CODE                              MD_IRQID_OST
+#define    IRQ_MDRTT_CODE                            MD_IRQID_MDRTT
+#define    IRQ_MDEVDO_CODE                           MD_IRQID_MDEVDO
+#define    IRQ_ULSP_LOG_MCU_RT_INT_CODE              MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define    IRQ_ULSP_LOG_MCU_OD_INT_CODE              MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define    IRQ_ULSP_LOG_DSP4G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define    IRQ_ULSP_LOG_DSP4G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define    IRQ_ULSP_LOG_DSP5G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define    IRQ_ULSP_LOG_DSP5G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define    IRQ_SHARE_D12MINT1_CODE                   MD_IRQID_SHARE_D12MINT1
+#define    IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE        MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define    IRQ_AIRQ_SERDES_CODE                      MD_IRQID_AIRQ_SERDES
+#define    IRQ_AIRQ_COS_CODE                         MD_IRQID_AIRQ_COS
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define    IRQ_PPPHA_ENC0_INT_CODE                   MD_IRQID_PPPHA_ENC0_INT
+#define    IRQ_PPPHA_ENC1_INT_CODE                   MD_IRQID_PPPHA_ENC1_INT
+#define    IRQ_PPPHA_DEC0_INT_CODE                   MD_IRQID_PPPHA_DEC0_INT
+#define    IRQ_PPPHA_DEC1_INT_CODE                   MD_IRQID_PPPHA_DEC1_INT
+#define    IRQ_CS_NR_IRQ_CODE                        MD_IRQID_CS_NR_IRQ
+#define    IRQ_CS_NR_ERR_IRQ_CODE                    MD_IRQID_CS_NR_ERR_IRQ
+#define    IRQ_SDF_OVERFLOW_IRQ_CODE                 MD_IRQID_SDF_OVERFLOW_IRQ
+#define    IRQ_MCUMMU_INT_CODE                       MD_IRQID_MCUMMU_INT
+#define    IRQ_BIGRAM_0_IRQ_0_CODE                   MD_IRQID_BIGRAM_0_IRQ_0
+#define    IRQ_COS_PREP_INT_CODE                     MD_IRQID_COS_PREP_INT
+#define    IRQ_TRACE_INT_CODE                        MD_IRQID_TRACE_INT
+#define    IRQ_NR_TIMER_IRQ0_CODE                    MD_IRQID_NR_TIMER_IRQ0
+#define    IRQ_NR_TIMER_IRQ1_CODE                    MD_IRQID_NR_TIMER_IRQ1
+#define    IRQ_NR_TIMER_IRQ2_CODE                    MD_IRQID_NR_TIMER_IRQ2
+#define    IRQ_NR_TIMER_IRQ3_CODE                    MD_IRQID_NR_TIMER_IRQ3
+#define    IRQ_NR_TIMER_IRQ4_CODE                    MD_IRQID_NR_TIMER_IRQ4
+#define    IRQ_NR_TIMER_IRQ5_CODE                    MD_IRQID_NR_TIMER_IRQ5
+#define    IRQ_NR_TIMER_IRQ6_CODE                    MD_IRQID_NR_TIMER_IRQ6
+#define    IRQ_NR_TIMER_IRQ7_CODE                    MD_IRQID_NR_TIMER_IRQ7
+#define    IRQ_NR_TIMER_IRQ8_CODE                    MD_IRQID_NR_TIMER_IRQ8
+#define    IRQ_NR_TIMER_IRQ9_CODE                    MD_IRQID_NR_TIMER_IRQ9
+#define    IRQ_NR_TIMER_IRQ10_CODE                   MD_IRQID_NR_TIMER_IRQ10
+#define    IRQ_NR_TIMER_IRQ11_CODE                   MD_IRQID_NR_TIMER_IRQ11
+#define    IRQ_NR_TIMER_IRQ12_CODE                   MD_IRQID_NR_TIMER_IRQ12
+#define    IRQ_NR_TIMER_IRQ13_CODE                   MD_IRQID_NR_TIMER_IRQ13
+#define    IRQ_NR_TIMER_IRQ14_CODE                   MD_IRQID_NR_TIMER_IRQ14
+#define    IRQ_NR_TIMER_IRQ15_CODE                   MD_IRQID_NR_TIMER_IRQ15
+#define    IRQ_NR_TIMER_IRQ16_CODE                   MD_IRQID_NR_TIMER_IRQ16
+#define    IRQ_NR_TIMER_IRQ17_CODE                   MD_IRQID_NR_TIMER_IRQ17
+#define    IRQ_NR_TIMER_IRQ18_CODE                   MD_IRQID_NR_TIMER_IRQ18
+#define    IRQ_NR_TIMER_IRQ19_CODE                   MD_IRQID_NR_TIMER_IRQ19
+#define    IRQ_NR_TIMER_IRQ20_CODE                   MD_IRQID_NR_TIMER_IRQ20
+#define    IRQ_NR_TIMER_IRQ21_CODE                   MD_IRQID_NR_TIMER_IRQ21
+#define    IRQ_NR_TIMER_IRQ22_CODE                   MD_IRQID_NR_TIMER_IRQ22
+#define    IRQ_NR_TIMER_IRQ23_CODE                   MD_IRQID_NR_TIMER_IRQ23
+#define    IRQ_NR_TIMER_IRQ24_CODE                   MD_IRQID_NR_TIMER_IRQ24
+#define    IRQ_NR_TIMER_IRQ25_CODE                   MD_IRQID_NR_TIMER_IRQ25
+#define    IRQ_NR_TIMER_IRQ26_CODE                   MD_IRQID_NR_TIMER_IRQ26
+#define    IRQ_NR_TIMER_IRQ27_CODE                   MD_IRQID_NR_TIMER_IRQ27
+#define    IRQ_NR_TIMER_IRQ28_CODE                   MD_IRQID_NR_TIMER_IRQ28
+#define    IRQ_NR_TIMER_IRQ29_CODE                   MD_IRQID_NR_TIMER_IRQ29
+#define    IRQ_NR_TIMER_IRQ30_CODE                   MD_IRQID_NR_TIMER_IRQ30
+#define    IRQ_NR_TIMER_IRQ31_CODE                   MD_IRQID_NR_TIMER_IRQ31
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define    IRQ_NR_TIMER_CNTDN_IRQ0_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define    IRQ_NR_TIMER_CNTDN_IRQ1_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define    IRQ_NR_TIMER_CNTDN_IRQ2_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define    IRQ_NR_TIMER_CNTDN_IRQ3_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define    IRQ_NR_EVENTGEN_SPU_CODE                  MD_IRQID_NR_EVENTGEN_SPU
+#define    IRQ_SI_CM_ERR_CODE                        MD_IRQID_SI_CM_ERR
+#define    IRQ_SI_CM_PCINT_CODE                      MD_IRQID_SI_CM_PCINT
+#define    IRQ_MDM2C_U3G_CODE                        MD_IRQID_MDM2C_U3G
+#define    IRQ_RAKE_CMIF_M2C_IRQ_0_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define    IRQ_RAKE_CMIF_M2C_IRQ_1_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define    IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define    IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define    IRQ_RAKE_CMIF_PD_DO_IRQ_CODE              MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define    IRQ_MDMCU_BUSMON_MATCH_STS_CODE           MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define    IRQ_MDINFRA_BUSMON_MATCH_STS_CODE         MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define    IRQ_ELMTOP_EMI_IRQ_CODE                   MD_IRQID_ELMTOP_EMI_IRQ
+#define    IRQ_ELM_DMA_IRQ_CODE                      MD_IRQID_ELM_DMA_IRQ
+#define    IRQ_BUSMPU_IRQ_CODE                       MD_IRQID_BUSMPU_IRQ
+#define    IRQ_ST1X_CPINT_CODE                       MD_IRQID_ST1X_CPINT
+#define    IRQ_ST1x_HALF_CPINT_CODE                  MD_IRQID_ST1x_HALF_CPINT
+#define    IRQ_ST1x_CFG_CPINT_CODE                   MD_IRQID_ST1x_CFG_CPINT
+#define    IRQ_ST1x_WAKEUP_IRQ_CODE                  MD_IRQID_ST1x_WAKEUP_IRQ
+#define    IRQ_STDO_CPINT_CODE                       MD_IRQID_STDO_CPINT
+#define    IRQ_STDO_HALF_CPINT_CODE                  MD_IRQID_STDO_HALF_CPINT
+#define    IRQ_STDO_CFG_CPINT_CODE                   MD_IRQID_STDO_CFG_CPINT
+#define    IRQ_STDO_WAKEUP_IRQ_CODE                  MD_IRQID_STDO_WAKEUP_IRQ
+#define    IRQ_UART_MD0_CODE                         MD_IRQID_UART_MD0
+#define    IRQ_UART_MD1_CODE                         MD_IRQID_UART_MD1
+#define    IRQ_EINT0_CODE                            MD_IRQID_EINT0
+#define    IRQ_EINT1_CODE                            MD_IRQID_EINT1
+#define    IRQ_EINT2_CODE                            MD_IRQID_EINT2
+#define    IRQ_EINT3_CODE                            MD_IRQID_EINT3
+#define    IRQ_EINT_SHARE_CODE                       MD_IRQID_EINT_SHARE
+#define    IRQ_GPTM1_CODE                            MD_IRQID_GPTM1
+#define    IRQ_GPTM2_CODE                            MD_IRQID_GPTM2
+#define    IRQ_GPTM3_CODE                            MD_IRQID_GPTM3
+#define    IRQ_GPTM4_CODE                            MD_IRQID_GPTM4
+#define    IRQ_GPTM5_CODE                            MD_IRQID_GPTM5
+#define    IRQ_GPTM6_CODE                            MD_IRQID_GPTM6
+#define    IRQ_GPTM7_CODE                            MD_IRQID_GPTM7
+#define    IRQ_GPTM8_CODE                            MD_IRQID_GPTM8
+#define    IRQ_GPTM9_CODE                            MD_IRQID_GPTM9
+#define    IRQ_GPTM10_CODE                           MD_IRQID_GPTM10
+#define    IRQ_GPTM11_CODE                           MD_IRQID_GPTM11
+#define    IRQ_IDC_PM_INT_CODE                       MD_IRQID_IDC_PM_INT
+#define    IRQ_IDC_UART_IRQ_CODE                     MD_IRQID_IDC_UART_IRQ
+#define    IRQ_MDGDMA_FDMA5_CODE                     MD_IRQID_MDGDMA_FDMA5
+#define    IRQ_MDGDMA_FDMA6_CODE                     MD_IRQID_MDGDMA_FDMA6
+#define    IRQ_TDMA_CTIRQ4_CODE                      MD_IRQID_TDMA_CTIRQ4
+#define    IRQ_PDMA_CODE                             MD_IRQID_PDMA
+#define    IRQ_MDINFRA_BUS_DECERROR_CODE             MD_IRQID_MDINFRA_BUS_DECERROR
+#define    IRQ_I2C_TOP_INT_CODE                      MD_IRQID_I2C_TOP_INT
+#define    IRQ_SOE_CODE                              MD_IRQID_SOE
+#define    IRQ_ABM_INT_CODE                          MD_IRQID_ABM_INT
+#define    IRQ_ABM_ERROR_INT_CODE                    MD_IRQID_ABM_ERROR_INT
+#define    IRQ_USIP0_CODE                            MD_IRQID_USIP0
+#define    IRQ_USIP1_CODE                            MD_IRQID_USIP1
+#define    IRQ_USIP2_CODE                            MD_IRQID_USIP2
+#define    IRQ_USIP3_CODE                            MD_IRQID_USIP3
+#define    IRQ_USIP4_CODE                            MD_IRQID_USIP4
+#define    IRQ_USIP5_CODE                            MD_IRQID_USIP5
+#define    IRQ_USIP6_CODE                            MD_IRQID_USIP6
+#define    IRQ_USIP7_CODE                            MD_IRQID_USIP7
+#define    IRQ_USIP8_CODE                            MD_IRQID_USIP8
+#define    IRQ_USIP9_CODE                            MD_IRQID_USIP9
+#define    IRQ_USIP10_CODE                           MD_IRQID_USIP10
+#define    IRQ_USIP11_CODE                           MD_IRQID_USIP11
+#define    IRQ_USIP12_CODE                           MD_IRQID_USIP12
+#define    IRQ_USIP13_CODE                           MD_IRQID_USIP13
+#define    IRQ_TX_NR_CC0_IRQ_CODE                    MD_IRQID_TX_NR_CC0_IRQ
+#define    IRQ_TX_NR_CC1_IRQ_CODE                    MD_IRQID_TX_NR_CC1_IRQ
+#define    IRQ_TX_NR_ERR_CC_IRQ_CODE                 MD_IRQID_TX_NR_ERR_CC_IRQ
+#define    IRQ_MDMCU_SPU_IRQ_CODE                    MD_IRQID_MDMCU_SPU_IRQ
+#define    IRQ_DEM_TRIG_PS_INT_LE_CODE               MD_IRQID_DEM_TRIG_PS_INT_LE
+#define    IRQ_ECT_CODE                              MD_IRQID_ECT
+#define    IRQ_MDMCU_BUS_DECERR_IRQ_CODE             MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define    IRQ_MDMCU_OSTD_THROTTLE_CODE              MD_IRQID_MDMCU_OSTD_THROTTLE
+#define    IRQ_SHAOLIN_OSTD_THROTTLE_CODE            MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define    IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE         MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define    IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_AP2MD_CONN_WF_CCIF_0_CODE             MD_IRQID_AP2MD_CONN_WF_CCIF_0
+#define    IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_AP2MD_CONN_WF_CCIF_1_CODE             MD_IRQID_AP2MD_CONN_WF_CCIF_1
+#define    IRQ_MDWDT_CODE                            MD_IRQID_MDWDT
+#define    IRQ_MDGDMA_FDMA0_2_CODE                   MD_IRQID_MDGDMA_FDMA0_2
+#define    IRQ_MDGDMA_FDMA1_CODE                     MD_IRQID_MDGDMA_FDMA1
+#define    IRQ_MDGDMA_FDMA3_CODE                     MD_IRQID_MDGDMA_FDMA3
+#define    IRQ_MDGDMA_FDMA4_CODE                     MD_IRQID_MDGDMA_FDMA4
+#define    IRQ_MDGDMA_HDMA0_1_CODE                   MD_IRQID_MDGDMA_HDMA0_1
+#define    IRQ_MDGDMA_HDMA2_3_CODE                   MD_IRQID_MDGDMA_HDMA2_3
+#define    IRQ_AP2MD_CCIF0_0_CODE                    MD_IRQID_AP2MD_CCIF0_0
+#define    IRQ_AP2MD_CCIF0_1_CODE                    MD_IRQID_AP2MD_CCIF0_1
+#define    IRQ_AP2MD_CCIF1_0_CODE                    MD_IRQID_AP2MD_CCIF1_0
+#define    IRQ_AP2MD_CCIF1_1_CODE                    MD_IRQID_AP2MD_CCIF1_1
+#define    IRQ_IEBIT_CHECK_IRQ0_CODE                 MD_IRQID_IEBIT_CHECK_IRQ0
+#define    IRQ_IEBIT_CHECK_IRQ1_CODE                 MD_IRQID_IEBIT_CHECK_IRQ1
+#define    IRQ_IEBIT_CHECK_IRQ2_CODE                 MD_IRQID_IEBIT_CHECK_IRQ2
+#define    IRQ_IEBIT_CHECK_IRQ3_CODE                 MD_IRQID_IEBIT_CHECK_IRQ3
+#define    IRQ_IEBIT_CHECK_IRQ4_CODE                 MD_IRQID_IEBIT_CHECK_IRQ4
+#define    IRQ_IEBIT_CHECK_IRQ5_CODE                 MD_IRQID_IEBIT_CHECK_IRQ5
+#define    IRQ_IEBIT_CHECK_IRQ6_CODE                 MD_IRQID_IEBIT_CHECK_IRQ6
+#define    IRQ_IEBIT_CHECK_IRQ7_CODE                 MD_IRQID_IEBIT_CHECK_IRQ7
+#define    IRQ_IEBIT_CHECK_IRQ8_CODE                 MD_IRQID_IEBIT_CHECK_IRQ8
+#define    IRQ_IEBIT_CHECK_IRQ9_CODE                 MD_IRQID_IEBIT_CHECK_IRQ9
+#define    IRQ_IEBIT_CHECK_IRQ10_CODE                MD_IRQID_IEBIT_CHECK_IRQ10
+#define    IRQ_IEBIT_CHECK_IRQ11_CODE                MD_IRQID_IEBIT_CHECK_IRQ11
+#define    IRQ_NRL2_HRT_CODE                         MD_IRQID_NRL2_HRT
+#define    IRQ_NRL2_NOTIF_CODE                       MD_IRQID_NRL2_NOTIF
+#define    IRQ_NRL2_EXCEP_CODE                       MD_IRQID_NRL2_EXCEP
+#define    IRQ_NRL2_DPMAIF_MD_CODE                   MD_IRQID_NRL2_DPMAIF_MD
+#define    IRQ_RXDFE_IRQ0_CODE                       MD_IRQID_RXDFE_IRQ0
+#define    IRQ_IDC_UART_TX_FORCE_ON_CODE             MD_IRQID_IDC_UART_TX_FORCE_ON
+#define    IRQ_RXDFE_IRQ2_CODE                       MD_IRQID_RXDFE_IRQ2
+#define    IRQ_RXDFE_IRQ3_CODE                       MD_IRQID_RXDFE_IRQ3
+#define    IRQ_AP2MD_CONN_BGF_CCIF_0_CODE            MD_IRQID_AP2MD_CONN_BGF_CCIF_0
+#define    IRQ_MD_RXDFE_BB_DUMP_CODE                 MD_IRQID_MD_RXDFE_BB_DUMP
+#define    IRQ_AP2MD_CONN_BGF_CCIF_1_CODE            MD_IRQID_AP2MD_CONN_BGF_CCIF_1
+#define    IRQ_TXCRP_CODE                            MD_IRQID_TXCRP
+#define    IRQ_CM_NR_IRQ_CODE                        MD_IRQID_CM_NR_IRQ
+#define    IRQ_CM_NR_ERR_IRQ_CODE                    MD_IRQID_CM_NR_ERR_IRQ
+#define    IRQ_L1_LTE_SLEEP_IRQ_CODE                 MD_IRQID_L1_LTE_SLEEP_IRQ
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define    IRQ_D_GDMA_0_IRQ_CODE                     MD_IRQID_D_GDMA_0_IRQ
+#define    IRQ_D_GDMA_1_IRQ_CODE                     MD_IRQID_D_GDMA_1_IRQ
+#define    IRQ_D_GDMA_2_IRQ_CODE                     MD_IRQID_D_GDMA_2_IRQ
+#define    IRQ_D_GDMA_3_IRQ_CODE                     MD_IRQID_D_GDMA_3_IRQ
+#define    IRQ_D_GDMA_4_IRQ_CODE                     MD_IRQID_D_GDMA_4_IRQ
+#define    IRQ_D_GDMA_5_IRQ_CODE                     MD_IRQID_D_GDMA_5_IRQ
+#define    IRQ_PLL_GEARHP_RDY_CODE                   MD_IRQID_PLL_GEARHP_RDY
+#define    IRQ_REQ_ABNORM_IRQ_CODE                   MD_IRQID_REQ_ABNORM_IRQ
+#define    IRQ_NRL2_DPMAIF_MDMCU_CODE                MD_IRQID_NRL2_DPMAIF_MDMCU
+#define    IRQ_AP2MD_APWDT_IRQ_CODE                  MD_IRQID_AP2MD_APWDT_IRQ
+#define    IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE          MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ
+#define    IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE           MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ
+#define    IRQ_DUMMY_PRIORITY_CODE_5                 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define    IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE             MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define    IRQ_L1M_PHY_LTMR_IRQ_0_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define    IRQ_L1M_PHY_LTMR_IRQ_1_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define    IRQ_L1M_PHY_LTMR_IRQ_2_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define    IRQ_L1M_PHY_LTMR_IRQ_3_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define    IRQ_L1M_PHY_LTMR_IRQ_4_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define    IRQ_L1M_PHY_LTMR_IRQ_5_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define    IRQ_L1M_PHY_LTMR_IRQ_6_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define    IRQ_L1M_PHY_LTMR_IRQ_7_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define    IRQ_DUMMY_PRIORITY_CODE_6                 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define    IRQ_L1_LTE_WAKEUP_IRQ_CODE                MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define    IRQ_TDD_WAKEUP_IRQ_CODE                   MD_IRQID_TDD_WAKEUP_IRQ
+#define    IRQ_TDD_TIMER_L1D_1_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define    IRQ_TDD_TIMER_L1D_2_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define    IRQ_RTR_SLT_0_IRQ_CODE                    MD_IRQID_RTR_SLT_0_IRQ
+#define    IRQ_RTR_SLT_1_IRQ_CODE                    MD_IRQID_RTR_SLT_1_IRQ
+#define    IRQ_FDD_SLP_IRQ_CODE                      MD_IRQID_FDD_SLP_IRQ
+#define    IRQ_IRDBG_MCU_INT_CODE                    MD_IRQID_IRDBG_MCU_INT
+#define    IRQ_MD_DVFS_CTRL_IRQ_0_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define    IRQ_MD_DVFS_CTRL_IRQ_1_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define    IRQ_NR_SLP_WAKEUP_CODE                    MD_IRQID_NR_SLP_WAKEUP
+#define    IRQ_NR_SLP_SLEEP_CODE                     MD_IRQID_NR_SLP_SLEEP
+#define    IRQ_NR_TIMER_ERR_CODE                     MD_IRQID_NR_TIMER_ERR
+#define    IRQ_TXBSRP_CODE                           MD_IRQID_TXBSRP
+#define    IRQ_TXDFE_D_CODE                          MD_IRQID_TXDFE_D
+#define    IRQ_NR_EVENTGEN_ERR_CODE                  MD_IRQID_NR_EVENTGEN_ERR
+#define    IRQ_AIRQ_PAD_CODE                         MD_IRQID_AIRQ_PAD
+#define    IRQ_CSSYS_FDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_FDD_CS_IRQ
+#define    IRQ_CSSYS_TDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_TDD_CS_IRQ
+#define    IRQ_CSSYS_LTE_CS_IRQ_CODE                 MD_IRQID_CSSYS_LTE_CS_IRQ
+#define    IRQ_CSSYS_1X_CS_IRQ_CODE                  MD_IRQID_CSSYS_1X_CS_IRQ
+#define    IRQ_CSSYS_DO_CS_IRQ_CODE                  MD_IRQID_CSSYS_DO_CS_IRQ
+#define    IRQ_PCIE_INTERRUPT_OUT_CODE               MD_IRQID_PCIE_INTERRUPT_OUT
+#define    IRQ_UCNT_SCH_IRQ_CODE                     MD_IRQID_UCNT_SCH_IRQ
+#define    IRQ_UCNT_ERR_IRQ_CODE                     MD_IRQID_UCNT_ERR_IRQ
+#define    IRQ_UCNT_ADJ_IRQ_CODE                     MD_IRQID_UCNT_ADJ_IRQ
+#define    IRQ_SL_WAITSLEEP_CODE                     MD_IRQID_SL_WAITSLEEP
+#define    IRQ_PTP_THERM_INT_INT_CODE                MD_IRQID_PTP_THERM_INT_INT
+#define    IRQ_PTP_FSM_INT_CODE                      MD_IRQID_PTP_FSM_INT
+#define    IRQ_AP2MD_DAPC_CODE                       MD_IRQID_AP2MD_DAPC
+#define    IRQ_AP2MD_CCIF2_CODE                      MD_IRQID_AP2MD_CCIF2
+#define    IRQ_AP2MD_UFS_CODE                        MD_IRQID_AP2MD_UFS
+#define    IRQ_SSUSB_INTERRUPT_OUT_CODE              MD_IRQID_SSUSB_INTERRUPT_OUT
+#define    IRQ_AP2MD_MSDC0_CODE                      MD_IRQID_AP2MD_MSDC0
+#define    IRQ_MIPI_IRQ_CODE                         MD_IRQID_MIPI_IRQ
+#define    IRQ_CONN_BT_ISOCH_CODE                    MD_IRQID_CONN_BT_ISOCH
+#define    IRQ_RMPU_CTIREIGIN_CODE                   MD_IRQID_RMPU_CTIREIGIN
+#define    IRQ_FREQM_IRQ_CODE                        MD_IRQID_FREQM_IRQ
+#define    IRQ_BT_CVSD_CODE                          MD_IRQID_BT_CVSD
+#define    IRQ_SW_LISR0_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_0
+#define    IRQ_SW_LISR1_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_1
+#define    IRQ_SW_LISR2_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_2
+#define    IRQ_SW_LISR3_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_3
+#define    IRQ_SW_LISR4_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_4
+#define    IRQ_SW_LISR5_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_5
+#define    IRQ_SW_LISR6_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_6
+#define    IRQ_SW_LISR7_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_7
+#define    IRQ_SW_LISR8_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_8
+#define    IRQ_SW_LISR9_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_9
+#define    IRQ_SW_LISR10_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_10
+#define    IRQ_SW_LISR11_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_11
+#define    IRQ_SW_LISR12_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_12
+#define    IRQ_SW_LISR13_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_13
+#define    IRQ_SW_LISR14_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_14
+#define    IRQ_SW_LISR15_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_15
+#define    IRQ_SW_LISR16_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_16
+#define    IRQ_SW_LISR17_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_17
+#define    IRQ_SW_LISR18_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_18
+#define    IRQ_SW_LISR19_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_19
+#define    IRQ_SW_LISR20_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_20
+#define    IRQ_SW_LISR21_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_21
+#define    IRQ_SW_LISR22_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_22
+#define    IRQ_SW_LISR23_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_23
+#define    IRQ_SW_LISR24_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_24
+#define    IRQ_SW_LISR25_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_25
+#define    IRQ_SW_LISR26_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_26
+#define    IRQ_SW_LISR27_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_27
+#define    IRQ_SW_LISR28_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_28
+#define    IRQ_SW_LISR29_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_29
+#define    IRQ_SW_LISR30_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_30
+#define    IRQ_SW_LISR31_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_31
+#define    IRQ_SW_LISR32_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_32
+#define    IRQ_SW_LISR33_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_33
+#define    IRQ_SW_LISR34_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_34
+#define    IRQ_SW_LISR35_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_35
+#define    IRQ_SW_LISR36_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_36
+#define    IRQ_SW_LISR37_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_37
+#define    IRQ_SW_LISR38_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_38
+#define    IRQ_SW_LISR39_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_39
+#define    IRQ_SW_LISR40_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_40
+#define    IRQ_SW_LISR41_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_41
+#define    IRQ_SW_LISR42_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_42
+#define    IRQ_SW_LISR43_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_43
+#define    IRQ_SW_LISR44_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_44
+#define    IRQ_SW_LISR45_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_45
+#define    IRQ_SW_LISR46_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_46
+#define    IRQ_SW_LISR47_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_47
+#define    IRQ_SW_LISR48_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_48
+#define    IRQ_SW_LISR49_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_49
+#define    IRQ_SW_LISR50_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_50
+#define    IRQ_SW_LISR51_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_51
+#define    IRQ_SW_LISR52_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_52
+#define    IRQ_SW_LISR53_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_53
+#define    IRQ_SW_LISR54_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_54
+#define    IRQ_SW_LISR55_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_55
+#define    IRQ_SW_LISR56_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_56
+#define    IRQ_SW_LISR57_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_57
+#define    IRQ_SW_LISR58_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_58
+#define    IRQ_SW_LISR59_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_59
+#define    IRQ_SW_LISR60_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_60
+#define    IRQ_SW_LISR61_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_61
+#define    IRQ_SW_LISR62_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_62
+#define    IRQ_SW_LISR63_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_63
+#define    IRQ_SW_LISR64_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_64
+#define    IRQ_DUMMY_PRIORITY_CODE_8                 MD_IRQID_DUMMY_PRIORITY_IRQ8
+#define    IRQ_DUMMY_PRIORITY_CODE_9                 MD_IRQID_DUMMY_PRIORITY_IRQ9
+#define    IRQ_DUMMY_PRIORITY_CODE_10                MD_IRQID_DUMMY_PRIORITY_IRQ10
+#define    IRQ_DUMMY_PRIORITY_CODE_11                MD_IRQID_DUMMY_PRIORITY_IRQ11
+#define    IRQ_DUMMY_PRIORITY_CODE_12                MD_IRQID_DUMMY_PRIORITY_IRQ12
+#define    IRQ_DUMMY_PRIORITY_CODE_13                MD_IRQID_DUMMY_PRIORITY_IRQ13
+#define    IRQ_DUMMY_PRIORITY_CODE_14                MD_IRQID_DUMMY_PRIORITY_IRQ14
+#define    IRQ_DUMMY_PRIORITY_CODE_15                MD_IRQID_DUMMY_PRIORITY_IRQ15
+#define    IRQ_DUMMY_PRIORITY_CODE_16                MD_IRQID_DUMMY_PRIORITY_IRQ16
+#define    IRQ_DUMMY_PRIORITY_CODE_17                MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define    IRQ_DUMMY_PRIORITY_CODE_18                MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define    IRQ_DUMMY_PRIORITY_CODE_19                MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define    IRQ_DUMMY_PRIORITY_CODE_20                MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define    IRQ_DUMMY_PRIORITY_CODE_21                MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define    IRQ_DUMMY_PRIORITY_CODE_22                MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define    IRQ_DUMMY_PRIORITY_CODE_23                MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define    IRQ_DUMMY_PRIORITY_CODE_24                MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define    IRQ_DUMMY_PRIORITY_CODE_25                MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define    IRQ_DUMMY_PRIORITY_CODE_26                MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define    IRQ_DUMMY_PRIORITY_CODE_27                MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define    IRQ_DUMMY_PRIORITY_CODE_28                MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define    IRQ_DUMMY_PRIORITY_CODE_29                MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define    IRQ_DUMMY_PRIORITY_CODE_30                MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define    IRQ_SW_MODIS_MASE_HMU_CODE                IRQ_DUMMY_PRIORITY_CODE_25
+#define    IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE         IRQ_DUMMY_PRIORITY_CODE_26
+#define    IRQ_SW_MODIS_MASE_NR_TXLISR_CODE          IRQ_DUMMY_PRIORITY_CODE_27
+#define    IRQ_L1_PAE_SW_LISR0                       IRQ_DUMMY_PRIORITY_CODE_28
+#define    IRQ_L1_PAE_SW_LISR1                       IRQ_DUMMY_PRIORITY_CODE_29
+#define    IRQ_L1_PAE_SW_LISR2                       IRQ_DUMMY_PRIORITY_CODE_30
+#endif 
+
+
+/* IRQ Affinity Group Definition */
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+    /* Group0(0) */                                                                             0xFFE, \
+    /* Group1(1) */                                                                             0xFFD, \
+    /* Group2(2) */                                                                             0xFFB, \
+    /* Group3(3) */                                                                             0xFF7, \
+    /* Group4(4) */                                                                             0xFEF, \
+    /* Group5(5) */                                                                             0xFDF, \
+    /* Group6(6) */                                                                             0xFBF, \
+    /* Group7(7) */                                                                             0xF7F, \
+    /* Group8(8) */                                                                             0xEFF, \
+    /* Group9(9) */                                                                             0xDFF, \
+    /* Group10(10) */                                                                           0xBFF, \
+    /* Group11(11) */                                                                           0x7FF, \
+    /* Group12(1,4) */                                                                          0xFED, \
+    /* Group13(0,1,2) */                                                                        0xFF8, \
+    /* Group14(3,6,9) */                                                                        0xDB7, \
+    /* Group15(0,3,6,9) */                                                                      0xDB6, \
+    /* Group16(3,4,6,7,9,10) */                                                                 0x927, \
+    /* Group17(0,1,2,3,4,6,7,9,10) */                                                           0x920, \
+    /* Group18(3,4,5,6,7,8,9,10,11) */                                                          0x007, \
+    /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */                                                    0x000, \
+    /* Group20(3,4,6,7,9,10)        -> Reserved for NR runtime change affinity */               0x927, \
+    /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */               0x007, \
+    /* Group22(2)                   -> Reserved for LTE runtime change affinity */              0xFFB, \
+    /* Group23(0,2,3,4,6,7,9,10)    -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */  0x922, \
+    /* Group24(3,6,7,9,10)          -> Temp solution for IRQ0xEE to not preempt NR RX IRQs */   0x937, \
+    /* Group25(0,3,5,6,7,8,9,11)    -> Workaround for Serdes HW bug */                          0x416, \
+    /* Group26(0,2,3,6,7,9,10)      -> Workaround for IRQ0x80 pending hard affinity HRT IRQs */ 0x932, \
+    /* Group27 */                                                                               0xFFF, \
+    /* Group28 */                                                                               0xFFF, \
+    /* Group29 */                                                                               0xFFF, \
+    /* Group30 */                                                                               0xFFF, \
+    /* Group31 */                                                                               0xFFF,
+#endif
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions - 
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0         0   //(0)
+#define IRQ_AFFINITY_GROUP_VPE1         1   //(1)
+#define IRQ_AFFINITY_GROUP_VPE2         2   //(2)
+#define IRQ_AFFINITY_GROUP_VPE3         3   //(3)
+#define IRQ_AFFINITY_GROUP_VPE4         4   //(4)
+#define IRQ_AFFINITY_GROUP_VPE5         5   //(5)
+#define IRQ_AFFINITY_GROUP_VPE6         6   //(6)
+#define IRQ_AFFINITY_GROUP_VPE7         7   //(7)
+#define IRQ_AFFINITY_GROUP_VPE8	        8   //(8)
+#define IRQ_AFFINITY_GROUP_VPE9         9   //(9)
+#define IRQ_AFFINITY_GROUP_VPE10        10  //(10)
+#define IRQ_AFFINITY_GROUP_VPE11        11  //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4     12  //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0    13  //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR    14  //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP   15  //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR       16  //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP      17  //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR      18  //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE      19  //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+#define MAX_NUM_TASKS          256
+#define MAX_HISR_PRIORITY      2
+
+typedef enum
+{
+    VPE_STATUS_LISR_HIGHEST      = 0,
+    VPE_STATUS_LISR_LOWEST       = 342,
+    VPE_STATUS_HISR_TASK_HIGHEST = 512,
+    VPE_STATUS_HISR_TASK_LOWEST  = VPE_STATUS_HISR_TASK_HIGHEST + MAX_NUM_TASKS + MAX_HISR_PRIORITY, 
+    VPE_STATUS_END               = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_MT6877_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6877_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6877_SW_Handle.h
new file mode 100644
index 0000000..62e02dd
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6877_SW_Handle.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6877_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   MT6877
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE0  = Karthigeyan Reddy
+      SW_TRIGGER_CODE1  = Karthigeyan Reddy
+      SW_TRIGGER_CODE2  = Karthigeyan Reddy
+      SW_TRIGGER_CODE3  = Karthigeyan Reddy
+      SW_TRIGGER_CODE4  = Karthigeyan Reddy
+      SW_TRIGGER_CODE5  = Karthigeyan Reddy
+      SW_TRIGGER_CODE6  = Zengling Jin
+      SW_TRIGGER_CODE7  = Zengling Jin
+      SW_TRIGGER_CODE8  = Zengling Jin
+      SW_TRIGGER_CODE9  = Cruze Yu
+      SW_TRIGGER_CODE10 = Cruze Yu
+      SW_TRIGGER_CODE11 = Cruze Yu
+      SW_TRIGGER_CODE12 = Cruze Yu
+      SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+      SW_TRIGGER_CODE14 = HW Jheng
+      SW_TRIGGER_CODE15 = Frank Hu
+      SW_TRIGGER_CODE16 = KH Hsiao
+      SW_TRIGGER_CODE17 = Deepti Varadarajan
+      SW_TRIGGER_CODE18 = Owen Ho
+      SW_TRIGGER_CODE19 = Owen Ho
+      SW_TRIGGER_CODE20 = Owen Ho
+      SW_TRIGGER_CODE21 = Owen Ho
+      SW_TRIGGER_CODE22 = Jun-Ying Huang
+      SW_TRIGGER_CODE23 = Jun-Ying Huang
+      SW_TRIGGER_CODE24 = Jun-Ying Huang
+      SW_TRIGGER_CODE25 = Jun-Ying Huang
+      SW_TRIGGER_CODE26 = Wade Huang
+      SW_TRIGGER_CODE27 = Tee-Yuen Chun
+      SW_TRIGGER_CODE28 = YY Hsieh 
+      SW_TRIGGER_CODE29 = Hamilton Liang
+      SW_TRIGGER_CODE30 = HW Jheng
+      SW_TRIGGER_CODE31 = Weimin Zeng
+      SW_TRIGGER_CODE32 = Weimin Zeng
+      SW_TRIGGER_CODE33 = Jocobrian Chang
+      SW_TRIGGER_CODE34 = JiaHong Hsu
+      SW_TRIGGER_CODE35 = Cheng-Long Wu
+      SW_TRIGGER_CODE36 = Cheng-Long Wu
+      SW_TRIGGER_CODE37 = Jocobrian Chang
+      SW_TRIGGER_CODE38 = Jocobrian Chang
+      SW_TRIGGER_CODE39 = Jocobrian Chang
+      SW_TRIGGER_CODE40 = Shu-Wei Ho
+      SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+      SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+  */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6885.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6885.h
new file mode 100644
index 0000000..631e754
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6885.h
@@ -0,0 +1,564 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6885.h
+ *
+ * Project:
+ * --------
+ *   MT6885
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MT6885_H__
+#define __INTRCTRL_MT6885_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+
+#define NUM_IRQ_SOURCES          (368)
+
+/* CIRQ Interrupt Sources */
+#define    IRQ_USIM0_CODE                            MD_IRQID_USIM0
+#define    IRQ_USIM1_CODE                            MD_IRQID_USIM1
+#define    IRQ_TDMA_CTIRQ1_CODE                      MD_IRQID_TDMA_CTIRQ1
+#define    IRQ_TDMA_CTIRQ2_CODE                      MD_IRQID_TDMA_CTIRQ2
+#define    IRQ_TDMA_CTIRQ3_CODE                      MD_IRQID_TDMA_CTIRQ3
+#define    IRQ_TDMA_WAKEUP_IRQ_CODE                  MD_IRQID_TDMA_WAKEUP_IRQ
+#define    IRQ_OST_CODE                              MD_IRQID_OST
+#define    IRQ_MDRTT_CODE                            MD_IRQID_MDRTT
+#define    IRQ_MDEVDO_CODE                           MD_IRQID_MDEVDO
+#define    IRQ_ULSP_LOG_MCU_RT_INT_CODE              MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define    IRQ_ULSP_LOG_MCU_OD_INT_CODE              MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define    IRQ_ULSP_LOG_DSP4G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define    IRQ_ULSP_LOG_DSP4G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define    IRQ_ULSP_LOG_DSP5G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define    IRQ_ULSP_LOG_DSP5G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define    IRQ_SHARE_D12MINT1_CODE                   MD_IRQID_SHARE_D12MINT1
+#define    IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE        MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define    IRQ_AIRQ_SERDES_CODE                      MD_IRQID_AIRQ_SERDES
+#define    IRQ_AIRQ_COS_CODE                         MD_IRQID_AIRQ_COS
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define    IRQ_PPPHA_ENC0_INT_CODE                   MD_IRQID_PPPHA_ENC0_INT
+#define    IRQ_PPPHA_ENC1_INT_CODE                   MD_IRQID_PPPHA_ENC1_INT
+#define    IRQ_PPPHA_DEC0_INT_CODE                   MD_IRQID_PPPHA_DEC0_INT
+#define    IRQ_PPPHA_DEC1_INT_CODE                   MD_IRQID_PPPHA_DEC1_INT
+#define    IRQ_CS_NR_IRQ_CODE                        MD_IRQID_CS_NR_IRQ
+#define    IRQ_CS_NR_ERR_IRQ_CODE                    MD_IRQID_CS_NR_ERR_IRQ
+#define    IRQ_SDF_OVERFLOW_IRQ_CODE                 MD_IRQID_SDF_OVERFLOW_IRQ
+#define    IRQ_MCUMMU_INT_CODE                       MD_IRQID_MCUMMU_INT
+#define    IRQ_BIGRAM_0_IRQ_0_CODE                   MD_IRQID_BIGRAM_0_IRQ_0
+#define    IRQ_COS_PREP_INT_CODE                     MD_IRQID_COS_PREP_INT
+#define    IRQ_TRACE_INT_CODE                        MD_IRQID_TRACE_INT
+#define    IRQ_NR_TIMER_IRQ0_CODE                    MD_IRQID_NR_TIMER_IRQ0
+#define    IRQ_NR_TIMER_IRQ1_CODE                    MD_IRQID_NR_TIMER_IRQ1
+#define    IRQ_NR_TIMER_IRQ2_CODE                    MD_IRQID_NR_TIMER_IRQ2
+#define    IRQ_NR_TIMER_IRQ3_CODE                    MD_IRQID_NR_TIMER_IRQ3
+#define    IRQ_NR_TIMER_IRQ4_CODE                    MD_IRQID_NR_TIMER_IRQ4
+#define    IRQ_NR_TIMER_IRQ5_CODE                    MD_IRQID_NR_TIMER_IRQ5
+#define    IRQ_NR_TIMER_IRQ6_CODE                    MD_IRQID_NR_TIMER_IRQ6
+#define    IRQ_NR_TIMER_IRQ7_CODE                    MD_IRQID_NR_TIMER_IRQ7
+#define    IRQ_NR_TIMER_IRQ8_CODE                    MD_IRQID_NR_TIMER_IRQ8
+#define    IRQ_NR_TIMER_IRQ9_CODE                    MD_IRQID_NR_TIMER_IRQ9
+#define    IRQ_NR_TIMER_IRQ10_CODE                   MD_IRQID_NR_TIMER_IRQ10
+#define    IRQ_NR_TIMER_IRQ11_CODE                   MD_IRQID_NR_TIMER_IRQ11
+#define    IRQ_NR_TIMER_IRQ12_CODE                   MD_IRQID_NR_TIMER_IRQ12
+#define    IRQ_NR_TIMER_IRQ13_CODE                   MD_IRQID_NR_TIMER_IRQ13
+#define    IRQ_NR_TIMER_IRQ14_CODE                   MD_IRQID_NR_TIMER_IRQ14
+#define    IRQ_NR_TIMER_IRQ15_CODE                   MD_IRQID_NR_TIMER_IRQ15
+#define    IRQ_NR_TIMER_IRQ16_CODE                   MD_IRQID_NR_TIMER_IRQ16
+#define    IRQ_NR_TIMER_IRQ17_CODE                   MD_IRQID_NR_TIMER_IRQ17
+#define    IRQ_NR_TIMER_IRQ18_CODE                   MD_IRQID_NR_TIMER_IRQ18
+#define    IRQ_NR_TIMER_IRQ19_CODE                   MD_IRQID_NR_TIMER_IRQ19
+#define    IRQ_NR_TIMER_IRQ20_CODE                   MD_IRQID_NR_TIMER_IRQ20
+#define    IRQ_NR_TIMER_IRQ21_CODE                   MD_IRQID_NR_TIMER_IRQ21
+#define    IRQ_NR_TIMER_IRQ22_CODE                   MD_IRQID_NR_TIMER_IRQ22
+#define    IRQ_NR_TIMER_IRQ23_CODE                   MD_IRQID_NR_TIMER_IRQ23
+#define    IRQ_NR_TIMER_IRQ24_CODE                   MD_IRQID_NR_TIMER_IRQ24
+#define    IRQ_NR_TIMER_IRQ25_CODE                   MD_IRQID_NR_TIMER_IRQ25
+#define    IRQ_NR_TIMER_IRQ26_CODE                   MD_IRQID_NR_TIMER_IRQ26
+#define    IRQ_NR_TIMER_IRQ27_CODE                   MD_IRQID_NR_TIMER_IRQ27
+#define    IRQ_NR_TIMER_IRQ28_CODE                   MD_IRQID_NR_TIMER_IRQ28
+#define    IRQ_NR_TIMER_IRQ29_CODE                   MD_IRQID_NR_TIMER_IRQ29
+#define    IRQ_NR_TIMER_IRQ30_CODE                   MD_IRQID_NR_TIMER_IRQ30
+#define    IRQ_NR_TIMER_IRQ31_CODE                   MD_IRQID_NR_TIMER_IRQ31
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define    IRQ_NR_TIMER_CNTDN_IRQ0_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define    IRQ_NR_TIMER_CNTDN_IRQ1_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define    IRQ_NR_TIMER_CNTDN_IRQ2_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define    IRQ_NR_TIMER_CNTDN_IRQ3_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define    IRQ_NR_EVENTGEN_SPU_CODE                  MD_IRQID_NR_EVENTGEN_SPU
+#define    IRQ_SI_CM_ERR_CODE                        MD_IRQID_SI_CM_ERR
+#define    IRQ_SI_CM_PCINT_CODE                      MD_IRQID_SI_CM_PCINT
+#define    IRQ_MDM2C_U3G_CODE                        MD_IRQID_MDM2C_U3G
+#define    IRQ_RAKE_CMIF_M2C_IRQ_0_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define    IRQ_RAKE_CMIF_M2C_IRQ_1_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define    IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define    IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define    IRQ_RAKE_CMIF_PD_DO_IRQ_CODE              MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define    IRQ_MDMCU_BUSMON_MATCH_STS_CODE           MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define    IRQ_MDINFRA_BUSMON_MATCH_STS_CODE         MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define    IRQ_ELMTOP_EMI_IRQ_CODE                   MD_IRQID_ELMTOP_EMI_IRQ
+#define    IRQ_ELM_DMA_IRQ_CODE                      MD_IRQID_ELM_DMA_IRQ
+#define    IRQ_BUSMPU_IRQ_CODE                       MD_IRQID_BUSMPU_IRQ
+#define    IRQ_ST1X_CPINT_CODE                       MD_IRQID_ST1X_CPINT
+#define    IRQ_ST1x_HALF_CPINT_CODE                  MD_IRQID_ST1x_HALF_CPINT
+#define    IRQ_ST1x_CFG_CPINT_CODE                   MD_IRQID_ST1x_CFG_CPINT
+#define    IRQ_ST1x_WAKEUP_IRQ_CODE                  MD_IRQID_ST1x_WAKEUP_IRQ
+#define    IRQ_STDO_CPINT_CODE                       MD_IRQID_STDO_CPINT
+#define    IRQ_STDO_HALF_CPINT_CODE                  MD_IRQID_STDO_HALF_CPINT
+#define    IRQ_STDO_CFG_CPINT_CODE                   MD_IRQID_STDO_CFG_CPINT
+#define    IRQ_STDO_WAKEUP_IRQ_CODE                  MD_IRQID_STDO_WAKEUP_IRQ
+#define    IRQ_UART_MD0_CODE                         MD_IRQID_UART_MD0
+#define    IRQ_UART_MD1_CODE                         MD_IRQID_UART_MD1
+#define    IRQ_EINT0_CODE                            MD_IRQID_EINT0
+#define    IRQ_EINT1_CODE                            MD_IRQID_EINT1
+#define    IRQ_EINT2_CODE                            MD_IRQID_EINT2
+#define    IRQ_EINT3_CODE                            MD_IRQID_EINT3
+#define    IRQ_EINT_SHARE_CODE                       MD_IRQID_EINT_SHARE
+#define    IRQ_GPTM1_CODE                            MD_IRQID_GPTM1
+#define    IRQ_GPTM2_CODE                            MD_IRQID_GPTM2
+#define    IRQ_GPTM3_CODE                            MD_IRQID_GPTM3
+#define    IRQ_GPTM4_CODE                            MD_IRQID_GPTM4
+#define    IRQ_GPTM5_CODE                            MD_IRQID_GPTM5
+#define    IRQ_GPTM6_CODE                            MD_IRQID_GPTM6
+#define    IRQ_GPTM7_CODE                            MD_IRQID_GPTM7
+#define    IRQ_GPTM8_CODE                            MD_IRQID_GPTM8
+#define    IRQ_GPTM9_CODE                            MD_IRQID_GPTM9
+#define    IRQ_GPTM10_CODE                           MD_IRQID_GPTM10
+#define    IRQ_GPTM11_CODE                           MD_IRQID_GPTM11
+#define    IRQ_IDC_PM_INT_CODE                       MD_IRQID_IDC_PM_INT
+#define    IRQ_IDC_UART_IRQ_CODE                     MD_IRQID_IDC_UART_IRQ
+#define    IRQ_MDGDMA_FDMA5_CODE                     MD_IRQID_MDGDMA_FDMA5
+#define    IRQ_MDGDMA_FDMA6_CODE                     MD_IRQID_MDGDMA_FDMA6
+#define    IRQ_TDMA_CTIRQ4_CODE                      MD_IRQID_TDMA_CTIRQ4
+#define    IRQ_PDMA_CODE                             MD_IRQID_PDMA
+#define    IRQ_MDINFRA_BUS_DECERROR_CODE             MD_IRQID_MDINFRA_BUS_DECERROR
+#define    IRQ_I2C_TOP_INT_CODE                      MD_IRQID_I2C_TOP_INT
+#define    IRQ_SOE_CODE                              MD_IRQID_SOE
+#define    IRQ_ABM_INT_CODE                          MD_IRQID_ABM_INT
+#define    IRQ_ABM_ERROR_INT_CODE                    MD_IRQID_ABM_ERROR_INT
+#define    IRQ_USIP0_CODE                            MD_IRQID_USIP0
+#define    IRQ_USIP1_CODE                            MD_IRQID_USIP1
+#define    IRQ_USIP2_CODE                            MD_IRQID_USIP2
+#define    IRQ_USIP3_CODE                            MD_IRQID_USIP3
+#define    IRQ_USIP4_CODE                            MD_IRQID_USIP4
+#define    IRQ_USIP5_CODE                            MD_IRQID_USIP5
+#define    IRQ_USIP6_CODE                            MD_IRQID_USIP6
+#define    IRQ_USIP7_CODE                            MD_IRQID_USIP7
+#define    IRQ_USIP8_CODE                            MD_IRQID_USIP8
+#define    IRQ_USIP9_CODE                            MD_IRQID_USIP9
+#define    IRQ_USIP10_CODE                           MD_IRQID_USIP10
+#define    IRQ_USIP11_CODE                           MD_IRQID_USIP11
+#define    IRQ_USIP12_CODE                           MD_IRQID_USIP12
+#define    IRQ_USIP13_CODE                           MD_IRQID_USIP13
+#define    IRQ_TX_NR_CC0_IRQ_CODE                    MD_IRQID_TX_NR_CC0_IRQ
+#define    IRQ_TX_NR_CC1_IRQ_CODE                    MD_IRQID_TX_NR_CC1_IRQ
+#define    IRQ_TX_NR_ERR_CC_IRQ_CODE                 MD_IRQID_TX_NR_ERR_CC_IRQ
+#define    IRQ_MDMCU_SPU_IRQ_CODE                    MD_IRQID_MDMCU_SPU_IRQ
+#define    IRQ_DEM_TRIG_PS_INT_LE_CODE               MD_IRQID_DEM_TRIG_PS_INT_LE
+#define    IRQ_ECT_CODE                              MD_IRQID_ECT
+#define    IRQ_MDMCU_BUS_DECERR_IRQ_CODE             MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define    IRQ_MDMCU_OSTD_THROTTLE_CODE              MD_IRQID_MDMCU_OSTD_THROTTLE
+#define    IRQ_SHAOLIN_OSTD_THROTTLE_CODE            MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define    IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE         MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define    IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_AP2MD_CONN_WF_CCIF_0_CODE             MD_IRQID_AP2MD_CONN_WF_CCIF_0
+#define    IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_AP2MD_CONN_WF_CCIF_1_CODE             MD_IRQID_AP2MD_CONN_WF_CCIF_1
+#define    IRQ_MDWDT_CODE                            MD_IRQID_MDWDT
+#define    IRQ_MDGDMA_FDMA0_2_CODE                   MD_IRQID_MDGDMA_FDMA0_2
+#define    IRQ_MDGDMA_FDMA1_CODE                     MD_IRQID_MDGDMA_FDMA1
+#define    IRQ_MDGDMA_FDMA3_CODE                     MD_IRQID_MDGDMA_FDMA3
+#define    IRQ_MDGDMA_FDMA4_CODE                     MD_IRQID_MDGDMA_FDMA4
+#define    IRQ_MDGDMA_HDMA0_1_CODE                   MD_IRQID_MDGDMA_HDMA0_1
+#define    IRQ_MDGDMA_HDMA2_3_CODE                   MD_IRQID_MDGDMA_HDMA2_3
+#define    IRQ_AP2MD_CCIF0_0_CODE                    MD_IRQID_AP2MD_CCIF0_0
+#define    IRQ_AP2MD_CCIF0_1_CODE                    MD_IRQID_AP2MD_CCIF0_1
+#define    IRQ_AP2MD_CCIF1_0_CODE                    MD_IRQID_AP2MD_CCIF1_0
+#define    IRQ_AP2MD_CCIF1_1_CODE                    MD_IRQID_AP2MD_CCIF1_1
+#define    IRQ_IEBIT_CHECK_IRQ0_CODE                 MD_IRQID_IEBIT_CHECK_IRQ0
+#define    IRQ_IEBIT_CHECK_IRQ1_CODE                 MD_IRQID_IEBIT_CHECK_IRQ1
+#define    IRQ_IEBIT_CHECK_IRQ2_CODE                 MD_IRQID_IEBIT_CHECK_IRQ2
+#define    IRQ_IEBIT_CHECK_IRQ3_CODE                 MD_IRQID_IEBIT_CHECK_IRQ3
+#define    IRQ_IEBIT_CHECK_IRQ4_CODE                 MD_IRQID_IEBIT_CHECK_IRQ4
+#define    IRQ_IEBIT_CHECK_IRQ5_CODE                 MD_IRQID_IEBIT_CHECK_IRQ5
+#define    IRQ_IEBIT_CHECK_IRQ6_CODE                 MD_IRQID_IEBIT_CHECK_IRQ6
+#define    IRQ_IEBIT_CHECK_IRQ7_CODE                 MD_IRQID_IEBIT_CHECK_IRQ7
+#define    IRQ_IEBIT_CHECK_IRQ8_CODE                 MD_IRQID_IEBIT_CHECK_IRQ8
+#define    IRQ_IEBIT_CHECK_IRQ9_CODE                 MD_IRQID_IEBIT_CHECK_IRQ9
+#define    IRQ_IEBIT_CHECK_IRQ10_CODE                MD_IRQID_IEBIT_CHECK_IRQ10
+#define    IRQ_IEBIT_CHECK_IRQ11_CODE                MD_IRQID_IEBIT_CHECK_IRQ11
+#define    IRQ_NRL2_HRT_CODE                         MD_IRQID_NRL2_HRT
+#define    IRQ_NRL2_NOTIF_CODE                       MD_IRQID_NRL2_NOTIF
+#define    IRQ_NRL2_EXCEP_CODE                       MD_IRQID_NRL2_EXCEP
+#define    IRQ_NRL2_DPMAIF_MD_CODE                   MD_IRQID_NRL2_DPMAIF_MD
+#define    IRQ_RXDFE_IRQ0_CODE                       MD_IRQID_RXDFE_IRQ0
+#define    IRQ_IDC_UART_TX_FORCE_ON_CODE             MD_IRQID_IDC_UART_TX_FORCE_ON
+#define    IRQ_RXDFE_IRQ2_CODE                       MD_IRQID_RXDFE_IRQ2
+#define    IRQ_RXDFE_IRQ3_CODE                       MD_IRQID_RXDFE_IRQ3
+#define    IRQ_AP2MD_CONN_BGF_CCIF_0_CODE            MD_IRQID_AP2MD_CONN_BGF_CCIF_0
+#define    IRQ_MD_RXDFE_BB_DUMP_CODE                 MD_IRQID_MD_RXDFE_BB_DUMP
+#define    IRQ_AP2MD_CONN_BGF_CCIF_1_CODE            MD_IRQID_AP2MD_CONN_BGF_CCIF_1
+#define    IRQ_TXCRP_CODE                            MD_IRQID_TXCRP
+#define    IRQ_CM_NR_IRQ_CODE                        MD_IRQID_CM_NR_IRQ
+#define    IRQ_CM_NR_ERR_IRQ_CODE                    MD_IRQID_CM_NR_ERR_IRQ
+#define    IRQ_L1_LTE_SLEEP_IRQ_CODE                 MD_IRQID_L1_LTE_SLEEP_IRQ
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define    IRQ_D_GDMA_0_IRQ_CODE                     MD_IRQID_D_GDMA_0_IRQ
+#define    IRQ_D_GDMA_1_IRQ_CODE                     MD_IRQID_D_GDMA_1_IRQ
+#define    IRQ_D_GDMA_2_IRQ_CODE                     MD_IRQID_D_GDMA_2_IRQ
+#define    IRQ_D_GDMA_3_IRQ_CODE                     MD_IRQID_D_GDMA_3_IRQ
+#define    IRQ_D_GDMA_4_IRQ_CODE                     MD_IRQID_D_GDMA_4_IRQ
+#define    IRQ_D_GDMA_5_IRQ_CODE                     MD_IRQID_D_GDMA_5_IRQ
+#define    IRQ_PLL_GEARHP_RDY_CODE                   MD_IRQID_PLL_GEARHP_RDY
+#define    IRQ_REQ_ABNORM_IRQ_CODE                   MD_IRQID_REQ_ABNORM_IRQ
+#define    IRQ_NRL2_DPMAIF_MDMCU_CODE                MD_IRQID_NRL2_DPMAIF_MDMCU
+#define    IRQ_AP2MD_APWDT_IRQ_CODE                  MD_IRQID_AP2MD_APWDT_IRQ
+#define    IRQ_DUMMY_PRIORITY_CODE_3                 MD_IRQID_DUMMY_PRIORITY_IRQ3
+#define    IRQ_DUMMY_PRIORITY_CODE_4                 MD_IRQID_DUMMY_PRIORITY_IRQ4
+#define    IRQ_DUMMY_PRIORITY_CODE_5                 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define    IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE             MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define    IRQ_L1M_PHY_LTMR_IRQ_0_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define    IRQ_L1M_PHY_LTMR_IRQ_1_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define    IRQ_L1M_PHY_LTMR_IRQ_2_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define    IRQ_L1M_PHY_LTMR_IRQ_3_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define    IRQ_L1M_PHY_LTMR_IRQ_4_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define    IRQ_L1M_PHY_LTMR_IRQ_5_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define    IRQ_L1M_PHY_LTMR_IRQ_6_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define    IRQ_L1M_PHY_LTMR_IRQ_7_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define    IRQ_DUMMY_PRIORITY_CODE_6                 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define    IRQ_L1_LTE_WAKEUP_IRQ_CODE                MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define    IRQ_TDD_WAKEUP_IRQ_CODE                   MD_IRQID_TDD_WAKEUP_IRQ
+#define    IRQ_TDD_TIMER_L1D_1_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define    IRQ_TDD_TIMER_L1D_2_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define    IRQ_RTR_SLT_0_IRQ_CODE                    MD_IRQID_RTR_SLT_0_IRQ
+#define    IRQ_RTR_SLT_1_IRQ_CODE                    MD_IRQID_RTR_SLT_1_IRQ
+#define    IRQ_FDD_SLP_IRQ_CODE                      MD_IRQID_FDD_SLP_IRQ
+#define    IRQ_IRDBG_MCU_INT_CODE                    MD_IRQID_IRDBG_MCU_INT
+#define    IRQ_MD_DVFS_CTRL_IRQ_0_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define    IRQ_MD_DVFS_CTRL_IRQ_1_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define    IRQ_NR_SLP_WAKEUP_CODE                    MD_IRQID_NR_SLP_WAKEUP
+#define    IRQ_NR_SLP_SLEEP_CODE                     MD_IRQID_NR_SLP_SLEEP
+#define    IRQ_NR_TIMER_ERR_CODE                     MD_IRQID_NR_TIMER_ERR
+#define    IRQ_TXBSRP_CODE                           MD_IRQID_TXBSRP
+#define    IRQ_TXDFE_D_CODE                          MD_IRQID_TXDFE_D
+#define    IRQ_NR_EVENTGEN_ERR_CODE                  MD_IRQID_NR_EVENTGEN_ERR
+#define    IRQ_AIRQ_PAD_CODE                         MD_IRQID_AIRQ_PAD
+#define    IRQ_CSSYS_FDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_FDD_CS_IRQ
+#define    IRQ_CSSYS_TDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_TDD_CS_IRQ
+#define    IRQ_CSSYS_LTE_CS_IRQ_CODE                 MD_IRQID_CSSYS_LTE_CS_IRQ
+#define    IRQ_CSSYS_1X_CS_IRQ_CODE                  MD_IRQID_CSSYS_1X_CS_IRQ
+#define    IRQ_CSSYS_DO_CS_IRQ_CODE                  MD_IRQID_CSSYS_DO_CS_IRQ
+#define    IRQ_PCIE_INTERRUPT_OUT_CODE               MD_IRQID_PCIE_INTERRUPT_OUT
+#define    IRQ_UCNT_SCH_IRQ_CODE                     MD_IRQID_UCNT_SCH_IRQ
+#define    IRQ_UCNT_ERR_IRQ_CODE                     MD_IRQID_UCNT_ERR_IRQ
+#define    IRQ_UCNT_ADJ_IRQ_CODE                     MD_IRQID_UCNT_ADJ_IRQ
+#define    IRQ_SL_WAITSLEEP_CODE                     MD_IRQID_SL_WAITSLEEP
+#define    IRQ_PTP_THERM_INT_INT_CODE                MD_IRQID_PTP_THERM_INT_INT
+#define    IRQ_PTP_FSM_INT_CODE                      MD_IRQID_PTP_FSM_INT
+#define    IRQ_AP2MD_DAPC_CODE                       MD_IRQID_AP2MD_DAPC
+#define    IRQ_AP2MD_CCIF2_CODE                      MD_IRQID_AP2MD_CCIF2
+#define    IRQ_AP2MD_UFS_CODE                        MD_IRQID_AP2MD_UFS
+#define    IRQ_SSUSB_INTERRUPT_OUT_CODE              MD_IRQID_SSUSB_INTERRUPT_OUT
+#define    IRQ_AP2MD_MSDC0_CODE                      MD_IRQID_AP2MD_MSDC0
+#define    IRQ_MIPI_IRQ_CODE                         MD_IRQID_MIPI_IRQ
+#define    IRQ_CONN_BT_ISOCH_CODE                    MD_IRQID_CONN_BT_ISOCH
+#define    IRQ_RMPU_CTIREIGIN_CODE                   MD_IRQID_RMPU_CTIREIGIN
+#define    IRQ_FREQM_IRQ_CODE                        MD_IRQID_FREQM_IRQ
+#define    IRQ_BT_CVSD_CODE                          MD_IRQID_BT_CVSD
+#define    IRQ_SW_LISR0_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_0
+#define    IRQ_SW_LISR1_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_1
+#define    IRQ_SW_LISR2_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_2
+#define    IRQ_SW_LISR3_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_3
+#define    IRQ_SW_LISR4_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_4
+#define    IRQ_SW_LISR5_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_5
+#define    IRQ_SW_LISR6_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_6
+#define    IRQ_SW_LISR7_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_7
+#define    IRQ_SW_LISR8_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_8
+#define    IRQ_SW_LISR9_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_9
+#define    IRQ_SW_LISR10_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_10
+#define    IRQ_SW_LISR11_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_11
+#define    IRQ_SW_LISR12_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_12
+#define    IRQ_SW_LISR13_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_13
+#define    IRQ_SW_LISR14_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_14
+#define    IRQ_SW_LISR15_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_15
+#define    IRQ_SW_LISR16_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_16
+#define    IRQ_SW_LISR17_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_17
+#define    IRQ_SW_LISR18_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_18
+#define    IRQ_SW_LISR19_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_19
+#define    IRQ_SW_LISR20_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_20
+#define    IRQ_SW_LISR21_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_21
+#define    IRQ_SW_LISR22_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_22
+#define    IRQ_SW_LISR23_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_23
+#define    IRQ_SW_LISR24_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_24
+#define    IRQ_SW_LISR25_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_25
+#define    IRQ_SW_LISR26_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_26
+#define    IRQ_SW_LISR27_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_27
+#define    IRQ_SW_LISR28_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_28
+#define    IRQ_SW_LISR29_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_29
+#define    IRQ_SW_LISR30_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_30
+#define    IRQ_SW_LISR31_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_31
+#define    IRQ_SW_LISR32_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_32
+#define    IRQ_SW_LISR33_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_33
+#define    IRQ_SW_LISR34_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_34
+#define    IRQ_SW_LISR35_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_35
+#define    IRQ_SW_LISR36_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_36
+#define    IRQ_SW_LISR37_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_37
+#define    IRQ_SW_LISR38_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_38
+#define    IRQ_SW_LISR39_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_39
+#define    IRQ_SW_LISR40_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_40
+#define    IRQ_SW_LISR41_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_41
+#define    IRQ_SW_LISR42_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_42
+#define    IRQ_SW_LISR43_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_43
+#define    IRQ_SW_LISR44_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_44
+#define    IRQ_SW_LISR45_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_45
+#define    IRQ_SW_LISR46_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_46
+#define    IRQ_SW_LISR47_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_47
+#define    IRQ_SW_LISR48_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_48
+#define    IRQ_SW_LISR49_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_49
+#define    IRQ_SW_LISR50_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_50
+#define    IRQ_SW_LISR51_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_51
+#define    IRQ_SW_LISR52_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_52
+#define    IRQ_SW_LISR53_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_53
+#define    IRQ_SW_LISR54_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_54
+#define    IRQ_SW_LISR55_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_55
+#define    IRQ_SW_LISR56_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_56
+#define    IRQ_SW_LISR57_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_57
+#define    IRQ_SW_LISR58_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_58
+#define    IRQ_SW_LISR59_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_59
+#define    IRQ_SW_LISR60_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_60
+#define    IRQ_SW_LISR61_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_61
+#define    IRQ_SW_LISR62_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_62
+#define    IRQ_SW_LISR63_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_63
+#define    IRQ_SW_LISR64_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_64
+#define    IRQ_DUMMY_PRIORITY_CODE_8                 MD_IRQID_DUMMY_PRIORITY_IRQ8
+#define    IRQ_DUMMY_PRIORITY_CODE_9                 MD_IRQID_DUMMY_PRIORITY_IRQ9
+#define    IRQ_DUMMY_PRIORITY_CODE_10                MD_IRQID_DUMMY_PRIORITY_IRQ10
+#define    IRQ_DUMMY_PRIORITY_CODE_11                MD_IRQID_DUMMY_PRIORITY_IRQ11
+#define    IRQ_DUMMY_PRIORITY_CODE_12                MD_IRQID_DUMMY_PRIORITY_IRQ12
+#define    IRQ_DUMMY_PRIORITY_CODE_13                MD_IRQID_DUMMY_PRIORITY_IRQ13
+#define    IRQ_DUMMY_PRIORITY_CODE_14                MD_IRQID_DUMMY_PRIORITY_IRQ14
+#define    IRQ_DUMMY_PRIORITY_CODE_15                MD_IRQID_DUMMY_PRIORITY_IRQ15
+#define    IRQ_DUMMY_PRIORITY_CODE_16                MD_IRQID_DUMMY_PRIORITY_IRQ16
+#define    IRQ_DUMMY_PRIORITY_CODE_17                MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define    IRQ_DUMMY_PRIORITY_CODE_18                MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define    IRQ_DUMMY_PRIORITY_CODE_19                MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define    IRQ_DUMMY_PRIORITY_CODE_20                MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define    IRQ_DUMMY_PRIORITY_CODE_21                MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define    IRQ_DUMMY_PRIORITY_CODE_22                MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define    IRQ_DUMMY_PRIORITY_CODE_23                MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define    IRQ_DUMMY_PRIORITY_CODE_24                MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define    IRQ_DUMMY_PRIORITY_CODE_25                MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define    IRQ_DUMMY_PRIORITY_CODE_26                MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define    IRQ_DUMMY_PRIORITY_CODE_27                MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define    IRQ_DUMMY_PRIORITY_CODE_28                MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define    IRQ_DUMMY_PRIORITY_CODE_29                MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define    IRQ_DUMMY_PRIORITY_CODE_30                MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define    IRQ_SW_MODIS_MASE_HMU_CODE                IRQ_DUMMY_PRIORITY_CODE_25
+#define    IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE         IRQ_DUMMY_PRIORITY_CODE_26
+#define    IRQ_SW_MODIS_MASE_NR_TXLISR_CODE          IRQ_DUMMY_PRIORITY_CODE_27
+#define    IRQ_L1_PAE_SW_LISR0                       IRQ_DUMMY_PRIORITY_CODE_28
+#define    IRQ_L1_PAE_SW_LISR1                       IRQ_DUMMY_PRIORITY_CODE_29
+#define    IRQ_L1_PAE_SW_LISR2                       IRQ_DUMMY_PRIORITY_CODE_30
+#endif 
+
+
+/* IRQ Affinity Group Definition */
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+    /* Group0(0) */                                                                             0xFFE, \
+    /* Group1(1) */                                                                             0xFFD, \
+    /* Group2(2) */                                                                             0xFFB, \
+    /* Group3(3) */                                                                             0xFF7, \
+    /* Group4(4) */                                                                             0xFEF, \
+    /* Group5(5) */                                                                             0xFDF, \
+    /* Group6(6) */                                                                             0xFBF, \
+    /* Group7(7) */                                                                             0xF7F, \
+    /* Group8(8) */                                                                             0xEFF, \
+    /* Group9(9) */                                                                             0xDFF, \
+    /* Group10(10) */                                                                           0xBFF, \
+    /* Group11(11) */                                                                           0x7FF, \
+    /* Group12(1,4) */                                                                          0xFED, \
+    /* Group13(0,1,2) */                                                                        0xFF8, \
+    /* Group14(3,6,9) */                                                                        0xDB7, \
+    /* Group15(0,3,6,9) */                                                                      0xDB6, \
+    /* Group16(3,4,6,7,9,10) */                                                                 0x927, \
+    /* Group17(0,1,2,3,4,6,7,9,10) */                                                           0x920, \
+    /* Group18(3,4,5,6,7,8,9,10,11) */                                                          0x007, \
+    /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */                                                    0x000, \
+    /* Group20(3,4,6,7,9,10)        -> Reserved for NR runtime change affinity */               0x927, \
+    /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */               0x007, \
+    /* Group22(2)                   -> Reserved for LTE runtime change affinity */              0xFFB, \
+    /* Group23(0,2,3,4,6,7,9,10)    -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */  0x922, \
+    /* Group24(3,6,7,9,10)          -> Temp solution for IRQ0xEE to not preempt NR RX IRQs */   0x937, \
+    /* Group25(0,3,5,6,7,8,9,11)    -> Workaround for Serdes HW bug */                          0x416, \
+    /* Group26(0,2,3,6,7,9,10)      -> Workaround for IRQ0x80 pending hard affinity HRT IRQs */ 0x932, \
+    /* Group27 */                                                                               0xFFF, \
+    /* Group28 */                                                                               0xFFF, \
+    /* Group29 */                                                                               0xFFF, \
+    /* Group30 */                                                                               0xFFF, \
+    /* Group31 */                                                                               0xFFF,
+#endif
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions - 
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0         0   //(0)
+#define IRQ_AFFINITY_GROUP_VPE1         1   //(1)
+#define IRQ_AFFINITY_GROUP_VPE2         2   //(2)
+#define IRQ_AFFINITY_GROUP_VPE3         3   //(3)
+#define IRQ_AFFINITY_GROUP_VPE4         4   //(4)
+#define IRQ_AFFINITY_GROUP_VPE5         5   //(5)
+#define IRQ_AFFINITY_GROUP_VPE6         6   //(6)
+#define IRQ_AFFINITY_GROUP_VPE7         7   //(7)
+#define IRQ_AFFINITY_GROUP_VPE8	        8   //(8)
+#define IRQ_AFFINITY_GROUP_VPE9         9   //(9)
+#define IRQ_AFFINITY_GROUP_VPE10        10  //(10)
+#define IRQ_AFFINITY_GROUP_VPE11        11  //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4     12  //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0    13  //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR    14  //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP   15  //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR       16  //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP      17  //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR      18  //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE      19  //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+#define MAX_NUM_TASKS          256
+#define MAX_HISR_PRIORITY      2
+
+typedef enum
+{
+    VPE_STATUS_LISR_HIGHEST      = 0,
+    VPE_STATUS_LISR_LOWEST       = 340,
+    VPE_STATUS_HISR_TASK_HIGHEST = 512,
+    VPE_STATUS_HISR_TASK_LOWEST  = VPE_STATUS_HISR_TASK_HIGHEST + MAX_NUM_TASKS + MAX_HISR_PRIORITY, 
+    VPE_STATUS_END               = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_MT6885_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6885_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6885_SW_Handle.h
new file mode 100644
index 0000000..241d5ad
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_MT6885_SW_Handle.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MT6885_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   MT6885
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE0  = Karthigeyan Reddy
+      SW_TRIGGER_CODE1  = Karthigeyan Reddy
+      SW_TRIGGER_CODE2  = Karthigeyan Reddy
+      SW_TRIGGER_CODE3  = Karthigeyan Reddy
+      SW_TRIGGER_CODE4  = Karthigeyan Reddy
+      SW_TRIGGER_CODE5  = Karthigeyan Reddy
+      SW_TRIGGER_CODE6  = Zengling Jin
+      SW_TRIGGER_CODE7  = Zengling Jin
+      SW_TRIGGER_CODE8  = Zengling Jin
+      SW_TRIGGER_CODE9  = Cruze Yu
+      SW_TRIGGER_CODE10 = Cruze Yu
+      SW_TRIGGER_CODE11 = Cruze Yu
+      SW_TRIGGER_CODE12 = Cruze Yu
+      SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+      SW_TRIGGER_CODE14 = HW Jheng
+      SW_TRIGGER_CODE15 = Frank Hu
+      SW_TRIGGER_CODE16 = KH Hsiao
+      SW_TRIGGER_CODE17 = Deepti Varadarajan
+      SW_TRIGGER_CODE18 = Owen Ho
+      SW_TRIGGER_CODE19 = Owen Ho
+      SW_TRIGGER_CODE20 = Owen Ho
+      SW_TRIGGER_CODE21 = Owen Ho
+      SW_TRIGGER_CODE22 = Jun-Ying Huang
+      SW_TRIGGER_CODE23 = Jun-Ying Huang
+      SW_TRIGGER_CODE24 = Jun-Ying Huang
+      SW_TRIGGER_CODE25 = Jun-Ying Huang
+      SW_TRIGGER_CODE26 = Wade Huang
+      SW_TRIGGER_CODE27 = Tee-Yuen Chun
+      SW_TRIGGER_CODE28 = YY Hsieh 
+      SW_TRIGGER_CODE29 = Hamilton Liang
+      SW_TRIGGER_CODE30 = HW Jheng
+      SW_TRIGGER_CODE31 = Weimin Zeng
+      SW_TRIGGER_CODE32 = Weimin Zeng
+      SW_TRIGGER_CODE33 = Jocobrian Chang
+      SW_TRIGGER_CODE34 = JiaHong Hsu
+      SW_TRIGGER_CODE35 = Cheng-Long Wu
+      SW_TRIGGER_CODE36 = Cheng-Long Wu
+      SW_TRIGGER_CODE37 = Jocobrian Chang
+      SW_TRIGGER_CODE38 = Jocobrian Chang
+      SW_TRIGGER_CODE39 = Jocobrian Chang
+      SW_TRIGGER_CODE40 = Shu-Wei Ho
+      SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+      SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+  */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_SW_Handle.h
new file mode 100644
index 0000000..7a3ca5a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/intrCtrl_SW_Handle.h
@@ -0,0 +1,121 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *   This file include the each BB chip software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/* Include Chip SW handler */
+
+#if defined(MT6297)
+   #include "intrCtrl_MT6297_SW_Handle.h"
+#endif
+
+#if defined(MT6885)
+   #include "intrCtrl_MT6885_SW_Handle.h"
+#endif
+
+#if defined(MT6873)
+   #include "intrCtrl_MT6873_SW_Handle.h"
+#endif
+
+#if defined(MT6853)
+   #include "intrCtrl_MT6853_SW_Handle.h"
+#endif
+
+#if defined(MT6833)
+   #include "intrCtrl_MT6833_SW_Handle.h"
+#endif
+
+#if defined(MT6877)
+   #include "intrCtrl_MT6877_SW_Handle.h"
+#endif
+
+#if defined(CHIP10992)
+   #include "intrCtrl_CHIP10992_SW_Handle.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority.h
new file mode 100644
index 0000000..318d6cc
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority.h
@@ -0,0 +1,27 @@
+#if defined(MT6297)
+   #include "irqPriority_MT6297.h"
+#endif
+
+#if defined(MT6885)
+   #include "irqPriority_MT6885.h"
+#endif
+
+#if defined(MT6873)
+   #include "irqPriority_MT6873.h"
+#endif
+
+#if defined(MT6853)
+   #include "irqPriority_MT6853.h"
+#endif
+
+#if defined(MT6833)
+   #include "irqPriority_MT6833.h"
+#endif
+
+#if defined(MT6877)
+   #include "irqPriority_MT6877.h"
+#endif
+
+#if defined(CHIP10992)
+   #include "irqPriority_CHIP10992.h"
+#endif
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority_CHIP10992.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_CHIP10992.h
new file mode 100644
index 0000000..21b3909
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_CHIP10992.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_TX_FORCE_ON_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_SL_WAITSLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA6_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA0_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA2_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DAPC_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_CLDMA0_MD_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA1_MD_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA2_MD_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA3_MD_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MHCCIF_SAP2USIP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MHCCIF_SAP2MDMCU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NFI_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA1_AP_INT_PCIE_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA3_AP_INT_PCIE_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6297.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6297.h
new file mode 100644
index 0000000..4f2f28e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6297.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_READ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MHCCIF_SAP2USIP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA2_MD_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA0_MD_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CLDMA1_MD_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE1_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE1_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NFI_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MHCCIF_SAP2MDMCU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_0)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_1)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_7)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_11)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_12)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_13)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_14)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_15)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_16)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6833.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6833.h
new file mode 100644
index 0000000..2accbab
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6833.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_TX_FORCE_ON_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_SL_WAITSLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA6_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA0_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA2_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DAPC_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_11)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_12)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_13)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_14)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_15)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_16)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6853.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6853.h
new file mode 100644
index 0000000..2accbab
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6853.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_TX_FORCE_ON_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_SL_WAITSLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA6_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA0_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA2_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DAPC_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_11)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_12)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_13)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_14)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_15)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_16)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6873.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6873.h
new file mode 100644
index 0000000..d117327
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6873.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_TX_FORCE_ON_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_SL_WAITSLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA6_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA0_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA2_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DAPC_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_11)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_12)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_13)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_14)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_15)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_16)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6877.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6877.h
new file mode 100644
index 0000000..2accbab
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6877.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_TX_FORCE_ON_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_SL_WAITSLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA6_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA0_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA2_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DAPC_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_SUSPEND_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APMCU_ACTIVE_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_11)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_12)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_13)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_14)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_15)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_16)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6885.h b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6885.h
new file mode 100644
index 0000000..94eb3bd
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqPriority_MT6885.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_TX_FORCE_ON_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_SL_WAITSLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA6_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA0_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA2_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DAPC_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_11)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_12)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_13)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_14)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_15)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_16)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid.h b/mcu/interface/driver/devdrv/cirq/md97/irqid.h
new file mode 100644
index 0000000..e7d88b7
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid.h
@@ -0,0 +1,32 @@
+#ifndef __IRQID_H__
+#define __IRQID_H__
+
+#if defined(MT6297)
+   #include "irqid_MT6297.h"
+#endif
+
+#if defined(MT6885)
+   #include "irqid_MT6885.h"
+#endif
+
+#if defined(MT6873)
+   #include "irqid_MT6873.h"
+#endif
+
+#if defined(MT6853)
+   #include "irqid_MT6853.h"
+#endif
+
+#if defined(MT6833)
+   #include "irqid_MT6833.h"
+#endif
+
+#if defined(MT6877)
+   #include "irqid_MT6877.h"
+#endif
+
+#if defined(CHIP10992)
+   #include "irqid_CHIP10992.h"
+#endif
+
+#endif /*end of __IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid_CHIP10992.h b/mcu/interface/driver/devdrv/cirq/md97/irqid_CHIP10992.h
new file mode 100644
index 0000000..69ab11e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid_CHIP10992.h
@@ -0,0 +1,388 @@
+#ifndef __CHIP10992_IRQID_H__
+#define __CHIP10992_IRQID_H__
+
+
+//CHIP10992 IRQID
+#define MD_IRQID_USIM0                                0
+#define MD_IRQID_USIM1                                1
+#define MD_IRQID_TDMA_CTIRQ1                          2
+#define MD_IRQID_TDMA_CTIRQ2                          3
+#define MD_IRQID_TDMA_CTIRQ3                          4
+#define MD_IRQID_TDMA_WAKEUP_IRQ                      5
+#define MD_IRQID_OST                                  6
+#define MD_IRQID_MDRTT                                7
+#define MD_IRQID_MDEVDO                               8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT                  9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT                 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT               11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT               12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT               13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT               14
+#define MD_IRQID_SHARE_D12MINT1                      15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ          16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ          17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ          18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ          19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ          20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ          21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ           22
+#define MD_IRQID_AIRQ_SERDES                         23
+#define MD_IRQID_AIRQ_COS                            24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR            25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR            26
+#define MD_IRQID_PPPHA_ENC0_INT                      27
+#define MD_IRQID_PPPHA_ENC1_INT                      28
+#define MD_IRQID_PPPHA_DEC0_INT                      29
+#define MD_IRQID_PPPHA_DEC1_INT                      30
+#define MD_IRQID_CS_NR_IRQ                           31
+#define MD_IRQID_CS_NR_ERR_IRQ                       32
+#define MD_IRQID_SDF_OVERFLOW_IRQ                    33
+#define MD_IRQID_MCUMMU_INT                          34
+#define MD_IRQID_BIGRAM_0_IRQ_0                      35
+#define MD_IRQID_COS_PREP_INT                        36
+#define MD_IRQID_TRACE_INT                           37
+#define MD_IRQID_NR_TIMER_IRQ0                       38
+#define MD_IRQID_NR_TIMER_IRQ1                       39
+#define MD_IRQID_NR_TIMER_IRQ2                       40
+#define MD_IRQID_NR_TIMER_IRQ3                       41
+#define MD_IRQID_NR_TIMER_IRQ4                       42
+#define MD_IRQID_NR_TIMER_IRQ5                       43
+#define MD_IRQID_NR_TIMER_IRQ6                       44
+#define MD_IRQID_NR_TIMER_IRQ7                       45
+#define MD_IRQID_NR_TIMER_IRQ8                       46
+#define MD_IRQID_NR_TIMER_IRQ9                       47
+#define MD_IRQID_NR_TIMER_IRQ10                      48
+#define MD_IRQID_NR_TIMER_IRQ11                      49
+#define MD_IRQID_NR_TIMER_IRQ12                      50
+#define MD_IRQID_NR_TIMER_IRQ13                      51
+#define MD_IRQID_NR_TIMER_IRQ14                      52
+#define MD_IRQID_NR_TIMER_IRQ15                      53
+#define MD_IRQID_NR_TIMER_IRQ16                      54
+#define MD_IRQID_NR_TIMER_IRQ17                      55
+#define MD_IRQID_NR_TIMER_IRQ18                      56
+#define MD_IRQID_NR_TIMER_IRQ19                      57
+#define MD_IRQID_NR_TIMER_IRQ20                      58
+#define MD_IRQID_NR_TIMER_IRQ21                      59
+#define MD_IRQID_NR_TIMER_IRQ22                      60
+#define MD_IRQID_NR_TIMER_IRQ23                      61
+#define MD_IRQID_NR_TIMER_IRQ24                      62
+#define MD_IRQID_NR_TIMER_IRQ25                      63
+#define MD_IRQID_NR_TIMER_IRQ26                      64
+#define MD_IRQID_NR_TIMER_IRQ27                      65
+#define MD_IRQID_NR_TIMER_IRQ28                      66
+#define MD_IRQID_NR_TIMER_IRQ29                      67
+#define MD_IRQID_NR_TIMER_IRQ30                      68
+#define MD_IRQID_NR_TIMER_IRQ31                      69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0           70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1           71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2           72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3           73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4           74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5           75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6           76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7           77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8           78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9           79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10          80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11          81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12          82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13          83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14          84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15          85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16          86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17          87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0                 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1                 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2                 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3                 91
+#define MD_IRQID_NR_EVENTGEN_SPU                     92
+#define MD_IRQID_SI_CM_ERR                           93
+#define MD_IRQID_SI_CM_PCINT                         94
+#define MD_IRQID_MDM2C_U3G                           95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0                 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1                 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ                98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ                99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ                100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS             101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS           102
+#define MD_IRQID_ELMTOP_EMI_IRQ                     103
+#define MD_IRQID_ELM_DMA_IRQ                        104
+#define MD_IRQID_BUSMPU_IRQ                         105
+#define MD_IRQID_ST1X_CPINT                         106
+#define MD_IRQID_ST1x_HALF_CPINT                    107
+#define MD_IRQID_ST1x_CFG_CPINT                     108
+#define MD_IRQID_ST1x_WAKEUP_IRQ                    109
+#define MD_IRQID_STDO_CPINT                         110
+#define MD_IRQID_STDO_HALF_CPINT                    111
+#define MD_IRQID_STDO_CFG_CPINT                     112
+#define MD_IRQID_STDO_WAKEUP_IRQ                    113
+#define MD_IRQID_UART_MD0                           114
+#define MD_IRQID_UART_MD1                           115
+#define MD_IRQID_EINT0                              116
+#define MD_IRQID_EINT1                              117
+#define MD_IRQID_EINT2                              118
+#define MD_IRQID_EINT3                              119
+#define MD_IRQID_EINT_SHARE                         120
+#define MD_IRQID_GPTM1                              121
+#define MD_IRQID_GPTM2                              122
+#define MD_IRQID_GPTM3                              123
+#define MD_IRQID_GPTM4                              124
+#define MD_IRQID_GPTM5                              125
+#define MD_IRQID_GPTM6                              126
+#define MD_IRQID_GPTM7                              127
+#define MD_IRQID_GPTM8                              128
+#define MD_IRQID_GPTM9                              129
+#define MD_IRQID_GPTM10                             130
+#define MD_IRQID_GPTM11                             131
+#define MD_IRQID_IDC_PM_INT                         132
+#define MD_IRQID_IDC_UART_IRQ                       133
+#define MD_IRQID_MDGDMA_FDMA5                       134
+#define MD_IRQID_MDGDMA_FDMA6                       135
+#define MD_IRQID_TDMA_CTIRQ4                        136
+#define MD_IRQID_PDMA                               137
+#define MD_IRQID_MDINFRA_BUS_DECERROR               138
+#define MD_IRQID_I2C_TOP_INT                        139
+#define MD_IRQID_SOE                                140
+#define MD_IRQID_ABM_INT                            141
+#define MD_IRQID_ABM_ERROR_INT                      142
+#define MD_IRQID_USIP0                              143
+#define MD_IRQID_USIP1                              144
+#define MD_IRQID_USIP2                              145
+#define MD_IRQID_USIP3                              146
+#define MD_IRQID_USIP4                              147
+#define MD_IRQID_USIP5                              148
+#define MD_IRQID_USIP6                              149
+#define MD_IRQID_USIP7                              150
+#define MD_IRQID_USIP8                              151
+#define MD_IRQID_USIP9                              152
+#define MD_IRQID_USIP10                             153
+#define MD_IRQID_USIP11                             154
+#define MD_IRQID_USIP12                             155
+#define MD_IRQID_USIP13                             156
+#define MD_IRQID_TX_NR_CC0_IRQ                      157
+#define MD_IRQID_TX_NR_CC1_IRQ                      158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ                   159
+#define MD_IRQID_MDMCU_SPU_IRQ                      160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE                 161
+#define MD_IRQID_ECT                                162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ               163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE                164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE              165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ           166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ     167
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_0               168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ     169
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_1               170
+#define MD_IRQID_MDWDT                              171
+#define MD_IRQID_MDGDMA_FDMA0_2                     172
+#define MD_IRQID_MDGDMA_FDMA1                       173
+#define MD_IRQID_MDGDMA_FDMA3                       174
+#define MD_IRQID_MDGDMA_FDMA4                       175
+#define MD_IRQID_MDGDMA_HDMA0_1                     176
+#define MD_IRQID_MDGDMA_HDMA2_3                     177
+#define MD_IRQID_AP2MD_CCIF0_0                      178
+#define MD_IRQID_AP2MD_CCIF0_1                      179
+#define MD_IRQID_AP2MD_CCIF1_0                      180
+#define MD_IRQID_AP2MD_CCIF1_1                      181
+#define MD_IRQID_IEBIT_CHECK_IRQ0                   182
+#define MD_IRQID_IEBIT_CHECK_IRQ1                   183
+#define MD_IRQID_IEBIT_CHECK_IRQ2                   184
+#define MD_IRQID_IEBIT_CHECK_IRQ3                   185
+#define MD_IRQID_IEBIT_CHECK_IRQ4                   186
+#define MD_IRQID_IEBIT_CHECK_IRQ5                   187
+#define MD_IRQID_IEBIT_CHECK_IRQ6                   188
+#define MD_IRQID_IEBIT_CHECK_IRQ7                   189
+#define MD_IRQID_IEBIT_CHECK_IRQ8                   190
+#define MD_IRQID_IEBIT_CHECK_IRQ9                   191
+#define MD_IRQID_IEBIT_CHECK_IRQ10                  192
+#define MD_IRQID_IEBIT_CHECK_IRQ11                  193
+#define MD_IRQID_NRL2_HRT                           194
+#define MD_IRQID_NRL2_NOTIF                         195
+#define MD_IRQID_NRL2_EXCEP                         196
+#define MD_IRQID_NRL2_DPMAIF_MD                     197
+#define MD_IRQID_RXDFE_IRQ0                         198
+#define MD_IRQID_IDC_UART_TX_FORCE_ON               199
+#define MD_IRQID_RXDFE_IRQ2                         200
+#define MD_IRQID_RXDFE_IRQ3                         201
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_0              202
+#define MD_IRQID_MD_RXDFE_BB_DUMP                   203
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_1              204
+#define MD_IRQID_TXCRP                              205
+#define MD_IRQID_CM_NR_IRQ                          206
+#define MD_IRQID_CM_NR_ERR_IRQ                      207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ                   208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0      209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1      210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2      211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3      212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4      213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5      214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6      215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7      216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8      217
+#define MD_IRQID_D_GDMA_0_IRQ                       218
+#define MD_IRQID_D_GDMA_1_IRQ                       219
+#define MD_IRQID_D_GDMA_2_IRQ                       220
+#define MD_IRQID_D_GDMA_3_IRQ                       221
+#define MD_IRQID_D_GDMA_4_IRQ                       222
+#define MD_IRQID_D_GDMA_5_IRQ                       223
+#define MD_IRQID_PLL_GEARHP_RDY                     224
+#define MD_IRQID_REQ_ABNORM_IRQ                     225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU                  226
+#define MD_IRQID_AP2MD_APWDT_IRQ                    227
+#define MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ            228
+#define MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ             229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5                230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ               231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0                 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1                 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2                 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3                 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4                 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5                 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6                 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7                 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6                240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ                  241
+#define MD_IRQID_TDD_WAKEUP_IRQ                     242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ                243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ                244
+#define MD_IRQID_RTR_SLT_0_IRQ                      245
+#define MD_IRQID_RTR_SLT_1_IRQ                      246
+#define MD_IRQID_FDD_SLP_IRQ                        247
+#define MD_IRQID_IRDBG_MCU_INT                      248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0                 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1                 250
+#define MD_IRQID_NR_SLP_WAKEUP                      251
+#define MD_IRQID_NR_SLP_SLEEP                       252
+#define MD_IRQID_NR_TIMER_ERR                       253
+#define MD_IRQID_TXBSRP                             254
+#define MD_IRQID_TXDFE_D                            255
+#define MD_IRQID_NR_EVENTGEN_ERR                    256
+#define MD_IRQID_AIRQ_PAD                           257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ                   258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ                   259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ                   260
+#define MD_IRQID_CSSYS_1X_CS_IRQ                    261
+#define MD_IRQID_CSSYS_DO_CS_IRQ                    262
+#define MD_IRQID_PCIE_INTERRUPT_OUT                 263
+#define MD_IRQID_UCNT_SCH_IRQ                       264
+#define MD_IRQID_UCNT_ERR_IRQ                       265
+#define MD_IRQID_UCNT_ADJ_IRQ                       266
+#define MD_IRQID_SL_WAITSLEEP                       267
+#define MD_IRQID_PTP_THERM_INT_INT                  268
+#define MD_IRQID_PTP_FSM_INT                        269
+#define MD_IRQID_AP2MD_DAPC                         270
+#define MD_IRQID_AP2MD_CCIF2                        271
+#define MD_IRQID_AP2MD_UFS                          272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT                273
+#define MD_IRQID_AP2MD_MSDC0                        274
+#define MD_IRQID_MIPI_IRQ                           275
+#define MD_IRQID_CONN_BT_ISOCH                      276
+#define MD_IRQID_RMPU_CTIREIGIN                     277
+#define MD_IRQID_FREQM_IRQ                          278
+#define MD_IRQID_BT_CVSD                            279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0              280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1              281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2              282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3              283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4              284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5              285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6              286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7              287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8              288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9              289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10             290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11             291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12             292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13             293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14             294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15             295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16             296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17             297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18             298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19             299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20             300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21             301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22             302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23             303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24             304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25             305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26             306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27             307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28             308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29             309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30             310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31             311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32             312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33             313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34             314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35             315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36             316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37             317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38             318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39             319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40             320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41             321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42             322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43             323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44             324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45             325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46             326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47             327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48             328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49             329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50             330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51             331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52             332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53             333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54             334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55             335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56             336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57             337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58             338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59             339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60             340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61             341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62             342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63             343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64             344
+#define MD_IRQID_CLDMA0_MD_IRQ                      345
+#define MD_IRQID_CLDMA1_MD_IRQ                      346
+#define MD_IRQID_CLDMA2_MD_IRQ                      347
+#define MD_IRQID_CLDMA3_MD_IRQ                      348
+#define MD_IRQID_MHCCIF_SAP2USIP_IRQ                349
+#define MD_IRQID_MHCCIF_SAP2MDMCU_IRQ               350
+#define MD_IRQID_NFI_MD                             351
+#define MD_IRQID_CLDMA1_AP_INT_PCIE_MD              352
+#define MD_IRQID_CLDMA3_AP_INT_PCIE_MD              353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17               354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18               355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19               356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20               357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21               358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22               359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23               360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24               361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25               362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26               363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27               364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28               365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29               366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30               367
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __CHIP10992_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6297.h b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6297.h
new file mode 100644
index 0000000..d7de046
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6297.h
@@ -0,0 +1,387 @@
+#ifndef __MT6297_IRQID_H__
+#define __MT6297_IRQID_H__
+
+
+//Gen97 IRQID
+#define MD_IRQID_USIM0       	                      0
+#define MD_IRQID_USIM1       	                      1
+#define MD_IRQID_TDMA_CTIRQ1	                      2
+#define MD_IRQID_TDMA_CTIRQ2	                      3
+#define MD_IRQID_TDMA_CTIRQ3	                      4
+#define MD_IRQID_TDMA_WAKEUP_IRQ	                  5
+#define MD_IRQID_OST          	                      6
+#define MD_IRQID_MDRTT	                              7
+#define MD_IRQID_MDEVDO	                              8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT	              9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT	             10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT	             11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT	             12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT	             13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT	             14
+#define MD_IRQID_SHARE_D12MINT1	                     15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ	         16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ	         17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ	         18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ	         19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ	         20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ	         21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ	         22
+#define MD_IRQID_AIRQ_SERDES	                     23
+#define MD_IRQID_AIRQ_COS                            24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR	         25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR            26
+#define MD_IRQID_PPPHA_ENC0_INT                      27
+#define MD_IRQID_PPPHA_ENC1_INT                      28
+#define MD_IRQID_PPPHA_DEC0_INT                      29
+#define MD_IRQID_PPPHA_DEC1_INT                      30
+#define MD_IRQID_CS_NR_IRQ                           31
+#define MD_IRQID_CS_NR_ERR_IRQ                       32
+#define MD_IRQID_SDF_OVERFLOW_IRQ                    33
+#define MD_IRQID_MCUMMU_INT                          34
+#define MD_IRQID_BIGRAM_0_IRQ_0                      35
+#define MD_IRQID_COS_PREP_INT                        36
+#define MD_IRQID_TRACE_INT                           37
+#define MD_IRQID_NR_TIMER_IRQ0                       38
+#define MD_IRQID_NR_TIMER_IRQ1                       39
+#define MD_IRQID_NR_TIMER_IRQ2                       40
+#define MD_IRQID_NR_TIMER_IRQ3                       41
+#define MD_IRQID_NR_TIMER_IRQ4                       42
+#define MD_IRQID_NR_TIMER_IRQ5                       43
+#define MD_IRQID_NR_TIMER_IRQ6                       44
+#define MD_IRQID_NR_TIMER_IRQ7                       45
+#define MD_IRQID_NR_TIMER_IRQ8                       46
+#define MD_IRQID_NR_TIMER_IRQ9                       47
+#define MD_IRQID_NR_TIMER_IRQ10                      48
+#define MD_IRQID_NR_TIMER_IRQ11                      49
+#define MD_IRQID_NR_TIMER_IRQ12                      50
+#define MD_IRQID_NR_TIMER_IRQ13                      51
+#define MD_IRQID_NR_TIMER_IRQ14                      52
+#define MD_IRQID_NR_TIMER_IRQ15                      53
+#define MD_IRQID_NR_TIMER_IRQ16                      54
+#define MD_IRQID_NR_TIMER_IRQ17                      55
+#define MD_IRQID_NR_TIMER_IRQ18                      56
+#define MD_IRQID_NR_TIMER_IRQ19                      57
+#define MD_IRQID_NR_TIMER_IRQ20                      58
+#define MD_IRQID_NR_TIMER_IRQ21                      59
+#define MD_IRQID_NR_TIMER_IRQ22                      60
+#define MD_IRQID_NR_TIMER_IRQ23                      61
+#define MD_IRQID_NR_TIMER_IRQ24                      62
+#define MD_IRQID_NR_TIMER_IRQ25                      63
+#define MD_IRQID_NR_TIMER_IRQ26                      64
+#define MD_IRQID_NR_TIMER_IRQ27                      65
+#define MD_IRQID_NR_TIMER_IRQ28                      66
+#define MD_IRQID_NR_TIMER_IRQ29                      67
+#define MD_IRQID_NR_TIMER_IRQ30                      68
+#define MD_IRQID_NR_TIMER_IRQ31                      69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0           70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1           71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2           72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3           73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4           74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5           75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6           76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7           77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8           78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9           79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10          80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11          81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12          82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13          83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14          84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15          85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16          86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17          87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0                 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1                 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2                 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3                 91
+#define MD_IRQID_NR_EVENTGEN_SPU                     92
+#define MD_IRQID_SI_CM_ERR                           93
+#define MD_IRQID_SI_CM_PCINT                         94
+#define MD_IRQID_MDM2C_U3G                           95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0                 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1                 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ                98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ                99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ                100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS             101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS           102
+#define MD_IRQID_ELMTOP_EMI_IRQ                     103
+#define MD_IRQID_ELM_DMA_IRQ                        104
+#define MD_IRQID_BUSMPU_IRQ                         105
+#define MD_IRQID_ST1X_CPINT                         106
+#define MD_IRQID_ST1x_HALF_CPINT                    107
+#define MD_IRQID_ST1x_CFG_CPINT                     108
+#define MD_IRQID_ST1x_WAKEUP_IRQ                    109
+#define MD_IRQID_STDO_CPINT                         110
+#define MD_IRQID_STDO_HALF_CPINT                    111
+#define MD_IRQID_STDO_CFG_CPINT                     112
+#define MD_IRQID_STDO_WAKEUP_IRQ                    113
+#define MD_IRQID_UART_MD0                           114
+#define MD_IRQID_UART_MD1                           115
+#define MD_IRQID_EINT0                              116
+#define MD_IRQID_EINT1                              117
+#define MD_IRQID_EINT2                              118
+#define MD_IRQID_EINT3                              119
+#define MD_IRQID_EINT_SHARE                         120
+#define MD_IRQID_GPTM1                              121
+#define MD_IRQID_GPTM2                              122
+#define MD_IRQID_GPTM3                              123
+#define MD_IRQID_GPTM4                              124
+#define MD_IRQID_GPTM5                              125
+#define MD_IRQID_GPTM6                              126
+#define MD_IRQID_GPTM7                              127
+#define MD_IRQID_GPTM8                              128
+#define MD_IRQID_GPTM9                              129
+#define MD_IRQID_GPTM10                             130
+#define MD_IRQID_GPTM11                             131
+#define MD_IRQID_IDC_PM_INT                         132
+#define MD_IRQID_IDC_UART_IRQ                       133
+#define MD_IRQID_DUMMY_PRIORITY_IRQ0                134
+#define MD_IRQID_CLDMA0_MD_IRQ                      135
+#define MD_IRQID_DUMMY_PRIORITY_IRQ1                136
+#define MD_IRQID_CLDMA1_MD_IRQ                      137
+#define MD_IRQID_MDINFRA_BUS_DECERROR               138
+#define MD_IRQID_I2C_TOP_INT                        139
+#define MD_IRQID_SOE                                140
+#define MD_IRQID_ABM_INT                            141
+#define MD_IRQID_ABM_ERROR_INT                      142
+#define MD_IRQID_USIP0                              143
+#define MD_IRQID_USIP1                              144
+#define MD_IRQID_USIP2                              145
+#define MD_IRQID_USIP3                              146
+#define MD_IRQID_USIP4                              147
+#define MD_IRQID_USIP5                              148
+#define MD_IRQID_USIP6                              149
+#define MD_IRQID_USIP7                              150
+#define MD_IRQID_USIP8                              151
+#define MD_IRQID_USIP9                              152
+#define MD_IRQID_USIP10                             153
+#define MD_IRQID_USIP11                             154
+#define MD_IRQID_USIP12                             155
+#define MD_IRQID_USIP13                             156
+#define MD_IRQID_TX_NR_CC0_IRQ                      157
+#define MD_IRQID_TX_NR_CC1_IRQ                      158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ                   159
+#define MD_IRQID_MDMCU_SPU_IRQ                      160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE                 161
+#define MD_IRQID_ECT                                162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ               163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE                164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE              165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ           166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ     167
+#define MD_IRQID_MCORE1_MML1_DSPPMU_TOP_EMI_IRQ     168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ     169
+#define MD_IRQID_VCORE1_MML1_DSPPMU_TOP_EMI_IRQ     170
+#define MD_IRQID_MDWDT                              171
+#define MD_IRQID_MDGDMA0                            172
+#define MD_IRQID_MDGDMA1                            173
+#define MD_IRQID_MDGDMA2                            174
+#define MD_IRQID_MDGDMA3                            175
+#define MD_IRQID_MDGDMA4                            176
+#define MD_IRQID_MDGDMA5                            177
+#define MD_IRQID_AP2MD_CCIF0_0                      178
+#define MD_IRQID_AP2MD_CCIF0_1                      179
+#define MD_IRQID_AP2MD_CCIF1_0                      180
+#define MD_IRQID_AP2MD_CCIF1_1                      181
+#define MD_IRQID_IEBIT_CHECK_IRQ0                   182
+#define MD_IRQID_IEBIT_CHECK_IRQ1                   183
+#define MD_IRQID_IEBIT_CHECK_IRQ2                   184
+#define MD_IRQID_IEBIT_CHECK_IRQ3                   185
+#define MD_IRQID_IEBIT_CHECK_IRQ4                   186
+#define MD_IRQID_IEBIT_CHECK_IRQ5                   187
+#define MD_IRQID_IEBIT_CHECK_IRQ6                   188
+#define MD_IRQID_IEBIT_CHECK_IRQ7                   189
+#define MD_IRQID_IEBIT_CHECK_IRQ8                   190
+#define MD_IRQID_IEBIT_CHECK_IRQ9                   191
+#define MD_IRQID_IEBIT_CHECK_IRQ10                  192
+#define MD_IRQID_IEBIT_CHECK_IRQ11                  193
+#define MD_IRQID_NRL2_HRT                           194
+#define MD_IRQID_NRL2_NOTIF                         195
+#define MD_IRQID_NRL2_EXCEP                         196
+#define MD_IRQID_NRL2_DPMAIF_MD                     197
+#define MD_IRQID_RXDFE_IRQ0                         198
+#define MD_IRQID_RXDFE_IRQ1                         199
+#define MD_IRQID_RXDFE_IRQ2                         200
+#define MD_IRQID_RXDFE_IRQ3                         201
+#define MD_IRQID_RXDFE_IRQ4                         202
+#define MD_IRQID_MD_RXDFE_BB_DUMP                   203
+#define MD_IRQID_RXDFE_IRQ6                         204
+#define MD_IRQID_TXCRP                              205
+#define MD_IRQID_CM_NR_IRQ                          206
+#define MD_IRQID_CM_NR_ERR_IRQ                      207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ                   208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0      209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1      210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2      211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3      212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4      213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5      214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6      215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7      216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8      217
+#define MD_IRQID_D_GDMA_0_IRQ                       218
+#define MD_IRQID_D_GDMA_1_IRQ                       219
+#define MD_IRQID_D_GDMA_2_IRQ                       220
+#define MD_IRQID_D_GDMA_3_IRQ                       221
+#define MD_IRQID_D_GDMA_4_IRQ                       222
+#define MD_IRQID_D_GDMA_5_IRQ                       223
+#define MD_IRQID_PLL_GEARHP_RDY                     224
+#define MD_IRQID_REQ_ABNORM_IRQ                     225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU                  226
+#define MD_IRQID_AP2MD_APWDT_IRQ                    227
+#define MD_IRQID_DUMMY_PRIORITY_IRQ3                228
+#define MD_IRQID_DUMMY_PRIORITY_IRQ4                229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5                230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ               231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0                 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1                 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2                 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3                 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4                 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5                 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6                 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7                 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6                240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ                  241
+#define MD_IRQID_TDD_WAKEUP_IRQ                     242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ                243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ                244
+#define MD_IRQID_RTR_SLT_0_IRQ                      245
+#define MD_IRQID_RTR_SLT_1_IRQ                      246
+#define MD_IRQID_FDD_SLP_IRQ                        247
+#define MD_IRQID_IRDBG_MCU_INT                      248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0                 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1                 250
+#define MD_IRQID_NR_SLP_WAKEUP                      251
+#define MD_IRQID_NR_SLP_SLEEP                       252
+#define MD_IRQID_NR_TIMER_ERR                       253
+#define MD_IRQID_TXBSRP                             254
+#define MD_IRQID_TXDFE_D                            255
+#define MD_IRQID_NR_EVENTGEN_ERR                    256
+#define MD_IRQID_AIRQ_PAD                           257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ                   258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ                   259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ                   260
+#define MD_IRQID_CSSYS_1X_CS_IRQ                    261
+#define MD_IRQID_CSSYS_DO_CS_IRQ                    262
+#define MD_IRQID_PCIE_INTERRUPT_OUT                 263
+#define MD_IRQID_UCNT_SCH_IRQ                       264
+#define MD_IRQID_UCNT_ERR_IRQ                       265
+#define MD_IRQID_UCNT_ADJ_IRQ                       266
+#define MD_IRQID_NFI_MD                             267
+#define MD_IRQID_PTP_THERM_INT_INT                  268
+#define MD_IRQID_PTP_FSM_INT                        269
+#define MD_IRQID_MHCCIF_SAP2USIP_IRQ                270
+#define MD_IRQID_MHCCIF_SAP2MDMCU_IRQ               271
+#define MD_IRQID_MUSB_INTERRUPT_OUT                 272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT                273
+#define MD_IRQID_AP2MD_MSDC0                        274
+#define MD_IRQID_MIPI_READ_IRQ                      275
+#define MD_IRQID_CLDMA2_MD_IRQ                      276
+#define MD_IRQID_RMPU_CTIREIGIN                     277
+#define MD_IRQID_FREQM_IRQ                          278
+#define MD_IRQID_DUMMY_PRIORITY_IRQ7                279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0              280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1              281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2              282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3              283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4              284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5              285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6              286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7              287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8              288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9              289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10             290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11             291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12             292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13             293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14             294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15             295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16             296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17             297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18             298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19             299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20             300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21             301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22             302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23             303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24             304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25             305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26             306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27             307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28             308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29             309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30             310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31             311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32             312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33             313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34             314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35             315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36             316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37             317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38             318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39             319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40             320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41             321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42             322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43             323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44             324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45             325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46             326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47             327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48             328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49             329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50             330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51             331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52             332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53             333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54             334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55             335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56             336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57             337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58             338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59             339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60             340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61             341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62             342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63             343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64             344
+#define MD_IRQID_DUMMY_PRIORITY_IRQ8                345
+#define MD_IRQID_DUMMY_PRIORITY_IRQ9                346
+#define MD_IRQID_DUMMY_PRIORITY_IRQ10               347
+#define MD_IRQID_DUMMY_PRIORITY_IRQ11               348
+#define MD_IRQID_DUMMY_PRIORITY_IRQ12               349
+#define MD_IRQID_DUMMY_PRIORITY_IRQ13               350
+#define MD_IRQID_DUMMY_PRIORITY_IRQ14               351
+#define MD_IRQID_DUMMY_PRIORITY_IRQ15               352
+#define MD_IRQID_DUMMY_PRIORITY_IRQ16               353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17               354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18               355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19               356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20               357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21               358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22               359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23               360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24               361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25               362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26               363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27               364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28               365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29               366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30               367
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6297_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6833.h b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6833.h
new file mode 100644
index 0000000..a7e7eb6
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6833.h
@@ -0,0 +1,388 @@
+#ifndef __MT6833_IRQID_H__
+#define __MT6833_IRQID_H__
+
+
+//MT6833 IRQID
+#define MD_IRQID_USIM0                                0
+#define MD_IRQID_USIM1                                1
+#define MD_IRQID_TDMA_CTIRQ1                          2
+#define MD_IRQID_TDMA_CTIRQ2                          3
+#define MD_IRQID_TDMA_CTIRQ3                          4
+#define MD_IRQID_TDMA_WAKEUP_IRQ                      5
+#define MD_IRQID_OST                                  6
+#define MD_IRQID_MDRTT                                7
+#define MD_IRQID_MDEVDO                               8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT                  9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT                 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT               11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT               12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT               13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT               14
+#define MD_IRQID_SHARE_D12MINT1                      15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ          16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ          17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ          18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ          19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ          20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ          21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ           22
+#define MD_IRQID_AIRQ_SERDES                         23
+#define MD_IRQID_AIRQ_COS                            24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR            25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR            26
+#define MD_IRQID_PPPHA_ENC0_INT                      27
+#define MD_IRQID_PPPHA_ENC1_INT                      28
+#define MD_IRQID_PPPHA_DEC0_INT                      29
+#define MD_IRQID_PPPHA_DEC1_INT                      30
+#define MD_IRQID_CS_NR_IRQ                           31
+#define MD_IRQID_CS_NR_ERR_IRQ                       32
+#define MD_IRQID_SDF_OVERFLOW_IRQ                    33
+#define MD_IRQID_MCUMMU_INT                          34
+#define MD_IRQID_BIGRAM_0_IRQ_0                      35
+#define MD_IRQID_COS_PREP_INT                        36
+#define MD_IRQID_TRACE_INT                           37
+#define MD_IRQID_NR_TIMER_IRQ0                       38
+#define MD_IRQID_NR_TIMER_IRQ1                       39
+#define MD_IRQID_NR_TIMER_IRQ2                       40
+#define MD_IRQID_NR_TIMER_IRQ3                       41
+#define MD_IRQID_NR_TIMER_IRQ4                       42
+#define MD_IRQID_NR_TIMER_IRQ5                       43
+#define MD_IRQID_NR_TIMER_IRQ6                       44
+#define MD_IRQID_NR_TIMER_IRQ7                       45
+#define MD_IRQID_NR_TIMER_IRQ8                       46
+#define MD_IRQID_NR_TIMER_IRQ9                       47
+#define MD_IRQID_NR_TIMER_IRQ10                      48
+#define MD_IRQID_NR_TIMER_IRQ11                      49
+#define MD_IRQID_NR_TIMER_IRQ12                      50
+#define MD_IRQID_NR_TIMER_IRQ13                      51
+#define MD_IRQID_NR_TIMER_IRQ14                      52
+#define MD_IRQID_NR_TIMER_IRQ15                      53
+#define MD_IRQID_NR_TIMER_IRQ16                      54
+#define MD_IRQID_NR_TIMER_IRQ17                      55
+#define MD_IRQID_NR_TIMER_IRQ18                      56
+#define MD_IRQID_NR_TIMER_IRQ19                      57
+#define MD_IRQID_NR_TIMER_IRQ20                      58
+#define MD_IRQID_NR_TIMER_IRQ21                      59
+#define MD_IRQID_NR_TIMER_IRQ22                      60
+#define MD_IRQID_NR_TIMER_IRQ23                      61
+#define MD_IRQID_NR_TIMER_IRQ24                      62
+#define MD_IRQID_NR_TIMER_IRQ25                      63
+#define MD_IRQID_NR_TIMER_IRQ26                      64
+#define MD_IRQID_NR_TIMER_IRQ27                      65
+#define MD_IRQID_NR_TIMER_IRQ28                      66
+#define MD_IRQID_NR_TIMER_IRQ29                      67
+#define MD_IRQID_NR_TIMER_IRQ30                      68
+#define MD_IRQID_NR_TIMER_IRQ31                      69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0           70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1           71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2           72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3           73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4           74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5           75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6           76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7           77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8           78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9           79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10          80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11          81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12          82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13          83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14          84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15          85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16          86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17          87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0                 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1                 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2                 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3                 91
+#define MD_IRQID_NR_EVENTGEN_SPU                     92
+#define MD_IRQID_SI_CM_ERR                           93
+#define MD_IRQID_SI_CM_PCINT                         94
+#define MD_IRQID_MDM2C_U3G                           95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0                 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1                 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ                98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ                99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ                100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS             101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS           102
+#define MD_IRQID_ELMTOP_EMI_IRQ                     103
+#define MD_IRQID_ELM_DMA_IRQ                        104
+#define MD_IRQID_BUSMPU_IRQ                         105
+#define MD_IRQID_ST1X_CPINT                         106
+#define MD_IRQID_ST1x_HALF_CPINT                    107
+#define MD_IRQID_ST1x_CFG_CPINT                     108
+#define MD_IRQID_ST1x_WAKEUP_IRQ                    109
+#define MD_IRQID_STDO_CPINT                         110
+#define MD_IRQID_STDO_HALF_CPINT                    111
+#define MD_IRQID_STDO_CFG_CPINT                     112
+#define MD_IRQID_STDO_WAKEUP_IRQ                    113
+#define MD_IRQID_UART_MD0                           114
+#define MD_IRQID_UART_MD1                           115
+#define MD_IRQID_EINT0                              116
+#define MD_IRQID_EINT1                              117
+#define MD_IRQID_EINT2                              118
+#define MD_IRQID_EINT3                              119
+#define MD_IRQID_EINT_SHARE                         120
+#define MD_IRQID_GPTM1                              121
+#define MD_IRQID_GPTM2                              122
+#define MD_IRQID_GPTM3                              123
+#define MD_IRQID_GPTM4                              124
+#define MD_IRQID_GPTM5                              125
+#define MD_IRQID_GPTM6                              126
+#define MD_IRQID_GPTM7                              127
+#define MD_IRQID_GPTM8                              128
+#define MD_IRQID_GPTM9                              129
+#define MD_IRQID_GPTM10                             130
+#define MD_IRQID_GPTM11                             131
+#define MD_IRQID_IDC_PM_INT                         132
+#define MD_IRQID_IDC_UART_IRQ                       133
+#define MD_IRQID_MDGDMA_FDMA5                       134
+#define MD_IRQID_MDGDMA_FDMA6                       135
+#define MD_IRQID_TDMA_CTIRQ4                        136
+#define MD_IRQID_PDMA                               137
+#define MD_IRQID_MDINFRA_BUS_DECERROR               138
+#define MD_IRQID_I2C_TOP_INT                        139
+#define MD_IRQID_SOE                                140
+#define MD_IRQID_ABM_INT                            141
+#define MD_IRQID_ABM_ERROR_INT                      142
+#define MD_IRQID_USIP0                              143
+#define MD_IRQID_USIP1                              144
+#define MD_IRQID_USIP2                              145
+#define MD_IRQID_USIP3                              146
+#define MD_IRQID_USIP4                              147
+#define MD_IRQID_USIP5                              148
+#define MD_IRQID_USIP6                              149
+#define MD_IRQID_USIP7                              150
+#define MD_IRQID_USIP8                              151
+#define MD_IRQID_USIP9                              152
+#define MD_IRQID_USIP10                             153
+#define MD_IRQID_USIP11                             154
+#define MD_IRQID_USIP12                             155
+#define MD_IRQID_USIP13                             156
+#define MD_IRQID_TX_NR_CC0_IRQ                      157
+#define MD_IRQID_TX_NR_CC1_IRQ                      158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ                   159
+#define MD_IRQID_MDMCU_SPU_IRQ                      160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE                 161
+#define MD_IRQID_ECT                                162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ               163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE                164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE              165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ           166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ     167
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_0               168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ     169
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_1               170
+#define MD_IRQID_MDWDT                              171
+#define MD_IRQID_MDGDMA_FDMA0_2                     172
+#define MD_IRQID_MDGDMA_FDMA1                       173
+#define MD_IRQID_MDGDMA_FDMA3                       174
+#define MD_IRQID_MDGDMA_FDMA4                       175
+#define MD_IRQID_MDGDMA_HDMA0_1                     176
+#define MD_IRQID_MDGDMA_HDMA2_3                     177
+#define MD_IRQID_AP2MD_CCIF0_0                      178
+#define MD_IRQID_AP2MD_CCIF0_1                      179
+#define MD_IRQID_AP2MD_CCIF1_0                      180
+#define MD_IRQID_AP2MD_CCIF1_1                      181
+#define MD_IRQID_IEBIT_CHECK_IRQ0                   182
+#define MD_IRQID_IEBIT_CHECK_IRQ1                   183
+#define MD_IRQID_IEBIT_CHECK_IRQ2                   184
+#define MD_IRQID_IEBIT_CHECK_IRQ3                   185
+#define MD_IRQID_IEBIT_CHECK_IRQ4                   186
+#define MD_IRQID_IEBIT_CHECK_IRQ5                   187
+#define MD_IRQID_IEBIT_CHECK_IRQ6                   188
+#define MD_IRQID_IEBIT_CHECK_IRQ7                   189
+#define MD_IRQID_IEBIT_CHECK_IRQ8                   190
+#define MD_IRQID_IEBIT_CHECK_IRQ9                   191
+#define MD_IRQID_IEBIT_CHECK_IRQ10                  192
+#define MD_IRQID_IEBIT_CHECK_IRQ11                  193
+#define MD_IRQID_NRL2_HRT                           194
+#define MD_IRQID_NRL2_NOTIF                         195
+#define MD_IRQID_NRL2_EXCEP                         196
+#define MD_IRQID_NRL2_DPMAIF_MD                     197
+#define MD_IRQID_RXDFE_IRQ0                         198
+#define MD_IRQID_IDC_UART_TX_FORCE_ON               199
+#define MD_IRQID_RXDFE_IRQ2                         200
+#define MD_IRQID_RXDFE_IRQ3                         201
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_0              202
+#define MD_IRQID_MD_RXDFE_BB_DUMP                   203
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_1              204
+#define MD_IRQID_TXCRP                              205
+#define MD_IRQID_CM_NR_IRQ                          206
+#define MD_IRQID_CM_NR_ERR_IRQ                      207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ                   208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0      209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1      210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2      211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3      212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4      213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5      214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6      215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7      216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8      217
+#define MD_IRQID_D_GDMA_0_IRQ                       218
+#define MD_IRQID_D_GDMA_1_IRQ                       219
+#define MD_IRQID_D_GDMA_2_IRQ                       220
+#define MD_IRQID_D_GDMA_3_IRQ                       221
+#define MD_IRQID_D_GDMA_4_IRQ                       222
+#define MD_IRQID_D_GDMA_5_IRQ                       223
+#define MD_IRQID_PLL_GEARHP_RDY                     224
+#define MD_IRQID_REQ_ABNORM_IRQ                     225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU                  226
+#define MD_IRQID_AP2MD_APWDT_IRQ                    227
+#define MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ            228
+#define MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ             229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5                230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ               231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0                 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1                 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2                 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3                 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4                 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5                 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6                 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7                 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6                240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ                  241
+#define MD_IRQID_TDD_WAKEUP_IRQ                     242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ                243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ                244
+#define MD_IRQID_RTR_SLT_0_IRQ                      245
+#define MD_IRQID_RTR_SLT_1_IRQ                      246
+#define MD_IRQID_FDD_SLP_IRQ                        247
+#define MD_IRQID_IRDBG_MCU_INT                      248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0                 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1                 250
+#define MD_IRQID_NR_SLP_WAKEUP                      251
+#define MD_IRQID_NR_SLP_SLEEP                       252
+#define MD_IRQID_NR_TIMER_ERR                       253
+#define MD_IRQID_TXBSRP                             254
+#define MD_IRQID_TXDFE_D                            255
+#define MD_IRQID_NR_EVENTGEN_ERR                    256
+#define MD_IRQID_AIRQ_PAD                           257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ                   258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ                   259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ                   260
+#define MD_IRQID_CSSYS_1X_CS_IRQ                    261
+#define MD_IRQID_CSSYS_DO_CS_IRQ                    262
+#define MD_IRQID_PCIE_INTERRUPT_OUT                 263
+#define MD_IRQID_UCNT_SCH_IRQ                       264
+#define MD_IRQID_UCNT_ERR_IRQ                       265
+#define MD_IRQID_UCNT_ADJ_IRQ                       266
+#define MD_IRQID_SL_WAITSLEEP                       267
+#define MD_IRQID_PTP_THERM_INT_INT                  268
+#define MD_IRQID_PTP_FSM_INT                        269
+#define MD_IRQID_AP2MD_DAPC                         270
+#define MD_IRQID_AP2MD_CCIF2                        271
+#define MD_IRQID_AP2MD_UFS                          272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT                273
+#define MD_IRQID_AP2MD_MSDC0                        274
+#define MD_IRQID_MIPI_IRQ                           275
+#define MD_IRQID_CONN_BT_ISOCH                      276
+#define MD_IRQID_RMPU_CTIREIGIN                     277
+#define MD_IRQID_FREQM_IRQ                          278
+#define MD_IRQID_BT_CVSD                            279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0              280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1              281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2              282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3              283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4              284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5              285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6              286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7              287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8              288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9              289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10             290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11             291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12             292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13             293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14             294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15             295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16             296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17             297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18             298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19             299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20             300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21             301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22             302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23             303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24             304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25             305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26             306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27             307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28             308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29             309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30             310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31             311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32             312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33             313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34             314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35             315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36             316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37             317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38             318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39             319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40             320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41             321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42             322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43             323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44             324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45             325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46             326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47             327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48             328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49             329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50             330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51             331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52             332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53             333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54             334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55             335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56             336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57             337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58             338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59             339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60             340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61             341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62             342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63             343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64             344
+#define MD_IRQID_DUMMY_PRIORITY_IRQ8                345
+#define MD_IRQID_DUMMY_PRIORITY_IRQ9                346
+#define MD_IRQID_DUMMY_PRIORITY_IRQ10               347
+#define MD_IRQID_DUMMY_PRIORITY_IRQ11               348
+#define MD_IRQID_DUMMY_PRIORITY_IRQ12               349
+#define MD_IRQID_DUMMY_PRIORITY_IRQ13               350
+#define MD_IRQID_DUMMY_PRIORITY_IRQ14               351
+#define MD_IRQID_DUMMY_PRIORITY_IRQ15               352
+#define MD_IRQID_DUMMY_PRIORITY_IRQ16               353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17               354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18               355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19               356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20               357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21               358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22               359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23               360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24               361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25               362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26               363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27               364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28               365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29               366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30               367
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6833_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6853.h b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6853.h
new file mode 100644
index 0000000..276b39e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6853.h
@@ -0,0 +1,388 @@
+#ifndef __MT6853_IRQID_H__
+#define __MT6853_IRQID_H__
+
+
+//MT6853 IRQID
+#define MD_IRQID_USIM0                                0
+#define MD_IRQID_USIM1                                1
+#define MD_IRQID_TDMA_CTIRQ1                          2
+#define MD_IRQID_TDMA_CTIRQ2                          3
+#define MD_IRQID_TDMA_CTIRQ3                          4
+#define MD_IRQID_TDMA_WAKEUP_IRQ                      5
+#define MD_IRQID_OST                                  6
+#define MD_IRQID_MDRTT                                7
+#define MD_IRQID_MDEVDO                               8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT                  9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT                 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT               11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT               12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT               13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT               14
+#define MD_IRQID_SHARE_D12MINT1                      15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ          16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ          17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ          18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ          19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ          20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ          21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ           22
+#define MD_IRQID_AIRQ_SERDES                         23
+#define MD_IRQID_AIRQ_COS                            24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR            25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR            26
+#define MD_IRQID_PPPHA_ENC0_INT                      27
+#define MD_IRQID_PPPHA_ENC1_INT                      28
+#define MD_IRQID_PPPHA_DEC0_INT                      29
+#define MD_IRQID_PPPHA_DEC1_INT                      30
+#define MD_IRQID_CS_NR_IRQ                           31
+#define MD_IRQID_CS_NR_ERR_IRQ                       32
+#define MD_IRQID_SDF_OVERFLOW_IRQ                    33
+#define MD_IRQID_MCUMMU_INT                          34
+#define MD_IRQID_BIGRAM_0_IRQ_0                      35
+#define MD_IRQID_COS_PREP_INT                        36
+#define MD_IRQID_TRACE_INT                           37
+#define MD_IRQID_NR_TIMER_IRQ0                       38
+#define MD_IRQID_NR_TIMER_IRQ1                       39
+#define MD_IRQID_NR_TIMER_IRQ2                       40
+#define MD_IRQID_NR_TIMER_IRQ3                       41
+#define MD_IRQID_NR_TIMER_IRQ4                       42
+#define MD_IRQID_NR_TIMER_IRQ5                       43
+#define MD_IRQID_NR_TIMER_IRQ6                       44
+#define MD_IRQID_NR_TIMER_IRQ7                       45
+#define MD_IRQID_NR_TIMER_IRQ8                       46
+#define MD_IRQID_NR_TIMER_IRQ9                       47
+#define MD_IRQID_NR_TIMER_IRQ10                      48
+#define MD_IRQID_NR_TIMER_IRQ11                      49
+#define MD_IRQID_NR_TIMER_IRQ12                      50
+#define MD_IRQID_NR_TIMER_IRQ13                      51
+#define MD_IRQID_NR_TIMER_IRQ14                      52
+#define MD_IRQID_NR_TIMER_IRQ15                      53
+#define MD_IRQID_NR_TIMER_IRQ16                      54
+#define MD_IRQID_NR_TIMER_IRQ17                      55
+#define MD_IRQID_NR_TIMER_IRQ18                      56
+#define MD_IRQID_NR_TIMER_IRQ19                      57
+#define MD_IRQID_NR_TIMER_IRQ20                      58
+#define MD_IRQID_NR_TIMER_IRQ21                      59
+#define MD_IRQID_NR_TIMER_IRQ22                      60
+#define MD_IRQID_NR_TIMER_IRQ23                      61
+#define MD_IRQID_NR_TIMER_IRQ24                      62
+#define MD_IRQID_NR_TIMER_IRQ25                      63
+#define MD_IRQID_NR_TIMER_IRQ26                      64
+#define MD_IRQID_NR_TIMER_IRQ27                      65
+#define MD_IRQID_NR_TIMER_IRQ28                      66
+#define MD_IRQID_NR_TIMER_IRQ29                      67
+#define MD_IRQID_NR_TIMER_IRQ30                      68
+#define MD_IRQID_NR_TIMER_IRQ31                      69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0           70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1           71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2           72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3           73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4           74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5           75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6           76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7           77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8           78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9           79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10          80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11          81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12          82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13          83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14          84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15          85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16          86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17          87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0                 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1                 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2                 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3                 91
+#define MD_IRQID_NR_EVENTGEN_SPU                     92
+#define MD_IRQID_SI_CM_ERR                           93
+#define MD_IRQID_SI_CM_PCINT                         94
+#define MD_IRQID_MDM2C_U3G                           95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0                 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1                 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ                98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ                99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ                100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS             101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS           102
+#define MD_IRQID_ELMTOP_EMI_IRQ                     103
+#define MD_IRQID_ELM_DMA_IRQ                        104
+#define MD_IRQID_BUSMPU_IRQ                         105
+#define MD_IRQID_ST1X_CPINT                         106
+#define MD_IRQID_ST1x_HALF_CPINT                    107
+#define MD_IRQID_ST1x_CFG_CPINT                     108
+#define MD_IRQID_ST1x_WAKEUP_IRQ                    109
+#define MD_IRQID_STDO_CPINT                         110
+#define MD_IRQID_STDO_HALF_CPINT                    111
+#define MD_IRQID_STDO_CFG_CPINT                     112
+#define MD_IRQID_STDO_WAKEUP_IRQ                    113
+#define MD_IRQID_UART_MD0                           114
+#define MD_IRQID_UART_MD1                           115
+#define MD_IRQID_EINT0                              116
+#define MD_IRQID_EINT1                              117
+#define MD_IRQID_EINT2                              118
+#define MD_IRQID_EINT3                              119
+#define MD_IRQID_EINT_SHARE                         120
+#define MD_IRQID_GPTM1                              121
+#define MD_IRQID_GPTM2                              122
+#define MD_IRQID_GPTM3                              123
+#define MD_IRQID_GPTM4                              124
+#define MD_IRQID_GPTM5                              125
+#define MD_IRQID_GPTM6                              126
+#define MD_IRQID_GPTM7                              127
+#define MD_IRQID_GPTM8                              128
+#define MD_IRQID_GPTM9                              129
+#define MD_IRQID_GPTM10                             130
+#define MD_IRQID_GPTM11                             131
+#define MD_IRQID_IDC_PM_INT                         132
+#define MD_IRQID_IDC_UART_IRQ                       133
+#define MD_IRQID_MDGDMA_FDMA5                       134
+#define MD_IRQID_MDGDMA_FDMA6                       135
+#define MD_IRQID_TDMA_CTIRQ4                        136
+#define MD_IRQID_PDMA                               137
+#define MD_IRQID_MDINFRA_BUS_DECERROR               138
+#define MD_IRQID_I2C_TOP_INT                        139
+#define MD_IRQID_SOE                                140
+#define MD_IRQID_ABM_INT                            141
+#define MD_IRQID_ABM_ERROR_INT                      142
+#define MD_IRQID_USIP0                              143
+#define MD_IRQID_USIP1                              144
+#define MD_IRQID_USIP2                              145
+#define MD_IRQID_USIP3                              146
+#define MD_IRQID_USIP4                              147
+#define MD_IRQID_USIP5                              148
+#define MD_IRQID_USIP6                              149
+#define MD_IRQID_USIP7                              150
+#define MD_IRQID_USIP8                              151
+#define MD_IRQID_USIP9                              152
+#define MD_IRQID_USIP10                             153
+#define MD_IRQID_USIP11                             154
+#define MD_IRQID_USIP12                             155
+#define MD_IRQID_USIP13                             156
+#define MD_IRQID_TX_NR_CC0_IRQ                      157
+#define MD_IRQID_TX_NR_CC1_IRQ                      158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ                   159
+#define MD_IRQID_MDMCU_SPU_IRQ                      160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE                 161
+#define MD_IRQID_ECT                                162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ               163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE                164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE              165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ           166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ     167
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_0               168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ     169
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_1               170
+#define MD_IRQID_MDWDT                              171
+#define MD_IRQID_MDGDMA_FDMA0_2                     172
+#define MD_IRQID_MDGDMA_FDMA1                       173
+#define MD_IRQID_MDGDMA_FDMA3                       174
+#define MD_IRQID_MDGDMA_FDMA4                       175
+#define MD_IRQID_MDGDMA_HDMA0_1                     176
+#define MD_IRQID_MDGDMA_HDMA2_3                     177
+#define MD_IRQID_AP2MD_CCIF0_0                      178
+#define MD_IRQID_AP2MD_CCIF0_1                      179
+#define MD_IRQID_AP2MD_CCIF1_0                      180
+#define MD_IRQID_AP2MD_CCIF1_1                      181
+#define MD_IRQID_IEBIT_CHECK_IRQ0                   182
+#define MD_IRQID_IEBIT_CHECK_IRQ1                   183
+#define MD_IRQID_IEBIT_CHECK_IRQ2                   184
+#define MD_IRQID_IEBIT_CHECK_IRQ3                   185
+#define MD_IRQID_IEBIT_CHECK_IRQ4                   186
+#define MD_IRQID_IEBIT_CHECK_IRQ5                   187
+#define MD_IRQID_IEBIT_CHECK_IRQ6                   188
+#define MD_IRQID_IEBIT_CHECK_IRQ7                   189
+#define MD_IRQID_IEBIT_CHECK_IRQ8                   190
+#define MD_IRQID_IEBIT_CHECK_IRQ9                   191
+#define MD_IRQID_IEBIT_CHECK_IRQ10                  192
+#define MD_IRQID_IEBIT_CHECK_IRQ11                  193
+#define MD_IRQID_NRL2_HRT                           194
+#define MD_IRQID_NRL2_NOTIF                         195
+#define MD_IRQID_NRL2_EXCEP                         196
+#define MD_IRQID_NRL2_DPMAIF_MD                     197
+#define MD_IRQID_RXDFE_IRQ0                         198
+#define MD_IRQID_IDC_UART_TX_FORCE_ON               199
+#define MD_IRQID_RXDFE_IRQ2                         200
+#define MD_IRQID_RXDFE_IRQ3                         201
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_0              202
+#define MD_IRQID_MD_RXDFE_BB_DUMP                   203
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_1              204
+#define MD_IRQID_TXCRP                              205
+#define MD_IRQID_CM_NR_IRQ                          206
+#define MD_IRQID_CM_NR_ERR_IRQ                      207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ                   208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0      209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1      210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2      211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3      212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4      213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5      214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6      215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7      216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8      217
+#define MD_IRQID_D_GDMA_0_IRQ                       218
+#define MD_IRQID_D_GDMA_1_IRQ                       219
+#define MD_IRQID_D_GDMA_2_IRQ                       220
+#define MD_IRQID_D_GDMA_3_IRQ                       221
+#define MD_IRQID_D_GDMA_4_IRQ                       222
+#define MD_IRQID_D_GDMA_5_IRQ                       223
+#define MD_IRQID_PLL_GEARHP_RDY                     224
+#define MD_IRQID_REQ_ABNORM_IRQ                     225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU                  226
+#define MD_IRQID_AP2MD_APWDT_IRQ                    227
+#define MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ            228
+#define MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ             229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5                230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ               231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0                 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1                 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2                 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3                 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4                 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5                 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6                 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7                 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6                240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ                  241
+#define MD_IRQID_TDD_WAKEUP_IRQ                     242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ                243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ                244
+#define MD_IRQID_RTR_SLT_0_IRQ                      245
+#define MD_IRQID_RTR_SLT_1_IRQ                      246
+#define MD_IRQID_FDD_SLP_IRQ                        247
+#define MD_IRQID_IRDBG_MCU_INT                      248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0                 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1                 250
+#define MD_IRQID_NR_SLP_WAKEUP                      251
+#define MD_IRQID_NR_SLP_SLEEP                       252
+#define MD_IRQID_NR_TIMER_ERR                       253
+#define MD_IRQID_TXBSRP                             254
+#define MD_IRQID_TXDFE_D                            255
+#define MD_IRQID_NR_EVENTGEN_ERR                    256
+#define MD_IRQID_AIRQ_PAD                           257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ                   258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ                   259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ                   260
+#define MD_IRQID_CSSYS_1X_CS_IRQ                    261
+#define MD_IRQID_CSSYS_DO_CS_IRQ                    262
+#define MD_IRQID_PCIE_INTERRUPT_OUT                 263
+#define MD_IRQID_UCNT_SCH_IRQ                       264
+#define MD_IRQID_UCNT_ERR_IRQ                       265
+#define MD_IRQID_UCNT_ADJ_IRQ                       266
+#define MD_IRQID_SL_WAITSLEEP                       267
+#define MD_IRQID_PTP_THERM_INT_INT                  268
+#define MD_IRQID_PTP_FSM_INT                        269
+#define MD_IRQID_AP2MD_DAPC                         270
+#define MD_IRQID_AP2MD_CCIF2                        271
+#define MD_IRQID_AP2MD_UFS                          272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT                273
+#define MD_IRQID_AP2MD_MSDC0                        274
+#define MD_IRQID_MIPI_IRQ                           275
+#define MD_IRQID_CONN_BT_ISOCH                      276
+#define MD_IRQID_RMPU_CTIREIGIN                     277
+#define MD_IRQID_FREQM_IRQ                          278
+#define MD_IRQID_BT_CVSD                            279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0              280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1              281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2              282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3              283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4              284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5              285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6              286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7              287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8              288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9              289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10             290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11             291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12             292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13             293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14             294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15             295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16             296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17             297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18             298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19             299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20             300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21             301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22             302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23             303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24             304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25             305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26             306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27             307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28             308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29             309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30             310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31             311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32             312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33             313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34             314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35             315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36             316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37             317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38             318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39             319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40             320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41             321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42             322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43             323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44             324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45             325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46             326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47             327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48             328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49             329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50             330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51             331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52             332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53             333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54             334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55             335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56             336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57             337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58             338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59             339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60             340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61             341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62             342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63             343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64             344
+#define MD_IRQID_DUMMY_PRIORITY_IRQ8                345
+#define MD_IRQID_DUMMY_PRIORITY_IRQ9                346
+#define MD_IRQID_DUMMY_PRIORITY_IRQ10               347
+#define MD_IRQID_DUMMY_PRIORITY_IRQ11               348
+#define MD_IRQID_DUMMY_PRIORITY_IRQ12               349
+#define MD_IRQID_DUMMY_PRIORITY_IRQ13               350
+#define MD_IRQID_DUMMY_PRIORITY_IRQ14               351
+#define MD_IRQID_DUMMY_PRIORITY_IRQ15               352
+#define MD_IRQID_DUMMY_PRIORITY_IRQ16               353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17               354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18               355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19               356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20               357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21               358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22               359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23               360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24               361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25               362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26               363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27               364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28               365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29               366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30               367
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6853_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6873.h b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6873.h
new file mode 100644
index 0000000..fe017a6
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6873.h
@@ -0,0 +1,388 @@
+#ifndef __MT6873_IRQID_H__
+#define __MT6873_IRQID_H__
+
+
+//MT6873 IRQID
+#define MD_IRQID_USIM0                                0
+#define MD_IRQID_USIM1                                1
+#define MD_IRQID_TDMA_CTIRQ1                          2
+#define MD_IRQID_TDMA_CTIRQ2                          3
+#define MD_IRQID_TDMA_CTIRQ3                          4
+#define MD_IRQID_TDMA_WAKEUP_IRQ                      5
+#define MD_IRQID_OST                                  6
+#define MD_IRQID_MDRTT                                7
+#define MD_IRQID_MDEVDO                               8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT                  9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT                 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT               11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT               12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT               13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT               14
+#define MD_IRQID_SHARE_D12MINT1                      15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ          16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ          17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ          18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ          19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ          20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ          21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ           22
+#define MD_IRQID_AIRQ_SERDES                         23
+#define MD_IRQID_AIRQ_COS                            24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR            25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR            26
+#define MD_IRQID_PPPHA_ENC0_INT                      27
+#define MD_IRQID_PPPHA_ENC1_INT                      28
+#define MD_IRQID_PPPHA_DEC0_INT                      29
+#define MD_IRQID_PPPHA_DEC1_INT                      30
+#define MD_IRQID_CS_NR_IRQ                           31
+#define MD_IRQID_CS_NR_ERR_IRQ                       32
+#define MD_IRQID_SDF_OVERFLOW_IRQ                    33
+#define MD_IRQID_MCUMMU_INT                          34
+#define MD_IRQID_BIGRAM_0_IRQ_0                      35
+#define MD_IRQID_COS_PREP_INT                        36
+#define MD_IRQID_TRACE_INT                           37
+#define MD_IRQID_NR_TIMER_IRQ0                       38
+#define MD_IRQID_NR_TIMER_IRQ1                       39
+#define MD_IRQID_NR_TIMER_IRQ2                       40
+#define MD_IRQID_NR_TIMER_IRQ3                       41
+#define MD_IRQID_NR_TIMER_IRQ4                       42
+#define MD_IRQID_NR_TIMER_IRQ5                       43
+#define MD_IRQID_NR_TIMER_IRQ6                       44
+#define MD_IRQID_NR_TIMER_IRQ7                       45
+#define MD_IRQID_NR_TIMER_IRQ8                       46
+#define MD_IRQID_NR_TIMER_IRQ9                       47
+#define MD_IRQID_NR_TIMER_IRQ10                      48
+#define MD_IRQID_NR_TIMER_IRQ11                      49
+#define MD_IRQID_NR_TIMER_IRQ12                      50
+#define MD_IRQID_NR_TIMER_IRQ13                      51
+#define MD_IRQID_NR_TIMER_IRQ14                      52
+#define MD_IRQID_NR_TIMER_IRQ15                      53
+#define MD_IRQID_NR_TIMER_IRQ16                      54
+#define MD_IRQID_NR_TIMER_IRQ17                      55
+#define MD_IRQID_NR_TIMER_IRQ18                      56
+#define MD_IRQID_NR_TIMER_IRQ19                      57
+#define MD_IRQID_NR_TIMER_IRQ20                      58
+#define MD_IRQID_NR_TIMER_IRQ21                      59
+#define MD_IRQID_NR_TIMER_IRQ22                      60
+#define MD_IRQID_NR_TIMER_IRQ23                      61
+#define MD_IRQID_NR_TIMER_IRQ24                      62
+#define MD_IRQID_NR_TIMER_IRQ25                      63
+#define MD_IRQID_NR_TIMER_IRQ26                      64
+#define MD_IRQID_NR_TIMER_IRQ27                      65
+#define MD_IRQID_NR_TIMER_IRQ28                      66
+#define MD_IRQID_NR_TIMER_IRQ29                      67
+#define MD_IRQID_NR_TIMER_IRQ30                      68
+#define MD_IRQID_NR_TIMER_IRQ31                      69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0           70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1           71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2           72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3           73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4           74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5           75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6           76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7           77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8           78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9           79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10          80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11          81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12          82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13          83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14          84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15          85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16          86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17          87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0                 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1                 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2                 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3                 91
+#define MD_IRQID_NR_EVENTGEN_SPU                     92
+#define MD_IRQID_SI_CM_ERR                           93
+#define MD_IRQID_SI_CM_PCINT                         94
+#define MD_IRQID_MDM2C_U3G                           95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0                 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1                 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ                98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ                99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ                100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS             101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS           102
+#define MD_IRQID_ELMTOP_EMI_IRQ                     103
+#define MD_IRQID_ELM_DMA_IRQ                        104
+#define MD_IRQID_BUSMPU_IRQ                         105
+#define MD_IRQID_ST1X_CPINT                         106
+#define MD_IRQID_ST1x_HALF_CPINT                    107
+#define MD_IRQID_ST1x_CFG_CPINT                     108
+#define MD_IRQID_ST1x_WAKEUP_IRQ                    109
+#define MD_IRQID_STDO_CPINT                         110
+#define MD_IRQID_STDO_HALF_CPINT                    111
+#define MD_IRQID_STDO_CFG_CPINT                     112
+#define MD_IRQID_STDO_WAKEUP_IRQ                    113
+#define MD_IRQID_UART_MD0                           114
+#define MD_IRQID_UART_MD1                           115
+#define MD_IRQID_EINT0                              116
+#define MD_IRQID_EINT1                              117
+#define MD_IRQID_EINT2                              118
+#define MD_IRQID_EINT3                              119
+#define MD_IRQID_EINT_SHARE                         120
+#define MD_IRQID_GPTM1                              121
+#define MD_IRQID_GPTM2                              122
+#define MD_IRQID_GPTM3                              123
+#define MD_IRQID_GPTM4                              124
+#define MD_IRQID_GPTM5                              125
+#define MD_IRQID_GPTM6                              126
+#define MD_IRQID_GPTM7                              127
+#define MD_IRQID_GPTM8                              128
+#define MD_IRQID_GPTM9                              129
+#define MD_IRQID_GPTM10                             130
+#define MD_IRQID_GPTM11                             131
+#define MD_IRQID_IDC_PM_INT                         132
+#define MD_IRQID_IDC_UART_IRQ                       133
+#define MD_IRQID_MDGDMA_FDMA5                       134
+#define MD_IRQID_MDGDMA_FDMA6                       135
+#define MD_IRQID_TDMA_CTIRQ4                        136
+#define MD_IRQID_PDMA                               137
+#define MD_IRQID_MDINFRA_BUS_DECERROR               138
+#define MD_IRQID_I2C_TOP_INT                        139
+#define MD_IRQID_SOE                                140
+#define MD_IRQID_ABM_INT                            141
+#define MD_IRQID_ABM_ERROR_INT                      142
+#define MD_IRQID_USIP0                              143
+#define MD_IRQID_USIP1                              144
+#define MD_IRQID_USIP2                              145
+#define MD_IRQID_USIP3                              146
+#define MD_IRQID_USIP4                              147
+#define MD_IRQID_USIP5                              148
+#define MD_IRQID_USIP6                              149
+#define MD_IRQID_USIP7                              150
+#define MD_IRQID_USIP8                              151
+#define MD_IRQID_USIP9                              152
+#define MD_IRQID_USIP10                             153
+#define MD_IRQID_USIP11                             154
+#define MD_IRQID_USIP12                             155
+#define MD_IRQID_USIP13                             156
+#define MD_IRQID_TX_NR_CC0_IRQ                      157
+#define MD_IRQID_TX_NR_CC1_IRQ                      158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ                   159
+#define MD_IRQID_MDMCU_SPU_IRQ                      160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE                 161
+#define MD_IRQID_ECT                                162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ               163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE                164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE              165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ           166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ     167
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_0               168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ     169
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_1               170
+#define MD_IRQID_MDWDT                              171
+#define MD_IRQID_MDGDMA_FDMA0_2                     172
+#define MD_IRQID_MDGDMA_FDMA1                       173
+#define MD_IRQID_MDGDMA_FDMA3                       174
+#define MD_IRQID_MDGDMA_FDMA4                       175
+#define MD_IRQID_MDGDMA_HDMA0_1                     176
+#define MD_IRQID_MDGDMA_HDMA2_3                     177
+#define MD_IRQID_AP2MD_CCIF0_0                      178
+#define MD_IRQID_AP2MD_CCIF0_1                      179
+#define MD_IRQID_AP2MD_CCIF1_0                      180
+#define MD_IRQID_AP2MD_CCIF1_1                      181
+#define MD_IRQID_IEBIT_CHECK_IRQ0                   182
+#define MD_IRQID_IEBIT_CHECK_IRQ1                   183
+#define MD_IRQID_IEBIT_CHECK_IRQ2                   184
+#define MD_IRQID_IEBIT_CHECK_IRQ3                   185
+#define MD_IRQID_IEBIT_CHECK_IRQ4                   186
+#define MD_IRQID_IEBIT_CHECK_IRQ5                   187
+#define MD_IRQID_IEBIT_CHECK_IRQ6                   188
+#define MD_IRQID_IEBIT_CHECK_IRQ7                   189
+#define MD_IRQID_IEBIT_CHECK_IRQ8                   190
+#define MD_IRQID_IEBIT_CHECK_IRQ9                   191
+#define MD_IRQID_IEBIT_CHECK_IRQ10                  192
+#define MD_IRQID_IEBIT_CHECK_IRQ11                  193
+#define MD_IRQID_NRL2_HRT                           194
+#define MD_IRQID_NRL2_NOTIF                         195
+#define MD_IRQID_NRL2_EXCEP                         196
+#define MD_IRQID_NRL2_DPMAIF_MD                     197
+#define MD_IRQID_RXDFE_IRQ0                         198
+#define MD_IRQID_IDC_UART_TX_FORCE_ON               199
+#define MD_IRQID_RXDFE_IRQ2                         200
+#define MD_IRQID_RXDFE_IRQ3                         201
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_0              202
+#define MD_IRQID_MD_RXDFE_BB_DUMP                   203
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_1              204
+#define MD_IRQID_TXCRP                              205
+#define MD_IRQID_CM_NR_IRQ                          206
+#define MD_IRQID_CM_NR_ERR_IRQ                      207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ                   208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0      209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1      210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2      211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3      212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4      213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5      214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6      215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7      216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8      217
+#define MD_IRQID_D_GDMA_0_IRQ                       218
+#define MD_IRQID_D_GDMA_1_IRQ                       219
+#define MD_IRQID_D_GDMA_2_IRQ                       220
+#define MD_IRQID_D_GDMA_3_IRQ                       221
+#define MD_IRQID_D_GDMA_4_IRQ                       222
+#define MD_IRQID_D_GDMA_5_IRQ                       223
+#define MD_IRQID_PLL_GEARHP_RDY                     224
+#define MD_IRQID_REQ_ABNORM_IRQ                     225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU                  226
+#define MD_IRQID_AP2MD_APWDT_IRQ                    227
+#define MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ            228
+#define MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ             229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5                230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ               231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0                 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1                 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2                 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3                 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4                 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5                 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6                 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7                 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6                240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ                  241
+#define MD_IRQID_TDD_WAKEUP_IRQ                     242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ                243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ                244
+#define MD_IRQID_RTR_SLT_0_IRQ                      245
+#define MD_IRQID_RTR_SLT_1_IRQ                      246
+#define MD_IRQID_FDD_SLP_IRQ                        247
+#define MD_IRQID_IRDBG_MCU_INT                      248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0                 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1                 250
+#define MD_IRQID_NR_SLP_WAKEUP                      251
+#define MD_IRQID_NR_SLP_SLEEP                       252
+#define MD_IRQID_NR_TIMER_ERR                       253
+#define MD_IRQID_TXBSRP                             254
+#define MD_IRQID_TXDFE_D                            255
+#define MD_IRQID_NR_EVENTGEN_ERR                    256
+#define MD_IRQID_AIRQ_PAD                           257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ                   258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ                   259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ                   260
+#define MD_IRQID_CSSYS_1X_CS_IRQ                    261
+#define MD_IRQID_CSSYS_DO_CS_IRQ                    262
+#define MD_IRQID_PCIE_INTERRUPT_OUT                 263
+#define MD_IRQID_UCNT_SCH_IRQ                       264
+#define MD_IRQID_UCNT_ERR_IRQ                       265
+#define MD_IRQID_UCNT_ADJ_IRQ                       266
+#define MD_IRQID_SL_WAITSLEEP                       267
+#define MD_IRQID_PTP_THERM_INT_INT                  268
+#define MD_IRQID_PTP_FSM_INT                        269
+#define MD_IRQID_AP2MD_DAPC                         270
+#define MD_IRQID_AP2MD_CCIF2                        271
+#define MD_IRQID_AP2MD_UFS                          272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT                273
+#define MD_IRQID_AP2MD_MSDC0                        274
+#define MD_IRQID_MIPI_IRQ                           275
+#define MD_IRQID_CONN_BT_ISOCH                      276
+#define MD_IRQID_RMPU_CTIREIGIN                     277
+#define MD_IRQID_FREQM_IRQ                          278
+#define MD_IRQID_BT_CVSD                            279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0              280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1              281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2              282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3              283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4              284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5              285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6              286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7              287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8              288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9              289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10             290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11             291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12             292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13             293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14             294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15             295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16             296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17             297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18             298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19             299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20             300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21             301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22             302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23             303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24             304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25             305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26             306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27             307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28             308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29             309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30             310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31             311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32             312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33             313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34             314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35             315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36             316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37             317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38             318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39             319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40             320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41             321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42             322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43             323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44             324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45             325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46             326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47             327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48             328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49             329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50             330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51             331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52             332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53             333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54             334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55             335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56             336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57             337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58             338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59             339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60             340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61             341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62             342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63             343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64             344
+#define MD_IRQID_DUMMY_PRIORITY_IRQ8                345
+#define MD_IRQID_DUMMY_PRIORITY_IRQ9                346
+#define MD_IRQID_DUMMY_PRIORITY_IRQ10               347
+#define MD_IRQID_DUMMY_PRIORITY_IRQ11               348
+#define MD_IRQID_DUMMY_PRIORITY_IRQ12               349
+#define MD_IRQID_DUMMY_PRIORITY_IRQ13               350
+#define MD_IRQID_DUMMY_PRIORITY_IRQ14               351
+#define MD_IRQID_DUMMY_PRIORITY_IRQ15               352
+#define MD_IRQID_DUMMY_PRIORITY_IRQ16               353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17               354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18               355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19               356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20               357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21               358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22               359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23               360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24               361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25               362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26               363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27               364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28               365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29               366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30               367
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6873_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6877.h b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6877.h
new file mode 100644
index 0000000..3bf835b
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6877.h
@@ -0,0 +1,388 @@
+#ifndef __MT6877_IRQID_H__
+#define __MT6877_IRQID_H__
+
+
+//MT6877 IRQID
+#define MD_IRQID_USIM0                                0
+#define MD_IRQID_USIM1                                1
+#define MD_IRQID_TDMA_CTIRQ1                          2
+#define MD_IRQID_TDMA_CTIRQ2                          3
+#define MD_IRQID_TDMA_CTIRQ3                          4
+#define MD_IRQID_TDMA_WAKEUP_IRQ                      5
+#define MD_IRQID_OST                                  6
+#define MD_IRQID_MDRTT                                7
+#define MD_IRQID_MDEVDO                               8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT                  9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT                 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT               11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT               12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT               13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT               14
+#define MD_IRQID_SHARE_D12MINT1                      15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ          16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ          17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ          18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ          19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ          20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ          21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ           22
+#define MD_IRQID_AIRQ_SERDES                         23
+#define MD_IRQID_AIRQ_COS                            24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR            25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR            26
+#define MD_IRQID_PPPHA_ENC0_INT                      27
+#define MD_IRQID_PPPHA_ENC1_INT                      28
+#define MD_IRQID_PPPHA_DEC0_INT                      29
+#define MD_IRQID_PPPHA_DEC1_INT                      30
+#define MD_IRQID_CS_NR_IRQ                           31
+#define MD_IRQID_CS_NR_ERR_IRQ                       32
+#define MD_IRQID_SDF_OVERFLOW_IRQ                    33
+#define MD_IRQID_MCUMMU_INT                          34
+#define MD_IRQID_BIGRAM_0_IRQ_0                      35
+#define MD_IRQID_COS_PREP_INT                        36
+#define MD_IRQID_TRACE_INT                           37
+#define MD_IRQID_NR_TIMER_IRQ0                       38
+#define MD_IRQID_NR_TIMER_IRQ1                       39
+#define MD_IRQID_NR_TIMER_IRQ2                       40
+#define MD_IRQID_NR_TIMER_IRQ3                       41
+#define MD_IRQID_NR_TIMER_IRQ4                       42
+#define MD_IRQID_NR_TIMER_IRQ5                       43
+#define MD_IRQID_NR_TIMER_IRQ6                       44
+#define MD_IRQID_NR_TIMER_IRQ7                       45
+#define MD_IRQID_NR_TIMER_IRQ8                       46
+#define MD_IRQID_NR_TIMER_IRQ9                       47
+#define MD_IRQID_NR_TIMER_IRQ10                      48
+#define MD_IRQID_NR_TIMER_IRQ11                      49
+#define MD_IRQID_NR_TIMER_IRQ12                      50
+#define MD_IRQID_NR_TIMER_IRQ13                      51
+#define MD_IRQID_NR_TIMER_IRQ14                      52
+#define MD_IRQID_NR_TIMER_IRQ15                      53
+#define MD_IRQID_NR_TIMER_IRQ16                      54
+#define MD_IRQID_NR_TIMER_IRQ17                      55
+#define MD_IRQID_NR_TIMER_IRQ18                      56
+#define MD_IRQID_NR_TIMER_IRQ19                      57
+#define MD_IRQID_NR_TIMER_IRQ20                      58
+#define MD_IRQID_NR_TIMER_IRQ21                      59
+#define MD_IRQID_NR_TIMER_IRQ22                      60
+#define MD_IRQID_NR_TIMER_IRQ23                      61
+#define MD_IRQID_NR_TIMER_IRQ24                      62
+#define MD_IRQID_NR_TIMER_IRQ25                      63
+#define MD_IRQID_NR_TIMER_IRQ26                      64
+#define MD_IRQID_NR_TIMER_IRQ27                      65
+#define MD_IRQID_NR_TIMER_IRQ28                      66
+#define MD_IRQID_NR_TIMER_IRQ29                      67
+#define MD_IRQID_NR_TIMER_IRQ30                      68
+#define MD_IRQID_NR_TIMER_IRQ31                      69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0           70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1           71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2           72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3           73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4           74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5           75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6           76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7           77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8           78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9           79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10          80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11          81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12          82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13          83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14          84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15          85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16          86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17          87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0                 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1                 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2                 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3                 91
+#define MD_IRQID_NR_EVENTGEN_SPU                     92
+#define MD_IRQID_SI_CM_ERR                           93
+#define MD_IRQID_SI_CM_PCINT                         94
+#define MD_IRQID_MDM2C_U3G                           95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0                 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1                 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ                98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ                99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ                100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS             101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS           102
+#define MD_IRQID_ELMTOP_EMI_IRQ                     103
+#define MD_IRQID_ELM_DMA_IRQ                        104
+#define MD_IRQID_BUSMPU_IRQ                         105
+#define MD_IRQID_ST1X_CPINT                         106
+#define MD_IRQID_ST1x_HALF_CPINT                    107
+#define MD_IRQID_ST1x_CFG_CPINT                     108
+#define MD_IRQID_ST1x_WAKEUP_IRQ                    109
+#define MD_IRQID_STDO_CPINT                         110
+#define MD_IRQID_STDO_HALF_CPINT                    111
+#define MD_IRQID_STDO_CFG_CPINT                     112
+#define MD_IRQID_STDO_WAKEUP_IRQ                    113
+#define MD_IRQID_UART_MD0                           114
+#define MD_IRQID_UART_MD1                           115
+#define MD_IRQID_EINT0                              116
+#define MD_IRQID_EINT1                              117
+#define MD_IRQID_EINT2                              118
+#define MD_IRQID_EINT3                              119
+#define MD_IRQID_EINT_SHARE                         120
+#define MD_IRQID_GPTM1                              121
+#define MD_IRQID_GPTM2                              122
+#define MD_IRQID_GPTM3                              123
+#define MD_IRQID_GPTM4                              124
+#define MD_IRQID_GPTM5                              125
+#define MD_IRQID_GPTM6                              126
+#define MD_IRQID_GPTM7                              127
+#define MD_IRQID_GPTM8                              128
+#define MD_IRQID_GPTM9                              129
+#define MD_IRQID_GPTM10                             130
+#define MD_IRQID_GPTM11                             131
+#define MD_IRQID_IDC_PM_INT                         132
+#define MD_IRQID_IDC_UART_IRQ                       133
+#define MD_IRQID_MDGDMA_FDMA5                       134
+#define MD_IRQID_MDGDMA_FDMA6                       135
+#define MD_IRQID_TDMA_CTIRQ4                        136
+#define MD_IRQID_PDMA                               137
+#define MD_IRQID_MDINFRA_BUS_DECERROR               138
+#define MD_IRQID_I2C_TOP_INT                        139
+#define MD_IRQID_SOE                                140
+#define MD_IRQID_ABM_INT                            141
+#define MD_IRQID_ABM_ERROR_INT                      142
+#define MD_IRQID_USIP0                              143
+#define MD_IRQID_USIP1                              144
+#define MD_IRQID_USIP2                              145
+#define MD_IRQID_USIP3                              146
+#define MD_IRQID_USIP4                              147
+#define MD_IRQID_USIP5                              148
+#define MD_IRQID_USIP6                              149
+#define MD_IRQID_USIP7                              150
+#define MD_IRQID_USIP8                              151
+#define MD_IRQID_USIP9                              152
+#define MD_IRQID_USIP10                             153
+#define MD_IRQID_USIP11                             154
+#define MD_IRQID_USIP12                             155
+#define MD_IRQID_USIP13                             156
+#define MD_IRQID_TX_NR_CC0_IRQ                      157
+#define MD_IRQID_TX_NR_CC1_IRQ                      158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ                   159
+#define MD_IRQID_MDMCU_SPU_IRQ                      160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE                 161
+#define MD_IRQID_ECT                                162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ               163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE                164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE              165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ           166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ     167
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_0               168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ     169
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_1               170
+#define MD_IRQID_MDWDT                              171
+#define MD_IRQID_MDGDMA_FDMA0_2                     172
+#define MD_IRQID_MDGDMA_FDMA1                       173
+#define MD_IRQID_MDGDMA_FDMA3                       174
+#define MD_IRQID_MDGDMA_FDMA4                       175
+#define MD_IRQID_MDGDMA_HDMA0_1                     176
+#define MD_IRQID_MDGDMA_HDMA2_3                     177
+#define MD_IRQID_AP2MD_CCIF0_0                      178
+#define MD_IRQID_AP2MD_CCIF0_1                      179
+#define MD_IRQID_AP2MD_CCIF1_0                      180
+#define MD_IRQID_AP2MD_CCIF1_1                      181
+#define MD_IRQID_IEBIT_CHECK_IRQ0                   182
+#define MD_IRQID_IEBIT_CHECK_IRQ1                   183
+#define MD_IRQID_IEBIT_CHECK_IRQ2                   184
+#define MD_IRQID_IEBIT_CHECK_IRQ3                   185
+#define MD_IRQID_IEBIT_CHECK_IRQ4                   186
+#define MD_IRQID_IEBIT_CHECK_IRQ5                   187
+#define MD_IRQID_IEBIT_CHECK_IRQ6                   188
+#define MD_IRQID_IEBIT_CHECK_IRQ7                   189
+#define MD_IRQID_IEBIT_CHECK_IRQ8                   190
+#define MD_IRQID_IEBIT_CHECK_IRQ9                   191
+#define MD_IRQID_IEBIT_CHECK_IRQ10                  192
+#define MD_IRQID_IEBIT_CHECK_IRQ11                  193
+#define MD_IRQID_NRL2_HRT                           194
+#define MD_IRQID_NRL2_NOTIF                         195
+#define MD_IRQID_NRL2_EXCEP                         196
+#define MD_IRQID_NRL2_DPMAIF_MD                     197
+#define MD_IRQID_RXDFE_IRQ0                         198
+#define MD_IRQID_IDC_UART_TX_FORCE_ON               199
+#define MD_IRQID_RXDFE_IRQ2                         200
+#define MD_IRQID_RXDFE_IRQ3                         201
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_0              202
+#define MD_IRQID_MD_RXDFE_BB_DUMP                   203
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_1              204
+#define MD_IRQID_TXCRP                              205
+#define MD_IRQID_CM_NR_IRQ                          206
+#define MD_IRQID_CM_NR_ERR_IRQ                      207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ                   208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0      209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1      210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2      211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3      212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4      213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5      214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6      215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7      216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8      217
+#define MD_IRQID_D_GDMA_0_IRQ                       218
+#define MD_IRQID_D_GDMA_1_IRQ                       219
+#define MD_IRQID_D_GDMA_2_IRQ                       220
+#define MD_IRQID_D_GDMA_3_IRQ                       221
+#define MD_IRQID_D_GDMA_4_IRQ                       222
+#define MD_IRQID_D_GDMA_5_IRQ                       223
+#define MD_IRQID_PLL_GEARHP_RDY                     224
+#define MD_IRQID_REQ_ABNORM_IRQ                     225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU                  226
+#define MD_IRQID_AP2MD_APWDT_IRQ                    227
+#define MD_IRQID_AP2MD_APMCU_SUSPEND_IRQ            228
+#define MD_IRQID_AP2MD_APMCU_ACTIVE_IRQ             229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5                230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ               231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0                 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1                 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2                 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3                 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4                 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5                 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6                 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7                 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6                240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ                  241
+#define MD_IRQID_TDD_WAKEUP_IRQ                     242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ                243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ                244
+#define MD_IRQID_RTR_SLT_0_IRQ                      245
+#define MD_IRQID_RTR_SLT_1_IRQ                      246
+#define MD_IRQID_FDD_SLP_IRQ                        247
+#define MD_IRQID_IRDBG_MCU_INT                      248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0                 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1                 250
+#define MD_IRQID_NR_SLP_WAKEUP                      251
+#define MD_IRQID_NR_SLP_SLEEP                       252
+#define MD_IRQID_NR_TIMER_ERR                       253
+#define MD_IRQID_TXBSRP                             254
+#define MD_IRQID_TXDFE_D                            255
+#define MD_IRQID_NR_EVENTGEN_ERR                    256
+#define MD_IRQID_AIRQ_PAD                           257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ                   258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ                   259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ                   260
+#define MD_IRQID_CSSYS_1X_CS_IRQ                    261
+#define MD_IRQID_CSSYS_DO_CS_IRQ                    262
+#define MD_IRQID_PCIE_INTERRUPT_OUT                 263
+#define MD_IRQID_UCNT_SCH_IRQ                       264
+#define MD_IRQID_UCNT_ERR_IRQ                       265
+#define MD_IRQID_UCNT_ADJ_IRQ                       266
+#define MD_IRQID_SL_WAITSLEEP                       267
+#define MD_IRQID_PTP_THERM_INT_INT                  268
+#define MD_IRQID_PTP_FSM_INT                        269
+#define MD_IRQID_AP2MD_DAPC                         270
+#define MD_IRQID_AP2MD_CCIF2                        271
+#define MD_IRQID_AP2MD_UFS                          272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT                273
+#define MD_IRQID_AP2MD_MSDC0                        274
+#define MD_IRQID_MIPI_IRQ                           275
+#define MD_IRQID_CONN_BT_ISOCH                      276
+#define MD_IRQID_RMPU_CTIREIGIN                     277
+#define MD_IRQID_FREQM_IRQ                          278
+#define MD_IRQID_BT_CVSD                            279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0              280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1              281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2              282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3              283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4              284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5              285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6              286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7              287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8              288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9              289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10             290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11             291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12             292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13             293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14             294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15             295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16             296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17             297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18             298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19             299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20             300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21             301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22             302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23             303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24             304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25             305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26             306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27             307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28             308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29             309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30             310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31             311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32             312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33             313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34             314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35             315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36             316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37             317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38             318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39             319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40             320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41             321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42             322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43             323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44             324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45             325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46             326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47             327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48             328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49             329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50             330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51             331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52             332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53             333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54             334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55             335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56             336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57             337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58             338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59             339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60             340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61             341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62             342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63             343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64             344
+#define MD_IRQID_DUMMY_PRIORITY_IRQ8                345
+#define MD_IRQID_DUMMY_PRIORITY_IRQ9                346
+#define MD_IRQID_DUMMY_PRIORITY_IRQ10               347
+#define MD_IRQID_DUMMY_PRIORITY_IRQ11               348
+#define MD_IRQID_DUMMY_PRIORITY_IRQ12               349
+#define MD_IRQID_DUMMY_PRIORITY_IRQ13               350
+#define MD_IRQID_DUMMY_PRIORITY_IRQ14               351
+#define MD_IRQID_DUMMY_PRIORITY_IRQ15               352
+#define MD_IRQID_DUMMY_PRIORITY_IRQ16               353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17               354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18               355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19               356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20               357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21               358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22               359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23               360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24               361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25               362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26               363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27               364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28               365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29               366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30               367
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6877_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6885.h b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6885.h
new file mode 100644
index 0000000..ed37ecc
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/irqid_MT6885.h
@@ -0,0 +1,388 @@
+#ifndef __MT6885_IRQID_H__
+#define __MT6885_IRQID_H__
+
+
+//MT6885 IRQID
+#define MD_IRQID_USIM0                                0
+#define MD_IRQID_USIM1                                1
+#define MD_IRQID_TDMA_CTIRQ1                          2
+#define MD_IRQID_TDMA_CTIRQ2                          3
+#define MD_IRQID_TDMA_CTIRQ3                          4
+#define MD_IRQID_TDMA_WAKEUP_IRQ                      5
+#define MD_IRQID_OST                                  6
+#define MD_IRQID_MDRTT                                7
+#define MD_IRQID_MDEVDO                               8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT                  9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT                 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT               11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT               12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT               13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT               14
+#define MD_IRQID_SHARE_D12MINT1                      15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ          16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ          17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ          18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ          19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ          20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ          21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ           22
+#define MD_IRQID_AIRQ_SERDES                         23
+#define MD_IRQID_AIRQ_COS                            24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR            25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR            26
+#define MD_IRQID_PPPHA_ENC0_INT                      27
+#define MD_IRQID_PPPHA_ENC1_INT                      28
+#define MD_IRQID_PPPHA_DEC0_INT                      29
+#define MD_IRQID_PPPHA_DEC1_INT                      30
+#define MD_IRQID_CS_NR_IRQ                           31
+#define MD_IRQID_CS_NR_ERR_IRQ                       32
+#define MD_IRQID_SDF_OVERFLOW_IRQ                    33
+#define MD_IRQID_MCUMMU_INT                          34
+#define MD_IRQID_BIGRAM_0_IRQ_0                      35
+#define MD_IRQID_COS_PREP_INT                        36
+#define MD_IRQID_TRACE_INT                           37
+#define MD_IRQID_NR_TIMER_IRQ0                       38
+#define MD_IRQID_NR_TIMER_IRQ1                       39
+#define MD_IRQID_NR_TIMER_IRQ2                       40
+#define MD_IRQID_NR_TIMER_IRQ3                       41
+#define MD_IRQID_NR_TIMER_IRQ4                       42
+#define MD_IRQID_NR_TIMER_IRQ5                       43
+#define MD_IRQID_NR_TIMER_IRQ6                       44
+#define MD_IRQID_NR_TIMER_IRQ7                       45
+#define MD_IRQID_NR_TIMER_IRQ8                       46
+#define MD_IRQID_NR_TIMER_IRQ9                       47
+#define MD_IRQID_NR_TIMER_IRQ10                      48
+#define MD_IRQID_NR_TIMER_IRQ11                      49
+#define MD_IRQID_NR_TIMER_IRQ12                      50
+#define MD_IRQID_NR_TIMER_IRQ13                      51
+#define MD_IRQID_NR_TIMER_IRQ14                      52
+#define MD_IRQID_NR_TIMER_IRQ15                      53
+#define MD_IRQID_NR_TIMER_IRQ16                      54
+#define MD_IRQID_NR_TIMER_IRQ17                      55
+#define MD_IRQID_NR_TIMER_IRQ18                      56
+#define MD_IRQID_NR_TIMER_IRQ19                      57
+#define MD_IRQID_NR_TIMER_IRQ20                      58
+#define MD_IRQID_NR_TIMER_IRQ21                      59
+#define MD_IRQID_NR_TIMER_IRQ22                      60
+#define MD_IRQID_NR_TIMER_IRQ23                      61
+#define MD_IRQID_NR_TIMER_IRQ24                      62
+#define MD_IRQID_NR_TIMER_IRQ25                      63
+#define MD_IRQID_NR_TIMER_IRQ26                      64
+#define MD_IRQID_NR_TIMER_IRQ27                      65
+#define MD_IRQID_NR_TIMER_IRQ28                      66
+#define MD_IRQID_NR_TIMER_IRQ29                      67
+#define MD_IRQID_NR_TIMER_IRQ30                      68
+#define MD_IRQID_NR_TIMER_IRQ31                      69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0           70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1           71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2           72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3           73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4           74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5           75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6           76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7           77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8           78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9           79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10          80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11          81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12          82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13          83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14          84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15          85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16          86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17          87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0                 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1                 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2                 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3                 91
+#define MD_IRQID_NR_EVENTGEN_SPU                     92
+#define MD_IRQID_SI_CM_ERR                           93
+#define MD_IRQID_SI_CM_PCINT                         94
+#define MD_IRQID_MDM2C_U3G                           95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0                 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1                 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ                98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ                99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ                100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS             101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS           102
+#define MD_IRQID_ELMTOP_EMI_IRQ                     103
+#define MD_IRQID_ELM_DMA_IRQ                        104
+#define MD_IRQID_BUSMPU_IRQ                         105
+#define MD_IRQID_ST1X_CPINT                         106
+#define MD_IRQID_ST1x_HALF_CPINT                    107
+#define MD_IRQID_ST1x_CFG_CPINT                     108
+#define MD_IRQID_ST1x_WAKEUP_IRQ                    109
+#define MD_IRQID_STDO_CPINT                         110
+#define MD_IRQID_STDO_HALF_CPINT                    111
+#define MD_IRQID_STDO_CFG_CPINT                     112
+#define MD_IRQID_STDO_WAKEUP_IRQ                    113
+#define MD_IRQID_UART_MD0                           114
+#define MD_IRQID_UART_MD1                           115
+#define MD_IRQID_EINT0                              116
+#define MD_IRQID_EINT1                              117
+#define MD_IRQID_EINT2                              118
+#define MD_IRQID_EINT3                              119
+#define MD_IRQID_EINT_SHARE                         120
+#define MD_IRQID_GPTM1                              121
+#define MD_IRQID_GPTM2                              122
+#define MD_IRQID_GPTM3                              123
+#define MD_IRQID_GPTM4                              124
+#define MD_IRQID_GPTM5                              125
+#define MD_IRQID_GPTM6                              126
+#define MD_IRQID_GPTM7                              127
+#define MD_IRQID_GPTM8                              128
+#define MD_IRQID_GPTM9                              129
+#define MD_IRQID_GPTM10                             130
+#define MD_IRQID_GPTM11                             131
+#define MD_IRQID_IDC_PM_INT                         132
+#define MD_IRQID_IDC_UART_IRQ                       133
+#define MD_IRQID_MDGDMA_FDMA5                       134
+#define MD_IRQID_MDGDMA_FDMA6                       135
+#define MD_IRQID_TDMA_CTIRQ4                        136
+#define MD_IRQID_PDMA                               137
+#define MD_IRQID_MDINFRA_BUS_DECERROR               138
+#define MD_IRQID_I2C_TOP_INT                        139
+#define MD_IRQID_SOE                                140
+#define MD_IRQID_ABM_INT                            141
+#define MD_IRQID_ABM_ERROR_INT                      142
+#define MD_IRQID_USIP0                              143
+#define MD_IRQID_USIP1                              144
+#define MD_IRQID_USIP2                              145
+#define MD_IRQID_USIP3                              146
+#define MD_IRQID_USIP4                              147
+#define MD_IRQID_USIP5                              148
+#define MD_IRQID_USIP6                              149
+#define MD_IRQID_USIP7                              150
+#define MD_IRQID_USIP8                              151
+#define MD_IRQID_USIP9                              152
+#define MD_IRQID_USIP10                             153
+#define MD_IRQID_USIP11                             154
+#define MD_IRQID_USIP12                             155
+#define MD_IRQID_USIP13                             156
+#define MD_IRQID_TX_NR_CC0_IRQ                      157
+#define MD_IRQID_TX_NR_CC1_IRQ                      158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ                   159
+#define MD_IRQID_MDMCU_SPU_IRQ                      160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE                 161
+#define MD_IRQID_ECT                                162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ               163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE                164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE              165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ           166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ     167
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_0               168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ     169
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_1               170
+#define MD_IRQID_MDWDT                              171
+#define MD_IRQID_MDGDMA_FDMA0_2                     172
+#define MD_IRQID_MDGDMA_FDMA1                       173
+#define MD_IRQID_MDGDMA_FDMA3                       174
+#define MD_IRQID_MDGDMA_FDMA4                       175
+#define MD_IRQID_MDGDMA_HDMA0_1                     176
+#define MD_IRQID_MDGDMA_HDMA2_3                     177
+#define MD_IRQID_AP2MD_CCIF0_0                      178
+#define MD_IRQID_AP2MD_CCIF0_1                      179
+#define MD_IRQID_AP2MD_CCIF1_0                      180
+#define MD_IRQID_AP2MD_CCIF1_1                      181
+#define MD_IRQID_IEBIT_CHECK_IRQ0                   182
+#define MD_IRQID_IEBIT_CHECK_IRQ1                   183
+#define MD_IRQID_IEBIT_CHECK_IRQ2                   184
+#define MD_IRQID_IEBIT_CHECK_IRQ3                   185
+#define MD_IRQID_IEBIT_CHECK_IRQ4                   186
+#define MD_IRQID_IEBIT_CHECK_IRQ5                   187
+#define MD_IRQID_IEBIT_CHECK_IRQ6                   188
+#define MD_IRQID_IEBIT_CHECK_IRQ7                   189
+#define MD_IRQID_IEBIT_CHECK_IRQ8                   190
+#define MD_IRQID_IEBIT_CHECK_IRQ9                   191
+#define MD_IRQID_IEBIT_CHECK_IRQ10                  192
+#define MD_IRQID_IEBIT_CHECK_IRQ11                  193
+#define MD_IRQID_NRL2_HRT                           194
+#define MD_IRQID_NRL2_NOTIF                         195
+#define MD_IRQID_NRL2_EXCEP                         196
+#define MD_IRQID_NRL2_DPMAIF_MD                     197
+#define MD_IRQID_RXDFE_IRQ0                         198
+#define MD_IRQID_IDC_UART_TX_FORCE_ON               199
+#define MD_IRQID_RXDFE_IRQ2                         200
+#define MD_IRQID_RXDFE_IRQ3                         201
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_0              202
+#define MD_IRQID_MD_RXDFE_BB_DUMP                   203
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_1              204
+#define MD_IRQID_TXCRP                              205
+#define MD_IRQID_CM_NR_IRQ                          206
+#define MD_IRQID_CM_NR_ERR_IRQ                      207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ                   208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0      209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1      210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2      211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3      212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4      213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5      214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6      215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7      216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8      217
+#define MD_IRQID_D_GDMA_0_IRQ                       218
+#define MD_IRQID_D_GDMA_1_IRQ                       219
+#define MD_IRQID_D_GDMA_2_IRQ                       220
+#define MD_IRQID_D_GDMA_3_IRQ                       221
+#define MD_IRQID_D_GDMA_4_IRQ                       222
+#define MD_IRQID_D_GDMA_5_IRQ                       223
+#define MD_IRQID_PLL_GEARHP_RDY                     224
+#define MD_IRQID_REQ_ABNORM_IRQ                     225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU                  226
+#define MD_IRQID_AP2MD_APWDT_IRQ                    227
+#define MD_IRQID_DUMMY_PRIORITY_IRQ3                228
+#define MD_IRQID_DUMMY_PRIORITY_IRQ4                229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5                230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ               231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0                 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1                 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2                 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3                 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4                 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5                 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6                 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7                 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6                240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ                  241
+#define MD_IRQID_TDD_WAKEUP_IRQ                     242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ                243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ                244
+#define MD_IRQID_RTR_SLT_0_IRQ                      245
+#define MD_IRQID_RTR_SLT_1_IRQ                      246
+#define MD_IRQID_FDD_SLP_IRQ                        247
+#define MD_IRQID_IRDBG_MCU_INT                      248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0                 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1                 250
+#define MD_IRQID_NR_SLP_WAKEUP                      251
+#define MD_IRQID_NR_SLP_SLEEP                       252
+#define MD_IRQID_NR_TIMER_ERR                       253
+#define MD_IRQID_TXBSRP                             254
+#define MD_IRQID_TXDFE_D                            255
+#define MD_IRQID_NR_EVENTGEN_ERR                    256
+#define MD_IRQID_AIRQ_PAD                           257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ                   258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ                   259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ                   260
+#define MD_IRQID_CSSYS_1X_CS_IRQ                    261
+#define MD_IRQID_CSSYS_DO_CS_IRQ                    262
+#define MD_IRQID_PCIE_INTERRUPT_OUT                 263
+#define MD_IRQID_UCNT_SCH_IRQ                       264
+#define MD_IRQID_UCNT_ERR_IRQ                       265
+#define MD_IRQID_UCNT_ADJ_IRQ                       266
+#define MD_IRQID_SL_WAITSLEEP                       267
+#define MD_IRQID_PTP_THERM_INT_INT                  268
+#define MD_IRQID_PTP_FSM_INT                        269
+#define MD_IRQID_AP2MD_DAPC                         270
+#define MD_IRQID_AP2MD_CCIF2                        271
+#define MD_IRQID_AP2MD_UFS                          272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT                273
+#define MD_IRQID_AP2MD_MSDC0                        274
+#define MD_IRQID_MIPI_IRQ                           275
+#define MD_IRQID_CONN_BT_ISOCH                      276
+#define MD_IRQID_RMPU_CTIREIGIN                     277
+#define MD_IRQID_FREQM_IRQ                          278
+#define MD_IRQID_BT_CVSD                            279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0              280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1              281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2              282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3              283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4              284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5              285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6              286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7              287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8              288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9              289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10             290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11             291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12             292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13             293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14             294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15             295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16             296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17             297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18             298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19             299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20             300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21             301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22             302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23             303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24             304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25             305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26             306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27             307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28             308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29             309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30             310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31             311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32             312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33             313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34             314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35             315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36             316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37             317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38             318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39             319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40             320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41             321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42             322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43             323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44             324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45             325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46             326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47             327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48             328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49             329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50             330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51             331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52             332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53             333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54             334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55             335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56             336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57             337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58             338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59             339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60             340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61             341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62             342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63             343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64             344
+#define MD_IRQID_DUMMY_PRIORITY_IRQ8                345
+#define MD_IRQID_DUMMY_PRIORITY_IRQ9                346
+#define MD_IRQID_DUMMY_PRIORITY_IRQ10               347
+#define MD_IRQID_DUMMY_PRIORITY_IRQ11               348
+#define MD_IRQID_DUMMY_PRIORITY_IRQ12               349
+#define MD_IRQID_DUMMY_PRIORITY_IRQ13               350
+#define MD_IRQID_DUMMY_PRIORITY_IRQ14               351
+#define MD_IRQID_DUMMY_PRIORITY_IRQ15               352
+#define MD_IRQID_DUMMY_PRIORITY_IRQ16               353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17               354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18               355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19               356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20               357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21               358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22               359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23               360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24               361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25               362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26               363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27               364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28               365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29               366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30               367
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MT6885_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97/isrentry.h b/mcu/interface/driver/devdrv/cirq/md97/isrentry.h
new file mode 100644
index 0000000..7fa5cf2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97/isrentry.h
@@ -0,0 +1,107 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   isrentry.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*******************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2001
+*
+*******************************************************************************/
+
+#ifndef _ISRENTRY_H
+#define _ISRENTRY_H
+
+#include "kal_general_types.h"
+
+/*************************************************************************
+ * Define data structures.
+ *************************************************************************/
+
+typedef struct 
+{
+   kal_uint32 vector;
+   void (*lisr_handler) (kal_uint32);
+   kal_char *description;
+} irqlisr_entry;
+
+/*************************************************************************
+ * Define function prototypes.
+ *************************************************************************/
+#define IRQ_Default_LISR MDCIRQ_IRQ_Default_LISR
+
+void MDCIRQ_IRQ_LISR_Init(void);
+void MDCIRQ_IRQ_Default_LISR(kal_uint32);
+
+
+#endif /* _ISRENTRY_H */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl.h b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl.h
new file mode 100644
index 0000000..9228b1b
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl.h
@@ -0,0 +1,294 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *   Common type and structure definition for MediaTek GSM/GPRS software
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _INTRCTRL_H
+#define _INTRCTRL_H
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "mips_ia_utils_public.h"
+#include "us_timer.h"
+#include "kal_public_api.h"
+
+#if defined(MERCURY)
+#include "intrCtrl_MERCURY.h"
+#endif
+
+/*******************************************************************************
+ * Declarations and Definitions
+ *******************************************************************************/
+#define __ENABLE_SW_TRIGGER_INTERRUPT__
+
+#define EDGE_SENSITIVE           KAL_TRUE
+#define LEVEL_SENSITIVE          KAL_FALSE
+
+#define IRQ_NOT_LISR_CONTEXT     (0xFFFF)
+
+#if defined(__CIRQ_MASK_REG_NR_1_NEW__) || defined(__CIRQ_MASK_REG_NR_2_NEW__) || defined(__CIRQ_MASK_REG_NR_3_NEW__) || defined(__CIRQ_MASK_REG_NR_4_NEW__) || defined(__CIRQ_MASK_REG_NR_5_NEW__)
+#define __CIRQ_DESIGN_NEW__
+#endif
+
+typedef struct CIRQ_MASK_VALUE_STRUCT
+{
+    kal_uint32 irq_mask[12]; 
+} CIRQ_MASK_VALUE_T;
+
+/* To enable SW Trigger Interrupt for new BB chips
+   Need to modify 3 files
+   1. add a file intrCtrl_MTxxxx_SW_Handler.h
+   2. add an entry on intrCtrl_SW_Handler.h
+   3. modify IRQ_SetSWRegister & IRQ_ResetSWRegister to support BB Chips on intrCtrl.c  */
+#if defined(__ENABLE_SW_TRIGGER_INTERRUPT__)
+typedef enum
+{
+#define X_SW_HANDLE_CONST(a, b, c) a=(b),
+#include "intrCtrl_SW_Handle.h"
+#undef X_SW_HANDLE_CONST
+    SW_HANDLE_END
+} SW_CODE_HANDLE;
+
+#define Activate_LISR(code) MDCIRQ_Activate_LISR(code)
+#define Deactivate_LISR(code) MDCIRQ_Deactivate_LISR(code)
+
+extern void MDCIRQ_Activate_LISR(SW_CODE_HANDLE code);
+extern void MDCIRQ_Deactivate_LISR(SW_CODE_HANDLE code);
+extern void MDCIRQ_Activate_LISR_without_ITC(SW_CODE_HANDLE code);
+extern void MDCIRQ_Deactivate_LISR_without_ITC(SW_CODE_HANDLE code);
+extern const kal_uint16 SW_Code_Handle2Code[NUM_IRQ_SOURCES];
+
+/* Use to translate the mapping between software handler to hardware interrupt code */
+#define SW_code_handle2code(a)  (a)
+
+extern kal_uint32 SW_INT_Counter[NUM_IRQ_SOURCES];
+
+#endif /* __ENABLE_SW_TRIGGER_INTERRUPT__ */
+
+
+#define IRQClearInt(vector) MDCIRQ_IRQClearInt(vector)
+#define IRQMask(vector) MDCIRQ_IRQMask(vector)
+#define IRQUnmask(vector) MDCIRQ_IRQUnmask(vector)
+#define IRQSensitivity(vector, e) MDCIRQ_IRQSensitivity(vector, e)
+#define IRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code) MDCIRQ_VPE_SPL_Compare_with_IRQ_Priority(VPE, code)
+
+
+extern kal_uint32 SaveAndSetIRQMask(void);
+extern void RestoreIRQMask(kal_uint32);
+extern void MDCIRQ_IRQClearInt(kal_uint16);
+extern void MDCIRQ_IRQMask(kal_uint16);
+extern void MDCIRQ_IRQUnmask(kal_uint16);
+extern void MDCIRQ_IRQSensitivity(kal_uint16, kal_bool);
+extern void initINTR(void);
+extern kal_uint32 IRQMask_Status(kal_uint16 code);
+extern kal_uint32 IRQ_Status(void);
+
+
+#define IRQ_Register_LISR(code, lisr, description) \
+    MDCIRQ_IRQ_Register_LISR(code, (void*)lisr, description)
+extern void MDCIRQ_IRQ_Register_LISR(kal_uint16 code, void (*reg_lisr)(kal_uint32 vector), char* description);
+
+#define NRIRQ_Affinity_Change_NSA() MDCIRQ_Runtime_Change_NRIRQ_Affinity_NSA()
+#define NRIRQ_Affinity_Change_SA() MDCIRQ_Runtime_Change_NRIRQ_Affinity_SA()
+extern void MDCIRQ_Runtime_Change_NRIRQ_Affinity_NSA();
+extern void MDCIRQ_Runtime_Change_NRIRQ_Affinity_SA();
+
+#define LTEIRQ_Affinity_Change_ENDC() MDCIRQ_Runtime_Change_LTEIRQ_Affinity_ENDC()
+#define LTEIRQ_Affinity_Change_LTEONLY() MDCIRQ_Runtime_Change_LTEIRQ_Affinity_LTEONLY()
+extern void MDCIRQ_Runtime_Change_LTEIRQ_Affinity_ENDC();
+extern void MDCIRQ_Runtime_Change_LTEIRQ_Affinity_LTEONLY();
+
+extern void initVPEIRQ(void);
+
+extern kal_uint32 sst_dhl_irq_count[];
+extern kal_uint32 sst_dhl_irq_caller[];
+extern kal_uint32 DHLIrqCounter[];
+
+extern kal_int32 INC_Initialize_State;
+
+typedef enum
+{
+#define IRQ_PRIORITY_CONST(a) a##_PRIORITY,
+#include "irqPriority.h"
+#undef IRQ_PRIORITY_CONST
+    IRQ_PRIORITY_END,
+    IRQ_HRT_PRIORITY_THRESHOLD = IRQ_SW_LISR40_CODE_PRIORITY + 1,
+    IRQ_EQUALLY_DISPATCH_PRIORITY_THRESHOLD = IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE_PRIORITY,
+} IRQ_PRIORITY;
+
+typedef enum {
+    MDCIRQ_To_BUS_Normal = 0x0,
+    MDCIRQ_To_BUS_PreUltra = 0x1,
+    MDCIRQ_To_BUS_Ultra =0x2,
+} MDCIRQ_Bus_QoS_Signal;
+
+/***********************************
+NOTE:
+1. below API is only for L1 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define IF_DI_OR_LISR()     (Ibit_Status()==0 || kal_if_lisr())
+
+/***********************************
+NOTE:
+1. below API is only for L2 logging, please not use
+2. if you want to use, please confirm with CIRQ owner first
+***********************************/
+#define __IRQ_LOCK_WITHOUT_CHECK__
+#define __NESTED_DI_CHECK__
+
+#if defined(__L2_LOGGING_IRQ_LOC__)
+#if defined(__IRQ_LOCK_WITHOUT_CHECK__) && (defined(__MIPS_IA__) || defined(__MIPS_I7200__))
+#if defined(__NESTED_DI_CHECK__) && !defined (__ESL_MASE_GEN97__)
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+    kal_uint32 vpe_num = 0;\
+    miu_mt_dmt();\
+    __asm__ __volatile__\
+    (\
+        "di %0\n\t"\
+        "ehb\n\t"\
+        :"=&r"(oldmask), "=&r"(newmask)\
+        :\
+        :"$31","memory"\
+    );\
+    oldmask &= 0x1;\
+    vpe_num = miu_get_current_vpe_id();\
+    sst_dhl_irq_count[vpe_num]++;\
+    sst_dhl_irq_caller[vpe_num] = (kal_uint32)__builtin_return_address(0);\
+    DHLIrqCounter[vpe_num] = ust_get_current_time();\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+    kal_uint32 tmp=1;\
+    sst_dhl_irq_count[miu_get_current_vpe_id()]--;\
+    __asm__ __volatile__\
+    (\
+        "bne %0, %1, END\n\t"\
+        "ei\n\t"\
+        "ehb\n\t"\
+        "END:emt\n\t"\
+        "ehb\n\t"\
+        :\
+        :"r"(oldmask), "r"(tmp)\
+        :"memory"\
+    );\
+} while(0)
+#else
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{\
+    miu_mt_dmt();\
+    __asm__ __volatile__\
+    (\
+        "di %0\n\t"\
+        "ehb\n\t"\
+        :"=&r"(oldmask), "=&r"(newmask)\
+        :\
+        :"$31","memory"\
+    );\
+    oldmask &= 0x1;\
+} while(0)
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{\
+    kal_uint32 tmp=1;\
+    __asm__ __volatile__\
+    (\
+        "bne %0, %1, END\n\t"\
+        "ei\n\t"\
+        "ehb\n\t"\
+        "END:emt\n\t"\
+        "ehb\n\t"\
+        :\
+        :"r"(oldmask), "r"(tmp)\
+        :"memory"\
+    );\
+} while(0)
+#endif
+
+#else
+
+#define LOCK_CPU_INTERRUPT(oldmask, newmask) \
+do{ \
+	oldmask = kal_hrt_SaveAndSetIRQMask(); \
+}while(0);
+
+#define UNLOCK_CPU_INTERRUPT(oldmask) \
+do{ \
+	kal_hrt_RestoreIRQMask(oldmask); \
+}while(0);
+
+#endif
+#endif
+
+#endif /* _INTRCTRL_H */
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY.h b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY.h
new file mode 100644
index 0000000..9ab9a29
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY.h
@@ -0,0 +1,561 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MERCURY.h
+ *
+ * Project:
+ * --------
+ *   MERCURY
+ *
+ * Description:
+ * ------------
+ *   Definition for chipset interrupt table
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __INTRCTRL_MERCURY_H__
+#define __INTRCTRL_MERCURY_H__
+
+
+#include "reg_base.h"
+#include "irqid.h"
+#include "kal_public_api.h"
+#include "isrentry.h"
+#include "hisr_config.h"
+
+
+#define NUM_IRQ_SOURCES          (368)
+
+/* CIRQ Interrupt Sources */
+#define    IRQ_USIM0_CODE                            MD_IRQID_USIM0
+#define    IRQ_USIM1_CODE                            MD_IRQID_USIM1
+#define    IRQ_TDMA_CTIRQ1_CODE                      MD_IRQID_TDMA_CTIRQ1
+#define    IRQ_TDMA_CTIRQ2_CODE                      MD_IRQID_TDMA_CTIRQ2
+#define    IRQ_TDMA_CTIRQ3_CODE                      MD_IRQID_TDMA_CTIRQ3
+#define    IRQ_TDMA_WAKEUP_IRQ_CODE                  MD_IRQID_TDMA_WAKEUP_IRQ
+#define    IRQ_OST_CODE                              MD_IRQID_OST
+#define    IRQ_MDRTT_CODE                            MD_IRQID_MDRTT
+#define    IRQ_MDEVDO_CODE                           MD_IRQID_MDEVDO
+#define    IRQ_ULSP_LOG_MCU_RT_INT_CODE              MD_IRQID_ULSP_LOG_MCU_RT_INT
+#define    IRQ_ULSP_LOG_MCU_OD_INT_CODE              MD_IRQID_ULSP_LOG_MCU_OD_INT
+#define    IRQ_ULSP_LOG_DSP4G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_RT_INT
+#define    IRQ_ULSP_LOG_DSP4G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP4G_OD_INT
+#define    IRQ_ULSP_LOG_DSP5G_RT_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_RT_INT
+#define    IRQ_ULSP_LOG_DSP5G_OD_INT_CODE            MD_IRQID_ULSP_LOG_DSP5G_OD_INT
+#define    IRQ_SHARE_D12MINT1_CODE                   MD_IRQID_SHARE_D12MINT1
+#define    IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE       MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ
+#define    IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE        MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ
+#define    IRQ_AIRQ_SERDES_CODE                      MD_IRQID_AIRQ_SERDES
+#define    IRQ_AIRQ_COS_CODE                         MD_IRQID_AIRQ_COS
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR
+#define    IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE         MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR
+#define    IRQ_PPPHA_ENC0_INT_CODE                   MD_IRQID_PPPHA_ENC0_INT
+#define    IRQ_PPPHA_ENC1_INT_CODE                   MD_IRQID_PPPHA_ENC1_INT
+#define    IRQ_PPPHA_DEC0_INT_CODE                   MD_IRQID_PPPHA_DEC0_INT
+#define    IRQ_PPPHA_DEC1_INT_CODE                   MD_IRQID_PPPHA_DEC1_INT
+#define    IRQ_CS_NR_IRQ_CODE                        MD_IRQID_CS_NR_IRQ
+#define    IRQ_CS_NR_ERR_IRQ_CODE                    MD_IRQID_CS_NR_ERR_IRQ
+#define    IRQ_SDF_OVERFLOW_IRQ_CODE                 MD_IRQID_SDF_OVERFLOW_IRQ
+#define    IRQ_MCUMMU_INT_CODE                       MD_IRQID_MCUMMU_INT
+#define    IRQ_BIGRAM_0_IRQ_0_CODE                   MD_IRQID_BIGRAM_0_IRQ_0
+#define    IRQ_COS_PREP_INT_CODE                     MD_IRQID_COS_PREP_INT
+#define    IRQ_TRACE_INT_CODE                        MD_IRQID_TRACE_INT
+#define    IRQ_NR_TIMER_IRQ0_CODE                    MD_IRQID_NR_TIMER_IRQ0
+#define    IRQ_NR_TIMER_IRQ1_CODE                    MD_IRQID_NR_TIMER_IRQ1
+#define    IRQ_NR_TIMER_IRQ2_CODE                    MD_IRQID_NR_TIMER_IRQ2
+#define    IRQ_NR_TIMER_IRQ3_CODE                    MD_IRQID_NR_TIMER_IRQ3
+#define    IRQ_NR_TIMER_IRQ4_CODE                    MD_IRQID_NR_TIMER_IRQ4
+#define    IRQ_NR_TIMER_IRQ5_CODE                    MD_IRQID_NR_TIMER_IRQ5
+#define    IRQ_NR_TIMER_IRQ6_CODE                    MD_IRQID_NR_TIMER_IRQ6
+#define    IRQ_NR_TIMER_IRQ7_CODE                    MD_IRQID_NR_TIMER_IRQ7
+#define    IRQ_NR_TIMER_IRQ8_CODE                    MD_IRQID_NR_TIMER_IRQ8
+#define    IRQ_NR_TIMER_IRQ9_CODE                    MD_IRQID_NR_TIMER_IRQ9
+#define    IRQ_NR_TIMER_IRQ10_CODE                   MD_IRQID_NR_TIMER_IRQ10
+#define    IRQ_NR_TIMER_IRQ11_CODE                   MD_IRQID_NR_TIMER_IRQ11
+#define    IRQ_NR_TIMER_IRQ12_CODE                   MD_IRQID_NR_TIMER_IRQ12
+#define    IRQ_NR_TIMER_IRQ13_CODE                   MD_IRQID_NR_TIMER_IRQ13
+#define    IRQ_NR_TIMER_IRQ14_CODE                   MD_IRQID_NR_TIMER_IRQ14
+#define    IRQ_NR_TIMER_IRQ15_CODE                   MD_IRQID_NR_TIMER_IRQ15
+#define    IRQ_NR_TIMER_IRQ16_CODE                   MD_IRQID_NR_TIMER_IRQ16
+#define    IRQ_NR_TIMER_IRQ17_CODE                   MD_IRQID_NR_TIMER_IRQ17
+#define    IRQ_NR_TIMER_IRQ18_CODE                   MD_IRQID_NR_TIMER_IRQ18
+#define    IRQ_NR_TIMER_IRQ19_CODE                   MD_IRQID_NR_TIMER_IRQ19
+#define    IRQ_NR_TIMER_IRQ20_CODE                   MD_IRQID_NR_TIMER_IRQ20
+#define    IRQ_NR_TIMER_IRQ21_CODE                   MD_IRQID_NR_TIMER_IRQ21
+#define    IRQ_NR_TIMER_IRQ22_CODE                   MD_IRQID_NR_TIMER_IRQ22
+#define    IRQ_NR_TIMER_IRQ23_CODE                   MD_IRQID_NR_TIMER_IRQ23
+#define    IRQ_NR_TIMER_IRQ24_CODE                   MD_IRQID_NR_TIMER_IRQ24
+#define    IRQ_NR_TIMER_IRQ25_CODE                   MD_IRQID_NR_TIMER_IRQ25
+#define    IRQ_NR_TIMER_IRQ26_CODE                   MD_IRQID_NR_TIMER_IRQ26
+#define    IRQ_NR_TIMER_IRQ27_CODE                   MD_IRQID_NR_TIMER_IRQ27
+#define    IRQ_NR_TIMER_IRQ28_CODE                   MD_IRQID_NR_TIMER_IRQ28
+#define    IRQ_NR_TIMER_IRQ29_CODE                   MD_IRQID_NR_TIMER_IRQ29
+#define    IRQ_NR_TIMER_IRQ30_CODE                   MD_IRQID_NR_TIMER_IRQ30
+#define    IRQ_NR_TIMER_IRQ31_CODE                   MD_IRQID_NR_TIMER_IRQ31
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE        MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16
+#define    IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE       MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17
+#define    IRQ_NR_TIMER_CNTDN_IRQ0_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ0
+#define    IRQ_NR_TIMER_CNTDN_IRQ1_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ1
+#define    IRQ_NR_TIMER_CNTDN_IRQ2_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ2
+#define    IRQ_NR_TIMER_CNTDN_IRQ3_CODE              MD_IRQID_NR_TIMER_CNTDN_IRQ3
+#define    IRQ_NR_EVENTGEN_SPU_CODE                  MD_IRQID_NR_EVENTGEN_SPU
+#define    IRQ_SI_CM_ERR_CODE                        MD_IRQID_SI_CM_ERR
+#define    IRQ_SI_CM_PCINT_CODE                      MD_IRQID_SI_CM_PCINT
+#define    IRQ_MDM2C_U3G_CODE                        MD_IRQID_MDM2C_U3G
+#define    IRQ_RAKE_CMIF_M2C_IRQ_0_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_0
+#define    IRQ_RAKE_CMIF_M2C_IRQ_1_CODE              MD_IRQID_RAKE_CMIF_M2C_IRQ_1
+#define    IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FPC_1X_IRQ
+#define    IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE             MD_IRQID_RAKE_CMIF_FOE_1X_IRQ
+#define    IRQ_RAKE_CMIF_PD_DO_IRQ_CODE              MD_IRQID_RAKE_CMIF_PD_DO_IRQ
+#define    IRQ_MDMCU_BUSMON_MATCH_STS_CODE           MD_IRQID_MDMCU_BUSMON_MATCH_STS
+#define    IRQ_MDINFRA_BUSMON_MATCH_STS_CODE         MD_IRQID_MDINFRA_BUSMON_MATCH_STS
+#define    IRQ_ELMTOP_EMI_IRQ_CODE                   MD_IRQID_ELMTOP_EMI_IRQ
+#define    IRQ_ELM_DMA_IRQ_CODE                      MD_IRQID_ELM_DMA_IRQ
+#define    IRQ_BUSMPU_IRQ_CODE                       MD_IRQID_BUSMPU_IRQ
+#define    IRQ_ST1X_CPINT_CODE                       MD_IRQID_ST1X_CPINT
+#define    IRQ_ST1x_HALF_CPINT_CODE                  MD_IRQID_ST1x_HALF_CPINT
+#define    IRQ_ST1x_CFG_CPINT_CODE                   MD_IRQID_ST1x_CFG_CPINT
+#define    IRQ_ST1x_WAKEUP_IRQ_CODE                  MD_IRQID_ST1x_WAKEUP_IRQ
+#define    IRQ_STDO_CPINT_CODE                       MD_IRQID_STDO_CPINT
+#define    IRQ_STDO_HALF_CPINT_CODE                  MD_IRQID_STDO_HALF_CPINT
+#define    IRQ_STDO_CFG_CPINT_CODE                   MD_IRQID_STDO_CFG_CPINT
+#define    IRQ_STDO_WAKEUP_IRQ_CODE                  MD_IRQID_STDO_WAKEUP_IRQ
+#define    IRQ_UART_MD0_CODE                         MD_IRQID_UART_MD0
+#define    IRQ_UART_MD1_CODE                         MD_IRQID_UART_MD1
+#define    IRQ_EINT0_CODE                            MD_IRQID_EINT0
+#define    IRQ_EINT1_CODE                            MD_IRQID_EINT1
+#define    IRQ_EINT2_CODE                            MD_IRQID_EINT2
+#define    IRQ_EINT3_CODE                            MD_IRQID_EINT3
+#define    IRQ_EINT_SHARE_CODE                       MD_IRQID_EINT_SHARE
+#define    IRQ_GPTM1_CODE                            MD_IRQID_GPTM1
+#define    IRQ_GPTM2_CODE                            MD_IRQID_GPTM2
+#define    IRQ_GPTM3_CODE                            MD_IRQID_GPTM3
+#define    IRQ_GPTM4_CODE                            MD_IRQID_GPTM4
+#define    IRQ_GPTM5_CODE                            MD_IRQID_GPTM5
+#define    IRQ_GPTM6_CODE                            MD_IRQID_GPTM6
+#define    IRQ_GPTM7_CODE                            MD_IRQID_GPTM7
+#define    IRQ_GPTM8_CODE                            MD_IRQID_GPTM8
+#define    IRQ_GPTM9_CODE                            MD_IRQID_GPTM9
+#define    IRQ_GPTM10_CODE                           MD_IRQID_GPTM10
+#define    IRQ_GPTM11_CODE                           MD_IRQID_GPTM11
+#define    IRQ_IDC_PM_INT_CODE                       MD_IRQID_IDC_PM_INT
+#define    IRQ_IDC_UART_IRQ_CODE                     MD_IRQID_IDC_UART_IRQ
+#define    IRQ_MDGDMA_FDMA5_CODE                     MD_IRQID_MDGDMA_FDMA5
+#define    IRQ_MDGDMA_FDMA6_CODE                     MD_IRQID_MDGDMA_FDMA6
+#define    IRQ_TDMA_CTIRQ4_CODE                      MD_IRQID_TDMA_CTIRQ4
+#define    IRQ_PDMA_CODE                             MD_IRQID_PDMA
+#define    IRQ_MDINFRA_BUS_DECERROR_CODE             MD_IRQID_MDINFRA_BUS_DECERROR
+#define    IRQ_I2C_TOP_INT_CODE                      MD_IRQID_I2C_TOP_INT
+#define    IRQ_SOE_CODE                              MD_IRQID_SOE
+#define    IRQ_ABM_INT_CODE                          MD_IRQID_ABM_INT
+#define    IRQ_ABM_ERROR_INT_CODE                    MD_IRQID_ABM_ERROR_INT
+#define    IRQ_USIP0_CODE                            MD_IRQID_USIP0
+#define    IRQ_USIP1_CODE                            MD_IRQID_USIP1
+#define    IRQ_USIP2_CODE                            MD_IRQID_USIP2
+#define    IRQ_USIP3_CODE                            MD_IRQID_USIP3
+#define    IRQ_USIP4_CODE                            MD_IRQID_USIP4
+#define    IRQ_USIP5_CODE                            MD_IRQID_USIP5
+#define    IRQ_USIP6_CODE                            MD_IRQID_USIP6
+#define    IRQ_USIP7_CODE                            MD_IRQID_USIP7
+#define    IRQ_USIP8_CODE                            MD_IRQID_USIP8
+#define    IRQ_USIP9_CODE                            MD_IRQID_USIP9
+#define    IRQ_USIP10_CODE                           MD_IRQID_USIP10
+#define    IRQ_USIP11_CODE                           MD_IRQID_USIP11
+#define    IRQ_USIP12_CODE                           MD_IRQID_USIP12
+#define    IRQ_USIP13_CODE                           MD_IRQID_USIP13
+#define    IRQ_TX_NR_CC0_IRQ_CODE                    MD_IRQID_TX_NR_CC0_IRQ
+#define    IRQ_TX_NR_CC1_IRQ_CODE                    MD_IRQID_TX_NR_CC1_IRQ
+#define    IRQ_TX_NR_ERR_CC_IRQ_CODE                 MD_IRQID_TX_NR_ERR_CC_IRQ
+#define    IRQ_MDMCU_SPU_IRQ_CODE                    MD_IRQID_MDMCU_SPU_IRQ
+#define    IRQ_DEM_TRIG_PS_INT_LE_CODE               MD_IRQID_DEM_TRIG_PS_INT_LE
+#define    IRQ_ECT_CODE                              MD_IRQID_ECT
+#define    IRQ_MDMCU_BUS_DECERR_IRQ_CODE             MD_IRQID_MDMCU_BUS_DECERR_IRQ
+#define    IRQ_MDMCU_OSTD_THROTTLE_CODE              MD_IRQID_MDMCU_OSTD_THROTTLE
+#define    IRQ_SHAOLIN_OSTD_THROTTLE_CODE            MD_IRQID_SHAOLIN_OSTD_THROTTLE
+#define    IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE         MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ
+#define    IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_AP2MD_CONN_WF_CCIF_0_CODE             MD_IRQID_AP2MD_CONN_WF_CCIF_0
+#define    IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE   MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ
+#define    IRQ_AP2MD_CONN_WF_CCIF_1_CODE             MD_IRQID_AP2MD_CONN_WF_CCIF_1
+#define    IRQ_MDWDT_CODE                            MD_IRQID_MDWDT
+#define    IRQ_MDGDMA_FDMA0_2_CODE                   MD_IRQID_MDGDMA_FDMA0_2
+#define    IRQ_MDGDMA_FDMA1_CODE                     MD_IRQID_MDGDMA_FDMA1
+#define    IRQ_MDGDMA_FDMA3_CODE                     MD_IRQID_MDGDMA_FDMA3
+#define    IRQ_MDGDMA_FDMA4_CODE                     MD_IRQID_MDGDMA_FDMA4
+#define    IRQ_MDGDMA_HDMA0_1_CODE                   MD_IRQID_MDGDMA_HDMA0_1
+#define    IRQ_MDGDMA_HDMA2_3_CODE                   MD_IRQID_MDGDMA_HDMA2_3
+#define    IRQ_AP2MD_CCIF0_0_CODE                    MD_IRQID_AP2MD_CCIF0_0
+#define    IRQ_AP2MD_CCIF0_1_CODE                    MD_IRQID_AP2MD_CCIF0_1
+#define    IRQ_AP2MD_CCIF1_0_CODE                    MD_IRQID_AP2MD_CCIF1_0
+#define    IRQ_AP2MD_CCIF1_1_CODE                    MD_IRQID_AP2MD_CCIF1_1
+#define    IRQ_IEBIT_CHECK_IRQ0_CODE                 MD_IRQID_IEBIT_CHECK_IRQ0
+#define    IRQ_IEBIT_CHECK_IRQ1_CODE                 MD_IRQID_IEBIT_CHECK_IRQ1
+#define    IRQ_IEBIT_CHECK_IRQ2_CODE                 MD_IRQID_IEBIT_CHECK_IRQ2
+#define    IRQ_IEBIT_CHECK_IRQ3_CODE                 MD_IRQID_IEBIT_CHECK_IRQ3
+#define    IRQ_IEBIT_CHECK_IRQ4_CODE                 MD_IRQID_IEBIT_CHECK_IRQ4
+#define    IRQ_IEBIT_CHECK_IRQ5_CODE                 MD_IRQID_IEBIT_CHECK_IRQ5
+#define    IRQ_IEBIT_CHECK_IRQ6_CODE                 MD_IRQID_IEBIT_CHECK_IRQ6
+#define    IRQ_IEBIT_CHECK_IRQ7_CODE                 MD_IRQID_IEBIT_CHECK_IRQ7
+#define    IRQ_IEBIT_CHECK_IRQ8_CODE                 MD_IRQID_IEBIT_CHECK_IRQ8
+#define    IRQ_IEBIT_CHECK_IRQ9_CODE                 MD_IRQID_IEBIT_CHECK_IRQ9
+#define    IRQ_IEBIT_CHECK_IRQ10_CODE                MD_IRQID_IEBIT_CHECK_IRQ10
+#define    IRQ_IEBIT_CHECK_IRQ11_CODE                MD_IRQID_IEBIT_CHECK_IRQ11
+#define    IRQ_NRL2_HRT_CODE                         MD_IRQID_NRL2_HRT
+#define    IRQ_NRL2_NOTIF_CODE                       MD_IRQID_NRL2_NOTIF
+#define    IRQ_NRL2_EXCEP_CODE                       MD_IRQID_NRL2_EXCEP
+#define    IRQ_NRL2_DPMAIF_MD_CODE                   MD_IRQID_NRL2_DPMAIF_MD
+#define    IRQ_RXDFE_IRQ0_CODE                       MD_IRQID_RXDFE_IRQ0
+#define    IRQ_IDC_UART_TX_FORCE_ON_CODE             MD_IRQID_IDC_UART_TX_FORCE_ON
+#define    IRQ_RXDFE_IRQ2_CODE                       MD_IRQID_RXDFE_IRQ2
+#define    IRQ_RXDFE_IRQ3_CODE                       MD_IRQID_RXDFE_IRQ3
+#define    IRQ_AP2MD_CONN_BGF_CCIF_0_CODE            MD_IRQID_AP2MD_CONN_BGF_CCIF_0
+#define    IRQ_MD_RXDFE_BB_DUMP_CODE                 MD_IRQID_MD_RXDFE_BB_DUMP
+#define    IRQ_AP2MD_CONN_BGF_CCIF_1_CODE            MD_IRQID_AP2MD_CONN_BGF_CCIF_1
+#define    IRQ_TXCRP_CODE                            MD_IRQID_TXCRP
+#define    IRQ_CM_NR_IRQ_CODE                        MD_IRQID_CM_NR_IRQ
+#define    IRQ_CM_NR_ERR_IRQ_CODE                    MD_IRQID_CM_NR_ERR_IRQ
+#define    IRQ_L1_LTE_SLEEP_IRQ_CODE                 MD_IRQID_L1_LTE_SLEEP_IRQ
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7
+#define    IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE    MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8
+#define    IRQ_D_GDMA_0_IRQ_CODE                     MD_IRQID_D_GDMA_0_IRQ
+#define    IRQ_D_GDMA_1_IRQ_CODE                     MD_IRQID_D_GDMA_1_IRQ
+#define    IRQ_D_GDMA_2_IRQ_CODE                     MD_IRQID_D_GDMA_2_IRQ
+#define    IRQ_D_GDMA_3_IRQ_CODE                     MD_IRQID_D_GDMA_3_IRQ
+#define    IRQ_D_GDMA_4_IRQ_CODE                     MD_IRQID_D_GDMA_4_IRQ
+#define    IRQ_D_GDMA_5_IRQ_CODE                     MD_IRQID_D_GDMA_5_IRQ
+#define    IRQ_PLL_GEARHP_RDY_CODE                   MD_IRQID_PLL_GEARHP_RDY
+#define    IRQ_REQ_ABNORM_IRQ_CODE                   MD_IRQID_REQ_ABNORM_IRQ
+#define    IRQ_NRL2_DPMAIF_MDMCU_CODE                MD_IRQID_NRL2_DPMAIF_MDMCU
+#define    IRQ_AP2MD_APWDT_IRQ_CODE                  MD_IRQID_AP2MD_APWDT_IRQ
+#define    IRQ_DUMMY_PRIORITY_CODE_3                 MD_IRQID_DUMMY_PRIORITY_IRQ3
+#define    IRQ_DUMMY_PRIORITY_CODE_4                 MD_IRQID_DUMMY_PRIORITY_IRQ4
+#define    IRQ_DUMMY_PRIORITY_CODE_5                 MD_IRQID_DUMMY_PRIORITY_IRQ5
+#define    IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE             MD_IRQID_L1M_PHY_LTMR_SPU_IRQ
+#define    IRQ_L1M_PHY_LTMR_IRQ_0_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_0
+#define    IRQ_L1M_PHY_LTMR_IRQ_1_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_1
+#define    IRQ_L1M_PHY_LTMR_IRQ_2_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_2
+#define    IRQ_L1M_PHY_LTMR_IRQ_3_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_3
+#define    IRQ_L1M_PHY_LTMR_IRQ_4_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_4
+#define    IRQ_L1M_PHY_LTMR_IRQ_5_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_5
+#define    IRQ_L1M_PHY_LTMR_IRQ_6_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_6
+#define    IRQ_L1M_PHY_LTMR_IRQ_7_CODE               MD_IRQID_L1M_PHY_LTMR_IRQ_7
+#define    IRQ_DUMMY_PRIORITY_CODE_6                 MD_IRQID_DUMMY_PRIORITY_IRQ6
+#define    IRQ_L1_LTE_WAKEUP_IRQ_CODE                MD_IRQID_L1_LTE_WAKEUP_IRQ
+#define    IRQ_TDD_WAKEUP_IRQ_CODE                   MD_IRQID_TDD_WAKEUP_IRQ
+#define    IRQ_TDD_TIMER_L1D_1_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_1_IRQ
+#define    IRQ_TDD_TIMER_L1D_2_IRQ_CODE              MD_IRQID_TDD_TIMER_L1D_2_IRQ
+#define    IRQ_RTR_SLT_0_IRQ_CODE                    MD_IRQID_RTR_SLT_0_IRQ
+#define    IRQ_RTR_SLT_1_IRQ_CODE                    MD_IRQID_RTR_SLT_1_IRQ
+#define    IRQ_FDD_SLP_IRQ_CODE                      MD_IRQID_FDD_SLP_IRQ
+#define    IRQ_IRDBG_MCU_INT_CODE                    MD_IRQID_IRDBG_MCU_INT
+#define    IRQ_MD_DVFS_CTRL_IRQ_0_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_0
+#define    IRQ_MD_DVFS_CTRL_IRQ_1_CODE               MD_IRQID_MD_DVFS_CTRL_IRQ_1
+#define    IRQ_NR_SLP_WAKEUP_CODE                    MD_IRQID_NR_SLP_WAKEUP
+#define    IRQ_NR_SLP_SLEEP_CODE                     MD_IRQID_NR_SLP_SLEEP
+#define    IRQ_NR_TIMER_ERR_CODE                     MD_IRQID_NR_TIMER_ERR
+#define    IRQ_TXBSRP_CODE                           MD_IRQID_TXBSRP
+#define    IRQ_TXDFE_D_CODE                          MD_IRQID_TXDFE_D
+#define    IRQ_NR_EVENTGEN_ERR_CODE                  MD_IRQID_NR_EVENTGEN_ERR
+#define    IRQ_AIRQ_PAD_CODE                         MD_IRQID_AIRQ_PAD
+#define    IRQ_CSSYS_FDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_FDD_CS_IRQ
+#define    IRQ_CSSYS_TDD_CS_IRQ_CODE                 MD_IRQID_CSSYS_TDD_CS_IRQ
+#define    IRQ_CSSYS_LTE_CS_IRQ_CODE                 MD_IRQID_CSSYS_LTE_CS_IRQ
+#define    IRQ_CSSYS_1X_CS_IRQ_CODE                  MD_IRQID_CSSYS_1X_CS_IRQ
+#define    IRQ_CSSYS_DO_CS_IRQ_CODE                  MD_IRQID_CSSYS_DO_CS_IRQ
+#define    IRQ_PCIE_INTERRUPT_OUT_CODE               MD_IRQID_PCIE_INTERRUPT_OUT
+#define    IRQ_UCNT_SCH_IRQ_CODE                     MD_IRQID_UCNT_SCH_IRQ
+#define    IRQ_UCNT_ERR_IRQ_CODE                     MD_IRQID_UCNT_ERR_IRQ
+#define    IRQ_UCNT_ADJ_IRQ_CODE                     MD_IRQID_UCNT_ADJ_IRQ
+#define    IRQ_SL_WAITSLEEP_CODE                     MD_IRQID_SL_WAITSLEEP
+#define    IRQ_PTP_THERM_INT_INT_CODE                MD_IRQID_PTP_THERM_INT_INT
+#define    IRQ_PTP_FSM_INT_CODE                      MD_IRQID_PTP_FSM_INT
+#define    IRQ_AP2MD_DAPC_CODE                       MD_IRQID_AP2MD_DAPC
+#define    IRQ_AP2MD_CCIF2_CODE                      MD_IRQID_AP2MD_CCIF2
+#define    IRQ_AP2MD_UFS_CODE                        MD_IRQID_AP2MD_UFS
+#define    IRQ_SSUSB_INTERRUPT_OUT_CODE              MD_IRQID_SSUSB_INTERRUPT_OUT
+#define    IRQ_AP2MD_MSDC0_CODE                      MD_IRQID_AP2MD_MSDC0
+#define    IRQ_MIPI_IRQ_CODE                         MD_IRQID_MIPI_IRQ
+#define    IRQ_CONN_BT_ISOCH_CODE                    MD_IRQID_CONN_BT_ISOCH
+#define    IRQ_RMPU_CTIREIGIN_CODE                   MD_IRQID_RMPU_CTIREIGIN
+#define    IRQ_FREQM_IRQ_CODE                        MD_IRQID_FREQM_IRQ
+#define    IRQ_BT_CVSD_CODE                          MD_IRQID_BT_CVSD
+#define    IRQ_SW_LISR0_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_0
+#define    IRQ_SW_LISR1_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_1
+#define    IRQ_SW_LISR2_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_2
+#define    IRQ_SW_LISR3_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_3
+#define    IRQ_SW_LISR4_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_4
+#define    IRQ_SW_LISR5_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_5
+#define    IRQ_SW_LISR6_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_6
+#define    IRQ_SW_LISR7_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_7
+#define    IRQ_SW_LISR8_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_8
+#define    IRQ_SW_LISR9_CODE                         MD_IRQID_SW_TRIGGER_RESERVED_9
+#define    IRQ_SW_LISR10_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_10
+#define    IRQ_SW_LISR11_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_11
+#define    IRQ_SW_LISR12_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_12
+#define    IRQ_SW_LISR13_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_13
+#define    IRQ_SW_LISR14_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_14
+#define    IRQ_SW_LISR15_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_15
+#define    IRQ_SW_LISR16_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_16
+#define    IRQ_SW_LISR17_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_17
+#define    IRQ_SW_LISR18_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_18
+#define    IRQ_SW_LISR19_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_19
+#define    IRQ_SW_LISR20_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_20
+#define    IRQ_SW_LISR21_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_21
+#define    IRQ_SW_LISR22_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_22
+#define    IRQ_SW_LISR23_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_23
+#define    IRQ_SW_LISR24_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_24
+#define    IRQ_SW_LISR25_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_25
+#define    IRQ_SW_LISR26_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_26
+#define    IRQ_SW_LISR27_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_27
+#define    IRQ_SW_LISR28_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_28
+#define    IRQ_SW_LISR29_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_29
+#define    IRQ_SW_LISR30_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_30
+#define    IRQ_SW_LISR31_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_31
+#define    IRQ_SW_LISR32_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_32
+#define    IRQ_SW_LISR33_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_33
+#define    IRQ_SW_LISR34_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_34
+#define    IRQ_SW_LISR35_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_35
+#define    IRQ_SW_LISR36_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_36
+#define    IRQ_SW_LISR37_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_37
+#define    IRQ_SW_LISR38_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_38
+#define    IRQ_SW_LISR39_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_39
+#define    IRQ_SW_LISR40_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_40
+#define    IRQ_SW_LISR41_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_41
+#define    IRQ_SW_LISR42_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_42
+#define    IRQ_SW_LISR43_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_43
+#define    IRQ_SW_LISR44_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_44
+#define    IRQ_SW_LISR45_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_45
+#define    IRQ_SW_LISR46_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_46
+#define    IRQ_SW_LISR47_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_47
+#define    IRQ_SW_LISR48_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_48
+#define    IRQ_SW_LISR49_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_49
+#define    IRQ_SW_LISR50_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_50
+#define    IRQ_SW_LISR51_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_51
+#define    IRQ_SW_LISR52_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_52
+#define    IRQ_SW_LISR53_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_53
+#define    IRQ_SW_LISR54_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_54
+#define    IRQ_SW_LISR55_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_55
+#define    IRQ_SW_LISR56_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_56
+#define    IRQ_SW_LISR57_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_57
+#define    IRQ_SW_LISR58_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_58
+#define    IRQ_SW_LISR59_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_59
+#define    IRQ_SW_LISR60_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_60
+#define    IRQ_SW_LISR61_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_61
+#define    IRQ_SW_LISR62_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_62
+#define    IRQ_SW_LISR63_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_63
+#define    IRQ_SW_LISR64_CODE                        MD_IRQID_SW_TRIGGER_RESERVED_64
+#define    IRQ_DUMMY_PRIORITY_CODE_8                 MD_IRQID_DUMMY_PRIORITY_IRQ8
+#define    IRQ_DUMMY_PRIORITY_CODE_9                 MD_IRQID_DUMMY_PRIORITY_IRQ9
+#define    IRQ_DUMMY_PRIORITY_CODE_10                MD_IRQID_DUMMY_PRIORITY_IRQ10
+#define    IRQ_DUMMY_PRIORITY_CODE_11                MD_IRQID_DUMMY_PRIORITY_IRQ11
+#define    IRQ_DUMMY_PRIORITY_CODE_12                MD_IRQID_DUMMY_PRIORITY_IRQ12
+#define    IRQ_DUMMY_PRIORITY_CODE_13                MD_IRQID_DUMMY_PRIORITY_IRQ13
+#define    IRQ_DUMMY_PRIORITY_CODE_14                MD_IRQID_DUMMY_PRIORITY_IRQ14
+#define    IRQ_DUMMY_PRIORITY_CODE_15                MD_IRQID_DUMMY_PRIORITY_IRQ15
+#define    IRQ_DUMMY_PRIORITY_CODE_16                MD_IRQID_DUMMY_PRIORITY_IRQ16
+#define    IRQ_DUMMY_PRIORITY_CODE_17                MD_IRQID_DUMMY_PRIORITY_IRQ17
+#define    IRQ_DUMMY_PRIORITY_CODE_18                MD_IRQID_DUMMY_PRIORITY_IRQ18
+#define    IRQ_DUMMY_PRIORITY_CODE_19                MD_IRQID_DUMMY_PRIORITY_IRQ19
+#define    IRQ_DUMMY_PRIORITY_CODE_20                MD_IRQID_DUMMY_PRIORITY_IRQ20
+#define    IRQ_DUMMY_PRIORITY_CODE_21                MD_IRQID_DUMMY_PRIORITY_IRQ21
+#define    IRQ_DUMMY_PRIORITY_CODE_22                MD_IRQID_DUMMY_PRIORITY_IRQ22
+#define    IRQ_DUMMY_PRIORITY_CODE_23                MD_IRQID_DUMMY_PRIORITY_IRQ23
+#define    IRQ_DUMMY_PRIORITY_CODE_24                MD_IRQID_DUMMY_PRIORITY_IRQ24
+#define    IRQ_DUMMY_PRIORITY_CODE_25                MD_IRQID_DUMMY_PRIORITY_IRQ25
+#define    IRQ_DUMMY_PRIORITY_CODE_26                MD_IRQID_DUMMY_PRIORITY_IRQ26
+#define    IRQ_DUMMY_PRIORITY_CODE_27                MD_IRQID_DUMMY_PRIORITY_IRQ27
+#define    IRQ_DUMMY_PRIORITY_CODE_28                MD_IRQID_DUMMY_PRIORITY_IRQ28
+#define    IRQ_DUMMY_PRIORITY_CODE_29                MD_IRQID_DUMMY_PRIORITY_IRQ29
+#define    IRQ_DUMMY_PRIORITY_CODE_30                MD_IRQID_DUMMY_PRIORITY_IRQ30
+
+#if defined(__ESL_MASE__) || defined(__SPV_UFPS_LOAD__)
+#define    IRQ_SW_MODIS_MASE_HMU_CODE                IRQ_DUMMY_PRIORITY_CODE_25
+#define    IRQ_SW_MODIS_MASE_LTE_TXLISR_CODE         IRQ_DUMMY_PRIORITY_CODE_26
+#define    IRQ_SW_MODIS_MASE_NR_TXLISR_CODE          IRQ_DUMMY_PRIORITY_CODE_27
+#define    IRQ_L1_PAE_SW_LISR0                       IRQ_DUMMY_PRIORITY_CODE_28
+#define    IRQ_L1_PAE_SW_LISR1                       IRQ_DUMMY_PRIORITY_CODE_29
+#define    IRQ_L1_PAE_SW_LISR2                       IRQ_DUMMY_PRIORITY_CODE_30
+#endif 
+
+
+/* IRQ Affinity Group Definition */
+#if defined(__ESL_SINGLE_CORE__)
+#define INTERRUPT_GROUP_M2V_LIST \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, \
+    0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE, 0xFFE,
+#else
+#define INTERRUPT_GROUP_M2V_LIST \
+    /* Group0(0) */                                                                             0xFFE, \
+    /* Group1(1) */                                                                             0xFFD, \
+    /* Group2(2) */                                                                             0xFFB, \
+    /* Group3(3) */                                                                             0xFF7, \
+    /* Group4(4) */                                                                             0xFEF, \
+    /* Group5(5) */                                                                             0xFDF, \
+    /* Group6(6) */                                                                             0xFBF, \
+    /* Group7(7) */                                                                             0xF7F, \
+    /* Group8(8) */                                                                             0xEFF, \
+    /* Group9(9) */                                                                             0xDFF, \
+    /* Group10(10) */                                                                           0xBFF, \
+    /* Group11(11) */                                                                           0x7FF, \
+    /* Group12(1,4) */                                                                          0xFED, \
+    /* Group13(0,1,2) */                                                                        0xFF8, \
+    /* Group14(3,6,9) */                                                                        0xDB7, \
+    /* Group15(0,3,6,9) */                                                                      0xDB6, \
+    /* Group16(3,4,6,7,9,10) */                                                                 0x927, \
+    /* Group17(0,1,2,3,4,6,7,9,10) */                                                           0x920, \
+    /* Group18(3,4,5,6,7,8,9,10,11) */                                                          0x007, \
+    /* Group19(0,1,2,3,4,5,6,7,8,9,10,11) */                                                    0x000, \
+    /* Group20(3,4,6,7,9,10)        -> Reserved for NR runtime change affinity */               0x927, \
+    /* Group21(3,4,5,6,7,8,9,10,11) -> Reserved for NR runtime change affinity */               0x007, \
+    /* Group22(2)                   -> Reserved for LTE runtime change affinity */              0xFFB, \
+    /* Group23(0,2,3,4,6,7,9,10)    -> Workaround for UL1D slottick(IRQ0xF5) HRT fail issue */  0x922, \
+    /* Group24 */                                                                               0xFFF, \
+    /* Group25 */                                                                               0xFFF, \
+    /* Group26 */                                                                               0xFFF, \
+    /* Group27 */                                                                               0xFFF, \
+    /* Group28 */                                                                               0xFFF, \
+    /* Group29 */                                                                               0xFFF, \
+    /* Group30 */                                                                               0xFFF, \
+    /* Group31 */                                                                               0xFFF,
+#endif
+
+
+/*******************************************************************************
+ * IRQ affinity group definitions - 
+ * Defined so that users can call MACROs instead of the group number directyly.
+ * Currently, used in drv_busmon.c
+ *******************************************************************************/
+#define IRQ_AFFINITY_GROUP_VPE0         0   //(0)
+#define IRQ_AFFINITY_GROUP_VPE1         1   //(1)
+#define IRQ_AFFINITY_GROUP_VPE2         2   //(2)
+#define IRQ_AFFINITY_GROUP_VPE3         3   //(3)
+#define IRQ_AFFINITY_GROUP_VPE4         4   //(4)
+#define IRQ_AFFINITY_GROUP_VPE5         5   //(5)
+#define IRQ_AFFINITY_GROUP_VPE6         6   //(6)
+#define IRQ_AFFINITY_GROUP_VPE7         7   //(7)
+#define IRQ_AFFINITY_GROUP_VPE8	        8   //(8)
+#define IRQ_AFFINITY_GROUP_VPE9         9   //(9)
+#define IRQ_AFFINITY_GROUP_VPE10        10  //(10)
+#define IRQ_AFFINITY_GROUP_VPE11        11  //(11)
+#define IRQ_AFFINITY_GROUP_VPE1VPE4     12  //(1,4)
+#define IRQ_AFFINITY_GROUP_HRT_CORE0    13  //(0,1,2)
+#define IRQ_AFFINITY_GROUP_NORMAL_NR    14  //(3,6,9)
+#define IRQ_AFFINITY_GROUP_NORMAL_SMP   15  //(0,3,6,9)
+#define IRQ_AFFINITY_GROUP_HRT_NR       16  //(3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_HRT_SMP      17  //(0,1,2,3,4,6,7,9,10)
+#define IRQ_AFFINITY_GROUP_CHRT_NR      18  //(3,4,5,6,7,8,9,10,11)
+#define IRQ_AFFINITY_GROUP_ALL_VPE      19  //(0,1,2,3,4,5,6,7,8,9,10,11)
+
+
+#define IRQ_MASK0              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0000))
+#define IRQ_MASK1              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0004))
+#define IRQ_MASK2              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0008))
+#define IRQ_MASK3              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x000C))
+#define IRQ_MASK4              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00010))
+#define IRQ_MASK5              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00014))
+#define IRQ_MASK6              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00018))
+#define IRQ_MASK7              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0001C))
+#define IRQ_MASK8              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00020))
+#define IRQ_MASK9              ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00024))
+#define IRQ_MASK10             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x00028))
+#define IRQ_MASK11             ((volatile UINT32P)(MDCIRQ_IMKR_BASE+0x0002C))
+
+
+typedef enum
+{
+    VPE_STATUS_LISR_HIGHEST      = 0,
+    VPE_STATUS_LISR_LOWEST       = 337,
+    VPE_STATUS_HISR_TASK_HIGHEST = 512,
+    VPE_STATUS_HISR_TASK_LOWEST  = VPE_STATUS_HISR_TASK_HIGHEST+KAL_MAX_NUM_TASKS, 
+    VPE_STATUS_END               = 1023,
+} VPE_STATUS;
+
+
+/* For SWLA to display IRQ name instead of IRQID */
+enum CIRQ_Code_Def_MET_Enum
+{
+    IRQ_USIM0 = IRQ_USIM0_CODE,
+};
+
+#endif /* end of __INTRCTRL_MERCURY_H__ */
+
+
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY_SW_Handle.h
new file mode 100644
index 0000000..ce65e41
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_MERCURY_SW_Handle.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_MERCURY_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   MERCURY
+ *
+ * Description:
+ * ------------
+ *   This file define software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *
+ ****************************************************************************/
+
+
+/* Add SW handler mapping:
+      1st parameter: The name of software handler
+      2nd parameter: The software handler number
+      3th parameter: The mapping of software handler to hardware interrupt code
+      User:
+      SW_TRIGGER_CODE0  = Karthigeyan Reddy
+      SW_TRIGGER_CODE1  = Karthigeyan Reddy
+      SW_TRIGGER_CODE2  = Karthigeyan Reddy
+      SW_TRIGGER_CODE3  = Karthigeyan Reddy
+      SW_TRIGGER_CODE4  = Karthigeyan Reddy
+      SW_TRIGGER_CODE5  = Karthigeyan Reddy
+      SW_TRIGGER_CODE6  = Zengling Jin
+      SW_TRIGGER_CODE7  = Zengling Jin
+      SW_TRIGGER_CODE8  = Zengling Jin
+      SW_TRIGGER_CODE9  = Cruze Yu
+      SW_TRIGGER_CODE10 = Cruze Yu
+      SW_TRIGGER_CODE11 = Cruze Yu
+      SW_TRIGGER_CODE12 = Cruze Yu
+      SW_TRIGGER_CODE13 = Huei-Ya, Yuda Lee
+      SW_TRIGGER_CODE14 = HW Jheng
+      SW_TRIGGER_CODE15 = Frank Hu
+      SW_TRIGGER_CODE16 = KH Hsiao
+      SW_TRIGGER_CODE17 = Deepti Varadarajan
+      SW_TRIGGER_CODE18 = Owen Ho
+      SW_TRIGGER_CODE19 = Owen Ho
+      SW_TRIGGER_CODE20 = Owen Ho
+      SW_TRIGGER_CODE21 = Owen Ho
+      SW_TRIGGER_CODE22 = Jun-Ying Huang
+      SW_TRIGGER_CODE23 = Jun-Ying Huang
+      SW_TRIGGER_CODE24 = Jun-Ying Huang
+      SW_TRIGGER_CODE25 = Jun-Ying Huang
+      SW_TRIGGER_CODE26 = Wade Huang
+      SW_TRIGGER_CODE27 = Tee-Yuen Chun
+      SW_TRIGGER_CODE28 = YY Hsieh 
+      SW_TRIGGER_CODE29 = Hamilton Liang
+      SW_TRIGGER_CODE30 = HW Jheng
+      SW_TRIGGER_CODE31 = Weimin Zeng
+      SW_TRIGGER_CODE32 = Weimin Zeng
+      SW_TRIGGER_CODE33 = Jocobrian Chang
+      SW_TRIGGER_CODE34 = JiaHong Hsu
+      SW_TRIGGER_CODE35 = Cheng-Long Wu
+      SW_TRIGGER_CODE36 = Cheng-Long Wu
+      SW_TRIGGER_CODE37 = Jocobrian Chang
+      SW_TRIGGER_CODE38 = Jocobrian Chang
+      SW_TRIGGER_CODE39 = Jocobrian Chang
+      SW_TRIGGER_CODE40 = Shu-Wei Ho
+      SW_TRIGGER_CODE41 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE42 = Hedy Han(Reserved for Busmon IRQ runtime configuration.)
+      SW_TRIGGER_CODE43 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE44 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE45 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE46 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE47 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE48 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE49 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE50 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE51 = Chia-Han Wu(SW reserved IRQ)
+      SW_TRIGGER_CODE52 = Chia-Han Wu(SW reserved IRQ, Highest Priority)
+      SW_TRIGGER_CODE53 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE54 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE55 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE56 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE57 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE58 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE59 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE60 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE61 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE62 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE63 = Pasi Arffman(Used for OSIPI temporarily)
+      SW_TRIGGER_CODE64 = Pasi Arffman(Used for OSIPI temporarily)
+  */
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE0, IRQ_SW_LISR0_CODE, IRQ_SW_LISR0_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE1, IRQ_SW_LISR1_CODE, IRQ_SW_LISR1_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE2, IRQ_SW_LISR2_CODE, IRQ_SW_LISR2_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE3, IRQ_SW_LISR3_CODE, IRQ_SW_LISR3_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE4, IRQ_SW_LISR4_CODE, IRQ_SW_LISR4_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE5, IRQ_SW_LISR5_CODE, IRQ_SW_LISR5_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE6, IRQ_SW_LISR6_CODE, IRQ_SW_LISR6_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE7, IRQ_SW_LISR7_CODE, IRQ_SW_LISR7_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE8, IRQ_SW_LISR8_CODE, IRQ_SW_LISR8_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE9, IRQ_SW_LISR9_CODE, IRQ_SW_LISR9_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE10, IRQ_SW_LISR10_CODE, IRQ_SW_LISR10_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE11, IRQ_SW_LISR11_CODE, IRQ_SW_LISR11_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE12, IRQ_SW_LISR12_CODE, IRQ_SW_LISR12_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE13, IRQ_SW_LISR13_CODE, IRQ_SW_LISR13_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE14, IRQ_SW_LISR14_CODE, IRQ_SW_LISR14_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE15, IRQ_SW_LISR15_CODE, IRQ_SW_LISR15_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE16, IRQ_SW_LISR16_CODE, IRQ_SW_LISR16_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE17, IRQ_SW_LISR17_CODE, IRQ_SW_LISR17_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE18, IRQ_SW_LISR18_CODE, IRQ_SW_LISR18_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE19, IRQ_SW_LISR19_CODE, IRQ_SW_LISR19_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE20, IRQ_SW_LISR20_CODE, IRQ_SW_LISR20_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE21, IRQ_SW_LISR21_CODE, IRQ_SW_LISR21_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE22, IRQ_SW_LISR22_CODE, IRQ_SW_LISR22_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE23, IRQ_SW_LISR23_CODE, IRQ_SW_LISR23_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE24, IRQ_SW_LISR24_CODE, IRQ_SW_LISR24_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE25, IRQ_SW_LISR25_CODE, IRQ_SW_LISR25_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE26, IRQ_SW_LISR26_CODE, IRQ_SW_LISR26_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE27, IRQ_SW_LISR27_CODE, IRQ_SW_LISR27_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE28, IRQ_SW_LISR28_CODE, IRQ_SW_LISR28_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE29, IRQ_SW_LISR29_CODE, IRQ_SW_LISR29_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE30, IRQ_SW_LISR30_CODE, IRQ_SW_LISR30_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE31, IRQ_SW_LISR31_CODE, IRQ_SW_LISR31_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE32, IRQ_SW_LISR32_CODE, IRQ_SW_LISR32_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE33, IRQ_SW_LISR33_CODE, IRQ_SW_LISR33_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE34, IRQ_SW_LISR34_CODE, IRQ_SW_LISR34_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE35, IRQ_SW_LISR35_CODE, IRQ_SW_LISR35_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE36, IRQ_SW_LISR36_CODE, IRQ_SW_LISR36_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE37, IRQ_SW_LISR37_CODE, IRQ_SW_LISR37_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE38, IRQ_SW_LISR38_CODE, IRQ_SW_LISR38_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE39, IRQ_SW_LISR39_CODE, IRQ_SW_LISR39_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE40, IRQ_SW_LISR40_CODE, IRQ_SW_LISR40_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE41, IRQ_SW_LISR41_CODE, IRQ_SW_LISR41_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE42, IRQ_SW_LISR42_CODE, IRQ_SW_LISR42_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE43, IRQ_SW_LISR43_CODE, IRQ_SW_LISR43_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE44, IRQ_SW_LISR44_CODE, IRQ_SW_LISR44_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE45, IRQ_SW_LISR45_CODE, IRQ_SW_LISR45_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE46, IRQ_SW_LISR46_CODE, IRQ_SW_LISR46_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE47, IRQ_SW_LISR47_CODE, IRQ_SW_LISR47_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE48, IRQ_SW_LISR48_CODE, IRQ_SW_LISR48_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE49, IRQ_SW_LISR49_CODE, IRQ_SW_LISR49_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE50, IRQ_SW_LISR50_CODE, IRQ_SW_LISR50_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE51, IRQ_SW_LISR51_CODE, IRQ_SW_LISR51_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE52, IRQ_SW_LISR52_CODE, IRQ_SW_LISR52_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE53, IRQ_SW_LISR53_CODE, IRQ_SW_LISR53_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE54, IRQ_SW_LISR54_CODE, IRQ_SW_LISR54_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE55, IRQ_SW_LISR55_CODE, IRQ_SW_LISR55_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE56, IRQ_SW_LISR56_CODE, IRQ_SW_LISR56_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE57, IRQ_SW_LISR57_CODE, IRQ_SW_LISR57_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE58, IRQ_SW_LISR58_CODE, IRQ_SW_LISR58_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE59, IRQ_SW_LISR59_CODE, IRQ_SW_LISR59_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE60, IRQ_SW_LISR60_CODE, IRQ_SW_LISR60_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE61, IRQ_SW_LISR61_CODE, IRQ_SW_LISR61_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE62, IRQ_SW_LISR62_CODE, IRQ_SW_LISR62_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE63, IRQ_SW_LISR63_CODE, IRQ_SW_LISR63_CODE)
+X_SW_HANDLE_CONST(SW_TRIGGER_CODE64, IRQ_SW_LISR64_CODE, IRQ_SW_LISR64_CODE)
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_SW_Handle.h b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_SW_Handle.h
new file mode 100644
index 0000000..5499477
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/intrCtrl_SW_Handle.h
@@ -0,0 +1,72 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   intrCtrl_SW_Handle.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *   This file include the each BB chip software interrupt handler.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/* Include Chip SW handler */
+
+#if defined(MERCURY)
+   #include "intrCtrl_MERCURY_SW_Handle.h"
+#endif
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/irqPriority.h b/mcu/interface/driver/devdrv/cirq/md97p/irqPriority.h
new file mode 100644
index 0000000..07b86ff
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/irqPriority.h
@@ -0,0 +1,3 @@
+#if defined(MERCURY)
+   #include "irqPriority_MERCURY.h"
+#endif
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/irqPriority_MERCURY.h b/mcu/interface/driver/devdrv/cirq/md97p/irqPriority_MERCURY.h
new file mode 100644
index 0000000..8bbd894
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/irqPriority_MERCURY.h
@@ -0,0 +1,368 @@
+IRQ_PRIORITY_CONST(IRQ_SW_LISR52_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_ERR_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_SERDES_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_COS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_NOR_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPBTDMA_TOP_L1_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_BIGRAM_0_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_COS_PREP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_SI_CM_PCINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUS_DECERROR_CODE)
+IRQ_PRIORITY_CONST(IRQ_ECT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUS_DECERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDWDT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA4_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_IEBIT_CHECK_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_3_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_4_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_D_GDMA_5_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_APWDT_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXBSRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_AIRQ_PAD_CODE)
+IRQ_PRIORITY_CONST(IRQ_MIPI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RMPU_CTIREIGIN_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR26_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR41_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR42_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_ERR_CC_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TX_NR_CC1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXDFE_D_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ28_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C2_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C3_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C4_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C5_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR35_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR36_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP6_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM8_CODE)
+IRQ_PRIORITY_CONST(IRQ_FDD_SLP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C0_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_HRT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_NOTIF_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_EXCEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCUMMU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_WAKEUP_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP11_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP7_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP8_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP9_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP10_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_0_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_TDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_6_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_4_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR34_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR33_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR37_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MML1_DSPCSIF_TOP_S2C1_CIRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_RXDFE_BB_DUMP_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP0_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDD_TIMER_L1D_2_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP13_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_FDD_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDM2C_U3G_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR13_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FPC_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_FOE_1X_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CS_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_CM_NR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_SLP_SLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1_LTE_SLEEP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDEVDO_CODE)
+IRQ_PRIORITY_CONST(IRQ_RTR_SLT_1_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR3_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR5_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CFG_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR9_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1X_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR16_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_M2C_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_WAKEUP_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ1_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_TDMA_CTIRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHARE_D12MINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIP12_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR1_CODE)
+IRQ_PRIORITY_CONST(IRQ_FREQM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR10_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR11_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR32_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR12_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR31_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR0_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR7_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM7_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR8_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ5_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ6_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR2_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_IRQ_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_1X_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_RAKE_CMIF_PD_DO_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ST1x_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_STDO_HALF_CPINT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR40_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MDMCU_CODE)
+IRQ_PRIORITY_CONST(IRQ_NRL2_DPMAIF_MD_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_LTE_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDINFRA_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_BUSMON_MATCH_STS_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_PM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_TX_FORCE_ON_CODE)
+IRQ_PRIORITY_CONST(IRQ_IDC_UART_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PCIE_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR27_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_PDMA_CODE)
+IRQ_PRIORITY_CONST(IRQ_SL_WAITSLEEP_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_DEC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC0_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PPPHA_ENC1_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_SCH_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ERR_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UCNT_ADJ_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_MSDC0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM0_CODE)
+IRQ_PRIORITY_CONST(IRQ_USIM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DVFS_BLOCK_ELM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_OST_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDRTT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_MCU_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP4G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_RT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ULSP_LOG_DSP5G_OD_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SDF_OVERFLOW_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_TRACE_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ4_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ7_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ9_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ10_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ18_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ19_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ20_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ21_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ22_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ23_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ24_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ25_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ26_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ27_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ29_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ30_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_IRQ31_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ0_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ11_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ12_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ13_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ14_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ15_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ16_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_INFORM_DONE_IRQ17_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_CNTDN_IRQ3_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_SPU_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELMTOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_ELM_DMA_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_BUSMPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD0_CODE)
+IRQ_PRIORITY_CONST(IRQ_UART_MD1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT0_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT1_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT2_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT3_CODE)
+IRQ_PRIORITY_CONST(IRQ_EINT_SHARE_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM1_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM2_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM4_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM5_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM3_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM9_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM10_CODE)
+IRQ_PRIORITY_CONST(IRQ_GPTM11_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA5_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA6_CODE)
+IRQ_PRIORITY_CONST(IRQ_I2C_TOP_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_SOE_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_ABM_ERROR_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_DEM_TRIG_PS_INT_LE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDMCU_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_SHAOLIN_OSTD_THROTTLE_CODE)
+IRQ_PRIORITY_CONST(IRQ_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_WF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA0_2_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_FDMA3_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA0_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_MDGDMA_HDMA2_3_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF0_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF1_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_RXDFE_IRQ2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CONN_BGF_CCIF_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_TXCRP_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_INFORM_DONE_IRQ8_CODE)
+IRQ_PRIORITY_CONST(IRQ_PLL_GEARHP_RDY_CODE)
+IRQ_PRIORITY_CONST(IRQ_REQ_ABNORM_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_L1M_PHY_LTMR_SPU_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_IRDBG_MCU_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_0_CODE)
+IRQ_PRIORITY_CONST(IRQ_MD_DVFS_CTRL_IRQ_1_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_TIMER_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_NR_EVENTGEN_ERR_CODE)
+IRQ_PRIORITY_CONST(IRQ_CSSYS_DO_CS_IRQ_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_THERM_INT_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_PTP_FSM_INT_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_DAPC_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_CCIF2_CODE)
+IRQ_PRIORITY_CONST(IRQ_AP2MD_UFS_CODE)
+IRQ_PRIORITY_CONST(IRQ_SSUSB_INTERRUPT_OUT_CODE)
+IRQ_PRIORITY_CONST(IRQ_CONN_BT_ISOCH_CODE)
+IRQ_PRIORITY_CONST(IRQ_BT_CVSD_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR14_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR15_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR18_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR19_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR20_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR21_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR22_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR23_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR24_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR25_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR28_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR29_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR30_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR38_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR39_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR43_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR44_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR45_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR46_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR47_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR48_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR49_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR50_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR51_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR53_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR54_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR55_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR56_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR57_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR58_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR59_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR60_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR61_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR62_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR63_CODE)
+IRQ_PRIORITY_CONST(IRQ_SW_LISR64_CODE)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_3)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_4)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_5)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_6)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_8)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_9)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_10)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_11)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_12)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_13)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_14)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_15)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_16)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_17)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_18)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_19)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_20)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_21)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_22)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_23)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_24)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_25)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_26)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_27)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_28)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_29)
+IRQ_PRIORITY_CONST(IRQ_DUMMY_PRIORITY_CODE_30)
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/irqid.h b/mcu/interface/driver/devdrv/cirq/md97p/irqid.h
new file mode 100644
index 0000000..e30d214
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/irqid.h
@@ -0,0 +1,8 @@
+#ifndef __IRQID_H__
+#define __IRQID_H__
+
+#if defined(MERCURY)
+   #include "irqid_MERCURY.h"
+#endif
+
+#endif /*end of __IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/irqid_MERCURY.h b/mcu/interface/driver/devdrv/cirq/md97p/irqid_MERCURY.h
new file mode 100644
index 0000000..39d74a3
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/irqid_MERCURY.h
@@ -0,0 +1,388 @@
+#ifndef __MERCURY_IRQID_H__
+#define __MERCURY_IRQID_H__
+
+
+//MERCURY IRQID
+#define MD_IRQID_USIM0                                0
+#define MD_IRQID_USIM1                                1
+#define MD_IRQID_TDMA_CTIRQ1                          2
+#define MD_IRQID_TDMA_CTIRQ2                          3
+#define MD_IRQID_TDMA_CTIRQ3                          4
+#define MD_IRQID_TDMA_WAKEUP_IRQ                      5
+#define MD_IRQID_OST                                  6
+#define MD_IRQID_MDRTT                                7
+#define MD_IRQID_MDEVDO                               8
+#define MD_IRQID_ULSP_LOG_MCU_RT_INT                  9
+#define MD_IRQID_ULSP_LOG_MCU_OD_INT                 10
+#define MD_IRQID_ULSP_LOG_DSP4G_RT_INT               11
+#define MD_IRQID_ULSP_LOG_DSP4G_OD_INT               12
+#define MD_IRQID_ULSP_LOG_DSP5G_RT_INT               13
+#define MD_IRQID_ULSP_LOG_DSP5G_OD_INT               14
+#define MD_IRQID_SHARE_D12MINT1                      15
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C0_CIRQ          16
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C1_CIRQ          17
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C2_CIRQ          18
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C3_CIRQ          19
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C4_CIRQ          20
+#define MD_IRQID_MML1_DSPCSIF_TOP_S2C5_CIRQ          21
+#define MD_IRQID_MML1_DSPCSIF_TOP_ERR_CIRQ           22
+#define MD_IRQID_AIRQ_SERDES                         23
+#define MD_IRQID_AIRQ_COS                            24
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_NOR            25
+#define MD_IRQID_MML1_DSPBTDMA_TOP_L1_ERR            26
+#define MD_IRQID_PPPHA_ENC0_INT                      27
+#define MD_IRQID_PPPHA_ENC1_INT                      28
+#define MD_IRQID_PPPHA_DEC0_INT                      29
+#define MD_IRQID_PPPHA_DEC1_INT                      30
+#define MD_IRQID_CS_NR_IRQ                           31
+#define MD_IRQID_CS_NR_ERR_IRQ                       32
+#define MD_IRQID_SDF_OVERFLOW_IRQ                    33
+#define MD_IRQID_MCUMMU_INT                          34
+#define MD_IRQID_BIGRAM_0_IRQ_0                      35
+#define MD_IRQID_COS_PREP_INT                        36
+#define MD_IRQID_TRACE_INT                           37
+#define MD_IRQID_NR_TIMER_IRQ0                       38
+#define MD_IRQID_NR_TIMER_IRQ1                       39
+#define MD_IRQID_NR_TIMER_IRQ2                       40
+#define MD_IRQID_NR_TIMER_IRQ3                       41
+#define MD_IRQID_NR_TIMER_IRQ4                       42
+#define MD_IRQID_NR_TIMER_IRQ5                       43
+#define MD_IRQID_NR_TIMER_IRQ6                       44
+#define MD_IRQID_NR_TIMER_IRQ7                       45
+#define MD_IRQID_NR_TIMER_IRQ8                       46
+#define MD_IRQID_NR_TIMER_IRQ9                       47
+#define MD_IRQID_NR_TIMER_IRQ10                      48
+#define MD_IRQID_NR_TIMER_IRQ11                      49
+#define MD_IRQID_NR_TIMER_IRQ12                      50
+#define MD_IRQID_NR_TIMER_IRQ13                      51
+#define MD_IRQID_NR_TIMER_IRQ14                      52
+#define MD_IRQID_NR_TIMER_IRQ15                      53
+#define MD_IRQID_NR_TIMER_IRQ16                      54
+#define MD_IRQID_NR_TIMER_IRQ17                      55
+#define MD_IRQID_NR_TIMER_IRQ18                      56
+#define MD_IRQID_NR_TIMER_IRQ19                      57
+#define MD_IRQID_NR_TIMER_IRQ20                      58
+#define MD_IRQID_NR_TIMER_IRQ21                      59
+#define MD_IRQID_NR_TIMER_IRQ22                      60
+#define MD_IRQID_NR_TIMER_IRQ23                      61
+#define MD_IRQID_NR_TIMER_IRQ24                      62
+#define MD_IRQID_NR_TIMER_IRQ25                      63
+#define MD_IRQID_NR_TIMER_IRQ26                      64
+#define MD_IRQID_NR_TIMER_IRQ27                      65
+#define MD_IRQID_NR_TIMER_IRQ28                      66
+#define MD_IRQID_NR_TIMER_IRQ29                      67
+#define MD_IRQID_NR_TIMER_IRQ30                      68
+#define MD_IRQID_NR_TIMER_IRQ31                      69
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ0           70
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ1           71
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ2           72
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ3           73
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ4           74
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ5           75
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ6           76
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ7           77
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ8           78
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ9           79
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ10          80
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ11          81
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ12          82
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ13          83
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ14          84
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ15          85
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ16          86
+#define MD_IRQID_NR_TIMER_INFORM_DONE_IRQ17          87
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ0                 88
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ1                 89
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ2                 90
+#define MD_IRQID_NR_TIMER_CNTDN_IRQ3                 91
+#define MD_IRQID_NR_EVENTGEN_SPU                     92
+#define MD_IRQID_SI_CM_ERR                           93
+#define MD_IRQID_SI_CM_PCINT                         94
+#define MD_IRQID_MDM2C_U3G                           95
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_0                 96
+#define MD_IRQID_RAKE_CMIF_M2C_IRQ_1                 97
+#define MD_IRQID_RAKE_CMIF_FPC_1X_IRQ                98
+#define MD_IRQID_RAKE_CMIF_FOE_1X_IRQ                99
+#define MD_IRQID_RAKE_CMIF_PD_DO_IRQ                100
+#define MD_IRQID_MDMCU_BUSMON_MATCH_STS             101
+#define MD_IRQID_MDINFRA_BUSMON_MATCH_STS           102
+#define MD_IRQID_ELMTOP_EMI_IRQ                     103
+#define MD_IRQID_ELM_DMA_IRQ                        104
+#define MD_IRQID_BUSMPU_IRQ                         105
+#define MD_IRQID_ST1X_CPINT                         106
+#define MD_IRQID_ST1x_HALF_CPINT                    107
+#define MD_IRQID_ST1x_CFG_CPINT                     108
+#define MD_IRQID_ST1x_WAKEUP_IRQ                    109
+#define MD_IRQID_STDO_CPINT                         110
+#define MD_IRQID_STDO_HALF_CPINT                    111
+#define MD_IRQID_STDO_CFG_CPINT                     112
+#define MD_IRQID_STDO_WAKEUP_IRQ                    113
+#define MD_IRQID_UART_MD0                           114
+#define MD_IRQID_UART_MD1                           115
+#define MD_IRQID_EINT0                              116
+#define MD_IRQID_EINT1                              117
+#define MD_IRQID_EINT2                              118
+#define MD_IRQID_EINT3                              119
+#define MD_IRQID_EINT_SHARE                         120
+#define MD_IRQID_GPTM1                              121
+#define MD_IRQID_GPTM2                              122
+#define MD_IRQID_GPTM3                              123
+#define MD_IRQID_GPTM4                              124
+#define MD_IRQID_GPTM5                              125
+#define MD_IRQID_GPTM6                              126
+#define MD_IRQID_GPTM7                              127
+#define MD_IRQID_GPTM8                              128
+#define MD_IRQID_GPTM9                              129
+#define MD_IRQID_GPTM10                             130
+#define MD_IRQID_GPTM11                             131
+#define MD_IRQID_IDC_PM_INT                         132
+#define MD_IRQID_IDC_UART_IRQ                       133
+#define MD_IRQID_MDGDMA_FDMA5                       134
+#define MD_IRQID_MDGDMA_FDMA6                       135
+#define MD_IRQID_TDMA_CTIRQ4                        136
+#define MD_IRQID_PDMA                               137
+#define MD_IRQID_MDINFRA_BUS_DECERROR               138
+#define MD_IRQID_I2C_TOP_INT                        139
+#define MD_IRQID_SOE                                140
+#define MD_IRQID_ABM_INT                            141
+#define MD_IRQID_ABM_ERROR_INT                      142
+#define MD_IRQID_USIP0                              143
+#define MD_IRQID_USIP1                              144
+#define MD_IRQID_USIP2                              145
+#define MD_IRQID_USIP3                              146
+#define MD_IRQID_USIP4                              147
+#define MD_IRQID_USIP5                              148
+#define MD_IRQID_USIP6                              149
+#define MD_IRQID_USIP7                              150
+#define MD_IRQID_USIP8                              151
+#define MD_IRQID_USIP9                              152
+#define MD_IRQID_USIP10                             153
+#define MD_IRQID_USIP11                             154
+#define MD_IRQID_USIP12                             155
+#define MD_IRQID_USIP13                             156
+#define MD_IRQID_TX_NR_CC0_IRQ                      157
+#define MD_IRQID_TX_NR_CC1_IRQ                      158
+#define MD_IRQID_TX_NR_ERR_CC_IRQ                   159
+#define MD_IRQID_MDMCU_SPU_IRQ                      160
+#define MD_IRQID_DEM_TRIG_PS_INT_LE                 161
+#define MD_IRQID_ECT                                162
+#define MD_IRQID_MDMCU_BUS_DECERR_IRQ               163
+#define MD_IRQID_MDMCU_OSTD_THROTTLE                164
+#define MD_IRQID_SHAOLIN_OSTD_THROTTLE              165
+#define MD_IRQID_AP2MD_DVFS_BLOCK_ELM_IRQ           166
+#define MD_IRQID_MCORE0_MML1_DSPPMU_TOP_EMI_IRQ     167
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_0               168
+#define MD_IRQID_VCORE0_MML1_DSPPMU_TOP_EMI_IRQ     169
+#define MD_IRQID_AP2MD_CONN_WF_CCIF_1               170
+#define MD_IRQID_MDWDT                              171
+#define MD_IRQID_MDGDMA_FDMA0_2                     172
+#define MD_IRQID_MDGDMA_FDMA1                       173
+#define MD_IRQID_MDGDMA_FDMA3                       174
+#define MD_IRQID_MDGDMA_FDMA4                       175
+#define MD_IRQID_MDGDMA_HDMA0_1                     176
+#define MD_IRQID_MDGDMA_HDMA2_3                     177
+#define MD_IRQID_AP2MD_CCIF0_0                      178
+#define MD_IRQID_AP2MD_CCIF0_1                      179
+#define MD_IRQID_AP2MD_CCIF1_0                      180
+#define MD_IRQID_AP2MD_CCIF1_1                      181
+#define MD_IRQID_IEBIT_CHECK_IRQ0                   182
+#define MD_IRQID_IEBIT_CHECK_IRQ1                   183
+#define MD_IRQID_IEBIT_CHECK_IRQ2                   184
+#define MD_IRQID_IEBIT_CHECK_IRQ3                   185
+#define MD_IRQID_IEBIT_CHECK_IRQ4                   186
+#define MD_IRQID_IEBIT_CHECK_IRQ5                   187
+#define MD_IRQID_IEBIT_CHECK_IRQ6                   188
+#define MD_IRQID_IEBIT_CHECK_IRQ7                   189
+#define MD_IRQID_IEBIT_CHECK_IRQ8                   190
+#define MD_IRQID_IEBIT_CHECK_IRQ9                   191
+#define MD_IRQID_IEBIT_CHECK_IRQ10                  192
+#define MD_IRQID_IEBIT_CHECK_IRQ11                  193
+#define MD_IRQID_NRL2_HRT                           194
+#define MD_IRQID_NRL2_NOTIF                         195
+#define MD_IRQID_NRL2_EXCEP                         196
+#define MD_IRQID_NRL2_DPMAIF_MD                     197
+#define MD_IRQID_RXDFE_IRQ0                         198
+#define MD_IRQID_IDC_UART_TX_FORCE_ON               199
+#define MD_IRQID_RXDFE_IRQ2                         200
+#define MD_IRQID_RXDFE_IRQ3                         201
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_0              202
+#define MD_IRQID_MD_RXDFE_BB_DUMP                   203
+#define MD_IRQID_AP2MD_CONN_BGF_CCIF_1              204
+#define MD_IRQID_TXCRP                              205
+#define MD_IRQID_CM_NR_IRQ                          206
+#define MD_IRQID_CM_NR_ERR_IRQ                      207
+#define MD_IRQID_L1_LTE_SLEEP_IRQ                   208
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ0      209
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ1      210
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ2      211
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ3      212
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ4      213
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ5      214
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ6      215
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ7      216
+#define MD_IRQID_L1M_PHY_LTMR_INFORM_DONE_IRQ8      217
+#define MD_IRQID_D_GDMA_0_IRQ                       218
+#define MD_IRQID_D_GDMA_1_IRQ                       219
+#define MD_IRQID_D_GDMA_2_IRQ                       220
+#define MD_IRQID_D_GDMA_3_IRQ                       221
+#define MD_IRQID_D_GDMA_4_IRQ                       222
+#define MD_IRQID_D_GDMA_5_IRQ                       223
+#define MD_IRQID_PLL_GEARHP_RDY                     224
+#define MD_IRQID_REQ_ABNORM_IRQ                     225
+#define MD_IRQID_NRL2_DPMAIF_MDMCU                  226
+#define MD_IRQID_AP2MD_APWDT_IRQ                    227
+#define MD_IRQID_DUMMY_PRIORITY_IRQ3                228
+#define MD_IRQID_DUMMY_PRIORITY_IRQ4                229
+#define MD_IRQID_DUMMY_PRIORITY_IRQ5                230
+#define MD_IRQID_L1M_PHY_LTMR_SPU_IRQ               231
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_0                 232
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_1                 233
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_2                 234
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_3                 235
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_4                 236
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_5                 237
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_6                 238
+#define MD_IRQID_L1M_PHY_LTMR_IRQ_7                 239
+#define MD_IRQID_DUMMY_PRIORITY_IRQ6                240
+#define MD_IRQID_L1_LTE_WAKEUP_IRQ                  241
+#define MD_IRQID_TDD_WAKEUP_IRQ                     242
+#define MD_IRQID_TDD_TIMER_L1D_1_IRQ                243
+#define MD_IRQID_TDD_TIMER_L1D_2_IRQ                244
+#define MD_IRQID_RTR_SLT_0_IRQ                      245
+#define MD_IRQID_RTR_SLT_1_IRQ                      246
+#define MD_IRQID_FDD_SLP_IRQ                        247
+#define MD_IRQID_IRDBG_MCU_INT                      248
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_0                 249
+#define MD_IRQID_MD_DVFS_CTRL_IRQ_1                 250
+#define MD_IRQID_NR_SLP_WAKEUP                      251
+#define MD_IRQID_NR_SLP_SLEEP                       252
+#define MD_IRQID_NR_TIMER_ERR                       253
+#define MD_IRQID_TXBSRP                             254
+#define MD_IRQID_TXDFE_D                            255
+#define MD_IRQID_NR_EVENTGEN_ERR                    256
+#define MD_IRQID_AIRQ_PAD                           257
+#define MD_IRQID_CSSYS_FDD_CS_IRQ                   258
+#define MD_IRQID_CSSYS_TDD_CS_IRQ                   259
+#define MD_IRQID_CSSYS_LTE_CS_IRQ                   260
+#define MD_IRQID_CSSYS_1X_CS_IRQ                    261
+#define MD_IRQID_CSSYS_DO_CS_IRQ                    262
+#define MD_IRQID_PCIE_INTERRUPT_OUT                 263
+#define MD_IRQID_UCNT_SCH_IRQ                       264
+#define MD_IRQID_UCNT_ERR_IRQ                       265
+#define MD_IRQID_UCNT_ADJ_IRQ                       266
+#define MD_IRQID_SL_WAITSLEEP                       267
+#define MD_IRQID_PTP_THERM_INT_INT                  268
+#define MD_IRQID_PTP_FSM_INT                        269
+#define MD_IRQID_AP2MD_DAPC                         270
+#define MD_IRQID_AP2MD_CCIF2                        271
+#define MD_IRQID_AP2MD_UFS                          272
+#define MD_IRQID_SSUSB_INTERRUPT_OUT                273
+#define MD_IRQID_AP2MD_MSDC0                        274
+#define MD_IRQID_MIPI_IRQ                           275
+#define MD_IRQID_CONN_BT_ISOCH                      276
+#define MD_IRQID_RMPU_CTIREIGIN                     277
+#define MD_IRQID_FREQM_IRQ                          278
+#define MD_IRQID_BT_CVSD                            279
+#define MD_IRQID_SW_TRIGGER_RESERVED_0              280
+#define MD_IRQID_SW_TRIGGER_RESERVED_1              281
+#define MD_IRQID_SW_TRIGGER_RESERVED_2              282
+#define MD_IRQID_SW_TRIGGER_RESERVED_3              283
+#define MD_IRQID_SW_TRIGGER_RESERVED_4              284
+#define MD_IRQID_SW_TRIGGER_RESERVED_5              285
+#define MD_IRQID_SW_TRIGGER_RESERVED_6              286
+#define MD_IRQID_SW_TRIGGER_RESERVED_7              287
+#define MD_IRQID_SW_TRIGGER_RESERVED_8              288
+#define MD_IRQID_SW_TRIGGER_RESERVED_9              289
+#define MD_IRQID_SW_TRIGGER_RESERVED_10             290
+#define MD_IRQID_SW_TRIGGER_RESERVED_11             291
+#define MD_IRQID_SW_TRIGGER_RESERVED_12             292
+#define MD_IRQID_SW_TRIGGER_RESERVED_13             293
+#define MD_IRQID_SW_TRIGGER_RESERVED_14             294
+#define MD_IRQID_SW_TRIGGER_RESERVED_15             295
+#define MD_IRQID_SW_TRIGGER_RESERVED_16             296
+#define MD_IRQID_SW_TRIGGER_RESERVED_17             297
+#define MD_IRQID_SW_TRIGGER_RESERVED_18             298
+#define MD_IRQID_SW_TRIGGER_RESERVED_19             299
+#define MD_IRQID_SW_TRIGGER_RESERVED_20             300
+#define MD_IRQID_SW_TRIGGER_RESERVED_21             301
+#define MD_IRQID_SW_TRIGGER_RESERVED_22             302
+#define MD_IRQID_SW_TRIGGER_RESERVED_23             303
+#define MD_IRQID_SW_TRIGGER_RESERVED_24             304
+#define MD_IRQID_SW_TRIGGER_RESERVED_25             305
+#define MD_IRQID_SW_TRIGGER_RESERVED_26             306
+#define MD_IRQID_SW_TRIGGER_RESERVED_27             307
+#define MD_IRQID_SW_TRIGGER_RESERVED_28             308
+#define MD_IRQID_SW_TRIGGER_RESERVED_29             309
+#define MD_IRQID_SW_TRIGGER_RESERVED_30             310
+#define MD_IRQID_SW_TRIGGER_RESERVED_31             311
+#define MD_IRQID_SW_TRIGGER_RESERVED_32             312
+#define MD_IRQID_SW_TRIGGER_RESERVED_33             313
+#define MD_IRQID_SW_TRIGGER_RESERVED_34             314
+#define MD_IRQID_SW_TRIGGER_RESERVED_35             315
+#define MD_IRQID_SW_TRIGGER_RESERVED_36             316
+#define MD_IRQID_SW_TRIGGER_RESERVED_37             317
+#define MD_IRQID_SW_TRIGGER_RESERVED_38             318
+#define MD_IRQID_SW_TRIGGER_RESERVED_39             319
+#define MD_IRQID_SW_TRIGGER_RESERVED_40             320
+#define MD_IRQID_SW_TRIGGER_RESERVED_41             321
+#define MD_IRQID_SW_TRIGGER_RESERVED_42             322
+#define MD_IRQID_SW_TRIGGER_RESERVED_43             323
+#define MD_IRQID_SW_TRIGGER_RESERVED_44             324
+#define MD_IRQID_SW_TRIGGER_RESERVED_45             325
+#define MD_IRQID_SW_TRIGGER_RESERVED_46             326
+#define MD_IRQID_SW_TRIGGER_RESERVED_47             327
+#define MD_IRQID_SW_TRIGGER_RESERVED_48             328
+#define MD_IRQID_SW_TRIGGER_RESERVED_49             329
+#define MD_IRQID_SW_TRIGGER_RESERVED_50             330
+#define MD_IRQID_SW_TRIGGER_RESERVED_51             331
+#define MD_IRQID_SW_TRIGGER_RESERVED_52             332
+#define MD_IRQID_SW_TRIGGER_RESERVED_53             333
+#define MD_IRQID_SW_TRIGGER_RESERVED_54             334
+#define MD_IRQID_SW_TRIGGER_RESERVED_55             335
+#define MD_IRQID_SW_TRIGGER_RESERVED_56             336
+#define MD_IRQID_SW_TRIGGER_RESERVED_57             337
+#define MD_IRQID_SW_TRIGGER_RESERVED_58             338
+#define MD_IRQID_SW_TRIGGER_RESERVED_59             339
+#define MD_IRQID_SW_TRIGGER_RESERVED_60             340
+#define MD_IRQID_SW_TRIGGER_RESERVED_61             341
+#define MD_IRQID_SW_TRIGGER_RESERVED_62             342
+#define MD_IRQID_SW_TRIGGER_RESERVED_63             343
+#define MD_IRQID_SW_TRIGGER_RESERVED_64             344
+#define MD_IRQID_DUMMY_PRIORITY_IRQ8                345
+#define MD_IRQID_DUMMY_PRIORITY_IRQ9                346
+#define MD_IRQID_DUMMY_PRIORITY_IRQ10               347
+#define MD_IRQID_DUMMY_PRIORITY_IRQ11               348
+#define MD_IRQID_DUMMY_PRIORITY_IRQ12               349
+#define MD_IRQID_DUMMY_PRIORITY_IRQ13               350
+#define MD_IRQID_DUMMY_PRIORITY_IRQ14               351
+#define MD_IRQID_DUMMY_PRIORITY_IRQ15               352
+#define MD_IRQID_DUMMY_PRIORITY_IRQ16               353
+#define MD_IRQID_DUMMY_PRIORITY_IRQ17               354
+#define MD_IRQID_DUMMY_PRIORITY_IRQ18               355
+#define MD_IRQID_DUMMY_PRIORITY_IRQ19               356
+#define MD_IRQID_DUMMY_PRIORITY_IRQ20               357
+#define MD_IRQID_DUMMY_PRIORITY_IRQ21               358
+#define MD_IRQID_DUMMY_PRIORITY_IRQ22               359
+#define MD_IRQID_DUMMY_PRIORITY_IRQ23               360
+#define MD_IRQID_DUMMY_PRIORITY_IRQ24               361
+#define MD_IRQID_DUMMY_PRIORITY_IRQ25               362
+#define MD_IRQID_DUMMY_PRIORITY_IRQ26               363
+#define MD_IRQID_DUMMY_PRIORITY_IRQ27               364
+#define MD_IRQID_DUMMY_PRIORITY_IRQ28               365
+#define MD_IRQID_DUMMY_PRIORITY_IRQ29               366
+#define MD_IRQID_DUMMY_PRIORITY_IRQ30               367
+
+
+/* VPE internal IRQID */
+#define VPE_IRQID_SW_Trigger0 0
+#define VPE_IRQID_SW_Trigger1 1
+#define VPE_IRQID_IPPCI 2
+#define VPE_IRQID_IPTI 3
+#define VPE_IRQID_IPFDCI 4
+#define VPE_IRQID_OSIPI 5
+#define VPE_IRQID_MDCIRQ 6
+#define VPE_IRQID_CSC 7
+#define VPE_IRQID_END 8
+#define VPE_MAX_IRQ_NUM 8
+
+#endif /*end of __MERCURY_IRQID_H__*/
diff --git a/mcu/interface/driver/devdrv/cirq/md97p/isrentry.h b/mcu/interface/driver/devdrv/cirq/md97p/isrentry.h
new file mode 100644
index 0000000..63ba404
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cirq/md97p/isrentry.h
@@ -0,0 +1,103 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   isrentry.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+/*******************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2001
+*
+*******************************************************************************/
+
+#ifndef _ISRENTRY_H
+#define _ISRENTRY_H
+
+#include "kal_general_types.h"
+
+/*************************************************************************
+ * Define data structures.
+ *************************************************************************/
+
+typedef struct 
+{
+   kal_uint32 vector;
+   void (*lisr_handler) (kal_uint32);
+   kal_char *description;
+} irqlisr_entry;
+
+/*************************************************************************
+ * Define function prototypes.
+ *************************************************************************/
+#define IRQ_Default_LISR MDCIRQ_IRQ_Default_LISR
+
+void MDCIRQ_IRQ_LISR_Init(void);
+void MDCIRQ_IRQ_Default_LISR(kal_uint32);
+
+
+#endif /* _ISRENTRY_H */
+
+
diff --git a/mcu/interface/driver/devdrv/cmif/inc/basic_load/cmif_m2c_isr_config_do_pd.h b/mcu/interface/driver/devdrv/cmif/inc/basic_load/cmif_m2c_isr_config_do_pd.h
new file mode 100644
index 0000000..c5efcd1
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cmif/inc/basic_load/cmif_m2c_isr_config_do_pd.h
@@ -0,0 +1,515 @@
+#if defined(__MD32S_CMIF_DRV_TEST__)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ0)
+irq_name("CMIF_M2C_DO_PD_IRQ0")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1)
+irq_name("CMIF_M2C_DO_PD_IRQ1")
+irq_entry_function(CMIF_DriverTestISR_DO_PD)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ2)
+irq_name("CMIF_M2C_DO_PD_IRQ2")
+irq_entry_function(CMIF_DriverTestISR_DO_PD)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ3)
+irq_name("CMIF_M2C_DO_PD_IRQ3")
+irq_entry_function(CMIF_DriverTestISR_DO_PD)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ4)
+irq_name("CMIF_M2C_DO_PD_IRQ4")
+irq_entry_function(CMIF_DriverTestISR_DO_PD)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ5)
+irq_name("CMIF_M2C_DO_PD_IRQ5")
+irq_entry_function(CMIF_DriverTestISR_DO_PD)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ6)
+irq_name("CMIF_M2C_DO_PD_IRQ6")
+irq_entry_function(CMIF_DriverTestISR_DO_PD)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ7)
+irq_name("CMIF_M2C_DO_PD_IRQ7")
+irq_entry_function(CMIF_DriverTestISR_DO_PD)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ8)
+irq_name("CMIF_M2C_DO_PD_IRQ8")
+irq_entry_function(CMIF_DriverTestISR_DO_PD)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ9)
+irq_name("CMIF_M2C_DO_PD_IRQ9")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQA)
+irq_name("CMIF_M2C_DO_PD_IRQA")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQB)
+irq_name("CMIF_M2C_DO_PD_IRQB")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQC)
+irq_name("CMIF_M2C_DO_PD_IRQC")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQD)
+irq_name("CMIF_M2C_DO_PD_IRQD")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQE)
+irq_name("CMIF_M2C_DO_PD_IRQE")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQF)
+irq_name("CMIF_M2C_DO_PD_IRQF")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ10)
+irq_name("CMIF_M2C_DO_PD_IRQ10")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ11)
+irq_name("CMIF_M2C_DO_PD_IRQ11")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ12)
+irq_name("CMIF_M2C_DO_PD_IRQ12")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ13)
+irq_name("CMIF_M2C_DO_PD_IRQ13")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ14)
+irq_name("CMIF_M2C_DO_PD_IRQ14")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ15)
+irq_name("CMIF_M2C_DO_PD_IRQ15")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ16)
+irq_name("CMIF_M2C_DO_PD_IRQ16")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ17)
+irq_name("CMIF_M2C_DO_PD_IRQ17")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ18)
+irq_name("CMIF_M2C_DO_PD_IRQ18")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ19)
+irq_name("CMIF_M2C_DO_PD_IRQ19")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1A)
+irq_name("CMIF_M2C_DO_PD_IRQ1A")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1B)
+irq_name("CMIF_M2C_DO_PD_IRQ1B")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1C)
+irq_name("CMIF_M2C_DO_PD_IRQ1C")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1D)
+irq_name("CMIF_M2C_DO_PD_IRQ1D")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1E)
+irq_name("CMIF_M2C_DO_PD_IRQ1E")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1F)
+irq_name("CMIF_M2C_DO_PD_IRQ1F")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else /* basic load */
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ0)
+irq_name("CMIF_M2C_DO_PD_IRQ0")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1)
+irq_name("CMIF_M2C_DO_PD_IRQ1")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ2)
+irq_name("CMIF_M2C_DO_PD_IRQ2")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ3)
+irq_name("CMIF_M2C_DO_PD_IRQ3")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ4)
+irq_name("CMIF_M2C_DO_PD_IRQ4")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ5)
+irq_name("CMIF_M2C_DO_PD_IRQ5")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ6)
+irq_name("CMIF_M2C_DO_PD_IRQ6")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ7)
+irq_name("CMIF_M2C_DO_PD_IRQ7")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ8)
+irq_name("CMIF_M2C_DO_PD_IRQ8")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ9)
+irq_name("CMIF_M2C_DO_PD_IRQ9")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQA)
+irq_name("CMIF_M2C_DO_PD_IRQA")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQB)
+irq_name("CMIF_M2C_DO_PD_IRQB")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQC)
+irq_name("CMIF_M2C_DO_PD_IRQC")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQD)
+irq_name("CMIF_M2C_DO_PD_IRQD")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQE)
+irq_name("CMIF_M2C_DO_PD_IRQE")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQF)
+irq_name("CMIF_M2C_DO_PD_IRQF")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ10)
+irq_name("CMIF_M2C_DO_PD_IRQ10")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ11)
+irq_name("CMIF_M2C_DO_PD_IRQ11")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ12)
+irq_name("CMIF_M2C_DO_PD_IRQ12")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ13)
+irq_name("CMIF_M2C_DO_PD_IRQ13")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ14)
+irq_name("CMIF_M2C_DO_PD_IRQ14")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ15)
+irq_name("CMIF_M2C_DO_PD_IRQ15")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ16)
+irq_name("CMIF_M2C_DO_PD_IRQ16")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ17)
+irq_name("CMIF_M2C_DO_PD_IRQ17")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ18)
+irq_name("CMIF_M2C_DO_PD_IRQ18")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ19)
+irq_name("CMIF_M2C_DO_PD_IRQ19")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1A)
+irq_name("CMIF_M2C_DO_PD_IRQ1A")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1B)
+irq_name("CMIF_M2C_DO_PD_IRQ1B")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1C)
+irq_name("CMIF_M2C_DO_PD_IRQ1C")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1D)
+irq_name("CMIF_M2C_DO_PD_IRQ1D")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1E)
+irq_name("CMIF_M2C_DO_PD_IRQ1E")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_DO_PD_IRQ1F)
+irq_name("CMIF_M2C_DO_PD_IRQ1F")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cmif/inc/basic_load/cmif_m2c_isr_config_foe_1x.h b/mcu/interface/driver/devdrv/cmif/inc/basic_load/cmif_m2c_isr_config_foe_1x.h
new file mode 100644
index 0000000..6d2b023
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cmif/inc/basic_load/cmif_m2c_isr_config_foe_1x.h
@@ -0,0 +1,515 @@
+#if defined(__MD32S_CMIF_DRV_TEST__)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ0)
+irq_name("CMIF_M2C_FOE_1X_IRQ0")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1)
+irq_name("CMIF_M2C_FOE_1X_IRQ1")
+irq_entry_function(CMIF_DriverTestISR_FOE_1X)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ2)
+irq_name("CMIF_M2C_FOE_1X_IRQ2")
+irq_entry_function(CMIF_DriverTestISR_FOE_1X)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ3)
+irq_name("CMIF_M2C_FOE_1X_IRQ3")
+irq_entry_function(CMIF_DriverTestISR_FOE_1X)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ4)
+irq_name("CMIF_M2C_FOE_1X_IRQ4")
+irq_entry_function(CMIF_DriverTestISR_FOE_1X)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ5)
+irq_name("CMIF_M2C_FOE_1X_IRQ5")
+irq_entry_function(CMIF_DriverTestISR_FOE_1X)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ6)
+irq_name("CMIF_M2C_FOE_1X_IRQ6")
+irq_entry_function(CMIF_DriverTestISR_FOE_1X)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ7)
+irq_name("CMIF_M2C_FOE_1X_IRQ7")
+irq_entry_function(CMIF_DriverTestISR_FOE_1X)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ8)
+irq_name("CMIF_M2C_FOE_1X_IRQ8")
+irq_entry_function(CMIF_DriverTestISR_FOE_1X)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ9)
+irq_name("CMIF_M2C_FOE_1X_IRQ9")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQA)
+irq_name("CMIF_M2C_FOE_1X_IRQA")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQB)
+irq_name("CMIF_M2C_FOE_1X_IRQB")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQC)
+irq_name("CMIF_M2C_FOE_1X_IRQC")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQD)
+irq_name("CMIF_M2C_FOE_1X_IRQD")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQE)
+irq_name("CMIF_M2C_FOE_1X_IRQE")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQF)
+irq_name("CMIF_M2C_FOE_1X_IRQF")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ10)
+irq_name("CMIF_M2C_FOE_1X_IRQ10")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ11)
+irq_name("CMIF_M2C_FOE_1X_IRQ11")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ12)
+irq_name("CMIF_M2C_FOE_1X_IRQ12")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ13)
+irq_name("CMIF_M2C_FOE_1X_IRQ13")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ14)
+irq_name("CMIF_M2C_FOE_1X_IRQ14")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ15)
+irq_name("CMIF_M2C_FOE_1X_IRQ15")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ16)
+irq_name("CMIF_M2C_FOE_1X_IRQ16")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ17)
+irq_name("CMIF_M2C_FOE_1X_IRQ17")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ18)
+irq_name("CMIF_M2C_FOE_1X_IRQ18")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ19)
+irq_name("CMIF_M2C_FOE_1X_IRQ19")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1A)
+irq_name("CMIF_M2C_FOE_1X_IRQ1A")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1B)
+irq_name("CMIF_M2C_FOE_1X_IRQ1B")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1C)
+irq_name("CMIF_M2C_FOE_1X_IRQ1C")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1D)
+irq_name("CMIF_M2C_FOE_1X_IRQ1D")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1E)
+irq_name("CMIF_M2C_FOE_1X_IRQ1E")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1F)
+irq_name("CMIF_M2C_FOE_1X_IRQ1F")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else /* basic load */
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ0)
+irq_name("CMIF_M2C_FOE_1X_IRQ0")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1)
+irq_name("CMIF_M2C_FOE_1X_IRQ1")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ2)
+irq_name("CMIF_M2C_FOE_1X_IRQ2")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ3)
+irq_name("CMIF_M2C_FOE_1X_IRQ3")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ4)
+irq_name("CMIF_M2C_FOE_1X_IRQ4")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ5)
+irq_name("CMIF_M2C_FOE_1X_IRQ5")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ6)
+irq_name("CMIF_M2C_FOE_1X_IRQ6")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ7)
+irq_name("CMIF_M2C_FOE_1X_IRQ7")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ8)
+irq_name("CMIF_M2C_FOE_1X_IRQ8")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ9)
+irq_name("CMIF_M2C_FOE_1X_IRQ9")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQA)
+irq_name("CMIF_M2C_FOE_1X_IRQA")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQB)
+irq_name("CMIF_M2C_FOE_1X_IRQB")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQC)
+irq_name("CMIF_M2C_FOE_1X_IRQC")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQD)
+irq_name("CMIF_M2C_FOE_1X_IRQD")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQE)
+irq_name("CMIF_M2C_FOE_1X_IRQE")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQF)
+irq_name("CMIF_M2C_FOE_1X_IRQF")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ10)
+irq_name("CMIF_M2C_FOE_1X_IRQ10")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ11)
+irq_name("CMIF_M2C_FOE_1X_IRQ11")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ12)
+irq_name("CMIF_M2C_FOE_1X_IRQ12")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ13)
+irq_name("CMIF_M2C_FOE_1X_IRQ13")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ14)
+irq_name("CMIF_M2C_FOE_1X_IRQ14")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ15)
+irq_name("CMIF_M2C_FOE_1X_IRQ15")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ16)
+irq_name("CMIF_M2C_FOE_1X_IRQ16")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ17)
+irq_name("CMIF_M2C_FOE_1X_IRQ17")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ18)
+irq_name("CMIF_M2C_FOE_1X_IRQ18")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ19)
+irq_name("CMIF_M2C_FOE_1X_IRQ19")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1A)
+irq_name("CMIF_M2C_FOE_1X_IRQ1A")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1B)
+irq_name("CMIF_M2C_FOE_1X_IRQ1B")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1C)
+irq_name("CMIF_M2C_FOE_1X_IRQ1C")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1D)
+irq_name("CMIF_M2C_FOE_1X_IRQ1D")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1E)
+irq_name("CMIF_M2C_FOE_1X_IRQ1E")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FOE_1X_IRQ1F)
+irq_name("CMIF_M2C_FOE_1X_IRQ1F")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cmif/inc/basic_load/cmif_m2c_isr_config_fpc_1x.h b/mcu/interface/driver/devdrv/cmif/inc/basic_load/cmif_m2c_isr_config_fpc_1x.h
new file mode 100644
index 0000000..9494060
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cmif/inc/basic_load/cmif_m2c_isr_config_fpc_1x.h
@@ -0,0 +1,515 @@
+#if defined(__MD32S_CMIF_DRV_TEST__)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ0)
+irq_name("CMIF_M2C_FPC_1X_IRQ0")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1)
+irq_name("CMIF_M2C_FPC_1X_IRQ1")
+irq_entry_function(CMIF_DriverTestISR_FPC_1X)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ2)
+irq_name("CMIF_M2C_FPC_1X_IRQ2")
+irq_entry_function(CMIF_DriverTestISR_FPC_1X)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ3)
+irq_name("CMIF_M2C_FPC_1X_IRQ3")
+irq_entry_function(CMIF_DriverTestISR_FPC_1X)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ4)
+irq_name("CMIF_M2C_FPC_1X_IRQ4")
+irq_entry_function(CMIF_DriverTestISR_FPC_1X)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ5)
+irq_name("CMIF_M2C_FPC_1X_IRQ5")
+irq_entry_function(CMIF_DriverTestISR_FPC_1X)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ6)
+irq_name("CMIF_M2C_FPC_1X_IRQ6")
+irq_entry_function(CMIF_DriverTestISR_FPC_1X)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ7)
+irq_name("CMIF_M2C_FPC_1X_IRQ7")
+irq_entry_function(CMIF_DriverTestISR_FPC_1X)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ8)
+irq_name("CMIF_M2C_FPC_1X_IRQ8")
+irq_entry_function(CMIF_DriverTestISR_FPC_1X)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ9)
+irq_name("CMIF_M2C_FPC_1X_IRQ9")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQA)
+irq_name("CMIF_M2C_FPC_1X_IRQA")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQB)
+irq_name("CMIF_M2C_FPC_1X_IRQB")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQC)
+irq_name("CMIF_M2C_FPC_1X_IRQC")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQD)
+irq_name("CMIF_M2C_FPC_1X_IRQD")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQE)
+irq_name("CMIF_M2C_FPC_1X_IRQE")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQF)
+irq_name("CMIF_M2C_FPC_1X_IRQF")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ10)
+irq_name("CMIF_M2C_FPC_1X_IRQ10")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ11)
+irq_name("CMIF_M2C_FPC_1X_IRQ11")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ12)
+irq_name("CMIF_M2C_FPC_1X_IRQ12")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ13)
+irq_name("CMIF_M2C_FPC_1X_IRQ13")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ14)
+irq_name("CMIF_M2C_FPC_1X_IRQ14")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ15)
+irq_name("CMIF_M2C_FPC_1X_IRQ15")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ16)
+irq_name("CMIF_M2C_FPC_1X_IRQ16")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ17)
+irq_name("CMIF_M2C_FPC_1X_IRQ17")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ18)
+irq_name("CMIF_M2C_FPC_1X_IRQ18")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ19)
+irq_name("CMIF_M2C_FPC_1X_IRQ19")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1A)
+irq_name("CMIF_M2C_FPC_1X_IRQ1A")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1B)
+irq_name("CMIF_M2C_FPC_1X_IRQ1B")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1C)
+irq_name("CMIF_M2C_FPC_1X_IRQ1C")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1D)
+irq_name("CMIF_M2C_FPC_1X_IRQ1D")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1E)
+irq_name("CMIF_M2C_FPC_1X_IRQ1E")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1F)
+irq_name("CMIF_M2C_FPC_1X_IRQ1F")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else /* basic load */
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ0)
+irq_name("CMIF_M2C_FPC_1X_IRQ0")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1)
+irq_name("CMIF_M2C_FPC_1X_IRQ1")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ2)
+irq_name("CMIF_M2C_FPC_1X_IRQ2")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ3)
+irq_name("CMIF_M2C_FPC_1X_IRQ3")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ4)
+irq_name("CMIF_M2C_FPC_1X_IRQ4")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ5)
+irq_name("CMIF_M2C_FPC_1X_IRQ5")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ6)
+irq_name("CMIF_M2C_FPC_1X_IRQ6")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ7)
+irq_name("CMIF_M2C_FPC_1X_IRQ7")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ8)
+irq_name("CMIF_M2C_FPC_1X_IRQ8")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ9)
+irq_name("CMIF_M2C_FPC_1X_IRQ9")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQA)
+irq_name("CMIF_M2C_FPC_1X_IRQA")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQB)
+irq_name("CMIF_M2C_FPC_1X_IRQB")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQC)
+irq_name("CMIF_M2C_FPC_1X_IRQC")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQD)
+irq_name("CMIF_M2C_FPC_1X_IRQD")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQE)
+irq_name("CMIF_M2C_FPC_1X_IRQE")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQF)
+irq_name("CMIF_M2C_FPC_1X_IRQF")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ10)
+irq_name("CMIF_M2C_FPC_1X_IRQ10")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ11)
+irq_name("CMIF_M2C_FPC_1X_IRQ11")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ12)
+irq_name("CMIF_M2C_FPC_1X_IRQ12")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ13)
+irq_name("CMIF_M2C_FPC_1X_IRQ13")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ14)
+irq_name("CMIF_M2C_FPC_1X_IRQ14")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ15)
+irq_name("CMIF_M2C_FPC_1X_IRQ15")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ16)
+irq_name("CMIF_M2C_FPC_1X_IRQ16")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ17)
+irq_name("CMIF_M2C_FPC_1X_IRQ17")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ18)
+irq_name("CMIF_M2C_FPC_1X_IRQ18")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ19)
+irq_name("CMIF_M2C_FPC_1X_IRQ19")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1A)
+irq_name("CMIF_M2C_FPC_1X_IRQ1A")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1B)
+irq_name("CMIF_M2C_FPC_1X_IRQ1B")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1C)
+irq_name("CMIF_M2C_FPC_1X_IRQ1C")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1D)
+irq_name("CMIF_M2C_FPC_1X_IRQ1D")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1E)
+irq_name("CMIF_M2C_FPC_1X_IRQ1E")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_FPC_1X_IRQ1F)
+irq_name("CMIF_M2C_FPC_1X_IRQ1F")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cmif/inc/basic_load/cmif_m2c_isr_config_u3g_rake.h b/mcu/interface/driver/devdrv/cmif/inc/basic_load/cmif_m2c_isr_config_u3g_rake.h
new file mode 100644
index 0000000..9a50374
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cmif/inc/basic_load/cmif_m2c_isr_config_u3g_rake.h
@@ -0,0 +1,515 @@
+#if defined(__MD32S_CMIF_DRV_TEST__)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ0)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ0")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1")
+irq_entry_function(CMIF_DriverTestISR_U3G)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ2)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ2")
+irq_entry_function(CMIF_DriverTestISR_U3G)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ3)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ3")
+irq_entry_function(CMIF_DriverTestISR_U3G)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ4)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ4")
+irq_entry_function(CMIF_DriverTestISR_U3G)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ5)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ5")
+irq_entry_function(CMIF_DriverTestISR_U3G)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ6)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ6")
+irq_entry_function(CMIF_DriverTestISR_U3G)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ7)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ7")
+irq_entry_function(CMIF_DriverTestISR_U3G)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ8)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ8")
+irq_entry_function(CMIF_DriverTestISR_U3G)
+irq_auto_eoi(CMIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ9)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ9")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQA)
+irq_name("CMIF_M2C_U3G_RAKE_IRQA")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQB)
+irq_name("CMIF_M2C_U3G_RAKE_IRQB")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQC)
+irq_name("CMIF_M2C_U3G_RAKE_IRQC")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQD)
+irq_name("CMIF_M2C_U3G_RAKE_IRQD")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQE)
+irq_name("CMIF_M2C_U3G_RAKE_IRQE")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQF)
+irq_name("CMIF_M2C_U3G_RAKE_IRQF")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ10)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ10")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ11)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ11")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ12)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ12")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ13)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ13")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ14)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ14")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ15)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ15")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ16)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ16")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ17)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ17")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ18)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ18")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ19)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ19")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1A)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1A")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1B)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1B")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1C)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1C")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1D)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1D")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1E)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1E")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1F)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1F")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else /* basic load */
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ0)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ0")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ2)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ2")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ3)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ3")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ4)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ4")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ5)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ5")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ6)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ6")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ7)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ7")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ8)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ8")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ9)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ9")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQA)
+irq_name("CMIF_M2C_U3G_RAKE_IRQA")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQB)
+irq_name("CMIF_M2C_U3G_RAKE_IRQB")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQC)
+irq_name("CMIF_M2C_U3G_RAKE_IRQC")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQD)
+irq_name("CMIF_M2C_U3G_RAKE_IRQD")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQE)
+irq_name("CMIF_M2C_U3G_RAKE_IRQE")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQF)
+irq_name("CMIF_M2C_U3G_RAKE_IRQF")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ10)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ10")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ11)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ11")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ12)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ12")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ13)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ13")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ14)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ14")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ15)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ15")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ16)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ16")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ17)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ17")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ18)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ18")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ19)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ19")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1A)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1A")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1B)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1B")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1C)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1C")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1D)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1D")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1E)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1E")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CMIF_M2C_U3G_RAKE_IRQ1F)
+irq_name("CMIF_M2C_U3G_RAKE_IRQ1F")
+irq_entry_function(CMIF_DefaultISR)
+irq_auto_eoi(CMIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cmif/inc/cmif_m2c_isr_config_do_pd_pre.h b/mcu/interface/driver/devdrv/cmif/inc/cmif_m2c_isr_config_do_pd_pre.h
new file mode 100644
index 0000000..67186eb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cmif/inc/cmif_m2c_isr_config_do_pd_pre.h
@@ -0,0 +1,9 @@
+#if defined(__MAUI_BASIC__)
+
+    #include "basic_load/cmif_m2c_isr_config_do_pd.h"
+
+#else
+    
+    #include "cmif_m2c_isr_config_do_pd.h"
+    
+#endif
diff --git a/mcu/interface/driver/devdrv/cmif/inc/cmif_m2c_isr_config_foe_1x_pre.h b/mcu/interface/driver/devdrv/cmif/inc/cmif_m2c_isr_config_foe_1x_pre.h
new file mode 100644
index 0000000..f6ead93
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cmif/inc/cmif_m2c_isr_config_foe_1x_pre.h
@@ -0,0 +1,9 @@
+#if defined(__MAUI_BASIC__)
+
+    #include "basic_load/cmif_m2c_isr_config_foe_1x.h"
+
+#else
+    
+    #include "cmif_m2c_isr_config_foe_1x.h"
+    
+#endif
diff --git a/mcu/interface/driver/devdrv/cmif/inc/cmif_m2c_isr_config_fpc_1x_pre.h b/mcu/interface/driver/devdrv/cmif/inc/cmif_m2c_isr_config_fpc_1x_pre.h
new file mode 100644
index 0000000..fd543ee
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cmif/inc/cmif_m2c_isr_config_fpc_1x_pre.h
@@ -0,0 +1,9 @@
+#if defined(__MAUI_BASIC__)
+
+    #include "basic_load/cmif_m2c_isr_config_fpc_1x.h"
+
+#else
+    
+    #include "cmif_m2c_isr_config_fpc_1x.h"
+    
+#endif
diff --git a/mcu/interface/driver/devdrv/cmif/inc/cmif_m2c_isr_config_u3g_rake_pre.h b/mcu/interface/driver/devdrv/cmif/inc/cmif_m2c_isr_config_u3g_rake_pre.h
new file mode 100644
index 0000000..1c55374
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cmif/inc/cmif_m2c_isr_config_u3g_rake_pre.h
@@ -0,0 +1,9 @@
+#if defined(__MAUI_BASIC__)
+
+    #include "basic_load/cmif_m2c_isr_config_u3g_rake.h"
+
+#else
+    
+    #include "cmif_m2c_isr_config_u3g_rake.h"
+    
+#endif
diff --git a/mcu/interface/driver/devdrv/cmif/inc/drv_cmif.h b/mcu/interface/driver/devdrv/cmif/inc/drv_cmif.h
new file mode 100644
index 0000000..ca692f3
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cmif/inc/drv_cmif.h
@@ -0,0 +1,234 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2014
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   cmif.h
+ *
+ * Project:
+ * --------
+ *   
+ *
+ * Description:
+ * ------------
+ *   
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+  * $Revision$
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __DRV_CMIF_H__
+#define __DRV_CMIF_H__
+
+
+#include "kal_public_api.h"
+#include "kal_general_types.h"
+
+#include "cmif_common_def.h"
+
+/*******************************************************************************
+ * Typedefs 
+ *******************************************************************************/
+/*
+
+emum CMIF_C2M_U3G_Code_t defined in
+"common/interface/driver/sys_drv/cmif/cmif_c2m_isr_config_u3g.h"
+
+emum CMIF_M2C_U3G_Code_t defined in
+"common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_u3g_rake.h"
+
+emum CMIF_M2C_FPC_1X_Code_t defined in
+"common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_fpc_1x.h"
+
+emum CMIF_M2C_DO_PD_Code_t defined in
+"common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_do_pd.h"
+
+emum CMIF_M2C_FOE_1X_Code_t defined in
+"common/interface/driver/sys_drv/cmif/cmif_m2c_isr_config_foe_1x.h"
+
+
+// Define status register type
+typedef struct{
+    kal_uint32 mask31_0;    
+}CMIF_Mask_t;
+*/
+
+typedef kal_char                cmif_char;   
+typedef kal_uint8               cmif_uint8;  
+typedef kal_int8                cmif_int8;   
+typedef kal_uint16              cmif_uint16; 
+typedef kal_int16               cmif_int16;  
+typedef kal_uint32              cmif_uint32; 
+typedef kal_int32               cmif_int32;  
+typedef kal_bool                cmif_bool;
+
+/* User callback should be registered in common/interface/driver/sys_drv/cmif/ */
+
+// Define user callback function type
+typedef void (*CMIF_InterruptEntryFun)(CMIF_Mask_t*);
+
+/*******************************************************************************
+ * Function prototypes
+ *******************************************************************************/
+/**
+  *  CMIF Init: Register Interrupt
+  *  It would register IRQ for
+  *     - M2C RAKE U3G, FPC_1X, DO_PD, FOE_1X
+  */
+extern void CMIF_Init();
+
+
+/**
+  *  CMIF Interrupt: MCU trigger MD32 
+  *
+  *  @param[in]  code  trigger interrupt code. Please use enum defined in index(enum) of callback table
+  *  @return no return
+  *
+  **/
+extern void CMIF_C2M_SWI_SW_U3G(CMIF_C2M_U3G_Code_t code);
+
+
+
+/**
+  *  Get CMIF Status register value
+  *  @param[in]   mask    the value of status register(s)
+  *
+  **/
+extern void CMIF_M2C_STATUS_U3G(CMIF_Mask_t* mask);
+extern void CMIF_M2C_STATUS_FPC_1X(CMIF_Mask_t* mask);
+extern void CMIF_M2C_STATUS_DO_PD(CMIF_Mask_t* mask);
+extern void CMIF_M2C_STATUS_FOE_1X(CMIF_Mask_t* mask);
+
+extern void CMIF_C2M_STATUS_U3G(CMIF_Mask_t* mask);
+
+
+extern cmif_uint32 CMIF_C2M_STATUS_U3G_READ();
+
+extern cmif_bool CMIF_MD32AllowPowerDown();
+
+
+/**
+  *   When the `irq_auto_eoi()` attribute is `CMIF_FALSE`
+  *   Users could call these function to clean the interrupt bit 
+  */
+extern void CMIF_M2C_EOI_U3G(CMIF_M2C_U3G_Code_t code);
+extern void CMIF_M2C_EOI_FPC_1X(CMIF_M2C_FPC_1X_Code_t code);
+extern void CMIF_M2C_EOI_DO_PD(CMIF_M2C_DO_PD_Code_t code);
+extern void CMIF_M2C_EOI_FOE_1X(CMIF_M2C_FOE_1X_Code_t code);
+
+
+
+#endif   /* __DRV_CMIF_H__ */
diff --git a/mcu/interface/driver/devdrv/cpu/cpu.h b/mcu/interface/driver/devdrv/cpu/cpu.h
new file mode 100644
index 0000000..2ade9ef
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cpu/cpu.h
@@ -0,0 +1,137 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   cpu.h
+ *
+ * Project:
+ * --------
+ *   TATAKA
+ *
+ * Description:
+ * ------------
+ *   For CPU related functions
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 11 20 2017 tungchieh.tsai
+ * [MOLY00290533] [UMOLYA] Phase out CPU_CLOCK_MHZ relative API
+ *
+ * 12 13 2016 tungchieh.tsai
+ * [MOLY00216138] Integrate MDMCU macro
+ *
+ * 12 08 2016 tungchieh.tsai
+ * [MOLY00216138] Integrate MDMCU macro
+ *
+ * 12 08 2016 tungchieh.tsai
+ * [MOLY00216138] Integrate MDMCU macro
+ *
+ * 06 03 2016 yh.peng
+ * [MOLY00182649] [UMOLY/UMOLYA] Fix build warning.
+ * .
+ *
+ * 10 06 2015 yh.peng
+ * [MOLY00142591] [6292] 91Plus merge back to UMOLY
+ * Check in CPU cycle counter API.
+ *
+ * 08 14 2015 yh.peng
+ * [MOLY00136315] [System Service] [91 plus] Merge Back To UMOLY TRUNK
+ * Check in for Fix build error.
+ *
+ * 05 13 2015 yh.peng
+ * [MOLY00110737] [MT6291+] Check in init code.
+ * .Fix all assembly code to sw break.
+ *
+ * 04 30 2015 hc.yang
+ * [MOLY00110489] [MT6291PLUS] Modify files for BASIC_P load
+ * Phase in necessary modified files for BASIC_P load for MIPS compiler.
+ *
+ * 07 16 2013 cindy.tu
+ * [MOLY00027330] [ARM7toMOLY] ARM7 Build/SYSGEN/Functions Update to TRUNK
+ *
+ * 04 16 2013 chin-chieh.hung
+ * [MOLY00013348] [MT6290 Bring-up] Basic Platform Support
+ * Firstcall branch, MOLY Trunk Code Sync
+ *
+ * 04 08 2013 chin-chieh.hung
+ * [MOLY00013348] [MT6290 Bring-up] Basic Platform Support
+ * update CR4 performance monitor counter macro setting
+ *
+ * 03 27 2013 chin-chieh.hung
+ * [MOLY00012803] malmo asm software tracer support
+ * Add MALMO-SWTR support for MT6290
+ *
+ * 02 05 2013 cindy.tu
+ * [MOLY00009879] Rename MT7208 projects to MT6290
+ * <saved by Perforce>
+ *
+ * 02 04 2013 cindy.tu
+ * [MOLY00009879] Rename MT7208 projects to MT6290
+ * <saved by Perforce>
+ ****************************************************************************/
+
+#ifndef __DEVDRV_CPU_H__
+#define __DEVDRV_CPU_H__
+
+#include "kal_public_defs.h"
+#include "mips_ia_utils_public.h"
+
+/*************************************************************************
+ * Define constants
+ *************************************************************************/
+#define CPU_PMU_COUNTER_WRAP    (0xFFFFFFFFUL)
+
+/*************************************************************************
+ * Define MACROS
+ *************************************************************************/
+
+/* the input(start, end) is 32-bit PMU ticks */
+#define cpu_event_get_duration(start, end) \
+    (((end) >= (start))? ((end) - (start)): ((CPU_PMU_COUNTER_WRAP - (start) + (end) + 1)))
+
+#define cpu_event_counter_get_cycle(counter)    \
+    do {                                        \
+        counter = miu_cycle_counter_read();     \
+    } while(0)
+
+#endif  /* __DEVDRV_CPU_H__ */
diff --git a/mcu/interface/driver/devdrv/cs_sram_ctrl/cs_sram_ctrl_global_extern.h b/mcu/interface/driver/devdrv/cs_sram_ctrl/cs_sram_ctrl_global_extern.h
new file mode 100644
index 0000000..f5b616e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cs_sram_ctrl/cs_sram_ctrl_global_extern.h
@@ -0,0 +1,264 @@
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   sram_ctrl_global_extern.h
+ *
+ * Project:
+ * --------
+ *   R11GX Project depend on makefile configuration
+ *
+ * Description:
+ * ------------
+ *   History for each file.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by Perforce. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by Perforce. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*
+**********************************************************************************************************************************************************
+*[File         ]       sram_ctrl_global_extern.h
+*[Version      ]       v1.0
+*[Revision Date]       2014-12-22
+*[Author       ]       Boky Chen
+*[Description  ]
+*    The program is for sram control user to include [user only need to include the header file!!!].
+*
+*[Copyright]
+*    Copyright (C) 2005 MediaTek Incorporation. All Rights Reserved.
+**********************************************************************************************************************************************************
+*/
+
+#ifndef __SRAM_CTRL_GLOBAL_EXTERN_H__
+#define __SRAM_CTRL_GLOBAL_EXTERN_H__
+
+#include "kal_general_types.h"
+
+typedef enum
+{
+    SRAM_PWR_ON=0,
+    SRAM_PWR_DWN,
+    SRAM_PWR_SLP,
+    SRAM_PWR_DSLP,
+    SRAM_PWR_STAT_END,
+}en_sram_pwr_stat;
+
+typedef enum
+{
+    CS_ICC,
+    CS_IMC,
+    CS_MPC,
+    CS_MMU,
+    CS_CORE_NUM,
+}en_cs_core;
+
+typedef enum
+{
+    CS_CSIF,
+    CS_PM_ICM,
+    CS_DDL_PM,
+    CS_PIC_SRAM_END,
+}en_pic_sram_type;
+
+typedef enum
+{
+    SRAM_SW_CTRL,
+    SRAM_HW_CTRL,
+    SRAM_OWNER_END
+}en_sram_owner;
+
+typedef enum
+{
+     G0_RXTDB_CM    =0x000001
+    ,G1_RXTDB_CM    =0x000002
+    ,G2_RXTDB_CM    =0x000004
+    ,G3_RXTDB_CM    =0x000008
+    ,G4_RXTDB_CM    =0x000010
+    ,G5_RXTDB_CM    =0x000020
+    ,G6_RXTDB_CM    =0x000040
+    ,G7_RXTDB_CM    =0x000080
+    ,G8_RXTDB_CM    =0x000100
+    ,G9_RXTDB_CM    =0x000200
+    ,G10_RXTDB_CM   =0x000400
+    ,G0_RXTDB_TEST  =0x000800
+    ,G0_RXTDB_RX    =0x001000
+    ,G1_RXTDB_RX    =0x002000
+    ,G2_RXTDB_RX    =0x004000
+    ,G3_RXTDB_RX    =0x008000
+    ,G9_RXTDB_RX    =0x010000
+    ,G4_RXTDB_RX    =0x020000
+    ,G5_RXTDB_RX    =0x040000
+    ,G6_RXTDB_RX    =0x080000
+    ,G7_RXTDB_RX    =0x100000
+    ,G8_RXTDB_RX    =0x200000
+}RXTDB_BITMAP;
+
+typedef enum{
+    #undef CS_SRAM_CTRL_ICC_CSIF_REG
+    #undef CS_SRAM_CTRL_IMC_CSIF_REG
+    #undef CS_SRAM_CTRL_MPC_CSIF_REG
+    #undef CS_SRAM_CTRL_ICC_PMICM_REG
+    #undef CS_SRAM_CTRL_IMC_PMICM_REG
+    #undef CS_SRAM_CTRL_MPC_PMICM_REG
+    #undef CS_SRAM_CTRL_IMC_DDLPM_REG
+    #undef CS_SRAM_CTRL_MPC_DDLPM_REG
+    #undef CS_SRAM_CTRL_RXTDB_REG
+    #undef CS_SRAM_CTRL_RXDMP_REG
+
+    #define CS_SRAM_CTRL_ICC_CSIF_REG(power_on_init_state, power_down_init_state) \
+    CS_SRAM_CTRL_ICC_CSIF_ON_INIT = power_on_init_state, CS_SRAM_CTRL_ICC_CSIF_OF_INIT = power_down_init_state,
+    #define CS_SRAM_CTRL_IMC_CSIF_REG(power_on_init_state, power_down_init_state) \
+    CS_SRAM_CTRL_IMC_CSIF_ON_INIT = power_on_init_state, CS_SRAM_CTRL_IMC_CSIF_OF_INIT = power_down_init_state,
+    #define CS_SRAM_CTRL_MPC_CSIF_REG(power_on_init_state, power_down_init_state) \
+    CS_SRAM_CTRL_MPC_CSIF_ON_INIT = power_on_init_state, CS_SRAM_CTRL_MPC_CSIF_OF_INIT = power_down_init_state,
+    #define CS_SRAM_CTRL_ICC_PMICM_REG(power_on_init_state, power_down_init_state) \
+    CS_SRAM_CTRL_ICC_PMICM_ON_INIT = power_on_init_state, CS_SRAM_CTRL_ICC_PMICM_OF_INIT = power_down_init_state,
+    #define CS_SRAM_CTRL_IMC_PMICM_REG(power_on_init_state, power_down_init_state) \
+    CS_SRAM_CTRL_IMC_PMICM_ON_INIT = power_on_init_state, CS_SRAM_CTRL_IMC_PMICM_OF_INIT = power_down_init_state,
+    #define CS_SRAM_CTRL_MPC_PMICM_REG(power_on_init_state, power_down_init_state) \
+    CS_SRAM_CTRL_MPC_PMICM_ON_INIT = power_on_init_state, CS_SRAM_CTRL_MPC_PMICM_OF_INIT = power_down_init_state,
+    #define CS_SRAM_CTRL_IMC_DDLPM_REG(power_on_init_state, power_down_init_state) \
+    CS_SRAM_CTRL_IMC_DDLPM_ON_INIT = power_on_init_state, CS_SRAM_CTRL_IMC_DDLPM_OF_INIT = power_down_init_state,
+    #define CS_SRAM_CTRL_MPC_DDLPM_REG(power_on_init_state, power_down_init_state) \
+    CS_SRAM_CTRL_MPC_DDLPM_ON_INIT = power_on_init_state, CS_SRAM_CTRL_MPC_DDLPM_OF_INIT = power_down_init_state,
+    #define CS_SRAM_CTRL_RXDMP_REG(group_name, err_en_id, sw_or_hw_ctrl, power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_RXTDB_REG(group_name, err_en_id, sw_or_hw_ctrl, power_on_init_state, power_down_init_state) 
+    #include "cs_sram_ctrl_register.h"
+    
+    #undef CS_SRAM_CTRL_ICC_CSIF_REG
+    #undef CS_SRAM_CTRL_IMC_CSIF_REG
+    #undef CS_SRAM_CTRL_MPC_CSIF_REG
+    #undef CS_SRAM_CTRL_ICC_PMICM_REG
+    #undef CS_SRAM_CTRL_IMC_PMICM_REG
+    #undef CS_SRAM_CTRL_MPC_PMICM_REG
+    #undef CS_SRAM_CTRL_IMC_DDLPM_REG
+    #undef CS_SRAM_CTRL_MPC_DDLPM_REG
+    #undef CS_SRAM_CTRL_RXTDB_REG
+    #undef CS_SRAM_CTRL_RXDMP_REG
+    CS_SRAM_CTRL_REG_END
+}cs_sram_ctrl_csif_pm_icm_sw_init_vaule;
+
+typedef enum{
+    #undef CS_SRAM_CTRL_ICC_CSIF_REG
+    #undef CS_SRAM_CTRL_IMC_CSIF_REG
+    #undef CS_SRAM_CTRL_MPC_CSIF_REG
+    #undef CS_SRAM_CTRL_ICC_PMICM_REG
+    #undef CS_SRAM_CTRL_IMC_PMICM_REG
+    #undef CS_SRAM_CTRL_MPC_PMICM_REG
+    #undef CS_SRAM_CTRL_IMC_DDLPM_REG
+    #undef CS_SRAM_CTRL_MPC_DDLPM_REG
+    #undef CS_SRAM_CTRL_RXTDB_REG
+    #undef CS_SRAM_CTRL_RXDMP_REG
+
+    #define CS_SRAM_CTRL_ICC_CSIF_REG(power_on_init_state, power_down_init_state) 
+    #define CS_SRAM_CTRL_IMC_CSIF_REG(power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_MPC_CSIF_REG(power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_ICC_PMICM_REG(power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_IMC_PMICM_REG(power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_MPC_PMICM_REG(power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_IMC_DDLPM_REG(power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_MPC_DDLPM_REG(power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_RXDMP_REG(group_name, err_en_id, sw_or_hw_ctrl, power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_RXTDB_REG(group_name, err_en_id, sw_or_hw_ctrl, power_on_init_state, power_down_init_state) group_name,
+    #include "cs_sram_ctrl_register.h"
+    
+    #undef CS_SRAM_CTRL_ICC_CSIF_REG
+    #undef CS_SRAM_CTRL_IMC_CSIF_REG
+    #undef CS_SRAM_CTRL_MPC_CSIF_REG
+    #undef CS_SRAM_CTRL_ICC_PMICM_REG
+    #undef CS_SRAM_CTRL_IMC_PMICM_REG
+    #undef CS_SRAM_CTRL_MPC_PMICM_REG
+    #undef CS_SRAM_CTRL_IMC_DDLPM_REG
+    #undef CS_SRAM_CTRL_MPC_DDLPM_REG
+    #undef CS_SRAM_CTRL_RXTDB_REG
+    #undef CS_SRAM_CTRL_RXDMP_REG
+    CS_SRAM_RXTDB_GROUP_END
+}cs_sram_rxtdb_group;
+
+typedef enum{
+    #undef CS_SRAM_CTRL_ICC_CSIF_REG
+    #undef CS_SRAM_CTRL_IMC_CSIF_REG
+    #undef CS_SRAM_CTRL_MPC_CSIF_REG
+    #undef CS_SRAM_CTRL_ICC_PMICM_REG
+    #undef CS_SRAM_CTRL_IMC_PMICM_REG
+    #undef CS_SRAM_CTRL_MPC_PMICM_REG
+    #undef CS_SRAM_CTRL_IMC_DDLPM_REG
+    #undef CS_SRAM_CTRL_MPC_DDLPM_REG
+    #undef CS_SRAM_CTRL_RXTDB_REG
+    #undef CS_SRAM_CTRL_RXDMP_REG
+
+    #define CS_SRAM_CTRL_ICC_CSIF_REG(power_on_init_state, power_down_init_state) 
+    #define CS_SRAM_CTRL_IMC_CSIF_REG(power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_MPC_CSIF_REG(power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_ICC_PMICM_REG(power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_IMC_PMICM_REG(power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_MPC_PMICM_REG(power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_IMC_DDLPM_REG(power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_MPC_DDLPM_REG(power_on_init_state, power_down_init_state)
+    #define CS_SRAM_CTRL_RXDMP_REG(group_name, err_en_id, sw_or_hw_ctrl, power_on_init_state, power_down_init_state) group_name,
+    #define CS_SRAM_CTRL_RXTDB_REG(group_name, err_en_id, sw_or_hw_ctrl, power_on_init_state, power_down_init_state) 
+    #include "cs_sram_ctrl_register.h"
+    
+    #undef CS_SRAM_CTRL_ICC_CSIF_REG
+    #undef CS_SRAM_CTRL_IMC_CSIF_REG
+    #undef CS_SRAM_CTRL_MPC_CSIF_REG
+    #undef CS_SRAM_CTRL_ICC_PMICM_REG
+    #undef CS_SRAM_CTRL_IMC_PMICM_REG
+    #undef CS_SRAM_CTRL_MPC_PMICM_REG
+    #undef CS_SRAM_CTRL_IMC_DDLPM_REG
+    #undef CS_SRAM_CTRL_MPC_DDLPM_REG
+    #undef CS_SRAM_CTRL_RXTDB_REG
+    #undef CS_SRAM_CTRL_RXDMP_REG
+    CS_SRAM_RXDMP_GROUP_END
+}cs_sram_rxdmp_group;
+
+#if defined(__ENABLE_CS_SRAM_CTRL__)
+    void                cs_sram_ctrl_init(void);
+    void                set_cur_pic_pwr_stat(en_cs_core cs_core, en_pic_sram_type pic_sram_type, en_sram_pwr_stat pwr_stat);
+    en_sram_pwr_stat    get_cur_pic_pwr_stat(en_cs_core cs_core, en_pic_sram_type pic_sram_type);
+    void                set_mtcmos_off_pic_pwr_stat(en_cs_core cs_core, en_pic_sram_type pic_sram_type, en_sram_pwr_stat pwr_stat);
+    en_sram_pwr_stat    get_mtcmos_off_pic_pwr_stat(en_cs_core cs_core, en_pic_sram_type pic_sram_type);
+    void                set_cur_rxtdb_pwr_stat(kal_uint32 rxtdb_bmap);
+    kal_uint32          get_cur_rxtdb_pwr_stat(void);
+    void                set_cur_rxdmp_pwr_stat(kal_uint32 rxdmp_bmap);
+    kal_uint32          get_cur_rxdmp_pwr_stat(void);
+    void                cs_sram_tiny_init(en_cs_core cs_core);
+    void                cs_sram_check_error_enable(en_cs_core cs_core);
+#else
+    #define             cs_sram_ctrl_init()
+    #define             set_cur_pic_pwr_stat(p1, p2, p3)
+    #define             get_cur_pic_pwr_stat(p1, p2)                    0
+    #define             set_mtcmos_off_pic_pwr_stat(p1, p2, p3)
+    #define             get_mtcmos_off_pic_pwr_stat(p1, p2)             0
+    #define             set_cur_rxtdb_pwr_stat(p1)
+    #define             get_cur_rxtdb_pwr_stat()                        0
+    #define             set_cur_rxdmp_pwr_stat(p1)
+    #define             get_cur_rxdmp_pwr_stat()                        0
+    #define             cs_sram_tiny_init(p1)
+    #define             cs_sram_check_error_enable(p1)
+#endif
+
+#endif //__SRAM_CTRL_GLOBAL_EXTERN_H__
diff --git a/mcu/interface/driver/devdrv/cs_sram_ctrl/cs_sram_ctrl_register.h b/mcu/interface/driver/devdrv/cs_sram_ctrl/cs_sram_ctrl_register.h
new file mode 100644
index 0000000..d36140a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cs_sram_ctrl/cs_sram_ctrl_register.h
@@ -0,0 +1,5 @@
+#if   (defined(MT6763))
+
+#else
+    #error "SRAM control didn't support on this chip!!!"
+#endif
diff --git a/mcu/interface/driver/devdrv/cs_sram_ctrl/cs_sram_ctrl_register_elbrus.h b/mcu/interface/driver/devdrv/cs_sram_ctrl/cs_sram_ctrl_register_elbrus.h
new file mode 100644
index 0000000..dbf9aa3
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cs_sram_ctrl/cs_sram_ctrl_register_elbrus.h
@@ -0,0 +1,24 @@
+/* CS_SRAM_CTRL_XXX_CSIF_REG(power_on_init_state, power_down_init_state)
+ * CS_SRAM_CTRL_XXX_ICM_REG(power_on_init_state, power_down_init_state)
+ * CS_SRAM_CTRL_XXX_PM_REG(power_on_init_state, power_down_init_state)
+ * CS_SRAM_CTRL_XXX_DPM_REG(power_on_init_state, power_down_init_state)
+ * CS_SRAM_CTRL_RXTDB_REG(group_name, err_signal, sw_or_hw_control, power_on_init_state, power_down_init_state) 
+ * CS_SRAM_CTRL_RXDMP_REG(group_name, err_signal, sw_or_hw_control, power_on_init_state, power_down_init_state) 
+ * group_name : add postfix _T to group name to avoid build error
+ *
+ */
+CS_SRAM_CTRL_ICC_CSIF_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+CS_SRAM_CTRL_IMC_CSIF_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+CS_SRAM_CTRL_MPC_CSIF_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+
+CS_SRAM_CTRL_ICC_PMICM_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+CS_SRAM_CTRL_IMC_PMICM_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+CS_SRAM_CTRL_MPC_PMICM_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+
+CS_SRAM_CTRL_MPC_DDLPM_REG(SRAM_PWR_DWN, SRAM_PWR_DWN)
+//RXDMP
+CS_SRAM_CTRL_RXDMP_REG(G0_RXDMP_EXT_T,    rxdmp_ext_sram_active,          SRAM_SW_CTRL, SRAM_PWR_DWN,    SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXDMP_REG(G1_RXDMP_EXT_T,    rxdmp_ext_sram_active,          SRAM_SW_CTRL, SRAM_PWR_DWN,    SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXDMP_REG(G2_RXDMP_EXT_T,    rxdmp_ext_sram_active,          SRAM_SW_CTRL, SRAM_PWR_DWN,    SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXDMP_REG(G3_RXDMP_EXT_T,    rxdmp_ext_sram_active,          SRAM_SW_CTRL, SRAM_PWR_DWN,    SRAM_PWR_DWN)
+
diff --git a/mcu/interface/driver/devdrv/cs_sram_ctrl/cs_sram_ctrl_register_mt6755.h b/mcu/interface/driver/devdrv/cs_sram_ctrl/cs_sram_ctrl_register_mt6755.h
new file mode 100644
index 0000000..099c96c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cs_sram_ctrl/cs_sram_ctrl_register_mt6755.h
@@ -0,0 +1,45 @@
+/* CS_SRAM_CTRL_XXX_CSIF_REG(power_on_init_state, power_down_init_state)
+ * CS_SRAM_CTRL_XXX_ICM_REG(power_on_init_state, power_down_init_state)
+ * CS_SRAM_CTRL_XXX_PM_REG(power_on_init_state, power_down_init_state)
+ * CS_SRAM_CTRL_XXX_DPM_REG(power_on_init_state, power_down_init_state)
+ * CS_SRAM_CTRL_RXTDB_REG(group_name, err_signal, sw_or_hw_control, power_on_init_state, power_down_init_state) 
+ * CS_SRAM_CTRL_RXDMP_REG(group_name, err_signal, sw_or_hw_control, power_on_init_state, power_down_init_state) 
+ * group_name : add postfix _T to group name to avoid build error
+ *
+ */
+CS_SRAM_CTRL_ICC_CSIF_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+CS_SRAM_CTRL_IMC_CSIF_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+CS_SRAM_CTRL_MPC_CSIF_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+
+CS_SRAM_CTRL_ICC_PMICM_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+CS_SRAM_CTRL_IMC_PMICM_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+CS_SRAM_CTRL_MPC_PMICM_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+
+CS_SRAM_CTRL_IMC_DDLPM_REG(SRAM_PWR_DWN, SRAM_PWR_DWN)
+CS_SRAM_CTRL_MPC_DDLPM_REG(SRAM_PWR_DWN, SRAM_PWR_DWN)
+//RXTDB
+CS_SRAM_CTRL_RXTDB_REG(G0_RXTDB_CM_T,   rxtdb_g0_1_cm_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G1_RXTDB_CM_T,   rxtdb_g0_1_cm_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G2_RXTDB_CM_T,   rxtdb_g2_3_4_cm_sram_active,    SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G3_RXTDB_CM_T,   rxtdb_g2_3_4_cm_sram_active,    SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G4_RXTDB_CM_T,   rxtdb_g2_3_4_cm_sram_active,    SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G5_RXTDB_CM_T,   rxtdb_g5_cm_sram_active,        SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G6_RXTDB_CM_T,   rxtdb_g6_7_cm_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G7_RXTDB_CM_T,   rxtdb_g6_7_cm_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G8_RXTDB_CM_T,   rxtdb_g8_9_10_cm_sram_active,   SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G9_RXTDB_CM_T,   rxtdb_g8_9_10_cm_sram_active,   SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G10_RXTDB_CM_T,  rxtdb_g8_9_10_cm_sram_active,   SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G0_RXTDB_TEST_T, rxtdb_g0_test_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G0_RXTDB_RX_T,   rxtdb_g0_1_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G1_RXTDB_RX_T,   rxtdb_g0_1_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G2_RXTDB_RX_T,   rxtdb_g2_3_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G3_RXTDB_RX_T,   rxtdb_g2_3_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G9_RXTDB_RX_T,   rxtdb_g9_rx_sram_active,        SRAM_SW_CTRL, SRAM_PWR_ON,    SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G4_RXTDB_RX_T,   rxtdb_g4_5_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G5_RXTDB_RX_T,   rxtdb_g4_5_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G6_RXTDB_RX_T,   rxtdb_g6_7_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G7_RXTDB_RX_T,   rxtdb_g6_7_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G8_RXTDB_RX_T,   rxtdb_g8_rx_sram_active,        SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+//RXDMP
+CS_SRAM_CTRL_RXDMP_REG(G0_RXDMP_EXT,    rxdmp_ext_sram_active,          SRAM_SW_CTRL, SRAM_PWR_DWN,    SRAM_PWR_DWN)
+
diff --git a/mcu/interface/driver/devdrv/cs_sram_ctrl/cs_sram_ctrl_register_tk6291.h b/mcu/interface/driver/devdrv/cs_sram_ctrl/cs_sram_ctrl_register_tk6291.h
new file mode 100644
index 0000000..099c96c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cs_sram_ctrl/cs_sram_ctrl_register_tk6291.h
@@ -0,0 +1,45 @@
+/* CS_SRAM_CTRL_XXX_CSIF_REG(power_on_init_state, power_down_init_state)
+ * CS_SRAM_CTRL_XXX_ICM_REG(power_on_init_state, power_down_init_state)
+ * CS_SRAM_CTRL_XXX_PM_REG(power_on_init_state, power_down_init_state)
+ * CS_SRAM_CTRL_XXX_DPM_REG(power_on_init_state, power_down_init_state)
+ * CS_SRAM_CTRL_RXTDB_REG(group_name, err_signal, sw_or_hw_control, power_on_init_state, power_down_init_state) 
+ * CS_SRAM_CTRL_RXDMP_REG(group_name, err_signal, sw_or_hw_control, power_on_init_state, power_down_init_state) 
+ * group_name : add postfix _T to group name to avoid build error
+ *
+ */
+CS_SRAM_CTRL_ICC_CSIF_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+CS_SRAM_CTRL_IMC_CSIF_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+CS_SRAM_CTRL_MPC_CSIF_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+
+CS_SRAM_CTRL_ICC_PMICM_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+CS_SRAM_CTRL_IMC_PMICM_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+CS_SRAM_CTRL_MPC_PMICM_REG(SRAM_PWR_ON, SRAM_PWR_SLP)
+
+CS_SRAM_CTRL_IMC_DDLPM_REG(SRAM_PWR_DWN, SRAM_PWR_DWN)
+CS_SRAM_CTRL_MPC_DDLPM_REG(SRAM_PWR_DWN, SRAM_PWR_DWN)
+//RXTDB
+CS_SRAM_CTRL_RXTDB_REG(G0_RXTDB_CM_T,   rxtdb_g0_1_cm_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G1_RXTDB_CM_T,   rxtdb_g0_1_cm_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G2_RXTDB_CM_T,   rxtdb_g2_3_4_cm_sram_active,    SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G3_RXTDB_CM_T,   rxtdb_g2_3_4_cm_sram_active,    SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G4_RXTDB_CM_T,   rxtdb_g2_3_4_cm_sram_active,    SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G5_RXTDB_CM_T,   rxtdb_g5_cm_sram_active,        SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G6_RXTDB_CM_T,   rxtdb_g6_7_cm_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G7_RXTDB_CM_T,   rxtdb_g6_7_cm_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G8_RXTDB_CM_T,   rxtdb_g8_9_10_cm_sram_active,   SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G9_RXTDB_CM_T,   rxtdb_g8_9_10_cm_sram_active,   SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G10_RXTDB_CM_T,  rxtdb_g8_9_10_cm_sram_active,   SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G0_RXTDB_TEST_T, rxtdb_g0_test_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G0_RXTDB_RX_T,   rxtdb_g0_1_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G1_RXTDB_RX_T,   rxtdb_g0_1_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G2_RXTDB_RX_T,   rxtdb_g2_3_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G3_RXTDB_RX_T,   rxtdb_g2_3_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G9_RXTDB_RX_T,   rxtdb_g9_rx_sram_active,        SRAM_SW_CTRL, SRAM_PWR_ON,    SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G4_RXTDB_RX_T,   rxtdb_g4_5_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G5_RXTDB_RX_T,   rxtdb_g4_5_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G6_RXTDB_RX_T,   rxtdb_g6_7_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G7_RXTDB_RX_T,   rxtdb_g6_7_rx_sram_active,      SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+CS_SRAM_CTRL_RXTDB_REG(G8_RXTDB_RX_T,   rxtdb_g8_rx_sram_active,        SRAM_SW_CTRL, SRAM_PWR_DWN,   SRAM_PWR_DWN)
+//RXDMP
+CS_SRAM_CTRL_RXDMP_REG(G0_RXDMP_EXT,    rxdmp_ext_sram_active,          SRAM_SW_CTRL, SRAM_PWR_DWN,    SRAM_PWR_DWN)
+
diff --git a/mcu/interface/driver/devdrv/csif/csif_l1core_public_api.h b/mcu/interface/driver/devdrv/csif/csif_l1core_public_api.h
new file mode 100644
index 0000000..840301a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/csif_l1core_public_api.h
@@ -0,0 +1,188 @@
+#ifndef __CSIF_L1CORE_PUBLIC_API_H__
+#define __CSIF_L1CORE_PUBLIC_API_H__
+
+/*******************************************************************************
+ *  Headers
+ *******************************************************************************/
+#include "kal_general_types.h"
+#if defined(__MAUI_BASIC__)
+#if defined(__MD97__)
+    #include "mt6297/csif_basic_def.h"
+#elif defined(__MD98__)
+    #include "mt6297p/csif_basic_def.h"
+#else
+    #error "Unsupport generation type"
+#endif
+#else
+    #include "csif_common_def.h"
+#endif
+
+/*******************************************************************************
+ * Typedefs
+ *******************************************************************************/
+/*
+emum CSIF_C2S_N0_ENUM_T defined in
+"common/interface/driver/sys_drv/csif/csif_c2s_isr_config_n0.h"
+
+emum CSIF_C2S_N1_ENUM_T defined in
+"common/interface/driver/sys_drv/csif/csif_c2s_isr_config_n1.h"
+
+emum CSIF_S2C_N0_ENUM_T defined in
+"common/interface/driver/sys_drv/csif/csif_s2c_isr_config_n0.h"
+
+emum CSIF_S2C_N1_ENUM_T defined in
+"common/interface/driver/sys_drv/csif/csif_s2c_isr_config_n1.h"
+
+*/
+
+typedef kal_char                csif_char;
+typedef kal_uint8               csif_uint8;
+typedef kal_int8                csif_int8;
+typedef kal_uint16              csif_uint16;
+typedef kal_int16               csif_int16;
+typedef kal_uint32              csif_uint32;
+typedef kal_int32               csif_int32;
+typedef kal_uint64              csif_uint64;
+typedef kal_int64               csif_int64;
+typedef kal_bool                csif_bool;
+
+/* Define status register type */
+typedef struct {
+    csif_uint32 id;
+    csif_uint32 code;
+    csif_uint32 masked_status;
+    csif_uint32 *reg_addr;
+} CSIF_ID_STATUS_t;
+
+typedef struct {
+    csif_uint32 r_idx;
+    csif_uint32 w_idx;
+    csif_uint32 mail_num;
+} CSIF_MAILBOX_STATUS_t;
+
+typedef struct {
+    csif_uint32 addr;
+    csif_uint32 size;
+} CSIF_OLPDET_CONFIG_t;
+
+typedef struct {
+    CSIF_MAILBOX_C2S_INDEX mID;
+    csif_uint32 mail;
+} CSIF_MAIL_INFO_t;
+
+typedef struct {
+    CSIF_C2S_INDEX nID;
+    csif_uint32 code;
+} CSIF_IRQ_INFO_t;
+
+/* User callback should be registered in common/interface/driver/sys_drv/csif/ */
+
+typedef enum {
+    CSIF_DSP_MPU0,
+    CSIF_DSP_MPU1,
+    CSIF_L1_MPU0,
+    CSIF_L1_MPU1,
+    CSIF_MPU_TOTAL_NUM
+} CSIF_MPU_ENUM_T;
+
+typedef enum {
+    CSIF_MPU_READ,
+    CSIF_MPU_WRITE,
+    CSIF_MPU_TOTAL_TYPE
+} CSIF_MPU_TYPE_ENUM_T;
+
+typedef enum {
+    CSIF_SET_CONTENT_ERROR,
+    CSIF_CLR_CONTENT_ERROR,
+    CSIF_OLP_HIT_ERROR,
+#if defined(MT6885) || defined(MT6873) || defined(MT6853)|| defined(CHIP10992) || defined(MT6833) || defined(MT6877) || defined(MT6298)
+    CSIF_CLR_NOHIT_ERROR,    // CLR_NOHIT_ERROR only available from Petrus
+#elif defined(MT6297)
+#else
+    #error "Unsupport project, need to do platform option porting!!"
+#endif
+    CSIF_OLPDET_ERROR_TOTAL_NUM
+} CSIF_OLPDET_ERROR_TYPE_ENUM_T;
+
+typedef enum {
+    CSIF_FULL_ERROR,
+    CSIF_CONTENT_ERROR,
+    CSIF_MAILBOX_ERROR_TOTAL_NUM
+} CSIF_MAILBOX_ERROR_TYPE_ENUM_T;
+
+/* Define user callback function type */
+typedef void (*CSIF_InterruptEntryFun)(CSIF_ID_STATUS_t*);
+
+/*******************************************************************************
+ * User-Aware MCU part API
+ *******************************************************************************/
+
+extern void csif_init(void);
+
+extern void CSIF_S2C_N0_Handler(kal_uint32 irq_id);
+extern void CSIF_S2C_N1_Handler(kal_uint32 irq_id);
+extern void CSIF_S2C_N2_Handler(kal_uint32 irq_id);
+extern void CSIF_S2C_N3_Handler(kal_uint32 irq_id);
+extern void CSIF_S2C_N4_Handler(kal_uint32 irq_id);
+extern void CSIF_S2C_N5_Handler(kal_uint32 irq_id);
+extern void CSIF_L1_ERR_Handler(kal_uint32 irq_id);
+
+extern void CSIF_C2S_SWI_Set(CSIF_C2S_INDEX nID, csif_uint32 code);
+extern csif_uint32 CSIF_C2S_SWI_Read(CSIF_C2S_INDEX nID);
+extern csif_uint32 CSIF_C2S_SWI_MASKED_Read(CSIF_C2S_INDEX nID);
+
+extern csif_uint32 CSIF_S2C_SWI_Read(CSIF_S2C_INDEX nID);
+extern csif_uint32 CSIF_S2C_SWI_MASKED_Read(CSIF_S2C_INDEX nID);
+extern csif_uint32 CSIF_S2C_SWI_Enable_Read(CSIF_S2C_INDEX nID);
+extern void CSIF_S2C_SWI_Enable(CSIF_S2C_INDEX nID, csif_uint32 code);
+extern void CSIF_S2C_SWI_Disable(CSIF_S2C_INDEX nID, csif_uint32 code);
+//#define CSIF_S2C_SWI_Enable(nID, code);
+//#define CSIF_S2C_SWI_Disable(nID, code);
+
+extern csif_uint32 CSIF_S2C_Overflow_Read(CSIF_S2C_INDEX nID);
+extern void CSIF_S2C_Overflow_Clear(CSIF_S2C_INDEX nID, csif_uint32 code);
+extern csif_uint32 CSIF_C2S_Overflow_Read(CSIF_C2S_INDEX nID);
+extern void CSIF_C2S_Overflow_Clear(CSIF_C2S_INDEX nID, csif_uint32 code);
+
+extern void CSIF_MPU_Set(CSIF_MPU_ENUM_T mpuID, csif_uint32 start, csif_uint32 range, CSIF_MPU_TYPE_ENUM_T type);
+//#define CSIF_MPU_Set(mpuID, start, range, type);
+
+extern csif_uint32 CSIF_CORE_IDLE_Read(void);
+
+extern csif_uint32 CSIF_IDLE_ENABLE_Read(CSIF_S2C_INDEX nID);
+extern void CSIF_IDLE_ENABLE_Set(CSIF_S2C_INDEX nID, csif_uint32 enable_map);
+extern void CSIF_IDLE_ENABLE_Clr(CSIF_S2C_INDEX nID, csif_uint32 clr_bit_map);
+
+extern void CSIF_MAILBOX_C2S_Send(CSIF_MAILBOX_C2S_INDEX mID, csif_uint32 mail);
+extern CSIF_MAILBOX_STATUS_t CSIF_MAILBOX_C2S_Status_Read(CSIF_MAILBOX_C2S_INDEX mID);
+extern csif_uint32 CSIF_MAILBOX_C2S_Max_FIFO_Usage_Read(CSIF_MAILBOX_C2S_INDEX mID);
+extern csif_uint32 CSIF_MAILBOX_S2C_Read(CSIF_MAILBOX_S2C_INDEX mID);
+extern CSIF_MAILBOX_STATUS_t CSIF_MAILBOX_S2C_Status_Read(CSIF_MAILBOX_S2C_INDEX mID);
+extern csif_uint32 CSIF_MAILBOX_S2C_Max_FIFO_Usage_Read(CSIF_MAILBOX_S2C_INDEX mID);
+
+// for L1 MCU LPWR scenario debug feature, not normal case usage
+extern csif_uint32 CSIF_MAILBOX_C2S_Read(CSIF_MAILBOX_C2S_INDEX mID);
+
+extern void CSIF_OLPDET_Set(csif_uint32 addr, csif_uint32 size);
+extern void CSIF_OLPDET_Clr(csif_uint32 addr, csif_uint32 size);
+extern csif_uint32 CSIF_Total_Inuse_Mem_Size(void);
+
+#if defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877) || defined(MT6298)
+extern csif_uint32 CSIF_Total_Max_Mem_Size(void);
+extern void CSIF_Total_Max_Mem_Size_Clear(void);
+#elif defined(MT6297)
+#else
+    #error "Unsupport project, need to do platform option porting!!"
+#endif
+
+// Multiple operation API
+extern void CSIF_OLPDET_Multiple_Set(csif_uint32 length, CSIF_OLPDET_CONFIG_t* olpdet_config_array);
+extern void CSIF_OLPDET_Multiple_Clr(csif_uint32 length, CSIF_OLPDET_CONFIG_t* olpdet_config_array);
+
+extern void CSIF_MAILBOX_C2S_Multiple_Send(csif_uint32 length, CSIF_MAIL_INFO_t* mail_info_array);
+
+extern void CSIF_MAILBOX_C2S_Multiple_Send_C2S_SWI_Multiple_Set(csif_uint32 mailbox_length, CSIF_MAIL_INFO_t* mail_info_array, \
+                                                                csif_uint32 irq_length,     CSIF_IRQ_INFO_t* irq_info_array);
+
+
+#endif /*__CSIF_L1CORE_PUBLIC_API_H__*/
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_c2s_isr_config_n0.h b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_c2s_isr_config_n0.h
new file mode 100644
index 0000000..382cf9e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_c2s_isr_config_n0.h
@@ -0,0 +1,104 @@
+// C2S_IRQ_N0
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code     irq_ovfl_allowed
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID31,    CSIF_TRUE,    31)
+#elif defined(__CSIF_PROFILING__)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID0,     CSIF_TRUE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID1,     CSIF_TRUE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID2,     CSIF_TRUE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID3,     CSIF_TRUE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID4,     CSIF_TRUE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID5,     CSIF_TRUE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID6,     CSIF_TRUE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID7,     CSIF_TRUE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID8,     CSIF_TRUE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID9,     CSIF_TRUE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID10,    CSIF_TRUE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID11,    CSIF_TRUE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID12,    CSIF_TRUE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID13,    CSIF_TRUE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID14,    CSIF_TRUE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID15,    CSIF_TRUE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID31,    CSIF_TRUE,    31)
+#else
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID16,    CSIF_FALSE,    16)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID17,    CSIF_FALSE,    17)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID18,    CSIF_FALSE,    18)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID19,    CSIF_FALSE,    19)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID20,    CSIF_FALSE,    20)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID21,    CSIF_FALSE,    21)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID22,    CSIF_FALSE,    22)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID23,    CSIF_FALSE,    23)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID24,    CSIF_FALSE,    24)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID25,    CSIF_FALSE,    25)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID26,    CSIF_FALSE,    26)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID27,    CSIF_FALSE,    27)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID28,    CSIF_FALSE,    28)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID29,    CSIF_FALSE,    29)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID30,    CSIF_FALSE,    30)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID31,    CSIF_FALSE,    31)
+#endif
+
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_c2s_isr_config_n1.h b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_c2s_isr_config_n1.h
new file mode 100644
index 0000000..eaf4812
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_c2s_isr_config_n1.h
@@ -0,0 +1,105 @@
+// C2S_IRQ_N1
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code     irq_ovfl_allowed
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID31,    CSIF_TRUE,    31)
+#elif defined(__CSIF_PROFILING__)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID0,     CSIF_TRUE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID1,     CSIF_TRUE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID2,     CSIF_TRUE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID3,     CSIF_TRUE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID4,     CSIF_TRUE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID5,     CSIF_TRUE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID6,     CSIF_TRUE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID7,     CSIF_TRUE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID8,     CSIF_TRUE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID9,     CSIF_TRUE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID10,    CSIF_TRUE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID11,    CSIF_TRUE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID12,    CSIF_TRUE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID13,    CSIF_TRUE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID14,    CSIF_TRUE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID15,    CSIF_TRUE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID31,    CSIF_TRUE,    31)
+#else
+                //CSIF handler         code     irq_ovfl_allowed
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID16,    CSIF_FALSE,    16)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID17,    CSIF_FALSE,    17)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID18,    CSIF_FALSE,    18)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID19,    CSIF_FALSE,    19)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID20,    CSIF_FALSE,    20)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID21,    CSIF_FALSE,    21)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID22,    CSIF_FALSE,    22)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID23,    CSIF_FALSE,    23)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID24,    CSIF_FALSE,    24)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID25,    CSIF_FALSE,    25)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID26,    CSIF_FALSE,    26)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID27,    CSIF_FALSE,    27)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID28,    CSIF_FALSE,    28)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID29,    CSIF_FALSE,    29)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID30,    CSIF_FALSE,    30)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID31,    CSIF_FALSE,    31)
+#endif
+
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_c2s_isr_config_n2.h b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_c2s_isr_config_n2.h
new file mode 100644
index 0000000..8c39e96
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_c2s_isr_config_n2.h
@@ -0,0 +1,105 @@
+// C2S_IRQ_N2
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code     irq_ovfl_allowed
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID31,    CSIF_TRUE,    31)
+#elif defined(__CSIF_PROFILING__)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID0,     CSIF_TRUE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID1,     CSIF_TRUE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID2,     CSIF_TRUE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID3,     CSIF_TRUE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID4,     CSIF_TRUE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID5,     CSIF_TRUE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID6,     CSIF_TRUE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID7,     CSIF_TRUE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID8,     CSIF_TRUE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID9,     CSIF_TRUE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID10,    CSIF_TRUE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID11,    CSIF_TRUE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID12,    CSIF_TRUE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID13,    CSIF_TRUE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID14,    CSIF_TRUE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID15,    CSIF_TRUE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID31,    CSIF_TRUE,    31)
+#else
+                //CSIF handler         code     irq_ovfl_allowed
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID16,    CSIF_FALSE,    16)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID17,    CSIF_FALSE,    17)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID18,    CSIF_FALSE,    18)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID19,    CSIF_FALSE,    19)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID20,    CSIF_FALSE,    20)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID21,    CSIF_FALSE,    21)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID22,    CSIF_FALSE,    22)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID23,    CSIF_FALSE,    23)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID24,    CSIF_FALSE,    24)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID25,    CSIF_FALSE,    25)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID26,    CSIF_FALSE,    26)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID27,    CSIF_FALSE,    27)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID28,    CSIF_FALSE,    28)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID29,    CSIF_FALSE,    29)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID30,    CSIF_FALSE,    30)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID31,    CSIF_FALSE,    31)
+#endif
+
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_c2s_isr_config_n3.h b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_c2s_isr_config_n3.h
new file mode 100644
index 0000000..c1a68a9
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_c2s_isr_config_n3.h
@@ -0,0 +1,105 @@
+// C2S_IRQ_N3
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code     irq_ovfl_allowed
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID31,    CSIF_TRUE,    31)
+#elif defined(__CSIF_PROFILING__)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID0,     CSIF_TRUE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID1,     CSIF_TRUE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID2,     CSIF_TRUE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID3,     CSIF_TRUE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID4,     CSIF_TRUE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID5,     CSIF_TRUE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID6,     CSIF_TRUE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID7,     CSIF_TRUE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID8,     CSIF_TRUE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID9,     CSIF_TRUE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID10,    CSIF_TRUE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID11,    CSIF_TRUE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID12,    CSIF_TRUE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID13,    CSIF_TRUE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID14,    CSIF_TRUE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID15,    CSIF_TRUE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID31,    CSIF_TRUE,    31)
+#else
+                //CSIF handler         code     irq_ovfl_allowed
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID16,    CSIF_FALSE,    16)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID17,    CSIF_FALSE,    17)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID18,    CSIF_FALSE,    18)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID19,    CSIF_FALSE,    19)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID20,    CSIF_FALSE,    20)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID21,    CSIF_FALSE,    21)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID22,    CSIF_FALSE,    22)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID23,    CSIF_FALSE,    23)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID24,    CSIF_FALSE,    24)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID25,    CSIF_FALSE,    25)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID26,    CSIF_FALSE,    26)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID27,    CSIF_FALSE,    27)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID28,    CSIF_FALSE,    28)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID29,    CSIF_FALSE,    29)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID30,    CSIF_FALSE,    30)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID31,    CSIF_FALSE,    31)
+#endif
+
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_l1_err_isr_config.h b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_l1_err_isr_config.h
new file mode 100644
index 0000000..e9feeef
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_l1_err_isr_config.h
@@ -0,0 +1,59 @@
+#if defined(__CSIF_DRV_TEST__)
+                    //CSIF err handler      code    
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    S2C_IRQ0_OVFL,       0)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    S2C_IRQ1_OVFL,       1)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    S2C_IRQ2_OVFL,       2)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    S2C_IRQ3_OVFL,       3)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    S2C_IRQ4_OVFL,       4)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    S2C_IRQ5_OVFL,       5)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    C2S_IRQ0_OVFL,       6)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    C2S_IRQ1_OVFL,       7)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    C2S_IRQ2_OVFL,       8)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    C2S_IRQ3_OVFL,       9)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_MPU0_ERR,         10)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_MPU1_ERR,         11)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_DSM_W_UNDEF,      12)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_DSM_R_UNDEF,      13)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_DSR_W_UNDEF,      14)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_DSR_R_UNDEF,      15)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    DSP_MPU0_CFG_ERR,     16)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    DSP_MPU1_CFG_ERR,     17)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_MPU0_CFG_ERR,     18)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_MPU1_CFG_ERR,     19)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    MAILBOX0_ERR,        20)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    MAILBOX1_ERR,        21)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    MAILBOX2_ERR,        22)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    MAILBOX3_ERR,        23)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    MAILBOX4_ERR,        24)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    MAILBOX5_ERR,        25)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_olpdet_err    ,    OLPDET_ERR,          26)
+#else
+                    //CSIF err handler      code    
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    S2C_IRQ0_OVFL,       0)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    S2C_IRQ1_OVFL,       1)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    S2C_IRQ2_OVFL,       2)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    S2C_IRQ3_OVFL,       3)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    S2C_IRQ4_OVFL,       4)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    S2C_IRQ5_OVFL,       5)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    C2S_IRQ0_OVFL,       6)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    C2S_IRQ1_OVFL,       7)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    C2S_IRQ2_OVFL,       8)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    C2S_IRQ3_OVFL,       9)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_MPU0_ERR,         10)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_MPU1_ERR,         11)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_DSM_W_UNDEF,      12)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_DSM_R_UNDEF,      13)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_DSR_W_UNDEF,      14)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_DSR_R_UNDEF,      15)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    DSP_MPU0_CFG_ERR,     16)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    DSP_MPU1_CFG_ERR,     17)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_MPU0_CFG_ERR,     18)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_MPU1_CFG_ERR,     19)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    MAILBOX0_ERR,        20)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    MAILBOX1_ERR,        21)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    MAILBOX2_ERR,        22)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    MAILBOX3_ERR,        23)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    MAILBOX4_ERR,        24)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    MAILBOX5_ERR,        25)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    OLPDET_ERR,          26)
+#endif
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_mailbox_config.h b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_mailbox_config.h
new file mode 100644
index 0000000..1b96549
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_mailbox_config.h
@@ -0,0 +1,29 @@
+#if defined(__CSIF_DRV_TEST__) || defined(__SSDVT_FRAMEWORK__)
+//********************Mailbox HW definition ***********************//
+//************* User MUST NOT modify this table *******************//
+//                    size(entries)      HW_ID
+M_CSIF_MAILBOX_HW_INFO(256,             HW_ID0)
+M_CSIF_MAILBOX_HW_INFO(64,              HW_ID1)
+M_CSIF_MAILBOX_HW_INFO(64,              HW_ID2)
+M_CSIF_MAILBOX_HW_INFO(64,              HW_ID3)
+M_CSIF_MAILBOX_HW_INFO(64,              HW_ID4)
+M_CSIF_MAILBOX_HW_INFO(64,              HW_ID5)
+//************* User MUST NOT modify this table *******************//
+//*****************************************************************//
+
+
+//************* User register mailbox on this table ***************//
+//************* Shoalin -> Mcore mailbox 
+//                       code       HW_ID (map to HW Info above)    
+M_CSIF_MAILBOX_C2S_INFO(SS_TEST_ID0,   HW_ID0)
+M_CSIF_MAILBOX_C2S_INFO(SS_TEST_ID1,   HW_ID1)
+M_CSIF_MAILBOX_C2S_INFO(SS_TEST_ID2,   HW_ID2)
+// enum will be CSIF_MAILBOX_C2S_$code
+//************* Mcore -> Shaolin mailbox 
+//                       code       HW_ID (map to HW Info above)
+M_CSIF_MAILBOX_S2C_INFO(SS_TEST_ID3,   HW_ID3)
+M_CSIF_MAILBOX_S2C_INFO(SS_TEST_ID4,   HW_ID4)
+M_CSIF_MAILBOX_S2C_INFO(SS_TEST_ID5,   HW_ID5)
+// enum will be CSIF_MAILBOX_S2C_$code
+//***********User register mailbox on this table*******************//
+#endif
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n0.h b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n0.h
new file mode 100644
index 0000000..b81c2f3
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n0.h
@@ -0,0 +1,106 @@
+// S2C_IRQ_N0
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID16,    CSIF_TRUE,    16)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID17,    CSIF_TRUE,    17)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID18,    CSIF_TRUE,    18)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID19,    CSIF_TRUE,    19)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID20,    CSIF_TRUE,    20)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID21,    CSIF_TRUE,    21)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID22,    CSIF_TRUE,    22)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID23,    CSIF_TRUE,    23)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID24,    CSIF_TRUE,    24)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID25,    CSIF_TRUE,    25)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID26,    CSIF_TRUE,    26)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID27,    CSIF_TRUE,    27)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID28,    CSIF_TRUE,    28)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID29,    CSIF_TRUE,    29)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID30,    CSIF_TRUE,    30)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID31,    CSIF_TRUE,    31)
+#elif defined(__CSIF_CROSS_CORE_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID31,    CSIF_FALSE,    31)
+#else
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  sonic_deactivate_cb_n0    ,    N0_ID0,     CSIF_TRUE,    0)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID31,    CSIF_FALSE,    31)
+#endif
+
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n1.h b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n1.h
new file mode 100644
index 0000000..25efc5f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n1.h
@@ -0,0 +1,105 @@
+// S2C_IRQ_N1
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID0,     CSIF_FALSE,   0)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID1,     CSIF_FALSE,   1)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID2,     CSIF_FALSE,   2)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID3,     CSIF_FALSE,   3)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID4,     CSIF_FALSE,   4)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID5,     CSIF_FALSE,   5)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID6,     CSIF_FALSE,   6)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID7,     CSIF_FALSE,   7)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID8,     CSIF_FALSE,   8)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID9,     CSIF_FALSE,   9)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID10,    CSIF_FALSE,   10)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID11,    CSIF_FALSE,   11)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID12,    CSIF_FALSE,   12)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID13,    CSIF_FALSE,   13)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID14,    CSIF_FALSE,   14)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID15,    CSIF_FALSE,   15)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID16,    CSIF_TRUE,    16)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID17,    CSIF_TRUE,    17)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID18,    CSIF_TRUE,    18)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID19,    CSIF_TRUE,    19)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID20,    CSIF_TRUE,    20)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID21,    CSIF_TRUE,    21)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID22,    CSIF_TRUE,    22)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID23,    CSIF_TRUE,    23)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID24,    CSIF_TRUE,    24)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID25,    CSIF_TRUE,    25)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID26,    CSIF_TRUE,    26)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID27,    CSIF_TRUE,    27)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID28,    CSIF_TRUE,    28)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID29,    CSIF_TRUE,    29)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID30,    CSIF_TRUE,    30)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID31,    CSIF_TRUE,    31)
+#elif defined(__CSIF_CROSS_CORE_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID31,    CSIF_FALSE,    31)
+#else
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID31,    CSIF_FALSE,    31)
+#endif
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n2.h b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n2.h
new file mode 100644
index 0000000..e540e98
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n2.h
@@ -0,0 +1,105 @@
+// S2C_IRQ_n2
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID0,     CSIF_FALSE,  0)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID1,     CSIF_FALSE,  1)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID2,     CSIF_FALSE,  2)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID3,     CSIF_FALSE,  3)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID4,     CSIF_FALSE,  4)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID5,     CSIF_FALSE,  5)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID6,     CSIF_FALSE,  6)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID7,     CSIF_FALSE,  7)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID8,     CSIF_FALSE,  8)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID9,     CSIF_FALSE,  9)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID10,    CSIF_FALSE,  10)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID11,    CSIF_FALSE,  11)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID12,    CSIF_FALSE,  12)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID13,    CSIF_FALSE,  13)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID14,    CSIF_FALSE,  14)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID15,    CSIF_FALSE,  15)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID16,    CSIF_TRUE,   16)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID17,    CSIF_TRUE,   17)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID18,    CSIF_TRUE,   18)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID19,    CSIF_TRUE,   19)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID20,    CSIF_TRUE,   20)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID21,    CSIF_TRUE,   21)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID22,    CSIF_TRUE,   22)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID23,    CSIF_TRUE,   23)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID24,    CSIF_TRUE,   24)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID25,    CSIF_TRUE,   25)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID26,    CSIF_TRUE,   26)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID27,    CSIF_TRUE,   27)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID28,    CSIF_TRUE,   28)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID29,    CSIF_TRUE,   29)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID30,    CSIF_TRUE,   30)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID31,    CSIF_TRUE,   31)
+#elif defined(__CSIF_CROSS_CORE_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID31,    CSIF_FALSE,    31)
+#else
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID31,    CSIF_FALSE,    31)
+#endif
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n3.h b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n3.h
new file mode 100644
index 0000000..94d4649
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n3.h
@@ -0,0 +1,105 @@
+// S2C_IRQ_n3
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID0,     CSIF_FALSE,  0)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID1,     CSIF_FALSE,  1)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID2,     CSIF_FALSE,  2)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID3,     CSIF_FALSE,  3)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID4,     CSIF_FALSE,  4)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID5,     CSIF_FALSE,  5)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID6,     CSIF_FALSE,  6)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID7,     CSIF_FALSE,  7)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID8,     CSIF_FALSE,  8)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID9,     CSIF_FALSE,  9)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID10,    CSIF_FALSE,  10)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID11,    CSIF_FALSE,  11)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID12,    CSIF_FALSE,  12)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID13,    CSIF_FALSE,  13)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID14,    CSIF_FALSE,  14)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID15,    CSIF_FALSE,  15)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID16,    CSIF_TRUE,   16)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID17,    CSIF_TRUE,   17)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID18,    CSIF_TRUE,   18)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID19,    CSIF_TRUE,   19)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID20,    CSIF_TRUE,   20)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID21,    CSIF_TRUE,   21)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID22,    CSIF_TRUE,   22)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID23,    CSIF_TRUE,   23)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID24,    CSIF_TRUE,   24)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID25,    CSIF_TRUE,   25)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID26,    CSIF_TRUE,   26)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID27,    CSIF_TRUE,   27)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID28,    CSIF_TRUE,   28)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID29,    CSIF_TRUE,   29)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID30,    CSIF_TRUE,   30)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID31,    CSIF_TRUE,   31)
+#elif defined(__CSIF_CROSS_CORE_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID31,    CSIF_FALSE,    31)
+#else
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID31,    CSIF_FALSE,    31)
+#endif
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n4.h b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n4.h
new file mode 100644
index 0000000..e9ef22b
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n4.h
@@ -0,0 +1,105 @@
+// S2C_IRQ_n4
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID0,     CSIF_FALSE,  0)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID1,     CSIF_FALSE,  1)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID2,     CSIF_FALSE,  2)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID3,     CSIF_FALSE,  3)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID4,     CSIF_FALSE,  4)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID5,     CSIF_FALSE,  5)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID6,     CSIF_FALSE,  6)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID7,     CSIF_FALSE,  7)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID8,     CSIF_FALSE,  8)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID9,     CSIF_FALSE,  9)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID10,    CSIF_FALSE,  10)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID11,    CSIF_FALSE,  11)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID12,    CSIF_FALSE,  12)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID13,    CSIF_FALSE,  13)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID14,    CSIF_FALSE,  14)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID15,    CSIF_FALSE,  15)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID16,    CSIF_TRUE,   16)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID17,    CSIF_TRUE,   17)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID18,    CSIF_TRUE,   18)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID19,    CSIF_TRUE,   19)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID20,    CSIF_TRUE,   20)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID21,    CSIF_TRUE,   21)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID22,    CSIF_TRUE,   22)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID23,    CSIF_TRUE,   23)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID24,    CSIF_TRUE,   24)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID25,    CSIF_TRUE,   25)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID26,    CSIF_TRUE,   26)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID27,    CSIF_TRUE,   27)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID28,    CSIF_TRUE,   28)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID29,    CSIF_TRUE,   29)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID30,    CSIF_TRUE,   30)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID31,    CSIF_TRUE,   31)
+#elif defined(__CSIF_CROSS_CORE_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID31,    CSIF_FALSE,    31)
+#else
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID31,    CSIF_FALSE,    31)
+#endif
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n5.h b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n5.h
new file mode 100644
index 0000000..0c91594
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/basic/csif_s2c_isr_config_n5.h
@@ -0,0 +1,106 @@
+// S2C_IRQ_N5
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID0,     CSIF_FALSE,  0)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID1,     CSIF_FALSE,  1)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID2,     CSIF_FALSE,  2)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID3,     CSIF_FALSE,  3)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID4,     CSIF_FALSE,  4)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID5,     CSIF_FALSE,  5)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID6,     CSIF_FALSE,  6)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID7,     CSIF_FALSE,  7)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID8,     CSIF_FALSE,  8)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID9,     CSIF_FALSE,  9)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID10,    CSIF_FALSE,  10)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID11,    CSIF_FALSE,  11)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID12,    CSIF_FALSE,  12)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID13,    CSIF_FALSE,  13)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID14,    CSIF_FALSE,  14)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID15,    CSIF_FALSE,  15)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID16,    CSIF_TRUE,   16)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID17,    CSIF_TRUE,   17)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID18,    CSIF_TRUE,   18)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID19,    CSIF_TRUE,   19)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID20,    CSIF_TRUE,   20)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID21,    CSIF_TRUE,   21)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID22,    CSIF_TRUE,   22)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID23,    CSIF_TRUE,   23)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID24,    CSIF_TRUE,   24)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID25,    CSIF_TRUE,   25)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID26,    CSIF_TRUE,   26)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID27,    CSIF_TRUE,   27)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID28,    CSIF_TRUE,   28)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID29,    CSIF_TRUE,   29)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID30,    CSIF_TRUE,   30)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID31,    CSIF_TRUE,   31)
+#elif defined(__CSIF_CROSS_CORE_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID31,    CSIF_FALSE,    31)
+#else
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID31,    CSIF_FALSE,    31)
+
+#endif
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/csif_basic_def.h b/mcu/interface/driver/devdrv/csif/mt6297/csif_basic_def.h
new file mode 100644
index 0000000..b5fc555
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/csif_basic_def.h
@@ -0,0 +1,255 @@
+/*******************************************
+*   please DO NOT include this file
+*   this file is for mcu/dsp csif driver include only 
+************************************************/
+
+/*******************************************************************************
+  * IRQ Enums 
+  *******************************************************************************/
+
+/* C2S IRQ */
+
+#undef M_CSIF_C2S_INFO
+#define M_CSIF_C2S_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIF_C2S_ID_##Code=Value,
+
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N0_Enum{
+    #include "basic/csif_c2s_isr_config_n0.h"
+    CSIF_C2S_N0_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N0_ENUM_T;
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N1_Enum{
+    //CSIF_C2S_N1_START_ID = 31,
+    #include "basic/csif_c2s_isr_config_n1.h"
+    CSIF_C2S_N1_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N1_ENUM_T;
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N2_Enum{
+    //CSIF_C2S_N2_START_ID = 63,
+    #include "basic/csif_c2s_isr_config_n2.h"
+    CSIF_C2S_N2_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N2_ENUM_T;
+typedef enum CSIF_C2S_InterruptHandlerCode_N3_Enum{
+    //CSIF_C2S_N3_START_ID = 95,
+    #include "basic/csif_c2s_isr_config_n3.h"
+    CSIF_C2S_N3_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N3_ENUM_T;
+
+#undef M_CSIF_C2S_INFO
+
+/* S2C IRQ*/
+
+#undef M_CSIF_S2C_INFO
+#define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIF_S2C_ID_##Code=Value,
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N0_Enum{
+    #include "basic/csif_s2c_isr_config_n0.h"
+    CSIF_S2C_N0_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N0_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N1_Enum{
+    //CSIF_S2C_N1_START_ID = 31,
+    #include "basic/csif_s2c_isr_config_n1.h"
+    CSIF_S2C_N1_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N1_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N2_Enum{
+    //CSIF_S2C_N2_START_ID = 63,
+    #include "basic/csif_s2c_isr_config_n2.h"
+    CSIF_S2C_N2_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N2_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N3_Enum{
+    //CSIF_S2C_N3_START_ID = 95,
+    #include "basic/csif_s2c_isr_config_n3.h"
+    CSIF_S2C_N3_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N3_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N4_Enum{
+    //CSIF_S2C_N4_START_ID = 127,
+    #include "basic/csif_s2c_isr_config_n4.h"
+    CSIF_S2C_N4_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N4_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N5_Enum{
+    //CSIF_S2C_N5_START_ID = 159,
+    #include "basic/csif_s2c_isr_config_n5.h"
+    CSIF_S2C_N5_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N5_ENUM_T;
+
+#undef M_CSIF_S2C_INFO
+
+#if defined(__MSONIC__)
+/* DSP Error */
+#undef M_CSIF_DSP_ERR_INFO
+#define M_CSIF_DSP_ERR_INFO(CSIFErrHandler, Code, Value) CSIF_DSP_Err_##Code=Value,
+
+typedef enum CSIF_DSP_Err_InterruptHandlerCode_Enum{
+    #include "basic/csif_dsp_err_isr_config.h"
+    CSIF_DSP_ERR_TOTAL_NUMBER
+}CSIF_DSP_ERR_ENUM_T;
+
+#undef M_CSIF_DSP_ERR_INFO
+
+#elif defined(__CR4__) || defined(__MIPS_I7200__) || defined(__MIPS_IA__)
+/* L1 Error */
+#undef M_CSIF_L1_ERR_INFO
+#define M_CSIF_L1_ERR_INFO(CSIFErrHandler, Code, Value) CSIF_L1_Err_##Code=Value,
+
+typedef enum CSIF_L1_Err_InterruptHandlerCode_Enum{
+    #include "basic/csif_l1_err_isr_config.h"
+    CSIF_L1_ERR_TOTAL_NUMBER
+}CSIF_L1_ERR_ENUM_T;
+
+#undef M_CSIF_L1_ERR_INFO
+#else
+#error "not supported core"
+#endif
+
+
+/* CSIF C2S Int enum */
+typedef enum CSIF_C2S_Index_Enum{
+    CSIF_ENUM_C2S_N0,
+    CSIF_ENUM_C2S_N1,
+    CSIF_ENUM_C2S_N2,
+    CSIF_ENUM_C2S_N3,
+    CSIF_ENUM_ALL_C2S_INT_NUM
+}CSIF_C2S_INDEX;
+
+/* CSIF S2C Int enum */
+typedef enum CSIF_S2C_Index_Enum{
+    CSIF_ENUM_S2C_N0,
+    CSIF_ENUM_S2C_N1,
+    CSIF_ENUM_S2C_N2,
+    CSIF_ENUM_S2C_N3,
+    CSIF_ENUM_S2C_N4,
+    CSIF_ENUM_S2C_N5,
+    CSIF_ENUM_ALL_S2C_INT_NUM
+}CSIF_S2C_INDEX;
+
+
+/*******************************************************************************
+  * Mailbox Enum 
+  *******************************************************************************/
+/* MAILBOX HW INDEX */
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+#define M_CSIF_MAILBOX_HW_INFO(Size, HW_ID) CSIF_MAILBOX_##HW_ID,
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID)
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID)
+typedef enum CSIF_MAILBOX_HW_Index_Enum{
+    #include "basic/csif_mailbox_config.h"
+    CSIF_MAILBOX_HW_TOTAL_NUMBER
+}CSIF_MAILBOX_HW_INDEX;
+
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+/* MAILBOX Total num */
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+#define M_CSIF_MAILBOX_HW_INFO(Size, HW_ID)
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID) CSIF_MAILBOX_TOTAL_ID_##Code,
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID) CSIF_MAILBOX_TOTAL_ID_##Code,
+typedef enum CSIF_MAILBOX_TOTAL_Index_Enum{
+    #include "basic/csif_mailbox_config.h"
+    CSIF_MAILBOX_SW_TOTAL_NUMBER
+}CSIF_MAILBOX_TOTAL_ENUM_T;
+
+#undef M_CSIF_MAILBOX_C2S_INFO
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID) CSIF_MAILBOX_TOTAL_C2S_ID_##Code,
+#undef M_CSIF_MAILBOX_S2C_INFO
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID)
+
+typedef enum CSIF_MAILBOX_TOTAL_C2S_NUM_Enum{
+    #include "basic/csif_mailbox_config.h"
+    CSIF_MAILBOX_SW_TOTAL_C2S_NUMBER
+}CSIF_MAILBOX_TOTAL_C2S_ENUM_T;
+
+#undef M_CSIF_MAILBOX_C2S_INFO
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID)
+#undef M_CSIF_MAILBOX_S2C_INFO
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID) CSIF_MAILBOX_TOTAL_S2C_ID_##Code,
+
+typedef enum CSIF_MAILBOX_TOTAL_S2C_NUM_Enum{
+    #include "basic/csif_mailbox_config.h"
+    CSIF_MAILBOX_SW_TOTAL_S2C_NUMBER
+}CSIF_MAILBOX_TOTAL_S2C_ENUM_T;
+
+#if defined(__MSONIC__)
+KAL_CASSERT((CSIF_MAILBOX_SW_TOTAL_NUMBER <= CSIF_MAILBOX_HW_TOTAL_NUMBER));
+#endif
+
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+/* C2S MAILBOX Index*/
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+#define M_CSIF_MAILBOX_HW_INFO(Size, HW_ID)
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID) CSIF_MAILBOX_C2S_##Code=CSIF_MAILBOX_##HW_ID,
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID)
+typedef enum CSIF_MAILBOX_C2S_Index_Enum{
+    #include "basic/csif_mailbox_config.h"
+    CSIF_MAILBOX_C2S_LAST_ID
+}CSIF_MAILBOX_C2S_INDEX;
+
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+/* S2C MAILBOX Index*/
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+#define M_CSIF_MAILBOX_HW_INFO(Size, HW_ID)
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID)
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID) CSIF_MAILBOX_S2C_##Code=CSIF_MAILBOX_##HW_ID,
+typedef enum CSIF_MAILBOX_S2C_Index_Enum{
+    #include "basic/csif_mailbox_config.h"
+    CSIF_MAILBOX_S2C_LAST_ID
+}CSIF_MAILBOX_S2C_INDEX;
+
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+
+
+/*******************************************************************************
+  * Macros 
+  *******************************************************************************/
+
+#define CSIF_C2S_N0_TOTAL_NUMBER               (CSIF_C2S_N0_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N1_TOTAL_NUMBER               (CSIF_C2S_N1_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N2_TOTAL_NUMBER               (CSIF_C2S_N2_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N3_TOTAL_NUMBER               (CSIF_C2S_N3_TOTAL_NUMBER_ENUM)
+//#define CSIF_C2S_N1_TOTAL_NUMBER               (CSIF_C2S_N1_TOTAL_NUMBER_ENUM - CSIF_C2S_N1_START_ID - 1)
+//#define CSIF_C2S_N2_TOTAL_NUMBER               (CSIF_C2S_N2_TOTAL_NUMBER_ENUM - CSIF_C2S_N2_START_ID - 1)
+//#define CSIF_C2S_N3_TOTAL_NUMBER               (CSIF_C2S_N3_TOTAL_NUMBER_ENUM - CSIF_C2S_N3_START_ID - 1)
+
+
+#define CSIF_S2C_N0_TOTAL_NUMBER               (CSIF_S2C_N0_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N1_TOTAL_NUMBER               (CSIF_S2C_N1_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N2_TOTAL_NUMBER               (CSIF_S2C_N2_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N3_TOTAL_NUMBER               (CSIF_S2C_N3_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N4_TOTAL_NUMBER               (CSIF_S2C_N4_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N5_TOTAL_NUMBER               (CSIF_S2C_N5_TOTAL_NUMBER_ENUM)
+//#define CSIF_S2C_N1_TOTAL_NUMBER               (CSIF_S2C_N1_TOTAL_NUMBER_ENUM - CSIF_S2C_N1_START_ID - 1)
+//#define CSIF_S2C_N2_TOTAL_NUMBER               (CSIF_S2C_N2_TOTAL_NUMBER_ENUM - CSIF_S2C_N2_START_ID - 1)
+//#define CSIF_S2C_N3_TOTAL_NUMBER               (CSIF_S2C_N3_TOTAL_NUMBER_ENUM - CSIF_S2C_N3_START_ID - 1)
+//#define CSIF_S2C_N4_TOTAL_NUMBER               (CSIF_S2C_N4_TOTAL_NUMBER_ENUM - CSIF_S2C_N4_START_ID - 1)
+//#define CSIF_S2C_N5_TOTAL_NUMBER               (CSIF_S2C_N5_TOTAL_NUMBER_ENUM - CSIF_S2C_N5_START_ID - 1)
+
+#define CSIF_MAILBOX_TOTAL_NUM                  (CSIF_MAILBOX_SW_TOTAL_NUMBER)
+#define CSIF_MAILBOX_C2S_NUM                    (CSIF_MAILBOX_SW_TOTAL_C2S_NUMBER)
+#define CSIF_MAILBOX_S2C_NUM                    (CSIF_MAILBOX_SW_TOTAL_S2C_NUMBER)
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/csif_c2s_isr_config_n0_pre.h b/mcu/interface/driver/devdrv/csif/mt6297/csif_c2s_isr_config_n0_pre.h
new file mode 100644
index 0000000..76bf694
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/csif_c2s_isr_config_n0_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_c2s_isr_config_n0.h"
+#else
+    #include "mt6297/csif_c2s_isr_config_n0.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/csif_c2s_isr_config_n1_pre.h b/mcu/interface/driver/devdrv/csif/mt6297/csif_c2s_isr_config_n1_pre.h
new file mode 100644
index 0000000..f2d68f4
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/csif_c2s_isr_config_n1_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_c2s_isr_config_n1.h"
+#else
+    #include "mt6297/csif_c2s_isr_config_n1.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/csif_c2s_isr_config_n2_pre.h b/mcu/interface/driver/devdrv/csif/mt6297/csif_c2s_isr_config_n2_pre.h
new file mode 100644
index 0000000..8753511
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/csif_c2s_isr_config_n2_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_c2s_isr_config_n2.h"
+#else
+    #include "mt6297/csif_c2s_isr_config_n2.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/csif_c2s_isr_config_n3_pre.h b/mcu/interface/driver/devdrv/csif/mt6297/csif_c2s_isr_config_n3_pre.h
new file mode 100644
index 0000000..b896798
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/csif_c2s_isr_config_n3_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_c2s_isr_config_n3.h"
+#else
+    #include "mt6297/csif_c2s_isr_config_n3.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/csif_l1_err_isr_config_pre.h b/mcu/interface/driver/devdrv/csif/mt6297/csif_l1_err_isr_config_pre.h
new file mode 100644
index 0000000..acc540a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/csif_l1_err_isr_config_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_l1_err_isr_config.h"
+#else
+    #include "mt6297/csif_l1_err_isr_config.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/csif_mailbox_config_pre.h b/mcu/interface/driver/devdrv/csif/mt6297/csif_mailbox_config_pre.h
new file mode 100644
index 0000000..9bae6b5
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/csif_mailbox_config_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_mailbox_config.h"
+#else
+    #include "mt6297/csif_mailbox_config.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n0_pre.h b/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n0_pre.h
new file mode 100644
index 0000000..28d4220
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n0_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_s2c_isr_config_n0.h"
+#else
+    #include "mt6297/csif_s2c_isr_config_n0.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n1_pre.h b/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n1_pre.h
new file mode 100644
index 0000000..cc3b069
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n1_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_s2c_isr_config_n1.h"
+#else
+    #include "mt6297/csif_s2c_isr_config_n1.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n2_pre.h b/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n2_pre.h
new file mode 100644
index 0000000..e8b22f9
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n2_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_s2c_isr_config_n2.h"
+#else
+    #include "mt6297/csif_s2c_isr_config_n2.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n3_pre.h b/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n3_pre.h
new file mode 100644
index 0000000..ff34ef5
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n3_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_s2c_isr_config_n3.h"
+#else
+    #include "mt6297/csif_s2c_isr_config_n3.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n4_pre.h b/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n4_pre.h
new file mode 100644
index 0000000..3433341
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n4_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_s2c_isr_config_n4.h"
+#else
+    #include "mt6297/csif_s2c_isr_config_n4.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n5_pre.h b/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n5_pre.h
new file mode 100644
index 0000000..bc2b01a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297/csif_s2c_isr_config_n5_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_s2c_isr_config_n5.h"
+#else
+    #include "mt6297/csif_s2c_isr_config_n5.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_c2s_isr_config_n0.h b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_c2s_isr_config_n0.h
new file mode 100644
index 0000000..382cf9e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_c2s_isr_config_n0.h
@@ -0,0 +1,104 @@
+// C2S_IRQ_N0
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code     irq_ovfl_allowed
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID31,    CSIF_TRUE,    31)
+#elif defined(__CSIF_PROFILING__)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID0,     CSIF_TRUE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID1,     CSIF_TRUE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID2,     CSIF_TRUE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID3,     CSIF_TRUE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID4,     CSIF_TRUE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID5,     CSIF_TRUE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID6,     CSIF_TRUE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID7,     CSIF_TRUE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID8,     CSIF_TRUE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID9,     CSIF_TRUE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID10,    CSIF_TRUE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID11,    CSIF_TRUE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID12,    CSIF_TRUE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID13,    CSIF_TRUE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID14,    CSIF_TRUE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID15,    CSIF_TRUE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N0_ID31,    CSIF_TRUE,    31)
+#else
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID16,    CSIF_FALSE,    16)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID17,    CSIF_FALSE,    17)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID18,    CSIF_FALSE,    18)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID19,    CSIF_FALSE,    19)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID20,    CSIF_FALSE,    20)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID21,    CSIF_FALSE,    21)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID22,    CSIF_FALSE,    22)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID23,    CSIF_FALSE,    23)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID24,    CSIF_FALSE,    24)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID25,    CSIF_FALSE,    25)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID26,    CSIF_FALSE,    26)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID27,    CSIF_FALSE,    27)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID28,    CSIF_FALSE,    28)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID29,    CSIF_FALSE,    29)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID30,    CSIF_FALSE,    30)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N0_ID31,    CSIF_FALSE,    31)
+#endif
+
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_c2s_isr_config_n1.h b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_c2s_isr_config_n1.h
new file mode 100644
index 0000000..eaf4812
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_c2s_isr_config_n1.h
@@ -0,0 +1,105 @@
+// C2S_IRQ_N1
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code     irq_ovfl_allowed
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID31,    CSIF_TRUE,    31)
+#elif defined(__CSIF_PROFILING__)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID0,     CSIF_TRUE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID1,     CSIF_TRUE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID2,     CSIF_TRUE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID3,     CSIF_TRUE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID4,     CSIF_TRUE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID5,     CSIF_TRUE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID6,     CSIF_TRUE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID7,     CSIF_TRUE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID8,     CSIF_TRUE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID9,     CSIF_TRUE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID10,    CSIF_TRUE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID11,    CSIF_TRUE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID12,    CSIF_TRUE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID13,    CSIF_TRUE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID14,    CSIF_TRUE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID15,    CSIF_TRUE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N1_ID31,    CSIF_TRUE,    31)
+#else
+                //CSIF handler         code     irq_ovfl_allowed
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID16,    CSIF_FALSE,    16)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID17,    CSIF_FALSE,    17)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID18,    CSIF_FALSE,    18)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID19,    CSIF_FALSE,    19)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID20,    CSIF_FALSE,    20)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID21,    CSIF_FALSE,    21)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID22,    CSIF_FALSE,    22)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID23,    CSIF_FALSE,    23)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID24,    CSIF_FALSE,    24)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID25,    CSIF_FALSE,    25)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID26,    CSIF_FALSE,    26)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID27,    CSIF_FALSE,    27)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID28,    CSIF_FALSE,    28)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID29,    CSIF_FALSE,    29)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID30,    CSIF_FALSE,    30)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N1_ID31,    CSIF_FALSE,    31)
+#endif
+
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_c2s_isr_config_n2.h b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_c2s_isr_config_n2.h
new file mode 100644
index 0000000..8c39e96
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_c2s_isr_config_n2.h
@@ -0,0 +1,105 @@
+// C2S_IRQ_N2
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code     irq_ovfl_allowed
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID31,    CSIF_TRUE,    31)
+#elif defined(__CSIF_PROFILING__)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID0,     CSIF_TRUE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID1,     CSIF_TRUE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID2,     CSIF_TRUE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID3,     CSIF_TRUE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID4,     CSIF_TRUE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID5,     CSIF_TRUE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID6,     CSIF_TRUE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID7,     CSIF_TRUE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID8,     CSIF_TRUE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID9,     CSIF_TRUE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID10,    CSIF_TRUE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID11,    CSIF_TRUE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID12,    CSIF_TRUE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID13,    CSIF_TRUE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID14,    CSIF_TRUE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID15,    CSIF_TRUE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N2_ID31,    CSIF_TRUE,    31)
+#else
+                //CSIF handler         code     irq_ovfl_allowed
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID16,    CSIF_FALSE,    16)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID17,    CSIF_FALSE,    17)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID18,    CSIF_FALSE,    18)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID19,    CSIF_FALSE,    19)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID20,    CSIF_FALSE,    20)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID21,    CSIF_FALSE,    21)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID22,    CSIF_FALSE,    22)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID23,    CSIF_FALSE,    23)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID24,    CSIF_FALSE,    24)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID25,    CSIF_FALSE,    25)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID26,    CSIF_FALSE,    26)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID27,    CSIF_FALSE,    27)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID28,    CSIF_FALSE,    28)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID29,    CSIF_FALSE,    29)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID30,    CSIF_FALSE,    30)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N2_ID31,    CSIF_FALSE,    31)
+#endif
+
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_c2s_isr_config_n3.h b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_c2s_isr_config_n3.h
new file mode 100644
index 0000000..c1a68a9
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_c2s_isr_config_n3.h
@@ -0,0 +1,105 @@
+// C2S_IRQ_N3
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code     irq_ovfl_allowed
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID31,    CSIF_TRUE,    31)
+#elif defined(__CSIF_PROFILING__)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID0,     CSIF_TRUE,    0)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID1,     CSIF_TRUE,    1)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID2,     CSIF_TRUE,    2)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID3,     CSIF_TRUE,    3)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID4,     CSIF_TRUE,    4)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID5,     CSIF_TRUE,    5)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID6,     CSIF_TRUE,    6)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID7,     CSIF_TRUE,    7)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID8,     CSIF_TRUE,    8)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID9,     CSIF_TRUE,    9)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID10,    CSIF_TRUE,    10)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID11,    CSIF_TRUE,    11)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID12,    CSIF_TRUE,    12)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID13,    CSIF_TRUE,    13)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID14,    CSIF_TRUE,    14)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID15,    CSIF_TRUE,    15)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID16,    CSIF_TRUE,    16)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID17,    CSIF_TRUE,    17)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID18,    CSIF_TRUE,    18)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID19,    CSIF_TRUE,    19)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID20,    CSIF_TRUE,    20)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID21,    CSIF_TRUE,    21)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID22,    CSIF_TRUE,    22)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID23,    CSIF_TRUE,    23)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID24,    CSIF_TRUE,    24)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID25,    CSIF_TRUE,    25)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID26,    CSIF_TRUE,    26)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID27,    CSIF_TRUE,    27)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID28,    CSIF_TRUE,    28)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID29,    CSIF_TRUE,    29)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID30,    CSIF_TRUE,    30)
+M_CSIF_C2S_INFO(  CSIF_Test    ,    N3_ID31,    CSIF_TRUE,    31)
+#else
+                //CSIF handler         code     irq_ovfl_allowed
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID0,     CSIF_FALSE,    0)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID1,     CSIF_FALSE,    1)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID2,     CSIF_FALSE,    2)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID3,     CSIF_FALSE,    3)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID4,     CSIF_FALSE,    4)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID5,     CSIF_FALSE,    5)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID6,     CSIF_FALSE,    6)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID7,     CSIF_FALSE,    7)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID8,     CSIF_FALSE,    8)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID9,     CSIF_FALSE,    9)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID10,    CSIF_FALSE,    10)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID11,    CSIF_FALSE,    11)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID12,    CSIF_FALSE,    12)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID13,    CSIF_FALSE,    13)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID14,    CSIF_FALSE,    14)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID15,    CSIF_FALSE,    15)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID16,    CSIF_FALSE,    16)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID17,    CSIF_FALSE,    17)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID18,    CSIF_FALSE,    18)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID19,    CSIF_FALSE,    19)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID20,    CSIF_FALSE,    20)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID21,    CSIF_FALSE,    21)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID22,    CSIF_FALSE,    22)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID23,    CSIF_FALSE,    23)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID24,    CSIF_FALSE,    24)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID25,    CSIF_FALSE,    25)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID26,    CSIF_FALSE,    26)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID27,    CSIF_FALSE,    27)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID28,    CSIF_FALSE,    28)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID29,    CSIF_FALSE,    29)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID30,    CSIF_FALSE,    30)
+M_CSIF_C2S_INFO(  CSIF_Invalid    ,    N3_ID31,    CSIF_FALSE,    31)
+#endif
+
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_l1_err_isr_config.h b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_l1_err_isr_config.h
new file mode 100644
index 0000000..e9feeef
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_l1_err_isr_config.h
@@ -0,0 +1,59 @@
+#if defined(__CSIF_DRV_TEST__)
+                    //CSIF err handler      code    
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    S2C_IRQ0_OVFL,       0)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    S2C_IRQ1_OVFL,       1)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    S2C_IRQ2_OVFL,       2)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    S2C_IRQ3_OVFL,       3)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    S2C_IRQ4_OVFL,       4)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    S2C_IRQ5_OVFL,       5)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    C2S_IRQ0_OVFL,       6)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    C2S_IRQ1_OVFL,       7)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    C2S_IRQ2_OVFL,       8)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    C2S_IRQ3_OVFL,       9)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_MPU0_ERR,         10)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_MPU1_ERR,         11)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_DSM_W_UNDEF,      12)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_DSM_R_UNDEF,      13)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_DSR_W_UNDEF,      14)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_DSR_R_UNDEF,      15)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    DSP_MPU0_CFG_ERR,     16)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    DSP_MPU1_CFG_ERR,     17)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_MPU0_CFG_ERR,     18)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    L1_MPU1_CFG_ERR,     19)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    MAILBOX0_ERR,        20)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    MAILBOX1_ERR,        21)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    MAILBOX2_ERR,        22)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    MAILBOX3_ERR,        23)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    MAILBOX4_ERR,        24)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_err    ,    MAILBOX5_ERR,        25)
+M_CSIF_L1_ERR_INFO(  CSIF_drv_test_olpdet_err    ,    OLPDET_ERR,          26)
+#else
+                    //CSIF err handler      code    
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    S2C_IRQ0_OVFL,       0)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    S2C_IRQ1_OVFL,       1)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    S2C_IRQ2_OVFL,       2)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    S2C_IRQ3_OVFL,       3)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    S2C_IRQ4_OVFL,       4)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    S2C_IRQ5_OVFL,       5)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    C2S_IRQ0_OVFL,       6)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    C2S_IRQ1_OVFL,       7)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    C2S_IRQ2_OVFL,       8)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    C2S_IRQ3_OVFL,       9)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_MPU0_ERR,         10)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_MPU1_ERR,         11)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_DSM_W_UNDEF,      12)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_DSM_R_UNDEF,      13)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_DSR_W_UNDEF,      14)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_DSR_R_UNDEF,      15)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    DSP_MPU0_CFG_ERR,     16)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    DSP_MPU1_CFG_ERR,     17)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_MPU0_CFG_ERR,     18)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    L1_MPU1_CFG_ERR,     19)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    MAILBOX0_ERR,        20)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    MAILBOX1_ERR,        21)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    MAILBOX2_ERR,        22)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    MAILBOX3_ERR,        23)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    MAILBOX4_ERR,        24)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    MAILBOX5_ERR,        25)
+M_CSIF_L1_ERR_INFO(  CSIF_Invalid    ,    OLPDET_ERR,          26)
+#endif
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_mailbox_config.h b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_mailbox_config.h
new file mode 100644
index 0000000..1b96549
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_mailbox_config.h
@@ -0,0 +1,29 @@
+#if defined(__CSIF_DRV_TEST__) || defined(__SSDVT_FRAMEWORK__)
+//********************Mailbox HW definition ***********************//
+//************* User MUST NOT modify this table *******************//
+//                    size(entries)      HW_ID
+M_CSIF_MAILBOX_HW_INFO(256,             HW_ID0)
+M_CSIF_MAILBOX_HW_INFO(64,              HW_ID1)
+M_CSIF_MAILBOX_HW_INFO(64,              HW_ID2)
+M_CSIF_MAILBOX_HW_INFO(64,              HW_ID3)
+M_CSIF_MAILBOX_HW_INFO(64,              HW_ID4)
+M_CSIF_MAILBOX_HW_INFO(64,              HW_ID5)
+//************* User MUST NOT modify this table *******************//
+//*****************************************************************//
+
+
+//************* User register mailbox on this table ***************//
+//************* Shoalin -> Mcore mailbox 
+//                       code       HW_ID (map to HW Info above)    
+M_CSIF_MAILBOX_C2S_INFO(SS_TEST_ID0,   HW_ID0)
+M_CSIF_MAILBOX_C2S_INFO(SS_TEST_ID1,   HW_ID1)
+M_CSIF_MAILBOX_C2S_INFO(SS_TEST_ID2,   HW_ID2)
+// enum will be CSIF_MAILBOX_C2S_$code
+//************* Mcore -> Shaolin mailbox 
+//                       code       HW_ID (map to HW Info above)
+M_CSIF_MAILBOX_S2C_INFO(SS_TEST_ID3,   HW_ID3)
+M_CSIF_MAILBOX_S2C_INFO(SS_TEST_ID4,   HW_ID4)
+M_CSIF_MAILBOX_S2C_INFO(SS_TEST_ID5,   HW_ID5)
+// enum will be CSIF_MAILBOX_S2C_$code
+//***********User register mailbox on this table*******************//
+#endif
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n0.h b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n0.h
new file mode 100644
index 0000000..b81c2f3
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n0.h
@@ -0,0 +1,106 @@
+// S2C_IRQ_N0
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID16,    CSIF_TRUE,    16)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID17,    CSIF_TRUE,    17)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID18,    CSIF_TRUE,    18)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID19,    CSIF_TRUE,    19)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID20,    CSIF_TRUE,    20)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID21,    CSIF_TRUE,    21)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID22,    CSIF_TRUE,    22)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID23,    CSIF_TRUE,    23)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID24,    CSIF_TRUE,    24)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID25,    CSIF_TRUE,    25)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID26,    CSIF_TRUE,    26)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID27,    CSIF_TRUE,    27)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID28,    CSIF_TRUE,    28)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID29,    CSIF_TRUE,    29)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID30,    CSIF_TRUE,    30)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N0_ID31,    CSIF_TRUE,    31)
+#elif defined(__CSIF_CROSS_CORE_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N0_ID31,    CSIF_FALSE,    31)
+#else
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  sonic_deactivate_cb_n0    ,    N0_ID0,     CSIF_TRUE,    0)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N0_ID31,    CSIF_FALSE,    31)
+#endif
+
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n1.h b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n1.h
new file mode 100644
index 0000000..25efc5f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n1.h
@@ -0,0 +1,105 @@
+// S2C_IRQ_N1
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID0,     CSIF_FALSE,   0)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID1,     CSIF_FALSE,   1)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID2,     CSIF_FALSE,   2)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID3,     CSIF_FALSE,   3)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID4,     CSIF_FALSE,   4)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID5,     CSIF_FALSE,   5)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID6,     CSIF_FALSE,   6)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID7,     CSIF_FALSE,   7)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID8,     CSIF_FALSE,   8)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID9,     CSIF_FALSE,   9)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID10,    CSIF_FALSE,   10)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID11,    CSIF_FALSE,   11)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID12,    CSIF_FALSE,   12)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID13,    CSIF_FALSE,   13)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID14,    CSIF_FALSE,   14)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID15,    CSIF_FALSE,   15)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID16,    CSIF_TRUE,    16)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID17,    CSIF_TRUE,    17)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID18,    CSIF_TRUE,    18)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID19,    CSIF_TRUE,    19)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID20,    CSIF_TRUE,    20)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID21,    CSIF_TRUE,    21)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID22,    CSIF_TRUE,    22)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID23,    CSIF_TRUE,    23)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID24,    CSIF_TRUE,    24)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID25,    CSIF_TRUE,    25)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID26,    CSIF_TRUE,    26)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID27,    CSIF_TRUE,    27)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID28,    CSIF_TRUE,    28)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID29,    CSIF_TRUE,    29)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID30,    CSIF_TRUE,    30)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N1_ID31,    CSIF_TRUE,    31)
+#elif defined(__CSIF_CROSS_CORE_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N1_ID31,    CSIF_FALSE,    31)
+#else
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N1_ID31,    CSIF_FALSE,    31)
+#endif
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n2.h b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n2.h
new file mode 100644
index 0000000..e540e98
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n2.h
@@ -0,0 +1,105 @@
+// S2C_IRQ_n2
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID0,     CSIF_FALSE,  0)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID1,     CSIF_FALSE,  1)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID2,     CSIF_FALSE,  2)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID3,     CSIF_FALSE,  3)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID4,     CSIF_FALSE,  4)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID5,     CSIF_FALSE,  5)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID6,     CSIF_FALSE,  6)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID7,     CSIF_FALSE,  7)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID8,     CSIF_FALSE,  8)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID9,     CSIF_FALSE,  9)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID10,    CSIF_FALSE,  10)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID11,    CSIF_FALSE,  11)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID12,    CSIF_FALSE,  12)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID13,    CSIF_FALSE,  13)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID14,    CSIF_FALSE,  14)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID15,    CSIF_FALSE,  15)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID16,    CSIF_TRUE,   16)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID17,    CSIF_TRUE,   17)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID18,    CSIF_TRUE,   18)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID19,    CSIF_TRUE,   19)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID20,    CSIF_TRUE,   20)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID21,    CSIF_TRUE,   21)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID22,    CSIF_TRUE,   22)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID23,    CSIF_TRUE,   23)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID24,    CSIF_TRUE,   24)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID25,    CSIF_TRUE,   25)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID26,    CSIF_TRUE,   26)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID27,    CSIF_TRUE,   27)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID28,    CSIF_TRUE,   28)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID29,    CSIF_TRUE,   29)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID30,    CSIF_TRUE,   30)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N2_ID31,    CSIF_TRUE,   31)
+#elif defined(__CSIF_CROSS_CORE_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N2_ID31,    CSIF_FALSE,    31)
+#else
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N2_ID31,    CSIF_FALSE,    31)
+#endif
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n3.h b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n3.h
new file mode 100644
index 0000000..94d4649
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n3.h
@@ -0,0 +1,105 @@
+// S2C_IRQ_n3
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID0,     CSIF_FALSE,  0)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID1,     CSIF_FALSE,  1)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID2,     CSIF_FALSE,  2)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID3,     CSIF_FALSE,  3)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID4,     CSIF_FALSE,  4)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID5,     CSIF_FALSE,  5)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID6,     CSIF_FALSE,  6)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID7,     CSIF_FALSE,  7)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID8,     CSIF_FALSE,  8)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID9,     CSIF_FALSE,  9)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID10,    CSIF_FALSE,  10)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID11,    CSIF_FALSE,  11)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID12,    CSIF_FALSE,  12)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID13,    CSIF_FALSE,  13)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID14,    CSIF_FALSE,  14)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID15,    CSIF_FALSE,  15)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID16,    CSIF_TRUE,   16)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID17,    CSIF_TRUE,   17)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID18,    CSIF_TRUE,   18)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID19,    CSIF_TRUE,   19)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID20,    CSIF_TRUE,   20)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID21,    CSIF_TRUE,   21)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID22,    CSIF_TRUE,   22)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID23,    CSIF_TRUE,   23)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID24,    CSIF_TRUE,   24)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID25,    CSIF_TRUE,   25)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID26,    CSIF_TRUE,   26)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID27,    CSIF_TRUE,   27)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID28,    CSIF_TRUE,   28)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID29,    CSIF_TRUE,   29)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID30,    CSIF_TRUE,   30)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N3_ID31,    CSIF_TRUE,   31)
+#elif defined(__CSIF_CROSS_CORE_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N3_ID31,    CSIF_FALSE,    31)
+#else
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N3_ID31,    CSIF_FALSE,    31)
+#endif
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n4.h b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n4.h
new file mode 100644
index 0000000..e9ef22b
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n4.h
@@ -0,0 +1,105 @@
+// S2C_IRQ_n4
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID0,     CSIF_FALSE,  0)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID1,     CSIF_FALSE,  1)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID2,     CSIF_FALSE,  2)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID3,     CSIF_FALSE,  3)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID4,     CSIF_FALSE,  4)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID5,     CSIF_FALSE,  5)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID6,     CSIF_FALSE,  6)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID7,     CSIF_FALSE,  7)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID8,     CSIF_FALSE,  8)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID9,     CSIF_FALSE,  9)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID10,    CSIF_FALSE,  10)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID11,    CSIF_FALSE,  11)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID12,    CSIF_FALSE,  12)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID13,    CSIF_FALSE,  13)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID14,    CSIF_FALSE,  14)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID15,    CSIF_FALSE,  15)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID16,    CSIF_TRUE,   16)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID17,    CSIF_TRUE,   17)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID18,    CSIF_TRUE,   18)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID19,    CSIF_TRUE,   19)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID20,    CSIF_TRUE,   20)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID21,    CSIF_TRUE,   21)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID22,    CSIF_TRUE,   22)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID23,    CSIF_TRUE,   23)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID24,    CSIF_TRUE,   24)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID25,    CSIF_TRUE,   25)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID26,    CSIF_TRUE,   26)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID27,    CSIF_TRUE,   27)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID28,    CSIF_TRUE,   28)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID29,    CSIF_TRUE,   29)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID30,    CSIF_TRUE,   30)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N4_ID31,    CSIF_TRUE,   31)
+#elif defined(__CSIF_CROSS_CORE_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N4_ID31,    CSIF_FALSE,    31)
+#else
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N4_ID31,    CSIF_FALSE,    31)
+#endif
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n5.h b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n5.h
new file mode 100644
index 0000000..0c91594
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/basic/csif_s2c_isr_config_n5.h
@@ -0,0 +1,106 @@
+// S2C_IRQ_N5
+#if defined(__CSIF_DRV_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID0,     CSIF_FALSE,  0)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID1,     CSIF_FALSE,  1)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID2,     CSIF_FALSE,  2)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID3,     CSIF_FALSE,  3)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID4,     CSIF_FALSE,  4)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID5,     CSIF_FALSE,  5)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID6,     CSIF_FALSE,  6)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID7,     CSIF_FALSE,  7)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID8,     CSIF_FALSE,  8)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID9,     CSIF_FALSE,  9)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID10,    CSIF_FALSE,  10)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID11,    CSIF_FALSE,  11)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID12,    CSIF_FALSE,  12)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID13,    CSIF_FALSE,  13)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID14,    CSIF_FALSE,  14)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID15,    CSIF_FALSE,  15)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID16,    CSIF_TRUE,   16)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID17,    CSIF_TRUE,   17)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID18,    CSIF_TRUE,   18)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID19,    CSIF_TRUE,   19)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID20,    CSIF_TRUE,   20)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID21,    CSIF_TRUE,   21)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID22,    CSIF_TRUE,   22)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID23,    CSIF_TRUE,   23)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID24,    CSIF_TRUE,   24)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID25,    CSIF_TRUE,   25)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID26,    CSIF_TRUE,   26)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID27,    CSIF_TRUE,   27)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID28,    CSIF_TRUE,   28)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID29,    CSIF_TRUE,   29)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID30,    CSIF_TRUE,   30)
+M_CSIF_S2C_INFO(  CSIF_Test    ,    N5_ID31,    CSIF_TRUE,   31)
+#elif defined(__CSIF_CROSS_CORE_TEST__)
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_CROSSCORE_TEST    ,    N5_ID31,    CSIF_FALSE,    31)
+#else
+                //CSIF handler         code      irq_ovfl_allowed
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID0,     CSIF_FALSE,    0)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID1,     CSIF_FALSE,    1)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID2,     CSIF_FALSE,    2)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID3,     CSIF_FALSE,    3)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID4,     CSIF_FALSE,    4)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID5,     CSIF_FALSE,    5)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID6,     CSIF_FALSE,    6)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID7,     CSIF_FALSE,    7)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID8,     CSIF_FALSE,    8)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID9,     CSIF_FALSE,    9)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID10,    CSIF_FALSE,    10)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID11,    CSIF_FALSE,    11)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID12,    CSIF_FALSE,    12)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID13,    CSIF_FALSE,    13)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID14,    CSIF_FALSE,    14)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID15,    CSIF_FALSE,    15)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID16,    CSIF_FALSE,    16)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID17,    CSIF_FALSE,    17)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID18,    CSIF_FALSE,    18)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID19,    CSIF_FALSE,    19)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID20,    CSIF_FALSE,    20)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID21,    CSIF_FALSE,    21)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID22,    CSIF_FALSE,    22)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID23,    CSIF_FALSE,    23)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID24,    CSIF_FALSE,    24)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID25,    CSIF_FALSE,    25)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID26,    CSIF_FALSE,    26)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID27,    CSIF_FALSE,    27)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID28,    CSIF_FALSE,    28)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID29,    CSIF_FALSE,    29)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID30,    CSIF_FALSE,    30)
+M_CSIF_S2C_INFO(  CSIF_Invalid    ,    N5_ID31,    CSIF_FALSE,    31)
+
+#endif
+                
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/csif_basic_def.h b/mcu/interface/driver/devdrv/csif/mt6297p/csif_basic_def.h
new file mode 100644
index 0000000..b5fc555
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/csif_basic_def.h
@@ -0,0 +1,255 @@
+/*******************************************
+*   please DO NOT include this file
+*   this file is for mcu/dsp csif driver include only 
+************************************************/
+
+/*******************************************************************************
+  * IRQ Enums 
+  *******************************************************************************/
+
+/* C2S IRQ */
+
+#undef M_CSIF_C2S_INFO
+#define M_CSIF_C2S_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIF_C2S_ID_##Code=Value,
+
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N0_Enum{
+    #include "basic/csif_c2s_isr_config_n0.h"
+    CSIF_C2S_N0_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N0_ENUM_T;
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N1_Enum{
+    //CSIF_C2S_N1_START_ID = 31,
+    #include "basic/csif_c2s_isr_config_n1.h"
+    CSIF_C2S_N1_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N1_ENUM_T;
+
+typedef enum CSIF_C2S_InterruptHandlerCode_N2_Enum{
+    //CSIF_C2S_N2_START_ID = 63,
+    #include "basic/csif_c2s_isr_config_n2.h"
+    CSIF_C2S_N2_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N2_ENUM_T;
+typedef enum CSIF_C2S_InterruptHandlerCode_N3_Enum{
+    //CSIF_C2S_N3_START_ID = 95,
+    #include "basic/csif_c2s_isr_config_n3.h"
+    CSIF_C2S_N3_TOTAL_NUMBER_ENUM
+}CSIF_C2S_N3_ENUM_T;
+
+#undef M_CSIF_C2S_INFO
+
+/* S2C IRQ*/
+
+#undef M_CSIF_S2C_INFO
+#define M_CSIF_S2C_INFO(CSIFHandler, Code, IRQ_ovfl_allow, Value) CSIF_S2C_ID_##Code=Value,
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N0_Enum{
+    #include "basic/csif_s2c_isr_config_n0.h"
+    CSIF_S2C_N0_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N0_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N1_Enum{
+    //CSIF_S2C_N1_START_ID = 31,
+    #include "basic/csif_s2c_isr_config_n1.h"
+    CSIF_S2C_N1_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N1_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N2_Enum{
+    //CSIF_S2C_N2_START_ID = 63,
+    #include "basic/csif_s2c_isr_config_n2.h"
+    CSIF_S2C_N2_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N2_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N3_Enum{
+    //CSIF_S2C_N3_START_ID = 95,
+    #include "basic/csif_s2c_isr_config_n3.h"
+    CSIF_S2C_N3_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N3_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N4_Enum{
+    //CSIF_S2C_N4_START_ID = 127,
+    #include "basic/csif_s2c_isr_config_n4.h"
+    CSIF_S2C_N4_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N4_ENUM_T;
+
+typedef enum CSIF_S2C_InterruptHandlerCode_N5_Enum{
+    //CSIF_S2C_N5_START_ID = 159,
+    #include "basic/csif_s2c_isr_config_n5.h"
+    CSIF_S2C_N5_TOTAL_NUMBER_ENUM
+}CSIF_S2C_N5_ENUM_T;
+
+#undef M_CSIF_S2C_INFO
+
+#if defined(__MSONIC__)
+/* DSP Error */
+#undef M_CSIF_DSP_ERR_INFO
+#define M_CSIF_DSP_ERR_INFO(CSIFErrHandler, Code, Value) CSIF_DSP_Err_##Code=Value,
+
+typedef enum CSIF_DSP_Err_InterruptHandlerCode_Enum{
+    #include "basic/csif_dsp_err_isr_config.h"
+    CSIF_DSP_ERR_TOTAL_NUMBER
+}CSIF_DSP_ERR_ENUM_T;
+
+#undef M_CSIF_DSP_ERR_INFO
+
+#elif defined(__CR4__) || defined(__MIPS_I7200__) || defined(__MIPS_IA__)
+/* L1 Error */
+#undef M_CSIF_L1_ERR_INFO
+#define M_CSIF_L1_ERR_INFO(CSIFErrHandler, Code, Value) CSIF_L1_Err_##Code=Value,
+
+typedef enum CSIF_L1_Err_InterruptHandlerCode_Enum{
+    #include "basic/csif_l1_err_isr_config.h"
+    CSIF_L1_ERR_TOTAL_NUMBER
+}CSIF_L1_ERR_ENUM_T;
+
+#undef M_CSIF_L1_ERR_INFO
+#else
+#error "not supported core"
+#endif
+
+
+/* CSIF C2S Int enum */
+typedef enum CSIF_C2S_Index_Enum{
+    CSIF_ENUM_C2S_N0,
+    CSIF_ENUM_C2S_N1,
+    CSIF_ENUM_C2S_N2,
+    CSIF_ENUM_C2S_N3,
+    CSIF_ENUM_ALL_C2S_INT_NUM
+}CSIF_C2S_INDEX;
+
+/* CSIF S2C Int enum */
+typedef enum CSIF_S2C_Index_Enum{
+    CSIF_ENUM_S2C_N0,
+    CSIF_ENUM_S2C_N1,
+    CSIF_ENUM_S2C_N2,
+    CSIF_ENUM_S2C_N3,
+    CSIF_ENUM_S2C_N4,
+    CSIF_ENUM_S2C_N5,
+    CSIF_ENUM_ALL_S2C_INT_NUM
+}CSIF_S2C_INDEX;
+
+
+/*******************************************************************************
+  * Mailbox Enum 
+  *******************************************************************************/
+/* MAILBOX HW INDEX */
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+#define M_CSIF_MAILBOX_HW_INFO(Size, HW_ID) CSIF_MAILBOX_##HW_ID,
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID)
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID)
+typedef enum CSIF_MAILBOX_HW_Index_Enum{
+    #include "basic/csif_mailbox_config.h"
+    CSIF_MAILBOX_HW_TOTAL_NUMBER
+}CSIF_MAILBOX_HW_INDEX;
+
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+/* MAILBOX Total num */
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+#define M_CSIF_MAILBOX_HW_INFO(Size, HW_ID)
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID) CSIF_MAILBOX_TOTAL_ID_##Code,
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID) CSIF_MAILBOX_TOTAL_ID_##Code,
+typedef enum CSIF_MAILBOX_TOTAL_Index_Enum{
+    #include "basic/csif_mailbox_config.h"
+    CSIF_MAILBOX_SW_TOTAL_NUMBER
+}CSIF_MAILBOX_TOTAL_ENUM_T;
+
+#undef M_CSIF_MAILBOX_C2S_INFO
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID) CSIF_MAILBOX_TOTAL_C2S_ID_##Code,
+#undef M_CSIF_MAILBOX_S2C_INFO
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID)
+
+typedef enum CSIF_MAILBOX_TOTAL_C2S_NUM_Enum{
+    #include "basic/csif_mailbox_config.h"
+    CSIF_MAILBOX_SW_TOTAL_C2S_NUMBER
+}CSIF_MAILBOX_TOTAL_C2S_ENUM_T;
+
+#undef M_CSIF_MAILBOX_C2S_INFO
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID)
+#undef M_CSIF_MAILBOX_S2C_INFO
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID) CSIF_MAILBOX_TOTAL_S2C_ID_##Code,
+
+typedef enum CSIF_MAILBOX_TOTAL_S2C_NUM_Enum{
+    #include "basic/csif_mailbox_config.h"
+    CSIF_MAILBOX_SW_TOTAL_S2C_NUMBER
+}CSIF_MAILBOX_TOTAL_S2C_ENUM_T;
+
+#if defined(__MSONIC__)
+KAL_CASSERT((CSIF_MAILBOX_SW_TOTAL_NUMBER <= CSIF_MAILBOX_HW_TOTAL_NUMBER));
+#endif
+
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+/* C2S MAILBOX Index*/
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+#define M_CSIF_MAILBOX_HW_INFO(Size, HW_ID)
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID) CSIF_MAILBOX_C2S_##Code=CSIF_MAILBOX_##HW_ID,
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID)
+typedef enum CSIF_MAILBOX_C2S_Index_Enum{
+    #include "basic/csif_mailbox_config.h"
+    CSIF_MAILBOX_C2S_LAST_ID
+}CSIF_MAILBOX_C2S_INDEX;
+
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+/* S2C MAILBOX Index*/
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+#define M_CSIF_MAILBOX_HW_INFO(Size, HW_ID)
+#define M_CSIF_MAILBOX_C2S_INFO(Code, HW_ID)
+#define M_CSIF_MAILBOX_S2C_INFO(Code, HW_ID) CSIF_MAILBOX_S2C_##Code=CSIF_MAILBOX_##HW_ID,
+typedef enum CSIF_MAILBOX_S2C_Index_Enum{
+    #include "basic/csif_mailbox_config.h"
+    CSIF_MAILBOX_S2C_LAST_ID
+}CSIF_MAILBOX_S2C_INDEX;
+
+#undef M_CSIF_MAILBOX_HW_INFO
+#undef M_CSIF_MAILBOX_C2S_INFO
+#undef M_CSIF_MAILBOX_S2C_INFO
+
+
+
+/*******************************************************************************
+  * Macros 
+  *******************************************************************************/
+
+#define CSIF_C2S_N0_TOTAL_NUMBER               (CSIF_C2S_N0_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N1_TOTAL_NUMBER               (CSIF_C2S_N1_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N2_TOTAL_NUMBER               (CSIF_C2S_N2_TOTAL_NUMBER_ENUM)
+#define CSIF_C2S_N3_TOTAL_NUMBER               (CSIF_C2S_N3_TOTAL_NUMBER_ENUM)
+//#define CSIF_C2S_N1_TOTAL_NUMBER               (CSIF_C2S_N1_TOTAL_NUMBER_ENUM - CSIF_C2S_N1_START_ID - 1)
+//#define CSIF_C2S_N2_TOTAL_NUMBER               (CSIF_C2S_N2_TOTAL_NUMBER_ENUM - CSIF_C2S_N2_START_ID - 1)
+//#define CSIF_C2S_N3_TOTAL_NUMBER               (CSIF_C2S_N3_TOTAL_NUMBER_ENUM - CSIF_C2S_N3_START_ID - 1)
+
+
+#define CSIF_S2C_N0_TOTAL_NUMBER               (CSIF_S2C_N0_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N1_TOTAL_NUMBER               (CSIF_S2C_N1_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N2_TOTAL_NUMBER               (CSIF_S2C_N2_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N3_TOTAL_NUMBER               (CSIF_S2C_N3_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N4_TOTAL_NUMBER               (CSIF_S2C_N4_TOTAL_NUMBER_ENUM)
+#define CSIF_S2C_N5_TOTAL_NUMBER               (CSIF_S2C_N5_TOTAL_NUMBER_ENUM)
+//#define CSIF_S2C_N1_TOTAL_NUMBER               (CSIF_S2C_N1_TOTAL_NUMBER_ENUM - CSIF_S2C_N1_START_ID - 1)
+//#define CSIF_S2C_N2_TOTAL_NUMBER               (CSIF_S2C_N2_TOTAL_NUMBER_ENUM - CSIF_S2C_N2_START_ID - 1)
+//#define CSIF_S2C_N3_TOTAL_NUMBER               (CSIF_S2C_N3_TOTAL_NUMBER_ENUM - CSIF_S2C_N3_START_ID - 1)
+//#define CSIF_S2C_N4_TOTAL_NUMBER               (CSIF_S2C_N4_TOTAL_NUMBER_ENUM - CSIF_S2C_N4_START_ID - 1)
+//#define CSIF_S2C_N5_TOTAL_NUMBER               (CSIF_S2C_N5_TOTAL_NUMBER_ENUM - CSIF_S2C_N5_START_ID - 1)
+
+#define CSIF_MAILBOX_TOTAL_NUM                  (CSIF_MAILBOX_SW_TOTAL_NUMBER)
+#define CSIF_MAILBOX_C2S_NUM                    (CSIF_MAILBOX_SW_TOTAL_C2S_NUMBER)
+#define CSIF_MAILBOX_S2C_NUM                    (CSIF_MAILBOX_SW_TOTAL_S2C_NUMBER)
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/csif_c2s_isr_config_n0_pre.h b/mcu/interface/driver/devdrv/csif/mt6297p/csif_c2s_isr_config_n0_pre.h
new file mode 100644
index 0000000..4779ee4
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/csif_c2s_isr_config_n0_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_c2s_isr_config_n0.h"
+#else
+    #include "mt6297p/csif_c2s_isr_config_n0.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/csif_c2s_isr_config_n1_pre.h b/mcu/interface/driver/devdrv/csif/mt6297p/csif_c2s_isr_config_n1_pre.h
new file mode 100644
index 0000000..760faab
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/csif_c2s_isr_config_n1_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_c2s_isr_config_n1.h"
+#else
+    #include "mt6297p/csif_c2s_isr_config_n1.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/csif_c2s_isr_config_n2_pre.h b/mcu/interface/driver/devdrv/csif/mt6297p/csif_c2s_isr_config_n2_pre.h
new file mode 100644
index 0000000..42c1043
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/csif_c2s_isr_config_n2_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_c2s_isr_config_n2.h"
+#else
+    #include "mt6297p/csif_c2s_isr_config_n2.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/csif_c2s_isr_config_n3_pre.h b/mcu/interface/driver/devdrv/csif/mt6297p/csif_c2s_isr_config_n3_pre.h
new file mode 100644
index 0000000..2ee2ebf
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/csif_c2s_isr_config_n3_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_c2s_isr_config_n3.h"
+#else
+    #include "mt6297p/csif_c2s_isr_config_n3.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/csif_l1_err_isr_config_pre.h b/mcu/interface/driver/devdrv/csif/mt6297p/csif_l1_err_isr_config_pre.h
new file mode 100644
index 0000000..de523d2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/csif_l1_err_isr_config_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_l1_err_isr_config.h"
+#else
+    #include "mt6297p/csif_l1_err_isr_config.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/csif_mailbox_config_pre.h b/mcu/interface/driver/devdrv/csif/mt6297p/csif_mailbox_config_pre.h
new file mode 100644
index 0000000..83106f3
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/csif_mailbox_config_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_mailbox_config.h"
+#else
+    #include "mt6297p/csif_mailbox_config.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n0_pre.h b/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n0_pre.h
new file mode 100644
index 0000000..7751249
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n0_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_s2c_isr_config_n0.h"
+#else
+    #include "mt6297p/csif_s2c_isr_config_n0.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n1_pre.h b/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n1_pre.h
new file mode 100644
index 0000000..3732de5
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n1_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_s2c_isr_config_n1.h"
+#else
+    #include "mt6297p/csif_s2c_isr_config_n1.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n2_pre.h b/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n2_pre.h
new file mode 100644
index 0000000..6bc2ba3
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n2_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_s2c_isr_config_n2.h"
+#else
+    #include "mt6297p/csif_s2c_isr_config_n2.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n3_pre.h b/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n3_pre.h
new file mode 100644
index 0000000..f5e437a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n3_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_s2c_isr_config_n3.h"
+#else
+    #include "mt6297p/csif_s2c_isr_config_n3.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n4_pre.h b/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n4_pre.h
new file mode 100644
index 0000000..40b8a1f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n4_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_s2c_isr_config_n4.h"
+#else
+    #include "mt6297p/csif_s2c_isr_config_n4.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n5_pre.h b/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n5_pre.h
new file mode 100644
index 0000000..789313e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/csif/mt6297p/csif_s2c_isr_config_n5_pre.h
@@ -0,0 +1,5 @@
+#if defined(__MAUI_BASIC__)
+    #include "basic/csif_s2c_isr_config_n5.h"
+#else
+    #include "mt6297p/csif_s2c_isr_config_n5.h"
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6293/cuif_u2c_isr_config_n0.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6293/cuif_u2c_isr_config_n0.h
new file mode 100644
index 0000000..633345d
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6293/cuif_u2c_isr_config_n0.h
@@ -0,0 +1,432 @@
+#if defined(__CUIF_DRV_TEST__)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L0)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L1)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L2)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L3)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L4)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+//LTE IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L5)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+//LTE IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SPEECH IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SPEECH IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// SPEECH IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SPEECH IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// SPEECH IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else /* basic */
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+//LTE IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+//LTE IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SPEECH IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH0)
+#if defined(__SLEEP_FLOW_IT_DSP__)
+irq_entry_function(CUIF_SLEEP_IT_CALLBACK)
+#else
+irq_entry_function(CUIF_DefaultISR)
+#endif
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SPEECH IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// SPEECH IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SPEECH IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// SPEECH IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6293/cuif_u2c_isr_config_n1.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6293/cuif_u2c_isr_config_n1.h
new file mode 100644
index 0000000..45d7ba3
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6293/cuif_u2c_isr_config_n1.h
@@ -0,0 +1,276 @@
+#if defined(__CUIF_DRV_TEST__)
+// 0
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// LTE IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L4)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_C0)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS0)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS1)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS2)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE0)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else /* basic */
+// 0
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// LTE IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6293/cuif_u2c_isr_config_n2.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6293/cuif_u2c_isr_config_n2.h
new file mode 100644
index 0000000..1974a22
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6293/cuif_u2c_isr_config_n2.h
@@ -0,0 +1,181 @@
+#if defined(__CUIF_DRV_TEST__)
+// 0
+// TDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_T0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// TDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_T1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// TDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_T2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// C2K IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_C3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS0)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS1)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS2)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE0)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else /* basic */
+
+// 0
+// TDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_T0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// TDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_T1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// TDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_T2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// C2K IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_C3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6293/cuif_u2c_isr_config_n3.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6293/cuif_u2c_isr_config_n3.h
new file mode 100644
index 0000000..4e422d4
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6293/cuif_u2c_isr_config_n3.h
@@ -0,0 +1,494 @@
+#if defined(__CUIF_DRV_TEST__)
+// 0
+// FDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// FDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// FDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// FDD IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// FDD IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W4)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// FDD IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W5)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// FDD IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W6)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FDD IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W7)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// FDD IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W8)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// FDD IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W9)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// FDD IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// FDD IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// FDD IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// FDD IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// FDD IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W14)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// FDD IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W15)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// FDD IRQ 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W16)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// FDD IRQ 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W17)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// FDD IRQ 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W18)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// FDD IRQ 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W19)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else /* basic */
+// 0
+// FDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// FDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// FDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// FDD IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// FDD IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// FDD IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// FDD IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FDD IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// FDD IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// FDD IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// FDD IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// FDD IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// FDD IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// FDD IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// FDD IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W14)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// FDD IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W15)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// FDD IRQ 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W16)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// FDD IRQ 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W17)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// FDD IRQ 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W18)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// FDD IRQ 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W19)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
+
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6293/cuif_u2c_isr_config_n4.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6293/cuif_u2c_isr_config_n4.h
new file mode 100644
index 0000000..54b553e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6293/cuif_u2c_isr_config_n4.h
@@ -0,0 +1,332 @@
+#if defined(__CUIF_DRV_TEST__)
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L0)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L1)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L2)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L3)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L4)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L5)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else /* basic */
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_L5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n0.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n0.h
new file mode 100644
index 0000000..fe2e1ff
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n0.h
@@ -0,0 +1,441 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SPEECH IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_TAIL)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SPEECH IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_TAIL)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SPEECH IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_HEAD)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// SPEECH IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SPEECH IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SPEECH IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_TAIL)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SPEECH IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_TAIL)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SPEECH IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_HEAD)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// SPEECH IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SPEECH IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n1.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n1.h
new file mode 100644
index 0000000..9ed9e78
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n1.h
@@ -0,0 +1,261 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+// basic load
+// 0
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_L0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n2.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n2.h
new file mode 100644
index 0000000..6bb680b
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n2.h
@@ -0,0 +1,182 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+// TDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_CEMMC)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// TDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_JDSRP)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// TDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_T2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// C2K IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_C3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+
+// basic load
+// 0
+// TDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_CEMMC)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// TDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_JDSRP)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// TDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_T2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// C2K IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_C3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n3.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n3.h
new file mode 100644
index 0000000..798d020
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n3.h
@@ -0,0 +1,496 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+// FDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W0_CC0_DMA_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// FDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W1_CC1_DMA_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// FDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W2_CC0_EBD_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// FDD IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W3_CC1_EBD_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// FDD IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W4_BCHSFN_DMA_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// FDD IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W5_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// FDD IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W6_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FDD IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W7_PC_DSCH_SUBF0_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// FDD IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W8_PC_DSCH_SUBF1_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// FDD IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W9_PC_DSCH_SUBF2_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// FDD IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W10_PC_DSCH_SUBF3_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// FDD IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W11_PC_DSCH_SUBF4_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// FDD IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W12_DC_DSCH_SUBF0_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// FDD IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W13_DC_DSCH_SUBF1_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// FDD IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W14_DC_DSCH_SUBF2_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// FDD IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W15_DC_DSCH_SUBF3_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// FDD IRQ 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W16_DC_DSCH_SUBF4_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// FDD IRQ 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W17)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// FDD IRQ 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W18)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// FDD IRQ 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W19)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+
+// basic load
+// 0
+// FDD IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W0_CC0_DMA_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// FDD IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W1_CC1_DMA_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// FDD IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W2_CC0_EBD_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// FDD IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W3_CC1_EBD_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// FDD IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W4_BCHSFN_DMA_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// FDD IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W5_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// FDD IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W6_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FDD IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W7_PC_DSCH_SUBF0_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// FDD IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W8_PC_DSCH_SUBF1_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// FDD IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W9_PC_DSCH_SUBF2_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// FDD IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W10_PC_DSCH_SUBF3_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// FDD IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W11_PC_DSCH_SUBF4_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// FDD IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W12_DC_DSCH_SUBF0_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// FDD IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W13_DC_DSCH_SUBF1_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// FDD IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W14_DC_DSCH_SUBF2_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// FDD IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W15_DC_DSCH_SUBF3_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// FDD IRQ 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W16_DC_DSCH_SUBF4_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// FDD IRQ 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W17)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// FDD IRQ 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W18)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// FDD IRQ 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W19)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 30
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 31
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n4.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n4.h
new file mode 100644
index 0000000..8928f13
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n4.h
@@ -0,0 +1,262 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_AFC)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+
+// basic load
+// 0
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_AFC)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n5.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n5.h
new file mode 100644
index 0000000..01c9ab1
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n5.h
@@ -0,0 +1,219 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_L0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_L0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n6.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n6.h
new file mode 100644
index 0000000..785ddd7
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6295/cuif_u2c_isr_config_n6.h
@@ -0,0 +1,218 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n0.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n0.h
new file mode 100644
index 0000000..01dab6e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n0.h
@@ -0,0 +1,365 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L0)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L1)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L2)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L3)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SPEECH IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_TAIL)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SPEECH IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_TAIL)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SPEECH IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_HEAD)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// SPEECH IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SPEECH IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 18
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// SS IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// SS IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// SS IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// SS IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SPEECH IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_TAIL)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SPEECH IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_TAIL)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SPEECH IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_HEAD)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// SPEECH IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SPEECH IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 18
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// SS IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// SS IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// SS IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// SS IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n1.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n1.h
new file mode 100644
index 0000000..9880284
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n1.h
@@ -0,0 +1,285 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n10.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n10.h
new file mode 100644
index 0000000..679a164
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n10.h
@@ -0,0 +1,259 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_BRP_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N10)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N10)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N10)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N10)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N10)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n11.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n11.h
new file mode 100644
index 0000000..b1e2694
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n11.h
@@ -0,0 +1,253 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N11)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N11)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N11)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N11)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N11)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n12.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n12.h
new file mode 100644
index 0000000..78dd740
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n12.h
@@ -0,0 +1,205 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N12)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N12)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N12)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N12)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N12)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n13.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n13.h
new file mode 100644
index 0000000..e237073
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n13.h
@@ -0,0 +1,317 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N13)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N13)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N13)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N13)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N13)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 18
+// reserve IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE14)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 18
+// reserve IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE14)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n2.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n2.h
new file mode 100644
index 0000000..ee73dac
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n2.h
@@ -0,0 +1,222 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS2)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE0)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#else
+
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n3.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n3.h
new file mode 100644
index 0000000..1832fdd
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n3.h
@@ -0,0 +1,380 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// FDD IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W6_RESERVED)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FDD IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W7_PC_DSCH_SUBF0_DONE)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// FDD IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W8_PC_DSCH_SUBF1_DONE)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// FDD IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W9_PC_DSCH_SUBF2_DONE)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// FDD IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W10_PC_DSCH_SUBF3_DONE)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// FDD IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W11_PC_DSCH_SUBF4_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// FDD IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W12_DC_DSCH_SUBF0_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// FDD IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W13_DC_DSCH_SUBF1_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// FDD IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W14_DC_DSCH_SUBF2_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// FDD IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W15_DC_DSCH_SUBF3_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// FDD IRQ 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W16_DC_DSCH_SUBF4_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// FDD IRQ 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W17)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// FDD IRQ 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W18)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// FDD IRQ 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W19)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 22
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#else
+
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// FDD IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W6_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FDD IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W7_PC_DSCH_SUBF0_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// FDD IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W8_PC_DSCH_SUBF1_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// FDD IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W9_PC_DSCH_SUBF2_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// FDD IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W10_PC_DSCH_SUBF3_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// FDD IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W11_PC_DSCH_SUBF4_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// FDD IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W12_DC_DSCH_SUBF0_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// FDD IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W13_DC_DSCH_SUBF1_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// FDD IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W14_DC_DSCH_SUBF2_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// FDD IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W15_DC_DSCH_SUBF3_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// FDD IRQ 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W16_DC_DSCH_SUBF4_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// FDD IRQ 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W17)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// FDD IRQ 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W18)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// FDD IRQ 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W19)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 22
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n4.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n4.h
new file mode 100644
index 0000000..4da3cd7
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n4.h
@@ -0,0 +1,254 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#else
+
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n5.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n5.h
new file mode 100644
index 0000000..5983ff7
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n5.h
@@ -0,0 +1,286 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_L0)
+irq_entry_function(CUIF_DriverTestISR_N5)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS0)
+irq_entry_function(CUIF_DriverTestISR_N5)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS1)
+irq_entry_function(CUIF_DriverTestISR_N5)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS2)
+irq_entry_function(CUIF_DriverTestISR_N5)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE0)
+irq_entry_function(CUIF_DriverTestISR_N5)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#else
+
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_L0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n6.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n6.h
new file mode 100644
index 0000000..f0cabdc
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n6.h
@@ -0,0 +1,381 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N6)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N6)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N6)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N6)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N6)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// reserve IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE14)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE15)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE16)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 22
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE17)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE18)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// reserve IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE14)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE15)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE16)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 22
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE17)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE18)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n7.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n7.h
new file mode 100644
index 0000000..6e996b5
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n7.h
@@ -0,0 +1,253 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N7)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N7)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N7)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N7)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N7)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n8.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n8.h
new file mode 100644
index 0000000..5b8b24b
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n8.h
@@ -0,0 +1,253 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N8)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N8)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N8)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N8)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N8)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n9.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n9.h
new file mode 100644
index 0000000..0474a78
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297/cuif_u2c_isr_config_n9.h
@@ -0,0 +1,253 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N9)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N9)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N9)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N9)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N9)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#if defined(MT6885) || defined(MT6873)
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#endif
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n0.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n0.h
new file mode 100644
index 0000000..127aca8
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n0.h
@@ -0,0 +1,362 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L0)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L1)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L2)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L3)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SPEECH IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_TAIL)
+irq_entry_function(CUIF_DriverTestISR_N0)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SPEECH IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_TAIL)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SPEECH IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_HEAD)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// SPEECH IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SPEECH IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// SS IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// SS IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// SS IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// SS IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// LTE IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// LTE IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// LTE IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_L3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// SPEECH IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_TAIL)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// SPEECH IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_DL_TAIL)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// SPEECH IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_SPEECH_UL_HEAD)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// SPEECH IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// SPEECH IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SPEECH4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// SS IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// SS IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// SS IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// SS IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// SS IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// SS IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// SS IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N0_SS6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n1.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n1.h
new file mode 100644
index 0000000..6607ee1
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n1.h
@@ -0,0 +1,281 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N1)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N1_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n10.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n10.h
new file mode 100644
index 0000000..deae1e7
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n10.h
@@ -0,0 +1,287 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_BRP_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N10)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N10)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N10)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N10)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N10)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N10_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n11.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n11.h
new file mode 100644
index 0000000..5da7c9e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n11.h
@@ -0,0 +1,252 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N11)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N11)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N11)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N11)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N11)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N11_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n12.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n12.h
new file mode 100644
index 0000000..3f30288
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n12.h
@@ -0,0 +1,249 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N12)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N12)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N12)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N12)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N12)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N12_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n13.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n13.h
new file mode 100644
index 0000000..442241a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n13.h
@@ -0,0 +1,314 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N13)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N13)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N13)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N13)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N13)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// reserve IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE14)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// reserve IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N13_RESERVE14)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n2.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n2.h
new file mode 100644
index 0000000..69018e5
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n2.h
@@ -0,0 +1,268 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS2)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE0)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N2)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+
+#else
+
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+
+// 12
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N2_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n3.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n3.h
new file mode 100644
index 0000000..0534f0e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n3.h
@@ -0,0 +1,471 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// FDD IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W6_RESERVED)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FDD IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W7_PC_DSCH_SUBF0_DONE)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// FDD IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W8_PC_DSCH_SUBF1_DONE)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// FDD IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W9_PC_DSCH_SUBF2_DONE)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// FDD IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W10_PC_DSCH_SUBF3_DONE)
+irq_entry_function(CUIF_DriverTestISR_N3)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// FDD IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W11_PC_DSCH_SUBF4_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// FDD IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W12_DC_DSCH_SUBF0_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// FDD IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W13_DC_DSCH_SUBF1_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// FDD IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W14_DC_DSCH_SUBF2_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// FDD IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W15_DC_DSCH_SUBF3_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// FDD IRQ 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W16_DC_DSCH_SUBF4_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// FDD IRQ 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W17)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// FDD IRQ 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W18)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// FDD IRQ 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W19)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+#else
+
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// FDD IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W6_RESERVED)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// FDD IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W7_PC_DSCH_SUBF0_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// FDD IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W8_PC_DSCH_SUBF1_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// FDD IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W9_PC_DSCH_SUBF2_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// FDD IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W10_PC_DSCH_SUBF3_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// FDD IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W11_PC_DSCH_SUBF4_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// FDD IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W12_DC_DSCH_SUBF0_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// FDD IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W13_DC_DSCH_SUBF1_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// FDD IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W14_DC_DSCH_SUBF2_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// FDD IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W15_DC_DSCH_SUBF3_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// FDD IRQ 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W16_DC_DSCH_SUBF4_DONE)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// FDD IRQ 17
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W17)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// FDD IRQ 18
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W18)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// FDD IRQ 19
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_W19)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// C2K IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_C0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 24
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 25
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 26
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 27
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 28
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 29
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N3_SS8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n4.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n4.h
new file mode 100644
index 0000000..f616e1d
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n4.h
@@ -0,0 +1,282 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N4)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N4_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n5.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n5.h
new file mode 100644
index 0000000..27eb533
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n5.h
@@ -0,0 +1,283 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_L0)
+irq_entry_function(CUIF_DriverTestISR_N5)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS0)
+irq_entry_function(CUIF_DriverTestISR_N5)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS1)
+irq_entry_function(CUIF_DriverTestISR_N5)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS2)
+irq_entry_function(CUIF_DriverTestISR_N5)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE0)
+irq_entry_function(CUIF_DriverTestISR_N5)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// LTE IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_L0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// SS 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// SS 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// SS 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_SS2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N5_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n6.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n6.h
new file mode 100644
index 0000000..77c25b2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n6.h
@@ -0,0 +1,377 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N6)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N6)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N6)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N6)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N6)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// reserve IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE14)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE15)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE16)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE17)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE18)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 18
+// reserve IRQ 13
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE13)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 19
+// reserve IRQ 14
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE14)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 20
+// reserve IRQ 15
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE15)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 21
+// reserve IRQ 16
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE16)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 22
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE17)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 23
+// reserved
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N6_RESERVE18)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n7.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n7.h
new file mode 100644
index 0000000..6f79c78
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n7.h
@@ -0,0 +1,282 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N7)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N7)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N7)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N7)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N7)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N7_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n8.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n8.h
new file mode 100644
index 0000000..cb1b751
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n8.h
@@ -0,0 +1,281 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N8)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N8)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N8)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N8)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N8)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N8_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n9.h b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n9.h
new file mode 100644
index 0000000..076aa48
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/basic_load/mt6297p/cuif_u2c_isr_config_n9.h
@@ -0,0 +1,281 @@
+#if defined(__CUIF_DRV_TEST__)
+
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_INNER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_OUTER_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_FEC_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_SPEECH_WFI)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE1)
+irq_entry_function(CUIF_DriverTestISR_N9)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE2)
+irq_entry_function(CUIF_DriverTestISR_N9)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE3)
+irq_entry_function(CUIF_DriverTestISR_N9)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE4)
+irq_entry_function(CUIF_DriverTestISR_N9)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE5)
+irq_entry_function(CUIF_DriverTestISR_N9)
+irq_auto_eoi(CUIF_FALSE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#else
+// basic load
+// 0
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_INNER_WFI)
+irq_entry_function(wfi_irq_callback_inner)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_OUTER_WFI)
+irq_entry_function(wfi_irq_callback_brp)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_SPEECH_WFI)
+irq_entry_function(wfi_irq_callback_speech)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_FEC_WFI)
+irq_entry_function(wfi_irq_callback_fec)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_DUMMY_WFI_0)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_DUMMY_WFI_1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 6
+// reserve IRQ 1
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE1)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 7
+// reserve IRQ 2
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE2)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 8
+// reserve IRQ 3
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE3)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 9
+// reserve IRQ 4
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE4)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 10
+// reserve IRQ 5
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE5)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 11
+// reserve IRQ 6
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE6)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 12
+// reserve IRQ 7
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE7)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 13
+// reserve IRQ 8
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE8)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 14
+// reserve IRQ 9
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE9)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 15
+// reserve IRQ 10
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE10)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 16
+// reserve IRQ 11
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE11)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+// 17
+// reserve IRQ 12
+/************************* Core ISR Configure Begin ****************/
+irq_index(CUIF_U2C_N9_RESERVE12)
+irq_entry_function(CUIF_DefaultISR)
+irq_auto_eoi(CUIF_TRUE)
+/************************* Core ISR Configure END ******************/
+
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/cuif_l1core_public.h b/mcu/interface/driver/devdrv/cuif/inc/cuif_l1core_public.h
new file mode 100644
index 0000000..a562ea7
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/cuif_l1core_public.h
@@ -0,0 +1,328 @@
+#ifndef __CUIF_L1CORE_PUBLIC_H__
+#define __CUIF_L1CORE_PUBLIC_H__
+
+#include "kal_general_types.h"
+
+#include "cuif_common_def.h"
+
+/*******************************************************************************
+ * Typedefs 
+ *******************************************************************************/
+/*
+
+emum CUIF_C2U_INNER_Code_t defined in
+"common/interface/driver/sys_drv/cuif/cuif_c2u_isr_config_inner.h"
+
+enum CUIF_C2U_OUTER_Code_t defined in
+"common/interface/driver/sys_drv/cuif/uif_c2u_isr_config_brp.h"
+
+enum CUIF_C2U_FEC_Code_t defined in
+"common/interface/driver/sys_drv/cuif/cuif_c2u_isr_config_fec_wbrp.h"
+
+enum CUIF_C2U_SPEECH_Code_t defined in
+"common/interface/driver/sys_drv/cuif/cuif_c2u_isr_config_speech.h"
+
+*/
+
+typedef kal_char                cuif_char;   
+typedef kal_uint8               cuif_uint8;  
+typedef kal_int8                cuif_int8;   
+typedef kal_uint16              cuif_uint16; 
+typedef kal_int16               cuif_int16;  
+typedef kal_uint32              cuif_uint32; 
+typedef kal_int32               cuif_int32;  
+typedef kal_bool                cuif_bool;
+
+/* Define status register type */
+typedef struct{
+    cuif_uint32 mask31_0;
+    cuif_uint32 *status_reg_addr;
+}CUIF_Mask_t;
+
+/* User callback should be registered in common/interface/driver/sys_drv/cuif/ */
+
+/* Define user callback function type */
+typedef void (*CUIF_InterruptEntryFun)(CUIF_Mask_t*);
+
+/*******************************************************************************
+  * User-Aware MCU part API
+  *******************************************************************************/
+/*
+where mask is typeof
+typedef struct{
+    cuif_uint32 mask31_0;    
+}CUIF_Mask_t;
+
+code is typeof
+cuif_uint32 code
+*/
+
+/* U2C direction */
+/* get interrupt STATUS */
+#define CUIF_U2C_N0_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N0, mask)
+#define CUIF_U2C_N1_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N1, mask)
+#define CUIF_U2C_N2_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N2, mask)
+#define CUIF_U2C_N3_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N3, mask)
+#define CUIF_U2C_N4_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N4, mask)
+#if defined(__MD95__)
+#define CUIF_U2C_N5_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N5, mask)
+#define CUIF_U2C_N6_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N6, mask)
+#elif defined(__MD97__) || defined(__MD97P__)
+#define CUIF_U2C_N5_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N5, mask)
+#define CUIF_U2C_N6_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N6, mask)
+#define CUIF_U2C_N7_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N7, mask)
+#define CUIF_U2C_N8_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N8, mask)
+#define CUIF_U2C_N9_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N9, mask)
+#define CUIF_U2C_N10_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N10, mask)
+#define CUIF_U2C_N11_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N11, mask)
+#define CUIF_U2C_N12_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N12, mask)
+#define CUIF_U2C_N13_STATUS(mask)        CUIF_U2C_STATUS(CUIF_ENUM_N13, mask)
+#endif
+
+#if defined(__MD93__) || defined(__MD95__)
+#define CUIF_U2C_WAKEUP_STATUS(mask)    CUIF_U2C_STATUS(CUIF_ENUM_WAKEUP, mask)
+#endif
+
+/* set interrupt EOI */
+#define CUIF_N0_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N0, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N0))
+#define CUIF_N1_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N1, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N1))
+#define CUIF_N2_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N2, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N2))
+#define CUIF_N3_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N3, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N3))
+#define CUIF_N4_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N4, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N4))
+#if defined(__MD95__)
+#define CUIF_N5_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N5, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N5))
+#define CUIF_N6_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N6, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N6))
+#elif defined(__MD97__) || defined(__MD97P__)
+#define CUIF_N5_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N5, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N5))
+#define CUIF_N6_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N6, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N6))
+#define CUIF_N7_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N7, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N7))
+#define CUIF_N8_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N8, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N8))
+#define CUIF_N9_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N9, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N9))
+#define CUIF_N10_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N10, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N10))
+#define CUIF_N11_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N11, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N11))
+#define CUIF_N12_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N12, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N12))
+#define CUIF_N13_EOI(code)               CUIF_U2C_EOI(CUIF_ENUM_N13, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N13))
+#endif
+
+/* clear speech wake-up source, only for speech usage */
+#if defined(__MD97__) || defined(__MD97P__)
+#define CUIF_SPEECH_WAKEUP_EOI()        CUIF_U2C_WAKEUP_EOI(CUIF_ENUM_WAKEUP, CUIF_ENUM_SPEECH, GET_MCU_INT_IRQ_LIMIT_NUMBER(WAKEUP))
+#else
+#define CUIF_SPEECH_WAKEUP_EOI()        CUIF_U2C_EOI(CUIF_ENUM_WAKEUP, CUIF_ENUM_SPEECH, GET_MCU_INT_IRQ_LIMIT_NUMBER(WAKEUP))
+#endif
+
+/* get ENABLE(mask) STATUS */
+#define CUIF_N0_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N0, mask)
+#define CUIF_N1_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N1, mask)
+#define CUIF_N2_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N2, mask)
+#define CUIF_N3_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N3, mask)
+#define CUIF_N4_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N4, mask)
+#if defined(__MD95__)
+#define CUIF_N5_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N5, mask)
+#define CUIF_N6_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N6, mask)
+#elif defined(__MD97__) || defined(__MD97P__)
+#define CUIF_N5_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N5, mask)
+#define CUIF_N6_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N6, mask)
+#define CUIF_N7_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N7, mask)
+#define CUIF_N8_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N8, mask)
+#define CUIF_N9_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N9, mask)
+#define CUIF_N10_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N10, mask)
+#define CUIF_N11_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N11, mask)
+#define CUIF_N12_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N12, mask)
+#define CUIF_N13_EN_STATUS(mask)         CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_N13, mask)
+#endif
+#define CUIF_WAKEUP_EN_STATUS(mask)     CUIF_U2C_ENABLE_STATUS(CUIF_ENUM_WAKEUP, mask)
+
+/* set mask ENABLE */
+#define CUIF_N0_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N0, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N0))
+#define CUIF_N1_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N1, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N1))
+#define CUIF_N2_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N2, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N2))
+#define CUIF_N3_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N3, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N3))
+#define CUIF_N4_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N4, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N4))
+#if defined(__MD95__)
+#define CUIF_N5_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N5, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N5))
+#define CUIF_N6_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N6, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N6))
+#elif defined(__MD97__) || defined(__MD97P__)
+#define CUIF_N5_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N5, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N5))
+#define CUIF_N6_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N6, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N6))
+#define CUIF_N7_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N7, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N7))
+#define CUIF_N8_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N8, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N8))
+#define CUIF_N9_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N9, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N9))
+#define CUIF_N10_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N10, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N10))
+#define CUIF_N11_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N11, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N11))
+#define CUIF_N12_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N12, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N12))
+#define CUIF_N13_ENABLE(code)            CUIF_U2C_ENABLE(CUIF_ENUM_N13, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N13))
+#endif
+#define CUIF_WAKEUP_ENABLE(code)        CUIF_U2C_ENABLE(CUIF_ENUM_WAKEUP, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(WAKEUP))
+
+/* set mask DISABLE */
+#define CUIF_N0_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N0, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N0))
+#define CUIF_N1_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N1, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N1))
+#define CUIF_N2_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N2, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N2))
+#define CUIF_N3_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N3, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N3))
+#define CUIF_N4_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N4, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N4))
+#if defined(__MD95__)
+#define CUIF_N5_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N5, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N5))
+#define CUIF_N6_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N6, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N6))
+#elif defined(__MD97__) || defined(__MD97P__)
+#define CUIF_N5_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N5, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N5))
+#define CUIF_N6_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N6, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N6))
+#define CUIF_N7_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N7, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N7))
+#define CUIF_N8_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N8, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N8))
+#define CUIF_N9_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N9, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N9))
+#define CUIF_N10_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N10, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N10))
+#define CUIF_N11_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N11, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N11))
+#define CUIF_N12_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N12, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N12))
+#define CUIF_N13_DISABLE(code)           CUIF_U2C_DISABLE(CUIF_ENUM_N13, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(N13))
+#endif
+#define CUIF_WAKEUP_DISABLE(code)       CUIF_U2C_DISABLE(CUIF_ENUM_WAKEUP, code, GET_MCU_INT_IRQ_LIMIT_NUMBER(WAKEUP))
+
+/* C2U direction */
+
+/* SET interrupt, if the code's bit has been set before, it will cause assertion */
+#define CUIF_INNER_SWI_SW(code)         CUIF_C2U_SWI_SW(CUIF_ENUM_INNER, code, GET_MODULE_IRQ_LIMIT_NUMBER(INNER))
+#define CUIF_BRP_SWI_SW(code)           CUIF_C2U_SWI_SW(CUIF_ENUM_OUTER, code, GET_MODULE_IRQ_LIMIT_NUMBER(OUTER))
+#define CUIF_FEC_SWI_SW(code)           CUIF_C2U_SWI_SW(CUIF_ENUM_FEC, code, GET_MODULE_IRQ_LIMIT_NUMBER(FEC))
+#define CUIF_SPEECH_SWI_SW(code)        CUIF_C2U_SWI_SW(CUIF_ENUM_SPEECH, code, GET_MODULE_IRQ_LIMIT_NUMBER(SPEECH))
+
+#if defined(__MD95__)
+/* SET interrupt, for logging purpose only, no check */
+#define CUIF_INNER_LOG_FILTER_WRITE_FLAG_SWI()   CUIF_C2U_SWI_NO_CHECK(CUIF_ENUM_INNER, CUIF_C2U_INNER_LOG_FILTER_WRITE_FLAG, GET_MODULE_IRQ_LIMIT_NUMBER(INNER))
+#define CUIF_OUTER_LOG_FILTER_WRITE_FLAG_SWI()   CUIF_C2U_SWI_NO_CHECK(CUIF_ENUM_OUTER, CUIF_C2U_BRP_LOG_FILTER_WRITE_FLAG, GET_MODULE_IRQ_LIMIT_NUMBER(OUTER))
+#define CUIF_FEC_LOG_FILTER_WRITE_FLAG_SWI()     CUIF_C2U_SWI_NO_CHECK(CUIF_ENUM_FEC, CUIF_C2U_FEC_WBRP_LOG_FILTER_WRITE_FLAG, GET_MODULE_IRQ_LIMIT_NUMBER(FEC))
+#define CUIF_SPEECH_LOG_FILTER_WRITE_FLAG_SWI()  CUIF_C2U_SWI_NO_CHECK(CUIF_ENUM_SPEECH, CUIF_C2U_SPEECH_LOG_FILTER_WRITE_FLAG, GET_MODULE_IRQ_LIMIT_NUMBER(SPEECH))
+#endif
+
+/* get C2U interrupt STATUS */
+#define CUIF_C2U_INNER_STATUS(mask)     CUIF_C2U_STATUS(CUIF_ENUM_INNER, mask)
+#define CUIF_C2U_OUTER_STATUS(mask)     CUIF_C2U_STATUS(CUIF_ENUM_OUTER, mask)
+#define CUIF_C2U_FEC_STATUS(mask)       CUIF_C2U_STATUS(CUIF_ENUM_FEC, mask)
+#define CUIF_C2U_SPEECH_STATUS(mask)    CUIF_C2U_STATUS(CUIF_ENUM_SPEECH, mask)
+
+/*******************************************************************************
+ * Function prototypes
+ *******************************************************************************/
+extern void CUIF_Init();
+
+
+/*
+  *  Get CUIF U2C Status register value
+  *  @param[in]    nID -the enum of N0, N1, N2, N3, N4, N5, N6
+  *  @param[out]   mask  - the value of status register(s)
+  *
+  */
+extern void CUIF_U2C_STATUS(CUIF_MCU_INT nID, CUIF_Mask_t* m);
+
+#if defined(__MD97__) || defined(__MD97P__)
+/*
+  *  Get CUIF U2C WAKEUP Status register value
+  *  @param[in]    nID -the enum of N0, N1, N2, N3, N4, N5, N6
+  *  @param[out]   mask  - the value of status register(s)
+  *
+  */
+extern void CUIF_U2C_WAKEUP_STATUS(CUIF_Mask_t* m);
+
+/**
+  *   When the `irq_auto_eoi()` attribute is `CUIF_FALSE`
+  *   Users could call these function to clean the interrupt bit
+  *
+  *  @param[in]  nID -the enum of N0, N1, N2, N3, N4, N5, N6
+  *  @param[in]  code  - use enum of `CUIF_U2C_NX_Code_t`, where NX = N0, N1, N2, N3, N4, N5, N6
+  *  @param[in]  limit - CUIF_MCU_INT_NX_SOURCES, where NX = N0, N1, N2, N3, N4, N5, N6
+  *  @return no return
+  *
+  */
+extern void CUIF_U2C_WAKEUP_EOI(CUIF_MCU_INT nID, cuif_uint32 code, cuif_uint32 limit);
+#endif
+
+/**
+  *   When the `irq_auto_eoi()` attribute is `CUIF_FALSE`
+  *   Users could call these function to clean the interrupt bit
+  *
+  *  @param[in]  nID -the enum of N0, N1, N2, N3, N4, N5, N6
+  *  @param[in]  code  - use enum of `CUIF_U2C_NX_Code_t`, where NX = N0, N1, N2, N3, N4, N5, N6
+  *  @param[in]  limit - CUIF_MCU_INT_NX_SOURCES, where NX = N0, N1, N2, N3, N4, N5, N6
+  *  @return no return
+  *
+  */
+extern void CUIF_U2C_EOI(CUIF_MCU_INT nID, cuif_uint32 code, cuif_uint32 limit);
+
+
+/*
+  *  Get CUIF enable(mask) status register value
+  *  @param[in]    nID -the enum of N0, N1, N2, N3, N4, N5, N6
+  *  @param[out]   mask  - the value of enable(mask) status register(s)
+  *
+  */
+extern void CUIF_U2C_ENABLE_STATUS(CUIF_MCU_INT nID, CUIF_Mask_t* m);
+
+/**
+  *   Set the bit of `code` to enable sorresponding CUIF interrupt
+  *
+  *  @param[in]  nID -the enum of N0, N1, N2, N3, N4, N5, N6
+  *  @param[in]  code  - use enum of `CUIF_U2C_NX_Code_t`, where NX = N0, N1, N2, N3, N4, N5, N6
+  *  @param[in]  limit - CUIF_MCU_INT_NX_SOURCES, where NX = N0, N1, N2, N3, N4, N5, N6
+  *  @return no return
+  *
+  */
+extern void CUIF_U2C_ENABLE(CUIF_MCU_INT nID, cuif_uint32 code, cuif_uint32 limit);
+
+/**
+  *   Set the bit of `code` to disable sorresponding CUIF interrupt
+  *
+  *  @param[in]  nID -the enum of N0, N1, N2, N3, N4, N5, N6
+  *  @param[in]  code  - use enum of `CUIF_U2C_NX_Code_t`, where NX = N0, N1, N2, N3, N4, N5, N6
+  *  @param[in]  limit - CUIF_MCU_INT_NX_SOURCES, where NX = N0, N1, N2, N3, N4, N5, N6
+  *  @return no return
+
+  *
+  */
+extern void CUIF_U2C_DISABLE(CUIF_MCU_INT nID, cuif_uint32 code, cuif_uint32 limit);
+
+
+/**
+  *  CUIF Interrupt: MCU trigger uSIP, if the code's bit has been set before, it will cause assertion
+  *
+  *  @param[in]    moduleID -the enum of INNER, OUTER, FEC, SPEECH
+  *  @param[in]  code  - use enum of `CUIF_C2U_XXX_Code_t`, where XXX = INNER, OUTER, FEC, SPEECH
+  *  @param[in]  limit - CUIF_NUM_INTERRUPT_X_SOURCES, where X = INNER, OUTER, FEC, SPEECH
+  *  @return no return
+  *
+  **/
+extern void CUIF_C2U_SWI_SW(CUIF_MODULE_INDEX moduleID, cuif_uint32 code, cuif_uint32 limit);
+
+/**
+  *  CUIF Interrupt: MCU trigger uSIP, it would not check if the code's bit has been set before
+  *
+  *  @param[in]    moduleID -the enum of INNER, OUTER, FEC, SPEECH
+  *  @param[in]  code  - use enum of `CUIF_C2U_XXX_Code_t`, where XXX = INNER, OUTER, FEC, SPEECH
+  *  @param[in]  limit - CUIF_NUM_INTERRUPT_X_SOURCES, where X = INNER, OUTER, FEC, SPEECH
+  *  @return no return
+  *
+  **/
+extern void CUIF_C2U_SWI_NO_CHECK(CUIF_MODULE_INDEX moduleID, cuif_uint32 code, cuif_uint32 limit);
+
+
+/**
+  *   Get CUIF C2U Status register value
+  *
+  *  @param[in]    moduleID -the enum of INNER, OUTER, FEC, SPEECH
+  *  @param[out]   mask  - the value of status register(s)
+  *
+  **/
+extern void CUIF_C2U_STATUS(CUIF_MODULE_INDEX moduleID, CUIF_Mask_t* m);
+
+/**
+  *   Backup CUIF U2C enable registers, used for sleep flow only
+  *
+  **/
+extern void CUIF_register_backup();
+
+/**
+  *   Restore CUIF U2C enable registers, used for sleep flow only
+  *
+  **/
+extern void CUIF_register_restore();
+
+#endif /*__CUIF_L1CORE_PUBLIC_H__*/
+
diff --git a/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n0_pre.h b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n0_pre.h
new file mode 100644
index 0000000..226b8e3
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n0_pre.h
@@ -0,0 +1,32 @@
+#if defined(__MAUI_BASIC__)
+
+#if defined(__MD93__)
+    #include "basic_load/mt6293/cuif_u2c_isr_config_n0.h"
+#elif defined(__MD95__)
+    #include "basic_load/mt6295/cuif_u2c_isr_config_n0.h"
+#elif defined(__MD97__)
+    #include "basic_load/mt6297/cuif_u2c_isr_config_n0.h"
+#elif defined(__MD97P__)
+    #include "basic_load/mt6297p/cuif_u2c_isr_config_n0.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+
+#else // #if defined(__MAUI_BASIC__)
+
+    
+#if defined(__MD93__)
+    #include "mt6293/cuif_u2c_isr_config_n0.h"
+#elif defined(__MD95__)
+    #include "mt6295/cuif_u2c_isr_config_n0.h"
+#elif defined(__MD97__)
+    #include "mt6297/cuif_u2c_isr_config_n0.h"
+#elif defined(__MD97P__)
+    #include "mt6297p/cuif_u2c_isr_config_n0.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+    
+#endif // #if defined(__MAUI_BASIC__)
diff --git a/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n10_pre.h b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n10_pre.h
new file mode 100644
index 0000000..807ed71
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n10_pre.h
@@ -0,0 +1,28 @@
+#if defined(__MAUI_BASIC__)
+
+#if defined(__MD97__)
+    #include "basic_load/mt6297/cuif_u2c_isr_config_n10.h"
+
+#elif defined(__MD97P__)
+    #include "basic_load/mt6297p/cuif_u2c_isr_config_n10.h"
+
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+
+#else
+
+    
+#if defined(__MD97__)
+    #include "mt6297/cuif_u2c_isr_config_n10.h"
+
+#elif defined(__MD97P__)
+    #include "mt6297p/cuif_u2c_isr_config_n10.h"
+
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+    
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n11_pre.h b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n11_pre.h
new file mode 100644
index 0000000..e8ee7d4
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n11_pre.h
@@ -0,0 +1,24 @@
+#if defined(__MAUI_BASIC__)
+
+#if defined(__MD97__)
+    #include "basic_load/mt6297/cuif_u2c_isr_config_n11.h"
+#elif defined(__MD97P__)
+    #include "basic_load/mt6297p/cuif_u2c_isr_config_n11.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+
+#else
+
+    
+#if defined(__MD97__)
+    #include "mt6297/cuif_u2c_isr_config_n11.h"
+#elif defined(__MD97P__)
+    #include "mt6297p/cuif_u2c_isr_config_n11.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+    
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n12_pre.h b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n12_pre.h
new file mode 100644
index 0000000..4e6ba8d
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n12_pre.h
@@ -0,0 +1,24 @@
+#if defined(__MAUI_BASIC__)
+
+#if defined(__MD97__)
+    #include "basic_load/mt6297/cuif_u2c_isr_config_n12.h"
+#elif defined(__MD97P__)
+    #include "basic_load/mt6297p/cuif_u2c_isr_config_n12.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+
+#else
+
+    
+#if defined(__MD97__)
+    #include "mt6297/cuif_u2c_isr_config_n12.h"
+#elif defined(__MD97P__)
+    #include "mt6297p/cuif_u2c_isr_config_n12.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+    
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n13_pre.h b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n13_pre.h
new file mode 100644
index 0000000..e8df9a7
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n13_pre.h
@@ -0,0 +1,24 @@
+#if defined(__MAUI_BASIC__)
+
+#if defined(__MD97__)
+    #include "basic_load/mt6297/cuif_u2c_isr_config_n13.h"
+#elif defined(__MD97P__)
+    #include "basic_load/mt6297p/cuif_u2c_isr_config_n13.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+
+#else
+
+    
+#if defined(__MD97__)
+    #include "mt6297/cuif_u2c_isr_config_n13.h"
+#elif defined(__MD97P__)
+    #include "mt6297p/cuif_u2c_isr_config_n13.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+    
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n1_pre.h b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n1_pre.h
new file mode 100644
index 0000000..5040799
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n1_pre.h
@@ -0,0 +1,32 @@
+#if defined(__MAUI_BASIC__)
+
+#if defined(__MD93__)
+    #include "basic_load/mt6293/cuif_u2c_isr_config_n1.h"
+#elif defined(__MD95__)
+    #include "basic_load/mt6295/cuif_u2c_isr_config_n1.h"
+#elif defined(__MD97__)
+    #include "basic_load/mt6297/cuif_u2c_isr_config_n1.h"
+#elif defined(__MD97P__)
+    #include "basic_load/mt6297p/cuif_u2c_isr_config_n1.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+
+#else // #if defined(__MAUI_BASIC__)
+
+    
+#if defined(__MD93__)
+    #include "mt6293/cuif_u2c_isr_config_n1.h"
+#elif defined(__MD95__)
+    #include "mt6295/cuif_u2c_isr_config_n1.h"
+#elif defined(__MD97__)
+    #include "mt6297/cuif_u2c_isr_config_n1.h"
+#elif defined(__MD97P__)
+    #include "mt6297p/cuif_u2c_isr_config_n1.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+    
+#endif // #if defined(__MAUI_BASIC__)
diff --git a/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n2_pre.h b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n2_pre.h
new file mode 100644
index 0000000..17acec1
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n2_pre.h
@@ -0,0 +1,32 @@
+#if defined(__MAUI_BASIC__)
+
+#if defined(__MD93__)
+    #include "basic_load/mt6293/cuif_u2c_isr_config_n2.h"
+#elif defined(__MD95__)
+    #include "basic_load/mt6295/cuif_u2c_isr_config_n2.h"
+#elif defined(__MD97__)
+    #include "basic_load/mt6297/cuif_u2c_isr_config_n2.h"
+#elif defined(__MD97P__)
+    #include "basic_load/mt6297p/cuif_u2c_isr_config_n2.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+
+#else // #if defined(__MAUI_BASIC__)
+
+    
+#if defined(__MD93__)
+    #include "mt6293/cuif_u2c_isr_config_n2.h"
+#elif defined(__MD95__)
+    #include "mt6295/cuif_u2c_isr_config_n2.h"
+#elif defined(__MD97__)
+    #include "mt6297/cuif_u2c_isr_config_n2.h"
+#elif defined(__MD97P__)
+    #include "mt6297p/cuif_u2c_isr_config_n2.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+    
+#endif // #if defined(__MAUI_BASIC__)
diff --git a/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n3_pre.h b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n3_pre.h
new file mode 100644
index 0000000..991efc4
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n3_pre.h
@@ -0,0 +1,32 @@
+#if defined(__MAUI_BASIC__)
+
+#if defined(__MD93__)
+    #include "basic_load/mt6293/cuif_u2c_isr_config_n3.h"
+#elif defined(__MD95__)
+    #include "basic_load/mt6295/cuif_u2c_isr_config_n3.h"
+#elif defined(__MD97__)
+    #include "basic_load/mt6297/cuif_u2c_isr_config_n3.h"
+#elif defined(__MD97P__)
+    #include "basic_load/mt6297p/cuif_u2c_isr_config_n3.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+
+#else // #if defined(__MAUI_BASIC__)
+
+    
+#if defined(__MD93__)
+    #include "mt6293/cuif_u2c_isr_config_n3.h"
+#elif defined(__MD95__)
+    #include "mt6295/cuif_u2c_isr_config_n3.h"
+#elif defined(__MD97__)
+    #include "mt6297/cuif_u2c_isr_config_n3.h"
+#elif defined(__MD97P__)
+    #include "mt6297p/cuif_u2c_isr_config_n3.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+    
+#endif // #if defined(__MAUI_BASIC__)
diff --git a/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n4_pre.h b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n4_pre.h
new file mode 100644
index 0000000..8fd8eed
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n4_pre.h
@@ -0,0 +1,32 @@
+#if defined(__MAUI_BASIC__)
+
+#if defined(__MD93__)
+    #include "basic_load/mt6293/cuif_u2c_isr_config_n4.h"
+#elif defined(__MD95__)
+    #include "basic_load/mt6295/cuif_u2c_isr_config_n4.h"
+#elif defined(__MD97__)
+    #include "basic_load/mt6297/cuif_u2c_isr_config_n4.h"
+#elif defined(__MD97P__)
+    #include "basic_load/mt6297p/cuif_u2c_isr_config_n4.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+
+#else // #if defined(__MAUI_BASIC__)
+
+    
+#if defined(__MD93__)
+    #include "mt6293/cuif_u2c_isr_config_n4.h"
+#elif defined(__MD95__)
+    #include "mt6295/cuif_u2c_isr_config_n4.h"
+#elif defined(__MD97__)
+    #include "mt6297/cuif_u2c_isr_config_n4.h"
+#elif defined(__MD97P__)
+    #include "mt6297p/cuif_u2c_isr_config_n4.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+    
+#endif // #if defined(__MAUI_BASIC__)
diff --git a/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n5_pre.h b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n5_pre.h
new file mode 100644
index 0000000..2b2d0ab
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n5_pre.h
@@ -0,0 +1,28 @@
+#if defined(__MAUI_BASIC__)
+
+#if defined(__MD95__)
+    #include "basic_load/mt6295/cuif_u2c_isr_config_n5.h"
+#elif defined(__MD97__)
+    #include "basic_load/mt6297/cuif_u2c_isr_config_n5.h"
+#elif defined(__MD97P__)
+    #include "basic_load/mt6297p/cuif_u2c_isr_config_n5.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+
+#else
+
+    
+#if defined(__MD95__)
+    #include "mt6295/cuif_u2c_isr_config_n5.h"
+#elif defined(__MD97__)
+    #include "mt6297/cuif_u2c_isr_config_n5.h"
+#elif defined(__MD97P__)
+    #include "mt6297p/cuif_u2c_isr_config_n5.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+    
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n6_pre.h b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n6_pre.h
new file mode 100644
index 0000000..74de977
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n6_pre.h
@@ -0,0 +1,28 @@
+#if defined(__MAUI_BASIC__)
+
+#if defined(__MD95__)
+    #include "basic_load/mt6295/cuif_u2c_isr_config_n6.h"
+#elif defined(__MD97__)
+    #include "basic_load/mt6297/cuif_u2c_isr_config_n6.h"
+#elif defined(__MD97P__)
+    #include "basic_load/mt6297p/cuif_u2c_isr_config_n6.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+
+#else
+
+    
+#if defined(__MD95__)
+    #include "mt6295/cuif_u2c_isr_config_n6.h"
+#elif defined(__MD97__)
+    #include "mt6297/cuif_u2c_isr_config_n6.h"
+#elif defined(__MD97P__)
+    #include "mt6297p/cuif_u2c_isr_config_n6.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+    
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n7_pre.h b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n7_pre.h
new file mode 100644
index 0000000..e0f41c8
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n7_pre.h
@@ -0,0 +1,24 @@
+#if defined(__MAUI_BASIC__)
+
+#if defined(__MD97__)
+    #include "basic_load/mt6297/cuif_u2c_isr_config_n7.h"
+#elif defined(__MD97P__)
+    #include "basic_load/mt6297p/cuif_u2c_isr_config_n7.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+
+#else
+
+    
+#if defined(__MD97__)
+    #include "mt6297/cuif_u2c_isr_config_n7.h"
+#elif defined(__MD97P__)
+    #include "mt6297p/cuif_u2c_isr_config_n7.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+    
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n8_pre.h b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n8_pre.h
new file mode 100644
index 0000000..4da734b
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n8_pre.h
@@ -0,0 +1,24 @@
+#if defined(__MAUI_BASIC__)
+
+#if defined(__MD97__)
+    #include "basic_load/mt6297/cuif_u2c_isr_config_n8.h"
+#elif defined(__MD97P__)
+    #include "basic_load/mt6297p/cuif_u2c_isr_config_n8.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+
+#else
+
+    
+#if defined(__MD97__)
+    #include "mt6297/cuif_u2c_isr_config_n8.h"
+#elif defined(__MD97P__)
+    #include "mt6297p/cuif_u2c_isr_config_n8.h"
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+    
+#endif
diff --git a/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n9_pre.h b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n9_pre.h
new file mode 100644
index 0000000..c046269
--- /dev/null
+++ b/mcu/interface/driver/devdrv/cuif/inc/cuif_u2c_isr_config_n9_pre.h
@@ -0,0 +1,28 @@
+#if defined(__MAUI_BASIC__)
+
+#if defined(__MD97__)
+    #include "basic_load/mt6297/cuif_u2c_isr_config_n9.h"
+
+#elif defined(__MD97P__)
+    #include "basic_load/mt6297p/cuif_u2c_isr_config_n9.h"
+
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+
+#else
+
+    
+#if defined(__MD97__)
+    #include "mt6297/cuif_u2c_isr_config_n9.h"
+
+#elif defined(__MD97P__)
+    #include "mt6297p/cuif_u2c_isr_config_n9.h"
+
+#else
+    #error "NOT support this arch!!!!"
+#endif
+
+    
+#endif
diff --git a/mcu/interface/driver/devdrv/d2d/inc/d2d_public.h b/mcu/interface/driver/devdrv/d2d/inc/d2d_public.h
new file mode 100644
index 0000000..4d2d6a0
--- /dev/null
+++ b/mcu/interface/driver/devdrv/d2d/inc/d2d_public.h
@@ -0,0 +1,22 @@
+#ifndef __D2D_PUBLIC_H__
+#define __D2D_PUBLIC_H__
+
+/*******************************************************************************
+ * Enum 
+ *******************************************************************************/
+
+typedef enum{
+    D2D_READ_INIT_CMD  = 0x128,
+    D2D_WRITE_INIT_CMD = 0x12c
+}D2D_RW_INIT_ENUM_T;
+
+/*******************************************************************************
+  * User-Aware MCU part API
+  *******************************************************************************/
+
+extern void d2d_init(void);
+extern void d2d_rwconfigure(D2D_RW_INIT_ENUM_T rw_config);
+extern void d2d_wreg32(kal_uint32 addr, kal_uint32 data);
+extern kal_uint32 d2d_rreg32(kal_uint32 addr);
+
+#endif
diff --git a/mcu/interface/driver/devdrv/dcm/dcm_sw.h b/mcu/interface/driver/devdrv/dcm/dcm_sw.h
new file mode 100644
index 0000000..8866d6c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/dcm/dcm_sw.h
@@ -0,0 +1,98 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   dcm_sw.h
+ *
+ * Project:
+ * --------
+ *   UMOLYE
+ *
+ * Description:
+ * ------------
+ *   This file defines DCM SW interface
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DCM_SW_H__
+#define __DCM_SW_H__
+
+#if defined(__MTK_TARGET__)
+
+  #if defined(__MD93__)
+      #include "dcm_sw_gen93.h"
+  #elif defined(__MD95__)
+      #include "dcm_sw_gen95.h"     
+  #elif defined(__MD97__)
+      #include "dcm_sw_gen97.h"   
+  #elif defined(__MD97P__)
+      #include "dcm_sw_gen97p.h"       
+  #else
+      #error "ERROR in DCM_SW define (dcm_sw.h)"
+  #endif
+
+#endif /* __MTK_TARGET__ */ 
+
+#endif /* __DCM_SW_H__ */
diff --git a/mcu/interface/driver/devdrv/dcm/dcm_sw_gen93.h b/mcu/interface/driver/devdrv/dcm/dcm_sw_gen93.h
new file mode 100644
index 0000000..6fb2aa4
--- /dev/null
+++ b/mcu/interface/driver/devdrv/dcm/dcm_sw_gen93.h
@@ -0,0 +1,139 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   dcm_sw.h
+ *
+ * Project:
+ * --------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   This file defines DCM SW interface
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DCM_SW_GEN93_H__
+#define __DCM_SW_GEN93_H__
+
+#if defined(__MTK_TARGET__)
+
+typedef enum {
+    DCM_IA_DCM_OFF,
+    DCM_IA_DCM_ONLY_CLK_DISABLE,
+    DCM_IA_DCM_MEMSLP_AND_CLK_DISABLE,        
+} DCM_IA_DCM_CONTROL_MODE;
+
+typedef enum {
+    DCM_LOCK_UNLOCK_MODULE_AT_COMMAND = 0,
+    DCM_LOCK_UNLOCK_MODULE_END,        
+} DCM_LOCK_UNLOCK_MODULE;
+
+/* DCM procedure to be executed in idle task */
+void DCM_Init( void );
+
+/* General DCM lock/unlock interface */
+kal_bool DCM_Query_Status(void);
+void DCM_SW_Lock(DCM_LOCK_UNLOCK_MODULE module);
+void DCM_SW_Unlock(DCM_LOCK_UNLOCK_MODULE module);
+
+void DCM_IA_DCM_Control(kal_bool enable, DCM_IA_DCM_CONTROL_MODE mode);
+void DCM_IA_DCM_Core1_Memslp_Path_Control(kal_bool enable);
+
+/* For LPM debugging */
+void DCM_Service_Change_LPM_Setting(kal_bool lpm_32K, kal_uint32 ext_src_sel, kal_uint32 src_sel);
+
+/* --------- Below Function nouse, for backward compatible. */
+kal_uint8 DCM_GetHandle(void);
+void DCM_Enable(kal_uint8 handle);
+void DCM_Disable(kal_uint8 handle);
+/* --------- Above Function nouse, for backward compatible. */
+
+#if defined(__MAUI_BASIC__)/* Disable DCM function on BASIC load for bring up. */
+//#define DCM_SUPPORT
+#else/* Enable DCM function on other load. */
+#define DCM_SUPPORT
+#endif
+
+//#define DCM_LPM_ENABLE /* Not supported in official load!! */
+
+#endif /* __MTK_TARGET__ */ 
+
+#endif /* __DCM_SW_GEN93_H__ */
diff --git a/mcu/interface/driver/devdrv/dcm/dcm_sw_gen95.h b/mcu/interface/driver/devdrv/dcm/dcm_sw_gen95.h
new file mode 100644
index 0000000..ca699e5
--- /dev/null
+++ b/mcu/interface/driver/devdrv/dcm/dcm_sw_gen95.h
@@ -0,0 +1,152 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   dcm_sw.h
+ *
+ * Project:
+ * --------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   This file defines DCM SW interface
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DCM_SW_GEN95_H__
+#define __DCM_SW_GEN95_H__
+
+#if defined(__MTK_TARGET__)
+
+typedef enum {
+    DCM_Lv2_IA_DCM_OFF = 0,
+    DCM_Lv2_IA_DCM_ONLY_CLK_DISABLE,
+    DCM_Lv2_IA_DCM_MEMSLP_AND_CLK_DISABLE,        
+} DCM_Lv2_IA_DCM_CONTROL_MODE;
+
+typedef enum {    
+    DCM_Lv3_IA_DCM_IMG_PATH = 0,
+    DCM_Lv3_IA_DCM_MTK_PATH = 1,     
+} DCM_Lv3_IA_DCM_CONTROL_PATH;
+
+typedef enum {    
+    DCM_Lv3_SFU_DCM = 0,
+    DCM_Lv3_SPU_DCM = 1, 
+    DCM_Lv3_SFU_SPU_WRAPPER_DCM = 2,
+    DCM_Lv3_SFU_SPU_ALL_DCM = 3    
+} DCM_Lv3_SFU_SPU_DCM_CONTROL;
+
+typedef enum {
+    DCM_LOCK_UNLOCK_MODULE_AT_COMMAND = 0,
+    DCM_LOCK_UNLOCK_MODULE_END,        
+} DCM_LOCK_UNLOCK_MODULE;
+
+/* DCM procedure to be executed in idle task */
+void DCM_Init( void );
+
+/* General DCM lock/unlock interface */
+kal_bool DCM_Query_Status(void);
+void DCM_SW_Lock(DCM_LOCK_UNLOCK_MODULE module);
+void DCM_SW_Unlock(DCM_LOCK_UNLOCK_MODULE module);
+
+void DCM_Lv2_IA_DCM_Control(kal_bool enable, DCM_Lv2_IA_DCM_CONTROL_MODE mode);
+void DCM_Lv2_IA_DCM_Core_Memslp_Path_Control(kal_bool enable, kal_uint32 core_id);
+void DCM_Lv2_IA_DCM_Mask_WakeUp_Source_In_GCR();
+void DCM_Lv3_SFU_SPU_DCM_Control(DCM_Lv3_SFU_SPU_DCM_CONTROL module, kal_bool enable);
+void DCM_Lv3_IA_DCM_Control(kal_bool enable, DCM_Lv3_IA_DCM_CONTROL_PATH path);
+
+/* For debugging only. */
+void DCM_Lv3_IA_CM2_DCM_Mon_Control(kal_bool enable);
+void DCM_Lv3_IA_CM2_DCM_Mon_Reset();
+kal_uint32 DCM_Lv3_IA_CM2_DCM_Mon_Status_Get();
+void DCM_Lv3_IA_CORE_DCM_Mon_Control(kal_bool enable);
+void DCM_Lv3_IA_CORE_DCM_Mon_Reset();
+kal_uint32 DCM_Lv3_IA_CORE_DCM_Mon_Status_Get();
+
+/* For LPM debugging */
+void DCM_Service_Change_LPM_Setting(kal_bool lpm_32K, kal_uint32 ext_src_sel, kal_uint32 src_sel);
+
+#if defined(__MAUI_BASIC__)/* Disable DCM function on BASIC load for bring up. */
+//#define DCM_SUPPORT
+#else/* Enable DCM function on other load. */
+#define DCM_SUPPORT
+#endif
+
+//#define DCM_LPM_ENABLE /* Not supported in official load!! */
+
+#endif /* __MTK_TARGET__ */ 
+
+#endif /* __DCM_SW_GEN95_H__ */
diff --git a/mcu/interface/driver/devdrv/dcm/dcm_sw_gen97.h b/mcu/interface/driver/devdrv/dcm/dcm_sw_gen97.h
new file mode 100644
index 0000000..112bef0
--- /dev/null
+++ b/mcu/interface/driver/devdrv/dcm/dcm_sw_gen97.h
@@ -0,0 +1,167 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   dcm_sw_gen97.h
+ *
+ * Project:
+ * --------
+ *   UMOLYE
+ *
+ * Description:
+ * ------------
+ *   This file defines DCM SW interface
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DCM_SW_GEN97_H__
+#define __DCM_SW_GEN97_H__
+
+#if defined(__MTK_TARGET__)
+
+typedef enum {
+    DCM_Lv2_SHAOLIN_DCM_OFF = 0,
+    DCM_Lv2_SHAOLIN_DCM_ONLY_CLK_DISABLE,
+    DCM_Lv2_SHAOLIN_DCM_MEMSLP_AND_CLK_DISABLE,        
+} DCM_Lv2_SHAOLIN_DCM_CONTROL_MODE;
+
+typedef enum {    
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY0 = 0,
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY1,
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY2,
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY3,
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY4,
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY5,
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY6,
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY7,    
+} DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY;
+
+typedef enum {    
+    DCM_Lv3_SFU_DCM = 0,
+    DCM_Lv3_SPU_DCM = 1, 
+    DCM_Lv3_SFU_SPU_WRAPPER_DCM = 2,
+    DCM_Lv3_SFU_SPU_ALL_DCM = 3    
+} DCM_Lv3_SFU_SPU_DCM_CONTROL;
+
+typedef enum {
+    DCM_LOCK_UNLOCK_MODULE_AT_COMMAND = 0,
+    DCM_LOCK_UNLOCK_MODULE_END,        
+} DCM_LOCK_UNLOCK_MODULE;
+
+/* DCM procedure to be executed in idle task */
+void DCM_Init( void );
+
+/* General DCM lock/unlock interface */
+kal_bool DCM_Query_Status(void);
+void DCM_SW_Lock(DCM_LOCK_UNLOCK_MODULE module);
+void DCM_SW_Unlock(DCM_LOCK_UNLOCK_MODULE module);
+
+void DCM_Lv2_SHAOLIN_DCM_Control(kal_bool enable, DCM_Lv2_SHAOLIN_DCM_CONTROL_MODE mode);
+void DCM_Lv2_SHAOLIN_DCM_Core_Memslp_Path_Control(kal_bool enable, kal_uint32 core_id);
+void DCM_Lv2_SHAOLIN_DCM_Lv2Cache_Memslp_Control(kal_bool enable, DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY way);
+void DCM_Lv2_SHAOLIN_DCM_Mask_WakeUp_Source_In_GCR();
+void DCM_Lv3_SFU_SPU_DCM_Control(DCM_Lv3_SFU_SPU_DCM_CONTROL module, kal_bool enable);
+void DCM_Lv3CACHE_DCM_Control(kal_bool enable);
+void DCM_Lv3_SHAOLIN_DCM_Control(kal_bool enable);
+
+/* For debugging only. */
+void DCM_Lv3_SHAOLIN_CM2_DCM_Mon_Control(kal_bool enable);
+void DCM_Lv3_SHAOLIN_CM2_DCM_Mon_Reset();
+kal_uint32 DCM_Lv3_SHAOLIN_CM2_DCM_Mon_Status_Get();
+void DCM_Lv3_SHAOLIN_CORE_DCM_Mon_Control(kal_bool enable);
+void DCM_Lv3Cache_DCM_Mon_Reset();
+kal_uint32 DCM_Lv3_SHAOLIN_CORE_DCM_Mon_Status_Get();
+void DCM_Lv3_SHAOLIN_CORE_DCM_Mon_Reset();
+kal_uint32 DCM_Lv3Cache_DCM_Mon_Status_Get();
+
+/* For LPM debugging */
+void LPM_Init(void);
+void LPM_Start(void);
+void LPM_Stop(void);
+void LPM_Print_and_Update_Setting(kal_uint32 vpe_id, kal_uint32 OST_ReadyToSlept);
+void LPM_Change_Setting(kal_bool lpm_32K, kal_uint32 ext_src_sel, kal_uint32 src_sel);
+
+#if defined(__MAUI_BASIC__)/* Disable DCM function on BASIC load for bring up. */
+//#define DCM_SUPPORT
+#else/* Enable DCM function on other load. */
+#define DCM_SUPPORT
+#endif
+
+//#define LV2_DCM_MEMSLP_ENABLE /* Disable it to avoid IOCU access 5us delay and reduce coding effort */
+
+//#define DCM_LPM_ENABLE /* Not supported in official load!! */
+
+#endif /* __MTK_TARGET__ */ 
+
+#endif /* __DCM_SW_GEN97_H__ */
diff --git a/mcu/interface/driver/devdrv/dcm/dcm_sw_gen97p.h b/mcu/interface/driver/devdrv/dcm/dcm_sw_gen97p.h
new file mode 100644
index 0000000..f9ea7d0
--- /dev/null
+++ b/mcu/interface/driver/devdrv/dcm/dcm_sw_gen97p.h
@@ -0,0 +1,148 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   dcm_sw_gen97p.h
+ *
+ * Project:
+ * --------
+ *   VMOLY
+ *
+ * Description:
+ * ------------
+ *   This file defines DCM SW interface
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DCM_SW_GEN97P_H__
+#define __DCM_SW_GEN97P_H__
+
+#if defined(__MTK_TARGET__)
+
+typedef enum {
+    DCM_Lv2_SHAOLIN_DCM_OFF = 0,
+    DCM_Lv2_SHAOLIN_DCM_ONLY_CLK_DISABLE,
+    DCM_Lv2_SHAOLIN_DCM_MEMSLP_AND_CLK_DISABLE,        
+} DCM_Lv2_SHAOLIN_DCM_CONTROL_MODE;
+
+typedef enum {    
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY0 = 0,
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY1,
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY2,
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY3,
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY4,
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY5,
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY6,
+    DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY7,    
+} DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY;
+
+typedef enum {    
+    DCM_Lv3_SFU_DCM = 0,
+    DCM_Lv3_SPU_DCM = 1, 
+    DCM_Lv3_SFU_SPU_WRAPPER_DCM = 2,
+    DCM_Lv3_SFU_SPU_ALL_DCM = 3    
+} DCM_Lv3_SFU_SPU_DCM_CONTROL;
+
+typedef enum {
+    DCM_LOCK_UNLOCK_MODULE_AT_COMMAND = 0,
+    DCM_LOCK_UNLOCK_MODULE_END,        
+} DCM_LOCK_UNLOCK_MODULE;
+
+/* DCM procedure to be executed in idle task */
+void DCM_Init( void );
+
+/* General DCM lock/unlock interface */
+kal_bool DCM_Query_Status(void);
+void DCM_SW_Lock(DCM_LOCK_UNLOCK_MODULE module);
+void DCM_SW_Unlock(DCM_LOCK_UNLOCK_MODULE module);
+
+void DCM_Lv2_SHAOLIN_DCM_Control(kal_bool enable, DCM_Lv2_SHAOLIN_DCM_CONTROL_MODE mode);
+void DCM_Lv2_SHAOLIN_DCM_Core_Memslp_Path_Control(kal_bool enable, kal_uint32 core_id);
+void DCM_Lv2_SHAOLIN_DCM_Lv2Cache_Memslp_Control(kal_bool enable, DCM_Lv2_SHAOLIN_DCM_Lv2CACHE_WAY way);
+void DCM_Lv2_SHAOLIN_DCM_Mask_WakeUp_Source_In_GCR();
+void DCM_Lv3_SFU_SPU_DCM_Control(DCM_Lv3_SFU_SPU_DCM_CONTROL module, kal_bool enable);
+void DCM_Lv3CACHE_DCM_Control(kal_bool enable);
+void DCM_Lv3_SHAOLIN_DCM_Control(kal_bool enable);
+
+/* For debugging only. */
+void DCM_Lv3_SHAOLIN_CM2_DCM_Mon_Control(kal_bool enable);
+void DCM_Lv3_SHAOLIN_CM2_DCM_Mon_Reset();
+kal_uint32 DCM_Lv3_SHAOLIN_CM2_DCM_Mon_Status_Get();
+void DCM_Lv3_SHAOLIN_CORE_DCM_Mon_Control(kal_bool enable);
+void DCM_Lv3Cache_DCM_Mon_Reset();
+kal_uint32 DCM_Lv3_SHAOLIN_CORE_DCM_Mon_Status_Get();
+void DCM_Lv3_SHAOLIN_CORE_DCM_Mon_Reset();
+kal_uint32 DCM_Lv3Cache_DCM_Mon_Status_Get();
+
+/* For LPM debugging */
+void LPM_Init(void);
+void LPM_Start(void);
+void LPM_Stop(void);
+void LPM_Print_and_Update_Setting(kal_uint32 vpe_id, kal_uint32 OST_ReadyToSlept);
+void LPM_Change_Setting(kal_bool lpm_32K, kal_uint32 ext_src_sel, kal_uint32 src_sel);
+
+#if defined(__MAUI_BASIC__)/* Disable DCM function on BASIC load for bring up. */
+//#define DCM_SUPPORT
+#else/* Enable DCM function on other load. */
+//#define DCM_SUPPORT
+#endif
+
+//#define LV2_DCM_MEMSLP_ENABLE /* Disable it to avoid IOCU access 5us delay and reduce coding effort */
+
+//#define DCM_LPM_ENABLE /* Not supported in official load!! */
+
+#endif /* __MTK_TARGET__ */ 
+
+#endif /* __DCM_SW_GEN97P_H__ */
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_bus_ao_public.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_bus_ao_public.h
new file mode 100644
index 0000000..1f34068
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_bus_ao_public.h
@@ -0,0 +1,27 @@
+#ifndef __DIGRF_BUS_AO_PUBLIC_H__
+#define __DIGRF_BUS_AO_PUBLIC_H__
+#if defined(__MD97__) || defined(__MD97P__)
+#define DIGRF_BUS_AO_HANGED_HEADER_MASK     (0xFF000000)
+#define DIGRF_BUS_AO_HANGED_HEADER          (0x99000000)
+
+typedef enum {
+	DIGRF_BUS_AO_BUSMON_SIMPLE_MODE     = ((0x1 << 0)),
+	DIGRF_BUS_AO_BUSMON_WRITE_MODE      = ((0x1 << 0) | (0x1 << 1)),
+	DIGRF_BUS_AO_BUSMON_READ_MODE       = ((0x1 << 0) | (0x1 << 2)),
+	DIGRF_BUS_AO_BUSMON_READ_WRITE_MODE = ((0x1 << 0) | (0x1 << 1) | (0x1 << 2)),
+	DIGRF_BUS_AO_BUSMON_MODE_LIMIT
+}DIGRF_BUS_AO_BUSMON_MODE_ENUM;
+
+typedef enum {
+	DIGRF_BUS_AO_BUSMON_READ_TRANSACTION 	= 0,
+	DIGRF_BUS_AO_BUSMON_WRITE_TRANSACTION 	= 1,
+	DIGRF_BUS_AO_BUSMON_TRANSACTION_TYPE_LIMIT
+}DIGRF_BUS_AO_BUSMON_TRANSACTION_ENUM;
+
+extern void DIGRF_BUS_AO_Init(void);
+extern void digrf_bus_ao_set_busmon_mode(DIGRF_BUS_AO_BUSMON_MODE_ENUM mode);
+extern void digrf_bus_ao_set_busmon_addr_data(DIGRF_BUS_AO_BUSMON_TRANSACTION_ENUM rw, kal_uint32 addr, kal_uint32 data);
+extern void digrf_bus_ao_set_busmon_addr_data_mask(DIGRF_BUS_AO_BUSMON_TRANSACTION_ENUM rw, kal_uint32 addr_mask, kal_uint32 data_mask);
+#endif //__MD97__
+
+#endif //__DIGRF_BUS_AO_PUBLIC_H__
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_bus_off_public.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_bus_off_public.h
new file mode 100644
index 0000000..945b0cb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_bus_off_public.h
@@ -0,0 +1,15 @@
+#ifndef __DIGRF_BUS_OFF_PUBLIC_H__
+#define __DIGRF_BUS_OFF_PUBLIC_H__
+
+#if defined(__MD97__) || defined(__MD97P__)
+#include "digrf_off_dbgmon_public.h"
+extern void DIGRF_BUS_OFF_Init(void);
+extern void DIGRF_BUS_OFF_Disable_to_AO_Path(void);
+extern void DIGRF_BUS_OFF_Enable_to_AO_Path(void);
+extern kal_uint32 DIGRF_BUS_OFF_Get_Bus_Off_Idle_Status(void);
+
+extern kal_uint32 DIGRF_BUS_OFF_Get_Bus_Status(DIGRF_DBGMON_STATUS status);
+
+#endif //__MD97__
+
+#endif //__DIGRF_BUS_OFF_PUBLIC_H__
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_busmon_public.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_busmon_public.h
new file mode 100644
index 0000000..85d0fd5
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_busmon_public.h
@@ -0,0 +1,276 @@
+#ifndef __DIGRF_BUSMON_PUBLIC_H__
+#define __DIGRF_BUSMON_PUBLIC_H__
+
+
+
+#include "digrf_platform_public.h"
+
+/*
+ * Busmon bus id
+ */
+typedef enum {
+   /* MD INFRA */
+   BUSMON_BUSID_COS_MST = 0,
+   BUSMON_BUSID_COS_SLV = 2,
+   BUSMON_BUSID_RXDFE_AXI = 3
+} digrf_busmon_busid_t;  
+
+typedef enum {
+   BUSMON_MON_DISABLE,
+   BUSMON_MON_ENABLE
+} digrf_drv_busmon_active_t;
+
+typedef enum {
+   BUSMON_MON_STATE_INACTIVE,
+   BUSMON_MON_STATE_ACTIVE
+} digrf_drv_busmon_mon_state_t;
+
+/* Busmon internal IP */
+typedef enum {
+   BUSMON_IP0,
+   BUSMON_IP1,
+
+   BUSMON_IP_MAX
+} digrf_drv_busmon_ip_t;
+
+/* Busmon IP status */
+typedef enum {
+   IP_IDLE = 0,
+   IP_REAL_ENABLE = 1,
+   IP_STOP = 2,
+} digrf_busmon_ip_status_t;
+
+/* AXImon Read/Write Selection */
+typedef enum {
+   AXIMON_RWSEL_WRITE=0,
+   AXIMON_RWSEL_READ=1,
+
+   AXIMON_RWSEL_MAX
+} digrf_drv_aximon_rwsel_t;
+
+typedef enum {
+   START_ORDER_IP0_IP1=0,
+   STOP_ORDER_IP0_IP1=1,
+   ORDER_IP0_IP1_MAX=2   
+} digrf_drv_busmon_mon_seq_check_mode_t;
+
+
+/*
+ * Busmon Target Monitor Mode
+ */
+typedef enum {
+   BUSMON_TG_MON_MODE_SNAP,
+   BUSMON_TG_MON_MODE_MONITOR,
+
+   BUSMON_TG_MON_MODE_MAX
+} digrf_drv_busmon_tg_mon_mode_t;
+
+/* Busmon Trigger Mode */
+typedef enum {
+   BUSMON_TRG_ADDRDATA,                 /* Address & Data Trigger */
+   BUSMON_TRG_CYCLE,                    /* Cycle Trigger */
+
+   BUSMON_TRG_MAX
+} digrf_drv_busmon_trg_mode_t;
+
+
+typedef enum {
+  COS_MST_M_MIPI =0,
+  COS_MST_M_DSB_H =1,
+  COS_MST_M_DSB_L =5,
+  COS_MST_COS_0 =2,
+  COS_MST_COS_1 =6
+  
+} digrf_cos_mst_m_id_t;
+
+
+typedef enum {
+  COS_MST_S_OTHERS,
+  COS_MST_S_RXDFE_H624M,
+  COS_MST_S_RXDFE_H312M_1,
+  COS_MST_S_RXDFE_H312M_2,
+  COS_MST_S_TXDFE,
+  COS_MST_S_TXK_CORE,
+  COS_MST_S_TPC,
+  COS_MST_S_EVT_GEN,
+  COS_MST_S_MIPI_RFFE,
+  COS_MST_S_OFF2A0,
+  COS_MST_S_APC,
+  COS_MST_S_DVT,
+  COS_MST_S_MIXEDSYS,
+  COS_MST_S_BSI,
+  COS_MST_S_DSB
+} digrf_cos_mst_s_id_t;
+
+
+
+typedef enum {
+    DIGRF_BUSREC_MODE_NORMAL = 0,
+    DIGRF_BUSREC_MODE_TEST = 1,
+} DIGRF_BUSREC_MODE;
+
+typedef enum {
+    DIGRF_BUSREC_GATE_NONE,
+    DIGRF_BUSREC_GATE_RESP,
+    DIGRF_BUSREC_GATE_CMD,
+    DIGRF_BUSREC_GATE_ALL,
+} DIGRF_BUSREC_GATE;
+
+typedef enum {
+    BUSREC_TYPE_WR,
+    BUSREC_TYPE_RD,
+    BUSREC_TYPE_MAX,
+} DIGRF_DIGRF_BUSREC_REC_TYPE;
+
+typedef enum {
+    DIGRF_BUSREC_RET_OK = 0,
+    DIGRF_BUSREC_RET_FAIL = -1,
+    DIGRF_BUSREC_RET_NOT_SUPPORTED = -2,
+    DIGRF_BUSREC_RET_INVALID_PARAMETER = -3,
+    DIGRF_BUSREC_RET_STARTED = -4,
+} DIGRF_BUSREC_RET;
+
+typedef enum {
+    BUSREC_START_AXVALID = 0,
+    BUSREC_START_AXVALID_AXREADY = 1,
+} DIGRF_BUSREC_STA_SEL;
+//--------------------------
+// Above for Bus Recorder
+//-------------------------
+
+
+/*******************************************************************************
+ * Define data structures.
+ *******************************************************************************/
+/* AXImon IP configuration of Monitor mode */
+typedef struct {
+   digrf_drv_aximon_rwsel_t rwsel;
+   kal_uint32 master_id;          /* specific transaction ID */
+   kal_uint32 master_id_mask;
+   kal_uint32 vpe_id;          /* specific VPE ID */
+   kal_uint32 vpe_id_mask;  
+   kal_uint32 ultra;          /* specific ULTRA */
+   kal_uint32 ultra_mask;    
+   kal_uint32 axlen ;     /* specific AxLEN */
+   kal_uint32 axlen_mask ;
+   kal_uint32 axsize ;      /* specific AxSIZE */ 
+   kal_uint32 axsize_mask ;
+   kal_bool all_master_enable;   /* any transaction ID */
+   kal_uint32 addr;              /* address */
+   kal_uint32 addr_mask;         /* address mask, 0: check, 1: ignore */
+   kal_bool   data_enable;   /* data target check at counting snap count */    
+   kal_uint32 data;          /* data 0 32-bit of bus width */
+   kal_uint32 data_mask;     /* data 0 mask 0: check, 1: ignore */   
+   kal_bool   cnt_wrap_en;
+} digrf_drv_aximon_mon_config_t;
+
+/* Configuration of Snapshot Mode */
+typedef struct {
+   digrf_drv_aximon_rwsel_t rwsel;
+   kal_uint32 master_id;          /* specific transaction ID */
+   kal_uint32 master_id_mask;
+   kal_uint32 vpe_id;          /* specific VPE ID */
+   kal_uint32 vpe_id_mask;   
+   kal_uint32 ultra;          /* specific ULTRA */
+   kal_uint32 ultra_mask;   
+   kal_uint32 axlen ;		  /* specific AxLEN */
+   kal_uint32 axlen_mask ;
+   kal_uint32 axsize ;		  /* specific AxSIZE */	
+   kal_uint32 axsize_mask ;
+   kal_bool all_master_enable;   /* ALL Master should only use in Monitor mode */
+   digrf_drv_busmon_trg_mode_t trg_mode;  /* trigger mode */
+   kal_uint32 addr;              /* address */
+   kal_uint32 addr_mask;         /* address mask, 0: check, 1: ignore */
+   kal_bool   data_enable;   /* data target check at counting snap count */   
+   kal_uint32 data;          /* data 0 32-bit of bus width */
+   kal_uint32 data_mask;     /* data 0 mask 0: check, 1: ignore */
+   kal_uint32 mon_cnt;           /* count select */ 
+   kal_uint32 cycle_cnt;         /* max cycle */    
+   kal_bool ost64_mode_enable;
+} digrf_drv_aximon_snp_config_t;
+
+/* Configuration of Trigger Mode */
+typedef struct {
+   kal_bool enable_seq_trg; /* TRUE==> sequencial mode, FALSE==> Concurrent mode */
+   digrf_drv_busmon_ip_t trigger_ip; /* Only use in Concurrent mode, determine which IP would trigger interrupt */   
+   digrf_drv_busmon_mon_seq_check_mode_t seq_check_mode; /* START_ORDER_IP0_IP1/STOP_ORDER_IP0_IP1 */   
+   digrf_drv_aximon_snp_config_t ip[BUSMON_IP_MAX];
+} digrf_drv_aximon_trg_config_t;
+
+/* Configuration of Moitor/Snapshot Hybrid Mode */
+typedef struct {
+   digrf_drv_busmon_ip_t mon_ip;
+   digrf_drv_aximon_mon_config_t mon;
+   digrf_drv_aximon_snp_config_t snp;
+} digrf_drv_aximon_hyb_config_t;
+
+/* Monitor Mode: Read-related informatin */
+typedef struct {
+   kal_uint32 QID;
+   kal_uint32 tot_bus_cyc;
+   kal_uint32 non_ov_trans_num;
+   kal_uint32 ov_trans_num;
+   kal_uint32 non_wgt_trans_cyc;
+   kal_uint32 wgt_trans_cyc;
+   kal_uint32 max_trans_cyc;
+   kal_uint32 max_ost_trans_num;
+   kal_uint32 cur_ost_trans_num;
+} digrf_drv_aximon_mon_transaction_info_t;
+
+/* Snapshot Mode */
+typedef struct {
+   kal_uint32 info0;
+   kal_uint32 info1;
+   kal_uint32 info2;
+   kal_uint32 info3;
+   kal_uint32 info4;
+   kal_uint32 info5;
+   kal_uint32 info6;
+   kal_uint32 info7;
+   kal_uint32 info8;
+   kal_uint32 info9;
+   kal_uint32 info10;
+   kal_uint32 info11;
+   kal_uint32 info12;
+   kal_uint32 hw_intr_frc;
+} digrf_drv_aximon_snp_info_t;
+
+/* Sequential Mode: */
+typedef struct {
+   digrf_drv_aximon_snp_info_t ip[BUSMON_IP_MAX];
+} digrf_drv_aximon_trg_info_t;
+
+
+//--------------------------
+// Below for Bus Recorder
+//-------------------------
+
+
+/*******************************************************************************
+ * Define Macros.
+ *******************************************************************************/
+/* Register field manipulation macro */
+#define DIGRF_EXTRACT_REG_FIELD_VAL(field_val, field_name) (((field_val) >> (field_name##_SHIFT)) & (field_name##_MASK))
+#define DIGRF_EXPAND_REG_FIELD_VAL(field_val, field_name) (((field_val) & (field_name##_MASK)) << (field_name##_SHIFT))
+#define DIGRF_CLEAR_REG_FIELD(reg_val, field_name) ((reg_val) & (~((field_name##_MASK) << (field_name##_SHIFT))))
+#define DIGRF_SET_REG_FIELD_VAL(reg_val, field_val, field_name) (DIGRF_CLEAR_REG_FIELD(reg_val, field_name) | DIGRF_EXPAND_REG_FIELD_VAL(field_val, field_name))
+
+void digrf_aximon_init(void);
+void digrf_aximon_deinit(void);
+void digrf_aximon_set_busid(digrf_busmon_busid_t id);
+void digrf_aximon_set_monitor(digrf_drv_busmon_ip_t mon_ip,digrf_drv_aximon_mon_config_t* config);
+void digrf_aximon_enable_interrupt(void);
+void digrf_aximon_get_ip_transaction_info(digrf_drv_busmon_ip_t mon_ip, digrf_drv_aximon_mon_transaction_info_t *info);
+void digrf_aximon_set_snap(digrf_drv_busmon_ip_t mon_ip, digrf_drv_aximon_snp_config_t *config);
+void digrf_aximon_get_snap_info(digrf_drv_busmon_ip_t mon_ip, digrf_drv_aximon_snp_info_t *info);
+void digrf_aximon_polling_IP_Real_Enable(digrf_drv_busmon_ip_t mon_ip);
+
+
+
+
+void config_digrf_aximon_snap_mode(digrf_drv_busmon_ip_t mon_ip, digrf_busmon_busid_t bus_id, digrf_drv_aximon_rwsel_t rw,kal_uint32 addr, kal_uint32 addr_mask,kal_uint32 data, kal_uint32 data_mask,kal_uint32 master_id,kal_uint32 master_id_mask);
+void config_digrf_aximon_mntr_mode(digrf_drv_busmon_ip_t mon_ip, digrf_busmon_busid_t bus_id, digrf_drv_aximon_rwsel_t rw,kal_uint32 addr, kal_uint32 addr_mask,kal_uint32 data, kal_uint32 data_mask,kal_uint32 master_id,kal_uint32 master_id_mask);
+void DIGRF_AXIMON_Init(void);
+void digrf_aximon_stop(void);
+void digrf_aximon_start(void);
+#endif
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_cos_prep_public.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_cos_prep_public.h
new file mode 100644
index 0000000..5b2a842
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_cos_prep_public.h
@@ -0,0 +1,9 @@
+#ifndef __DIGRF_COS_PREP_PUBLIC_H__
+#define __DIGRF_COS_PREP_PUBLIC_H__
+
+#if defined(__MD97__) || defined(__MD97P__)
+extern void DIGRF_COS_PREP_Init(void);
+
+#endif // __MD97__
+
+#endif //__DIGRF_COS_PREP_PUBLIC_H__
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_0_user_id.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_0_user_id.h
new file mode 100644
index 0000000..1758f4a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_0_user_id.h
@@ -0,0 +1,64 @@
+//DIGRF_D_GDMA_USER_ID(channel number, USER_ID, HW_TRIGGER )
+//HW_TRUGGERR: channel triggered by HW = 1  
+
+//normal user enum will be DIGRF_D_GDMA_NOR_ID_XXX
+//ex : DIGRF_D_GDMA_NOR_USER_ID(0, ABC, 0) will generate a enum
+//DGIRF_D_GDMA_NOR_ID_ABC.
+//debug user enum will be DIGRF_D_GDMA_DBG_ID_XXX
+//ex : DIGRF_D_GDMA_DBG_USER_ID(0, ABC, 0) will generate a enum
+//DGIRF_D_GDMA_DBG_ID_ABC.
+/**********************************************************/
+//Channel High part user id
+//RXDFE
+DIGRF_D_GDMA_0_H_USER_ID(0,     RXDFE_0)
+DIGRF_D_GDMA_0_H_USER_ID(1,     RXDFE_1)
+DIGRF_D_GDMA_0_H_USER_ID(2,     RXDFE_2)
+DIGRF_D_GDMA_0_H_USER_ID(3,     RXDFE_3)
+DIGRF_D_GDMA_0_H_USER_ID(4,     RXDFE_4)
+DIGRF_D_GDMA_0_H_USER_ID(5,     RXDFE_5)
+//RXAGC
+DIGRF_D_GDMA_0_H_USER_ID(6,     RXAGC_0)
+
+//Channel Low part user id
+//RXAGC
+DIGRF_D_GDMA_0_L_USER_ID(0,     RXAGC_0)
+DIGRF_D_GDMA_0_L_USER_ID(1,     RXAGC_1)
+DIGRF_D_GDMA_0_L_USER_ID(2,     RXAGC_2)
+DIGRF_D_GDMA_0_L_USER_ID(3,     RXAGC_3)
+DIGRF_D_GDMA_0_L_USER_ID(4,     RXAGC_4)
+DIGRF_D_GDMA_0_L_USER_ID(5,     RXAGC_5)
+DIGRF_D_GDMA_0_L_USER_ID(6,     RXAGC_6)
+DIGRF_D_GDMA_0_L_USER_ID(7,     RXAGC_7)
+DIGRF_D_GDMA_0_L_USER_ID(8,     RXAGC_8)
+DIGRF_D_GDMA_0_L_USER_ID(9,     RXAGC_9)
+DIGRF_D_GDMA_0_L_USER_ID(10,    RXAGC_10)
+DIGRF_D_GDMA_0_L_USER_ID(11,    RXAGC_11)
+DIGRF_D_GDMA_0_L_USER_ID(12,    RXAGC_12)
+DIGRF_D_GDMA_0_L_USER_ID(13,    RXAGC_13)
+DIGRF_D_GDMA_0_L_USER_ID(14,    RXAGC_14)
+DIGRF_D_GDMA_0_L_USER_ID(15,    RXAGC_15)
+DIGRF_D_GDMA_0_L_USER_ID(16,    RXAGC_16)
+DIGRF_D_GDMA_0_L_USER_ID(17,    RXAGC_17)
+DIGRF_D_GDMA_0_L_USER_ID(18,    RXAGC_18)
+DIGRF_D_GDMA_0_L_USER_ID(19,    RXAGC_19)
+DIGRF_D_GDMA_0_L_USER_ID(20,    RXAGC_20)
+DIGRF_D_GDMA_0_L_USER_ID(21,    RXAGC_21)
+DIGRF_D_GDMA_0_L_USER_ID(22,    RXAGC_22)
+DIGRF_D_GDMA_0_L_USER_ID(23,    RXAGC_23)
+DIGRF_D_GDMA_0_L_USER_ID(24,    RXAGC_24)
+DIGRF_D_GDMA_0_L_USER_ID(25,    RXAGC_25)
+DIGRF_D_GDMA_0_L_USER_ID(26,    RXAGC_26)
+DIGRF_D_GDMA_0_L_USER_ID(27,    RXAGC_27)
+DIGRF_D_GDMA_0_L_USER_ID(28,    RXAGC_28)
+DIGRF_D_GDMA_0_L_USER_ID(29,    RXAGC_29)
+DIGRF_D_GDMA_0_L_USER_ID(30,    RXAGC_30)
+DIGRF_D_GDMA_0_L_USER_ID(31,    RXAGC_31)
+//MIPI
+DIGRF_D_GDMA_0_L_USER_ID(32,    MIPI_0)
+DIGRF_D_GDMA_0_L_USER_ID(33,    MIPI_1)
+DIGRF_D_GDMA_0_L_USER_ID(34,    MIPI_2)
+DIGRF_D_GDMA_0_L_USER_ID(35,    MIPI_3)
+DIGRF_D_GDMA_0_L_USER_ID(36,    MIPI_4)
+DIGRF_D_GDMA_0_L_USER_ID(37,    MIPI_5)
+DIGRF_D_GDMA_0_L_USER_ID(38,    MIPI_6)
+DIGRF_D_GDMA_0_L_USER_ID(39,    MIPI_7)
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_1_user_id.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_1_user_id.h
new file mode 100644
index 0000000..373df1a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_1_user_id.h
@@ -0,0 +1,85 @@
+//DIGRF_D_GDMA_USER_ID(channel number, USER_ID, HW_TRIGGER )
+//HW_TRUGGERR: channel triggered by HW = 1  
+
+//normal user enum will be DIGRF_D_GDMA_NOR_ID_XXX
+//ex : DIGRF_D_GDMA_NOR_USER_ID(0, ABC, 0) will generate a enum
+//DGIRF_D_GDMA_NOR_ID_ABC.
+//debug user enum will be DIGRF_D_GDMA_DBG_ID_XXX
+//ex : DIGRF_D_GDMA_DBG_USER_ID(0, ABC, 0) will generate a enum
+//DGIRF_D_GDMA_DBG_ID_ABC.
+/**********************************************************/
+//Channel High part user id
+//RXDFE
+DIGRF_D_GDMA_1_H_USER_ID(0,     RXAGC_0)
+DIGRF_D_GDMA_1_H_USER_ID(0,     RXAGC_1)
+DIGRF_D_GDMA_1_H_USER_ID(0,     RXAGC_2)
+DIGRF_D_GDMA_1_H_USER_ID(0,     RXAGC_3)
+DIGRF_D_GDMA_1_H_USER_ID(0,     RXAGC_4)
+
+//Channel Low part user id
+//RXAGC
+DIGRF_D_GDMA_1_L_USER_ID(0,     RXAGC_0)
+DIGRF_D_GDMA_1_L_USER_ID(1,     RXAGC_1)
+DIGRF_D_GDMA_1_L_USER_ID(2,     RXAGC_2)
+DIGRF_D_GDMA_1_L_USER_ID(3,     RXAGC_3)
+DIGRF_D_GDMA_1_L_USER_ID(4,     RXAGC_4)
+DIGRF_D_GDMA_1_L_USER_ID(5,     RXAGC_5)
+DIGRF_D_GDMA_1_L_USER_ID(6,     RXAGC_6)
+DIGRF_D_GDMA_1_L_USER_ID(7,     RXAGC_7)
+DIGRF_D_GDMA_1_L_USER_ID(8,     RXAGC_8)
+DIGRF_D_GDMA_1_L_USER_ID(9,     RXAGC_9)
+DIGRF_D_GDMA_1_L_USER_ID(10,    RXAGC_10)
+DIGRF_D_GDMA_1_L_USER_ID(11,    RXAGC_11)
+DIGRF_D_GDMA_1_L_USER_ID(12,    RXAGC_12)
+DIGRF_D_GDMA_1_L_USER_ID(13,    RXAGC_13)
+DIGRF_D_GDMA_1_L_USER_ID(14,    RXAGC_14)
+DIGRF_D_GDMA_1_L_USER_ID(15,    RXAGC_15)
+DIGRF_D_GDMA_1_L_USER_ID(16,    RXAGC_16)
+DIGRF_D_GDMA_1_L_USER_ID(17,    RXAGC_17)
+DIGRF_D_GDMA_1_L_USER_ID(18,    RXAGC_18)
+DIGRF_D_GDMA_1_L_USER_ID(19,    RXAGC_19)
+DIGRF_D_GDMA_1_L_USER_ID(20,    RXAGC_20)
+DIGRF_D_GDMA_1_L_USER_ID(21,    RXAGC_21)
+DIGRF_D_GDMA_1_L_USER_ID(22,    RXAGC_22)
+DIGRF_D_GDMA_1_L_USER_ID(23,    RXAGC_23)
+DIGRF_D_GDMA_1_L_USER_ID(24,    RXAGC_24)
+DIGRF_D_GDMA_1_L_USER_ID(25,    RXAGC_25)
+DIGRF_D_GDMA_1_L_USER_ID(26,    RXAGC_26)
+DIGRF_D_GDMA_1_L_USER_ID(27,    RXAGC_27)
+DIGRF_D_GDMA_1_L_USER_ID(28,    RXAGC_28)
+DIGRF_D_GDMA_1_L_USER_ID(29,    RXAGC_29)
+DIGRF_D_GDMA_1_L_USER_ID(30,    RXAGC_30)
+DIGRF_D_GDMA_1_L_USER_ID(31,    RXAGC_31)
+DIGRF_D_GDMA_1_L_USER_ID(32,    RXAGC_32)
+DIGRF_D_GDMA_1_L_USER_ID(33,    RXAGC_33)
+DIGRF_D_GDMA_1_L_USER_ID(34,    RXAGC_34)
+DIGRF_D_GDMA_1_L_USER_ID(35,    RXAGC_35)
+DIGRF_D_GDMA_1_L_USER_ID(36,    RXAGC_36)
+DIGRF_D_GDMA_1_L_USER_ID(37,    RXAGC_37)
+DIGRF_D_GDMA_1_L_USER_ID(38,    RXAGC_38)
+DIGRF_D_GDMA_1_L_USER_ID(39,    RXAGC_39)
+DIGRF_D_GDMA_1_L_USER_ID(40,    RXAGC_40)
+DIGRF_D_GDMA_1_L_USER_ID(41,    RXAGC_41)
+DIGRF_D_GDMA_1_L_USER_ID(42,    RXAGC_42)
+DIGRF_D_GDMA_1_L_USER_ID(43,    RXAGC_43)
+DIGRF_D_GDMA_1_L_USER_ID(44,    RXAGC_44)
+DIGRF_D_GDMA_1_L_USER_ID(45,    RXAGC_45)
+DIGRF_D_GDMA_1_L_USER_ID(46,    RXAGC_46)
+DIGRF_D_GDMA_1_L_USER_ID(47,    RXAGC_47)
+DIGRF_D_GDMA_1_L_USER_ID(48,    RXAGC_48)
+DIGRF_D_GDMA_1_L_USER_ID(49,    RXAGC_49)
+DIGRF_D_GDMA_1_L_USER_ID(50,    RXAGC_50)
+DIGRF_D_GDMA_1_L_USER_ID(51,    RXAGC_51)
+//MIPI
+DIGRF_D_GDMA_1_L_USER_ID(52,    MIPI_0)
+DIGRF_D_GDMA_1_L_USER_ID(53,    MIPI_1)
+DIGRF_D_GDMA_1_L_USER_ID(54,    MIPI_2)
+DIGRF_D_GDMA_1_L_USER_ID(55,    MIPI_3)
+DIGRF_D_GDMA_1_L_USER_ID(56,    MIPI_4)
+DIGRF_D_GDMA_1_L_USER_ID(57,    MIPI_5)
+DIGRF_D_GDMA_1_L_USER_ID(58,    MIPI_6)
+DIGRF_D_GDMA_1_L_USER_ID(59,    MIPI_7)
+DIGRF_D_GDMA_1_L_USER_ID(60,    MIPI_8)
+DIGRF_D_GDMA_1_L_USER_ID(61,    MIPI_9)
+DIGRF_D_GDMA_1_L_USER_ID(62,    MIPI_10)
+DIGRF_D_GDMA_1_L_USER_ID(63,    MIPI_11)
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_2_user_id.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_2_user_id.h
new file mode 100644
index 0000000..9b37b20
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_2_user_id.h
@@ -0,0 +1,26 @@
+//DIGRF_D_GDMA_USER_ID(channel number, USER_ID, HW_TRIGGER )
+//HW_TRUGGERR: channel triggered by HW = 1  
+
+//normal user enum will be DIGRF_D_GDMA_NOR_ID_XXX
+//ex : DIGRF_D_GDMA_NOR_USER_ID(0, ABC, 0) will generate a enum
+//DGIRF_D_GDMA_NOR_ID_ABC.
+//debug user enum will be DIGRF_D_GDMA_DBG_ID_XXX
+//ex : DIGRF_D_GDMA_DBG_USER_ID(0, ABC, 0) will generate a enum
+//DGIRF_D_GDMA_DBG_ID_ABC.
+/**********************************************************/
+//Channel High part user id
+//TPC
+DIGRF_D_GDMA_2_H_USER_ID(0,     TPC_0)
+
+//Channel Low part user id
+DIGRF_D_GDMA_2_L_USER_ID(0,     TPC_0)
+DIGRF_D_GDMA_2_L_USER_ID(1,     TXDFE_0)
+DIGRF_D_GDMA_2_L_USER_ID(2,     TXDFE_1)
+DIGRF_D_GDMA_2_L_USER_ID(3,     TXDFE_2)
+DIGRF_D_GDMA_2_L_USER_ID(4,     TXDFE_3)
+DIGRF_D_GDMA_2_L_USER_ID(5,     TXDFE_4)
+DIGRF_D_GDMA_2_L_USER_ID(6,     TPC_1)
+DIGRF_D_GDMA_2_L_USER_ID(7,     TXK_0)
+DIGRF_D_GDMA_2_L_USER_ID(8,     TXK_1)
+DIGRF_D_GDMA_2_L_USER_ID(9,     TXK_2)
+DIGRF_D_GDMA_2_L_USER_ID(10,    TPC_2)
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_3_user_id.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_3_user_id.h
new file mode 100644
index 0000000..db0cead
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_3_user_id.h
@@ -0,0 +1,35 @@
+//DIGRF_D_GDMA_USER_ID(channel number, USER_ID, HW_TRIGGER )
+//HW_TRUGGERR: channel triggered by HW = 1  
+
+//normal user enum will be DIGRF_D_GDMA_NOR_ID_XXX
+//ex : DIGRF_D_GDMA_NOR_USER_ID(0, ABC, 0) will generate a enum
+//DGIRF_D_GDMA_NOR_ID_ABC.
+//debug user enum will be DIGRF_D_GDMA_DBG_ID_XXX
+//ex : DIGRF_D_GDMA_DBG_USER_ID(0, ABC, 0) will generate a enum
+//DGIRF_D_GDMA_DBG_ID_ABC.
+/**********************************************************/
+//Channel High part user id
+//TPC
+DIGRF_D_GDMA_3_H_USER_ID(0,     TPC_0)
+DIGRF_D_GDMA_3_H_USER_ID(1,     TPC_1)
+DIGRF_D_GDMA_3_H_USER_ID(2,     TPC_2)
+
+//Channel Low part user id
+DIGRF_D_GDMA_3_L_USER_ID(0,     TXDFE_0)
+DIGRF_D_GDMA_3_L_USER_ID(1,     TXDFE_1)
+DIGRF_D_GDMA_3_L_USER_ID(2,     TXDFE_2)
+DIGRF_D_GDMA_3_L_USER_ID(3,     TXDFE_3)
+DIGRF_D_GDMA_3_L_USER_ID(4,     TXDFE_4)
+DIGRF_D_GDMA_3_L_USER_ID(5,     TXDFE_5)
+DIGRF_D_GDMA_3_L_USER_ID(6,     TXDFE_6)
+DIGRF_D_GDMA_3_L_USER_ID(7,     TXDFE_7)
+DIGRF_D_GDMA_3_L_USER_ID(8,     TXDFE_8)
+DIGRF_D_GDMA_3_L_USER_ID(9,     TXDFE_9)
+DIGRF_D_GDMA_3_L_USER_ID(10,    TXDFE_10)
+DIGRF_D_GDMA_3_L_USER_ID(11,    TXDFE_11)
+DIGRF_D_GDMA_3_L_USER_ID(12,    TXDFE_12)
+DIGRF_D_GDMA_3_L_USER_ID(13,    TXDFE_13)
+DIGRF_D_GDMA_3_L_USER_ID(14,    TXDFE_14)
+DIGRF_D_GDMA_3_L_USER_ID(15,    TXDFE_15)
+DIGRF_D_GDMA_3_L_USER_ID(16,    TXDFE_16)
+DIGRF_D_GDMA_3_L_USER_ID(17,    TXDFE_17)
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_4_user_id.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_4_user_id.h
new file mode 100644
index 0000000..473ede0
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_4_user_id.h
@@ -0,0 +1,34 @@
+//DIGRF_D_GDMA_USER_ID(channel number, USER_ID, HW_TRIGGER )
+//HW_TRUGGERR: channel triggered by HW = 1  
+
+//normal user enum will be DIGRF_D_GDMA_NOR_ID_XXX
+//ex : DIGRF_D_GDMA_NOR_USER_ID(0, ABC, 0) will generate a enum
+//DGIRF_D_GDMA_NOR_ID_ABC.
+//debug user enum will be DIGRF_D_GDMA_DBG_ID_XXX
+//ex : DIGRF_D_GDMA_DBG_USER_ID(0, ABC, 0) will generate a enum
+//DGIRF_D_GDMA_DBG_ID_ABC.
+/**********************************************************/
+//Channel High part user id
+//TPC
+DIGRF_D_GDMA_4_H_USER_ID(0,     TPC_0)
+
+//Channel Low part user id
+DIGRF_D_GDMA_4_L_USER_ID(0,     TPC_0)
+DIGRF_D_GDMA_4_L_USER_ID(1,     TXDFE_0)
+DIGRF_D_GDMA_4_L_USER_ID(2,     TXDFE_1)
+DIGRF_D_GDMA_4_L_USER_ID(3,     TXDFE_2)
+DIGRF_D_GDMA_4_L_USER_ID(4,     TXDFE_3)
+DIGRF_D_GDMA_4_L_USER_ID(5,     TXDFE_4)
+DIGRF_D_GDMA_4_L_USER_ID(6,     TXDFE_5)
+DIGRF_D_GDMA_4_L_USER_ID(7,     TXDFE_6)
+DIGRF_D_GDMA_4_L_USER_ID(8,     TXDFE_7)
+DIGRF_D_GDMA_4_L_USER_ID(9,     TXDFE_8)
+DIGRF_D_GDMA_4_L_USER_ID(10,    TXDFE_9)
+DIGRF_D_GDMA_4_L_USER_ID(11,    TXDFE_10)
+DIGRF_D_GDMA_4_L_USER_ID(12,    TXDFE_11)
+DIGRF_D_GDMA_4_L_USER_ID(13,    TXDFE_12)
+DIGRF_D_GDMA_4_L_USER_ID(14,    TXDFE_13)
+DIGRF_D_GDMA_4_L_USER_ID(15,    TXDFE_14)
+DIGRF_D_GDMA_4_L_USER_ID(16,    TXDFE_15)
+DIGRF_D_GDMA_4_L_USER_ID(17,    TXDFE_16)
+DIGRF_D_GDMA_4_L_USER_ID(18,    TXDFE_17)
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_5_user_id.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_5_user_id.h
new file mode 100644
index 0000000..4b91089
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_5_user_id.h
@@ -0,0 +1,81 @@
+//DIGRF_D_GDMA_USER_ID(channel number, USER_ID, HW_TRIGGER )
+//HW_TRUGGERR: channel triggered by HW = 1  
+
+//normal user enum will be DIGRF_D_GDMA_NOR_ID_XXX
+//ex : DIGRF_D_GDMA_NOR_USER_ID(0, ABC, 0) will generate a enum
+//DGIRF_D_GDMA_NOR_ID_ABC.
+//debug user enum will be DIGRF_D_GDMA_DBG_ID_XXX
+//ex : DIGRF_D_GDMA_DBG_USER_ID(0, ABC, 0) will generate a enum
+//DGIRF_D_GDMA_DBG_ID_ABC.
+/**********************************************************/
+//Channel High part user id
+//TPC
+DIGRF_D_GDMA_5_H_USER_ID(0,     TXDFE_0)
+DIGRF_D_GDMA_5_H_USER_ID(1,     TXDFE_1)
+DIGRF_D_GDMA_5_H_USER_ID(2,     TXDFE_2)
+DIGRF_D_GDMA_5_H_USER_ID(3,     TXDFE_3)
+DIGRF_D_GDMA_5_H_USER_ID(4,     TXDFE_4)
+DIGRF_D_GDMA_5_H_USER_ID(5,     TXDFE_5)
+DIGRF_D_GDMA_5_H_USER_ID(6,     TXDFE_6)
+DIGRF_D_GDMA_5_H_USER_ID(7,     TXDFE_7)
+DIGRF_D_GDMA_5_H_USER_ID(8,     TXDFE_8)
+DIGRF_D_GDMA_5_H_USER_ID(9,     TXDFE_9)
+DIGRF_D_GDMA_5_H_USER_ID(10,    TXDFE_10)
+DIGRF_D_GDMA_5_H_USER_ID(11,    TXDFE_11)
+DIGRF_D_GDMA_5_H_USER_ID(12,    TXDFE_12)
+DIGRF_D_GDMA_5_H_USER_ID(13,    TXDFE_13)
+DIGRF_D_GDMA_5_H_USER_ID(14,    TXDFE_14)
+DIGRF_D_GDMA_5_H_USER_ID(15,    TXDFE_15)
+DIGRF_D_GDMA_5_H_USER_ID(16,    TXDFE_16)
+DIGRF_D_GDMA_5_H_USER_ID(17,    TXDFE_17)
+DIGRF_D_GDMA_5_H_USER_ID(18,    TXDFE_18)
+DIGRF_D_GDMA_5_H_USER_ID(19,    TXDFE_19)
+DIGRF_D_GDMA_5_H_USER_ID(20,    TXDFE_20)
+DIGRF_D_GDMA_5_H_USER_ID(21,    TXDFE_21)
+DIGRF_D_GDMA_5_H_USER_ID(22,    TXDFE_22)
+DIGRF_D_GDMA_5_H_USER_ID(23,    TXDFE_23)
+DIGRF_D_GDMA_5_H_USER_ID(24,    TXDFE_24)
+DIGRF_D_GDMA_5_H_USER_ID(25,    TXDFE_25)
+DIGRF_D_GDMA_5_H_USER_ID(26,    TXDFE_26)
+DIGRF_D_GDMA_5_H_USER_ID(27,    TXDFE_27)
+DIGRF_D_GDMA_5_H_USER_ID(28,    TXDFE_28)
+DIGRF_D_GDMA_5_H_USER_ID(29,    TXDFE_29)
+DIGRF_D_GDMA_5_H_USER_ID(30,    TXDFE_30)
+DIGRF_D_GDMA_5_H_USER_ID(31,    TXDFE_31)
+DIGRF_D_GDMA_5_H_USER_ID(32,    TXDFE_32)
+DIGRF_D_GDMA_5_H_USER_ID(33,    TXDFE_33)
+DIGRF_D_GDMA_5_H_USER_ID(34,    TXDFE_34)
+DIGRF_D_GDMA_5_H_USER_ID(35,    TXDFE_35)
+DIGRF_D_GDMA_5_H_USER_ID(36,    TXDFE_36)
+DIGRF_D_GDMA_5_H_USER_ID(37,    TXDFE_37)
+DIGRF_D_GDMA_5_H_USER_ID(38,    TXDFE_38)
+DIGRF_D_GDMA_5_H_USER_ID(39,    TXDFE_39)
+DIGRF_D_GDMA_5_H_USER_ID(40,    TXDFE_40)
+DIGRF_D_GDMA_5_H_USER_ID(41,    TXDFE_41)
+DIGRF_D_GDMA_5_H_USER_ID(42,    TXDFE_42)
+DIGRF_D_GDMA_5_H_USER_ID(43,    TXDFE_43)
+DIGRF_D_GDMA_5_H_USER_ID(44,    TXDFE_44)
+DIGRF_D_GDMA_5_H_USER_ID(45,    TXDFE_45)
+DIGRF_D_GDMA_5_H_USER_ID(46,    TXDFE_46)
+DIGRF_D_GDMA_5_H_USER_ID(47,    TXDFE_47)
+DIGRF_D_GDMA_5_H_USER_ID(48,    TXDFE_48)
+DIGRF_D_GDMA_5_H_USER_ID(49,    TXDFE_49)
+DIGRF_D_GDMA_5_H_USER_ID(50,    TXDFE_50)
+DIGRF_D_GDMA_5_H_USER_ID(51,    TXDFE_51)
+DIGRF_D_GDMA_5_H_USER_ID(52,    TXDFE_52)
+DIGRF_D_GDMA_5_H_USER_ID(53,    TXDFE_53)
+DIGRF_D_GDMA_5_H_USER_ID(54,    TXDFE_54)
+DIGRF_D_GDMA_5_H_USER_ID(55,    TXDFE_55)
+DIGRF_D_GDMA_5_H_USER_ID(56,    TXDFE_56)
+DIGRF_D_GDMA_5_H_USER_ID(57,    TXDFE_57)
+DIGRF_D_GDMA_5_H_USER_ID(58,    TXDFE_58)
+DIGRF_D_GDMA_5_H_USER_ID(59,    TXDFE_59)
+DIGRF_D_GDMA_5_H_USER_ID(60,    TXDFE_60)
+DIGRF_D_GDMA_5_H_USER_ID(61,    TXDFE_61)
+DIGRF_D_GDMA_5_H_USER_ID(62,    TXDFE_62)
+DIGRF_D_GDMA_5_H_USER_ID(63,    TXDFE_63)
+
+//Channel Low part user id
+DIGRF_D_GDMA_5_L_USER_ID(0,     TPC_0)
+DIGRF_D_GDMA_5_L_USER_ID(1,     TPC_1)
+DIGRF_D_GDMA_5_L_USER_ID(2,     TPC_2)
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_public.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_public.h
new file mode 100644
index 0000000..f5e7209
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_d_gdma_public.h
@@ -0,0 +1,243 @@
+#ifndef __DIGRF_D_GDMA_PUBLIC_H__
+#define __DIGRF_D_GDMA_PUBLIC_H__
+
+#if defined(__MD97__) || defined(__MD97P__)
+typedef enum{
+    #undef DIGRF_D_GDMA_0_H_USER_ID  
+    #undef DIGRF_D_GDMA_0_L_USER_ID  
+    #define DIGRF_D_GDMA_0_H_USER_ID(ID, ENUM)  DIGRF_D_GDMA_0_H_ID_##ENUM,
+    #define DIGRF_D_GDMA_0_L_USER_ID(ID, ENUM)
+    #include "digrf_d_gdma_0_user_id.h"
+    #undef DIGRF_D_GDMA_0_H_USER_ID  
+    #undef DIGRF_D_GDMA_0_L_USER_ID  
+    DIGRF_D_GDMA_0_H_END_ID
+}DIGRF_D_GDMA_0_H_ID;
+
+typedef enum{
+    #undef DIGRF_D_GDMA_0_H_USER_ID  
+    #undef DIGRF_D_GDMA_0_L_USER_ID  
+    #define DIGRF_D_GDMA_0_H_USER_ID(ID, ENUM)  
+    #define DIGRF_D_GDMA_0_L_USER_ID(ID, ENUM) DIGRF_D_GDMA_0_L_ID_##ENUM, 
+    #include "digrf_d_gdma_0_user_id.h"
+    #undef DIGRF_D_GDMA_0_H_USER_ID  
+    #undef DIGRF_D_GDMA_0_L_USER_ID  
+    DIGRF_D_GDMA_0_L_END_ID
+}DIGRF_D_GDMA_0_L_ID;
+
+typedef enum{
+    #undef DIGRF_D_GDMA_1_H_USER_ID  
+    #undef DIGRF_D_GDMA_1_L_USER_ID  
+    #define DIGRF_D_GDMA_1_H_USER_ID(ID, ENUM)  DIGRF_D_GDMA_1_H_ID_##ENUM,
+    #define DIGRF_D_GDMA_1_L_USER_ID(ID, ENUM)
+    #include "digrf_d_gdma_1_user_id.h"
+    #undef DIGRF_D_GDMA_1_H_USER_ID  
+    #undef DIGRF_D_GDMA_1_L_USER_ID  
+    DIGRF_D_GDMA_1_H_END_ID
+}DIGRF_D_GDMA_1_H_ID;
+
+typedef enum{
+    #undef DIGRF_D_GDMA_1_H_USER_ID  
+    #undef DIGRF_D_GDMA_1_L_USER_ID  
+    #define DIGRF_D_GDMA_1_H_USER_ID(ID, ENUM)  
+    #define DIGRF_D_GDMA_1_L_USER_ID(ID, ENUM) DIGRF_D_GDMA_1_L_ID_##ENUM, 
+    #include "digrf_d_gdma_1_user_id.h"
+    #undef DIGRF_D_GDMA_1_H_USER_ID  
+    #undef DIGRF_D_GDMA_1_L_USER_ID  
+    DIGRF_D_GDMA_1_L_END_ID
+}DIGRF_D_GDMA_1_L_ID;
+
+typedef enum{
+    #undef DIGRF_D_GDMA_2_H_USER_ID  
+    #undef DIGRF_D_GDMA_2_L_USER_ID  
+    #define DIGRF_D_GDMA_2_H_USER_ID(ID, ENUM)  DIGRF_D_GDMA_2_H_ID_##ENUM,
+    #define DIGRF_D_GDMA_2_L_USER_ID(ID, ENUM)
+    #include "digrf_d_gdma_2_user_id.h"
+    #undef DIGRF_D_GDMA_2_H_USER_ID  
+    #undef DIGRF_D_GDMA_2_L_USER_ID  
+    DIGRF_D_GDMA_2_H_END_ID
+}DIGRF_D_GDMA_2_H_ID;
+
+typedef enum{
+    #undef DIGRF_D_GDMA_2_H_USER_ID  
+    #undef DIGRF_D_GDMA_2_L_USER_ID  
+    #define DIGRF_D_GDMA_2_H_USER_ID(ID, ENUM)  
+    #define DIGRF_D_GDMA_2_L_USER_ID(ID, ENUM) DIGRF_D_GDMA_2_L_ID_##ENUM, 
+    #include "digrf_d_gdma_2_user_id.h"
+    #undef DIGRF_D_GDMA_2_H_USER_ID  
+    #undef DIGRF_D_GDMA_2_L_USER_ID  
+    DIGRF_D_GDMA_2_L_END_ID
+}DIGRF_D_GDMA_2_L_ID;
+
+typedef enum{
+    #undef DIGRF_D_GDMA_3_H_USER_ID  
+    #undef DIGRF_D_GDMA_3_L_USER_ID  
+    #define DIGRF_D_GDMA_3_H_USER_ID(ID, ENUM)  DIGRF_D_GDMA_3_H_ID_##ENUM,
+    #define DIGRF_D_GDMA_3_L_USER_ID(ID, ENUM)
+    #include "digrf_d_gdma_3_user_id.h"
+    #undef DIGRF_D_GDMA_3_H_USER_ID  
+    #undef DIGRF_D_GDMA_3_L_USER_ID  
+    DIGRF_D_GDMA_3_H_END_ID
+}DIGRF_D_GDMA_3_H_ID;
+
+typedef enum{
+    #undef DIGRF_D_GDMA_3_H_USER_ID  
+    #undef DIGRF_D_GDMA_3_L_USER_ID  
+    #define DIGRF_D_GDMA_3_H_USER_ID(ID, ENUM)  
+    #define DIGRF_D_GDMA_3_L_USER_ID(ID, ENUM) DIGRF_D_GDMA_3_L_ID_##ENUM, 
+    #include "digrf_d_gdma_3_user_id.h"
+    #undef DIGRF_D_GDMA_3_H_USER_ID  
+    #undef DIGRF_D_GDMA_3_L_USER_ID  
+    DIGRF_D_GDMA_3_L_END_ID
+}DIGRF_D_GDMA_3_L_ID;
+
+typedef enum{
+    #undef DIGRF_D_GDMA_4_H_USER_ID  
+    #undef DIGRF_D_GDMA_4_L_USER_ID  
+    #define DIGRF_D_GDMA_4_H_USER_ID(ID, ENUM)  DIGRF_D_GDMA_4_H_ID_##ENUM,
+    #define DIGRF_D_GDMA_4_L_USER_ID(ID, ENUM)
+    #include "digrf_d_gdma_4_user_id.h"
+    #undef DIGRF_D_GDMA_4_H_USER_ID  
+    #undef DIGRF_D_GDMA_4_L_USER_ID  
+    DIGRF_D_GDMA_4_H_END_ID
+}DIGRF_D_GDMA_4_H_ID;
+
+typedef enum{
+    #undef DIGRF_D_GDMA_4_H_USER_ID  
+    #undef DIGRF_D_GDMA_4_L_USER_ID  
+    #define DIGRF_D_GDMA_4_H_USER_ID(ID, ENUM)  
+    #define DIGRF_D_GDMA_4_L_USER_ID(ID, ENUM) DIGRF_D_GDMA_4_L_ID_##ENUM, 
+    #include "digrf_d_gdma_4_user_id.h"
+    #undef DIGRF_D_GDMA_4_H_USER_ID  
+    #undef DIGRF_D_GDMA_4_L_USER_ID  
+    DIGRF_D_GDMA_4_L_END_ID
+}DIGRF_D_GDMA_4_L_ID;
+
+typedef enum{
+    #undef DIGRF_D_GDMA_5_H_USER_ID  
+    #undef DIGRF_D_GDMA_5_L_USER_ID  
+    #define DIGRF_D_GDMA_5_H_USER_ID(ID, ENUM)  DIGRF_D_GDMA_5_H_ID_##ENUM,
+    #define DIGRF_D_GDMA_5_L_USER_ID(ID, ENUM)
+    #include "digrf_d_gdma_5_user_id.h"
+    #undef DIGRF_D_GDMA_5_H_USER_ID  
+    #undef DIGRF_D_GDMA_5_L_USER_ID  
+    DIGRF_D_GDMA_5_H_END_ID
+}DIGRF_D_GDMA_5_H_ID;
+
+typedef enum{
+    #undef DIGRF_D_GDMA_5_H_USER_ID  
+    #undef DIGRF_D_GDMA_5_L_USER_ID  
+    #define DIGRF_D_GDMA_5_H_USER_ID(ID, ENUM)  
+    #define DIGRF_D_GDMA_5_L_USER_ID(ID, ENUM) DIGRF_D_GDMA_5_L_ID_##ENUM, 
+    #include "digrf_d_gdma_5_user_id.h"
+    #undef DIGRF_D_GDMA_5_H_USER_ID  
+    #undef DIGRF_D_GDMA_5_L_USER_ID  
+    DIGRF_D_GDMA_5_L_END_ID
+}DIGRF_D_GDMA_5_L_ID;
+
+typedef union{
+    DIGRF_D_GDMA_0_H_ID channel_0_h_id;
+    DIGRF_D_GDMA_0_H_ID channel_1_h_id;
+    DIGRF_D_GDMA_0_H_ID channel_2_h_id;
+    DIGRF_D_GDMA_0_H_ID channel_3_h_id;
+    DIGRF_D_GDMA_0_H_ID channel_4_h_id;
+    DIGRF_D_GDMA_0_H_ID channel_5_h_id;
+    DIGRF_D_GDMA_0_L_ID channel_0_l_id;
+    DIGRF_D_GDMA_0_L_ID channel_1_l_id;
+    DIGRF_D_GDMA_0_L_ID channel_2_l_id;
+    DIGRF_D_GDMA_0_L_ID channel_3_l_id;
+    DIGRF_D_GDMA_0_L_ID channel_4_l_id;
+    DIGRF_D_GDMA_0_L_ID channel_5_l_id;
+}DIGRF_D_GDMA_CHANNEL_ID_UNION;
+
+typedef struct{
+//  DIGRF_D_GDMA_CHANNEL_ID_UNION channel_id;
+    kal_uint32 channel_id;
+    kal_uint32 source_addr;
+    kal_uint32 target_addr;
+    kal_uint8  enable;
+    kal_uint32 length;
+} DIGRF_D_GDMA_PAYLOAD;
+
+typedef enum{
+    DIGRF_D_GDMA_DONE,
+    DIGRF_D_GDMA_ONGOING,
+    DIGRF_D_GDMA_UNKNOW
+}DIGRF_D_GDMA_STATUS;
+
+typedef enum{
+    DIGRF_D_GDMA_MODULE_0_DEF = 0,
+    DIGRF_D_GDMA_MODULE_1_DEF = 1,
+    DIGRF_D_GDMA_MODULE_2_DEF = 2,
+    DIGRF_D_GDMA_MODULE_3_DEF = 3,
+    DIGRF_D_GDMA_MODULE_4_DEF = 4,
+    DIGRF_D_GDMA_MODULE_5_DEF = 5,
+    DIGRF_D_GDMA_MAX_MODULE_DEF
+}DIGRF_D_GDMA_MODULE_DEF;
+
+extern void DIGRF_D_GDMA_Init(void);
+extern void DIGRF_D_GDMA_H_Set(DIGRF_D_GDMA_PAYLOAD input, kal_uint32 module_id);
+extern void DIGRF_D_GDMA_H_Trigger(kal_uint32 id, kal_uint32 module_id);
+extern void DIGRF_D_GDMA_H_Multiple_Set(DIGRF_D_GDMA_PAYLOAD* input, kal_uint32 input_size, kal_uint32 module_id);
+extern DIGRF_D_GDMA_STATUS DIGRF_D_GDMA_H_Status_Check(kal_uint32 id, kal_uint32 module_id);
+extern void DIGRF_D_GDMA_L_Set(DIGRF_D_GDMA_PAYLOAD input, kal_uint32 module_id);
+extern void DIGRF_D_GDMA_L_Trigger(kal_uint32 id, kal_uint32 module_id);
+extern void DIGRF_D_GDMA_L_Multiple_Set(DIGRF_D_GDMA_PAYLOAD* input, kal_uint32 input_size, kal_uint32 module_id);
+extern DIGRF_D_GDMA_STATUS DIGRF_D_GDMA_L_Status_Check(kal_uint32 id, kal_uint32 module_id);
+
+//API for user
+#define DIGRF_D_GDMA_0_H_Set(input)                         DIGRF_D_GDMA_H_Set(input, DIGRF_D_GDMA_MODULE_0_DEF)
+#define DIGRF_D_GDMA_0_H_Trigger(id)                        DIGRF_D_GDMA_H_Trigger(id, DIGRF_D_GDMA_MODULE_0_DEF)
+#define DIGRF_D_GDMA_0_H_Status_Check(id)                   DIGRF_D_GDMA_H_Status_Check(id, DIGRF_D_GDMA_MODULE_0_DEF)
+#define DIGRF_D_GDMA_0_H_Multiple_Set(input, input_size)    DIGRF_D_GDMA_H_Multiple_Set(input, input_size, DIGRF_D_GDMA_MODULE_0_DEF)
+#define DIGRF_D_GDMA_0_L_Set(input)                         DIGRF_D_GDMA_L_Set(input, DIGRF_D_GDMA_MODULE_0_DEF)
+#define DIGRF_D_GDMA_0_L_Trigger(id)                        DIGRF_D_GDMA_L_Trigger(id, DIGRF_D_GDMA_MODULE_0_DEF)
+#define DIGRF_D_GDMA_0_L_Status_Check(id)                   DIGRF_D_GDMA_L_Status_Check(id, DIGRF_D_GDMA_MODULE_0_DEF)
+#define DIGRF_D_GDMA_0_L_Multiple_Set(input, input_size)    DIGRF_D_GDMA_L_Multiple_Set(input, input_size, DIGRF_D_GDMA_MODULE_0_DEF)
+
+#define DIGRF_D_GDMA_1_H_Set(input)                         DIGRF_D_GDMA_H_Set(input, DIGRF_D_GDMA_MODULE_1_DEF)
+#define DIGRF_D_GDMA_1_H_Trigger(id)                        DIGRF_D_GDMA_H_Trigger(id, DIGRF_D_GDMA_MODULE_1_DEF)
+#define DIGRF_D_GDMA_1_H_Status_Check(id)                   DIGRF_D_GDMA_H_Status_Check(id, DIGRF_D_GDMA_MODULE_1_DEF)
+#define DIGRF_D_GDMA_1_H_Multiple_Set(input, input_size)    DIGRF_D_GDMA_H_Multiple_Set(input, input_size, DIGRF_D_GDMA_MODULE_1_DEF)
+#define DIGRF_D_GDMA_1_L_Set(input)                         DIGRF_D_GDMA_L_Set(input, DIGRF_D_GDMA_MODULE_1_DEF)
+#define DIGRF_D_GDMA_1_L_Trigger(id)                        DIGRF_D_GDMA_L_Trigger(id, DIGRF_D_GDMA_MODULE_1_DEF)
+#define DIGRF_D_GDMA_1_L_Status_Check(id)                   DIGRF_D_GDMA_L_Status_Check(id, DIGRF_D_GDMA_MODULE_1_DEF)
+#define DIGRF_D_GDMA_1_L_Multiple_Set(input, input_size)    DIGRF_D_GDMA_L_Multiple_Set(input, input_size, DIGRF_D_GDMA_MODULE_1_DEF)
+
+#define DIGRF_D_GDMA_2_H_Set(input)                         DIGRF_D_GDMA_H_Set(input, DIGRF_D_GDMA_MODULE_2_DEF)
+#define DIGRF_D_GDMA_2_H_Trigger(id)                        DIGRF_D_GDMA_H_Trigger(id, DIGRF_D_GDMA_MODULE_2_DEF)
+#define DIGRF_D_GDMA_2_H_Status_Check(id)                   DIGRF_D_GDMA_H_Status_Check(id, DIGRF_D_GDMA_MODULE_2_DEF)
+#define DIGRF_D_GDMA_2_H_Multiple_Set(input, input_size)    DIGRF_D_GDMA_H_Multiple_Set(input, input_size, DIGRF_D_GDMA_MODULE_2_DEF)
+#define DIGRF_D_GDMA_2_L_Set(input)                         DIGRF_D_GDMA_L_Set(input, DIGRF_D_GDMA_MODULE_2_DEF)
+#define DIGRF_D_GDMA_2_L_Trigger(id)                        DIGRF_D_GDMA_L_Trigger(id, DIGRF_D_GDMA_MODULE_2_DEF)
+#define DIGRF_D_GDMA_2_L_Status_Check(id)                   DIGRF_D_GDMA_L_Status_Check(id, DIGRF_D_GDMA_MODULE_2_DEF)
+#define DIGRF_D_GDMA_2_L_Multiple_Set(input, input_size)    DIGRF_D_GDMA_L_Multiple_Set(input, input_size, DIGRF_D_GDMA_MODULE_2_DEF)
+
+#define DIGRF_D_GDMA_3_H_Set(input)                         DIGRF_D_GDMA_H_Set(input, DIGRF_D_GDMA_MODULE_3_DEF)
+#define DIGRF_D_GDMA_3_H_Trigger(id)                        DIGRF_D_GDMA_H_Trigger(id, DIGRF_D_GDMA_MODULE_3_DEF)
+#define DIGRF_D_GDMA_3_H_Status_Check(id)                   DIGRF_D_GDMA_H_Status_Check(id, DIGRF_D_GDMA_MODULE_3_DEF)
+#define DIGRF_D_GDMA_3_H_Multiple_Set(input, input_size)    DIGRF_D_GDMA_H_Multiple_Set(input, input_size, DIGRF_D_GDMA_MODULE_3_DEF)
+#define DIGRF_D_GDMA_3_L_Set(input)                         DIGRF_D_GDMA_L_Set(input, DIGRF_D_GDMA_MODULE_3_DEF)
+#define DIGRF_D_GDMA_3_L_Trigger(id)                        DIGRF_D_GDMA_L_Trigger(id, DIGRF_D_GDMA_MODULE_3_DEF)
+#define DIGRF_D_GDMA_3_L_Status_Check(id)                   DIGRF_D_GDMA_L_Status_Check(id, DIGRF_D_GDMA_MODULE_3_DEF)
+#define DIGRF_D_GDMA_3_L_Multiple_Set(input, input_size)    DIGRF_D_GDMA_L_Multiple_Set(input, input_size, DIGRF_D_GDMA_MODULE_3_DEF)
+
+#define DIGRF_D_GDMA_4_H_Set(input)                         DIGRF_D_GDMA_H_Set(input, DIGRF_D_GDMA_MODULE_4_DEF)
+#define DIGRF_D_GDMA_4_H_Trigger(id)                        DIGRF_D_GDMA_H_Trigger(id, DIGRF_D_GDMA_MODULE_4_DEF)
+#define DIGRF_D_GDMA_4_H_Status_Check(id)                   DIGRF_D_GDMA_H_Status_Check(id, DIGRF_D_GDMA_MODULE_4_DEF)
+#define DIGRF_D_GDMA_4_H_Multiple_Set(input, input_size)    DIGRF_D_GDMA_H_Multiple_Set(input, input_size, DIGRF_D_GDMA_MODULE_4_DEF)
+#define DIGRF_D_GDMA_4_L_Set(input)                         DIGRF_D_GDMA_L_Set(input, DIGRF_D_GDMA_MODULE_4_DEF)
+#define DIGRF_D_GDMA_4_L_Trigger(id)                        DIGRF_D_GDMA_L_Trigger(id, DIGRF_D_GDMA_MODULE_4_DEF)
+#define DIGRF_D_GDMA_4_L_Status_Check(id)                   DIGRF_D_GDMA_L_Status_Check(id, DIGRF_D_GDMA_MODULE_4_DEF)
+#define DIGRF_D_GDMA_4_L_Multiple_Set(input, input_size)    DIGRF_D_GDMA_L_Multiple_Set(input, input_size, DIGRF_D_GDMA_MODULE_4_DEF)
+
+#define DIGRF_D_GDMA_5_H_Set(input)                         DIGRF_D_GDMA_H_Set(input, DIGRF_D_GDMA_MODULE_5_DEF)
+#define DIGRF_D_GDMA_5_H_Trigger(id)                        DIGRF_D_GDMA_H_Trigger(id, DIGRF_D_GDMA_MODULE_5_DEF)
+#define DIGRF_D_GDMA_5_H_Status_Check(id)                   DIGRF_D_GDMA_H_Status_Check(id, DIGRF_D_GDMA_MODULE_5_DEF)
+#define DIGRF_D_GDMA_5_H_Multiple_Set(input, input_size)    DIGRF_D_GDMA_H_Multiple_Set(input, input_size, DIGRF_D_GDMA_MODULE_5_DEF)
+#define DIGRF_D_GDMA_5_L_Set(input)                         DIGRF_D_GDMA_L_Set(input, DIGRF_D_GDMA_MODULE_5_DEF)
+#define DIGRF_D_GDMA_5_L_Trigger(id)                        DIGRF_D_GDMA_L_Trigger(id, DIGRF_D_GDMA_MODULE_5_DEF)
+#define DIGRF_D_GDMA_5_L_Status_Check(id)                   DIGRF_D_GDMA_L_Status_Check(id, DIGRF_D_GDMA_MODULE_5_DEF)
+#define DIGRF_D_GDMA_5_L_Multiple_Set(input, input_size)    DIGRF_D_GDMA_L_Multiple_Set(input, input_size, DIGRF_D_GDMA_MODULE_5_DEF)
+
+#endif //__MD97__
+#endif //__DIGRF_D_GDMA_PUBLIC_H__
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_dsb_public.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_dsb_public.h
new file mode 100644
index 0000000..9a276f3
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_dsb_public.h
@@ -0,0 +1,104 @@
+#ifndef __DIGRF_DSB_PUBLIC_H__
+#define __DIGRF_DSB_PUBLIC_H__
+#if defined(__MD97__) || defined(__MD97P__)
+#include "digrf_platform_public.h"
+extern void DIGRF_DSB_Init(void);
+
+typedef enum{
+    #undef DIGRF_DSB_NOR_USER_ID
+    #undef DIGRF_DSB_DBG_USER_ID
+    #define DIGRF_DSB_NOR_USER_ID(ID, ENUM, HW, MODULE_ID) DIGRF_DSB_NOR_ID_##ENUM, 
+    #define DIGRF_DSB_DBG_USER_ID(ID, ENUM, HW, MODULE_ID) 
+    #include "digrf_dsb_user_id.h"
+    #undef DIGRF_DSB_NOR_USER_ID
+    #undef DIGRF_DSB_DBG_USER_ID
+    DIGRF_DSB_END_OF_ID
+}DIGRF_DSB_NOR_ID;
+
+typedef enum{
+    #undef DIGRF_DSB_NOR_USER_ID
+    #undef DIGRF_DSB_DBG_USER_ID
+    #define DIGRF_DSB_NOR_USER_ID(ID, ENUM, HW, MODULE_ID)
+    #define DIGRF_DSB_DBG_USER_ID(ID, ENUM, HW, MODULE_ID) DIGRF_DSB_DBG_ID_##ENUM, 
+    #include "digrf_dsb_user_id.h"
+    #undef DIGRF_DSB_NOR_USER_ID
+    #undef DIGRF_DSB_DBG_USER_ID
+    DIGRF_DSB_END_OF_DEBUG_ID
+}DIGRF_DSB_DEBUG_ID;
+
+typedef union{
+    DIGRF_DSB_NOR_ID   nor_id;
+    DIGRF_DSB_DEBUG_ID debug_id;
+}DIGRF_DSB_ID_ENUM;
+
+typedef enum{
+    #if defined(DIGRF_COLUMBUS_E1)
+    DIGRF_DSB_CHANNEL_ALL_DISABLE = 0x0,
+    DIGRF_DSB_CHANNEL_ALL_EN = 0x1,
+    #else
+    // Channel SW/HW trigger config with retrigger error enable
+    DIGRF_DSB_CHANNEL_ALL_DISABLE = 0x0,
+    DIGRF_DSB_CHANNEL_HW_EN = 0x1,
+    DIGRF_DSB_CHANNEL_SW_EN = 0x2,
+    DIGRF_DSB_CHANNEL_ALL_EN = 0x3,
+    // Channel SW/HW trigger config with retrigger error disable
+    DIGRF_DSB_CHANNEL_HW_EN_AND_RETRIGGER_ERR_DISABLE = (0x1 << 4) | DIGRF_DSB_CHANNEL_HW_EN,
+    DIGRF_DSB_CHANNEL_SW_EN_AND_RETRIGGER_ERR_DISABLE = (0x1 << 4) | DIGRF_DSB_CHANNEL_SW_EN,
+    DIGRF_DSB_CHANNEL_ALL_EN_AND_RETRIGGER_ERR_DISABLE = (0x1 << 4) | DIGRF_DSB_CHANNEL_ALL_EN,
+    #endif
+}DIGRF_DSB_CHANNEL_CONFIG_ENUM;
+
+#if defined(DIGRF_COLUMBUS_P)
+
+typedef enum{
+#undef  DIGRF_DSB_MPU_CFG
+#define DIGRF_DSB_MPU_CFG(id, start, end, mask) DIGRF_DSB_MPU_CHANNEL_##id = id,
+#include "dsb_config/digrf_dsb_mpu_cfg.h"
+#undef  DIGRF_DSB_MPU_CFG
+
+    DIGRF_DSB_MPU_CHANNEL_LIST
+}DIGRF_DSB_MPU_CHANNEL_ENUM;
+#endif //defined(DIGRF_COLUMBUS_P)
+
+typedef struct{
+    DIGRF_DSB_ID_ENUM channel_id;
+    kal_uint32 source_addr;
+    kal_uint32 target_addr;
+    DIGRF_DSB_CHANNEL_CONFIG_ENUM channel_config;
+    kal_uint32 length;
+} DIGRF_DSB_PAYLOAD;
+
+typedef enum{
+    DIGRF_DSB_DONE,
+    DIGRF_DSB_ONGOING,
+    DIGRF_DSB_UNKNOW
+}DIGRF_DSB_STATUS;
+
+typedef enum{
+    DIGRF_DSB_BUSY,
+    DIGRF_DSB_IDLE,
+    DIGRF_DSB_BUSY_STATUS_UNKNOW
+}DIGRF_DSB_BUSY_STATUS_ENUM;
+
+extern void DIGRF_DSB_Init(void);
+extern void DIGRF_DSB_NOR_Set(DIGRF_DSB_PAYLOAD input);
+extern void DIGRF_DSB_NOR_Trigger(DIGRF_DSB_NOR_ID id);
+extern void DIGRF_DSB_NOR_Multiple_Set(DIGRF_DSB_PAYLOAD* input, kal_uint32 input_size);
+extern DIGRF_DSB_STATUS DIGRF_DSB_NOR_Status_Check(DIGRF_DSB_NOR_ID id);
+extern void DIGRF_DSB_NOR_Done_Clear(DIGRF_DSB_NOR_ID id);
+extern DIGRF_DSB_BUSY_STATUS_ENUM DIGRF_DSB_NOR_Busy_Check(DIGRF_DSB_NOR_ID id);
+extern void DIGRF_DSB_Dump_Status(void);
+extern void DIGRF_DSB_Debug_Set(DIGRF_DSB_PAYLOAD input);
+extern void DIGRF_DSB_Debug_Trigger(DIGRF_DSB_DEBUG_ID id);
+extern void DIGRF_DSB_Debug_Multiple_Set(DIGRF_DSB_PAYLOAD* input, kal_uint32 input_size);
+extern DIGRF_DSB_STATUS DIGRF_DSB_Debug_Status_Check(DIGRF_DSB_DEBUG_ID id);
+extern void DIGRF_DSB_Debug_Done_Clear(DIGRF_DSB_DEBUG_ID id);
+extern DIGRF_DSB_BUSY_STATUS_ENUM DIGRF_DSB_Debug_Busy_Check(DIGRF_DSB_DEBUG_ID id);
+extern kal_uint32 DIGRF_DSB_Read_Reg32(kal_uint32 addr);
+
+#if defined(DIGRF_COLUMBUS_P)
+extern void DIGRF_DSB_MPU_Channel_Config(DIGRF_DSB_MPU_CHANNEL_ENUM channel, kal_uint32 start, kal_uint32 end, kal_uint32 mask);
+#endif //defined(DIGRF_COLUMBUS_P)
+#endif // __MD97__
+
+#endif //__DIGRF_DSB_PUBLIC_H__
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_dsb_user_id.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_dsb_user_id.h
new file mode 100644
index 0000000..95f77f2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_dsb_user_id.h
@@ -0,0 +1,9 @@
+#if defined(DIGRF_COLUMBUS_E1) || defined(DIGRF_COLUMBUS_E2_E3)
+    #include "dsb_config/digrf_columbus_config.h"
+#elif defined(DIGRF_COLUMBUS_L)
+    #include "dsb_config/digrf_columbus_lite_config.h"
+#elif defined(DIGRF_COLUMBUS_P) //Need porting for ColumbusP!!
+    #include "dsb_config/digrf_columbus_p_config.h"
+#else
+    #error "no such RF"
+#endif
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_global_con_public.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_global_con_public.h
new file mode 100644
index 0000000..7e60fde
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_global_con_public.h
@@ -0,0 +1,8 @@
+#ifndef __DIGRF_GLOBAL_CON_PULBIC_H__
+#define __DIGRF_GLOBAL_CON_PULBIC_H__
+
+#if defined(__MD97__) || defined(__MD97P__) 
+extern void DIGRF_Global_CON_Init(void);
+extern void DIGRF_DUMP_ALL_MODULE_FREQ_INIT(void);
+#endif //__MD97__
+#endif //__DIGRF_GLOBAL_CON_PUBLIC_H__
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_iomux_public.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_iomux_public.h
new file mode 100644
index 0000000..b988d21
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_iomux_public.h
@@ -0,0 +1,8 @@
+#ifndef __DIGRF_IOMUX_PULBIC_H__
+#define __DIGRF_IOMUX_PULBIC_H__
+
+#if defined(__MD97__) || defined(__MD97P__)
+extern void DIGRF_IOMUX_Init(void);
+
+#endif //__MD97__
+#endif //__DIGRF_IOMUX_PUBLIC_H__
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_mipi_public.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_mipi_public.h
new file mode 100644
index 0000000..4a8daca
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_mipi_public.h
@@ -0,0 +1,114 @@
+#ifndef __DIGRF_MIPI_PUBLIC_H__
+#define __DIGRF_MIPI_PUBLIC_H__
+
+#if defined(__MD97__) || defined(__MD97P__)
+#include "digrf_platform_public.h"
+
+#if defined(DIGRF_COLUMBUS_E1) || defined(DIGRF_COLUMBUS_E2_E3) || defined(DIGRF_COLUMBUS_L) || defined(DIGRF_COLUMBUS_P)
+#define DIGRF_MIPI_COM_BASE (0xAF000000)
+#define DIGRF_MIPI_COM_BUFFERABLE_BASE (0xBF000000)
+#define DIGRF_MIPI_COS_BASE (0xA9000000)
+#define DIGRF_MIPI_COS_BUFFERABLE_BASE (0xB9000000)
+#else
+#error "Unknown project, please porting COM base !!"
+#endif
+
+//MIPI slave address definition for user access
+typedef enum{
+    ACNT_EVT    = 0x0,
+    PAGE_ADDR   = 0x1,
+    TOPSM0_EVT  = 0x2,
+    ERR_STS0    = 0x3,
+    ERR_STS1    = 0x4,
+    IOMUX_CFG   = 0x5,
+    LOG_CTRL0   = 0x6,
+    LOG_CTRL1   = 0x7,
+    TRIG_TEST0  = 0x8,
+    TRIG_TEST1  = 0x9,
+    TRIG_TEST2  = 0xA,
+    CLKSW_CFG   = 0xB,
+    IDO0        = 0xC,
+    IDO1        = 0xD,
+    SPARE2      = 0xE,
+    SPARE3      = 0xF,
+    TOPSM1_EVT  = 0x10,
+    IDC_ON      = 0x11,
+    IDC_OFF     = 0x12,
+    DVFS        = 0x13,
+    PM_TRIG     = 0x1C,
+    PRODUCT_ID  = 0x1D,
+    MANUFACT_ID = 0x1E,
+    USID        = 0x1F,
+    REV_ID      = 0x21,
+    GSID        = 0x22,
+    UDR_RST     = 0x23,
+    ERR_SUM     = 0x24,
+    TEST_PATT   = 0x2C,
+    RAW_LOG_BASE = 0x40,
+#if defined(DIGRF_COLUMBUS_P)
+    RAW_LOG2_BASE = 0x57,
+#endif //defined(DIGRF_COLUMBUS_P)
+    APB_LOG_BASE = 0x70,
+    MIPI_SLV_END = 0x80
+}DIGRF_MIPI_SLV_ADDR_DEF;
+
+typedef enum{
+    PARITY_ODD      = 0,
+    PARITY_EVEN     = 1,
+    PARITY_UNKNOW   = 2
+}DIGRF_MIPI_PARITY;
+
+typedef enum{
+    A_DIE_SERDES_INIT_DONE    = 0x0,
+    D_DIE_SERDES_ERROR        = 0x1,
+    A_DIE_ON_IRQ_ERROR        = 0x2,
+    ENTER_EXCEPTION           = 0x3,
+    A_DIE_ENTER_DORMANT       = 0x4,
+    A_DIE_WAKE_UP_INIT_DONE   = 0x5,
+    SERDES_AT_CMD_TEST_BEGIN  = 0x6,
+    SERDES_AT_CMD_TEST_END    = 0x7,
+    A_DIE_ON_IRQ_RECOVER      = 0x8,
+}DIGRF_MIPI_PATH_CONFIG;
+
+typedef enum{
+    ENTER_EXCEPTION_BEGIN     = 0x0,
+    ENTER_EXCEPTION_END       = 0x1,
+    BB_REG_DUMP_END           = 0x2,
+}DIGRF_MIPI_EXCEPTION_DUMP;
+
+
+typedef struct{
+    DIGRF_MIPI_SLV_ADDR_DEF addr;
+    kal_uint8 data;
+    kal_uint8 parity;
+}DIGRF_MIPI_PAYLOAD;
+
+/*
+typedef struct{
+    DIGRF_MIPI_SLV_ADDR_DEF addr;
+    kal_uint8 data;
+    kal_uint8 parity;
+}DIGRF_MIPI_R_PAYLOAD;
+*/
+
+extern void DIGRF_MIPI_IMM_W(DIGRF_MIPI_PAYLOAD* input); 
+extern void DIGRF_MIPI_IMM_W_SYNC(void); 
+extern void DIGRF_MIPI_IMM_R(DIGRF_MIPI_PAYLOAD* input);
+extern void DIGRF_MIPI_IMM_FIRST_R(DIGRF_MIPI_PAYLOAD* input);  
+extern void DIGRF_MIPI_COM_W(kal_uint32 addr, kal_uint32 data); 
+extern kal_uint32 DIGRF_MIPI_COM_R(kal_uint32 addr); 
+extern void DIGRF_MIPI_Init(void);
+extern void DIGRF_MIPI_Slave_Init(void);
+extern void DIGRF_MIPI_Register_EX_dump(void);
+extern void DIGRF_MIPI_IMM_L_W(kal_uint32 addr, kal_uint32 data, kal_uint32 caller);
+extern kal_uint32 DIGRF_MIPI_IMM_L_R(kal_uint32 addr, kal_uint32 caller);
+extern void DIGRF_MIPI_Path_Config(DIGRF_MIPI_PATH_CONFIG path_case);
+extern kal_bool DIGRF_MIPI_Check_CoM_Region(kal_uint32 addr);
+
+void DIGRF_MIPI_DVFS_Protect(kal_uint32 user_id);
+void DIGRF_MIPI_DVFS_Record_Trigger_Time(kal_uint32 user_id);
+
+void DIGRF_MIPI_M_DUMP_REG(DIGRF_MIPI_EXCEPTION_DUMP mode);
+void DIGRF_MIPI_SLAVE_DUMP_REG(DIGRF_MIPI_EXCEPTION_DUMP mode);
+#endif //__MD97__
+#endif //__DIGRF_MIPI_PUBLIC_H__
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_off_clk_config.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_off_clk_config.h
new file mode 100644
index 0000000..4106878
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_off_clk_config.h
@@ -0,0 +1,52 @@
+#if defined(DIGRF_COLUMBUS_E1)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_BUS_CKCTL,                  DIGRF_OFF_CLKCTRL_OFF)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_MIPI_RFFE_APB_CKCTL,        DIGRF_OFF_CLKCTRL_OFF)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXDFE_624M_HOPPING_CKCTL,   DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TX_TICK_GEN_H624M_CKCTL,    DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TPC_312M_HOPPING_CKCTL,     DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXK_CORE_312M_HOPPING_CKCTL,DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXDFE_H312M_CKCTL,          DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXDFE_STREAM_H312M_CKCTL,   DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_FIX_ACNT_CKCTL,             DIGRF_OFF_CLKCTRL_ON)
+
+#elif defined(DIGRF_COLUMBUS_E2_E3)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_DVT_COS_CKCTL,              DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXDFE_624M_HOPPING_CKCTL,   DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TX_TICK_GEN_H624M_CKCTL,    DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TPC_312M_HOPPING_CKCTL,     DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXK_CORE_312M_HOPPING_CKCTL,DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXDFE_H312M_CKCTL,          DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXDFE_STREAM_H312M_CKCTL,   DIGRF_OFF_CLKCTRL_ON)
+
+#elif defined(DIGRF_COLUMBUS_L)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_DVT_COS_CKCTL,              DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXDFE_624M_HOPPING_CKCTL,   DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TX_TICK_GEN_H624M_CKCTL,    DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TPC_312M_HOPPING_CKCTL,     DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXK_CORE_312M_HOPPING_CKCTL,DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXDFE_H312M_CKCTL,          DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXDFE_STREAM_H312M_CKCTL,   DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_EVENT_H208M_CKCTL,          DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_APC_CK_CKCTL,               DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_EVENT_H104M_CKCTL,          DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_ACNT_CK_CKCTK,              DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_BSI_CK_CKCTK,               DIGRF_OFF_CLKCTRL_ON)
+
+#elif defined(DIGRF_COLUMBUS_L) || defined(DIGRF_COLUMBUS_P)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_DVT_COS_CKCTL,              DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXDFE_624M_HOPPING_CKCTL,   DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TX_TICK_GEN_H624M_CKCTL,    DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TPC_312M_HOPPING_CKCTL,     DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXK_CORE_312M_HOPPING_CKCTL,DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXDFE_H312M_CKCTL,          DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_TXDFE_STREAM_H312M_CKCTL,   DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_EVENT_H208M_CKCTL,          DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_APC_CK_CKCTL,               DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_EVENT_H104M_CKCTL,          DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_ACNT_CK_CKCTK,              DIGRF_OFF_CLKCTRL_ON)
+DIGRF_OFF_CLKCTRL_REG(DIGRF_OFF_CLK_BSI_CK_CKCTK,               DIGRF_OFF_CLKCTRL_ON)
+
+#else
+#error "No Match RF Option!!!"
+
+#endif
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_off_clk_public.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_off_clk_public.h
new file mode 100644
index 0000000..fc74ad4
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_off_clk_public.h
@@ -0,0 +1,84 @@
+#ifndef __DIGRF_OFF_CLK_PUBLIC_H__
+#define __DIGRF_OFF_CLK_PUBLIC_H__
+#if defined(__MD97__) || defined(__MD97P__)
+#include "digrf_platform_public.h"
+typedef enum{
+    DIGRF_OFF_CLKCTRL_OFF = 0,
+    DIGRF_OFF_CLKCTRL_ON  = 1,
+} DIGRF_OFF_CLKCTRL_ENUM;
+
+#if defined(DIGRF_COLUMBUS_E1)
+typedef enum{
+    DIGRF_OFF_CLK_BUS_CKCTL                     = 0x4,
+    DIGRF_OFF_CLK_MIPI_RFFE_APB_CKCTL           = 0x18,
+    DIGRF_OFF_CLK_TXDFE_624M_HOPPING_CKCTL      = 0x1C,
+    DIGRF_OFF_CLK_TX_TICK_GEN_H624M_CKCTL       = 0x20,
+    DIGRF_OFF_CLK_TPC_312M_HOPPING_CKCTL        = 0x24,
+    DIGRF_OFF_CLK_TXK_CORE_312M_HOPPING_CKCTL   = 0x28,
+    DIGRF_OFF_CLK_TXDFE_H312M_CKCTL             = 0x2C,
+    DIGRF_OFF_CLK_TXDFE_STREAM_H312M_CKCTL      = 0x34,
+    DIGRF_OFF_CLK_FIX_ACNT_CKCTL                = 0x38,
+} DIGRF_OFF_CLK_ENUM;
+#elif defined(DIGRF_COLUMBUS_E2_E3) 
+typedef enum{
+    DIGRF_OFF_CLK_MIPI_RFFE_APB_FREQ_SEL        = 0x0,
+    DIGRF_OFF_CLK_APC_APB_FREQ_SEL              = 0x4,
+    DIGRF_OFF_CLK_DVT_COS_CKCTL                 = 0x8,
+    DIGRF_OFF_CLK_TXDFE_624M_HOPPING_CKCTL      = 0x20,
+    DIGRF_OFF_CLK_TX_TICK_GEN_H624M_CKCTL       = 0x24,
+    DIGRF_OFF_CLK_TPC_312M_HOPPING_CKCTL        = 0x28,
+    DIGRF_OFF_CLK_TXK_CORE_312M_HOPPING_CKCTL   = 0x2C,
+    DIGRF_OFF_CLK_TXDFE_H312M_CKCTL             = 0x30,
+    DIGRF_OFF_CLK_TXDFE_STREAM_H312M_CKCTL      = 0x34,
+} DIGRF_OFF_CLK_ENUM;
+#elif defined(DIGRF_COLUMBUS_L)
+typedef enum{
+    DIGRF_OFF_CLK_MIPI_RFFE_APB_FREQ_SEL        = 0x0,
+    DIGRF_OFF_CLK_APC_APB_FREQ_SEL              = 0x4,
+    DIGRF_OFF_CLK_DVT_COS_CKCTL                 = 0x8,
+    DIGRF_OFF_CLK_TXDFE_624M_HOPPING_CKCTL      = 0x20,
+    DIGRF_OFF_CLK_TX_TICK_GEN_H624M_CKCTL       = 0x24,
+    DIGRF_OFF_CLK_TPC_312M_HOPPING_CKCTL        = 0x28,
+    DIGRF_OFF_CLK_TXK_CORE_312M_HOPPING_CKCTL   = 0x2C,
+    DIGRF_OFF_CLK_TXDFE_H312M_CKCTL             = 0x30,
+    DIGRF_OFF_CLK_TXDFE_STREAM_H312M_CKCTL      = 0x34,
+
+    // note: do not modify the enum value if not check the coda
+    //       (0x1 << 38) (for distinguish if this register)
+    //       and the | XXX is for the offset of this control bit
+    DIGRF_OFF_CLK_EVENT_H208M_CKCTL             = (0x38 << 8) | (0x0),
+    DIGRF_OFF_CLK_APC_CK_CKCTL                  = (0x38 << 8) | (0x1),
+    DIGRF_OFF_CLK_EVENT_H104M_CKCTL             = (0x38 << 8) | (0x2),
+    DIGRF_OFF_CLK_ACNT_CK_CKCTK                 = (0x38 << 8) | (0x3),
+    DIGRF_OFF_CLK_BSI_CK_CKCTK                  = (0x38 << 8) | (0x4),
+} DIGRF_OFF_CLK_ENUM;
+#elif defined(DIGRF_COLUMBUS_P)
+typedef enum{
+    DIGRF_OFF_CLK_MIPI_RFFE_APB_FREQ_SEL        = 0x0,
+    DIGRF_OFF_CLK_APC_APB_FREQ_SEL              = 0x4,
+    DIGRF_OFF_CLK_DVT_COS_CKCTL                 = 0x8,
+    DIGRF_OFF_CLK_TXDFE_624M_HOPPING_CKCTL      = 0x20,
+    DIGRF_OFF_CLK_TX_TICK_GEN_H624M_CKCTL       = 0x24,
+    DIGRF_OFF_CLK_TPC_312M_HOPPING_CKCTL        = 0x28,
+    DIGRF_OFF_CLK_TXK_CORE_312M_HOPPING_CKCTL   = 0x2C,
+    DIGRF_OFF_CLK_TXDFE_H312M_CKCTL             = 0x30,
+    DIGRF_OFF_CLK_TXDFE_STREAM_H312M_CKCTL      = 0x34,
+    DIGRF_OFF_CLK_EVENT_H208M_CKCTL             = 0x38,
+    DIGRF_OFF_CLK_APC_CK_CKCTL                  = 0x3C,
+    DIGRF_OFF_CLK_EVENT_H104M_CKCTL             = 0x40,
+    DIGRF_OFF_CLK_ACNT_CK_CKCTK                 = 0x44,
+    DIGRF_OFF_CLK_BSI_CK_CKCTK                  = 0x48,
+} DIGRF_OFF_CLK_ENUM;
+#else
+#error "No Match RF Option!!!"
+#endif
+
+
+// Public Function
+extern void DIGRF_OFF_CLK_Init(void);
+extern void DIGRF_OFF_CLK_Control(DIGRF_OFF_CLK_ENUM off_clk_name, DIGRF_OFF_CLKCTRL_ENUM value);
+extern DIGRF_OFF_CLKCTRL_ENUM DIGRF_OFF_CLK_Status(DIGRF_OFF_CLK_ENUM off_clk_name);
+extern void DIGRF_OFF_CLK_Dump_Status(void);
+
+#endif //__MD97__
+#endif //__DIGRF_OFF_CLK_PUBLIC_H__
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_off_dbgmon_public.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_off_dbgmon_public.h
new file mode 100644
index 0000000..7cb40bb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_off_dbgmon_public.h
@@ -0,0 +1,86 @@
+#ifndef __DIGRF_OFF_DBGMON_PUBLIC_H__
+#define __DIGRF_OFF_DBGMON_PUBLIC_H__
+
+#if defined(__MD97__) || defined(__MD97P__)
+
+#include "digrf_platform_public.h"
+#define DIGRF_OFF_DBGMON_BASE               (0x2D8000)
+#define DIGRF_OFF_DBGMON_BD_BASE            (0x388000)
+
+#define DIGRF_OFF_DBGMON_FLAG_MOD_SEL_REG   (DIGRF_OFF_DBGMON_BD_BASE + (0x0))
+#define DIGRF_OFF_DBGMON_TRIG_MOD_SEL_REG   (DIGRF_OFF_DBGMON_BD_BASE + (0x4))
+#define DIGRF_OFF_DBGMON_TRIG_BIT_SEL_REG   (DIGRF_OFF_DBGMON_BD_BASE + (0x8))
+#define DIGRF_OFF_DBGMON_CLK_BIT_SEL_REG    (DIGRF_OFF_DBGMON_BD_BASE + (0xC))
+#define DIGRF_OFF_DBGMON_DBG_FLAG0_SEL_REG  (DIGRF_OFF_DBGMON_BD_BASE + (0x10))
+#define DIGRF_OFF_DBGMON_DBG_FLAG1_SEL_REG  (DIGRF_OFF_DBGMON_BD_BASE + (0x14))
+#define DIGRF_OFF_DBGMON_DBG_FLAG2_SEL_REG  (DIGRF_OFF_DBGMON_BD_BASE + (0x18))
+#define DIGRF_OFF_DBGMON_DBG_FLAG3_SEL_REG  (DIGRF_OFF_DBGMON_BD_BASE + (0x1C))
+#define DIGRF_OFF_DBGMON_DBG_TRIG_SEL_REG   (DIGRF_OFF_DBGMON_BD_BASE + (0x20))
+#define DIGRF_OFF_DBGMON_DBG_CLK_SEL_REG    (DIGRF_OFF_DBGMON_BD_BASE + (0x24))
+#define DIGRF_OFF_DBGMON_FLAG_READ_REG      (DIGRF_OFF_DBGMON_BD_BASE + (0x30))
+#define DIGRF_OFF_DBGMON_FLAG_READ_EN_REG   (DIGRF_OFF_DBGMON_BD_BASE + (0x34))
+
+
+#if defined(DIGRF_COLUMBUS_E1)
+typedef enum{
+    DIGRF_DBGMON_BUS_OFF_STATUS = 0,
+    DIGRF_DBGMON_DSB_IDLE_STATUS,
+    DIGRF_DBGMON_TOTAL_NUMBER,
+}DIGRF_DBGMON_STATUS;
+
+#define DIGRF_DBGMON_BUS_OFF_STATUS_SEL             0x4
+#define DIGRF_DBGMON_DSB_IDLE_STATUS_SEL            0x5
+
+
+#else
+typedef enum{
+    DIGRF_DBGMON_COS_WRITE_ADDR = 0x0,
+    DIGRF_DBGMON_DSB_READ_ADDR,
+    DIGRF_DBGMON_BUS_OFF_STATUS,
+    DIGRF_DBGMON_COS_AXI_STATUS_1,
+    DIGRF_DBGMON_COS_MIPI_STATUS,
+    DIGRF_DBGMON_COS_AXI_ULTRA_STATUS,
+    DIGRF_DBGMON_COS_AXI_STATUS_2,
+    DIGRF_DBGMON_COS_OST_BUSMON_STATUS,
+    DIGRF_DBGMON_EXTIF2COS_AXI_STATUS,
+    DIGRF_DBGMON_EXTIF2COS_WDATA,
+    DIGRF_DBGMON_EXTIF2DSB_AXI_READ_STATUS,
+    DIGRF_DBGMON_EXTIF2DSB_RDATA,
+    DIGRF_DBGMON_EXTIF2DSB_AXI_WRITE_STATUS,
+    DIGRF_DBGMON_TPC_TX_APB_WO_STATUS,
+    DIGRF_DBGMON_TPC_TX_APB_PWDATA,
+    DIGRF_DBGMON_TPC_TX_APB_RO_STATUS,
+    DIGRF_DBGMON_TPC_TX_APB_RO_PRDATA,
+    DIGRF_DBGMON_TPC_TX_SYS_BUS_STATUS,
+    DIGRF_DBGMON_REMAP_STATUS,
+    DIGRF_DBGMON_ACNT_VAL,
+    DIGRF_DBGMON_TOTAL_NUMBER,
+}DIGRF_DBGMON_STATUS;
+
+
+#define DIGRF_DBGMON_COS_WRITE_ADDR_SEL             0x2
+#define DIGRF_DBGMON_DSB_READ_ADDR_SEL              0x3
+#define DIGRF_DBGMON_BUS_OFF_STATUS_SEL             0x4
+#define DIGRF_DBGMON_COS_AXI_STATUS_1_SEL           0x5
+#define DIGRF_DBGMON_COS_MIPI_STATUS_SEL            0x6
+#define DIGRF_DBGMON_COS_AXI_ULTRA_STATUS_SEL       0x7
+#define DIGRF_DBGMON_COS_AXI_STATUS_2_SEL           0x8
+#define DIGRF_DBGMON_COS_OST_BUSMON_STATUS_SEL      0xA
+#define DIGRF_DBGMON_EXTIF2COS_AXI_STATUS_SEL       0x12
+#define DIGRF_DBGMON_EXTIF2COS_WDATA_SEL            0x13
+#define DIGRF_DBGMON_EXTIF2DSB_AXI_READ_STATUS_SEL  0x14
+#define DIGRF_DBGMON_EXTIF2DSB_RDATA_SEL            0x15
+#define DIGRF_DBGMON_EXTIF2DSB_AXI_WRITE_STATUS_SEL 0x16
+#define DIGRF_DBGMON_TPC_TX_APB_WO_STATUS_SEL       0x17
+#define DIGRF_DBGMON_TPC_TX_APB_PWDATA_SEL          0x18
+#define DIGRF_DBGMON_TPC_TX_APB_RO_STATUS_SEL       0x19
+#define DIGRF_DBGMON_TPC_TX_APB_RO_PRDATA_SEL       0x1A
+#define DIGRF_DBGMON_TPC_TX_SYS_BUS_STATUS_SEL      0x1B
+#define DIGRF_DBGMON_REMAP_STATUS_SEL               0x1C
+#define DIGRF_DBGMON_ACNT_VAL_SEL                   0x1D
+#endif
+    
+kal_uint32 DIGRF_DBGMON_GET_status_by_different_select(kal_uint32 module, kal_uint32 select);
+
+#endif //__MD97__
+#endif //__DIGRF_OFF_DBGMON_PUBLIC_H__
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_on_clk_config.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_on_clk_config.h
new file mode 100644
index 0000000..f4b0e8d
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_on_clk_config.h
@@ -0,0 +1,44 @@
+#if defined(DIGRF_COLUMBUS_E1)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_AO_F26M_CK,       DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_DVTSRC_CK,        DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_TXDFE_CK,         DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_RXDFE_CK,         DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_USER_RESERVE,     DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_BUS_CK,           DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_FIX_CK,           DIGRF_ON_CLKCTRL_ON)
+#elif defined(DIGRF_COLUMBUS_E2_E3)
+
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_CSW_OFF_F26M_CK,  DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_DVTSRC_CK,        DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_TXDFE_CK,         DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_RXDFE_CK,         DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_BUS_CK,           DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_FIX_CK,           DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_APC_CK,           DIGRF_ON_CLKCTRL_OFF)
+
+#elif defined(DIGRF_COLUMBUS_L)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_AO_F26M_CK,       DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_CSW_OFF_F26M_CK,  DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_DVTSRC_CK,        DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_TXDFE_CK,         DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_AO_FIX_CK,        DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_RXDFE_CK,         DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_BUS_CK,           DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_OFF_FIX_CK,       DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_APC_CK,           DIGRF_ON_CLKCTRL_OFF)
+
+#elif defined(DIGRF_COLUMBUS_P)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_AO_F26M_CK,       DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_CSW_OFF_F26M_CK,  DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_DVTSRC_CK,        DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_TXDFE_CK,         DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_AO_FIX_CK,        DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_RXDFE_CK,         DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_BUS_CK,           DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_OFF_FIX_CK,       DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_OFF_312M_FIX_CK,  DIGRF_ON_CLKCTRL_ON)
+DIGRF_ON_CLKCTRL_REG(DIGRF_ON_CLK_APC_CK,           DIGRF_ON_CLKCTRL_OFF)
+
+#else
+#error "No Match RF Option!!!"
+#endif
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_on_clk_public.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_on_clk_public.h
new file mode 100644
index 0000000..06bd8c9
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_on_clk_public.h
@@ -0,0 +1,82 @@
+#ifndef __DIGRF_ON_CLK_PUBLIC_H__
+#define __DIGRF_ON_CLK_PUBLIC_H__
+
+#if defined(__MD97__) || defined(__MD97P__) 
+#include "digrf_platform_public.h"
+typedef enum{
+    DIGRF_ON_CLKCTRL_OFF = 0,
+    DIGRF_ON_CLKCTRL_ON  = 1,
+} DIGRF_ON_CLKCTRL_ENUM;
+
+
+#if defined(DIGRF_COLUMBUS_E1)
+typedef enum{
+    DIGRF_ON_CLK_AO_F26M_CK     = 0,
+    DIGRF_ON_CLK_DVTSRC_CK      = 1,
+    DIGRF_ON_CLK_TXDFE_CK       = 2,
+    DIGRF_ON_CLK_RXDFE_CK       = 3,
+    DIGRF_ON_CLK_USER_RESERVE   = 4,
+    DIGRF_ON_CLK_BUS_CK         = 5,
+    DIGRF_ON_CLK_FIX_CK         = 6,
+} DIGRF_ON_CLK_ENUM;
+
+#define DIGRF_ON_CLK_NUM    7
+
+#elif defined(DIGRF_COLUMBUS_E2_E3) 
+
+typedef enum{
+    DIGRF_ON_CLK_CSW_OFF_F26M_CK = 0x4,
+    DIGRF_ON_CLK_DVTSRC_CK       = 0x8,
+    DIGRF_ON_CLK_TXDFE_CK        = 0xC,
+    DIGRF_ON_CLK_RXDFE_CK        = 0x14,
+    DIGRF_ON_CLK_BUS_CK          = 0x18,
+    DIGRF_ON_CLK_FIX_CK          = 0x1C,
+    DIGRF_ON_CLK_APC_CK          = 0x8C,
+} DIGRF_ON_CLK_ENUM;
+
+#define DIGRF_ON_CLK_NUM    7
+
+#elif defined(DIGRF_COLUMBUS_L) 
+
+typedef enum{
+    DIGRF_ON_CLK_AO_F26M_CK      = 0x0,
+    DIGRF_ON_CLK_CSW_OFF_F26M_CK = 0x4,
+    DIGRF_ON_CLK_DVTSRC_CK       = 0x8,
+    DIGRF_ON_CLK_TXDFE_CK        = 0xC,
+    DIGRF_ON_CLK_AO_FIX_CK       = 0x10,
+    DIGRF_ON_CLK_RXDFE_CK        = 0x14,
+    DIGRF_ON_CLK_BUS_CK          = 0x18,
+    DIGRF_ON_CLK_OFF_FIX_CK      = 0x1C,
+    DIGRF_ON_CLK_APC_CK          = 0x8C,
+} DIGRF_ON_CLK_ENUM;
+
+#define DIGRF_ON_CLK_NUM    9
+
+#elif defined(DIGRF_COLUMBUS_P) 
+
+typedef enum{
+    DIGRF_ON_CLK_AO_F26M_CK      = 0x0,
+    DIGRF_ON_CLK_CSW_OFF_F26M_CK = 0x4,
+    DIGRF_ON_CLK_DVTSRC_CK       = 0x8,
+    DIGRF_ON_CLK_TXDFE_CK        = 0xC,
+    DIGRF_ON_CLK_AO_FIX_CK       = 0x10,
+    DIGRF_ON_CLK_RXDFE_CK        = 0x14,
+    DIGRF_ON_CLK_BUS_CK          = 0x18,
+    DIGRF_ON_CLK_OFF_FIX_CK      = 0x1C,
+    DIGRF_ON_CLK_OFF_312M_FIX_CK = 0x2C,
+    DIGRF_ON_CLK_APC_CK          = 0x8C,
+} DIGRF_ON_CLK_ENUM;
+
+#define DIGRF_ON_CLK_NUM    10
+
+#else
+#error "No Match RF Option!!!"
+#endif
+
+extern void DIGRF_ON_CLK_Init(void);
+extern void DIGRF_ON_CLK_Dump_Status(void);
+
+extern void DIGRF_ON_CLK_Control(DIGRF_ON_CLK_ENUM on_clk_name, DIGRF_ON_CLKCTRL_ENUM value);
+#endif //__MD97__
+#endif //__DIGRF_ON_CLK_PULBIC_H__
+
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_on_irq_public.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_on_irq_public.h
new file mode 100644
index 0000000..dc058ee
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_on_irq_public.h
@@ -0,0 +1,25 @@
+#ifndef __DIGRF_ON_IRQ_PUBLIC_H__
+#define __DIGRF_ON_IRQ_PUBLIC_H__
+
+#if defined(__MD97__) || defined(__MD97P__) 
+typedef enum{
+#undef DIGRF_IRQ_REG
+#define DIGRF_IRQ_REG(IRQ_ID, IRQ_ENUM, ENABLE, CallBack) IRQ_ENUM,
+#include "digrf_on_irq_user_config.h"
+#undef DIGRF_IRQ_REG
+    DIGRF_IRQ_ENUM_END
+} DIGRF_IRQ_ENUM;
+
+typedef enum {
+    DIGRF_ON_IRQ_NO_IRQ,
+    DIGRF_ON_IRQ_EXECUTING,
+} DIGRF_ON_IRQ_EXECUTE_STATUS;
+
+extern void DIGRF_ON_IRQ_Init(void);
+extern kal_uint32 DIGRF_ON_IRQ_Status_Check(kal_uint32 id);
+extern void DIGRF_ON_IRQ_Clear(kal_uint32 id); 
+extern kal_uint32 DIGRF_ON_IRQ_Status_Read(void);
+extern DIGRF_ON_IRQ_EXECUTE_STATUS DIGRF_ON_IRQ_Execute_Status_Check(void);
+
+#endif //__MD97__
+#endif //__DIGRF_ON_IRQ_PUBLIC_H__
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_on_irq_user_config.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_on_irq_user_config.h
new file mode 100644
index 0000000..1beed75
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_on_irq_user_config.h
@@ -0,0 +1,25 @@
+//DIGRF_IRQ_REG(IRQ_ID, IRQ_NAME, 1(IRQ ENABLE)/0(IRQ DISABLE), callback_function)
+//callback prototype : void callback_function(void) 
+#if !defined(__DIGRF_PLATFORM_TEST__)
+DIGRF_IRQ_REG(0, DIGRF_SERDES,      1, serdes_irq_handling_a)
+DIGRF_IRQ_REG(1, DIGRF_PLLMIXED,    1, DIGRF_PLLMIXED_IRQ_Handler)
+DIGRF_IRQ_REG(2, DIGRF_OFFBUS,      1, DIGRF_BUS_OFF_IRQ_Handler)
+DIGRF_IRQ_REG(3, DIGRF_AOBUS,       1, DIGRF_BUS_AO_IRQ_Handler)
+DIGRF_IRQ_REG(4, DIGRF_UCNT,        0, DIGRF_ON_IRQ_Default)
+DIGRF_IRQ_REG(5, DIGRF_MIPI,        1, DIGRF_MIPI_IRQ_Handler)
+DIGRF_IRQ_REG(6, DIGRF_DSB,         1, DIGRF_DSB_IRQ_Handler)
+#if defined(DIGRF_COLUMBUS_P)
+DIGRF_IRQ_REG(7, DIGRF_DSB_MPU,     1, DIGRF_DSB_MPU_IRQ_Handler)
+#endif //DIGRF_COLUMBUS_P
+#else
+DIGRF_IRQ_REG(0, DIGRF_SERDES,      1, DIGRF_ON_IRQ_TEST_ISR_0)
+DIGRF_IRQ_REG(1, DIGRF_PLLMIXED,    1, DIGRF_ON_IRQ_TEST_ISR_1)
+DIGRF_IRQ_REG(2, DIGRF_OFFBUS,      1, DIGRF_ON_IRQ_TEST_ISR_2)
+DIGRF_IRQ_REG(3, DIGRF_AOBUS,       1, DIGRF_ON_IRQ_TEST_ISR_3)
+DIGRF_IRQ_REG(4, DIGRF_UCNT,        1, DIGRF_ON_IRQ_TEST_ISR_4)
+DIGRF_IRQ_REG(5, DIGRF_MIPI,        1, DIGRF_ON_IRQ_TEST_ISR_5)
+DIGRF_IRQ_REG(6, DIGRF_DSB,         1, DIGRF_ON_IRQ_TEST_ISR_6)
+#if defined(DIGRF_COLUMBUS_P)
+DIGRF_IRQ_REG(7, DIGRF_DSB_MPU,     1, DIGRF_ON_IRQ_TEST_ISR_7)
+#endif //DIGRF_COLUMBUS_P
+#endif
diff --git a/mcu/interface/driver/devdrv/digrf_platform/digrf_platform_public.h b/mcu/interface/driver/devdrv/digrf_platform/digrf_platform_public.h
new file mode 100644
index 0000000..f450ba4
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/digrf_platform_public.h
@@ -0,0 +1,79 @@
+#ifndef __DIGRF_PLATFORM_PUBLIC_H__
+#define __DIGRF_PLATFORM_PUBLIC_H__
+
+#if defined(__MD97__) || defined(__MD97P__)
+
+#if defined(MT6190T_RF)
+    #define DIGRF_COLUMBUS_E1
+#elif defined(MT6190_RF)
+    // E2 and E3 is co-load
+    #define DIGRF_COLUMBUS_E2_E3
+#elif defined(MT6190M_RF)
+    #define DIGRF_COLUMBUS_L
+#elif defined(MT6195_RF) || defined(MT6195_NR_RF)
+    #define DIGRF_COLUMBUS_P
+#else
+    // BASIC load will not define RF info in proj makefile
+    #if defined(MT6297)
+        #define DIGRF_COLUMBUS_E1
+    #elif defined(MT6885) || defined(MT6873) || defined(MT6298) || defined(CHIP10992)
+        #define DIGRF_COLUMBUS_E2_E3
+    #elif defined(MT6853) || defined(MT6833) || defined(MT6877)
+        #define DIGRF_COLUMBUS_L
+    #else
+        #error "No Match D-die Project Option!!!"
+    #endif
+#endif
+
+
+
+
+#include "reg_base.h"
+#define DIGRF_PERI_ACCESS(addr)             (*(volatile kal_uint32*)(addr))
+#define DIGRF_PLATFORM_COS_BASE             (0xA9000000)
+#define DIGRF_PLATFORM_COS_BF_BASE          (0xB9000000)
+
+#define DIGRF_PLATFORM_COS_ACCESS(addr)       (DIGRF_PERI_ACCESS(DIGRF_PLATFORM_COS_BASE    + (addr)))
+#define DIGRF_PLATFORM_COS_BUFFERABLE_ACCESS(addr)  (DIGRF_PERI_ACCESS(DIGRF_PLATFORM_COS_BF_BASE + (addr)))
+
+#define __DIGRF_DEBUG__
+#define DIGRF_GET_RETURN_ADDRESS(data)      GET_RETURN_ADDRESS(data)
+
+typedef enum{
+    DIGRF_PLATFORM_EXIST = 0,
+    DIGRF_PLATFORM_NOT_EXIST = 1
+}DIGRF_PLATFORM_CHECK_STATUS_ENUM;
+
+typedef enum{
+    DIGRF_VERSION_COLUMBUS_E1 = 0x1,
+    DIGRF_VERSION_COLUMBUS_E1_ECO = 0x81,
+    DIGRF_VERSION_COLUMBUS_E2 = 0xE2,
+    DIGRF_VERSION_COLUMBUS_E3 = 0xE3,
+    DIGRF_VERSION_COLUMBUS_L = 0x4C,
+    #if defined(DIGRF_COLUMBUS_P)
+    DIGRF_VERSION_COLUMBUS_P = 0x50,
+    #endif  //DIGRF_COLUMBUS_P
+    DIGRF_VERSION_UNKNOWN = 0xFF
+}DIGRF_PLATFORM_VERSION_ENUM;
+
+extern void DIGRF_Platform_Init_Phase_1(void);
+extern void DIGRF_Platform_Init_Phase_2(void);
+extern void DIGRF_Platform_OFF_Domain_Init(void);
+extern DIGRF_PLATFORM_CHECK_STATUS_ENUM DIGRF_Platform_Check(void);
+extern kal_bool DIGRF_Platform_Can_Dump(void);
+extern void DIGRF_BUS_OFF_Register_EX_dump(void);
+extern DIGRF_PLATFORM_VERSION_ENUM DIGRF_Platform_Version_Check(void);
+
+#if defined(__DIGRF_PLATFORM_TEST__)
+// not for normal used... only for drvier dvt
+#define DIGRF_DVT_INDEX (BASE_MADDR_MODEML1_AO_DIGRF_MIPI_0 + (0x1118))
+#define DIGRF_DVT_FIELD (BASE_MADDR_MODEML1_AO_DIGRF_MIPI_0 + (0x1120))
+#endif
+#else // not MD97
+
+#define DIGRF_Platform_Init_Phase_1()
+#define DIGRF_Platform_Init_Phase_2()
+#define DIGRF_Platform_OFF_Domain_Init()
+#endif //__MD97__
+
+#endif //__DIGRF_PLATFORM_PUBLIC_H__
diff --git a/mcu/interface/driver/devdrv/digrf_platform/dsb_config/digrf_columbus_config.h b/mcu/interface/driver/devdrv/digrf_platform/dsb_config/digrf_columbus_config.h
new file mode 100644
index 0000000..f9383d6
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/dsb_config/digrf_columbus_config.h
@@ -0,0 +1,211 @@
+//DIGRF_DSB_USER_ID(channel number, USER_ID, HW_TRIGGER )
+//HW_TRIGGER: channel triggered by HW = 1  
+
+//normal user enum will be DIGRF_DSB_NOR_ID_XXX
+//ex : DIGRF_DSB_NOR_USER_ID(0, ABC, 0) will generate a enum
+//DIGRF_DSB_NOR_ID_ABC.
+//debug user enum will be DIGRF_DSB_DBG_ID_XXX
+//ex : DIGRF_DSB_DBG_USER_ID(0, ABC, 0) will generate a enum
+//DIGRF_DSB_DBG_ID_ABC.
+/**********************************************************/
+//NORMAL user part
+//RXDFE REPORT user id
+DIGRF_DSB_NOR_USER_ID(0,     RXDFE_RPT_0,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(1,     RXDFE_RPT_1,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(2,     RXDFE_RPT_2,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(3,     RXDFE_RPT_3,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(4,     RXDFE_RPT_4,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(5,     RXDFE_RPT_5,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(6,     RXDFE_RPT_6,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(7,     RXDFE_RPT_7,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(8,     RXDFE_RPT_8,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(9,     RXDFE_RPT_9,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(10,    RXDFE_RPT_10,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(11,    RXDFE_RPT_11,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(12,    RXDFE_RPT_12,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(13,    RXDFE_RPT_13,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(14,    RXDFE_RPT_14,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(15,    RXDFE_RPT_15,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(16,    RXDFE_RPT_16,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(17,    RXDFE_RPT_17,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(18,    RXDFE_RPT_18,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(19,    RXDFE_RPT_19,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(20,    RXDFE_RPT_20,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(21,    RXDFE_RPT_21,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(22,    RXDFE_RPT_22,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(23,    RXDFE_RPT_23,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(24,    RXDFE_RPT_24,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(25,    RXDFE_RPT_25,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(26,    RXDFE_RPT_26,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(27,    RXDFE_RPT_27,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(28,    RXDFE_RPT_28,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(29,    RXDFE_RPT_29,      SW_TRIGGER,     MOD_USR1_DSB)
+//BSI user
+DIGRF_DSB_NOR_USER_ID(30,    BSI_0,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(31,    BSI_1,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(32,    BSI_2,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(33,    BSI_3,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(34,    BSI_4,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(35,    BSI_5,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(36,    BSI_6,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(37,    BSI_7,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(38,    BSI_8,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(39,    BSI_9,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(40,    BSI_10,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(41,    BSI_11,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(42,    BSI_12,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(43,    BSI_13,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(44,    BSI_14,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(45,    BSI_15,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(46,    BSI_16,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(47,    BSI_17,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(48,    BSI_18,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(49,    BSI_19,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(50,    BSI_20,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(51,    BSI_21,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(52,    BSI_22,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(53,    BSI_23,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(54,    BSI_24,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(55,    BSI_25,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(56,    BSI_26,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(57,    BSI_27,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(58,    BSI_28,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(59,    BSI_29,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(60,    BSI_30,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(61,    BSI_31,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(62,    BSI_32,            SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(63,    BSI_33,            SW_TRIGGER,     MOD_USR2_DSB)
+//MIPI user
+DIGRF_DSB_NOR_USER_ID(64,    MIPI_0,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(65,    MIPI_1,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(66,    MIPI_2,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(67,    MIPI_3,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(68,    MIPI_4,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(69,    MIPI_5,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(70,    MIPI_6,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(71,    MIPI_7,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(72,    MIPI_8,            SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(73,    MIPI_9,            SW_TRIGGER,     MOD_USR2_DSB)
+//MM EVENT GEN user
+DIGRF_DSB_NOR_USER_ID(74,    MMEVTGEN_0,        HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(75,    MM_1,              SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(76,    MM_2,              SW_TRIGGER,     MOD_USR2_DSB)
+//RXDFE DC user
+DIGRF_DSB_NOR_USER_ID(77,    RXDFE_DC_0,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(78,    RXDFE_DC_1,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(79,    RXDFE_DC_2,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(80,    RXDFE_DC_3,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(81,    RXDFE_DC_4,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(82,    RXDFE_DC_5,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(83,    RXDFE_DC_6,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(84,    RXDFE_DC_7,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(85,    RXDFE_DC_8,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(86,    RXDFE_DC_9,        SW_TRIGGER,     MOD_USR1_DSB)
+//TxK user
+DIGRF_DSB_NOR_USER_ID(87,    TXK_0,             HW_TRIGGER,     MOD_USR3_DSB)
+DIGRF_DSB_NOR_USER_ID(88,    TXK_1,             HW_TRIGGER,     MOD_USR3_DSB)
+/**********************************************************/
+
+/**********************************************************/
+// DBG user part
+//TPC user
+DIGRF_DSB_DBG_USER_ID(0,     TPC_0,             SW_TRIGGER,     MOD_USR4_DSB)
+DIGRF_DSB_DBG_USER_ID(1,     TPC_1,             SW_TRIGGER,     MOD_USR4_DSB)
+DIGRF_DSB_DBG_USER_ID(2,     TPC_2,             SW_TRIGGER,     MOD_USR4_DSB)
+//RXDFE Log_Alg_C user
+DIGRF_DSB_DBG_USER_ID(3,     RXDFE_ALG_C_0,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(4,     RXDFE_ALG_C_1,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(5,     RXDFE_ALG_C_2,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(6,     RXDFE_ALG_C_3,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(7,     RXDFE_ALG_C_4,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(8,     RXDFE_ALG_C_5,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(9,     RXDFE_ALG_C_6,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(10,    RXDFE_ALG_C_7,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(11,    RXDFE_ALG_C_8,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(12,    RXDFE_ALG_C_9,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(13,    RXDFE_ALG_C_10,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(14,    RXDFE_ALG_C_11,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(15,    RXDFE_ALG_C_12,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(16,    RXDFE_ALG_C_13,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(17,    RXDFE_ALG_C_14,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(18,    RXDFE_ALG_C_15,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(19,    RXDFE_ALG_C_16,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(20,    RXDFE_ALG_C_17,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(21,    RXDFE_ALG_C_18,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(22,    RXDFE_ALG_C_19,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(23,    RXDFE_ALG_C_20,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(24,    RXDFE_ALG_C_21,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(25,    RXDFE_ALG_C_22,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(26,    RXDFE_ALG_C_23,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(27,    RXDFE_ALG_C_24,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(28,    RXDFE_ALG_C_25,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(29,    RXDFE_ALG_C_26,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(30,    RXDFE_ALG_C_27,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(31,    RXDFE_ALG_C_28,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(32,    RXDFE_ALG_C_29,    SW_TRIGGER,     MOD_USR5_DSB)
+//RXDFE Log_Alg_P user
+DIGRF_DSB_DBG_USER_ID(33,    RXDFE_ALG_P_0,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(34,    RXDFE_ALG_P_1,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(35,    RXDFE_ALG_P_2,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(36,    RXDFE_ALG_P_3,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(37,    RXDFE_ALG_P_4,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(38,    RXDFE_ALG_P_5,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(39,    RXDFE_ALG_P_6,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(40,    RXDFE_ALG_P_7,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(41,    RXDFE_ALG_P_8,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(42,    RXDFE_ALG_P_9,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(43,    RXDFE_ALG_P_10,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(44,    RXDFE_ALG_P_11,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(45,    RXDFE_ALG_P_12,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(46,    RXDFE_ALG_P_13,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(47,    RXDFE_ALG_P_14,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(48,    RXDFE_ALG_P_15,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(49,    RXDFE_ALG_P_16,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(50,    RXDFE_ALG_P_17,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(51,    RXDFE_ALG_P_18,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(52,    RXDFE_ALG_P_19,    SW_TRIGGER,     MOD_USR1_DSB)
+//BPI user
+DIGRF_DSB_DBG_USER_ID(53,    BPI_0,             HW_TRIGGER,     MOD_USR2_DSB)
+//MIPI
+DIGRF_DSB_DBG_USER_ID(54,    MIPI_0,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(55,    MIPI_1,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(56,    MIPI_2,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(57,    MIPI_3,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(58,    MIPI_4,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(59,    MIPI_5,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(60,    MIPI_6,            HW_TRIGGER,     MOD_USR2_DSB)
+//BSI user
+DIGRF_DSB_DBG_USER_ID(61,    BSI_0,             HW_TRIGGER,     MOD_USR2_DSB)
+//RXDFE log_rcc_fc user
+DIGRF_DSB_DBG_USER_ID(62,    RXDFE_RCC_FC_0,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(63,    RXDFE_RCC_FC_1,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(64,    RXDFE_RCC_FC_2,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(65,    RXDFE_RCC_FC_3,    SW_TRIGGER,     MOD_USR1_DSB)
+//RXDFE log_rcc_agc user
+DIGRF_DSB_DBG_USER_ID(66,    RXDFE_RCC_AGC_0,   SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(67,    RXDFE_RCC_AGC_1,   SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(68,    RXDFE_RCC_AGC_2,   SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(69,    RXDFE_RCC_AGC_3,   SW_TRIGGER,     MOD_USR1_DSB)
+//TXDFE user
+DIGRF_DSB_DBG_USER_ID(70,    TXDFE_0,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(71,    TXDFE_1,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(72,    TXDFE_2,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(73,    TXDFE_3,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(74,    TXDFE_4,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(75,    TXDFE_5,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(76,    TXDFE_6,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(77,    TXDFE_7,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(78,    TXDFE_8,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(79,    TXDFE_9,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(80,    TXDFE_10,          HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(81,    TXDFE_11,          HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(82,    TXDFE_12,          HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(83,    TXDFE_13,          HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(84,    TXDFE_14,          HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(85,    TXDFE_15,          HW_TRIGGER,     MOD_USR1_DSB)
+//DVT user
+DIGRF_DSB_DBG_USER_ID(86,    DVT_0,             HW_TRIGGER,     MOD_USR1_DSB)
+//SW reserved
+DIGRF_DSB_DBG_USER_ID(87,    RESERVED_0,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(88,    RESERVED_1,        SW_TRIGGER,     MOD_USR1_DSB)
+/**********************************************************/
diff --git a/mcu/interface/driver/devdrv/digrf_platform/dsb_config/digrf_columbus_lite_config.h b/mcu/interface/driver/devdrv/digrf_platform/dsb_config/digrf_columbus_lite_config.h
new file mode 100644
index 0000000..1471da9
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/dsb_config/digrf_columbus_lite_config.h
@@ -0,0 +1,211 @@
+//DIGRF_DSB_USER_ID(channel number, USER_ID, HW_TRIGGER )
+//HW_TRIGGER: channel triggered by HW = 1  
+
+//normal user enum will be DIGRF_DSB_NOR_ID_XXX
+//ex : DIGRF_DSB_NOR_USER_ID(0, ABC, 0) will generate a enum
+//DIGRF_DSB_NOR_ID_ABC.
+//debug user enum will be DIGRF_DSB_DBG_ID_XXX
+//ex : DIGRF_DSB_DBG_USER_ID(0, ABC, 0) will generate a enum
+//DIGRF_DSB_DBG_ID_ABC.
+/**********************************************************/
+//NORMAL user part
+//RXDFE REPORT user id
+DIGRF_DSB_NOR_USER_ID(0,     RXDFE_RPT_0,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(1,     RXDFE_RPT_1,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(2,     RXDFE_RPT_2,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(3,     RXDFE_RPT_3,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(4,     RXDFE_RPT_4,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(5,     RXDFE_RPT_5,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(6,     RXDFE_RPT_6,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(7,     RXDFE_RPT_7,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(8,     RXDFE_RPT_8,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(9,     RXDFE_RPT_9,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(10,    RXDFE_RPT_10,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(11,    RXDFE_RPT_11,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(12,    RXDFE_RPT_12,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(13,    RXDFE_RPT_13,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(14,    RXDFE_RPT_14,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(15,    RXDFE_RPT_15,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(16,    RXDFE_RPT_16,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(17,    RXDFE_RPT_17,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(18,    RXDFE_RPT_18,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(19,    RXDFE_RPT_19,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(20,    RXDFE_RPT_20,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(21,    RXDFE_RPT_21,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(22,    RXDFE_RPT_22,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(23,    RXDFE_RPT_23,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(24,    RXDFE_RPT_24,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(25,    RXDFE_RPT_25,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(26,    RXDFE_RPT_26,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(27,    RXDFE_RPT_27,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(28,    RXDFE_RPT_28,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(29,    RXDFE_RPT_29,      SW_TRIGGER,     MOD_USR1_DSB)
+//BSI user
+DIGRF_DSB_NOR_USER_ID(30,    BSI_0,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(31,    BSI_1,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(32,    BSI_2,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(33,    BSI_3,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(34,    BSI_4,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(35,    BSI_5,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(36,    BSI_6,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(37,    BSI_7,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(38,    BSI_8,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(39,    BSI_9,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(40,    BSI_10,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(41,    BSI_11,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(42,    BSI_12,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(43,    BSI_13,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(44,    BSI_14,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(45,    BSI_15,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(46,    BSI_16,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(47,    BSI_17,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(48,    BSI_18,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(49,    BSI_19,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(50,    BSI_20,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(51,    BSI_21,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(52,    BSI_22,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(53,    BSI_23,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(54,    BSI_24,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(55,    BSI_25,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(56,    BSI_26,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(57,    BSI_27,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(58,    BSI_28,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(59,    BSI_29,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(60,    BSI_30,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(61,    BSI_31,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(62,    BSI_32,            SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(63,    BSI_33,            SW_TRIGGER,     MOD_USR2_DSB)
+//MIPI user
+DIGRF_DSB_NOR_USER_ID(64,    MIPI_0,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(65,    MIPI_1,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(66,    MIPI_2,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(67,    MIPI_3,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(68,    MIPI_4,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(69,    MIPI_5,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(70,    MIPI_6,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(71,    MIPI_7,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(72,    MIPI_8,            SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(73,    MIPI_9,            SW_TRIGGER,     MOD_USR2_DSB)
+//MM EVENT GEN user
+DIGRF_DSB_NOR_USER_ID(74,    MMEVTGEN_0,        HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(75,    MM_1,              SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(76,    MM_2,              SW_TRIGGER,     MOD_USR2_DSB)
+//RXDFE DC user
+DIGRF_DSB_NOR_USER_ID(77,    RXDFE_DC_0,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(78,    RXDFE_DC_1,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(79,    RXDFE_DC_2,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(80,    RXDFE_DC_3,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(81,    RXDFE_DC_4,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(82,    RXDFE_DC_5,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(83,    RXDFE_DC_6,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(84,    RXDFE_DC_7,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(85,    RXDFE_DC_8,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(86,    RXDFE_DC_9,        SW_TRIGGER,     MOD_USR1_DSB)
+//TxK user
+DIGRF_DSB_NOR_USER_ID(87,    TXK_0,             HW_TRIGGER,     MOD_USR3_DSB)
+DIGRF_DSB_NOR_USER_ID(88,    TXK_1,             HW_TRIGGER,     MOD_USR3_DSB)
+/**********************************************************/
+
+/**********************************************************/
+// DBG user part
+//TPC user
+DIGRF_DSB_DBG_USER_ID(0,     TPC_0,             SW_TRIGGER,     MOD_USR4_DSB)
+DIGRF_DSB_DBG_USER_ID(1,     TPC_1,             SW_TRIGGER,     MOD_USR4_DSB)
+DIGRF_DSB_DBG_USER_ID(2,     TPC_2,             SW_TRIGGER,     MOD_USR4_DSB)
+//RXDFE Log_Alg_C user
+DIGRF_DSB_DBG_USER_ID(3,     RXDFE_ALG_C_0,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(4,     RXDFE_ALG_C_1,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(5,     RXDFE_ALG_C_2,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(6,     RXDFE_ALG_C_3,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(7,     RXDFE_ALG_C_4,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(8,     RXDFE_ALG_C_5,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(9,     RXDFE_ALG_C_6,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(10,    RXDFE_ALG_C_7,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(11,    RXDFE_ALG_C_8,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(12,    RXDFE_ALG_C_9,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(13,    RXDFE_ALG_C_10,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(14,    RXDFE_ALG_C_11,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(15,    RXDFE_ALG_C_12,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(16,    RXDFE_ALG_C_13,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(17,    RXDFE_ALG_C_14,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(18,    RXDFE_ALG_C_15,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(19,    RXDFE_ALG_C_16,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(20,    RXDFE_ALG_C_17,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(21,    RXDFE_ALG_C_18,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(22,    RXDFE_ALG_C_19,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(23,    RXDFE_ALG_C_20,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(24,    RXDFE_ALG_C_21,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(25,    RXDFE_ALG_C_22,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(26,    RXDFE_ALG_C_23,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(27,    RXDFE_ALG_C_24,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(28,    RXDFE_ALG_C_25,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(29,    RXDFE_ALG_C_26,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(30,    RXDFE_ALG_C_27,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(31,    RXDFE_ALG_C_28,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(32,    RXDFE_ALG_C_29,    SW_TRIGGER,     MOD_USR5_DSB)
+//RXDFE Log_Alg_P user
+DIGRF_DSB_DBG_USER_ID(33,    RXDFE_ALG_P_0,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(34,    RXDFE_ALG_P_1,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(35,    RXDFE_ALG_P_2,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(36,    RXDFE_ALG_P_3,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(37,    RXDFE_ALG_P_4,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(38,    RXDFE_ALG_P_5,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(39,    RXDFE_ALG_P_6,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(40,    RXDFE_ALG_P_7,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(41,    RXDFE_ALG_P_8,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(42,    RXDFE_ALG_P_9,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(43,    RXDFE_ALG_P_10,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(44,    RXDFE_ALG_P_11,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(45,    RXDFE_ALG_P_12,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(46,    RXDFE_ALG_P_13,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(47,    RXDFE_ALG_P_14,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(48,    RXDFE_ALG_P_15,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(49,    RXDFE_ALG_P_16,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(50,    RXDFE_ALG_P_17,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(51,    RXDFE_ALG_P_18,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(52,    RXDFE_ALG_P_19,    SW_TRIGGER,     MOD_USR1_DSB)
+//BPI user
+DIGRF_DSB_DBG_USER_ID(53,    BPI_0,             HW_TRIGGER,     MOD_USR2_DSB)
+//MIPI
+DIGRF_DSB_DBG_USER_ID(54,    MIPI_0,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(55,    MIPI_1,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(56,    MIPI_2,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(57,    MIPI_3,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(58,    MIPI_4,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(59,    MIPI_5,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(60,    MIPI_6,            HW_TRIGGER,     MOD_USR2_DSB)
+//BSI user
+DIGRF_DSB_DBG_USER_ID(61,    BSI_0,             HW_TRIGGER,     MOD_USR2_DSB)
+//RXDFE log_rcc_fc user
+DIGRF_DSB_DBG_USER_ID(62,    RXDFE_RCC_FC_0,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(63,    RXDFE_RCC_FC_1,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(64,    RXDFE_RCC_FC_2,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(65,    RXDFE_RCC_FC_3,    SW_TRIGGER,     MOD_USR1_DSB)
+//RXDFE log_rcc_agc user
+DIGRF_DSB_DBG_USER_ID(66,    RXDFE_RCC_AGC_0,   SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(67,    RXDFE_RCC_AGC_1,   SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(68,    RXDFE_RCC_AGC_2,   SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(69,    RXDFE_RCC_AGC_3,   SW_TRIGGER,     MOD_USR1_DSB)
+//TXDFE user
+DIGRF_DSB_DBG_USER_ID(70,    ETDPD,             SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(71,    MIPI_7,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(72,    TXDFE_2,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(73,    TXDFE_3,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(74,    TXDFE_4,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(75,    TXDFE_5,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(76,    TXDFE_6,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(77,    TXDFE_7,           HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(78,    RESERVED_2,        HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(79,    RESERVED_3,        HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(80,    RESERVED_4,        HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(81,    RESERVED_5,        HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(82,    RESERVED_6,        HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(83,    RESERVED_7,        HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(84,    RESERVED_8,        HW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(85,    RESERVED_9,        HW_TRIGGER,     MOD_USR1_DSB)
+//DVT user
+DIGRF_DSB_DBG_USER_ID(86,    DVT_0,             HW_TRIGGER,     MOD_USR1_DSB)
+//SW reserved
+DIGRF_DSB_DBG_USER_ID(87,    RESERVED_0,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(88,    RESERVED_1,        SW_TRIGGER,     MOD_USR1_DSB)
+/**********************************************************/
diff --git a/mcu/interface/driver/devdrv/digrf_platform/dsb_config/digrf_columbus_p_config.h b/mcu/interface/driver/devdrv/digrf_platform/dsb_config/digrf_columbus_p_config.h
new file mode 100644
index 0000000..6f2a975
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/dsb_config/digrf_columbus_p_config.h
@@ -0,0 +1,231 @@
+//DIGRF_DSB_USER_ID(channel number, USER_ID, HW_TRIGGER )
+//HW_TRIGGER: channel triggered by HW = 1  
+
+//normal user enum will be DIGRF_DSB_NOR_ID_XXX
+//ex : DIGRF_DSB_NOR_USER_ID(0, ABC, 0) will generate a enum
+//DIGRF_DSB_NOR_ID_ABC.
+//debug user enum will be DIGRF_DSB_DBG_ID_XXX
+//ex : DIGRF_DSB_DBG_USER_ID(0, ABC, 0) will generate a enum
+//DIGRF_DSB_DBG_ID_ABC.
+/**********************************************************/
+//NORMAL user part
+//RXDFE REPORT user id
+DIGRF_DSB_NOR_USER_ID(0,     RXDFE_RPT_0,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(1,     RXDFE_RPT_1,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(2,     RXDFE_RPT_2,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(3,     RXDFE_RPT_3,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(4,     RXDFE_RPT_4,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(5,     RXDFE_RPT_5,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(6,     RXDFE_RPT_6,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(7,     RXDFE_RPT_7,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(8,     RXDFE_RPT_8,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(9,     RXDFE_RPT_9,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(10,    RXDFE_RPT_10,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(11,    RXDFE_RPT_11,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(12,    RXDFE_RPT_12,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(13,    RXDFE_RPT_13,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(14,    RXDFE_RPT_14,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(15,    RXDFE_RPT_15,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(16,    RXDFE_RPT_16,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(17,    RXDFE_RPT_17,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(18,    RXDFE_RPT_18,      SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(19,    RXDFE_RPT_19,      SW_TRIGGER,     MOD_USR1_DSB)
+//BSI user
+DIGRF_DSB_NOR_USER_ID(20,    BSI_0,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(21,    BSI_1,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(22,    BSI_2,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(23,    BSI_3,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(24,    BSI_4,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(25,    BSI_5,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(26,    BSI_6,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(27,    BSI_7,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(28,    BSI_8,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(29,    BSI_9,             HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(30,    BSI_10,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(31,    BSI_11,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(32,    BSI_12,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(33,    BSI_13,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(34,    BSI_14,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(35,    BSI_15,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(36,    BSI_16,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(37,    BSI_17,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(38,    BSI_18,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(39,    BSI_19,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(40,    BSI_20,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(41,    BSI_21,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(42,    BSI_22,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(43,    BSI_23,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(44,    BSI_24,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(45,    BSI_25,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(46,    BSI_26,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(47,    BSI_27,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(48,    BSI_28,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(49,    BSI_29,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(50,    BSI_30,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(51,    BSI_31,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(52,    BSI_32,            SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(53,    BSI_33,            SW_TRIGGER,     MOD_USR2_DSB)
+//MIPI user
+DIGRF_DSB_NOR_USER_ID(54,    MIPI_0,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(55,    MIPI_1,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(56,    MIPI_2,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(57,    MIPI_3,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(58,    MIPI_4,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(59,    MIPI_5,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(60,    MIPI_6,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(61,    MIPI_7,            HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(62,    MIPI_8,            SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(63,    MIPI_9,            SW_TRIGGER,     MOD_USR2_DSB)
+//MM EVENT GEN user
+DIGRF_DSB_NOR_USER_ID(64,    MMEVTGEN_0,        HW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(65,    MM_1,              SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(66,    MM_2,              SW_TRIGGER,     MOD_USR2_DSB)
+//MIXEDSYS user
+DIGRF_DSB_NOR_USER_ID(67,    MIXEDSYS_0,        SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(68,    MIXEDSYS_1,        SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_NOR_USER_ID(69,    MIXEDSYS_2,        SW_TRIGGER,     MOD_USR2_DSB)
+//RXDFE DC user
+DIGRF_DSB_NOR_USER_ID(70,    RXDFE_DC_0,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(71,    RXDFE_DC_1,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(72,    RXDFE_DC_2,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(73,    RXDFE_DC_3,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(74,    RXDFE_DC_4,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(75,    RXDFE_DC_5,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(76,    RXDFE_DC_6,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(77,    RXDFE_DC_7,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(78,    RXDFE_DC_8,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(79,    RXDFE_DC_9,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(80,    RXDFE_DC_10,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(81,    RXDFE_DC_11,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(82,    RXDFE_DC_12,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(83,    RXDFE_DC_13,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(84,    RXDFE_DC_14,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(85,    RXDFE_DC_15,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(86,    RXDFE_DC_16,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(87,    RXDFE_DC_17,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(88,    RXDFE_DC_18,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(89,    RXDFE_DC_19,       SW_TRIGGER,     MOD_USR1_DSB)
+//RXDFE ISR user
+DIGRF_DSB_NOR_USER_ID(90,    RXDFE_ISR_0,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(91,    RXDFE_ISR_1,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(92,    RXDFE_ISR_2,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(93,    RXDFE_ISR_3,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(94,    RXDFE_ISR_4,       SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_NOR_USER_ID(95,    RXDFE_ISR_5,       SW_TRIGGER,     MOD_USR1_DSB)
+//TXK user
+DIGRF_DSB_NOR_USER_ID(96,    TXK_0,       		SW_TRIGGER,     MOD_USR3_DSB)
+DIGRF_DSB_NOR_USER_ID(97,    TXK_1,       		SW_TRIGGER,     MOD_USR3_DSB)
+/**********************************************************/
+
+/**********************************************************/
+// DBG user part
+
+//SW reserved
+DIGRF_DSB_DBG_USER_ID(0,     RESERVED_0,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(1,     RESERVED_1,        SW_TRIGGER,     MOD_USR1_DSB)
+//TPC user
+DIGRF_DSB_DBG_USER_ID(2,     TPC_0,             SW_TRIGGER,     MOD_USR4_DSB)
+DIGRF_DSB_DBG_USER_ID(3,     TPC_1,             SW_TRIGGER,     MOD_USR4_DSB)
+DIGRF_DSB_DBG_USER_ID(4,     TPC_2,             SW_TRIGGER,     MOD_USR4_DSB)
+//RXDFE Log_Alg_C user
+DIGRF_DSB_DBG_USER_ID(5,     RXDFE_ALG_C_0,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(6,     RXDFE_ALG_C_1,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(7,     RXDFE_ALG_C_2,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(8,     RXDFE_ALG_C_3,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(9,     RXDFE_ALG_C_4,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(10,    RXDFE_ALG_C_5,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(11,    RXDFE_ALG_C_6,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(12,    RXDFE_ALG_C_7,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(13,    RXDFE_ALG_C_8,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(14,    RXDFE_ALG_C_9,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(15,    RXDFE_ALG_C_10,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(16,    RXDFE_ALG_C_11,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(17,    RXDFE_ALG_C_12,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(18,    RXDFE_ALG_C_13,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(19,    RXDFE_ALG_C_14,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(20,    RXDFE_ALG_C_15,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(21,    RXDFE_ALG_C_16,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(22,    RXDFE_ALG_C_17,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(23,    RXDFE_ALG_C_18,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(24,    RXDFE_ALG_C_19,    SW_TRIGGER,     MOD_USR1_DSB)
+//RXDFE Log_Alg_P user
+DIGRF_DSB_DBG_USER_ID(25,    RXDFE_ALG_P_0,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(26,    RXDFE_ALG_P_1,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(27,    RXDFE_ALG_P_2,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(28,    RXDFE_ALG_P_3,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(29,    RXDFE_ALG_P_4,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(30,    RXDFE_ALG_P_5,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(31,    RXDFE_ALG_P_6,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(32,    RXDFE_ALG_P_7,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(33,    RXDFE_ALG_P_8,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(34,    RXDFE_ALG_P_9,     SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(35,    RXDFE_ALG_P_10,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(36,    RXDFE_ALG_P_11,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(37,    RXDFE_ALG_P_12,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(38,    RXDFE_ALG_P_13,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(39,    RXDFE_ALG_P_14,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(40,    RXDFE_ALG_P_15,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(41,    RXDFE_ALG_P_16,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(42,    RXDFE_ALG_P_17,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(43,    RXDFE_ALG_P_18,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(44,    RXDFE_ALG_P_19,    SW_TRIGGER,     MOD_USR1_DSB)
+//BPI user
+DIGRF_DSB_DBG_USER_ID(45,    BPI_0,             HW_TRIGGER,     MOD_USR2_DSB)
+//MIPI
+DIGRF_DSB_DBG_USER_ID(46,    MIPI_0,            SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(47,    MIPI_1,            SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(48,    MIPI_2,            SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(49,    MIPI_3,            SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(50,    MIPI_4,            SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(51,    MIPI_5,            SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(52,    MIPI_6,            SW_TRIGGER,     MOD_USR2_DSB)
+DIGRF_DSB_DBG_USER_ID(53,    MIPI_7,            SW_TRIGGER,     MOD_USR2_DSB)
+//BSI user
+DIGRF_DSB_DBG_USER_ID(54,    BSI_0,             SW_TRIGGER,     MOD_USR2_DSB)
+//RXDFE SW DBG user
+DIGRF_DSB_DBG_USER_ID(55,    RXDFE_SW_DBG_0,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(56,    RXDFE_SW_DBG_1,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(57,    RXDFE_SW_DBG_2,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(58,    RXDFE_SW_DBG_3,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(59,    RXDFE_SW_DBG_4,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(60,    RXDFE_SW_DBG_5,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(61,    RXDFE_SW_DBG_6,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(62,    RXDFE_SW_DBG_7,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(63,    RXDFE_SW_DBG_8,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(64,    RXDFE_SW_DBG_9,    SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(65,    RXDFE_SW_DBG_10,   SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(66,    RXDFE_SW_DBG_11,   SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(67,    RXDFE_SW_DBG_12,   SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(68,    RXDFE_SW_DBG_13,   SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(69,    RXDFE_SW_DBG_14,   SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(70,    RXDFE_SW_DBG_15,   SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(71,    RXDFE_SW_DBG_16,   SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(72,    RXDFE_SW_DBG_17,   SW_TRIGGER,     MOD_USR5_DSB)
+DIGRF_DSB_DBG_USER_ID(73,    RXDFE_SW_DBG_18,   SW_TRIGGER,     MOD_USR5_DSB)
+//RXDFE log_rcc_fc user
+DIGRF_DSB_DBG_USER_ID(74,    RXDFE_RCC_FC_0,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(75,    RXDFE_RCC_FC_1,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(76,    RXDFE_RCC_FC_2,    SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(77,    RXDFE_RCC_FC_3,    SW_TRIGGER,     MOD_USR1_DSB)
+//RXDFE log_rcc_agc user
+DIGRF_DSB_DBG_USER_ID(78,    RXDFE_RCC_AGC_0,   SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(79,    RXDFE_RCC_AGC_1,   SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(80,    RXDFE_RCC_AGC_2,   SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(81,    RXDFE_RCC_AGC_3,   SW_TRIGGER,     MOD_USR1_DSB)
+//TXDFE user
+DIGRF_DSB_DBG_USER_ID(82,    TXDFE_0,           SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(83,    TXDFE_1,           SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(84,    TXDFE_2,           SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(85,    TXDFE_3,           SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(86,    TXDFE_4,           SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(87,    TXDFE_5,           SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(88,    TXDFE_6,           SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(89,    TXDFE_7,           SW_TRIGGER,     MOD_USR1_DSB)
+//DVT user
+DIGRF_DSB_DBG_USER_ID(90,    DVT_0,             SW_TRIGGER,     MOD_USR1_DSB)
+//RESERVED
+DIGRF_DSB_DBG_USER_ID(91,    RESERVED_2,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(92,    RESERVED_3,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(93,    RESERVED_4,        SW_TRIGGER,     MOD_USR1_DSB)
+DIGRF_DSB_DBG_USER_ID(94,    RESERVED_5,        SW_TRIGGER,     MOD_USR1_DSB)
+/**********************************************************/
diff --git a/mcu/interface/driver/devdrv/digrf_platform/dsb_config/digrf_dsb_mpu_cfg.h b/mcu/interface/driver/devdrv/digrf_platform/dsb_config/digrf_dsb_mpu_cfg.h
new file mode 100644
index 0000000..930295a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/digrf_platform/dsb_config/digrf_dsb_mpu_cfg.h
@@ -0,0 +1,13 @@
+/*
+DIGRF_DSB_MPU_CFG(index, start, end, mask)
+	index	: MPU channel index
+	start	: MPU start address
+	end		: MPU end address
+	mask	: MPU address mask
+*/
+/**********************************************************/
+//					index,		start					end						mask
+DIGRF_DSB_MPU_CFG(	0,     		0x00000000,     		0xFFFFFFFF,     		0)
+DIGRF_DSB_MPU_CFG(	1,     		0x00000000,     		0xFFFFFFFF,     		0)
+DIGRF_DSB_MPU_CFG(	2,     		0x00000000,     		0xFFFFFFFF,     		0)
+DIGRF_DSB_MPU_CFG(	3,     		0x00000000,     		0xFFFFFFFF,     		0)
\ No newline at end of file
diff --git a/mcu/interface/driver/devdrv/ect/ect.h b/mcu/interface/driver/devdrv/ect/ect.h
new file mode 100644
index 0000000..2531c98
--- /dev/null
+++ b/mcu/interface/driver/devdrv/ect/ect.h
@@ -0,0 +1,264 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   ect.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *   This Module defines the HW initialization.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef ECT_H
+#define ECT_H
+
+#include "kal_general_types.h"
+
+/* channel setting */
+#define CH_NON  (0x0)
+#define CH_DBG  (0x1 << 0)
+//#define CH_DBG  CH_NON
+#define CH_RST  (0x1 << 1)
+#define CH_EXP  (0x1 << 2)
+
+
+
+
+
+#if (defined (__MD97P__) )
+#define ECT_SRC_NONE        (0x0)
+#define ECT_SRC_IA          (0x1 << 0)
+#define ECT_SRC_USIP    	(0x1 << 1)
+#define ECT_SRC_RAKE      	(0x1 << 2)
+#define ECT_SRC_SCQ         (0X1 << 3)
+#define ECT_SRC_MCORE       (0X1 << 4)
+#define ECT_SRC_VCORE       (0X1 << 5)
+
+#define ECT_SRC_USIP0_0     (0X1 << 8)
+#define ECT_SRC_USIP0_1     (0X1 << 9)
+#define ECT_SRC_USIP1_0     (0X1 << 10)
+#define ECT_SRC_USIP1_1     (0x1 << 11)
+
+#define ECT_SRC_SCQ0_0      (0x1 << 12)
+#define ECT_SRC_SCQ0_1      (0x1 << 13)
+#define ECT_SRC_SCQ1_0      (0x1 << 14)
+#define ECT_SRC_SCQ1_1      (0x1 << 15)
+
+#define ECT_SRC_MCORE0_0    (0x1 << 16)
+#define ECT_SRC_MCORE0_1    (0x1 << 17)
+#define ECT_SRC_MCORE0_2    (0x1 << 18)
+#define ECT_SRC_MCORE0_3    (0x1 << 19)
+#define ECT_SRC_MCORE0      (ECT_SRC_MCORE0_0|ECT_SRC_MCORE0_1|ECT_SRC_MCORE0_2|ECT_SRC_MCORE0_3)
+
+#define ECT_SRC_MCORE1_0    (0x1 << 20)
+#define ECT_SRC_MCORE1_1    (0x1 << 21)
+#define ECT_SRC_MCORE1_2    (0x1 << 22)
+#define ECT_SRC_MCORE1_3    (0x1 << 23)
+#define ECT_SRC_MCORE1      (ECT_SRC_MCORE1_0|ECT_SRC_MCORE1_1|ECT_SRC_MCORE1_2|ECT_SRC_MCORE1_3)
+
+#define ECT_SRC_VCORE0_0    (0x1 << 24)
+#define ECT_SRC_VCORE0_1    (0x1 << 25)
+#define ECT_SRC_VCORE0_2    (0x1 << 26)
+#define ECT_SRC_VCORE0_3    (0x1 << 27)
+#define ECT_SRC_VCORE0      (ECT_SRC_VCORE0_0|ECT_SRC_VCORE0_1|ECT_SRC_VCORE0_2|ECT_SRC_VCORE0_3)
+
+
+#elif (defined (__MD97__))
+#define ECT_SRC_NONE        (0x0)
+#define ECT_SRC_IA          (0x1 << 0)
+#define ECT_SRC_USIP    	(0x1 << 1)
+#define ECT_SRC_RAKE      	(0x1 << 2)
+#define ECT_SRC_SCQ         (0X1 << 3)
+#define ECT_SRC_MCORE       (0X1 << 4)
+#define ECT_SRC_VCORE       (0X1 << 5)
+
+#define ECT_SRC_USIP0_0     (0X1 << 8)
+#define ECT_SRC_USIP0_1     (0X1 << 9)
+#define ECT_SRC_USIP1_0     (0X1 << 10)
+#define ECT_SRC_USIP1_1     (0x1 << 11)
+
+#define ECT_SRC_SCQ0_0      (0x1 << 12)
+#define ECT_SRC_SCQ0_1      (0x1 << 13)
+#define ECT_SRC_SCQ1_0      (0x1 << 14)
+#define ECT_SRC_SCQ1_1      (0x1 << 15)
+
+#define ECT_SRC_MCORE0_0    (0x1 << 16)
+#define ECT_SRC_MCORE0_1    (0x1 << 17)
+#define ECT_SRC_MCORE0_2    (0x1 << 18)
+#define ECT_SRC_MCORE0_3    (0x1 << 19)
+#define ECT_SRC_MCORE0      (ECT_SRC_MCORE0_0|ECT_SRC_MCORE0_1|ECT_SRC_MCORE0_2|ECT_SRC_MCORE0_3)
+
+#define ECT_SRC_MCORE1_0    (0x1 << 20)
+#define ECT_SRC_MCORE1_1    (0x1 << 21)
+#define ECT_SRC_MCORE1_2    (0x1 << 22)
+#define ECT_SRC_MCORE1_3    (0x1 << 23)
+#define ECT_SRC_MCORE1      (ECT_SRC_MCORE1_0|ECT_SRC_MCORE1_1|ECT_SRC_MCORE1_2|ECT_SRC_MCORE1_3)
+
+#define ECT_SRC_VCORE0_0    (0x1 << 24)
+#define ECT_SRC_VCORE0_1    (0x1 << 25)
+#define ECT_SRC_VCORE0_2    (0x1 << 26)
+#define ECT_SRC_VCORE0_3    (0x1 << 27)
+#define ECT_SRC_VCORE0      (ECT_SRC_VCORE0_0|ECT_SRC_VCORE0_1|ECT_SRC_VCORE0_2|ECT_SRC_VCORE0_3)
+
+
+
+
+#else  // Gen93/95
+
+#define ECT_SRC_NONE    	(0x0)
+#define ECT_SRC_IA			(0x1 << 0)
+#define ECT_SRC_USIP    	(0x1 << 1)
+#define ECT_SRC_RAKE      	(0x1 << 2)
+#define ECT_SRC_SCQ         (0X1 << 3)
+#define ECT_SRC_USIP0_0     (0X1 << 4)
+#define ECT_SRC_USIP0_1     (0X1 << 5)
+#define ECT_SRC_USIP1_0     (0X1 << 6)
+#define ECT_SRC_USIP1_1     (0x1 << 7)
+#define ECT_SRC_SCQ0	    (0x1 << 8)
+#define ECT_SRC_SCQ1        (0x1 << 9)
+
+
+#endif  //if defined (__MD97__)
+
+#define ECT_SRC_INVALID_VPE (0xFFFFFFFF)
+
+/*IA&USIP TriggerIn*/
+#define IA_TRIGGERIN          (7)
+#define USIP_TRIGGERIN        (5)
+                              
+#define IA_TRIGGERIN_MASK     (1 << IA_TRIGGERIN)
+#define USIP_TRIGGERIN_MASK   (1 << USIP_TRIGGERIN)
+                              
+                              
+/*IA&USIP TriggerOut*/             
+#define IA_TRIGGEROUT         (3)
+#define USIP_TRIGGEROUT       (7)
+
+#define IA_TRIGGEROUT_MASK    (1 << IA_TRIGGEROUT)
+#define USIP_TRIGGEROUT_MASK  (1 << USIP_TRIGGEROUT)
+
+/*DSP TriggerIn*/
+#define RAKE_TRIGGERIN        (3)
+#define SCQ_TRIGGERIN         (2)
+#define MCORE_TRIGGERIN       (7)
+#define VCORE_TRIGGERIN       (5)
+                              
+#define RAKE_TRIGGERIN_MASK   (1 << RAKE_TRIGGERIN)
+#define SCQ_TRIGGERIN_MASK    (1 << SCQ_TRIGGERIN)
+#define MCORE_TRIGGERIN_MASK  (1 << MCORE_TRIGGERIN)
+#define VCORE_TRIGGERIN_MASK  (1 << VCORE_TRIGGERIN)
+                              
+/*DSP TriggerOut*/            
+#define MCORE_TRIGGEROUT      (7)
+#define VCORE_TRIGGEROUT      (6)
+#define RAKE_TRIGGEROUT       (5)
+#define SCQ_TRIGGEROUT        (4)
+                              
+#define MCORE_TRIGGEROUT_MASK (1 << MCORE_TRIGGEROUT)
+#define VCORE_TRIGGEROUT_MASK (1 << VCORE_TRIGGEROUT)
+#define RAKE_TRIGGEROUT_MASK  (1 << RAKE_TRIGGEROUT)
+#define SCQ_TRIGGEROUT_MASK   (1 << SCQ_TRIGGEROUT)
+
+#define TRIGGERIN_DEFAULT_VAL (0x40)
+
+#if (defined (__MD97__) || defined (__MD97P__) )
+#define BASE_MADDR_DBGSYS_1 BASE_MADDR_MDPERI_MDDBGSYS
+#endif  //if defined (__MD97__)
+
+#define IA_USIP_CTI           (BASE_MADDR_DBGSYS_1+0xC000)
+#define DSP_CTI               (BASE_MADDR_DBGSYS_1+0xD000)
+#define DBG_AO_MISC           (BASE_MADDR_DBGSYS_1+0xE000)
+#define DEM_BASE              (BASE_MADDR_DBGSYS_1+0x1100)
+
+
+#define BASE_MADDR_MD_CTI     (IA_USIP_CTI)
+#define BASE_MADDR_DSP_CTI    (DSP_CTI)
+
+
+void  ECT_Init(void);
+void ECT_Hdlr(kal_uint32 vector);
+void ECT_TrgExcp(void);
+kal_uint32 ECT_Query(void);
+kal_uint32 ECT_IsEnabled(void);
+
+kal_uint32 ECT_GetMDTriggerOut(void);
+kal_uint32 ECT_GetDSPTriggerOut(void);
+kal_uint32 ECT_GetMDTriggerIn(void);
+kal_uint32 ECT_GetDSPTriggerIn(void);
+
+// DSP CTI status APIs
+#if (defined (__MD97__) || defined (__MD97P__) )
+
+kal_uint32 ECT_Get_Usip_CTI_Status(void);
+kal_uint32 ECT_Get_Scq16_CTI_Status(void);
+kal_uint32 ECT_Get_MCORE_CTI_Status(void);
+kal_uint32 ECT_Get_VCORE_CTI_Status(void);
+
+
+#elif defined (__MD95__) || defined (__MD93__)
+
+kal_uint32 ECT_Get_Usip_CTI_Status(void);
+kal_uint32 ECT_Get_Scq16_CTI_Status(void);
+
+
+#else // if defined (__MD95__) || defined (__MD93__)
+   #error "unsupported Generation"
+#endif  //if defined (__MD97__)  
+
+
+#endif /* ECT_H */
diff --git a/mcu/interface/driver/devdrv/eint/eint.h b/mcu/interface/driver/devdrv/eint/eint.h
new file mode 100644
index 0000000..90955b2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/eint/eint.h
@@ -0,0 +1,592 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE. 
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *    eint.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *   This files define external interrupt constants definition
+ *
+ * Author:
+ * -------
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __EINT_H__
+#define __EINT_H__
+
+#include "kal_general_types.h"
+#include "dcl.h"
+#include "intrCtrl.h"
+//#include "Eint_internal.h"
+#include "eint_sw.h"
+
+ /*************************************************************************
+  * EINT Configuration
+  *************************************************************************/
+#define  LEVEL_HIGH           KAL_TRUE
+#define  LEVEL_LOW            KAL_FALSE
+#define  EINT_MASK_EINT0      0x00000001
+#define  EINT_INTACK_EINT0    0x00000001
+#define  EINT_STATUS_EINT0    0x00000001
+
+#if defined(__CIRQ_DESIGN_NEW__)
+   #define  EINTaddr(_no)  (*(volatile kal_uint16 *)(EINT0_CON+_no))
+#else
+   #define  EINTaddr(_no)  (*(volatile kal_uint16 *)(EINT0_CON+(0x4*_no)))
+#endif
+
+   #define  EINT_MASK_EINT(_no)  (EINT_MASK_EINT0 << (_no))
+   #define  EINT_INTACK_EINT(_no)  (EINT_INTACK_EINT0 << (_no))
+   #define  EINT_STATUS_EINT(_no)  (EINT_STATUS_EINT0 << (_no))
+
+   #define  EINT_CON_HIGHLEVEL   0x0800
+   #define  EINT_CON_LOWLEVEL    0x0000
+   #define  EINT_CON_DEBOUNCE    0x07ff
+   #define  EINT_CON_DEBOUNCE_EN 0x8000
+
+   #define EINT_CHANNEL_NOT_EXIST   EINT_TOTAL_CHANNEL
+   
+/*Engineering mode*/
+typedef enum 
+{
+   aux_eint_chann,
+   chrdet_eint_chann,
+   melody_eint_chann,
+   clamdet_eint_chann,
+   touch_panel_eint_chann,
+   usb_eint_chann,
+   chr_usb_eint_chann,
+   bt_eint_chann,
+   swdbg_eint_chann,
+   motion_senosr_eint_chann,
+   tdmb_eint_chann,
+   cmmb_eint_chann,
+   wifi_eint_chann,
+   otg_idpin_eint_chann,
+   sync_lcm_chann,
+   extra_a_key_eint_chann,
+   extra_b_key_eint_chann,
+   gps_eint_chann,
+   dcam_vsync_eint_chann,
+   jogball_up_eint_chann,
+   jogball_down_eint_chann,
+   jogball_right_eint_chann,
+   jogball_left_eint_chann,
+   bt_co_clock_eint_chann,
+   wifi_co_clock_eint_chann
+} eint_channel_type;
+#if defined(__MD93__)
+typedef struct 
+{
+   DCL_HANDLE eint_sw_debounce_handle;
+   kal_bool eint_intr_allow;
+   kal_uint8 eint_no;
+} EINT_SW_DEBOUNCE_STRUCT;
+#elif defined(__MD95__)
+#elif defined(__MD97__)
+#elif defined(__MD97P__)
+#else
+#error "no chip match"
+#endif
+typedef struct 
+{
+ 	void (*eint_func[EINT_TOTAL_CHANNEL])(void);
+  	kal_bool eint_active[EINT_TOTAL_CHANNEL];
+	kal_bool eint_auto_umask[EINT_TOTAL_CHANNEL];
+} eint_func;
+   
+typedef struct 
+{
+ 	void (*deint_func[DEDICATED_EINT_TOTAL_CHANNEL])(void);
+  	kal_bool deint_active[DEDICATED_EINT_TOTAL_CHANNEL];
+	kal_bool deint_auto_umask[DEDICATED_EINT_TOTAL_CHANNEL];
+} dedicated_eint_func;
+       
+extern void EINT_Registration(kal_uint8 eintno, kal_bool Dbounce_En, kal_bool ACT_Polarity, void (reg_hisr)(void), kal_bool auto_umask);
+extern void EXTRA_EINT_Registration(kal_uint8 eintno, kal_bool ACT_Polarity, void (reg_hisr)(void), kal_bool auto_umask);
+extern void DEINT_Registration(kal_uint8 deintno,void (reg_hisr)(void));
+extern kal_uint32 EINT_Query_HW_Debounce(void);
+extern void EINT_Set_HW_Debounce(kal_uint8 eintno, kal_uint32 ms);
+extern void EINT_Set_HW_Debounce_Enable(kal_uint8 eintno, kal_uint32 debounce_en);
+extern void EINT_Set_Polarity(kal_uint8 eintno, kal_bool ACT_Polarity);
+extern kal_uint32 EINT_Set_Sensitivity(kal_uint8 eintno, kal_bool sens);
+extern void EINT_LISR(kal_uint32 irq_id);
+extern void EINT_Mask(kal_uint8 eintno);
+extern void EINT_UnMask(kal_uint8 eintno);
+extern kal_uint32 EINT_SaveAndMask(kal_uint8 eintno);
+extern void EINT_RestoreMask(kal_uint8 eintno, kal_uint32 val);
+//extern void EINT_DISABLE(kal_uint8 eintno); 
+#if defined(__MD93__)
+extern kal_int32 EINT_SW_Debounce_Modify(kal_uint8 eintno, kal_uint8 debounce_time);
+#elif defined(__MD95__)
+#elif defined(__MD97__)
+#elif defined(__MD97P__)
+#else
+#error "no chip match"
+#endif
+extern kal_uint32 EINT_SaveAndMaskAll(void);
+extern void EINT_RestoreMaskAll(kal_uint32 val);
+extern void EINT_SetSWRegister(kal_uint8 eintno);
+extern void EINT_ResetSWRegister(kal_uint8 eintno);
+
+extern void SWWAR_EINT_Registration(kal_uint8 eintno, kal_bool Dbounce_En, kal_bool ACT_Polarity);
+extern void SWWAR_EINT_LISR_Registration(kal_uint8 eintno, void (*reg_lisr)(void));
+extern void SWWAR_EINT_LISR(void);
+extern void SWWAR_EINT_First_UnMask(kal_uint8 eintno);
+//for MT6290 to set HW debounce 32k cycle, which is maximum persion
+extern void EINT_Set_HW_Debounce_32KCycle(kal_uint8 eintno, kal_uint32 count_of_32kcycle);
+
+/*************************************************************************
+ * Customized functions' prototype
+ *************************************************************************/
+extern kal_uint8 *custom_config_eint_sw_debounce_time_delay(void);
+extern kal_uint8 custom_eint_get_channel(eint_channel_type type);   
+#endif /* __EINT_H__ */
+
diff --git a/mcu/interface/driver/devdrv/eint/eint_sw.h b/mcu/interface/driver/devdrv/eint/eint_sw.h
new file mode 100644
index 0000000..6959d87
--- /dev/null
+++ b/mcu/interface/driver/devdrv/eint/eint_sw.h
@@ -0,0 +1,287 @@
+#ifndef __MT6290_EINT_SW_H__
+#define __MT6290_EINT_SW_H__
+#include "irqid.h"
+#include "drv_comm.h"
+#include "intrCtrl.h"
+//#include "kal_debug.h"
+//#include "eint_hw.h"
+#ifdef __CUST_NEW__
+#include "eint_drv.h"
+#endif
+
+#define  IRQ_EIT_CODE     IRQ_EINT_SHARE_CODE
+#define  DEDICATED_EINT_IRQ0  IRQ_EINT0_CODE
+#define  DEDICATED_EINT_IRQ1  IRQ_EINT1_CODE
+#define  DEDICATED_EINT_IRQ2  IRQ_EINT2_CODE
+#define  DEDICATED_EINT_IRQ3  IRQ_EINT3_CODE
+
+#if defined(__MD97__) || defined(__MD97P__)
+#define  DEDICATED_EINT_TOTAL_CHANNEL 4
+#define  EINT_MAX_CHANNEL     12
+#define  EINT_TOTAL_CHANNEL   12
+#define  EINT_SRCPIN_HWTIED0	12
+#define  EINT_SRC_PIN_MAX     13
+#else
+#define  DEDICATED_EINT_TOTAL_CHANNEL 4
+#define  EINT_MAX_CHANNEL     4
+#define  EINT_TOTAL_CHANNEL   4
+#define  EINT_SRCPIN_HWTIED0	4
+#define  EINT_SRC_PIN_MAX     5
+#endif
+//only for mt6297,As not support dws
+#if defined(MT6297)
+//For SIM
+#define SIM1_SWAP_EINT_SRCPIN  1
+#define SIM1_SWAP_EINT_NUM     1
+#define SIM2_SWAP_EINT_SRCPIN  2
+#define SIM2_SWAP_EINT_NUM     2
+
+//For TYPEC/USB
+#define TYPEC_OE_EINT_SRCPIN   7
+#define TYPEC_OE_EINT_NUM      7
+#define USB_RESUME_EINT_SRCPIN 11
+#define USB_RESUME_EINT_NUM    11
+#endif
+
+#if defined(CHIP10992)
+	#define PCIE1_EINT_SRCPIN	6
+	#define PCIE1_EINT_NUM		6
+	#define PCIE2_EINT_SRCPIN 	8
+	#define PCIE2_EINT_NUM    	8
+	#define USB_RESUME_EINT_SRCPIN 11
+	#define USB_RESUME_EINT_NUM    11
+#endif
+#ifdef __CUST_NEW__
+#define  EINT_HARDWARE_DEBOUNCE (((EINT0_DEBOUNCE_TIME_DELAY>0)?1:0)<<0 | ((EINT1_DEBOUNCE_TIME_DELAY>0)?1:0)<<1 | ((EINT2_DEBOUNCE_TIME_DELAY>0)?1:0)<<2 |\
+                                ((EINT3_DEBOUNCE_TIME_DELAY>0)?1:0)<<3 | ((EINT4_DEBOUNCE_TIME_DELAY>0)?1:0)<<4 | ((EINT5_DEBOUNCE_TIME_DELAY>0)?1:0)<<5 |\
+                                ((EINT6_DEBOUNCE_TIME_DELAY>0)?1:0)<<6 | ((EINT7_DEBOUNCE_TIME_DELAY>0)?1:0)<<7 | ((EINT8_DEBOUNCE_TIME_DELAY>0)?1:0)<<8 |\
+                                ((EINT9_DEBOUNCE_TIME_DELAY>0)?1:0)<<9 | ((EINT10_DEBOUNCE_TIME_DELAY>0)?1:0)<<10 |((EINT11_DEBOUNCE_TIME_DELAY>0)?1:0)<<11|\
+                                ((EINT12_DEBOUNCE_TIME_DELAY>0)?1:0)<<12|((EINT13_DEBOUNCE_TIME_DELAY>0)?1:0)<<13| ((EINT14_DEBOUNCE_TIME_DELAY>0)?1:0)<<14|\
+                                ((EINT15_DEBOUNCE_TIME_DELAY>0)?1:0)<<15)
+#else
+#define EINT_HARDWARE_DEBOUNCE 0x0000000F
+#endif
+
+#define  EINT_OWNERSHIP_AP  1
+#define  EINT_OWNERSHIP_MD  0
+#define  EINT_NEGATIVE_POLARITY			0
+#define  EINT_POSITIVE_POLARITY			1
+
+
+#define  EINT_SRC_OFFSET	0x4
+#define  EINT_SRC_NUM_PER_REG 4
+#define  EINT_SRC_SHIFT_BIT  8
+
+#define BU_G_FLD(_i,_ms,_ls)	    (((_i)<<(31-(_ms))) >> (31- (_ms) + (_ls)))
+#define BU_G_BIT(_i,_n)				BU_G_FLD(_i, _n, _n)
+#ifdef __MTK_TARGET__
+#define EN_EINT_PRINTF  1
+
+#if EN_EINT_PRINTF
+extern void dbg_print(char *fmt,...);
+
+#define EINT_PRINT(fmt, var ...)	do {dbg_print(fmt"\n\r", ##var);} while (0)
+#define EINT_PRINTN(fmt, var ...)	do {dbg_print(fmt, ##var);} while (0)
+#define EINT_ERR(fmt, var ...)		do {EINT_PRINT("ERROR [%s:%d]"fmt, __FUNCTION__, __LINE__, ##var);} while (0)
+#define EINT_WARN(fmt, var ...)	do {EINT_PRINT("WARNING [%s:%d]"fmt, __FUNCTION__, __LINE__, ##var);} while (0)
+#else 
+#define EINT_PRINT(fmt, var ...)	
+#define EINT_PRINTN(fmt, var ...)	
+#define EINT_ERR(fmt, var ...)		
+#define EINT_WARN(fmt, var ...)	
+#endif
+#endif
+#define REG32(addr)					(*((volatile unsigned int*)(addr)))
+#define REG32_WRITE(addr, value)		do {(*((volatile unsigned int*)(addr))) = (unsigned int)(value);}while (0)
+
+
+#define EINT_NUM  EINT_TOTAL_CHANNEL
+#define EINT_OK    (0)
+#define EINT_FAIL  (-1)
+#define EINT_ENABLE  1
+#define EINT_DISABLE 0
+#define EINT_NEGATIVE_POLARITY			0
+#define EINT_POSITIVE_POLARITY			1
+#define EINT_EDGE_SENSITIVITY		0
+#define EINT_LEVEL_SENSITIVITY		1
+#define EINT_DB_DUR_DEFAULT 0x400
+#define EINT_DB_DUR_MAX	0xFFFF
+#define EINT_HW_DB_TIME_MAX 2000 //ms
+#define GPIO_DEINT_SENS_EDGE			1
+#define GPIO_DEINT_SENS_LEVEL			0
+
+/**
+ * @brief	GPIO EINT Configuration Enumeration
+ */
+typedef enum{  
+	GPIO_EINT0=0,
+	GPIO_EINT1,
+	GPIO_EINT2,
+	GPIO_EINT3,
+	GPIO_EINT4,
+	GPIO_EINT5,
+	GPIO_EINT6,
+	GPIO_EINT7,
+	GPIO_EINT8,
+	GPIO_EINT9,
+	GPIO_EINT10,
+	GPIO_EINT11,
+	GPIO_EINT12,
+	GPIO_EINT13,
+	GPIO_EINT14,
+	GPIO_EINT15,
+}eint_e;
+
+typedef enum{  
+	DEDICATED_EINT0=0,
+	DEDICATED_EINT1,
+	DEDICATED_EINT2,
+	DEDICATED_EINT3,
+}dedicated_eint_e;
+
+/**
+*  @brief  set the polarity parameter of the eint
+*  @param  eint        :  the eint index to be set
+*  @param  pol :	the polarity value to set, it should be 0~1
+*				  0: set pol to negative polarity
+*				  1: set pol to positive polarity
+*  @return EINT_OK :   set successful,  EINT_FAIL : set failed
+*/
+extern kal_int32 eint_set_pol(eint_e eint, kal_uint32 pol);
+
+/**
+*  @brief  set the debounce enable parameter of the eint
+*  @param  eint        :  the eint index to be set
+*  @param  debounce_en :	the debounce enable value to set, it should be 0~1
+*				  		0: enable debounce function
+*				  		1: disable debounce function
+*  @return EINT_OK :   set successful,  EINT_FAIL : set failed
+*/
+extern kal_int32 eint_set_debounce_enable(eint_e eint, kal_uint32 debounce_en);
+
+
+/**
+*  @brief  set the debounce duration parameter of the eint
+*  @param  eint        :  the eint index to be set
+*  @param  duration :	the debounce duration value to set, it should be 0~0x3fff
+*  @return EINT_OK :   set successful,  EINT_FAIL : set failed
+*/
+extern kal_int32 eint_set_debounce_duration(eint_e eint, kal_uint32 duration);
+
+
+/**
+*  @brief  set the irqen parameter of the eint
+*  @param  eint        :  the eint index to be set
+*  @param  enable :	the irq enable register value to set, it should be 0~1
+*				  		0: disable eint irq send to cirq/gic module
+*				  		1: enable eint irq send to cirq/gic module
+*  @return EINT_OK :   set successful,  EINT_FAIL : set failed
+*/
+extern kal_int32 eint_set_irqen(eint_e eint,kal_uint32 enable);
+
+extern void eint_set_mask_all(kal_uint32 mask_bits);
+
+extern void eint_set_unmask_all(kal_uint32 unmask_bits);
+
+
+/**
+ *  @brief     get  eint debounce enable value of eint
+ *  @param  eint :  The eint to be read.
+ *  @return   return the eint debounce parameter's value of eint
+ *                 0:  current debounce is disable
+ *                 1:  current debounce is enable
+ *                 EINT_FAIL: eint is out of range
+ */
+extern kal_int32 eint_get_debounce_enable(eint_e eint);
+
+/**
+ *  @brief     get  eint IRQEN value of eint
+ *  @return   return the eint debounce parameter's value of eint
+ *                 0:  current eint is unmask
+ *                 1:  current eint is mask
+ *                 EINT_FAIL: eint is out of range
+ */
+extern kal_int32 eint_get_irqen(void);
+
+
+/**
+*  @brief  set the sensitivity parameter of the eint
+*  @param  eint        :  the eint index to be set
+*  @param  type :	the sensitivity value to set, it should be 0~1
+*				  0: set sensitivity to edge(pulse)
+*				  1: set sensitivity to level
+*  @return EINT_OK :   set successful,  EINT_FAIL : set failed
+*/
+extern kal_int32 eint_set_type(eint_e eint, kal_uint32 type);
+
+/**
+*  @brief  set eint ownership register
+*  @param  eint  : the eint index to set ownerhsip
+*  @param  ownership : the ownership register bit value to set ,it should be 0~1
+*                                    0: set ownership to MD
+*                                    1: set ownership to AP
+*  @return GPIO_OK :	set successful,  GPIO_FAIL : set failed
+*/
+extern kal_int32 eint_set_ownership(kal_uint32 eint,kal_uint32 ownership);
+
+/**
+*  @brief  set the source gpio index parameter of the eint
+*  @param  eint        :  the eint index to be set
+*  @param  gpio_pin :	The pin which is to set as source gpio of eint. it should be 0~63
+*  @return GPIO_OK :   set successful,  GPIO_FAIL : set failed
+*/
+extern kal_int32 gpio_set_eint_src(eint_e eint, kal_uint8 gpio_pin);
+
+/**
+ *  @brief     set dedicated eint enable value of deint
+ *  @param  deint :  The dedicated eint to be set.
+ *  @param  eint: the l2 eint index to set as source eint of deint,it should be 0~15
+ *  @param  enable: the enable register value to set,it should be 0~1
+ *				   0: enable dedicated eint 
+ *				   1: disable dedicated eint 
+ *  @return GPIO_OK :	set successful,  GPIO_FAIL : set failed
+ */
+extern kal_int32 gpio_set_l1_eint(dedicated_eint_e deint,eint_e eint,kal_uint32 enable);
+
+extern kal_int32 eint_get_l1_irqen(dedicated_eint_e deint);
+extern kal_int32 eint_set_l1_eint_enable(dedicated_eint_e deint , kal_uint32 enable);
+/**
+ *  @brief     get  dedicated eint source l2 eint index value of l1_deint
+ *  @param  l1_deint :  The dedicated eint to be read.
+ *  @return   return the dedicated eint  source l2 eint index value of l1_deint
+ *                 src_eint:  0~0xf , l2 eint index
+ *                 GPIO_FAIL: l1_deint is out of range
+ */
+extern kal_int32 gpio_get_l1_eint_src(kal_uint32 l1_deint);
+
+
+/**
+ *  @brief     get  eint type parameter's value of eint
+ *  @param  eint :  The eint to be read.
+ *  @return   return the eint type parameter's value of eint
+ *                 0: current is edge(pulse) sensitivity
+ *                 1: current is level sensitivity
+ *                 GPIO_FAIL: eint is out of range
+ */
+extern kal_int32 gpio_get_eint_type(eint_e eint);
+
+/**
+ *  @brief     get  eint source gpio id of eint
+ *  @param  eint :  The eint to be read.
+ *  @return   return the eint source parameter's value of eint
+ *                 gpio_pin: 0~64 the gpio index of eint source
+ *                 GPIO_FAIL: eint is out of range
+ */
+extern kal_int32 gpio_get_eint_src(eint_e eint);
+
+
+/**
+ *  @brief     get  eint polarity value of eint
+ *  @param  eint :  The eint to be read.
+ *  @return   return the eint polarity parameter's value of eint
+ *                 0: current is negative polarity
+ *                 1: current is positive polarity
+ *                 GPIO_FAIL: eint is out of range
+ */
+extern kal_int32 gpio_get_eint_pol(eint_e eint);
+#endif
diff --git a/mcu/interface/driver/devdrv/emi/drv_emi.h b/mcu/interface/driver/devdrv/emi/drv_emi.h
new file mode 100644
index 0000000..10c0521
--- /dev/null
+++ b/mcu/interface/driver/devdrv/emi/drv_emi.h
@@ -0,0 +1,60 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   drv_emi.h
+ *
+ * Project:
+ * --------
+ *   MOLY
+ *
+ * Description:
+ * ------------
+ *   Header file for EMI driver
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DRV_EMI_H__
+#define __DRV_EMI_H__
+
+// UMOLY TRUNK don't support emi related source code since 6291
+#define emi_get_dram_temp()  0x7FFF
+
+#endif  /* __DRV_EMI_H__ */
diff --git a/mcu/interface/driver/devdrv/emi/emi_hw.h b/mcu/interface/driver/devdrv/emi/emi_hw.h
new file mode 100644
index 0000000..dc42837
--- /dev/null
+++ b/mcu/interface/driver/devdrv/emi/emi_hw.h
@@ -0,0 +1,231 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   emi_hw.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *   Definition for CONFIG hardware registers
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __EMI_HW_H__
+#define __EMI_HW_H__
+
+// UMOLY TRUNK don't support emi related source code since 6291
+
+#endif  /* __EMI_HW_H__ */
+
diff --git a/mcu/interface/driver/devdrv/emi/emi_sw.h b/mcu/interface/driver/devdrv/emi/emi_sw.h
new file mode 100644
index 0000000..7796e6c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/emi/emi_sw.h
@@ -0,0 +1,312 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2005
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   emi_hw.h
+ *
+ * Project:
+ * --------
+ *   Maui_Software
+ *
+ * Description:
+ * ------------
+ *   Definition for CONFIG hardware registers
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __EMI_SW_H__
+#define __EMI_SW_H__
+
+// UMOLY TRUNK don't support emi related source code since 6291
+
+#endif  /* __EMI_SW_H__ */
+
diff --git a/mcu/interface/driver/devdrv/gdma/md93/drv_gdma.h b/mcu/interface/driver/devdrv/gdma/md93/drv_gdma.h
new file mode 100644
index 0000000..838dcdd
--- /dev/null
+++ b/mcu/interface/driver/devdrv/gdma/md93/drv_gdma.h
@@ -0,0 +1,431 @@
+#ifndef __DRV_GDMA_H__
+#define __DRV_GDMA_H__
+
+/**
+ * GDMA channel definition
+ */
+typedef enum {
+    GDMA_CH_00,
+    GDMA_CH_01,
+    GDMA_CH_MAX,
+} gdma_channel_type_e;
+
+/**
+ * A structure to describe GPD source and destination address
+ */
+typedef struct gdma_gpd_addr_s {
+    kal_uint32 gdma_src_Gpd;
+    kal_uint32 gdma_dst_Gpd;
+} gdma_gpd_addr_t;
+
+/**
+ * Operation mode of GDMA
+ */
+typedef enum {
+    GDMA_MOD_LINKLIST,
+    GDMA_MOD_BASIC,
+    GDMA_MOD_DESCRIPTOR,
+    GDMA_MOD_MEMSET,
+} gdma_mod_e;
+
+/**
+ * Bus width definition
+ * For best memory bandwidth utilization, use GDMA_BUS_WIDTH_64BITS
+ */
+typedef enum {
+    GDMA_BUS_WIDTH_8BITS,   // reserved, DO NOT USE
+    GDMA_BUS_WIDTH_16BITS,  // reserved, DO NOT USE
+    GDMA_BUS_WIDTH_32BITS,  // reserved, DO NOT USE
+    GDMA_BUS_WIDTH_64BITS,
+    GDMA_BUS_WIDTH_MAX,
+} gdma_bus_width_e;
+
+/**
+ * Burst length definition
+ * For best memory bandwidth utilization, use GDMA_BST_SIZE_256B
+ */
+typedef enum {
+    GDMA_BST_SIZE_1B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_2B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_4B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_8B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_16B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_32B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_64B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_128B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_256B,
+} gdma_bst_size_e;
+
+/**
+ * A structure to describe bus width of source and destination
+ */
+typedef struct gdma_bus_width_s {
+    gdma_bus_width_e src_bus_width;
+    gdma_bus_width_e dst_bus_width;
+} gdma_bus_width_t;
+
+/**
+ * Channel priority definition
+ */
+typedef enum {
+    GDMA_PRI_HIGH,
+    GDMA_PRI_MEDIAN,
+    GDMA_PRI_LOW,
+} gdma_priority_e;
+
+/**
+ * A structure to describe configuration settings
+ */
+typedef struct gdma_cfg_s {
+    gdma_channel_type_e gdma_sel_channel;
+    gdma_mod_e          gdma_mod;
+    gdma_gpd_addr_t     gdma_gpd_addr;
+    kal_uint32          gdma_mod_basic_tx_size;
+    kal_uint16          gdma_other_para;
+    gdma_bus_width_t    gdma_bus_width;
+    gdma_priority_e     gdma_priority;
+    kal_bool            gdma_gpd_cs_en;
+    kal_bool            gdma_cs_en;
+    kal_bool            gdma_bd_dat_cs_en;
+    gdma_bst_size_e     gdma_bst_size;
+} gdma_cfg_t;
+
+/**
+ * Command type of GDMA
+ */
+typedef enum {
+    GDMA_START,
+    GDMA_RESUME,
+} gdma_start_cmd_type_e;
+
+/**
+ * Channel status
+ */
+typedef enum {
+    GDMA_STARTED,
+    GDMA_STOP,
+} gdma_status_type_e;
+
+/**
+ * Interrupt type for callback registration
+ */
+typedef enum {
+    GDMA_SRC_DONE           = 0,
+    GDMA_DST_DONE           = 4,
+    GDMA_SRC_QUE_EMPTY      = 8,
+    GDMA_DST_QUE_EMPTY      = 12,
+    GDMA_LEN_ERR            = 16,
+    GDMA_ALO_LEN_ERR        = 20,
+    GDMA_BD_CS_ERR          = 24,
+    GDMA_GPD_CS_ERR         = 28,
+    GDMA_REGION_ACCESS_ERR  = 32,
+    GDMA_INT_TYPE_MAX       = 36,
+} gdma_int_type_e;
+
+/**
+ * MDGDMA common queue
+ */
+#define MDGDMA_CQ_SIZE  50
+
+typedef struct gdma_cq_request_s {
+    kal_uint8  handle;    /*user request handle enum */
+    kal_uint16 dataSize;
+    kal_uint32 srcAddr;
+    kal_uint32 dstAddr;
+}gdma_cq_rqst_t;
+
+typedef struct gdma_cq_s {
+    gdma_cq_rqst_t      gdma_cq[MDGDMA_CQ_SIZE];
+    kal_uint8           gdma_cq_write;
+    kal_uint8           gdma_cq_read;
+    kal_bool            gdma_cq_active;
+} gdma_cq_t;
+
+/**
+ * MDGDMA common queue request return value
+ */
+typedef enum {
+    GDMA_CQ_SUCCESS = 0,
+    GDMA_CQ_FAIL_HANDLE_ERROR,
+    GDMA_CQ_FAIL_ADDR_ERROR,
+    GDMA_CQ_FAIL_SIZE_ERROR,
+    GDMA_CQ_FAIL_CQ_FULL,
+} gdma_cq_rqst_rtn_e;
+
+/**
+ * MDGDMA common queue APB access request handle
+ */
+typedef enum {
+    GDMA_CQ_HANDLE_START = 0,
+    GDMA_CQ_HANDLE_00 = GDMA_CQ_HANDLE_START,
+    GDMA_CQ_HANDLE_01,
+    GDMA_CQ_HANDLE_02,
+    GDMA_CQ_HANDLE_03,
+    GDMA_CQ_HANDLE_04,
+    GDMA_CQ_HANDLE_05,
+    GDMA_CQ_HANDLE_06,
+    GDMA_CQ_HANDLE_07,
+    GDMA_CQ_HANDLE_08,
+    GDMA_CQ_HANDLE_09,
+    GDMA_CQ_HANDLE_END,                                       //APB access request handle END
+    GDMA_CQ_MEMSET_HANDLE_START = GDMA_CQ_HANDLE_END,         //memset request handle ID START
+    GDMA_CQ_MEMSET_HANDLE_00 = GDMA_CQ_MEMSET_HANDLE_START,
+    GDMA_CQ_MEMSET_HANDLE_01,
+    GDMA_CQ_MEMSET_HANDLE_02,
+    GDMA_CQ_MEMSET_HANDLE_03,
+    GDMA_CQ_MEMSET_HANDLE_04,
+    GDMA_CQ_MEMSET_HANDLE_05,
+    GDMA_CQ_MEMSET_HANDLE_06,
+    GDMA_CQ_MEMSET_HANDLE_07,
+    GDMA_CQ_MEMSET_HANDLE_08,
+    GDMA_CQ_MEMSET_HANDLE_09,
+    GDMA_CQ_MEMSET_HANDLE_END,
+} gdma_cq_rqst_handle_e;
+
+/**
+ * MDGDMA common queue request status
+ */
+typedef enum {
+    GDMA_CQ_RQST_STS_UNHANDLE,
+    GDMA_CQ_RQST_STS_HANDLED,
+    GDMA_CQ_RQST_STS,
+} gdma_cq_rqst_sts_e;
+
+/**
+ * A structure to describe configuration settings for callback registration
+ */
+typedef struct gdma_cbType_s {
+    gdma_channel_type_e     gdma_channel;
+    gdma_int_type_e         gdma_int_type;
+} gdma_cbType_t;
+
+/**
+ * A structure to describe callback information
+ */
+typedef struct gdma_cbParameter_s {
+    gdma_channel_type_e gdma_channel;
+    gdma_int_type_e     gdma_int_type;
+    gdma_gpd_addr_t     gpd_info;
+} gdma_cbParameter_t;
+
+/**
+ * Prototype of callback function
+ */
+typedef void (*gdma_pcb_f)(gdma_cbParameter_t *gpd_info);
+
+/**
+ * System MCU type
+ */
+typedef enum {
+    GDMA_MCU_IA,
+    GDMA_MCU_USIP0,
+} gdma_irq2mcu_type_e;
+
+/**
+ * MDGDMA clock operation command
+ */
+typedef enum {
+    GDMA_CLK_ENABLE,
+    GDMA_CLK_DISABLE,
+} gdma_clk_type_e;
+
+/**
+ * Initial all GDMA driver
+ */
+kal_bool drv_gdma_init(void);
+
+#define DRV_GDMA_INITIALIZATION() \
+    drv_gdma_init();
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name MDGDMA
+///////////////////////////////////////////////////////////////////////////////
+ 
+///@{
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to configure the MDGDMA.
+/// \param [in] gdma_cfg    Configuration settings
+///
+/// \return                 KAL_TRUE if configuring is successful.
+/// \return                 KAL_FALSE if configuring is failed.
+///////////////////////////////////////////////////////////////////////////////
+kal_bool drv_gdma_set_config(gdma_cfg_t *gdma_cfg);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to start a channel of MDGDMA.
+/// \param [in] chId        Channel ID
+/// \param [in] cmd         Command type
+///
+/// \return                 KAL_TRUE if start command is issueed.
+/// \return                 KAL_FALSE if  failed to issue start command.
+///////////////////////////////////////////////////////////////////////////////
+kal_bool drv_gdma_start_cmd(gdma_channel_type_e chId, gdma_start_cmd_type_e cmd);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to stop a channel of MDGDMA.
+///
+/// \param [in] chId        Channel ID
+///////////////////////////////////////////////////////////////////////////////
+void drv_gdma_stop_cmd(gdma_channel_type_e chId);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                      This function is to get current GPD source and
+///                             destination address.
+/// \param [in] chId            Channel ID
+/// \param [in] cur_gpd_addr    Source and destination address of current GPD
+///////////////////////////////////////////////////////////////////////////////
+void drv_gdma_get_curGPD(gdma_channel_type_e chId, gdma_gpd_addr_t *cur_gpd_addr);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to get channel status of MDGDMA.
+///
+/// \param [in] chId        Channel ID
+///
+/// \return                 GDMA_STARTED if channel \p chId is started.
+/// \return                 GDMA_STOP if channel \p chId is started.
+///////////////////////////////////////////////////////////////////////////////
+gdma_status_type_e drv_gdma_get_status(gdma_channel_type_e chId);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to register callback function
+///                         of MDGDMA when specified interrupt is triggered.
+///
+/// \param [in] cbType      Callback type
+/// \param [in] callback    User defined callback function
+/// \return                 KAL_TRUE if registration is successful.
+/// \return                 KAL_FALSE if registration is failed.
+///////////////////////////////////////////////////////////////////////////////
+kal_bool drv_gdma_register_callback(gdma_cbType_t *cbType, gdma_pcb_f callback);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to set priority of a channel
+///
+/// \param [in] chId        Channel ID
+/// \param [in] priority    Channel priority
+///////////////////////////////////////////////////////////////////////////////
+void drv_gdma_set_priority(gdma_channel_type_e chId, gdma_priority_e priority);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used by user to notify GDMA
+///                         that channel operation is done.
+///
+/// \param [in] chId        Channel ID
+///////////////////////////////////////////////////////////////////////////////
+void drv_gdma_notify_done(gdma_channel_type_e chId);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used by user to request GDMA commnon queue
+///                          for APB access.
+///
+/// \Note                 param [in] dataSize   User data size (MAX data size is 0xFFFFFF) 
+///
+/// \param [in] handle     User request
+/// \param [in] srcAddr    User data source address
+/// \param [in] dstAddr    User data destination address
+/// \param [in] dataSize   User data size (MAX data size is 0xFFFFFF)
+/// \return                     GDMA_CQ_SUCCESS if request is successful.
+/// \return                     GDMA_CQ_FAIL_HANDLE_ERROR if request is failed.
+/// \return                     GDMA_CQ_FAIL_SIZE_ERROR if request is failed.
+/// \return                     GDMA_CQ_FAIL_CQ_FULL if request is failed.
+///////////////////////////////////////////////////////////////////////////////
+gdma_cq_rqst_rtn_e drv_gdma_cq_request(gdma_cq_rqst_handle_e handle, kal_uint32 srcAddr, kal_uint32 dstAddr, kal_uint32 dataSize);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used by user to polling request status
+///                          until the request is done.
+///
+/// \Note                  Blocking API
+///                          
+/// \param [in] handle  User request
+/// \return                 KAL_TRUE if request is done.
+///
+///////////////////////////////////////////////////////////////////////////////
+kal_bool drv_gdma_cq_rqst_polling(gdma_cq_rqst_handle_e handle);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used by user to polling request current status
+///                          
+/// \Note                  No-Blocking API
+///
+/// \param [in] handle  User request
+/// \return                 KAL_TRUE if request is done.
+/// \return                 KAL_FALSE if request is not done.
+///////////////////////////////////////////////////////////////////////////////
+kal_bool drv_gdma_cq_rqst_done(gdma_cq_rqst_handle_e handle);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  MDGDMA common queue callback function
+///////////////////////////////////////////////////////////////////////////////
+void drv_gdma_cq_cb(gdma_cbParameter_t *gpd_info);
+
+kal_bool drv_gdma_register_cq_cb(gdma_cbType_t *cbType, gdma_pcb_f callback);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used by user to request GDMA commnon queue
+///                          for memset().
+///
+/// \Note                 param [in] dataSize   User data size (MAX data size is 0xFFFFFF, 16MB) 
+///                          param [in] dstAddr    User data destination address (must be 4 Bytes align)
+///
+/// \param [in] handle      User request
+/// \param [in] value       Memset pattern (This value will be cast to [unsigned char].)
+/// \param [in] dstAddr    User data destination address (must be 4 Bytes align)
+/// \param [in] dataSize   User data size (MAX data size is 0xFFFFFF, 16MB)
+/// \return                     GDMA_CQ_SUCCESS if request is successful.
+/// \return                     GDMA_CQ_FAIL_HANDLE_ERROR if request is failed.
+/// \return                     GDMA_CQ_FAIL_SIZE_ERROR if request is failed.
+/// \return                     GDMA_CQ_FAIL_CQ_FULL if request is failed.
+///////////////////////////////////////////////////////////////////////////////
+gdma_cq_rqst_rtn_e drv_gdma_cq_memset_request(gdma_cq_rqst_handle_e handle, kal_uint32 value, kal_uint32 dstAddr, kal_uint32 dataSize);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used by user to polling request status
+///                          until the request is done.
+///
+/// \Note                  Blocking API
+///                          
+/// \param [in] handle  User request
+/// \return                 KAL_TRUE if request is done.
+///
+///////////////////////////////////////////////////////////////////////////////
+kal_bool drv_gdma_cq_memset_rqst_polling(gdma_cq_rqst_handle_e handle);
+
+kal_bool drv_gdma_cq_is_full(void);
+
+kal_bool drv_gdma_cq_is_empty(void);
+
+void drv_gdma_encq(gdma_cq_rqst_handle_e handle, kal_uint32 srcAddr, kal_uint32 dstAddr, kal_uint32 dataSize);
+
+gdma_cq_rqst_t * drv_gdma_decq(void);
+
+
+void drv_gdma_lock_sleep();
+
+void drv_gdma_unlock_sleep();
+
+void HDMA_PDN_SET(kal_uint32 channel);
+void HDMA_PDN_CLR(kal_uint32 channel);
+kal_bool HDMA_PDN_STS(kal_uint32 channel);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used by user to set GDMA 
+///                         FDMA channel 1 irq to IA or uSIP0.
+///
+/// \param [in] mcuType        mcu type
+///////////////////////////////////////////////////////////////////////////////
+void drv_gdma_irq2mcu_config(gdma_irq2mcu_type_e mcuType);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used by user to enable or disable
+///                          GDMA clock by channel.
+///
+/// \param [in] chId    GDMA channel ID
+/// \param [in] cmd    Enable/Disable clock command
+///////////////////////////////////////////////////////////////////////////////
+void drv_gdma_clk_config(gdma_channel_type_e chId, gdma_clk_type_e cmd);
+
+
+///@}
+
+#endif /* end of __DRV_GDMA_H__ */
diff --git a/mcu/interface/driver/devdrv/gdma/md95/drv_gdma.h b/mcu/interface/driver/devdrv/gdma/md95/drv_gdma.h
new file mode 100644
index 0000000..8a3466a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/gdma/md95/drv_gdma.h
@@ -0,0 +1,338 @@
+#ifndef __DRV_GDMA_H__
+#define __DRV_GDMA_H__
+
+/*****************************************************************************
+ * GDMA Common Queue Option Implementation
+ *****************************************************************************/
+#define OPT_SA_FIXED				(1 << 8)
+#define OPT_DA_FIXED				(1 << 9)
+#define OPT_DEST_SINGLE 			(1 << 10)
+
+#define OPT_GDMA_TPUT_EN			(0x1 << 31)
+#define OPT_GDMA_TPUT_OFFSET	    (16)
+#define OPT_GDMA_TPUT_MASK			(0xFFF << 16)
+
+#define GDMA_USR_INVALID_OPTION 	(~(OPT_SA_FIXED | OPT_DA_FIXED | OPT_DEST_SINGLE | OPT_GDMA_TPUT_EN | OPT_GDMA_TPUT_MASK))
+
+#define GDMA_INVALID_OPTION 	    (0x7 << 28) //option bit28/29/30 are reserved now;
+
+/*****************************************************************************
+ * GDMA Universal Implementation
+ *****************************************************************************/
+#define DRV_GDMA_INITIALIZATION()               drv_gdma_init()
+
+/***GDMA Channel Definition***/
+typedef enum {
+    GDMA_CH_00,
+    GDMA_CH_01,
+    GDMA_CH_02,
+    GDMA_CH_MAX,
+} gdma_channel_type_e;
+
+/***GDMA Channel Status Definition***/
+typedef enum {
+    GDMA_CH_INACTIVE,
+    GDMA_CH_ACTIVE
+} gdma_channel_status_type_e;
+
+/*** GDMA CQ Channel Status Definition ***/
+typedef enum {
+    CQ_CH_IDLE,
+    CQ_CH_BUSY
+} gdma_cq_channel_status_type_e;
+
+/*** Bus width definition For best memory bandwidth utilization, use GDMA_BUS_WIDTH_64BITS ***/
+typedef enum {
+    GDMA_BUS_WIDTH_8BITS,   // reserved, DO NOT USE
+    GDMA_BUS_WIDTH_16BITS,  // reserved, DO NOT USE
+    GDMA_BUS_WIDTH_32BITS,  // reserved, DO NOT USE
+    GDMA_BUS_WIDTH_64BITS,
+    GDMA_BUS_WIDTH_MAX
+} gdma_bus_width_e;
+
+/*** Burst length definition For best memory bandwidth utilization, use GDMA_BST_SIZE_256B ***/
+typedef enum {
+    GDMA_BST_SIZE_1B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_2B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_4B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_8B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_16B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_32B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_64B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_128B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_256B
+} gdma_bst_size_e;
+
+/*** Command type of GDMA ***/
+typedef enum {
+    GDMA_START,
+    GDMA_RESUME,
+    GDMA_STOP
+} gdma_start_cmd_type_e;
+
+/*** Operation mode of GDMA ***/
+typedef enum {
+    GDMA_MOD_LINKLIST,
+    GDMA_MOD_BASIC,
+    GDMA_MOD_DESCRIPTOR
+} gdma_mod_e;
+
+/*** A structure to describe GPD source and destination address ***/
+typedef struct gdma_gpd_addr_s {
+    kal_uint32 gdma_src_Gpd;
+    kal_uint32 gdma_dst_Gpd;
+} gdma_gpd_addr_t;
+
+/*** A structure to describe bus width of source and destination ***/
+typedef struct gdma_bus_width_s {
+    gdma_bus_width_e src_bus_width;
+    gdma_bus_width_e dst_bus_width;
+} gdma_bus_width_t;
+
+/*** Interrupt type for callback registration ***/
+typedef enum {
+    GDMA_SRC_DONE           = 0,
+    GDMA_DST_DONE           = 4,
+    GDMA_SRC_QUE_EMPTY      = 8,
+    GDMA_DST_QUE_EMPTY      = 12,
+    GDMA_LEN_ERR            = 16,
+    GDMA_ALO_LEN_ERR        = 20,
+    GDMA_BD_CS_ERR          = 24,
+    GDMA_GPD_CS_ERR         = 28,
+    GDMA_REGION_ACCESS_ERR  = 32,
+    GDMA_INT_TYPE_MAX       = 36
+} gdma_int_type_e;
+
+/*** A structure to describe configuration settings for callback registration ***/
+typedef struct gdma_cbType_s {
+    gdma_channel_type_e     gdma_channel;
+    gdma_int_type_e         gdma_int_type;
+} gdma_cbType_t;
+
+/*** A structure to describe callback information ***/
+typedef struct gdma_cbParameter_s {
+    gdma_channel_type_e     gdma_channel;
+    gdma_int_type_e         gdma_int_type;
+    gdma_gpd_addr_t         gpd_info;
+} gdma_cbParameter_t;
+
+/*** A structure to describe CQ APB mode regster/value pair ***/
+typedef struct cq_apb_reg_value_s {
+    kal_uint32 value;
+	kal_uint32 reg_addr;
+} cq_apb_reg_value_t;
+
+/***uSIP Prototype of callback function ***/
+typedef void (*gdma_pcb_f)(gdma_cbParameter_t *gpd_info);
+
+/***Common Queue Prototype of callback function ***/
+typedef void (*gdma_cq_callback)(void *param_ptr);
+
+/*****************************************************************************
+ * GDMA Common Queue Implementation
+ *****************************************************************************/
+
+/***GDMA common queue request return value***/
+typedef enum {
+    GDMA_CQ_SUCCESS = 0,
+    GDMA_CQ_FAIL_HANDLE_ERROR,
+    GDMA_CQ_INPUT_NULL_POINTER_ERROR,
+    GDMA_CQ_FAIL_ADDR_ERROR,
+    GDMA_CQ_FAIL_SIZE_ERROR,
+    GDMA_CQ_INVALID_MODE,
+    GDMA_CQ_FAIL_CQ_FULL,
+    GDMA_CQ_INVALID_OPTION,
+    GDMA_CQ_INVALID_PRIO,
+    GDMA_CQ_CONCURRENT_OPERATION
+} gdma_cq_rqst_rtn_e;
+
+/***GDMA CQ user handle definition ***/
+typedef enum {
+    #include "drv_gdma_handle_id.h"
+    GDMA_CQ_RESERVED_HANDLE_ID, // this reserved handle id is used to debug in future;
+    GDMA_CQ_HANDLE_TOTAL
+} gdma_cq_rqst_handle_e;
+
+/*** Channel priority definition ***/
+typedef enum {
+    GDMA_PRI_LOW,
+    GDMA_PRI_MEDIAN,
+    GDMA_PRI_HIGH,
+    GDMA_CQ_PRIO_TOTAL
+} gdma_priority_e;
+
+/*** MDGDMA clock operation command***/
+typedef enum {
+    GDMA_CLK_ENABLE,
+    GDMA_CLK_DISABLE,
+} gdma_clk_type_e;
+
+/***GDMA CQ support mode ***/
+typedef enum {
+    GDMA_CQ_BASIC_MODE,
+    GDMA_CQ_APB_MODE,
+    GDMA_CQ_MEMSET_MODE,
+    GDMA_CQ_MODE_TOTAL
+} gdma_cq_mode_type_e;
+
+/***CQ Request Input Parameter Structure***/
+typedef struct gdma_cq_req_input_s {
+    kal_uint32            src_addr; //Basic mode --> source address, APB mode --> this is the data/addr pair address, MEMSET mode --> this is the pattern id;
+    kal_uint32            dest_addr; //destination address;
+	kal_uint32            data_length; //APB mode --> this is the size of data/addr pair region, BASIC/MEMSET mode --> the length of transfer size;
+    kal_uint32            option; // for user to extend the feature of GDMA CQ;
+	gdma_cq_mode_type_e   mode; //CQ mode: BASIC/APB/MEMSET is available;
+	gdma_cq_rqst_handle_e handle_id;
+	gdma_priority_e       priority; //user request priority, default as low priority;
+	gdma_cq_callback      cq_callback; //user callback function;
+	void *                param_ptr; //the para that user callback function will use;
+    struct gdma_cq_req_input_s *next_node; //used to link available list / priority list
+} gdma_cq_req_input_t;
+
+/*****************************************************************************
+ * GDMA uSIP Implementation
+ *****************************************************************************/
+
+/*** System MCU type***/
+typedef enum {
+    GDMA_IRQ_TO_IA,
+    GDMA_IRQ_TO_USIP0
+} gdma_irq2mcu_type_e;
+
+typedef struct gdma_cfg_s {
+    gdma_channel_type_e gdma_sel_channel;
+    gdma_mod_e          gdma_mod;
+    gdma_gpd_addr_t     gdma_gpd_addr;
+    kal_uint32          gdma_mod_basic_tx_size;
+    kal_uint16          gdma_other_para;
+    gdma_bus_width_t    gdma_bus_width;
+    gdma_priority_e     gdma_priority;
+    kal_bool            gdma_gpd_cs_en;
+    kal_bool            gdma_cs_en;
+    kal_bool            gdma_bd_dat_cs_en;
+    gdma_bst_size_e     gdma_bst_size;
+} gdma_cfg_t;
+
+/***********************************************************************
+*
+*   DESCRIPTION
+*
+*      Attention: please user only use drv_gdma_cq_rqst, not call __drv_gdma_cq_rqst
+*
+*
+***********************************************************************/
+#define drv_gdma_cq_rqst(cq_req_input_ptr) __drv_gdma_cq_rqst(cq_req_input_ptr, __FILE__, __LINE__)
+
+gdma_cq_rqst_rtn_e __drv_gdma_cq_rqst(gdma_cq_req_input_t *cq_req_input_ptr, char *filename, kal_uint32 line);
+
+
+/***********************************************************************
+*
+*   DESCRIPTION
+*
+*      reserve for possible future use for lock sleep
+*
+*
+***********************************************************************/
+void drv_gdma_lock_sleep(void);
+void drv_gdma_unlock_sleep(void);
+
+kal_bool HDMA_PDN_STS(kal_uint32 channel);
+void HDMA_PDN_CLR(kal_uint32 channel);
+void HDMA_PDN_SET(kal_uint32 channel);
+
+/***********************************************************************
+*
+*   FUNCTION
+*
+*      drv_gdma_set_config
+*
+*   DESCRIPTION
+*
+*      This function is specificly used to configure CH1 for uSIP usage
+*
+*   INPUTS
+*
+*       gdma_cfg_t *gdma_cfg
+*
+***********************************************************************/
+kal_bool drv_gdma_set_config(gdma_cfg_t *gdma_cfg);
+
+/***********************************************************************
+*
+*   FUNCTION
+*
+*      drv_gdma_start_cmd
+*
+*   DESCRIPTION
+*
+*      This function is used to start CH1
+*
+*   INPUTS
+*
+*       gdma_channel_type_e chId, gdma_start_cmd_type_e cmd
+*
+***********************************************************************/
+kal_bool drv_gdma_start_cmd(gdma_channel_type_e chId, gdma_start_cmd_type_e cmd);
+
+/***********************************************************************
+*
+*   FUNCTION
+*
+*      drv_gdma_stop_cmd
+*
+*   DESCRIPTION
+*
+*      This function is used to stop CH0/1/2, CH1 no such request, while CH0/2 may need
+*      in future because common queue preempt may be allowed in order to support priority
+*      common queue
+*
+*   INPUTS
+*
+*       gdma_channel_type_e chId
+*
+***********************************************************************/
+void drv_gdma_stop_cmd(gdma_channel_type_e chId);
+
+/***********************************************************************
+*
+*   FUNCTION
+*
+*      drv_gdma_register_callback  drv_gdma_irq2mcu_config  drv_gdma_clk_config
+*
+*   DESCRIPTION
+*
+*      This function is specific to CH1
+*
+*   INPUTS
+*
+*       gdma_cbType_t *cbType, gdma_pcb_f callback
+*
+***********************************************************************/
+kal_bool drv_gdma_register_callback(gdma_cbType_t *cbType, gdma_pcb_f callback);
+
+void drv_gdma_irq2mcu_config(gdma_irq2mcu_type_e mcuType);
+void drv_gdma_clk_config(gdma_channel_type_e chId, gdma_clk_type_e cmd);
+
+/***********************************************************************
+*
+*   FUNCTION
+*
+*      drv_gdma_cq_rqst_polling / drv_gdma_cq_rqst_done
+*
+*   DESCRIPTION
+*
+*      support busy polling / try mechanism to check the CQ current status
+*      note: cur_status = COMPLETED means that the whole flow (HW Action + callback run)
+*      is over, cur_status = REQUEST just means that the user requests have not completed.
+*      in current mechanism, only the pre whole flow is over, the next CQ will continue;
+*
+*   INPUTS
+*      
+***********************************************************************/
+//kal_bool drv_gdma_cq_rqst_polling(gdma_cq_rqst_handle_e handle_id);
+//kal_bool drv_gdma_cq_rqst_done(gdma_cq_rqst_handle_e handle_id);
+
+void drv_gdma_notify_done(gdma_channel_type_e chId);
+kal_bool drv_gdma_init(void);
+#endif /* end of __DRV_GDMA_H__ */
diff --git a/mcu/interface/driver/devdrv/gdma/md95/drv_gdma_handle_id.h b/mcu/interface/driver/devdrv/gdma/md95/drv_gdma_handle_id.h
new file mode 100644
index 0000000..d669376
--- /dev/null
+++ b/mcu/interface/driver/devdrv/gdma/md95/drv_gdma_handle_id.h
@@ -0,0 +1,46 @@
+#ifndef __DRV_GDMA_HANDLE_ID_H__
+#define __DRV_GDMA_HANDLE_ID_H__
+
+/*****************************************************************************
+ * BASIC Mode Handle ID List
+ *****************************************************************************/
+GDMA_CQ_HANDLE_START = 0,
+GDMA_CQ_BASIC_HANDLE_ID_SWLA0 = GDMA_CQ_HANDLE_START,
+GDMA_CQ_BASIC_HANDLE_ID_SWLA1,
+GDMA_CQ_BASIC_HANDLE_ID_SWLA2,
+GDMA_CQ_BASIC_HANDLE_ID_SWLA3,
+GDMA_CQ_BASIC_HANDLE_ID_SWLA4,
+GDMA_CQ_BASIC_HANDLE_ID_SWLA5,
+///TODO: please list your BASIC mode handle ID here
+
+
+/*****************************************************************************
+ * APB Mode Handle ID List
+ *****************************************************************************/
+GDMA_CQ_APB_HANDLE_START,		  //apb request handle ID START
+GDMA_CQ_APB_HANDLE_00 = GDMA_CQ_APB_HANDLE_START,
+GDMA_CQ_APB_HANDLE_01,
+GDMA_CQ_APB_HANDLE_02,
+GDMA_CQ_APB_HANDLE_03,
+//GDMA_CQ_APB_HANDLE_04,
+//GDMA_CQ_APB_HANDLE_05,
+//GDMA_CQ_APB_HANDLE_06,
+//GDMA_CQ_APB_HANDLE_07,
+///TODO: please list your APB mode handle ID here
+
+
+/*****************************************************************************
+ * MEMSET Mode Handle ID List
+ *****************************************************************************/
+GDMA_CQ_MEMSET_HANDLE_START,	  //memset request handle ID START
+GDMA_CQ_MEMSET_HANDLE_00 = GDMA_CQ_MEMSET_HANDLE_START,
+GDMA_CQ_MEMSET_HANDLE_01,
+GDMA_CQ_MEMSET_HANDLE_02,
+GDMA_CQ_MEMSET_HANDLE_03,
+//GDMA_CQ_MEMSET_HANDLE_04,
+//GDMA_CQ_MEMSET_HANDLE_05,
+//GDMA_CQ_MEMSET_HANDLE_06,
+//GDMA_CQ_MEMSET_HANDLE_07,
+///TODO: please list your MEMSET mode handle ID here
+
+#endif /* end of __DRV_GDMA_H__ */
diff --git a/mcu/interface/driver/devdrv/gdma/md97/drv_gdma.h b/mcu/interface/driver/devdrv/gdma/md97/drv_gdma.h
new file mode 100644
index 0000000..b27c9f2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/gdma/md97/drv_gdma.h
@@ -0,0 +1,340 @@
+#ifndef __DRV_GDMA_H__
+#define __DRV_GDMA_H__
+
+/*****************************************************************************
+ * GDMA Common Queue Option Implementation
+ *****************************************************************************/
+#define OPT_SA_FIXED				(1 << 8)
+#define OPT_DA_FIXED				(1 << 9)
+#define OPT_DEST_SINGLE 			(1 << 10)
+
+#define OPT_GDMA_TPUT_EN			(0x1 << 31)
+#define OPT_GDMA_TPUT_OFFSET	    (16)
+#define OPT_GDMA_TPUT_MASK			(0xFFF << 16)
+
+#define GDMA_USR_INVALID_OPTION 	(~(OPT_SA_FIXED | OPT_DA_FIXED | OPT_DEST_SINGLE | OPT_GDMA_TPUT_EN | OPT_GDMA_TPUT_MASK))
+#define GDMA_USR_VALID_OPTION 	    (OPT_SA_FIXED | OPT_DA_FIXED | OPT_DEST_SINGLE | OPT_GDMA_TPUT_EN | OPT_GDMA_TPUT_MASK)
+
+#define GDMA_INVALID_OPTION 	    (0x7 << 28) //option bit28/29/30 are reserved now;
+
+/*****************************************************************************
+ * GDMA Universal Implementation
+ *****************************************************************************/
+#define DRV_GDMA_INITIALIZATION()               drv_gdma_init()
+
+/***GDMA Channel Definition***/
+typedef enum {
+    GDMA_CH_00,
+    GDMA_CH_01,
+    GDMA_CH_02,
+    GDMA_CH_03,
+    GDMA_CH_04,
+    GDMA_CH_MAX,
+} gdma_channel_type_e;
+
+/***GDMA Channel Status Definition***/
+typedef enum {
+    GDMA_CH_INACTIVE,
+    GDMA_CH_ACTIVE
+} gdma_channel_status_type_e;
+
+/*** GDMA CQ Channel Status Definition ***/
+typedef enum {
+    CQ_CH_IDLE,
+    CQ_CH_BUSY
+} gdma_cq_channel_status_type_e;
+
+/*** Bus width definition For best memory bandwidth utilization, use GDMA_BUS_WIDTH_64BITS ***/
+typedef enum {
+    GDMA_BUS_WIDTH_8BITS,   // reserved, DO NOT USE
+    GDMA_BUS_WIDTH_16BITS,  // reserved, DO NOT USE
+    GDMA_BUS_WIDTH_32BITS,  // reserved, DO NOT USE
+    GDMA_BUS_WIDTH_64BITS,
+    GDMA_BUS_WIDTH_MAX
+} gdma_bus_width_e;
+
+/*** Burst length definition For best memory bandwidth utilization, use GDMA_BST_SIZE_256B ***/
+typedef enum {
+    GDMA_BST_SIZE_1B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_2B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_4B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_8B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_16B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_32B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_64B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_128B, // reserved, DO NOT USE
+    GDMA_BST_SIZE_256B
+} gdma_bst_size_e;
+
+/*** Command type of GDMA ***/
+typedef enum {
+    GDMA_START,
+    GDMA_RESUME,
+    GDMA_STOP
+} gdma_start_cmd_type_e;
+
+/*** Operation mode of GDMA ***/
+typedef enum {
+    GDMA_MOD_LINKLIST,
+    GDMA_MOD_BASIC,
+    GDMA_MOD_DESCRIPTOR
+} gdma_mod_e;
+
+/*** A structure to describe GPD source and destination address ***/
+typedef struct gdma_gpd_addr_s {
+    kal_uint32 gdma_src_Gpd;
+    kal_uint32 gdma_dst_Gpd;
+} gdma_gpd_addr_t;
+
+/*** A structure to describe bus width of source and destination ***/
+typedef struct gdma_bus_width_s {
+    gdma_bus_width_e src_bus_width;
+    gdma_bus_width_e dst_bus_width;
+} gdma_bus_width_t;
+
+/*** Interrupt type for callback registration ***/
+typedef enum {
+    GDMA_SRC_DONE           = 0,
+    GDMA_DST_DONE           = 4,
+    GDMA_SRC_QUE_EMPTY      = 8,
+    GDMA_DST_QUE_EMPTY      = 12,
+    GDMA_LEN_ERR            = 16,
+    GDMA_ALO_LEN_ERR        = 20,
+    GDMA_BD_CS_ERR          = 24,
+    GDMA_GPD_CS_ERR         = 28,
+    GDMA_REGION_ACCESS_ERR  = 32,
+    GDMA_INT_TYPE_MAX       = 36
+} gdma_int_type_e;
+
+/*** A structure to describe configuration settings for callback registration ***/
+typedef struct gdma_cbType_s {
+    gdma_channel_type_e     gdma_channel;
+    gdma_int_type_e         gdma_int_type;
+} gdma_cbType_t;
+
+/*** A structure to describe callback information ***/
+typedef struct gdma_cbParameter_s {
+    gdma_channel_type_e     gdma_channel;
+    gdma_int_type_e         gdma_int_type;
+    gdma_gpd_addr_t         gpd_info;
+} gdma_cbParameter_t;
+
+/*** A structure to describe CQ APB mode regster/value pair ***/
+typedef struct cq_apb_reg_value_s {
+    kal_uint32 value;
+	kal_uint32 reg_addr;
+} cq_apb_reg_value_t;
+
+/***uSIP Prototype of callback function ***/
+typedef void (*gdma_pcb_f)(gdma_cbParameter_t *gpd_info);
+
+/***Common Queue Prototype of callback function ***/
+typedef void (*gdma_cq_callback)(void *param_ptr);
+
+/*****************************************************************************
+ * GDMA Common Queue Implementation
+ *****************************************************************************/
+
+/***GDMA common queue request return value***/
+typedef enum {
+    GDMA_CQ_SUCCESS = 0,
+    GDMA_CQ_FAIL_HANDLE_ERROR,
+    GDMA_CQ_INPUT_NULL_POINTER_ERROR,
+    GDMA_CQ_FAIL_ADDR_ERROR,
+    GDMA_CQ_FAIL_SIZE_ERROR,
+    GDMA_CQ_INVALID_MODE,
+    GDMA_CQ_FAIL_CQ_FULL,
+    GDMA_CQ_INVALID_OPTION,
+    GDMA_CQ_INVALID_PRIO,
+    GDMA_CQ_CONCURRENT_OPERATION
+} gdma_cq_rqst_rtn_e;
+
+/***GDMA CQ user handle definition ***/
+typedef enum {
+    #include "drv_gdma_handle_id.h"
+    GDMA_CQ_RESERVED_HANDLE_ID, // this reserved handle id is used to debug in future;
+    GDMA_CQ_HANDLE_TOTAL
+} gdma_cq_rqst_handle_e;
+
+/*** Channel priority definition ***/
+typedef enum {
+    GDMA_PRI_LOW,
+    GDMA_PRI_MEDIAN,
+    GDMA_PRI_HIGH,
+    GDMA_CQ_PRIO_TOTAL
+} gdma_priority_e;
+
+/*** MDGDMA clock operation command***/
+typedef enum {
+    GDMA_CLK_ENABLE,
+    GDMA_CLK_DISABLE,
+} gdma_clk_type_e;
+
+/***GDMA CQ support mode ***/
+typedef enum {
+    GDMA_CQ_BASIC_MODE,
+    GDMA_CQ_APB_MODE,
+    GDMA_CQ_MEMSET_MODE,
+    GDMA_CQ_MODE_TOTAL
+} gdma_cq_mode_type_e;
+
+/***CQ Request Input Parameter Structure***/
+typedef struct gdma_cq_req_input_s {
+    kal_uint32            src_addr; //Basic mode --> source address, APB mode --> this is the data/addr pair address, MEMSET mode --> this is the pattern id;
+    kal_uint32            dest_addr; //destination address;
+	kal_uint32            data_length; //APB mode --> this is the size of data/addr pair region, BASIC/MEMSET mode --> the length of transfer size;
+    kal_uint32            option; // for user to extend the feature of GDMA CQ;
+	gdma_cq_mode_type_e   mode; //CQ mode: BASIC/APB/MEMSET is available;
+	gdma_cq_rqst_handle_e handle_id;
+	gdma_cq_callback      cq_callback; //user callback function;
+	void *                param_ptr; //the para that user callback function will use;
+} gdma_cq_req_input_t;
+
+/*****************************************************************************
+ * GDMA uSIP Implementation
+ *****************************************************************************/
+
+/*** System MCU type***/
+typedef enum {
+    GDMA_IRQ_TO_IA,
+    GDMA_IRQ_TO_USIP0
+} gdma_irq2mcu_type_e;
+
+typedef struct gdma_cfg_s {
+    gdma_channel_type_e gdma_sel_channel;
+    gdma_mod_e          gdma_mod;
+    gdma_gpd_addr_t     gdma_gpd_addr;
+    kal_uint32          gdma_mod_basic_tx_size;
+    kal_uint16          gdma_other_para;
+    gdma_bus_width_t    gdma_bus_width;
+    gdma_priority_e     gdma_priority;
+    kal_bool            gdma_gpd_cs_en;
+    kal_bool            gdma_cs_en;
+    kal_bool            gdma_bd_dat_cs_en;
+    gdma_bst_size_e     gdma_bst_size;
+} gdma_cfg_t;
+
+/***********************************************************************
+*
+*   DESCRIPTION
+*
+*      Attention: please user only use drv_gdma_cq_rqst, not call __drv_gdma_cq_rqst
+*
+*
+***********************************************************************/
+#define drv_gdma_cq_rqst(cq_req_input_ptr) __drv_gdma_cq_rqst(cq_req_input_ptr, __FILE__, __LINE__)
+
+gdma_cq_rqst_rtn_e __drv_gdma_cq_rqst(gdma_cq_req_input_t *cq_req_input_ptr, char *filename, kal_uint32 line);
+
+
+/***********************************************************************
+*
+*   DESCRIPTION
+*
+*      reserve for possible future use for lock sleep
+*
+*
+***********************************************************************/
+void drv_gdma_lock_sleep(void);
+void drv_gdma_unlock_sleep(void);
+
+kal_bool HDMA_PDN_STS(kal_uint32 channel);
+void HDMA_PDN_CLR(kal_uint32 channel);
+void HDMA_PDN_SET(kal_uint32 channel);
+
+/***********************************************************************
+*
+*   FUNCTION
+*
+*      drv_gdma_set_config
+*
+*   DESCRIPTION
+*
+*      This function is specificly used to configure CH1 for uSIP usage
+*
+*   INPUTS
+*
+*       gdma_cfg_t *gdma_cfg
+*
+***********************************************************************/
+kal_bool drv_gdma_set_config(gdma_cfg_t *gdma_cfg);
+
+/***********************************************************************
+*
+*   FUNCTION
+*
+*      drv_gdma_start_cmd
+*
+*   DESCRIPTION
+*
+*      This function is used to start CH1
+*
+*   INPUTS
+*
+*       gdma_channel_type_e chId, gdma_start_cmd_type_e cmd
+*
+***********************************************************************/
+kal_bool drv_gdma_start_cmd(gdma_channel_type_e chId, gdma_start_cmd_type_e cmd);
+
+/***********************************************************************
+*
+*   FUNCTION
+*
+*      drv_gdma_stop_cmd
+*
+*   DESCRIPTION
+*
+*      This function is used to stop CH0/1/2, CH1 no such request, while CH0/2 may need
+*      in future because common queue preempt may be allowed in order to support priority
+*      common queue
+*
+*   INPUTS
+*
+*       gdma_channel_type_e chId
+*
+***********************************************************************/
+void drv_gdma_stop_cmd(gdma_channel_type_e chId);
+
+/***********************************************************************
+*
+*   FUNCTION
+*
+*      drv_gdma_register_callback  drv_gdma_irq2mcu_config  drv_gdma_clk_config
+*
+*   DESCRIPTION
+*
+*      This function is specific to CH1
+*
+*   INPUTS
+*
+*       gdma_cbType_t *cbType, gdma_pcb_f callback
+*
+***********************************************************************/
+kal_bool drv_gdma_register_callback(gdma_cbType_t *cbType, gdma_pcb_f callback);
+
+void drv_gdma_irq2mcu_config(gdma_channel_type_e chId,gdma_irq2mcu_type_e mcuType);
+void drv_gdma_clk_config(gdma_channel_type_e chId, gdma_clk_type_e cmd);
+
+/***********************************************************************
+*
+*   FUNCTION
+*
+*      drv_gdma_cq_rqst_polling / drv_gdma_cq_rqst_done
+*
+*   DESCRIPTION
+*
+*      support busy polling / try mechanism to check the CQ current status
+*      note: cur_status = COMPLETED means that the whole flow (HW Action + callback run)
+*      is over, cur_status = REQUEST just means that the user requests have not completed.
+*      in current mechanism, only the pre whole flow is over, the next CQ will continue;
+*
+*   INPUTS
+*      
+***********************************************************************/
+//kal_bool drv_gdma_cq_rqst_polling(gdma_cq_rqst_handle_e handle_id);
+//kal_bool drv_gdma_cq_rqst_done(gdma_cq_rqst_handle_e handle_id);
+
+void drv_gdma_notify_done(gdma_channel_type_e chId);
+kal_bool drv_gdma_init(void);
+void drv_gdma_memset(void*, kal_uint8, kal_uint32, gdma_cq_rqst_handle_e, kal_bool);
+#endif /* end of __DRV_GDMA_H__ */
diff --git a/mcu/interface/driver/devdrv/gdma/md97/drv_gdma_handle_id.h b/mcu/interface/driver/devdrv/gdma/md97/drv_gdma_handle_id.h
new file mode 100644
index 0000000..bd1f887
--- /dev/null
+++ b/mcu/interface/driver/devdrv/gdma/md97/drv_gdma_handle_id.h
@@ -0,0 +1,113 @@
+#ifndef __DRV_GDMA_HANDLE_ID_H__
+#define __DRV_GDMA_HANDLE_ID_H__
+
+/*****************************************************************************
+ * CH0 Handle ID list, NOTE:in gen97, CH0 only be used by RF
+ *****************************************************************************/
+/*****************************************************************************
+ * CH0 BASIC Mode Handle ID List
+ *****************************************************************************/
+GDMA_CQ0_HANDLE_START = 0,
+GDMA_CQ0_BASIC_HANDLE_00 = GDMA_CQ0_HANDLE_START,
+#ifdef ATEST_DRV_GDMA
+GDMA_CQ0_BASIC_HANDLE_01,
+GDMA_CQ0_BASIC_HANDLE_02,
+GDMA_CQ0_BASIC_HANDLE_03,
+GDMA_CQ0_BASIC_HANDLE_04,
+#endif
+///TODO: please list your BASIC mode handle ID here
+GDMA_CQ0_BASIC_HANDLE_MMRFD_0,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_1,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_2,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_3,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_4,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_5,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_6,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_7,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_8,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_9,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_10,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_11,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_12,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_13,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_14,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_15,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_16,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_17,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_18,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_19,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_20,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_21,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_22,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_23,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_24,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_25,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_26,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_27,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_28,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_29,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_30,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_31,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_32,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_33,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_34,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_35,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_36,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_37,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_38,
+GDMA_CQ0_BASIC_HANDLE_MMRFD_39,
+
+
+/*****************************************************************************
+ * CH0 APB Mode Handle ID List
+ *****************************************************************************/
+GDMA_CQ0_APB_HANDLE_START,		  //apb request handle ID START
+GDMA_CQ0_APB_HANDLE_00 = GDMA_CQ0_APB_HANDLE_START,
+#ifdef ATEST_DRV_GDMA
+GDMA_CQ0_APB_HANDLE_01,
+GDMA_CQ0_APB_HANDLE_02,
+GDMA_CQ0_APB_HANDLE_03,
+GDMA_CQ0_APB_HANDLE_04,
+#endif
+///TODO: please list your APB mode handle ID here
+GDMA_CQ0_HANDLE_END,
+
+
+/*****************************************************************************
+ * CH2 Handle ID list
+ *****************************************************************************/
+ /*****************************************************************************
+ * CH2 BASIC Mode Handle ID List
+ *****************************************************************************/
+GDMA_CQ2_HANDLE_START = GDMA_CQ0_HANDLE_END,
+GDMA_CQ2_BASIC_HANDLE_00 = GDMA_CQ2_HANDLE_START,
+#ifdef ATEST_DRV_GDMA
+GDMA_CQ2_BASIC_HANDLE_01,
+GDMA_CQ2_BASIC_HANDLE_02,
+GDMA_CQ2_BASIC_HANDLE_03,
+GDMA_CQ2_BASIC_HANDLE_04,
+#endif
+///TODO: please list your BASIC mode handle ID here
+/*****************************************************************************
+ * CH2 MEMSET Mode Handle ID List
+ *****************************************************************************/
+GDMA_CQ2_MEMSET_HANDLE_START,	  //memset request handle ID START
+GDMA_CQ2_MEMSET_HANDLE_00 = GDMA_CQ2_MEMSET_HANDLE_START,
+GDMA_CQ2_MEMSET_HANDLE_01_ERRC_MEMSET,
+GDMA_CQ2_MEMSET_HANDLE_02_IDC_MEMSET,
+GDMA_CQ2_MEMSET_HANDLE_03_XCAP_MEMSET,
+GDMA_CQ2_MEMSET_HANDLE_04_EL1_MEMSET,
+GDMA_CQ2_MEMSET_HANDLE_05_EL1_MPC_MEMSET,
+GDMA_CQ2_MEMSET_HANDLE_06_NL1_MEMSET,
+GDMA_CQ2_MEMSET_HANDLE_07_NL1MOB_MEMSET,
+#ifdef ATEST_DRV_GDMA
+GDMA_CQ2_MEMSET_HANDLE_01,
+GDMA_CQ2_MEMSET_HANDLE_02,
+GDMA_CQ2_MEMSET_HANDLE_03,
+GDMA_CQ2_MEMSET_HANDLE_04,
+#endif
+///TODO: please list your MEMSET mode handle ID here
+GDMA_CQ2_HANDLE_END,
+
+
+#endif /* end of __DRV_GDMA_H__ */
diff --git a/mcu/interface/driver/devdrv/log_seq/logseq_drv.h b/mcu/interface/driver/devdrv/log_seq/logseq_drv.h
new file mode 100644
index 0000000..e83313b
--- /dev/null
+++ b/mcu/interface/driver/devdrv/log_seq/logseq_drv.h
@@ -0,0 +1,1032 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2010
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+ /*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *      logseq_drv.h
+ *
+ * Project:
+ * --------
+ *      UMOLYYA
+ *
+ * Description:
+ * ------------
+ *      This module defines the public APIs of log_seq driver
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
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+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ *****************************************************************************/
+
+#ifndef LOGSEQ_DRV_H_
+#define LOGSEQ_DRV_H_
+
+#include "kal_general_types.h"
+
+#if defined(__MD93__) || defined(__MD95__)
+/*!
+ *  @brief LS error code enumeration
+ *  @param LS_NO_ERROR                  LS no error
+ *  @param LS_FLUSH_TIMEOUT             LS do flush timeout
+ *  @param LS_ABORT_TIMEOUT             LS do abort timeout
+ *  @param LS_FLUSH_RESUME_TIMEOUT      LS do flush & resume_after_flush timeout
+ *  @param LS_ABORT_RESUME_TIMEOUT      LS do abort & resume_after_abort timeout
+ *  @param LS_WHOLE_SYS_FLUSH_TIMEOUT   LS do whole system flush timeout
+ *  @param LS_BACKUP_FAIL               LS do backup fail
+ *  @param LS_RESTORE_FAIL              LS do restore fail
+ */
+typedef enum {
+    LS_NO_ERROR = 0,
+    LS_FLUSH_TIMEOUT = 0x1,
+    LS_ABORT_TIMEOUT = 0x2,
+    LS_FLUSH_RESUME_TIMEOUT = 0x4,
+    LS_ABORT_RESUME_TIMEOUT = 0x8,
+    LS_WHOLE_SYS_FLUSH_TIMEOUT = 0x10,
+    LS_BACKUP_FAIL = 0x20,
+    LS_RESTORE_FAIL = 0x40,
+    LS_NO_DATA = 0x80,
+    LS_INSERT_FAIL = 0x100,
+    LS_EX_FAIL = 0x200,
+    LS_FORCE_RLS_FAIL = 0x400,
+    LS_FORCE_ABORT_FAIL = 0x800,
+    LS_PLS_FLUSH_FAILED_DSP = 0x1000,
+    LS_PLS_FLUSH_FAILED_MCU = 0x2000
+}LS_ERROR_CODE;
+
+/*!
+ *  @brief LS channel id enumeration
+ *  @param LS_DSP_CH             LS DSP channel
+ *  @param LS_MCU_CH             LS MCU channel
+ *  @param LS_CH_NUM             LS total channel number
+ */
+typedef enum {
+    LS_DSP_CH,
+    LS_MCU_CH,
+    LS_CH_NUM
+}LS_CH_ID;
+
+/*!
+ *  @brief LS EMI mode selection: user could configure LS_PLS for pls mode and LS_NORMAL_STREAM for streaming mode 
+ */
+typedef enum{
+    LS_STREAM_EMI = 0,
+    LS_PLS_EMI = 1,
+    LS_EMI_MODE_NUM
+}LS_EMI_MODE;
+
+#elif defined(__MD97__)||defined(__MD97P__)
+/*!
+ *  @brief LS error code enumeration
+ *  @param LS_NO_ERROR                  LS no error
+ *  @param LS_FLUSH_TIMEOUT             LS do flush timeout
+ *  @param LS_ABORT_TIMEOUT             LS do abort timeout
+ *  @param LS_FLUSH_RESUME_TIMEOUT      LS do flush & resume_after_flush timeout
+ *  @param LS_ABORT_RESUME_TIMEOUT      LS do abort & resume_after_abort timeout
+ *  @param LS_WHOLE_SYS_FLUSH_TIMEOUT   LS do whole system flush timeout
+ *  @param LS_BACKUP_FAIL               LS do backup fail
+ *  @param LS_RESTORE_FAIL              LS do restore fail
+ *  @param LS_NO_DATA					LS do not have any new data that do not query by the user
+ * 	@param LS_INSERT_FAIL               LS insert emi_address != prev_emi_addr + new read length
+ *  @param LS_EX_FAIL					LS is eigther not inital correctly or  in the wrong backup/restore state as entering EE flow
+ * 	@param LS_FORCE_RLS_FAIL		    LS do not initial as calling force release API
+ *	@param LS_FORCE_ABORT_FAIL			LS do force abort failed
+ *	@param LS_PLS_FLUSH_FAILED_4G_DSP	LS failed to do the LS_FLUSH/ABORT in PLS mode(4G DSP)
+ * 	@param LS_PLS_FLUSH_FAILED_5G_DSP	LS failed to do the LS_FLUSH/ABORT in PLS mode(5G DSP)
+ *	@param LS_PLS_FLUSH_FAILED_MCU		LS failed to do the LS_FLUSH/ABORT in PLS mode(Shaolin or iA)
+ * 	@param LS_INVALID_GROUP_POLICY      LS set group policy with the false configuration
+ */
+
+/*add abort operation record for debug*/
+typedef struct {
+			kal_uint32 FRC; // FRC
+			kal_uint32 linnum;	//line number
+			kal_uint32 status;//status 0:abort 1:check  
+} ABORT_CHID_INFO;
+
+typedef struct {
+			kal_uint32 record_count; // channel ID 
+			ABORT_CHID_INFO  abort_record_ch[10];
+} ABORT_DEBUG_INFO;
+
+typedef enum{
+	LS_NORMAL_ABORT = 0,
+	LS_NORMAL_CHECK ,
+	LS_DORMANT_ABORT,
+	LS_DORMANT_CHECK,
+	LS_RESUME_CHECK,
+	LS_EXCEPTION_ABORT,
+	LS_EXCEPTION_CHECK,
+}LS_ABORT_STATUS;
+
+
+typedef enum {
+    LS_NO_ERROR = 0,
+    LS_FLUSH_TIMEOUT = 0x1,
+    LS_ABORT_TIMEOUT = 0x2,
+    LS_FLUSH_RESUME_TIMEOUT = 0x4,
+    LS_ABORT_RESUME_TIMEOUT = 0x8,
+    LS_WHOLE_SYS_FLUSH_TIMEOUT = 0x10,
+    LS_BACKUP_FAIL = 0x20,
+    LS_RESTORE_FAIL = 0x40,
+    LS_NO_DATA = 0x80,
+    LS_INSERT_FAIL = 0x100,
+    LS_EX_FAIL = 0x200,
+    LS_FORCE_RLS_FAIL = 0x400,
+    LS_FORCE_ABORT_FAIL = 0x800,
+	LS_PLS_FLUSH_FAILED_4G_DSP = 0x1000,
+	LS_PLS_FLUSH_FAILED_5G_DSP = 0x2000,
+	LS_PLS_FLUSH_FAILED_MCU = 0x4000,
+	LS_INVALID_GROUP_POLICY = 0x8000,
+	LS_INVALID_STOP_ADDR = 0x10000
+}LS_ERROR_CODE;
+
+/*!
+ *  @brief LS error code enumeration specifiy for sleep it
+ *  @param LS_SLEEP_NO_ERROR            LS no error
+ *  @param LS_SLEEP_ABORT_TIMEOUT  		LS do abort timeout
+ *  @param LS_SLEEP_BACKUP_FAIL  		LS do backup timeout
+ */
+typedef enum{
+	LS_SLEEP_NO_ERROR = 0,
+	LS_SLEEP_ABORT_TIMEOUT = 0x1,
+	LS_SLEEP_BACKUP_FAIL = 0x2,
+	LS_SLEEP_RESTORE_FAIL = 0x4
+}LS_SLEEP_ERROR_CODE;
+
+/*!
+ *  @brief LS channel id enumeration
+ *  @param LS_4G_DSP_NORMAL_CH             LS 4G DSP normal channel
+ *  @param LS_4G_DSP_ONDEMAND_CH           LS 4G DSP ondemand channel
+ *  @param LS_5G_DSP_NORMAL_CH             LS 5G DSP normal channel
+ * 	@param LS_5G_DSP_ONDEMAND_CH           LS 5G DSP ondemand channel
+ * 	@param LS_MCU_NORMAL_CH				   LS MCU normal channel
+ * 	@param LS_MCU_ONDEMAND_CH			   LS MCU ondemand channel
+ *	@param LS_CH_NUM					   LS total channel number
+ */
+typedef enum {
+	LS_4G_DSP_NORMAL_CH = 0,
+	LS_4G_DSP_ONDEMAND_CH = 1,
+	LS_5G_DSP_NORMAL_CH,
+	LS_5G_DSP_ONDEMAND_CH,
+	LS_MCU_NORMAL_CH, //Shaolin or iA
+	LS_MCU_ONDEMAND_CH, //Shaolin or iA
+	LS_CH_NUM
+}LS_CH_ID;
+
+/*!
+ *  @brief LS set id enumeration
+ *  @param LS_4G_DSP_ALL             LS 4G DSP normal and ondemand channel
+ *  @param LS_5G_DSP_ALL             LS 5G DSP normal and ondemand channel
+ * 	@param LS_MCU_ALL				 LS MCU normal and ondemand channel
+ * 	@param LS_SET_NUM			     LS all set channel number
+ */
+typedef enum {
+    LS_4G_DSP_ALL = 0,
+    LS_5G_DSP_ALL, 
+    LS_MCU_ALL,
+    LS_SET_NUM
+}LS_SET_ID;
+
+
+/*!
+ *  @brief LS EMI mode enumeration
+ *  @param LS_STREAM_EMI			LS configures streaming EMI
+ *	@param LS_WRAP_EMI				LS configures wrapping EMI
+ *	@param LS_EMI_MODE_NUM          LS EMI mode number
+ */
+typedef enum{
+	LS_STREAM_EMI = 0,
+	LS_WRAP_EMI = 1,
+	LS_EMI_MODE_NUM
+}LS_EMI_MODE;
+
+/*!
+ *  @brief LS mode type enumeration
+ *  @param LS_NON_PLS_MODE			user set LS as non-PLS logging/normal logging(USB, SD logging)
+ *	@param LS_PLS_MODE				user set LS as PLS logging(Passive Logging to SD)
+ *	@param LS_MODE_TYPE_NUM         LS mode type number
+ */
+typedef enum{
+    LS_NON_PLS_MODE = 0, 
+    LS_PLS_MODE = 1,
+    LS_MODE_TYPE_NUM
+}LS_MODE_TYPE;
+
+/*!
+ *  @brief LS output enumeration
+ *  @param LS_TO_SIB			LS output to SIB.
+ *	@param LS_TO_EMI			LS output to EMI.
+ *	@param LS_OUTPUT_NUM        LS output number
+ */
+typedef enum {
+    LS_TO_SIB = 0,
+    LS_TO_EMI,
+    LS_OUTPUT_NUM
+}LS_OUTPUT;
+
+/*!
+ *  @brief LS internal buffer unlock threshold setting enumeration
+ *  @param LS_EMPTY					 LS buffer unlock when the L2 is totally empty
+ *	@param LS_HALF_EMPTY			 LS buffer unlock when the L2 is 1/2 empty
+ *	@param LS_QUATER_EMPTY           LS buffer unlock when the L2 is 1/4 empty
+ *  @param LS_BUF_UNLOCK_THRS_NUM    LS buffer unlock number
+ */
+typedef enum {
+    LS_EMPTY = 0,
+    LS_HALF_EMPTY = 1,
+    LS_QUATER_EMPTY = 2,
+    LS_BUF_UNLOCK_THRS_NUM
+}LS_INTERNAL_BUF_UNLOCK_THS;
+
+/*!
+ *  @brief LS mode type enumeration
+ *  @param DENY_ALL						LS do not let any data in.
+ *	@param ACCEPT_GROUP0				LS only let the souce ID MSB = 0 data in.
+ *	@param ACCEPT_GROUP1         		LS only let the source ID MSB = 1 data in.
+ *	@param ACCEPT_BOTH					LS accept all source ID data.
+ *	@param DECODER_GROUP_POLICY_NUM     The group policy setting number
+ */
+typedef enum{
+    DENY_ALL = 0,
+    ACCEPT_GROUP0 = 1,
+    ACCEPT_GROUP1 = 2,
+    ACCEPT_BOTH = 3,
+    DECODER_GROUP_POLICY_NUM
+}DECODER_GROUP_POLICY;
+
+#else
+#error "No chip matched, please check it."
+#endif
+
+/*!
+ *  @brief LS get EMI buffer address & length whether is wrapped or not
+ *  @param LS_NO_WRAPPED          LS return without wrapped address & length
+ *  @param LS_WRAPPED             LS return with wrapped address & length
+ */
+typedef enum {
+    LS_GET_DATA,
+    LS_GET_NO_DATA
+}LS_GET_ADDR_LEN_INFO;
+
+/*!
+ *  @brief LS interrupt issue mode
+ *  @param LS_INT_THRESHOLD_MODE        LS issue interrupt by threshold count
+ *  @param LS_INT_REMAIN_SIZE_MODE      LS issue interrupt by EMI remain size
+ */
+typedef enum {
+    LS_INT_THRESHOLD_MODE,
+    LS_INT_REMAIN_SIZE_MODE
+}LS_LOGSEQ_INT_MODE;
+
+/*!
+ *  @brief LS EMI bandwidth selection. HW default is LS_BW_5US
+ */
+typedef enum{
+    LS_BW_NO_LIMIMT,
+    LS_BW_4US,
+    LS_BW_5US,
+    LS_BW_10US,
+    LS_BW_16US,
+    LS_BW_21US,
+    LS_BW_32US,
+    LS_BW_64US,
+    LS_BW_128US,
+    LS_BW_256US
+}LS_BW_CTRL;
+
+/*!
+ *  @brief LS logging mode: user only uses LS_NORMAL, and the others are for driver verification
+ */
+typedef enum{
+    LS_NORMAL = 0,
+    LS_L2AUTO = 1,
+    LS_INAUTO = 2,
+    LS_TEST_MODE = 4
+}LS_LOGGING_MODE;
+
+
+
+/*!
+ *  @brief LS threshold buffer query result: when user query threshold buffer info, the return value will be as below
+ */
+typedef enum {
+    LS_QUERY_END,
+    LS_QUERY_CONTINUE,
+    LS_QUERY_INVALID
+}LS_QUERY_THRS_BUF_INFO;
+
+#if defined(__MD93__) || defined(__MD95__)
+/*!
+ *  @brief define macro to configure LSInitInfo
+ */
+#define LS_Init_Info_initial    {0, 0, LS_BW_5US, 0, 0, 0, LS_NORMAL, 1, 0, 1, 0, 0, 0, LS_STREAM_EMI, 0}
+
+/*!
+ *  @brief LOG_SEQ_Init_Info is used to record the LOG_SEQ IP initial information
+ */
+typedef struct{
+    /*!
+     *  @brief ls_emi_base_addr is EMI base address
+     */
+    kal_uint32  ls_emi_base_addr;           // emi buffer address
+    /*!
+     *  @brief ls_emi_size is EMI buffer size (unit:byte)
+     */
+    kal_uint32  ls_emi_size:27;                // emi buffer size (unit:byte)
+     /*!
+     *  @brief ls_emi_bandwidth_ctrl is EMI bandwidth control(0~9, 0 is no limit)
+     */
+    kal_uint32  ls_emi_bandwidth_ctrl:4;      // 0~9, 0 is no limit
+    /*!
+     *  @brief ls_emi_wrapping_mode_en is EMI buffer wrapping mode enable(no interrupt will be issued, no EMI buffer blocking when LS write EMI buffer)
+     */
+    kal_uint32  ls_emi_wrapping_mode_en:1;    // 1, wrapping mode enable
+    /*!
+     *  @brief ls_emi_over_ths_int_level is EMI buffer over threshold interrupt level(unit:byte)
+     *         when threshold count over this level, LS will issue interrupt
+     */
+    kal_uint32  ls_emi_over_ths_int_level:27;
+    /*!
+     *  @brief ls_emi_over_ths_en is Enable LS to issue interrupt when threshold count beyond the LS_EMI_BUF_OVER_THS_LEVEL
+     */
+    kal_uint32  ls_emi_over_ths_en:1;
+    /*!
+     *  @brief ls_log_mode_en is LS input mode selection (0:normal, 1:L2AUTO mode, 2:INAUTO mode, 4:SW test mode,
+     */
+    kal_uint32  ls_log_mode_en:3;
+    /*!
+     *  @brief ls_output_to_emi is LS output path(0:output to ATB, 1:output to EMI)
+     */
+    kal_uint32  ls_output_to_emi:1;
+    /*!
+     *  @brief ls_auto_test_init_val is initial value control of auto test mode counter
+     */
+    kal_uint32  ls_auto_test_init_val:14;
+    /*!
+     *  @brief ls_internal_buf_unlock_ths is internal buffer unlock thesis after internal buffer full(0~2, 0:total empty, 1:half empty, 2:usage 1/4)
+     */
+    kal_uint32  ls_internal_buf_unlock_ths:2; // 0~2
+    /*!
+     *  @brief ls_emi_pri_ultra_en is LS Enable EMI Priority Dynamic Adjustment Feature
+     */
+    kal_uint32  ls_emi_pri_ultra_en:1;
+    /*!
+     *  @brief ls_emi_pri_ultra_h_level is LS set EMI priority to ULTRA if L2 buffer usage beyond this level (unit:128 bytes)
+     */
+    kal_uint32  ls_emi_pri_ultra_h_level:6;
+    /*!
+     *  @brief ls_emi_pri_ultra_l_level is LS set EMI priority to normal if L2 buffer usage below this level (unit:128 bytes)
+     */
+    kal_uint32  ls_emi_pri_ultra_l_level:6;
+	/*!
+	*  @brief ls_emi_mode is user can select emi to streaming mode or PLS mode
+	*/
+	kal_uint32	ls_emi_mode_select:1;
+    /*!
+     *  @brief reserve
+     */
+    kal_uint32  rsv:2;
+}LOG_SEQ_Init_Info;
+
+/*!
+ *  @brief LOG_SEQ_Callback_Info is used to record the LOG_SEQ IP callback functions
+ */
+typedef struct{
+    /*!
+     *  @brief buffer_over_ths_callback is LS callback function for EMI over threshold
+     */
+    void (*buffer_over_ths_callback)(kal_uint8);
+    /*!
+     *  @brief flush_callback is LS callback function for EMI flush in exception mode
+     */
+    void (*flush_ex_callback)(kal_uint8, kal_uint32, kal_uint32);
+    /*!
+     *  @brief the swwa callback for DHL to decide if activating sw workaround or assert.     
+     *  @param channel id     
+     */
+    void (*action_for_ls_abort_timeout)(kal_uint8);
+    
+}LOG_SEQ_Callback_Info;
+
+#elif defined(__MD97__)||defined(__MD97P__)
+/*!
+ *  @brief LOG_SEQ_Init_Info is used to record the LOG_SEQ IP initial information
+ */
+typedef struct{
+	/*!
+	 *	@brief ls_emi_base_addr is EMI base address
+	 */
+	kal_uint32	ls_emi_base_addr;			// emi buffer address
+	/*!
+	 *	@brief ls_emi_size is EMI buffer size (unit:byte)
+	 */
+	kal_uint32	ls_emi_size:27; 			   // emi buffer size (unit:byte)
+	 /*!
+	 *	@brief ls_emi_bandwidth_ctrl is EMI bandwidth control(0~9, 0 is no limit)
+	 */
+	kal_uint32	ls_emi_bandwidth_ctrl:4;	  // 0~9, 0 is no limit
+	/*!
+	 *	@brief ls_emi_wrapping_mode_en is EMI buffer wrapping mode enable(no interrupt will be issued, no EMI buffer blocking when LS write EMI buffer)
+	 */
+	kal_uint32	ls_emi_wrapping_mode_en:1;	  //0, streaming mode enable. 1, wrapping mode enable (DHL did not have to fill this variable)
+	/*!
+	 *	@brief ls_emi_over_ths_int_level is EMI buffer over threshold interrupt level(unit:byte)
+	 *		   when threshold count over this level, LS will issue interrupt
+	 */
+	kal_uint32	ls_emi_over_ths_int_level:27;
+	/*!
+	 *	@brief ls_emi_over_ths_en is Enable LS to issue interrupt when threshold count beyond the LS_EMI_BUF_OVER_THS_LEVEL
+	 */
+	kal_uint32	ls_emi_over_ths_en:1;
+	/*!
+	 *	@brief ls_log_mode_en is LS input mode selection (0:normal, 1:L2AUTO mode, 2:INAUTO mode, 4:SW test mode,
+	 */
+	kal_uint32	ls_log_mode_en:3;
+	/*!
+	 *	@brief ls_output_to_emi is LS output path(0:output to ATB, 1:output to EMI)
+	 */
+	kal_uint32	ls_output_to_emi:1;
+	/*!
+	 *	@brief ls_auto_test_init_val is initial value control of auto test mode counter
+	 */
+	kal_uint32	ls_auto_test_init_val:14;
+	/*!
+	 *	@brief ls_internal_buf_unlock_ths is internal buffer unlock thesis after internal buffer full(0~2, 0:total empty, 1:half empty, 2:usage 1/4)
+	 */
+	kal_uint32	ls_internal_buf_unlock_ths:2; // 0~2 0: empty, 1: half-empty, 2: quater-empty
+	/*!
+	 *	@brief ls_emi_pri_ultra_en is LS Enable EMI Priority Dynamic Adjustment Feature
+	 */
+	kal_uint32	ls_emi_pri_ultra_en:1;
+	/*!
+	 *	@brief ls_emi_pri_ultra_h_level is LS set EMI priority to ULTRA if L2 buffer usage beyond this level (unit:128 bytes)
+	 */
+	kal_uint32	ls_emi_pri_ultra_h_level:6;
+	/*!
+	 *	@brief ls_emi_pri_ultra_l_level is LS set EMI priority to normal if L2 buffer usage below this level (unit:128 bytes)
+	 */
+	kal_uint32	ls_emi_pri_ultra_l_level:6;
+	/*!
+	*  @brief ls_emi_mode is user can select emi to streaming mode or PLS mode
+	*/
+	kal_uint32	ls_mode_type_select:1; //PLS mode/non-PLS mode
+	/*!
+	 *	@brief reserve1
+	 */
+	kal_uint32	rsv1:2;
+	/*!
+	 *	@brief ls_group_policy is set the decoder policy to each LS (total 6 LS need to set)
+	 */
+	kal_uint8	ls_group_policy:2;
+	/*!
+	 *	@brief ls_hw_pwr_protect_en is set the hw lock power if ls_back_done = 0
+	 */	
+	kal_uint8	ls_hw_pwr_protect_en:1;
+	/*!
+	 *	@brief reserve2
+	 */
+	kal_uint8	rsv2:5;
+    /*!
+     *  @brief buffer_over_ths_callback is LS callback function for EMI over threshold
+     */
+	void (*buffer_over_ths_callback)(LS_CH_ID); 	// EMI interrupt callback(SW)
+    /*!
+     *  @brief flush_callback is LS callback function for EMI flush in exception mode
+     */
+	void (*flush_ex_callback)(LS_CH_ID, kal_uint32, kal_uint32);// LS flush in EE flow callback(SW)
+    /*!
+     *  @brief the swwa callback for DHL to decide if activating sw workaround or assert.     
+     *  @param channel id     
+     */
+	void (*action_for_ls_abort_timeout)(LS_CH_ID); // LS abort timeout swwa callback(SW)
+}LOG_SEQ_Init_Info;
+
+/*!
+ *  @brief LOG_SEQ_Sleep_Error_Status is used to record the LOG_SEQ sleep flow error information
+ */
+typedef struct{
+	LS_SLEEP_ERROR_CODE error_id[LS_CH_NUM];//the error information is recorded by channel
+}LOG_SEQ_Sleep_Error_Status;
+
+#else
+#error "No chip matched, please check it."
+#endif
+
+/*!
+ *  @brief LOG_SEQ_Emi_Buf_Addr_Len is EMI buffer address & length of EMI log
+ */
+typedef struct{
+    /*!
+     *  @brief addr is EMI log start address
+     */
+    kal_uint32  addr;
+    /*!
+     *  @brief len is EMI log length
+     */
+    kal_uint32  len;
+}LOG_SEQ_Emi_Buf_Addr_Len;
+
+/*!
+ *  @brief LOG_SEQ_Thrs_Buf_Info is EMI threshold buffer address & length of EMI log
+ */
+typedef struct log_seq_thrs_buf_info_t{
+    kal_uint32  addr;
+    kal_uint32  len;
+} LOG_SEQ_Thrs_Buf_Info;
+
+//===========================================================================
+
+#if defined(__MD93__) || defined(__MD95__)
+/*!
+ *  @brief LOG SEQ driver init
+ *  @param ch_id            channel id
+ *  @param pInitInfo        initial info.
+ */
+void logseq_drv_init(kal_uint8 ch_id, LOG_SEQ_Init_Info* pInitInfo);
+
+/*!
+ *  @brief LOG SEQ callback function init
+ *  @param pCallbackInfo    callback function info
+ */
+void logseq_drv_buf_full_callback_init(LOG_SEQ_Callback_Info* pCallbackInfo);
+
+/*!
+ *  @brief LOG SEQ get address and length that should be handled
+ *  @param ch_id            channel id
+ *  @param ls_addr_len      addr&len info
+ */
+void logseq_drv_get_addr_len(kal_uint8 ch_id, LOG_SEQ_Thrs_Buf_Info *thrs_buf);
+
+/*!
+ *  @brief LOG SEQ release EMI buffer from read pointer
+ *  @param ch_id            channel id
+ *  @param release_size     release size of EMI buffer
+ */
+void logseq_drv_release_emi_buf(kal_uint8 ch_id, kal_uint32 release_size);
+
+
+/*!
+ *  @brief LOG SEQ release EMI buffer from read pointer
+ *  @param ch_id            channel id
+ *  @param release_size     release size of EMI buffer
+ */
+void logseq_drv_release_emi_buf_ex(kal_uint8 ch_id, kal_uint32 release_size);
+
+
+/*!
+ *  @brief LOG SEQ stop LS with flush log in EMI buffer
+ *  @param ch_id            channel id
+ */
+kal_uint32 logseq_drv_stop(kal_uint8 ch_id);
+
+/*!
+ *  @brief LOG SEQ stop LS immediately
+ *  @param ch_id            channel id
+ */
+kal_uint32 logseq_drv_stop_im(kal_uint8 ch_id);
+
+/*!
+ *  @brief LOG SEQ resume LS logging from stop
+ *  @param ch_id            channel id
+ */
+kal_uint32 logseq_drv_resume(kal_uint8 ch_id);
+
+/*!
+ *  @brief LOG SEQ stop/re-dump LS in exception mode
+ *  @param ch_id                channel id
+ *  @param whole_sys_flush_en   trigger whole system flush or not
+ */
+kal_uint32 logseq_drv_stop_redump_ex(kal_uint8 ch_id, kal_bool whole_sys_flush_en);
+
+/*!
+ *  @brief LOG SEQ query EMI threshold buffer information
+ *  @param ch_id                channel id
+ *  @param thrs_buf             threshold buffer information
+ */
+kal_uint8 logseq_drv_query_thrs_buf(kal_uint8 ch_id, LOG_SEQ_Thrs_Buf_Info* thrs_buf);
+
+/*!
+ *  @brief LOG SEQ force release EMI threshold count without over threshold level
+ *  @param ch_id            channel id
+ */
+kal_uint32 logseq_drv_force_rls_ths_count(kal_uint8 ch_id);
+
+/*!
+ *  @brief LOG SEQ set EMI mode, default is LS_STREAM_EMI
+ *  @param ch_id            channel id
+ *	@param mode				LS_STREAM_EMI, LS_PLS_EMI
+ */
+kal_uint32 logseq_drv_set_mode(kal_uint8 ch_id, kal_atomic_uint32 mode);
+
+/*!
+ *  @brief LOG SEQ start tag log
+ *  @param void            
+ */
+kal_uint32 logseq_drv_tagStart(void);
+
+/*!
+ *  @brief LOG SEQ set EMI mode, default is LS_STREAM_EMI
+ *  @param void            
+ */
+void logseq_drv_tagEnd(void);
+
+#elif defined(__MD97__)||defined(__MD97P__)
+
+/*!
+ *  @brief LOG SEQ set/get SW TEST DATA register for test flag
+ *  @param ch_id           	channel ID
+ *  @param vaule             test flag vaule
+ */
+void  logseq_drv_set_sw_test_reg(LS_CH_ID ch_id, kal_uint32 vaule);	
+kal_uint32 logseq_drv_get_sw_test_reg(kal_uint8 ch_id);
+
+
+
+/*!
+ *  @brief LOG SEQ driver init (New in Gen97)
+ *  @param ch_id           	channel ID
+ *  @param pInitInfo  		fill the HW register initial value.
+ */
+void logseq_drv_set_default_value(LS_CH_ID ch_id, LOG_SEQ_Init_Info* pInitInfo);
+
+/*!
+ *  @brief LOG SEQ driver init
+ *  @param set_id           set id
+ *  @param normal_InitInfo  normal LS initial information
+ *	@param ondemand_InitInfo ondemand LS initial information
+ */
+void logseq_drv_init(LS_SET_ID set_id, LOG_SEQ_Init_Info* normalInitInfo, LOG_SEQ_Init_Info* ondemandInitInfo); 
+
+/*!
+ *  @brief LOG SEQ release EMI buffer from read pointer
+ *  @param ch_id            channel id
+ *  @param release_size     release size of EMI buffer
+ */
+void logseq_drv_release_emi_buf(LS_CH_ID ch_id, kal_uint32 release_size);
+
+/*!
+ *  @brief LOG SEQ stop LS with flush log in EMI buffer
+ *  @param 4G_DSP_en            4G DSP should do the LS backup/restore
+ *  @param 5G_DSP_en            5G DSP should do the LS backup/restore
+ *  @param MCU_en           	MCU should do the LS backup/restore
+ */
+LS_ERROR_CODE logseq_drv_stop(kal_uint8 _4G_DSP_en, kal_uint8 _5G_DSP_en, kal_uint8 MCU_en);
+
+/*!
+ *  @brief LOG SEQ stop LS immediately
+ *  @param 4G_DSP_en            4G DSP should do the LS backup/restore
+ *  @param 5G_DSP_en            5G DSP should do the LS backup/restore
+ *  @param MCU_en           	MCU should do the LS backup/restore
+ */
+LOG_SEQ_Sleep_Error_Status logseq_drv_stop_im(kal_uint8 _4G_DSP_en, kal_uint8 _5G_DSP_en, kal_uint8 MCU_en);
+
+/*!
+ *  @brief LOG SEQ resume LS logging from stop
+ *  @param 4G_DSP_en            4G DSP should do the LS backup/restore
+ *  @param 5G_DSP_en            5G DSP should do the LS backup/restore
+ *  @param MCU_en           	MCU should do the LS backup/restore
+ */
+LOG_SEQ_Sleep_Error_Status logseq_drv_resume(kal_uint8 _4G_DSP_en, kal_uint8 _5G_DSP_en, kal_uint8 MCU_en);
+
+/*!
+ *  @brief LOG SEQ resume LS logging from stop
+ *  @param 4G_DSP_en            4G DSP should do the LS backup/restore
+ *  @param 5G_DSP_en            5G DSP should do the LS backup/restore
+ *  @param MCU_en           	MCU should do the LS backup/restore
+ */
+LOG_SEQ_Sleep_Error_Status logseq_drv_resume_ex(kal_uint8 _4G_DSP_en, kal_uint8 _5G_DSP_en, kal_uint8 MCU_en);
+
+
+/*!
+ *  @brief LOG SEQ stop/re-dump LS in exception mode
+ *  @param ch_id                channel id
+ *  @param whole_sys_flush_en   trigger whole system flush or not
+ */
+LS_ERROR_CODE logseq_drv_stop_redump_ex(LS_CH_ID ch_id, kal_bool whole_sys_flush_en);
+
+/*!
+ *  @brief LOG SEQ query EMI threshold buffer information
+ *  @param ch_id                channel id
+ *  @param thrs_buf             threshold buffer information
+ */
+LS_QUERY_THRS_BUF_INFO logseq_drv_query_thrs_buf(LS_CH_ID ch_id, LOG_SEQ_Thrs_Buf_Info* thrs_buf);
+
+/*!
+ *  @brief LOG SEQ force release EMI threshold count without over threshold level
+ *  @param ch_id            channel id
+ */
+LS_ERROR_CODE logseq_drv_force_rls_ths_count(LS_CH_ID ch_id);
+
+/*!
+ *  @brief LOG SEQ set EMI mode, default is LS_STREAM_EMI
+ *  @param set_id            channel id
+ *	@param mode				 LS_NON_PLS_MODE, LS_PLS_MODE
+ */
+LS_ERROR_CODE logseq_drv_set_mode(LS_SET_ID set_id, LS_MODE_TYPE mode);
+
+/*!
+ *  @brief LOG SEQ start tag log
+ *  @param void            
+ */
+LS_ERROR_CODE logseq_drv_tagStart(void);
+
+/*!
+ *  @brief LOG SEQ set EMI mode, default is LS_STREAM_EMI
+ *  @param void            
+ */
+void logseq_drv_tagEnd(void);
+
+/*!
+ *  @brief set the stop address to the specific channel id (New in Gen97)
+ *  @param ch_id                channel id          
+ */
+LS_ERROR_CODE logseq_drv_set_stopAddr(LS_CH_ID ch_id, kal_uint32 addr);
+
+/*!
+ *  @brief clear the stop_address of specific channel id (New in Gen97)
+ *  @param ch_id                channel id          
+ */
+kal_bool logseq_drv_remove_stopAddr(LS_CH_ID ch_id);
+
+kal_uint32 logseq_drv_get_emi_type(kal_uint8 ch_id);
+
+#else
+#error "No chip matched, please check it."
+#endif
+
+//93.95.97 common prototype API
+/*!
+ *  @brief LOG SEQ set flush and resume simultaneously
+ *  @param ch_id            channel id
+ */
+kal_uint32 logseq_drv_flush_and_resume(kal_uint8 ch_id);
+
+/*!
+ *  @brief LOG SEQ get level 2 buffer usage
+ *  @param ch_id            channel id
+ */
+kal_uint32 logseq_drv_get_L2_usage(kal_uint8 ch_id);
+
+/*!
+ *  @brief LOG SEQ get EMI buffer size
+ *  @param ch_id            channel id
+ */
+kal_uint32 logseq_drv_get_emi_size(kal_uint8 ch_id);
+
+/*!
+ *  @brief LOG SEQ get EMI remain size
+ *  @param ch_id            channel id
+ */
+kal_uint32 logseq_drv_get_emi_remain_size(kal_uint32 ch_id);
+
+/*!
+ *  @brief check if LOG SEQ is init
+ *  @param ch_id            channel id
+ */
+kal_bool is_logseq_drv_init(kal_uint32 ch_id);
+
+/*!
+ *  @brief LOG SEQ call DHL callback after leaving dormant flow
+ *  @param ch_id            channel id
+ */
+kal_uint32 logseq_drv_resume_force_rls(kal_uint8 ch_id);
+
+/*!
+ *  @brief LOG SEQ LS reset on 93 sw workaround for LS abort failed
+ *  @param ch_id            channel id
+ */
+kal_uint32 logseq_drv_reinit_after_abort_failed(kal_uint8 ch_id);
+
+/*!
+ *  @brief LOG SEQ stop LS in exception mode
+ *  @param ch_id                channel id
+ *  @param whole_sys_flush_en   trigger whole system flush or not
+ */
+kal_uint32 logseq_drv_stop_ex(kal_uint8 ch_id, kal_bool whole_sys_flush_en);
+
+//20170801- OPPO NEW feature: to take the log from memory dump 
+//add two new APIs -logseq_drv_get_write_align_addr and logseq_drv_get_emi_wrapping_bit
+/*!
+ *  @brief get the emi write aligned address, read from HW reg or SW global on demand.
+register and backup variable
+ *  @param ch_id                channel id          
+ */
+kal_uint32 logseq_drv_get_write_align_addr(kal_uint8 ch_id);
+
+/*!
+ *  @brief judge if LOG SEQ get emi wrapping bit is set or not, read hw register and backup variable
+ *  @param ch_id                channel id          
+ */
+kal_bool logseq_drv_get_emi_wrapping_bit(kal_uint8 ch_id);
+
+//20180802- Gen97 new feature required by st3
+/*!
+ *  @brief get the emi write  address, read from HW reg.
+ *  @param ch_id                channel id          
+ */
+kal_uint32 logseq_drv_get_write_addr(kal_uint8 ch_id);
+
+/*!
+ *  @brief get the LS dbg information if LS abort timeout happened, 
+ the DHL should assert while using this API or it could cause HRT failed.
+ *  @param ch_id                channel id          
+ */
+void logseq_drv_ls_hang_dbg_info(kal_uint8 ch_id);
+
+/*!
+ *  @brief get the LS mode information 
+ the DHL can not call get mode API and set mode API at the same time
+ *  @param ch_id                channel id          
+ */
+kal_uint32 logseq_drv_get_mode_select(kal_uint8 ch_id);
+
+#endif /* LOG_SEQ_H_ */
diff --git a/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface.h b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface.h
new file mode 100644
index 0000000..b7e18aa
--- /dev/null
+++ b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface.h
@@ -0,0 +1,300 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * -----------
+ *   drv_mdap_interface.h
+ *
+ * Project:
+ * -----------
+ *   VMOLY
+ *
+ * Description:
+ * ------------
+ *   MD/AP interface driver related code
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#include "kal_general_types.h"
+
+#ifndef __DRV_MDAP_INTERFACE_H__
+#define __DRV_MDAP_INTERFACE_H__ 
+
+#if defined(__MTK_TARGET__) && !defined(__MAUI_BASIC__)
+#define __AMIF_TRACE_ENABLE__
+#define ENABLE_MDAPINTERFACE
+#endif
+
+#if defined(__MD93__)
+/* MD2SPM_DVFS_CON bit for configuration */
+#define MD2AP_CAMOUFLAGE_VAL    0x80000000
+#endif
+
+/* enumeration for all scenario */
+typedef enum
+{
+    #undef MDAP_SCENARIO_GROUP_INSTANCE
+    #undef MDAP_SCENARIO_INSTANCE
+    #undef MDAP_INSTANCE_BEGING
+    #undef MDAP_INSTANCE_END
+    #undef MDAP_ELM_INSTANCE
+    #undef MDAP_GEAR_INSTANCE
+
+    #define MDAP_INSTANCE_BEGING() E_MD2AP_SCENARIO_START = 0,
+    #define MDAP_SCENARIO_INSTANCE(SCENARIO,SCENARIO_GROUP,VALUE,GEAR_INDEX,MODE) SCENARIO VALUE,
+    #define MDAP_INSTANCE_END() E_MD2AP_SCENARIO_END,
+
+    #include "drv_mdap_interface_config.h"
+    MD2AP_LEGACY,    /* used by cl1mddvfs.c */
+    MD2AP_CAT6CA_DATAL = MD2AP_LEGACY,
+    MD2AP_CAT6NONCA_DATAL = MD2AP_LEGACY,
+    MD2AP_PAGING = MD2AP_LEGACY,
+    MD2AP_POSITION = MD2AP_LEGACY,
+    MD2AP_CELL_SEARCH = MD2AP_LEGACY,
+    MD2AP_CELL_MGT = MD2AP_LEGACY,
+    MD2AP_2G_TALKING = MD2AP_LEGACY,
+    MD2AP_2G_DATAL = MD2AP_LEGACY,
+    MD2AP_3G_TALKING = MD2AP_LEGACY,
+    MD2AP_3G_DATAL = MD2AP_LEGACY,
+} MD2AP_SCENARIO;
+
+/* enumeration for all scenario group */
+typedef enum
+{
+    #undef MDAP_SCENARIO_GROUP_INSTANCE
+    #undef MDAP_SCENARIO_INSTANCE
+    #undef MDAP_INSTANCE_BEGING
+    #undef MDAP_INSTANCE_END
+    #undef MDAP_ELM_INSTANCE
+
+    //#define MDAP_INSTANCE_BEGING() E_MD2AP_SCENARIO_GROUP_START = 0,
+    #define MDAP_SCENARIO_GROUP_INSTANCE(SCENARIO_GROUP, SCENARIO_GROUP_DEFAULT_SCENARIO,VALUE) SCENARIO_GROUP VALUE,
+    #define MDAP_INSTANCE_END() E_MD2AP_SCENARIO_GROUP_END,\
+                                E_MD2AP_SCENARIO_GROUP_DEFAULT,
+
+    #include "drv_mdap_interface_config.h"
+} MD2AP_SCENARIO_GROUP;
+
+/* enumeration for ELM index */
+typedef enum
+{
+    #undef MDAP_SCENARIO_GROUP_INSTANCE
+    #undef MDAP_SCENARIO_INSTANCE
+    #undef MDAP_INSTANCE_BEGING
+    #undef MDAP_INSTANCE_END
+    #undef MDAP_ELM_INSTANCE
+    #undef MDAP_GEAR_INSTANCE
+
+    #define MDAP_ELM_INSTANCE(CFG_INDEX, VALUE, R_LAT_NS, R_WIN_US, W_LAT_NS, W_WIN_US)    CFG_INDEX VALUE,
+    #define MDAP_INSTANCE_END()    E_MD2AP_ELM_INDEX_END,
+
+    #include "drv_mdap_interface_config.h"
+} MD2AP_ELM_INDEX;/* Each ELM configuration index to detect violation. */
+
+/* enumeration for GEAR index */
+typedef enum
+{
+    #undef MDAP_SCENARIO_GROUP_INSTANCE
+    #undef MDAP_SCENARIO_INSTANCE
+    #undef MDAP_INSTANCE_BEGING
+    #undef MDAP_INSTANCE_END
+    #undef MDAP_ELM_INSTANCE
+    #undef MDAP_GEAR_INSTANCE
+
+    #define MDAP_GEAR_INSTANCE(GEAR_INDEX, VALUE, ELM_INDEX)    GEAR_INDEX VALUE,
+    #define MDAP_INSTANCE_END()    E_MD2AP_GEAR_INDEX_END,
+
+    #include "drv_mdap_interface_config.h"
+} MD2AP_GEAR_INDEX; /* MD2AP Gear index */
+
+
+/* enumeration for MD2AP_ScenarioCheckAndConfig idx */
+typedef enum
+{
+    E_MD2AP_PRESET,
+    E_MD2AP_POSTSET,
+    E_MD2AP_START,
+    E_MD2AP_SWITCH,
+    E_MD2AP_DOR,    
+} MD2AP_FUNC_T;
+
+/* enumeration for all sim */
+typedef enum {
+    E_MD2AP_SIM1 = 0,
+    E_MD2AP_SIM2,
+    E_MD2AP_SIM3,
+    E_MD2AP_SIM4,
+    E_MD2AP_SIM_DC, /* Don't care. */
+    E_MD2AP_SIM_COUNT,
+    E_MD2AP_SIM_DC_3G_L1 = E_MD2AP_SIM_DC,    
+    E_MD2AP_SIM_DC_4G_L1 = E_MD2AP_SIM_DC,
+    E_MD2AP_SIM_DC_5G_L1 = E_MD2AP_SIM_DC,
+    E_MD2AP_SIM_SS  = E_MD2AP_SIM_DC,
+} MD2AP_SIM_ID;
+
+/* scenario and bit mapping table */
+typedef struct SCENARIO_INFO
+{
+    MD2AP_SCENARIO scenario;
+    MD2AP_GEAR_INDEX gear_index;
+    MD2AP_SCENARIO_GROUP group;
+}SCENARIO_INFO_T;/* Gear_index should be set for each scenario of GROUP */
+
+/* ELM table */
+typedef struct ELM_CFG
+{
+    MD2AP_ELM_INDEX elm_index;
+    kal_uint32      r_lat_ns;
+    kal_uint32      r_win_us;
+    kal_uint32      w_lat_ns;
+    kal_uint32      w_lat_us;
+}ELM_CFG_T;
+
+/* Gear table */
+typedef struct GEAR_CFG
+{
+    MD2AP_GEAR_INDEX gear_index;
+    MD2AP_ELM_INDEX  elm_index;
+}GEAR_CFG_T;
+
+/* scenario group table */
+typedef struct GROUP_STATUS
+{
+    MD2AP_SCENARIO scenario;
+    kal_bool preSetting;
+}GROUP_STATUS_T;
+
+/* test parameter */
+typedef enum MD2AP_TEST_TYPE_E
+{
+    MD2AP_TEST_TYPE_DEFAULT,
+    MD2AP_TEST_TYPE_END
+} MD2AP_TEST_TYPE_T;
+
+/* error code */
+typedef enum MD2AP_RET_E
+{
+    MD2AP_RET_SUCCESS = 0,
+    MD2AP_RET_PARA_OUT_OF_RANGE,
+    MD2AP_RET_SEQ_PRE_POST_NOT_IN_SEQ,
+    MD2AP_RET_SEQ_START_NOT_ALTER,
+} MD2AP_RET_T;
+
+void Drv_MDAPInterface_Init(void);
+
+/* For Dormant Backup/Restore */
+void Drv_MDAPInterface_Clear(void);
+void Drv_MDAPInterface_BackupClear(void);
+void Drv_MDAPInterface_Restore(void);
+void Drv_MDAPInterface_Dormant_Restore_Log(void);
+
+/* test and others */
+void Drv_MDAPInterface_Test(MD2AP_TEST_TYPE_T test_type);
+void Drv_MDAPInterface_Custom_Test(kal_uint32 cmd, kal_uint32 val);
+void Drv_MDAPInterface_DVFSRC_Log_On(kal_uint32 on);
+
+//YY: legacy code, User should know these function is no use.
+#define Drv_MD2AP_SetScenario(value)
+#define Drv_MD2AP_ClearScenario(value)
+
+kal_bool Drv_MDAPInterface_Dump(void);
+kal_uint32 drv_mdap_interface_hw_get_curr_scenario_reg();
+
+#if !defined(__MTK_TARGET__) || !defined(ENABLE_MDAPINTERFACE)/* AMIF disable */
+#define Drv_MD2AP_StartScenario(sim_id,value)
+#define Drv_MD2AP_preSetStartScenario(sim_id,value)
+#define Drv_MD2AP_postSetStartScenario(sim_id,value)
+#define Drv_MD2AP_SwitchScenario(sim_id,next_scenario)
+#else
+MD2AP_RET_T _Drv_MD2AP_StartScenario(MD2AP_SIM_ID sim_id, MD2AP_SCENARIO value);
+MD2AP_RET_T _Drv_MD2AP_preSetStartScenario(MD2AP_SIM_ID sim_id, MD2AP_SCENARIO value);
+MD2AP_RET_T _Drv_MD2AP_postSetStartScenario(MD2AP_SIM_ID sim_id, MD2AP_SCENARIO value);
+MD2AP_RET_T _Drv_MD2AP_SwitchScenario(MD2AP_SIM_ID, MD2AP_SCENARIO next_scenario);
+#define Drv_MD2AP_StartScenario(sim_id,value)	        _Drv_MD2AP_StartScenario(sim_id, value)
+#define Drv_MD2AP_preSetStartScenario(sim_id,value)     _Drv_MD2AP_preSetStartScenario(sim_id,value)
+#define Drv_MD2AP_postSetStartScenario(sim_id,value)    _Drv_MD2AP_postSetStartScenario(sim_id,value)
+#define Drv_MD2AP_SwitchScenario(sim_id,next_scenario)  _Drv_MD2AP_SwitchScenario(sim_id,next_scenario)
+#endif
+
+#endif
+
diff --git a/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config.h b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config.h
new file mode 100644
index 0000000..39f07c3
--- /dev/null
+++ b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config.h
@@ -0,0 +1,161 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * -----------
+ *   drv_mdap_interface.h
+ *
+ * Project:
+ * -----------
+ *   UMOLY
+ *
+ * Description:
+ * ------------
+ *   MD/AP interface driver related code
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef MDAP_SCENARIO_GROUP_INSTANCE
+#define MDAP_SCENARIO_GROUP_INSTANCE(SCENARIO_GROUP, SCENARIO_GROUP_DEFAULT_SCENARIO,VALUE)
+#endif
+
+#ifndef MDAP_SCENARIO_INSTANCE
+#define MDAP_SCENARIO_INSTANCE(SCENARIO,SCENARIO_GROUP,VALUE,GEAR_INDEX,MODE)
+#endif
+
+#ifndef MDAP_INSTANCE_BEGING
+#define MDAP_INSTANCE_BEGING()
+#endif
+
+#ifndef MDAP_INSTANCE_END
+#define MDAP_INSTANCE_END()
+#endif
+
+#ifndef MDAP_ELM_INSTANCE
+#define MDAP_ELM_INSTANCE(ELM_INDEX,VALUE,R_LAT_NS,R_WIN_US,W_LAT_NS,W_WIN_US)
+#endif
+
+#ifndef MDAP_GEAR_INSTANCE
+#define MDAP_GEAR_INSTANCE(GEAR_INDEX,VALUE,ELM_INDEX)
+#endif
+
+MDAP_INSTANCE_BEGING()
+
+#if defined(MT6763)
+  #include "drv_mdap_interface_config_mt6763.h"
+#elif defined(MT6739)
+  #include "drv_mdap_interface_config_mt6739.h"
+#elif defined(MT6771)
+  #include "drv_mdap_interface_config_mt6771.h"
+#elif defined(MT6765)
+  #include "drv_mdap_interface_config_mt6765.h"
+#elif defined(MT6295M)
+  #include "drv_mdap_interface_config_mt6295m.h"
+#elif defined(MT3967)
+  #include "drv_mdap_interface_config_mt3967.h"
+#elif defined(MT6779)
+  #include "drv_mdap_interface_config_mt6779.h"
+#elif defined(MT6297) || defined(MT6885) || defined(MT6873) || defined(MT6853) || defined(CHIP10992) || defined(MT6833) || defined(MT6877)/* APOLLO or PETRUS or MARGAUX or MOUTON or COLGIN or PALMER or MONTROSE */
+  #include "drv_mdap_interface_config_mt6297.h"  
+#elif defined(MERCURY)
+  #include "drv_mdap_interface_config_mt6297p.h"   
+#else
+  #error "Unsupported Chip"
+#endif
+
+MDAP_INSTANCE_END()
+
diff --git a/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt3967.h b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt3967.h
new file mode 100644
index 0000000..dce38e9
--- /dev/null
+++ b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt3967.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * -----------
+ *   drv_mdap_interface_config_mt3967.h
+ *
+ * Project:
+ * -----------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   Scenario Definition of MT6295M.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*                           Scenario Group,            Default Scenario        Value*/
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_2G,               MD2AP_2G_NO_INFO,       =0      )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GFDD,            MD2AP_3GFDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GTDD,            MD2AP_3GTDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G,               MD2AP_4G_NO_INFO,               )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_Tput,          MD2AP_4G_0Mbps,                 )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_positioning,   MD2AP_4G_NON_POSITIONING,       )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_C2K,              MD2AP_C2K_NO_INFO,              )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_L1,            MD2AP_4G_L1_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3G_FDD_L1,        MD2AP_3G_FDD_L1_NO_INFO,        )
+
+
+
+/* Scenarios in scenario group.
+** The sequence implies latency requirement from low to high.
+*/
+/*                     Scenario                         Scenario                 Value       MDAP           API
+**                     Name,                            group                    for ENUM,   bit,           invoking,       */
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_INFO,                scenario_2G,             =0,         MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_REQ,                 scenario_2G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_NONIDLE,      scenario_2G,             ,           MD2AP_GEAR1,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_IDLE,         scenario_2G,             ,           MD2AP_GEAR1,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_INFO,             scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_REQ,              scenario_3GFDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_TALKING,    scenario_3GFDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_PAGING,     scenario_3GFDD,          ,           MD2AP_GEAR1,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL1CC,          scenario_3GFDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL2CC,          scenario_3GFDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_INFO,             scenario_3GTDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_REQ,              scenario_3GTDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_TALKING,    scenario_3GTDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_PAGING,     scenario_3GTDD,          ,           MD2AP_GEAR9,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_HSPA,                scenario_3GTDD,          ,           MD2AP_GEAR14,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NO_INFO,                scenario_4G,             ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NO_REQ,                 scenario_4G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_CONNECTED,          scenario_4G,             ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_CONNECTED_MBMS,     scenario_4G,             ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL1CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL2CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR6,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL2CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR7,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL3CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR8,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL3CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR9,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL4CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR10,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL4CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR11,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_0Mbps,                  scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_75Mbps,                 scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_150Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_300Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_375Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_450Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_POSITIONING,        scenario_4G_positioning, ,           MD2AP_GEAR_INVALID,   MD2AP_SetClear     )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_POSITIONING,            scenario_4G_positioning, ,           MD2AP_GEAR31,   MD2AP_SetClear     )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_NO_SCENARIO,               scenario_2G,             ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_INFO,               scenario_C2K,            ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_REQ,                scenario_C2K,            ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_PAGING,                scenario_C2K,            ,           MD2AP_GEAR10,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_1X_TRAFFIC,            scenario_C2K,            ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_DO_DATALINK,           scenario_C2K,            ,           MD2AP_GEAR15,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_SHDR,                  scenario_C2K,            ,           MD2AP_GEAR16,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_INFO,             scenario_4G_L1,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_REQ,              scenario_4G_L1,          ,           MD2AP_GEAR0,     MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_0D0U,                scenario_4G_L1,          ,           MD2AP_GEAR2,     MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D0U,                scenario_4G_L1,          ,           MD2AP_GEAR20,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D1U,                scenario_4G_L1,          ,           MD2AP_GEAR21,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D1U,                scenario_4G_L1,          ,           MD2AP_GEAR21,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D2U,                scenario_4G_L1,          ,           MD2AP_GEAR22,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_3D1U,                scenario_4G_L1,          ,           MD2AP_GEAR23,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_3D2U,                scenario_4G_L1,          ,           MD2AP_GEAR23,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_3D3U,                scenario_4G_L1,          ,           MD2AP_GEAR23,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_4D1U,                scenario_4G_L1,          ,           MD2AP_GEAR24,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_4D2U,                scenario_4G_L1,          ,           MD2AP_GEAR24,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_4D3U,                scenario_4G_L1,          ,           MD2AP_GEAR24,    MD2AP_Switch       )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_NO_INFO,         scenario_3G_FDD_L1,      ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_NO_REQ,          scenario_3G_FDD_L1,      ,           MD2AP_GEAR0,    MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_IDLE,            scenario_3G_FDD_L1,      ,           MD2AP_GEAR8,    MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_WCDMA,           scenario_3G_FDD_L1,      ,           MD2AP_GEAR3,    MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_HSPA_1CC,        scenario_3G_FDD_L1,      ,           MD2AP_GEAR12,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_HSPA_2CC,        scenario_3G_FDD_L1,      ,           MD2AP_GEAR13,   MD2AP_Switch    )
+
+
+
+MDAP_GEAR_INSTANCE(MD2AP_GEAR0,   =0,     MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR1,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR2,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR3,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR4,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR5,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR6,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR7,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR8,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR9,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR10,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR11,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR12,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR13,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR14,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR15,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR16,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR17,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR18,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR19,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR20,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR21,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR22,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR23,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR24,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR25,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR26,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR27,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR28,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR29,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR30,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR31,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR_INVALID,  , MD2AP_ELM_CFG_1  )
+
+/*                ELM CFG Index,   Enum Value, R Latency   R Window     W Latency   W Window */
+/*                                             NanoSecond, MicroSecond, NanoSecond, MicroSecond */
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_0, =0,         4000+50,    200,         4000,       200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_1, ,           1000+50,    200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_2, ,           450+50,     200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_3, ,           400+50,     200,         300,        200                     )
+
diff --git a/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6295m.h b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6295m.h
new file mode 100644
index 0000000..ea36711
--- /dev/null
+++ b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6295m.h
@@ -0,0 +1,178 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * -----------
+ *   drv_mdap_interface_config_mt6295m.h
+ *
+ * Project:
+ * -----------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   Scenario Definition of MT6295M.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*                           Scenario Group,            Default Scenario        Value*/
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_2G,               MD2AP_2G_NO_INFO,       =0      )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GFDD,            MD2AP_3GFDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GTDD,            MD2AP_3GTDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G,               MD2AP_4G_NO_INFO,               )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_Tput,          MD2AP_4G_0Mbps,                 )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_positioning,   MD2AP_4G_NON_POSITIONING,       )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_C2K,              MD2AP_C2K_NO_INFO,              )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_L1,            MD2AP_4G_L1_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3G_FDD_L1,        MD2AP_3G_FDD_L1_NO_INFO,        )
+
+
+
+/* Scenarios in scenario group.
+** The sequence implies latency requirement from low to high.
+*/
+/*                     Scenario                         Scenario                 Value       MDAP           API
+**                     Name,                            group                    for ENUM,   bit,           invoking,       */
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_INFO,                scenario_2G,             =0,         MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_REQ,                 scenario_2G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_NONIDLE,      scenario_2G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_IDLE,         scenario_2G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_INFO,             scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_REQ,              scenario_3GFDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_TALKING,    scenario_3GFDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_PAGING,     scenario_3GFDD,          ,           MD2AP_GEAR1,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL1CC,          scenario_3GFDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL2CC,          scenario_3GFDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_INFO,             scenario_3GTDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_REQ,              scenario_3GTDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_TALKING,    scenario_3GTDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_PAGING,     scenario_3GTDD,          ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_HSPA,                scenario_3GTDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NO_INFO,                scenario_4G,             ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NO_REQ,                 scenario_4G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_CONNECTED,          scenario_4G,             ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_CONNECTED_MBMS,     scenario_4G,             ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL1CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL2CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR6,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL2CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR7,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL3CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR8,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL3CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR9,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL4CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR10,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL4CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR11,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_0Mbps,                  scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_75Mbps,                 scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_150Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_300Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_375Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_450Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_POSITIONING,        scenario_4G_positioning, ,           MD2AP_GEAR_INVALID,   MD2AP_SetClear     )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_POSITIONING,            scenario_4G_positioning, ,           MD2AP_GEAR15,   MD2AP_SetClear     )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_NO_SCENARIO,               scenario_2G,             ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_INFO,               scenario_C2K,            ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_REQ,                scenario_C2K,            ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_PAGING,                scenario_C2K,            ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_1X_TRAFFIC,            scenario_C2K,            ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_DO_DATALINK,           scenario_C2K,            ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_SHDR,                  scenario_C2K,            ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_INFO,             scenario_4G_L1,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_REQ,              scenario_4G_L1,          ,           MD2AP_GEAR0,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_0D0U,                scenario_4G_L1,          ,           MD2AP_GEAR0,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D0U,                scenario_4G_L1,          ,           MD2AP_GEAR1,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D1U,                scenario_4G_L1,          ,           MD2AP_GEAR5,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D1U,                scenario_4G_L1,          ,           MD2AP_GEAR6,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D2U,                scenario_4G_L1,          ,           MD2AP_GEAR7,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_3D1U,                scenario_4G_L1,          ,           MD2AP_GEAR7,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_3D2U,                scenario_4G_L1,          ,           MD2AP_GEAR7,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_3D3U,                scenario_4G_L1,          ,           MD2AP_GEAR7,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_4D1U,                scenario_4G_L1,          ,           MD2AP_GEAR7,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_4D2U,                scenario_4G_L1,          ,           MD2AP_GEAR7,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_4D3U,                scenario_4G_L1,          ,           MD2AP_GEAR7,    MD2AP_Switch       )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_NO_INFO,         scenario_3G_FDD_L1,      ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_NO_REQ,          scenario_3G_FDD_L1,      ,           MD2AP_GEAR0,    MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_IDLE,            scenario_3G_FDD_L1,      ,           MD2AP_GEAR3,    MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_WCDMA,           scenario_3G_FDD_L1,      ,           MD2AP_GEAR8,    MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_HSPA_1CC,        scenario_3G_FDD_L1,      ,           MD2AP_GEAR12,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_HSPA_2CC,        scenario_3G_FDD_L1,      ,           MD2AP_GEAR13,   MD2AP_Switch    )
+
+
+
+MDAP_GEAR_INSTANCE(MD2AP_GEAR0,   =0,     MD2AP_ELM_CFG_2  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR1,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR2,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR3,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR4,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR5,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR6,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR7,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR8,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR9,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR10,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR11,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR12,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR13,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR14,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR15,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR_INVALID,  , MD2AP_ELM_CFG_1 )
+
+/*                ELM CFG Index,   Enum Value, R Latency   R Window     W Latency   W Window */
+/*                                             NanoSecond, MicroSecond, NanoSecond, MicroSecond */
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_0, =0,         4000+50,    200,         4000,       200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_1, ,           1000+50,    200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_2, ,           450+50,     200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_3, ,           350+50,     200,         300,        200                     )
+
diff --git a/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6297.h b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6297.h
new file mode 100644
index 0000000..88e744f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6297.h
@@ -0,0 +1,233 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * -----------
+ *   drv_mdap_interface_config_mt3967.h
+ *
+ * Project:
+ * -----------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   Scenario Definition of MT6295M.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*                           Scenario Group,            Default Scenario        Value*/
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_2G,               MD2AP_2G_NO_INFO,       =0      )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GTDD,            MD2AP_3GTDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3G_FDD_L1,        MD2AP_3G_FDD_L1_NO_INFO,        )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_L1,            MD2AP_4G_L1_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_positioning,   MD2AP_4G_NON_POSITIONING,       )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_5G_L1,            MD2AP_5G_L1_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_C2K,              MD2AP_C2K_NO_INFO,              )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_SIB,              MD2AP_SIB_INACTIVE,             )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_DHL,              MD2AP_DHL_INACTIVE,             )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_DOR,              MD2AP_DOR_Leave,                )/* For AMIF MET dormant log only. */
+
+/***********Below: Legacy code for avoid build error. Not really use.*************************/
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GFDD,            MD2AP_3GFDD_NO_INFO,            )
+/***********Above: Legacy code for avoid build error. Not really use.*************************/
+
+
+/* Scenarios in scenario group.
+** The sequence implies latency requirement from low to high.
+*/
+/*                     Scenario                         Scenario                 Value       MDAP           API
+**                     Name,                            group                    for ENUM,   bit,           invoking,       */
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_INFO,                scenario_2G,             =0,         MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_REQ,                 scenario_2G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_IDLE,         scenario_2G,             ,           MD2AP_GEAR2,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_NONIDLE,      scenario_2G,             ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_INFO,               scenario_C2K,            ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_REQ,                scenario_C2K,            ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_DO_DATALINK,           scenario_C2K,            ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_SHDR,                  scenario_C2K,            ,           MD2AP_GEAR6,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_1X_TRAFFIC,            scenario_C2K,            ,           MD2AP_GEAR4,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_INFO,             scenario_3GTDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_REQ,              scenario_3GTDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_PAGING,     scenario_3GTDD,          ,           MD2AP_GEAR7,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_TALKING,    scenario_3GTDD,          ,           MD2AP_GEAR8,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_HSPA,                scenario_3GTDD,          ,           MD2AP_GEAR9,    MD2AP_PrePost      )//Datalinking
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_NO_INFO,         scenario_3G_FDD_L1,      ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_NO_REQ,          scenario_3G_FDD_L1,      ,           MD2AP_GEAR0,    MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_IDLE,            scenario_3G_FDD_L1,      ,           MD2AP_GEAR1,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_WCDMA,           scenario_3G_FDD_L1,      ,           MD2AP_GEAR10,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_HSPA_1CC,        scenario_3G_FDD_L1,      ,           MD2AP_GEAR11,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_HSPA_2CC,        scenario_3G_FDD_L1,      ,           MD2AP_GEAR12,   MD2AP_Switch    )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_INFO,             scenario_4G_L1,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_REQ,              scenario_4G_L1,          ,           MD2AP_GEAR0,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_0D0U,                scenario_4G_L1,          ,           MD2AP_GEAR13,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D0U,                scenario_4G_L1,          ,           MD2AP_GEAR14,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D1U,                scenario_4G_L1,          ,           MD2AP_GEAR14,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D1U,                scenario_4G_L1,          ,           MD2AP_GEAR15,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D2U,                scenario_4G_L1,          ,           MD2AP_GEAR15,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_3D1U,                scenario_4G_L1,          ,           MD2AP_GEAR16,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_3D2U,                scenario_4G_L1,          ,           MD2AP_GEAR16,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_3D3U,                scenario_4G_L1,          ,           MD2AP_GEAR16,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_4D1U,                scenario_4G_L1,          ,           MD2AP_GEAR17,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_4D2U,                scenario_4G_L1,          ,           MD2AP_GEAR17,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_4D3U,                scenario_4G_L1,          ,           MD2AP_GEAR17,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_5D1U,                scenario_4G_L1,          ,           MD2AP_GEAR18,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_5D2U,                scenario_4G_L1,          ,           MD2AP_GEAR18,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_5D3U,                scenario_4G_L1,          ,           MD2AP_GEAR18,    MD2AP_Switch       )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_POSITIONING,        scenario_4G_positioning, ,           MD2AP_GEAR0,    MD2AP_SetClear     )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_POSITIONING,            scenario_4G_positioning, ,           MD2AP_GEAR31,   MD2AP_SetClear     )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_NO_INFO,             scenario_5G_L1,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_NO_REQ,              scenario_5G_L1,          ,           MD2AP_GEAR0,    MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_1CC_15K,          scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_1CC_30K,          scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_1CC_60K,          scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_1CC_120K,         scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_1CC_240K,         scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_15K_15K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_15K_30K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_15K_60K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_15K_120K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_15K_240K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_30K_30K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_30K_60K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_30K_120K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_30K_240K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_60K_60K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_60K_120K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_60K_240K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_120K_120K,    scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_120K_240K,    scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_240K_240K,    scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_1CC_15K,          scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_1CC_30K,          scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_1CC_60K,          scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_1CC_120K,         scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_1CC_240K,         scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_15K_15K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_15K_30K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_15K_60K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_15K_120K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_15K_240K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_30K_30K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_30K_60K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_30K_120K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_30K_240K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_60K_60K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_60K_120K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_60K_240K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_120K_120K,    scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_120K_240K,    scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_240K_240K,    scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_SIB_INACTIVE,              scenario_SIB,            ,           MD2AP_GEAR0,    MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_SIB_ACTIVE_HIGHEST,        scenario_SIB,            ,           MD2AP_GEAR31,   MD2AP_Switch    )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_DHL_INACTIVE,              scenario_DHL,            ,           MD2AP_GEAR0,    MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_DHL_ACTIVE_HIGHEST,        scenario_DHL,            ,           MD2AP_GEAR31,   MD2AP_Switch    )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_DOR_Enter,                 scenario_DOR,            ,           MD2AP_GEAR0,    MD2AP_MET_LOG   )
+MDAP_SCENARIO_INSTANCE(MD2AP_DOR_Leave,                 scenario_DOR,            ,           MD2AP_GEAR_INVALID,   MD2AP_MET_LOG   )
+
+/***********Below: Legacy code for avoid build error. Not really use.*************************/
+/*********************************************************************************************/
+//Legacy code for scenario_3GFDD. We use scenario_3GFDD_L1 now.
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_INFO,             scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_REQ,              scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_TALKING,    scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_PAGING,     scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL1CC,          scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL2CC,          scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,    MD2AP_PrePost      )
+/*********************************************************************************************/
+/***********Above: Legacy code for avoid build error. Not really use.*************************/
+
+MDAP_GEAR_INSTANCE(MD2AP_GEAR0,   =0,     MD2AP_ELM_CFG_0 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR1,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR2,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR3,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR4,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR5,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR6,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR7,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR8,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR9,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR10,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR11,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR12,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR13,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR14,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR15,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR16,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR17,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR18,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR19,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR20,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR21,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR22,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR23,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR24,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR25,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR26,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR27,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR28,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR29,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR30,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR31,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR_INVALID,  , MD2AP_ELM_CFG_0 )
+
+/*                ELM CFG Index,   Enum Value, R Latency   R Window     W Latency   W Window */
+/*                                             NanoSecond, MicroSecond, NanoSecond, MicroSecond */
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_0, =0,         4000+50,    200,         4000,       200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_1, ,           1000+50,    200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_2, ,           450+50,     200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_3, ,           400+50,     200,         300,        200                     )
+
diff --git a/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6297p.h b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6297p.h
new file mode 100644
index 0000000..35a7bfa
--- /dev/null
+++ b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6297p.h
@@ -0,0 +1,233 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * -----------
+ *   drv_mdap_interface_config_mt6297p.h
+ *
+ * Project:
+ * -----------
+ *   VMOLY
+ *
+ * Description:
+ * ------------
+ *   Scenario Definition of MT6297p.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*                           Scenario Group,            Default Scenario        Value*/
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_2G,               MD2AP_2G_NO_INFO,       =0      )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GTDD,            MD2AP_3GTDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3G_FDD_L1,        MD2AP_3G_FDD_L1_NO_INFO,        )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_L1,            MD2AP_4G_L1_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_positioning,   MD2AP_4G_NON_POSITIONING,       )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_5G_L1,            MD2AP_5G_L1_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_C2K,              MD2AP_C2K_NO_INFO,              )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_SIB,              MD2AP_SIB_INACTIVE,             )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_DHL,              MD2AP_DHL_INACTIVE,             )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_DOR,              MD2AP_DOR_Leave,                )/* For AMIF MET dormant log only. */
+
+/***********Below: Legacy code for avoid build error. Not really use.*************************/
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GFDD,            MD2AP_3GFDD_NO_INFO,            )
+/***********Above: Legacy code for avoid build error. Not really use.*************************/
+
+
+/* Scenarios in scenario group.
+** The sequence implies latency requirement from low to high.
+*/
+/*                     Scenario                         Scenario                 Value       MDAP           API
+**                     Name,                            group                    for ENUM,   bit,           invoking,       */
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_INFO,                scenario_2G,             =0,         MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_REQ,                 scenario_2G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_IDLE,         scenario_2G,             ,           MD2AP_GEAR2,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_NONIDLE,      scenario_2G,             ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_INFO,               scenario_C2K,            ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_REQ,                scenario_C2K,            ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_DO_DATALINK,           scenario_C2K,            ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_SHDR,                  scenario_C2K,            ,           MD2AP_GEAR6,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_1X_TRAFFIC,            scenario_C2K,            ,           MD2AP_GEAR4,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_INFO,             scenario_3GTDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_REQ,              scenario_3GTDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_PAGING,     scenario_3GTDD,          ,           MD2AP_GEAR7,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_TALKING,    scenario_3GTDD,          ,           MD2AP_GEAR8,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_HSPA,                scenario_3GTDD,          ,           MD2AP_GEAR9,    MD2AP_PrePost      )//Datalinking
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_NO_INFO,         scenario_3G_FDD_L1,      ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_NO_REQ,          scenario_3G_FDD_L1,      ,           MD2AP_GEAR0,    MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_IDLE,            scenario_3G_FDD_L1,      ,           MD2AP_GEAR1,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_WCDMA,           scenario_3G_FDD_L1,      ,           MD2AP_GEAR10,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_HSPA_1CC,        scenario_3G_FDD_L1,      ,           MD2AP_GEAR11,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_HSPA_2CC,        scenario_3G_FDD_L1,      ,           MD2AP_GEAR12,   MD2AP_Switch    )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_INFO,             scenario_4G_L1,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_REQ,              scenario_4G_L1,          ,           MD2AP_GEAR0,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_0D0U,                scenario_4G_L1,          ,           MD2AP_GEAR13,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D0U,                scenario_4G_L1,          ,           MD2AP_GEAR14,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D1U,                scenario_4G_L1,          ,           MD2AP_GEAR14,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D1U,                scenario_4G_L1,          ,           MD2AP_GEAR15,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D2U,                scenario_4G_L1,          ,           MD2AP_GEAR15,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_3D1U,                scenario_4G_L1,          ,           MD2AP_GEAR16,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_3D2U,                scenario_4G_L1,          ,           MD2AP_GEAR16,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_3D3U,                scenario_4G_L1,          ,           MD2AP_GEAR16,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_4D1U,                scenario_4G_L1,          ,           MD2AP_GEAR17,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_4D2U,                scenario_4G_L1,          ,           MD2AP_GEAR17,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_4D3U,                scenario_4G_L1,          ,           MD2AP_GEAR17,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_5D1U,                scenario_4G_L1,          ,           MD2AP_GEAR18,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_5D2U,                scenario_4G_L1,          ,           MD2AP_GEAR18,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_5D3U,                scenario_4G_L1,          ,           MD2AP_GEAR18,    MD2AP_Switch       )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_POSITIONING,        scenario_4G_positioning, ,           MD2AP_GEAR_INVALID,   MD2AP_SetClear     )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_POSITIONING,            scenario_4G_positioning, ,           MD2AP_GEAR31,   MD2AP_SetClear     )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_NO_INFO,             scenario_5G_L1,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_NO_REQ,              scenario_5G_L1,          ,           MD2AP_GEAR0,    MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_1CC_15K,          scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_1CC_30K,          scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_1CC_60K,          scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_1CC_120K,         scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_1CC_240K,         scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_15K_15K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_15K_30K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_15K_60K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_15K_120K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_15K_240K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_30K_30K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_30K_60K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_30K_120K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_30K_240K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_60K_60K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_60K_120K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_60K_240K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_120K_120K,    scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_120K_240K,    scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_DL_2CC_240K_240K,    scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_1CC_15K,          scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_1CC_30K,          scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_1CC_60K,          scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_1CC_120K,         scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_1CC_240K,         scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_15K_15K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_15K_30K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_15K_60K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_15K_120K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_15K_240K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_30K_30K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_30K_60K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_30K_120K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_30K_240K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_60K_60K,      scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_60K_120K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_60K_240K,     scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_120K_120K,    scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_120K_240K,    scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_5G_L1_UL_2CC_240K_240K,    scenario_5G_L1,          ,           MD2AP_GEAR21,   MD2AP_Switch    )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_SIB_INACTIVE,              scenario_SIB,            ,           MD2AP_GEAR31,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_SIB_ACTIVE_HIGHEST,        scenario_SIB,            ,           MD2AP_GEAR31,   MD2AP_Switch    )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_DHL_INACTIVE,              scenario_DHL,            ,           MD2AP_GEAR31,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_DHL_ACTIVE_HIGHEST,        scenario_DHL,            ,           MD2AP_GEAR31,   MD2AP_Switch    )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_DOR_Enter,                 scenario_DOR,            ,           MD2AP_GEAR0,    MD2AP_MET_LOG   )
+MDAP_SCENARIO_INSTANCE(MD2AP_DOR_Leave,                 scenario_DOR,            ,           MD2AP_GEAR_INVALID,   MD2AP_MET_LOG   )
+
+/***********Below: Legacy code for avoid build error. Not really use.*************************/
+/*********************************************************************************************/
+//Legacy code for scenario_3GFDD. We use scenario_3GFDD_L1 now.
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_INFO,             scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_REQ,              scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_TALKING,    scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_PAGING,     scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL1CC,          scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL2CC,          scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,    MD2AP_PrePost      )
+/*********************************************************************************************/
+/***********Above: Legacy code for avoid build error. Not really use.*************************/
+
+MDAP_GEAR_INSTANCE(MD2AP_GEAR0,   =0,     MD2AP_ELM_CFG_0 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR1,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR2,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR3,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR4,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR5,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR6,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR7,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR8,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR9,   ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR10,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR11,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR12,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR13,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR14,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR15,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR16,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR17,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR18,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR19,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR20,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR21,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR22,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR23,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR24,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR25,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR26,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR27,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR28,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR29,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR30,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR31,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR_INVALID,  , MD2AP_ELM_CFG_0 )
+
+/*                ELM CFG Index,   Enum Value, R Latency   R Window     W Latency   W Window */
+/*                                             NanoSecond, MicroSecond, NanoSecond, MicroSecond */
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_0, =0,         4000+50,    200,         4000,       200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_1, ,           1000+50,    200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_2, ,           450+50,     200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_3, ,           400+50,     200,         300,        200                     )
+
diff --git a/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6739.h b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6739.h
new file mode 100644
index 0000000..b640c83
--- /dev/null
+++ b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6739.h
@@ -0,0 +1,180 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * -----------
+ *   drv_mdap_interface_config_mt6763.h
+ *
+ * Project:
+ * -----------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   MD/AP interface driver related code
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*                           Scenario Group,            Default Scenario        Value*/
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_2G,               MD2AP_2G_NO_INFO,       =0      )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GFDD,            MD2AP_3GFDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GTDD,            MD2AP_3GTDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G,               MD2AP_4G_NO_INFO,               )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_Tput,          MD2AP_4G_0Mbps,                 )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_positioning,   MD2AP_4G_NON_POSITIONING,       )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_C2K,              MD2AP_C2K_NO_INFO,              )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_L1,            MD2AP_4G_L1_NO_INFO,            )
+
+
+/* Scenarios in scenario group.
+** The sequence implies latency requirement from low to high.
+*/
+/*                     Scenario                         Scenario                 Value       MDAP           API
+**                     Name,                            group                    for ENUM,   bit,           invoking,       */
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_INFO,                scenario_2G,             =0,         MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_REQ,                 scenario_2G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_NONIDLE,      scenario_2G,             ,           MD2AP_GEAR2,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_IDLE,         scenario_2G,             ,           MD2AP_GEAR2,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_INFO,             scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_REQ,              scenario_3GFDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_TALKING,    scenario_3GFDD,          ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_PAGING,     scenario_3GFDD,          ,           MD2AP_GEAR1,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL1CC,          scenario_3GFDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL2CC,          scenario_3GFDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_INFO,             scenario_3GTDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_REQ,              scenario_3GTDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_TALKING,    scenario_3GTDD,          ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_PAGING,     scenario_3GTDD,          ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_HSPA,                scenario_3GTDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NO_INFO,                scenario_4G,             ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NO_REQ,                 scenario_4G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_CONNECTED,          scenario_4G,             ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_CONNECTED_MBMS,     scenario_4G,             ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL1CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL2CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR6,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL2CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR7,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL3CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR8,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL3CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR9,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL4CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR10,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL4CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR11,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_0Mbps,                  scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_75Mbps,                 scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_150Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_300Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_375Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_450Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_POSITIONING,        scenario_4G_positioning, ,           MD2AP_GEAR_INVALID,   MD2AP_SetClear     )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_POSITIONING,            scenario_4G_positioning, ,           MD2AP_GEAR15,   MD2AP_SetClear     )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_NO_SCENARIO,               scenario_2G,             ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_INFO,               scenario_C2K,            ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_REQ,                scenario_C2K,            ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_PAGING,                scenario_C2K,            ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_1X_TRAFFIC,            scenario_C2K,            ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_DO_DATALINK,           scenario_C2K,            ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_SHDR,                  scenario_C2K,            ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_INFO,             scenario_4G_L1,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_REQ,              scenario_4G_L1,          ,           MD2AP_GEAR0,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_0D0U,                scenario_4G_L1,          ,           MD2AP_GEAR0,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D0U,                scenario_4G_L1,          ,           MD2AP_GEAR1,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D1U,                scenario_4G_L1,          ,           MD2AP_GEAR5,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D1U,                scenario_4G_L1,          ,           MD2AP_GEAR6,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D2U,                scenario_4G_L1,          ,           MD2AP_GEAR7,    MD2AP_Switch       )
+
+MDAP_GEAR_INSTANCE(MD2AP_GEAR0,   =0,     MD2AP_ELM_CFG_2  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR1,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR2,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR3,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR4,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR5,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR6,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR7,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR8,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR9,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR10,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR11,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR12,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR13,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR14,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR15,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR_INVALID,  , MD2AP_ELM_CFG_1 )
+
+/*                ELM CFG Index,   Enum Value, R Latency   R Window     W Latency   W Window */
+/*                                             NanoSecond, MicroSecond, NanoSecond, MicroSecond */
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_0, =0,         4000+50,    200,         4000,       200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_1, ,           1000+50,    200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_2, ,           450+50,     200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_3, ,           350+50,     200,         300,        200                     )
+
diff --git a/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6763.h b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6763.h
new file mode 100644
index 0000000..b5ad9c2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6763.h
@@ -0,0 +1,184 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * -----------
+ *   drv_mdap_interface_config_mt6763.h
+ *
+ * Project:
+ * -----------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   MD/AP interface driver related code
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*                           Scenario Group,            Default Scenario        Value*/
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_2G,               MD2AP_2G_NO_INFO,       =0      )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GFDD,            MD2AP_3GFDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GTDD,            MD2AP_3GTDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G,               MD2AP_4G_NO_INFO,               )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_Tput,          MD2AP_4G_0Mbps,                 )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_positioning,   MD2AP_4G_NON_POSITIONING,       )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_C2K,              MD2AP_C2K_NO_INFO,              )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_L1,            MD2AP_4G_L1_NO_INFO,            )
+
+
+/* Scenarios in scenario group.
+** The sequence implies latency requirement from low to high.
+*/
+/*                     Scenario                         Scenario                 Value       MDAP           API
+**                     Name,                            group                    for ENUM,   bit,           invoking,       */
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_INFO,                scenario_2G,             =0,         MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_REQ,                 scenario_2G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_NONIDLE,      scenario_2G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_IDLE,         scenario_2G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_INFO,             scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_REQ,              scenario_3GFDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_TALKING,    scenario_3GFDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_PAGING,     scenario_3GFDD,          ,           MD2AP_GEAR1,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL1CC,          scenario_3GFDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL2CC,          scenario_3GFDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_INFO,             scenario_3GTDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_REQ,              scenario_3GTDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_TALKING,    scenario_3GTDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_PAGING,     scenario_3GTDD,          ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_HSPA,                scenario_3GTDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NO_INFO,                scenario_4G,             ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NO_REQ,                 scenario_4G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_CONNECTED,          scenario_4G,             ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_CONNECTED_MBMS,     scenario_4G,             ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL1CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL2CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR6,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL2CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR7,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL3CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR8,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL3CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR9,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL4CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR10,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL4CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR11,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_0Mbps,                  scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_75Mbps,                 scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_150Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_300Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_375Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_450Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_POSITIONING,        scenario_4G_positioning, ,           MD2AP_GEAR_INVALID,   MD2AP_SetClear     )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_POSITIONING,            scenario_4G_positioning, ,           MD2AP_GEAR15,   MD2AP_SetClear     )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_NO_SCENARIO,               scenario_2G,             ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_INFO,               scenario_C2K,            ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_REQ,                scenario_C2K,            ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_PAGING,                scenario_C2K,            ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_1X_TRAFFIC,            scenario_C2K,            ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_DO_DATALINK,           scenario_C2K,            ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_SHDR,                  scenario_C2K,            ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_INFO,             scenario_4G_L1,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_REQ,              scenario_4G_L1,          ,           MD2AP_GEAR0,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_0D0U,                scenario_4G_L1,          ,           MD2AP_GEAR0,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D0U,                scenario_4G_L1,          ,           MD2AP_GEAR1,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D1U,                scenario_4G_L1,          ,           MD2AP_GEAR5,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D1U,                scenario_4G_L1,          ,           MD2AP_GEAR6,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D2U,                scenario_4G_L1,          ,           MD2AP_GEAR7,    MD2AP_Switch       )
+
+MDAP_GEAR_INSTANCE(MD2AP_GEAR0,   =0,     MD2AP_ELM_CFG_2  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR1,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR2,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR3,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR4,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR5,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR6,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR7,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR8,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR9,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR10,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR11,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR12,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR13,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR14,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR15,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR_INVALID,  , MD2AP_ELM_CFG_1 )
+
+/*                ELM CFG Index,   Enum Value, R Latency   R Window     W Latency   W Window */
+/*                                             NanoSecond, MicroSecond, NanoSecond, MicroSecond */
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_0, =0,         4000+50,    200,         4000,       200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_1, ,           1000+50,    200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_2, ,           450+50,     200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_3, ,           350+50,     200,         300,        200                     )
+
diff --git a/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6765.h b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6765.h
new file mode 100644
index 0000000..9ab114b
--- /dev/null
+++ b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6765.h
@@ -0,0 +1,184 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * -----------
+ *   drv_mdap_interface_config_mt6763.h
+ *
+ * Project:
+ * -----------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   MD/AP interface driver related code
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*                           Scenario Group,            Default Scenario        Value*/
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_2G,               MD2AP_2G_NO_INFO,       =0      )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GFDD,            MD2AP_3GFDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GTDD,            MD2AP_3GTDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G,               MD2AP_4G_NO_INFO,               )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_Tput,          MD2AP_4G_0Mbps,                 )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_positioning,   MD2AP_4G_NON_POSITIONING,       )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_C2K,              MD2AP_C2K_NO_INFO,              )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_L1,            MD2AP_4G_L1_NO_INFO,            )
+
+
+/* Scenarios in scenario group.
+** The sequence implies latency requirement from low to high.
+*/
+/*                     Scenario                         Scenario                 Value       MDAP           API
+**                     Name,                            group                    for ENUM,   bit,           invoking,       */
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_INFO,                scenario_2G,             =0,         MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_REQ,                 scenario_2G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_NONIDLE,      scenario_2G,             ,           MD2AP_GEAR1,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_IDLE,         scenario_2G,             ,           MD2AP_GEAR1,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_INFO,             scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_REQ,              scenario_3GFDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_TALKING,    scenario_3GFDD,          ,           MD2AP_GEAR2,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_PAGING,     scenario_3GFDD,          ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL1CC,          scenario_3GFDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL2CC,          scenario_3GFDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_INFO,             scenario_3GTDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_REQ,              scenario_3GTDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_TALKING,    scenario_3GTDD,          ,           MD2AP_GEAR2,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_PAGING,     scenario_3GTDD,          ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_HSPA,                scenario_3GTDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NO_INFO,                scenario_4G,             ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NO_REQ,                 scenario_4G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_CONNECTED,          scenario_4G,             ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_CONNECTED_MBMS,     scenario_4G,             ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL1CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL2CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR6,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL2CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR7,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL3CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR8,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL3CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR9,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL4CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR10,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL4CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR11,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_0Mbps,                  scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_75Mbps,                 scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_150Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_300Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_375Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_450Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_POSITIONING,        scenario_4G_positioning, ,           MD2AP_GEAR_INVALID,   MD2AP_SetClear     )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_POSITIONING,            scenario_4G_positioning, ,           MD2AP_GEAR15,   MD2AP_SetClear     )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_NO_SCENARIO,               scenario_2G,             ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_INFO,               scenario_C2K,            ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_REQ,                scenario_C2K,            ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_PAGING,                scenario_C2K,            ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_1X_TRAFFIC,            scenario_C2K,            ,           MD2AP_GEAR2,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_DO_DATALINK,           scenario_C2K,            ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_SHDR,                  scenario_C2K,            ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_INFO,             scenario_4G_L1,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_REQ,              scenario_4G_L1,          ,           MD2AP_GEAR0,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_0D0U,                scenario_4G_L1,          ,           MD2AP_GEAR0,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D0U,                scenario_4G_L1,          ,           MD2AP_GEAR3,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D1U,                scenario_4G_L1,          ,           MD2AP_GEAR5,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D1U,                scenario_4G_L1,          ,           MD2AP_GEAR6,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D2U,                scenario_4G_L1,          ,           MD2AP_GEAR7,    MD2AP_Switch       )
+
+MDAP_GEAR_INSTANCE(MD2AP_GEAR0,   =0,     MD2AP_ELM_CFG_2  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR1,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR2,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR3,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR4,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR5,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR6,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR7,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR8,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR9,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR10,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR11,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR12,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR13,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR14,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR15,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR_INVALID,  , MD2AP_ELM_CFG_1 )
+
+/*                ELM CFG Index,   Enum Value, R Latency   R Window     W Latency   W Window */
+/*                                             NanoSecond, MicroSecond, NanoSecond, MicroSecond */
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_0, =0,         4000+50,    200,         4000,       200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_1, ,           1000+50,    200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_2, ,           450+50,     200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_3, ,           350+50,     200,         300,        200                     )
+
diff --git a/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6771.h b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6771.h
new file mode 100644
index 0000000..9ab114b
--- /dev/null
+++ b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6771.h
@@ -0,0 +1,184 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * -----------
+ *   drv_mdap_interface_config_mt6763.h
+ *
+ * Project:
+ * -----------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   MD/AP interface driver related code
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*                           Scenario Group,            Default Scenario        Value*/
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_2G,               MD2AP_2G_NO_INFO,       =0      )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GFDD,            MD2AP_3GFDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GTDD,            MD2AP_3GTDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G,               MD2AP_4G_NO_INFO,               )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_Tput,          MD2AP_4G_0Mbps,                 )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_positioning,   MD2AP_4G_NON_POSITIONING,       )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_C2K,              MD2AP_C2K_NO_INFO,              )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_L1,            MD2AP_4G_L1_NO_INFO,            )
+
+
+/* Scenarios in scenario group.
+** The sequence implies latency requirement from low to high.
+*/
+/*                     Scenario                         Scenario                 Value       MDAP           API
+**                     Name,                            group                    for ENUM,   bit,           invoking,       */
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_INFO,                scenario_2G,             =0,         MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_REQ,                 scenario_2G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_NONIDLE,      scenario_2G,             ,           MD2AP_GEAR1,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_IDLE,         scenario_2G,             ,           MD2AP_GEAR1,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_INFO,             scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_REQ,              scenario_3GFDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_TALKING,    scenario_3GFDD,          ,           MD2AP_GEAR2,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_PAGING,     scenario_3GFDD,          ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL1CC,          scenario_3GFDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL2CC,          scenario_3GFDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_INFO,             scenario_3GTDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_REQ,              scenario_3GTDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_TALKING,    scenario_3GTDD,          ,           MD2AP_GEAR2,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_PAGING,     scenario_3GTDD,          ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_HSPA,                scenario_3GTDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NO_INFO,                scenario_4G,             ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NO_REQ,                 scenario_4G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_CONNECTED,          scenario_4G,             ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_CONNECTED_MBMS,     scenario_4G,             ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL1CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL2CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR6,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL2CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR7,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL3CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR8,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL3CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR9,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL4CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR10,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL4CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR11,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_0Mbps,                  scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_75Mbps,                 scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_150Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_300Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_375Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_450Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_POSITIONING,        scenario_4G_positioning, ,           MD2AP_GEAR_INVALID,   MD2AP_SetClear     )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_POSITIONING,            scenario_4G_positioning, ,           MD2AP_GEAR15,   MD2AP_SetClear     )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_NO_SCENARIO,               scenario_2G,             ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_INFO,               scenario_C2K,            ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_REQ,                scenario_C2K,            ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_PAGING,                scenario_C2K,            ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_1X_TRAFFIC,            scenario_C2K,            ,           MD2AP_GEAR2,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_DO_DATALINK,           scenario_C2K,            ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_SHDR,                  scenario_C2K,            ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_INFO,             scenario_4G_L1,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_REQ,              scenario_4G_L1,          ,           MD2AP_GEAR0,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_0D0U,                scenario_4G_L1,          ,           MD2AP_GEAR0,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D0U,                scenario_4G_L1,          ,           MD2AP_GEAR3,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D1U,                scenario_4G_L1,          ,           MD2AP_GEAR5,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D1U,                scenario_4G_L1,          ,           MD2AP_GEAR6,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D2U,                scenario_4G_L1,          ,           MD2AP_GEAR7,    MD2AP_Switch       )
+
+MDAP_GEAR_INSTANCE(MD2AP_GEAR0,   =0,     MD2AP_ELM_CFG_2  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR1,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR2,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR3,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR4,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR5,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR6,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR7,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR8,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR9,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR10,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR11,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR12,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR13,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR14,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR15,  ,       MD2AP_ELM_CFG_3 )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR_INVALID,  , MD2AP_ELM_CFG_1 )
+
+/*                ELM CFG Index,   Enum Value, R Latency   R Window     W Latency   W Window */
+/*                                             NanoSecond, MicroSecond, NanoSecond, MicroSecond */
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_0, =0,         4000+50,    200,         4000,       200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_1, ,           1000+50,    200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_2, ,           450+50,     200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_3, ,           350+50,     200,         300,        200                     )
+
diff --git a/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6779.h b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6779.h
new file mode 100644
index 0000000..dce38e9
--- /dev/null
+++ b/mcu/interface/driver/devdrv/mdap_interface/drv_mdap_interface_config_mt6779.h
@@ -0,0 +1,194 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * -----------
+ *   drv_mdap_interface_config_mt3967.h
+ *
+ * Project:
+ * -----------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   Scenario Definition of MT6295M.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+/*                           Scenario Group,            Default Scenario        Value*/
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_2G,               MD2AP_2G_NO_INFO,       =0      )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GFDD,            MD2AP_3GFDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3GTDD,            MD2AP_3GTDD_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G,               MD2AP_4G_NO_INFO,               )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_Tput,          MD2AP_4G_0Mbps,                 )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_positioning,   MD2AP_4G_NON_POSITIONING,       )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_C2K,              MD2AP_C2K_NO_INFO,              )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_4G_L1,            MD2AP_4G_L1_NO_INFO,            )
+MDAP_SCENARIO_GROUP_INSTANCE(scenario_3G_FDD_L1,        MD2AP_3G_FDD_L1_NO_INFO,        )
+
+
+
+/* Scenarios in scenario group.
+** The sequence implies latency requirement from low to high.
+*/
+/*                     Scenario                         Scenario                 Value       MDAP           API
+**                     Name,                            group                    for ENUM,   bit,           invoking,       */
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_INFO,                scenario_2G,             =0,         MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_NO_REQ,                 scenario_2G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_NONIDLE,      scenario_2G,             ,           MD2AP_GEAR1,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_2G_CONNECTED_IDLE,         scenario_2G,             ,           MD2AP_GEAR1,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_INFO,             scenario_3GFDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NO_REQ,              scenario_3GFDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_TALKING,    scenario_3GFDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_NON_HSPA_PAGING,     scenario_3GFDD,          ,           MD2AP_GEAR1,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL1CC,          scenario_3GFDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GFDD_HSPA_DL2CC,          scenario_3GFDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_INFO,             scenario_3GTDD,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NO_REQ,              scenario_3GTDD,          ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_TALKING,    scenario_3GTDD,          ,           MD2AP_GEAR4,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_NON_HSPA_PAGING,     scenario_3GTDD,          ,           MD2AP_GEAR9,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_3GTDD_HSPA,                scenario_3GTDD,          ,           MD2AP_GEAR14,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NO_INFO,                scenario_4G,             ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NO_REQ,                 scenario_4G,             ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_CONNECTED,          scenario_4G,             ,           MD2AP_GEAR3,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_CONNECTED_MBMS,     scenario_4G,             ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL1CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL2CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR6,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL2CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR7,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL3CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR8,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL3CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR9,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL4CC_UL1CC,            scenario_4G,             ,           MD2AP_GEAR10,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_DL4CC_UL2CC,            scenario_4G,             ,           MD2AP_GEAR11,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_0Mbps,                  scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_75Mbps,                 scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_150Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_300Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_375Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_450Mbps,                scenario_4G_Tput,        ,           MD2AP_GEAR_INVALID,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_NON_POSITIONING,        scenario_4G_positioning, ,           MD2AP_GEAR_INVALID,   MD2AP_SetClear     )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_POSITIONING,            scenario_4G_positioning, ,           MD2AP_GEAR31,   MD2AP_SetClear     )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_NO_SCENARIO,               scenario_2G,             ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_INFO,               scenario_C2K,            ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_NO_REQ,                scenario_C2K,            ,           MD2AP_GEAR0,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_PAGING,                scenario_C2K,            ,           MD2AP_GEAR10,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_1X_TRAFFIC,            scenario_C2K,            ,           MD2AP_GEAR5,    MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_DO_DATALINK,           scenario_C2K,            ,           MD2AP_GEAR15,   MD2AP_PrePost      )
+MDAP_SCENARIO_INSTANCE(MD2AP_C2K_SHDR,                  scenario_C2K,            ,           MD2AP_GEAR16,   MD2AP_PrePost      )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_INFO,             scenario_4G_L1,          ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_NO_REQ,              scenario_4G_L1,          ,           MD2AP_GEAR0,     MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_0D0U,                scenario_4G_L1,          ,           MD2AP_GEAR2,     MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D0U,                scenario_4G_L1,          ,           MD2AP_GEAR20,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_1D1U,                scenario_4G_L1,          ,           MD2AP_GEAR21,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D1U,                scenario_4G_L1,          ,           MD2AP_GEAR21,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_2D2U,                scenario_4G_L1,          ,           MD2AP_GEAR22,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_3D1U,                scenario_4G_L1,          ,           MD2AP_GEAR23,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_3D2U,                scenario_4G_L1,          ,           MD2AP_GEAR23,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_3D3U,                scenario_4G_L1,          ,           MD2AP_GEAR23,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_4D1U,                scenario_4G_L1,          ,           MD2AP_GEAR24,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_4D2U,                scenario_4G_L1,          ,           MD2AP_GEAR24,    MD2AP_Switch       )
+MDAP_SCENARIO_INSTANCE(MD2AP_4G_L1_4D3U,                scenario_4G_L1,          ,           MD2AP_GEAR24,    MD2AP_Switch       )
+
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_NO_INFO,         scenario_3G_FDD_L1,      ,           MD2AP_GEAR_INVALID,   MD2AP_Developer    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_NO_REQ,          scenario_3G_FDD_L1,      ,           MD2AP_GEAR0,    MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_IDLE,            scenario_3G_FDD_L1,      ,           MD2AP_GEAR8,    MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_WCDMA,           scenario_3G_FDD_L1,      ,           MD2AP_GEAR3,    MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_HSPA_1CC,        scenario_3G_FDD_L1,      ,           MD2AP_GEAR12,   MD2AP_Switch    )
+MDAP_SCENARIO_INSTANCE(MD2AP_3G_FDD_L1_HSPA_2CC,        scenario_3G_FDD_L1,      ,           MD2AP_GEAR13,   MD2AP_Switch    )
+
+
+
+MDAP_GEAR_INSTANCE(MD2AP_GEAR0,   =0,     MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR1,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR2,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR3,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR4,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR5,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR6,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR7,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR8,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR9,   ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR10,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR11,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR12,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR13,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR14,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR15,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR16,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR17,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR18,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR19,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR20,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR21,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR22,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR23,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR24,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR25,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR26,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR27,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR28,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR29,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR30,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR31,  ,       MD2AP_ELM_CFG_3  )
+MDAP_GEAR_INSTANCE(MD2AP_GEAR_INVALID,  , MD2AP_ELM_CFG_1  )
+
+/*                ELM CFG Index,   Enum Value, R Latency   R Window     W Latency   W Window */
+/*                                             NanoSecond, MicroSecond, NanoSecond, MicroSecond */
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_0, =0,         4000+50,    200,         4000,       200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_1, ,           1000+50,    200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_2, ,           450+50,     200,         300,        200                     )
+MDAP_ELM_INSTANCE(MD2AP_ELM_CFG_3, ,           400+50,     200,         300,        200                     )
+
diff --git a/mcu/interface/driver/devdrv/mdipc/cc_irq_public.h b/mcu/interface/driver/devdrv/mdipc/cc_irq_public.h
new file mode 100644
index 0000000..d6fbfbd
--- /dev/null
+++ b/mcu/interface/driver/devdrv/mdipc/cc_irq_public.h
@@ -0,0 +1,147 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   cc_irq_public.h
+ *
+ * Project:
+ * --------
+ *   UMOLY
+ *
+ * Description:
+ * ------------
+ *   This Module defines CC IRQ API.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#if 0 //ndef __CC_IRQ_PUBLIC_H__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__CDMA2000_RAT__)/*_MD3_SUPPORT_*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif/*_MD3_SUPPORT_*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__CDMA2000_RAT__)/*_MD3_SUPPORT_*/ /* spinlock for MD1 & MD3 */
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif/*_MD3_SUPPORT_*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__CDMA2000_RAT__)/*_MD3_SUPPORT_*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif/*_MD3_SUPPORT_*/
+/* under construction !*/
+#endif    /* __CC_IRQ_PUBLIC_H__ */
+
diff --git a/mcu/interface/driver/devdrv/mdipc/cc_sys_comm_public.h b/mcu/interface/driver/devdrv/mdipc/cc_sys_comm_public.h
new file mode 100644
index 0000000..21247b5
--- /dev/null
+++ b/mcu/interface/driver/devdrv/mdipc/cc_sys_comm_public.h
@@ -0,0 +1,116 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   cc_sys_comm_public.h
+ *
+ * Project:
+ * --------
+ *   UMOLY
+ *
+ * Description:
+ * ------------
+ *   This Module defines CC SYS IRQ API.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#if 0 //ndef __CC_SYS_COMM_H__
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(__CDMA2000_RAT__)/*_MD3_SUPPORT_*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif/*_MD3_SUPPORT_*/
+/* under construction !*/
+#endif
diff --git a/mcu/interface/driver/devdrv/mdl_ebc/ebc_drv.h b/mcu/interface/driver/devdrv/mdl_ebc/ebc_drv.h
new file mode 100644
index 0000000..0d5813e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/mdl_ebc/ebc_drv.h
@@ -0,0 +1,171 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2010
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+ /*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *      ebc_drv.h
+ *
+ * Project:
+ * --------
+ *      UMOLY
+ *
+ * Description:
+ * ------------
+ *      This module defines the public APIs of EBC driver
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ *****************************************************************************/
+
+#ifndef EBC_DRV_H_
+#define EBC_DRV_H_
+
+#include "kal_general_types.h"
+
+// ============== define Channel Map ==================
+enum EBC_CH_ID {
+    EBC_MDL_RAKE_ID = 0,
+	EBC_MDL_RXBRP_ID,
+	EBC_MDL_MPC_ID,
+	EBC_MDL_IMC_ID,
+	EBC_MDL_ICC_ID,
+	EBC_MDP_MPC_ID,
+	EBC_MDP_IMC_ID,
+	EBC_MDP_ICC_ID,
+	EBC_MTOL_MPC_ID,
+	EBC_MTOL_IMC_ID,
+	EBC_MTOL_ICC_ID,
+    EBC_MDL_DFE_ID,
+    EBC_MDL_DFE2_ID,
+	EBC_CH_NUM
+};
+
+#define EBC_CH_BEGIN        (EBC_MDL_RAKE_ID)
+#define EBC_MDL_ID_BEGIN	(EBC_MDL_RAKE_ID)
+#define EBC_MDL2_ID_BEGIN   (EBC_MDL_DFE_ID)
+#define EBC_MDP_ID_BEGIN	(EBC_MDP_MPC_ID)
+#define EBC_MTOL_ID_BEGIN	(EBC_MTOL_MPC_ID)
+
+typedef union {
+	// all channel
+	kal_uint32 ALL;
+	// all channel of each type
+	struct {
+        kal_uint32 MDL_ALL:  5;	//ch id = 0~4
+		kal_uint32 MDP_ALL:  3;	//ch id = 5~7
+		kal_uint32 MTOL_ALL: 3;	//ch id = 8~10
+        kal_uint32 MDL2_ALL: 2; //ch id = 11~12
+	};
+	// each channel
+	struct {
+		kal_uint32 MDL_RAKE: 1;	//ch id = 1
+		kal_uint32 MDL_RXBRP:1;	//ch id = 2
+		kal_uint32 MDL_MPC:  1;	//ch id = 3
+		kal_uint32 MDL_IMC:  1;	//ch id = 4
+		kal_uint32 MDL_ICC:  1;	//ch id = 5
+		kal_uint32 MDP_MPC:  1;	//ch id = 6
+		kal_uint32 MDP_IMC:  1;	//ch id = 7
+		kal_uint32 MDP_ICC:  1;	//ch id = 8
+		kal_uint32 MTOL_MPC: 1;	//ch id = 9
+		kal_uint32 MTOL_IMC: 1;	//ch id = 10
+		kal_uint32 MTOL_ICC: 1;	//ch id = 11
+        kal_uint32 MDL_DFE1: 1; //ch id = 12
+        kal_uint32 MDL_DFE2: 1; //ch id = 13
+	};
+}EBC_CH_MAP;
+
+// ==================== Init Info ======================
+typedef struct {
+	kal_uint32 base_addr;
+	kal_uint32 size;
+} EBC_EMI_Info;
+
+typedef struct {
+	EBC_CH_MAP 	 ChEn;
+	kal_uint32 	 OptionFlag;
+	// return error, argu: channel id, base addr, size
+	kal_int32  (*flush_callback_ex)(kal_uint32, kal_uint32, kal_uint32);
+	void (*buffer_full_callback)(void);
+	EBC_EMI_Info ChBuf[EBC_CH_NUM];
+} EBC_Init_Info;
+
+#define EBC_INIT_INFO_DEFAULT 	{{0}, 0, 0, 0}
+
+// =================== EBC API ========================
+
+/* @brief EBC driver init
+ * @param initial info. & register callback function */
+kal_int32 ebc_drv_init(EBC_Init_Info* pInitInfo);
+
+/* @brief EBC driver stop in exception mode */
+kal_int32 ebc_drv_stop_ex(void);
+
+/* @brief EBC driver un-mask CIRQ */
+void ebc_drv_unmask_cirq(void);
+
+/* @brief EBC driver get all buffer full state */
+kal_uint32 ebc_drv_get_buf_full_state(void);
+
+/* @brief EBC driver clear buffer full state
+ * @param buffer map: one bit one buffer  */
+kal_uint32 ebc_drv_clr_buf_full_state(kal_uint32 BufMap);
+
+#endif /* EBC_DRV_H_ */
diff --git a/mcu/interface/driver/devdrv/mdl_ebc/mdl_reg_base.h b/mcu/interface/driver/devdrv/mdl_ebc/mdl_reg_base.h
new file mode 100644
index 0000000..9a11a2e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/mdl_ebc/mdl_reg_base.h
@@ -0,0 +1,22 @@
+/*
+ * mdl_reg.h
+ *
+ *  Created on: 2014/6/5
+ *      Author: MTK07117
+ */
+
+#ifndef MDL_REG_BASE_H_
+#define MDL_REG_BASE_H_
+
+// ===================== MDL register address ========================
+#define MDL_HW_NUM		(5)
+#define MDL0_BASEADDR	(0xA9B40000) // RAKE
+#define MDL1_BASEADDR	(0xA9340000) // RXBRP
+#define MDL2_BASEADDR	(0xAD601D00) // MPC
+#define MDL3_BASEADDR	(0xADE04500) // IMC
+#define MDL4_BASEADDR	(0xAEE01700) // ICC
+#define MDL2_HW_NUM		(2)
+#define MDL5_BASEADDR	(0xA7B40000) // DFE0
+#define MDL6_BASEADDR	(0xA3340000) // DFE1
+
+#endif /* MDL_REG_BASE_H_ */
diff --git a/mcu/interface/driver/devdrv/pcie/pcie_if.h b/mcu/interface/driver/devdrv/pcie/pcie_if.h
new file mode 100644
index 0000000..2121086
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pcie/pcie_if.h
@@ -0,0 +1,117 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   pcie.h
+ *
+ * Project:
+ * --------
+ *   VMOLY
+ *
+ * Description:
+ * ------------
+ *  PCIE device driver
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 10 09 2020 cindy.tu
+ * [MOLY00579078] [MT6880][Colgin][M.2][Low Power] Colgin Data Card(連 RVP) Flight mode suspend current: 4.3 mA  > target 4.1 mA
+ * 	
+ * 	.
+ *
+ * 08 14 2020 cody.lee
+ * [MOLY00558825] [Colgin] PCIE Loopback Test - add test option for one lane
+ * .
+ *
+ * 07 16 2020 cindy.tu
+ * [MOLY00520457] [PCIE][Colgin] PCIE driver
+ * Fix modis link error.
+ *
+ * 07 13 2020 cody.lee
+ * [MOLY00545672] [Colgin] PCIE MTCMOS CTRL API
+ *
+ * 06 01 2020 cindy.tu
+ * [MOLY00520457] [PCIE][Colgin] PCIE driver
+ * 	
+ * Sync pcie driver and fix build error
+ *
+ * 05 25 2020 cindy.tu
+ * [MOLY00503259] [PCIE][M70] PCIE link API
+ * 	
+ * Set SPM to use high speed clock instead of 32K when PCIE in low power state
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __PCIE_IF_H__
+#define __PCIE_IF_H__
+
+typedef enum{
+	PCIE_LINK_READY = 0, 
+	PCIE_NOT_INIT_ERR = 1, 
+	PCIE_LINK_NOT_READY = 2, 
+	PCIE_LINK_NOT_STABLE = 3, 
+	PCIE_LINK_UNKNOWN = 0xF,
+}PCIE_detect_result_e;
+typedef struct _pcie_link_status{
+	kal_uint32 lane_num;
+	kal_uint32 rate_level;
+}pcie_link_status_t;
+
+PCIE_detect_result_e pcie_detect(void);
+
+#ifdef __MTK_TARGET__
+PCIE_detect_result_e pcie_get_link_state(void);
+#else
+#define pcie_get_link_state()  (PCIE_LINK_UNKNOWN)
+#endif
+
+void pcie_report_link_status(pcie_link_status_t* pcie_link_status);
+
+extern kal_bool pcie_phy_loopback_test(kal_uint32);
+
+extern void pcie_mac_mtcmos_ctrl(kal_bool);
+extern void pcie_phy_mtcmos_ctrl(kal_bool);
+extern void pcie_cg_enable(void);
+extern void pcie_cg_disable(void);
+
+#endif
diff --git a/mcu/interface/driver/devdrv/pcmon/drv_pcmon.h b/mcu/interface/driver/devdrv/pcmon/drv_pcmon.h
new file mode 100644
index 0000000..f4fcf05
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pcmon/drv_pcmon.h
@@ -0,0 +1,264 @@
+#ifndef __DRV_PCMON_H__
+#define __DRV_PCMON_H__
+
+/*****************************************************************************
+ * Includes
+ *****************************************************************************/
+
+#include "drv_pcmon_common.h"
+#include "drv_pcmon_v2.h"
+
+/*****************************************************************************
+ * Type Definition
+ *****************************************************************************/
+
+typedef PDAMON_CFG_V2_T             PDAMON_CFG_T;
+typedef PDAMON_PC_PAIR_RAW_V2_T     PDAMON_PC_PAIR_RAW_T;
+typedef PDAMON_RAW_PER_CORE_V2_T    PDAMON_RAW_PER_CORE_T;
+typedef PDAMON_STOP_SOURCE_V2       PDAMON_STOP_SOURCE;
+typedef PDAMON_EVENT_MASK_V2        PDAMON_EVENT_MASK;
+typedef PDAMON_EX_RAW_V2_T          PDAMON_EX_RAW_T;
+typedef PDAMON_NEX_RAW_V2_T         PDAMON_NEX_RAW_T;
+
+#define PDAMON_IA_PIPED_CNT         PDAMON_IA_PIPED_CNT_V2
+#define PDAMON_DA_PIPED_CNT         PDAMON_DA_PIPED_CNT_V2
+
+/**
+ * For exception flow
+ */
+#define PDAMON_EX_PIPED_PC_CNT      (PDAMON_EX_PIPED_PC_CNT_V2)
+#define PDAMON_EX_PC_PAIR_CNT       (PDAMON_EX_PC_PAIR_CNT_V2)
+#define PDAMON_EX_PIPED_DA_CNT      (PDAMON_EX_PIPED_DA_CNT_V2)
+#define PDAMON_EX_DA_PAIR_CNT       (PDAMON_EX_DA_PAIR_CNT_V2)
+
+/**
+ * A structure for backup raw data of RMPU violation case
+ */
+typedef struct {
+    PDAMON_RAW_PER_CORE_T raw[PDAMON_CORE_NUM];
+} PDAMON_RMPU_VIO_BACKUP, *PPDAMON_RMPU_VIO_BACKUP;
+
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to initialize PDAMON driver
+///
+/// \return                 PDAMON_OK if initialization is successful
+/// \return                 PDAMON_FAIL if initialization is failed.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_init(void);
+
+///////////////////////////////////////////////////////////////////////////////
+//// \brief                 This function is to configure PCMON module when leave dormant.
+///
+/// \return                 PDAMON_OK if configuration is successful
+/// \return                 PDAMON_FAIL if configuration is failed.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_configure_dormant_leave(void);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to configure PDAMON of cores.
+///
+/// \param [in] cfg         A configuration structure.
+/// \param [in] core        Core ID.
+/// \return                 PDAMON_OK if configuration is successful;
+///                         Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_set_config(PDAMON_CFG_T *cfg, PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to setup PC match address.
+///
+/// \param [in] index       Match index from 0 to 5.
+/// \param [in] addr        Program counter to match.
+/// \param [in] enabled     Set this match as enabled or not.
+/// \return                 PDAMON_OK if configuration is successful;
+///                         Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_set_pc_match(kal_uint32 index, kal_uint32 addr, kal_bool enabled);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to setup PC match address.
+///
+/// \param [in] index       Match index from 0 to 5.
+/// \param [in] addr        Program counter to match.
+/// \param [in] mask        Mask of Program counter to match.
+/// \param [in] enabled     Set this match as enabled or not.
+/// \return                 PDAMON_OK if configuration is successful;
+///                         Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_set_pc_match_and_mask(kal_uint32 index, kal_uint32 addr, kal_uint32 mask, kal_bool enabled);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to start PDAMON of cores.
+///
+/// \param [in] core        Core definition. One of PDAMON_CORE_SEL.
+/// \return                 PDAMON_OK if starting capture is successful;
+///                         Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_start_capture(PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to stop PDAMON of cores.
+///
+/// \param [in] core        Core definition. One of PDAMON_CORE_SEL.
+/// \return                 PDAMON_OK if stopping capture is successful;
+///                         Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_stop_capture(PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is to stop capturing of PDAMON via GCR control
+/// \param [in] core        The core of PDAMON to be stopped
+///
+/// \return                 PDAMON_RET_OK if stop capturing of PDAMON via GCR is successful
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_gcr_stop_capture(PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to select PDAMON of specific
+///                         core.
+///
+/// \param [in] core        Core definition. One of PDAMON_CORE_SEL.
+/// \return                 PDAMON_OK if core selection is successful;
+///                         Not PDAMON_OK if failure.
+/// \note                   V2 : Not support.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_core_select(PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to check if PDAMON is stopped.
+///
+/// \return                 KAL_TRUE if PDAMON is stopped. KAL_FALSE otherwise.
+/// \note                   V1 : Must called after drv_pdamon_core_select
+///////////////////////////////////////////////////////////////////////////////
+kal_bool drv_pdamon_is_stopped(PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to check if PDAMON is stopped
+///                         by specific sources.
+///
+/// \return                 KAL_TRUE if PDAMON is stopped. KAL_FALSE otherwise.
+///////////////////////////////////////////////////////////////////////////////
+kal_bool drv_pdamon_is_stopped_by_sources(PDAMON_CORE_SEL core, PDAMON_STOP_SOURCE source);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to get PC record count of
+///                         specific core.
+///
+/// \return                 PC record count.
+/// \note                   V1 : Must called after drv_pdamon_core_select
+///////////////////////////////////////////////////////////////////////////////
+kal_uint32 drv_pdamon_get_pc_count(PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to get PC record count of
+///                         a specific TC of a core.
+///
+/// \return                 PC record count.
+/// \note                   V2 support only.
+///////////////////////////////////////////////////////////////////////////////
+kal_uint32 drv_pdamon_get_pc_count_by_tc(PDAMON_CORE_SEL core, PDAMON_TC_SEL tc);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to get DA record count of
+///                         specific core.
+///
+/// \return                 DA record count.
+/// \note                   V1 : Must called after drv_pdamon_core_select
+///////////////////////////////////////////////////////////////////////////////
+kal_uint32 drv_pdamon_get_da_count(PDAMON_CORE_SEL core);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to get DA record count of
+///                         a specific TC of a core.
+///
+/// \return                 DA record count.
+/// \note                   V2 support only.
+///////////////////////////////////////////////////////////////////////////////
+kal_uint32 drv_pdamon_get_da_count_by_tc(PDAMON_CORE_SEL core, PDAMON_TC_SEL tc);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to get PDAMON status value
+///
+/// \param [in/out] status  Buffer to store status value
+/// \return                 PDAMON_OK if status value is returned from PDAMON.
+///                         Not PDAMON_OK if failure.
+/// \note                   V1 : Must called after drv_pdamon_core_select
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_get_status(PDAMON_CORE_SEL core, kal_uint32 *status);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to get PDAMON status value
+///
+/// \param [in/out] status  Pointer to a buffer to store PC/DA record.
+/// \return                 PDAMON_OK if record is available from PDAMON.
+///                         Not PDAMON_OK if failure.
+/// \note                   V1 : Must called after drv_pdamon_core_select
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_get_raw(PDAMON_CORE_SEL core, PDAMON_RAW_PER_CORE_T *raw);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to get PC/DA record of specific
+///                         core in excpetion flow
+///
+/// \param [in] core        Core definition. One of PDAMON_CORE_SEL.
+/// \param [in] raw         Pointer to a buffer to store PC/DA record.
+/// \return                 PDAMON_OK if record is available.
+///                         Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_ex_get_raw(PDAMON_CORE_SEL core, PDAMON_EX_RAW_T *raw);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to get PC/DA record of specific
+///                         core in nested excpetion flow
+///
+/// \param [in] core        Core definition. One of PDAMON_CORE_SEL.
+/// \param [in] raw         Pointer to a buffer to store PC/DA record.
+/// \return                 PDAMON_OK if record is available.
+///                         Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_nex_get_raw(PDAMON_CORE_SEL core, PDAMON_NEX_RAW_T *raw);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                  This function is used to get PC/DA record of all
+///                         cores in excpetion flow
+///
+/// \return                 PDAMON_OK if all record are available.
+///                         Not PDAMON_OK if failure.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_ex_get_all_raw();
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                      This function is used to mask/un-mask stop sources.
+///
+/// \param [in] source          Stop source enumeration.
+///                             Please refer to PCMON_STOP_SOURCE.
+/// \param [in] mask            KAL_TRUE means mask stop source.
+///                             KAL_FALSE means unmask stop source.
+///
+/// \return                     PCMON_OK if mask/un-mask operation is done.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_mask_stop_sources(PDAMON_CORE_SEL core, PDAMON_STOP_SOURCE sources, kal_bool mask);
+
+///////////////////////////////////////////////////////////////////////////////
+/// \brief                      This function is used to backup PC/DA record and
+///                             re-start PCMon.
+///
+/// \param [in] mcu             KAL_TRUE means backup PC/DA record by MCU.
+///                             KAL_FALSE means backup PC/DA record by GDMA.
+/// \param [in/out] data_ptr    A pointer of buffer to store PC/DA record.
+/// \param [in] size            Size of data_ptr in byes. This value must be 256.
+/// \param [in] mask            KAL_TRUE means mask RMPU stop source after backup.
+///                             KAL_FALSE means unmask RMPU stop source after backup.
+///
+/// \return                     PCMON_INVALID_ARGUMENT means \size if not the
+///                             proper value.
+/// \return                     PCMON_OK if backup and restart are done.
+/// \return                     PCMON_FAIL if PCMon is not stopped. Backup can not
+///                             be done.
+///////////////////////////////////////////////////////////////////////////////
+PDAMON_RET drv_pdamon_backup_and_restart(kal_bool mcu, PPDAMON_RMPU_VIO_BACKUP data_ptr, kal_bool mask);
+
+#endif // end of __DRV_PCMON_H__
diff --git a/mcu/interface/driver/devdrv/pcmon/drv_pcmon_common.h b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_common.h
new file mode 100644
index 0000000..7199827
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_common.h
@@ -0,0 +1,212 @@
+#ifndef __DRV_PCMON_COMMON_H__
+#define __DRV_PCMON_COMMON_H__
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name PDAMON Common Preprocessor Directives
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+/**
+ * Number of PC pairs supported by PDAMON
+ */
+#if defined(__MD97__)
+    #define PDAMON_TC_NUM_PER_CORE      (6)
+#else
+    #define PDAMON_TC_NUM_PER_CORE      (4)
+#endif
+
+/**
+ * Number of PC pairs supported by PDAMON
+ */
+#if defined(__MD93__) || defined(__MD95_IS_2CORES__) || defined(__MD97_IS_2CORES__)
+    #define PDAMON_CORE_NUM             (2)
+#elif defined(__MD95__)
+    #define PDAMON_CORE_NUM             (3)
+#elif defined(__MD97__)
+    #define PDAMON_CORE_NUM             (4)
+#else
+    #error "ERROR in drv_pcmon_common.h #define PDAMON_CORE_NUM"
+#endif
+/**
+ * Number of PC pairs supported by PDAMON
+ */
+#if defined(__MD97__)
+    #define PDAMON_IA_RAW_CAPACITY      (56)
+#else
+    #define PDAMON_IA_RAW_CAPACITY      (32)
+#endif
+
+/**
+ * Number of DA pairs supported by PDAMON
+ */
+#if defined(__MD97__)
+    #define PDAMON_DA_RAW_CAPACITY      (56)
+#else
+    #define PDAMON_DA_RAW_CAPACITY      (32)
+#endif
+
+/**
+ * Number of PC pairs in pipeline
+ */
+#define PDAMON_IA_PIPED_CNT_V2      (3)
+
+/**
+ * Number of DA pairs in pipeline
+ */
+#define PDAMON_DA_PIPED_CNT_V2      (1)
+
+/**
+ * Max. size of PDAMON_EX_RAW_T
+ */
+#if defined(__MD97__)
+    #define PDAMON_EX_RAW_SIZE          (2048)
+#else
+    #define PDAMON_EX_RAW_SIZE          (1024)
+#endif
+
+/**
+ * Max. size of PDAMON_NEX_RAW_T
+ */
+#define PDAMON_NEX_RAW_SIZE         (512)
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name Type Definition
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+#if defined(__MD93__)
+#define PDAMON_DORMANT_TRACE_MAGIC      2454
+typedef enum {
+    PDAMON_DORMANT_ALREADY_STOPPED = 1,
+    PDAMON_DORMANT_NON_STOPPED,
+    PDAMON_DORMANT_STOPPED_BY_OTHERS,
+    PDAMON_DORMANT_STOPPED_BY_MAIN,             // Main means the SPRAM_DEC_ERR... such default want to mask.
+} PDAMON_DORMANT_STEP;
+#endif /* defined(__MD93__) */
+
+/**
+ * Core ID enumeration
+ */
+typedef enum {
+    PDAMON_CORE_0 = 0,                      ///< Core-0 PDAMON
+    PDAMON_CORE_1,                          ///< Core-1 PDAMON
+#if defined(__MD95__) && !defined(__MD95_IS_2CORES__)
+    PDAMON_CORE_2,                          ///< Core-2 PDAMON
+#endif
+#if defined(__MD97__) && !defined(__MD97_IS_2CORES__)
+    PDAMON_CORE_2,                          ///< Core-2 PDAMON
+    PDAMON_CORE_3,                          ///< Core-3 PDAMON
+#endif
+    PDAMON_CORE_CNT,
+    PDAMON_CORE_ALL = PDAMON_CORE_CNT,      ///< All core PDAMON
+} PDAMON_CORE_SEL;
+
+/**
+ * TC ID enumeration
+ */
+typedef enum {
+    PDAMON_TC_0 = 0,
+    PDAMON_TC_1,
+    PDAMON_TC_2,
+    PDAMON_TC_3,
+#if defined(__MD97__)
+    PDAMON_TC_4,
+    PDAMON_TC_5,
+#endif
+    PDAMON_TC_CNT,
+} PDAMON_TC_SEL;
+
+/**
+ * Return value of API
+ */
+typedef enum {
+    PDAMON_RET_OK,                          ///< Function call is successful
+    PDAMON_RET_FAIL,                        ///< Function call is failed
+    PDAMON_RET_UNSUPPORTED,                 ///< Function call is not supported
+    PDAMON_RET_INVALID_ARGUMENT,            ///< Invalid arguments of function call
+    PDAMON_RET_ALREADY_STARTED,             ///< PDAMon is started
+    PDAMON_RET_ALREADY_STOPPED,             ///< PDAMon is stopped
+} PDAMON_RET;
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name CODA Structures
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+/**
+ * A structure to describe tag register of DA pair
+ */
+typedef union {
+    struct {
+        kal_uint32 TC                   : 5;
+        kal_uint32 rsv_1                : 26;
+        kal_uint32 IDX                  : 1;
+    } Bits;
+    kal_uint32 Raw;
+} PDAMON_DA_PAIR_TAG, *PPDAMON_DA_PAIR_TAG;
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name API Structure
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+/**
+ * A structure to describe design version
+ */
+typedef struct PDAMON_VERSION_S {
+    kal_uint32 new_design   : 1;            ///< Gen92 new design or not
+    kal_uint32 reserved     : 31;           ///< Reserved
+} PDAMON_VERSION_T;
+
+/**
+ * A structure to describe raw data of PC pair in pipeline
+ */
+typedef struct PDAMON_PIPED_PC_PAIR_RAW_S {
+    kal_uint32 pc;                          ///< PC
+    kal_uint32 tc;                          ///< TC index
+    kal_uint32 frc;                         ///< FRC
+} PDAMON_PIPED_PC_PAIR_RAW_T;
+
+/**
+ * A structure to describe raw data of PC pair in pipeline
+ */
+typedef struct PDAMON_PIPED_PC_PAIR_RAW_ALIGNED_S {
+    kal_uint32 pc;                          ///< PC
+    kal_uint32 tc;                          ///< TC index
+    kal_uint32 frc;                         ///< FRC
+    kal_uint32 reserved;
+} PDAMON_PIPED_PC_PAIR_RAW_ALIGNED_T;
+
+/**
+ * A structure to describe raw data of DA pair
+ */
+typedef struct PDAMON_DA_PAIR_RAW_S {
+    kal_uint32          da;                 ///< Data address
+    kal_uint32          pc;                 ///< PC
+    kal_uint32          frc;                ///< FRC
+    PDAMON_DA_PAIR_TAG  tag;                ///< Tag value
+} PDAMON_DA_PAIR_RAW_T;
+
+/**
+ * A structure to describe raw data of DA pair in pipeline
+ */
+typedef struct PDAMON_PIPED_DA_PAIR_RAW_S {
+    kal_uint32 pc;                          ///< PC
+    kal_uint32 da;                          ///< Data address
+    kal_uint32 tc;                          ///< TC index
+    kal_uint32 frc;                         ///< FRC
+} PDAMON_PIPED_DA_PAIR_RAW_T;
+
+///@}
+
+#endif // __DRV_PCMON_COMMON_H__
diff --git a/mcu/interface/driver/devdrv/pcmon/drv_pcmon_ex.h b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_ex.h
new file mode 100644
index 0000000..df9e21f
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_ex.h
@@ -0,0 +1,43 @@
+#ifndef __DRV_PCMON_EX_H__
+#define __DRV_PCMON_EX_H__
+
+.macro PDAMON_STOP_ASM
+.set noreorder
+#if defined(__MD93__)
+    lui   $k1, 0xA021
+    addiu $k1, $k1, 0x800
+    lw    $k0, 0($k1)
+    ins   $k0, $zero, 0, 8
+    ori   $k0, $k0, 0x22
+    sw    $k0, 0($k1)
+    lw    $k0, 0($k1)
+#elif defined(__MD95__)
+    lui   $k1, 0xA021
+    addiu $k1, $k1, 0x1000
+    lw    $k0, 0($k1)
+    ins   $k0, $zero, 0, 12
+    ori   $k0, $k0, 0x222
+    sw    $k0, 0($k1)
+    lw    $k0, 0($k1)
+#elif defined(__MD97__) && !defined(MT6297_IA)
+    lui   $k1, 0xA029
+    addiu $k1, $k1, 0x1C00
+    lw    $k0, 0($k1)
+    ins   $k0, $zero, 0, 16
+    li    $k0, 0x2222
+    sw    $k0, 0($k1)
+    lw    $k0, 0($k1)
+#elif defined(__MD97__) && defined(MT6297_IA)
+    lui   $k1, 0xA021
+    addiu $k1, $k1, 0x2000
+    lw    $k0, 0($k1)
+    ins   $k0, $zero, 0, 16
+    li    $k0, 0x2222
+    sw    $k0, 0($k1)
+    lw    $k0, 0($k1)
+#else
+    #error "ERROR in drv_pcmon_ex.h, w/o define macro PDAMON_STOP_ASM"
+#endif
+.endm PDAMON_STOP_ASM
+
+#endif // __DRV_PCMON_EX_H__
diff --git a/mcu/interface/driver/devdrv/pcmon/drv_pcmon_init.h b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_init.h
new file mode 100644
index 0000000..883b81e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_init.h
@@ -0,0 +1,124 @@
+#ifndef __DRV_PCMON_INIT_H__
+#define __DRV_PCMON_INIT_H__
+
+#if defined(__MD97__)
+#define PC_NULL_ADDR      0x6
+#define PC_NULL_MASK      0xFFFFF804
+#else
+#define PC_NULL_ADDR      0x0
+#define PC_NULL_MASK      0xFFFFF800
+#endif
+
+#define PC_FUNC_MASK      0xFFFFFFF0
+#define PC_MATCH_DISABLE  0x1
+
+#if defined(__MD93__)
+#define PC_MATCH_3_ADDR   0xA021088C
+#elif defined(__MD95__)
+#define PC_MATCH_3_ADDR   0xA021108C
+#elif defined(__MD97__) && defined(MT6297_IA)
+#define PC_MATCH_3_ADDR   0xA02120CC
+#elif defined(__MD97__) && !defined(MT6297_IA)
+#define PC_MATCH_0_ADDR   0xA0291CC0
+#define PC_MATCH_0_MASK   0xA0291CD8
+#define PC_MATCH_1_ADDR   0xA0291CC4
+#define PC_MATCH_1_MASK   0xA0291CDC
+#define PC_MATCH_2_ADDR   0xA0291CC8
+#define PC_MATCH_2_MASK   0xA0291CE0
+#define PC_MATCH_3_ADDR   0xA0291CCC
+#define PC_MATCH_3_MASK   0xA0291CE4
+#else
+    #error "ERROR in drv_pcmon_init.h #define PC_MATCH_3_ADDR"
+#endif
+
+.extern general_ex_vector
+.extern NMI_handler
+.extern INT_TEMP_general_ex_vector
+
+.macro PDAMON_CONFIG
+.set push 
+.set nomips16
+#if !defined(__MD97__)
+PDAMON_PreSet_NULL_Protection:
+    la    t1, PC_MATCH_3_ADDR
+    li    t0, PC_NULL_ADDR
+    sw    t0, 0(t1)
+    lw    t0, 0(t1)
+#if defined(__MD93__)
+PDAMON_PreSet_Event_Mask:
+    lui   t1, 0xA021
+    addiu t1, t1, 0x800
+    lw    t0, 0(t1)
+    ins   t0, zero, 0, 8
+    ori   t0, t0, 0x22
+    sw    t0, 0(t1)
+    lw    t0, 0(t1)
+    lw    t0, 0x10(t1)
+    ori   t0, t0, 0x200
+    sw    t0, 0x10(t1)
+    lw    t0, 0x10(t1)
+    lw    t0, 0(t1)
+    ins   t0, zero, 0, 8
+    ori   t0, t0, 0x11
+    sw    t0, 0(t1)
+    lw    t0, 0(t1)
+#endif
+#else //defined(__MD97__)
+PDAMON_PreSet_NULL_Protection:
+    // Set PC MATCH3
+    li    $a1, PC_MATCH_3_ADDR
+    li    $a0, PC_MATCH_DISABLE
+    sw    $a0, 0($a1)
+    lw    $a0, 0($a1)
+    li    $a1, PC_MATCH_3_MASK
+    li    $a0, PC_NULL_MASK
+    sw    $a0, 0($a1)
+    lw    $a0, 0($a1)
+    li    $a1, PC_MATCH_3_ADDR
+    li    $a0, PC_NULL_ADDR
+    sw    $a0, 0($a1)
+    lw    $a0, 0($a1)
+    // Set PC MATCH0
+    li    $a1, PC_MATCH_0_ADDR
+    li    $a0, PC_MATCH_DISABLE
+    sw    $a0, 0($a1)
+    lw    $a0, 0($a1)
+    li    $a1, PC_MATCH_0_MASK
+    li    $a0, PC_FUNC_MASK
+    sw    $a0, 0($a1)
+    lw    $a0, 0($a1)
+    li    $a1, PC_MATCH_0_ADDR
+    li    $a0, general_ex_vector
+    sw    $a0, 0($a1)
+    lw    $a0, 0($a1)
+    // Set PC MATCH1
+    li    $a1, PC_MATCH_1_ADDR
+    li    $a0, PC_MATCH_DISABLE
+    sw    $a0, 0($a1)
+    lw    $a0, 0($a1)
+    li    $a1, PC_MATCH_1_MASK
+    li    $a0, PC_FUNC_MASK
+    sw    $a0, 0($a1)
+    lw    $a0, 0($a1)
+    li    $a1, PC_MATCH_1_ADDR
+    li    $a0, NMI_handler
+    sw    $a0, 0($a1)
+    lw    $a0, 0($a1)
+    // Set PC MATCH2
+    li    $a1, PC_MATCH_2_ADDR
+    li    $a0, PC_MATCH_DISABLE
+    sw    $a0, 0($a1)
+    lw    $a0, 0($a1)
+    li    $a1, PC_MATCH_2_MASK
+    li    $a0, PC_FUNC_MASK
+    sw    $a0, 0($a1)
+    lw    $a0, 0($a1)
+    li    $a1, PC_MATCH_2_ADDR
+    li    $a0, INT_TEMP_general_ex_vector
+    sw    $a0, 0($a1)
+    lw    $a0, 0($a1)
+#endif //!defined(__MD97__)
+.set pop
+.endm PDAMON_CONFIG
+
+#endif // __DRV_PCMON_INIT_H__
diff --git a/mcu/interface/driver/devdrv/pcmon/drv_pcmon_v2.h b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_v2.h
new file mode 100644
index 0000000..038c3eb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pcmon/drv_pcmon_v2.h
@@ -0,0 +1,542 @@
+#ifndef __DRV_PCMON_V2_H__
+#define __DRV_PCMON_V2_H__
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name V2 Preprocessor Directives
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+/**
+ * Number of PC match registers
+ */
+#define PDAMON_PC_MATCH_CNT         (6)
+
+/**
+ * Number of each TC's SPRAM size in EX
+ */
+#define PDAMON_EX_TC0_IA_MARGIN     (0)
+#define PDAMON_EX_TC1_IA_MARGIN     (1)
+#define PDAMON_EX_TC2_IA_MARGIN     (1)
+#define PDAMON_EX_TC3_IA_MARGIN     (1)
+#if defined(__MD97__) 
+    #define PDAMON_EX_TC4_IA_MARGIN (1)
+    #define PDAMON_EX_TC5_IA_MARGIN (1)
+    #define PDAMON_EX_TC_TOTAL_IA_PAIR  (PDAMON_IA_RAW_CAPACITY - PDAMON_EX_TC0_IA_MARGIN - PDAMON_EX_TC1_IA_MARGIN - PDAMON_EX_TC2_IA_MARGIN - PDAMON_EX_TC3_IA_MARGIN - PDAMON_EX_TC4_IA_MARGIN - PDAMON_EX_TC5_IA_MARGIN)
+#else
+    #define PDAMON_EX_TC_TOTAL_IA_PAIR  (PDAMON_IA_RAW_CAPACITY - PDAMON_EX_TC0_IA_MARGIN - PDAMON_EX_TC1_IA_MARGIN - PDAMON_EX_TC2_IA_MARGIN - PDAMON_EX_TC3_IA_MARGIN)
+#endif
+#define PDAMON_EX_TC0_DA_MARGIN     (1)
+#define PDAMON_EX_TC1_DA_MARGIN     (1)
+#define PDAMON_EX_TC2_DA_MARGIN     (1)
+#define PDAMON_EX_TC3_DA_MARGIN     (1)
+#if defined(__MD97__) 
+    #define PDAMON_EX_TC4_DA_MARGIN (1)
+    #define PDAMON_EX_TC5_DA_MARGIN (1)
+    #define PDAMON_EX_TC_TOTAL_DA_PAIR  (PDAMON_DA_RAW_CAPACITY - PDAMON_EX_TC0_DA_MARGIN - PDAMON_EX_TC1_DA_MARGIN - PDAMON_EX_TC2_DA_MARGIN - PDAMON_EX_TC3_DA_MARGIN - PDAMON_EX_TC4_DA_MARGIN - PDAMON_EX_TC5_DA_MARGIN)
+#else
+#define PDAMON_EX_TC_TOTAL_DA_PAIR  (PDAMON_DA_RAW_CAPACITY - PDAMON_EX_TC0_DA_MARGIN - PDAMON_EX_TC1_DA_MARGIN - PDAMON_EX_TC2_DA_MARGIN - PDAMON_EX_TC3_DA_MARGIN)
+#endif
+
+/**
+ * Number of each TC's SPRAM size in NEX
+ */
+#define PDAMON_NEX_TC0_IA_MARGIN    (1)
+#define PDAMON_NEX_TC1_IA_MARGIN    (1)
+#define PDAMON_NEX_TC2_IA_MARGIN    (1)
+#define PDAMON_NEX_TC3_IA_MARGIN    (2)
+#if defined(__MD97__) 
+    #define PDAMON_NEX_TC4_IA_MARGIN    (1)
+    #define PDAMON_NEX_TC5_IA_MARGIN    (2)
+    #define PDAMON_NEX_TC_TOTAL_IA_PAIR (PDAMON_IA_RAW_CAPACITY - PDAMON_NEX_TC0_IA_MARGIN - PDAMON_NEX_TC1_IA_MARGIN - PDAMON_NEX_TC2_IA_MARGIN - PDAMON_NEX_TC3_IA_MARGIN - PDAMON_NEX_TC4_IA_MARGIN - PDAMON_NEX_TC5_IA_MARGIN)
+#else
+    #define PDAMON_NEX_TC_TOTAL_IA_PAIR (PDAMON_IA_RAW_CAPACITY - PDAMON_NEX_TC0_IA_MARGIN - PDAMON_NEX_TC1_IA_MARGIN - PDAMON_NEX_TC2_IA_MARGIN - PDAMON_NEX_TC3_IA_MARGIN)
+#endif
+
+/**
+ * For exception flow
+ */
+#define PDAMON_EX_PIPED_PC_CNT_V2   (PDAMON_TC_NUM_PER_CORE * PDAMON_IA_PIPED_CNT_V2)
+#define PDAMON_EX_PC_PAIR_CNT_V2    (PDAMON_EX_TC_TOTAL_IA_PAIR)
+#define PDAMON_EX_PIPED_DA_CNT_V2   (PDAMON_DA_PIPED_CNT_V2)
+#define PDAMON_EX_DA_PAIR_CNT_V2    (PDAMON_EX_TC_TOTAL_DA_PAIR)
+#define PDAMON_EX_PIPED_FRC_CNT_V2  (PDAMON_TC_NUM_PER_CORE)
+#define PDAMON_NEX_PC_PAIR_CNT_V2   (PDAMON_NEX_TC_TOTAL_IA_PAIR)
+#define PDAMON_NEX_PIPED_FRC_CNT_V2 (PDAMON_EX_PIPED_FRC_CNT_V2 - 1)                        // -1 for insufficient room
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name Type Definition
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+/**
+ * Stop source of PCMon
+ */
+typedef enum {
+    PDAMON_SRC_NONE             = 0,
+    PDAMON_SRC_MDMCU_BUSMON     = 0x1,
+    PDAMON_SRC_MDINFRA_BUSMON   = 0x2,
+    PDAMON_SRC_MD_BUSERR        = 0x4,
+    PDAMON_SRC_BUS_MPU          = 0x8,
+    PDAMON_SRC_RGU              = 0x10,
+    PDAMON_SRC_RMPU             = 0x20,
+    PDAMON_SRC_CTI              = 0x40,
+    PDAMON_SRC_CMERR            = 0x80,
+#if defined(__MD93__)
+    PDAMON_SRC_SPRAM_DECERR     = 0x200,
+#endif
+    PDAMON_SRC_MDMCU_DECERR     = 0x400,
+    PDAMON_SRC_GCR              = 0x800,
+    PDAMON_SRC_SW               = 0x1000,
+    PDAMON_SRC_PC0_MATCH        = 0x2000,
+    PDAMON_SRC_PC1_MATCH        = 0x4000,
+    PDAMON_SRC_PC2_MATCH        = 0x8000,
+    PDAMON_SRC_PC3_MATCH        = 0x10000,
+    PDAMON_SRC_PC4_MATCH        = 0x20000,
+    PDAMON_SRC_PC5_MATCH        = 0x40000,
+} PDAMON_STOP_SOURCE_V2;
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name CODA Structures
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+#if defined(__MD95__) || defined(__MD97__) 
+/**
+ * A structure to describe first stop event register
+ */
+typedef union {
+    struct {
+        kal_uint32 MDMCU_BUSMON         : 1;
+        kal_uint32 MDINFRA_BUSMON       : 1;
+        kal_uint32 MD_BUS_ERR           : 1;
+        kal_uint32 BUSMPU               : 1;
+        kal_uint32 RGU                  : 1;
+        kal_uint32 RMPU                 : 1;
+        kal_uint32 CTI                  : 1;
+        kal_uint32 CM_ERR               : 1;
+        kal_uint32 rsv_1                : 2;
+        kal_uint32 MDMCU_DECERR         : 1;
+        kal_uint32 GCR                  : 1;
+        kal_uint32 SW                   : 1;
+        kal_uint32 PC_MATCH_0           : 1;
+        kal_uint32 PC_MATCH_1           : 1;
+        kal_uint32 PC_MATCH_2           : 1;
+        kal_uint32 PC_MATCH_3           : 1;
+        kal_uint32 PC_MATCH_4           : 1;
+        kal_uint32 PC_MATCH_5           : 1;
+        kal_uint32 rsv_2                : 13;
+    } Bits;
+    kal_uint32 Raw;
+} PDAMON_FIRST_STOP_EVENT, *PPDAMON_FIRST_STOP_EVENT;
+
+/**
+ * A structure to describe event mask register
+ */
+typedef union {
+    struct {
+        kal_uint32 MDMCU_BUSMON         : 1;
+        kal_uint32 MDINFRA_BUSMON       : 1;
+        kal_uint32 MD_BUS_ERR           : 1;
+        kal_uint32 BUSMPU               : 1;
+        kal_uint32 RGU                  : 1;
+        kal_uint32 RMPU                 : 1;
+        kal_uint32 CTI                  : 1;
+        kal_uint32 CM_ERR               : 1;
+        kal_uint32 rsv_1                : 2;
+        kal_uint32 MDMCU_DECERR         : 1;
+        kal_uint32 GCR                  : 1;
+        kal_uint32 SW                   : 1;
+        kal_uint32 PC_MATCH_0           : 1;
+        kal_uint32 PC_MATCH_1           : 1;
+        kal_uint32 PC_MATCH_2           : 1;
+        kal_uint32 PC_MATCH_3           : 1;
+        kal_uint32 PC_MATCH_4           : 1;
+        kal_uint32 PC_MATCH_5           : 1;
+        kal_uint32 rsv_2                : 13;
+    } Bits;
+    kal_uint32 Raw;
+} PDAMON_EVENT_MASK_V2, *PPDAMON_EVENT_MASK_V2;
+
+/**
+ * A structure to describe record status register
+ */
+typedef union {
+    struct {
+        kal_uint32 MDMCU_BUSMON         : 1;
+        kal_uint32 MDINFRA_BUSMON       : 1;
+        kal_uint32 MD_BUS_ERR           : 1;
+        kal_uint32 BUSMPU               : 1;
+        kal_uint32 RGU                  : 1;
+        kal_uint32 RMPU                 : 1;
+        kal_uint32 CTI                  : 1;
+        kal_uint32 CM_ERR               : 1;
+        kal_uint32 rsv_1                : 2;
+        kal_uint32 MDMCU_DECERR         : 1;
+        kal_uint32 GCR                  : 1;
+        kal_uint32 SW                   : 1;
+        kal_uint32 PC_MATCH_0           : 1;
+        kal_uint32 PC_MATCH_1           : 1;
+        kal_uint32 PC_MATCH_2           : 1;
+        kal_uint32 PC_MATCH_3           : 1;
+        kal_uint32 PC_MATCH_4           : 1;
+        kal_uint32 PC_MATCH_5           : 1;
+        kal_uint32 rsv_2                : 12;
+        kal_uint32 STOPPED              : 1;
+    } Bits;
+    kal_uint32 Raw;
+} PDAMON_RECORD_STS_V2, *PPDAMON_RECORD_STS_V2;
+
+#elif defined(__MD93__)
+/**
+ * A structure to describe event mask register
+ */
+typedef union {
+    struct {
+        kal_uint32 MDMCU_BUSMON         : 1;
+        kal_uint32 MDINFRA_BUSMON       : 1;
+        kal_uint32 MD_BUS_ERR           : 1;
+        kal_uint32 BUSMPU               : 1;
+        kal_uint32 RGU                  : 1;
+        kal_uint32 RMPU                 : 1;
+        kal_uint32 CTI                  : 1;
+        kal_uint32 CM_ERR               : 1;
+        kal_uint32 rsv_1                : 1;
+        kal_uint32 SPRAM_DECERR         : 1;
+        kal_uint32 MDMCU_DECERR         : 1;
+        kal_uint32 GCR                  : 1;
+        kal_uint32 SW                   : 1;
+        kal_uint32 PC_MATCH_0           : 1;
+        kal_uint32 PC_MATCH_1           : 1;
+        kal_uint32 PC_MATCH_2           : 1;
+        kal_uint32 PC_MATCH_3           : 1;
+        kal_uint32 PC_MATCH_4           : 1;
+        kal_uint32 PC_MATCH_5           : 1;
+        kal_uint32 rsv_2                : 13;
+    } Bits;
+    kal_uint32 Raw;
+} PDAMON_EVENT_MASK_V2, *PPDAMON_EVENT_MASK_V2;
+
+/**
+ * A structure to describe record status register
+ */
+typedef union {
+    struct {
+        kal_uint32 MDMCU_BUSMON         : 1;
+        kal_uint32 MDINFRA_BUSMON       : 1;
+        kal_uint32 MD_BUS_ERR           : 1;
+        kal_uint32 BUSMPU               : 1;
+        kal_uint32 RGU                  : 1;
+        kal_uint32 RMPU                 : 1;
+        kal_uint32 CTI                  : 1;
+        kal_uint32 CM_ERR               : 1;
+        kal_uint32 rsv_1                : 1;
+        kal_uint32 SPRAM_DECERR         : 1;
+        kal_uint32 MDMCU_DECERR         : 1;
+        kal_uint32 GCR                  : 1;
+        kal_uint32 SW                   : 1;
+        kal_uint32 PC_MATCH_0           : 1;
+        kal_uint32 PC_MATCH_1           : 1;
+        kal_uint32 PC_MATCH_2           : 1;
+        kal_uint32 PC_MATCH_3           : 1;
+        kal_uint32 PC_MATCH_4           : 1;
+        kal_uint32 PC_MATCH_5           : 1;
+        kal_uint32 rsv_2                : 12;
+        kal_uint32 STOPPED              : 1;
+    } Bits;
+    kal_uint32 Raw;
+} PDAMON_RECORD_STS_V2, *PPDAMON_RECORD_STS_V2;
+#endif 
+
+/**
+ * A structure to describe SRAM wrap status
+ */
+typedef union {
+    struct {
+        kal_uint32 TC0_SRAM_NON_WRAP_CNT: 5;
+        kal_uint32 rsv_1                : 2;
+        kal_uint32 TC0_SRAM_WRAP        : 1;
+        kal_uint32 TC1_SRAM_NON_WRAP_CNT: 5;
+        kal_uint32 rsv_2                : 2;
+        kal_uint32 TC1_SRAM_WRAP        : 1;
+        kal_uint32 TC2_SRAM_NON_WRAP_CNT: 5;
+        kal_uint32 rsv_3                : 2;
+        kal_uint32 TC2_SRAM_WRAP        : 1;
+        kal_uint32 TC3_SRAM_NON_WRAP_CNT: 5;
+        kal_uint32 rsv_4                : 2;
+        kal_uint32 TC3_SRAM_WRAP        : 1;
+    } Bits;
+    kal_uint32 Raw;
+} PDAMON_SRAM_WRAP_STS, *PPDAMON_SRAM_WRAP_STS;
+
+typedef union {
+    struct {
+        kal_uint32 TC4_SRAM_NON_WRAP_CNT: 5;
+        kal_uint32 rsv_1                : 2;
+        kal_uint32 TC4_SRAM_WRAP        : 1;
+        kal_uint32 TC5_SRAM_NON_WRAP_CNT: 5;
+        kal_uint32 rsv_2                : 2;
+        kal_uint32 TC5_SRAM_WRAP        : 1;
+        kal_uint32 TC6_SRAM_NON_WRAP_CNT: 5;
+        kal_uint32 rsv_3                : 2;
+        kal_uint32 TC6_SRAM_WRAP        : 1;
+    } Bits;
+    kal_uint32 Raw;
+} PDAMON_SRAM_WRAP_STS_EXT, *PPDAMON_SRAM_WRAP_STS_EXT;
+
+
+/**
+ * A structure to describe "tag" fields of PC raw data
+ */
+typedef union {
+    struct {
+#if defined(__MD97__) && !defined(APOLLO)
+        kal_uint32 TC               : 4;  //0~3
+        kal_uint32 rsv_1            : 4;  //4~7
+        kal_uint32 DA_TAG           : 6;  //8~13
+        kal_uint32 rsv_2            : 2;  //14~15
+        kal_uint32 SEQ_COUNT        : 11; //16~26
+        kal_uint32 rsv_3            : 2;  //27~28
+        kal_uint32 DST_DUAL_ISSUE   : 1;  //29
+        kal_uint32 SRC_DUAL_ISSUE   : 1;  //30
+        kal_uint32 IDX              : 1;  //31
+#else
+        kal_uint32 TC       : 5;
+        kal_uint32 rsv_1    : 11;
+        kal_uint32 DA_TAG   : 5;
+        kal_uint32 rsv_2    : 10;
+        kal_uint32 IDX      : 1;
+#endif
+    } Bits;
+    kal_uint32 Raw;
+} PDAMON_PC_PAIR_TAG_V2, *PPDAMON_PC_PAIR_TAG_V2;
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name API Structure
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+/**
+ * A structure to describe configuration
+ */
+typedef struct PDAMON_CFG_V2_S {
+    PDAMON_STOP_SOURCE_V2       stop_src_mask;      ///< Stop source mask
+} PDAMON_CFG_V2_T;
+
+/**
+ * A structure to describe raw data of PC pair
+ */
+typedef struct PDAMON_PC_PAIR_RAW_V2_S {
+    kal_uint32                  src;                ///< Source PC
+    kal_uint32                  dst;                ///< Destination PC
+    kal_uint32                  frc;                ///< FRC
+    PDAMON_PC_PAIR_TAG_V2       tag;                ///< Tag value
+} PDAMON_PC_PAIR_RAW_V2_T;
+
+/**
+ * A structure to describe PC and DA raw data for exception
+ * Capacity is 1024 or 2048 bytes
+ */
+#if defined(__MD97__) 
+#define PDAMON_EX_USED_V2       (sizeof(PDAMON_VERSION_T) + \
+                                sizeof(PDAMON_SRAM_WRAP_STS) + \
+                                sizeof(PDAMON_SRAM_WRAP_STS_EXT) + \
+                                sizeof(PDAMON_SRAM_WRAP_STS) + \
+                                sizeof(PDAMON_SRAM_WRAP_STS_EXT) + \
+                                sizeof(kal_uint32)*(PDAMON_TC_NUM_PER_CORE * PDAMON_IA_PIPED_CNT_V2) + \
+                                sizeof(kal_uint32)*PDAMON_EX_PIPED_FRC_CNT_V2 + \
+                                sizeof(PDAMON_PC_PAIR_RAW_V2_T)*PDAMON_EX_PC_PAIR_CNT_V2 + \
+                                sizeof(kal_uint32) + \
+                                sizeof(PDAMON_PIPED_DA_PAIR_RAW_T)*PDAMON_EX_PIPED_DA_CNT_V2 + \
+                                sizeof(PDAMON_DA_PAIR_RAW_T)*PDAMON_EX_DA_PAIR_CNT_V2 + \
+                                sizeof(kal_uint32) + \
+                                sizeof(PDAMON_RECORD_STS_V2) + \
+                                sizeof(PDAMON_FIRST_STOP_EVENT) + \
+                                sizeof(PDAMON_FIRST_STOP_EVENT) + \
+                                sizeof(kal_uint32))
+#elif defined(__MD95__)
+#define PDAMON_EX_USED_V2       (sizeof(PDAMON_VERSION_T) + \
+                                sizeof(PDAMON_SRAM_WRAP_STS) + \
+                                sizeof(PDAMON_SRAM_WRAP_STS) + \
+                                sizeof(kal_uint32)*(PDAMON_TC_NUM_PER_CORE * PDAMON_IA_PIPED_CNT_V2) + \
+                                sizeof(kal_uint32)*PDAMON_EX_PIPED_FRC_CNT_V2 + \
+                                sizeof(PDAMON_PC_PAIR_RAW_V2_T)*PDAMON_EX_PC_PAIR_CNT_V2 + \
+                                sizeof(PDAMON_PIPED_DA_PAIR_RAW_T)*PDAMON_EX_PIPED_DA_CNT_V2 + \
+                                sizeof(PDAMON_DA_PAIR_RAW_T)*PDAMON_EX_DA_PAIR_CNT_V2 + \
+                                sizeof(kal_uint32) + \
+                                sizeof(PDAMON_RECORD_STS_V2) + \
+                                sizeof(PDAMON_FIRST_STOP_EVENT) + \
+                                sizeof(kal_uint32))
+#elif defined(__MD93__)
+#define PDAMON_EX_USED_V2       (sizeof(PDAMON_VERSION_T) + \
+                                sizeof(PDAMON_SRAM_WRAP_STS) + \
+                                sizeof(PDAMON_SRAM_WRAP_STS) + \
+                                sizeof(kal_uint32)*(PDAMON_TC_NUM_PER_CORE * PDAMON_IA_PIPED_CNT_V2) + \
+                                sizeof(kal_uint32)*PDAMON_EX_PIPED_FRC_CNT_V2 + \
+                                sizeof(PDAMON_PC_PAIR_RAW_V2_T)*PDAMON_EX_PC_PAIR_CNT_V2 + \
+                                sizeof(PDAMON_PIPED_DA_PAIR_RAW_T)*PDAMON_EX_PIPED_DA_CNT_V2 + \
+                                sizeof(PDAMON_DA_PAIR_RAW_T)*PDAMON_EX_DA_PAIR_CNT_V2 + \
+                                sizeof(kal_uint32) + \
+                                sizeof(PDAMON_RECORD_STS_V2) + \
+                                sizeof(kal_uint32))
+#endif
+typedef struct PDAMON_EX_RAW_V2_S {
+    PDAMON_VERSION_T            version;
+    PDAMON_SRAM_WRAP_STS        pc_wrap;
+#if defined(__MD97__) 
+    PDAMON_SRAM_WRAP_STS_EXT    pc_wrap_ext;
+#endif
+    PDAMON_SRAM_WRAP_STS        da_wrap;
+#if defined(__MD97__) 
+    PDAMON_SRAM_WRAP_STS_EXT    da_wrap_ext;
+#endif
+    kal_uint32                  piped_pc[PDAMON_TC_NUM_PER_CORE][PDAMON_IA_PIPED_CNT_V2];
+    kal_uint32                  piped_pc_frc[PDAMON_EX_PIPED_FRC_CNT_V2];
+    PDAMON_PC_PAIR_RAW_V2_T     pc[PDAMON_EX_PC_PAIR_CNT_V2];
+#if (defined(__MD97__) && !defined(MT6297_IA)) 
+    kal_uint32                  piped_pc_dual_issue;
+#endif
+    PDAMON_PIPED_DA_PAIR_RAW_T  piped_da[PDAMON_EX_PIPED_DA_CNT_V2];
+    PDAMON_DA_PAIR_RAW_T        da[PDAMON_EX_DA_PAIR_CNT_V2];
+    kal_uint32                  last_tc_id;
+    PDAMON_RECORD_STS_V2        record_sts;
+#if defined(__MD95__) || defined(__MD97__) 
+    PDAMON_FIRST_STOP_EVENT     first_stop;
+#endif
+#if defined(__MD97__) 
+    PDAMON_FIRST_STOP_EVENT     first_stop_frc;
+#endif
+    kal_uint32                  sw_trig;
+    kal_uint32                  pad[(PDAMON_EX_RAW_SIZE - PDAMON_EX_USED_V2)/sizeof(kal_uint32)];
+} PDAMON_EX_RAW_V2_T;
+
+/**
+ * A structure to describe PC and DA raw data for nested exception
+ * Capacity is 512 bytes
+ */
+#if defined(__MD97__) 
+#define PDAMON_NEX_USED_V2      (sizeof(PDAMON_VERSION_T) + \
+                                sizeof(PDAMON_SRAM_WRAP_STS) + \
+                                sizeof(PDAMON_SRAM_WRAP_STS_EXT) + \
+                                sizeof(kal_uint32)*(PDAMON_TC_NUM_PER_CORE * PDAMON_IA_PIPED_CNT_V2) + \
+                                sizeof(kal_uint32)*PDAMON_NEX_PIPED_FRC_CNT_V2 + \
+                                sizeof(PDAMON_PC_PAIR_RAW_V2_T)*PDAMON_NEX_PC_PAIR_CNT_V2 + \
+                                sizeof(kal_uint32) + \
+                                sizeof(PDAMON_RECORD_STS_V2) + \
+                                sizeof(PDAMON_FIRST_STOP_EVENT) + \
+                                sizeof(PDAMON_FIRST_STOP_EVENT) + \
+                                sizeof(kal_uint32))
+#elif defined(__MD95__)
+#define PDAMON_NEX_USED_V2      (sizeof(PDAMON_VERSION_T) + \
+                                sizeof(PDAMON_SRAM_WRAP_STS) + \
+                                sizeof(kal_uint32)*(PDAMON_TC_NUM_PER_CORE * PDAMON_IA_PIPED_CNT_V2) + \
+                                sizeof(kal_uint32)*PDAMON_NEX_PIPED_FRC_CNT_V2 + \
+                                sizeof(PDAMON_PC_PAIR_RAW_V2_T)*PDAMON_NEX_PC_PAIR_CNT_V2 + \
+                                sizeof(kal_uint32) + \
+                                sizeof(PDAMON_RECORD_STS_V2) + \
+                                sizeof(PDAMON_FIRST_STOP_EVENT) + \
+                                sizeof(kal_uint32))
+#elif defined(__MD93__)
+#define PDAMON_NEX_USED_V2      (sizeof(PDAMON_VERSION_T) + \
+                                sizeof(PDAMON_SRAM_WRAP_STS) + \
+                                sizeof(kal_uint32)*(PDAMON_TC_NUM_PER_CORE * PDAMON_IA_PIPED_CNT_V2) + \
+                                sizeof(kal_uint32)*PDAMON_NEX_PIPED_FRC_CNT_V2 + \
+                                sizeof(PDAMON_PC_PAIR_RAW_V2_T)*PDAMON_NEX_PC_PAIR_CNT_V2 + \
+                                sizeof(kal_uint32) + \
+                                sizeof(PDAMON_RECORD_STS_V2) + \
+                                sizeof(kal_uint32))
+#endif
+typedef struct PDAMON_NEX_RAW_V2_S {
+    PDAMON_VERSION_T            version;
+    PDAMON_SRAM_WRAP_STS        pc_wrap;
+#if defined(__MD97__) 
+    PDAMON_SRAM_WRAP_STS_EXT    pc_wrap_ext;
+#endif
+    kal_uint32                  piped_pc[PDAMON_TC_NUM_PER_CORE][PDAMON_IA_PIPED_CNT_V2];
+    kal_uint32                  piped_pc_frc[PDAMON_NEX_PIPED_FRC_CNT_V2];
+    PDAMON_PC_PAIR_RAW_V2_T     pc[PDAMON_NEX_PC_PAIR_CNT_V2];
+    kal_uint32                  last_tc_id;
+    PDAMON_RECORD_STS_V2        record_sts;
+#if defined(__MD95__) || defined(__MD97__) 
+    PDAMON_FIRST_STOP_EVENT     first_stop;
+#endif
+#if defined(__MD97__) 
+    PDAMON_FIRST_STOP_EVENT     first_stop_frc;
+#endif
+    kal_uint32                  sw_trig;
+//    kal_uint32                  pad[(PDAMON_NEX_RAW_SIZE - PDAMON_NEX_USED_V2)/sizeof(kal_uint32)];
+} PDAMON_NEX_RAW_V2_T;
+
+/**
+ * A structure to describe PC/DA history of a core
+ */
+typedef struct PDAMON_RAW_PER_CORE_V2_S {
+    PDAMON_SRAM_WRAP_STS                pc_wrap;
+#if defined(__MD97__) 
+    PDAMON_SRAM_WRAP_STS_EXT            pc_wrap_ext;
+#endif
+    kal_uint32                          last_tc_id;
+    kal_uint32                          rsv_1[2];
+    PDAMON_PC_PAIR_RAW_V2_T             pc[PDAMON_IA_RAW_CAPACITY];
+    PDAMON_PIPED_PC_PAIR_RAW_ALIGNED_T  piped_pc[PDAMON_TC_NUM_PER_CORE][PDAMON_IA_PIPED_CNT_V2];
+#if (defined(__MD97__) && !defined(MT6297_IA)) 
+    kal_uint32                          piped_pc_dual_issue;
+#endif
+    PDAMON_SRAM_WRAP_STS                da_wrap;
+#if defined(__MD97__)
+    PDAMON_SRAM_WRAP_STS_EXT            da_wrap_ext;
+#endif
+    kal_uint32                          rsv_2[3];
+    PDAMON_DA_PAIR_RAW_T                da[PDAMON_IA_RAW_CAPACITY];
+    PDAMON_PIPED_DA_PAIR_RAW_T          piped_da[PDAMON_DA_PIPED_CNT_V2];
+    PDAMON_RECORD_STS_V2                record_sts;
+#if defined(__MD95__) || defined(__MD97__) 
+    PDAMON_FIRST_STOP_EVENT             first_stop;
+#endif
+#if defined(__MD97__) 
+    PDAMON_FIRST_STOP_EVENT             first_stop_frc;
+#endif
+    kal_uint32                          sw_trig;
+    kal_uint32                          flag;
+    kal_uint32                          rsv_3[1];
+} PDAMON_RAW_PER_CORE_V2_T;
+
+///@}
+
+///////////////////////////////////////////////////////////////////////////////
+/// \name Exception Macros
+///////////////////////////////////////////////////////////////////////////////
+
+///@{
+
+#define EX_PIPED_PC_PC(ptr, index)      ((ptr)->piped_pc[(index)/(PDAMON_IA_PIPED_CNT_V2)][(index)%(PDAMON_IA_PIPED_CNT_V2)])
+#define EX_PIPED_PC_TC(ptr, index)      ((index)/(PDAMON_IA_PIPED_CNT_V2))
+#define EX_PIPED_PC_FRC(ptr, index)     ((ptr)->piped_pc_frc[(index)/(PDAMON_IA_PIPED_CNT_V2)])
+
+#define EX_PC_PAIR_SRC(ptr, index)      ((ptr)->pc[(index)].src)
+#define EX_PC_PAIR_DST(ptr, index)      ((ptr)->pc[(index)].dst)
+#define EX_PC_PAIR_FRC(ptr, index)      ((ptr)->pc[(index)].frc)
+#define EX_PC_PAIR_TAG(ptr, index)      ((ptr)->pc[(index)].tag.Raw)
+
+#define EX_PIPED_DA_PC(ptr, index)      ((ptr)->piped_da[(index)].pc)
+#define EX_PIPED_DA_DA(ptr, index)      ((ptr)->piped_da[(index)].da)
+#define EX_PIPED_DA_TC(ptr, index)      ((ptr)->piped_da[(index)].tc)
+#define EX_PIPED_DA_FRC(ptr, index)     ((ptr)->piped_da[(index)].frc)
+
+#define EX_DA_PAIR_PC(ptr, index)       ((ptr)->da[(index)].pc)
+#define EX_DA_PAIR_DA(ptr, index)       ((ptr)->da[(index)].da)
+#define EX_DA_PAIR_FRC(ptr, index)      ((ptr)->da[(index)].frc)
+#define EX_DA_PAIR_TAG(ptr, index)      ((ptr)->da[(index)].tag.Raw)
+
+///@}
+
+#endif // __DRV_PCMON_V2_H__
diff --git a/mcu/interface/driver/devdrv/pdn/drvpdn.h b/mcu/interface/driver/devdrv/pdn/drvpdn.h
new file mode 100644
index 0000000..2192c27
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/drvpdn.h
@@ -0,0 +1,81 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   drvpdn.h
+ *
+ * Project:
+ * --------
+ *   UMOLY
+ *
+ * Description:
+ * ------------
+ *   PDN Driver (C Include File)
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 04 09 2014 tungchieh.tsai
+ * [MOLY00061872] [UMOLY][TK6291][SYYSTEN SERVICE] TK6291 PDN driver porting (dummy version)
+ *  	
+ * Update header
+ *
+ * 03 31 2013 gh.huang
+ * [MOLY00012450] Replace sys_drv/pdn with devdrv/pdn
+ *
+ ****************************************************************************/
+
+#ifndef __DRVPDN_H__
+#define __DRVPDN_H__
+
+#include "kal_public_defs.h"
+
+#define DRVPDN_INLINE             INLINE
+#define DRVPDN_INLINE_MODIFIER    INLINE_MODIFIER
+
+#include "drvpdn_inline.h"
+
+#undef DRVPDN_INLINE
+#undef DRVPDN_INLINE_MODIFIER
+
+#define PDN_STATUS(dev, s, t)       (s) = (t)PDN_STS((dev))
+
+#endif /* !__DRVPDN_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/drvpdn_inline.h b/mcu/interface/driver/devdrv/pdn/drvpdn_inline.h
new file mode 100644
index 0000000..497795a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/drvpdn_inline.h
@@ -0,0 +1,116 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   drvpdn_inline.h
+ *
+ * Project:
+ * --------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   PDN Driver (C Inline Implementation)
+ *      - PDN_SET(), PDN_CLR() is for Bus Clock Gating/Ungating
+ *      
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 30 2019 devin.yang
+ * [MOLY00426701] [Mercury] [mmWare] [MD97P] Build error fix.
+ * Update PDN driver.
+ *
+ * 03 09 2018 devin.yang
+ * [MOLY00312408] [System Service] [Compile Option] Add compile option for Gen97.
+ * .
+ *
+ * 10 31 2017 devin.yang
+ * [MOLY00286526] [93/95 re-arch][System Service][PDN] Update PDN driver compile option for 93/95 re-arch.
+ * .
+ *
+ * 10 30 2017 devin.yang
+ * [MOLY00286061] [System Service][PDN][Gen93] Update PDN driver for Cervino.
+ * .
+ *
+ * 08 25 2017 devin.yang
+ * [MOLY00273777] [System Service][PDN][Gen93][MT6771][UMOLYA][LR12A.R2.MP] Update PDN driver for Sylvia.
+ * .
+ *
+ * 06 09 2017 devin.yang
+ * [MOLY00256219] [System Service][MT6739][PDN] Update PDN driver for MT6739.
+ * .
+ *
+ * 11 23 2016 devin.yang
+ * [MOLY00204129] [System Service][PDN] Porting PDN drivers for MT6293.
+ * Update MT6293 PDN driver.
+ *
+ * 09 20 2016 devin.yang
+ * [MOLY00204129] [System Service][PDN] Porting PDN drivers for MT6293.
+ * .
+ *
+ * 03 30 2016 alan-tl.lin
+ * [MOLY00171849] [GEN93] Fix build error
+ * [PLL/PDN] Add compile option for GEN93
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __DRVPDN_INLINE_H__
+#define __DRVPDN_INLINE_H__
+
+#if defined(__MD93__)
+    #include "drvpdn_inline_mt6293.h"
+    #include "drvpdn_inline_username.h"
+
+#elif defined(__MD95__)
+    #include "drvpdn_inline_mt6295.h"
+    #include "drvpdn_inline_username.h"
+
+#elif defined(__MD97__) || defined(__MD97P__)
+    #include "drvpdn_inline_mt6297.h"
+    #include "drvpdn_inline_username.h"
+
+#else
+    #error "Unsupported Chip Target in PDN Module"
+#endif
+
+#endif /* !__DRVPDN_INLINE_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6293.h b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6293.h
new file mode 100644
index 0000000..f39dc60
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6293.h
@@ -0,0 +1,932 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   drvpdn_inline_mt6293.h
+ *
+ * Project:
+ * --------
+ *   UMOLY
+ *
+ * Description:
+ * ------------
+ *   PDN Driver (C Inline Implementation) for MT6293
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 03 16 2018 devin.yang
+ * [MOLY00314076] [System Service][Gen97] Fix build error and build warning.
+ * .
+ *
+ * 11 08 2017 devin.yang
+ * [MOLY00287863] [System Service][PDN][Gen95][UMOLYA] Fixed PDN driver.
+ * .
+ *
+ * 08 11 2017 devin.yang
+ * [MOLY00269905] [System Service][PDN][Gen93][UMOLYA][LR12A.R2.MP] Update PDN driver for new module clock control.
+ * .
+ *
+ * 08 10 2017 devin.yang
+ * [MOLY00269905] [System Service][PDN][Gen93][UMOLYA][LR12A.R2.MP] Update PDN driver for new module clock control.
+ * .
+ *
+ * 08 10 2017 devin.yang
+ * [MOLY00269905] [System Service][PDN][Gen93][UMOLYA][LR12A.R2.MP] Update PDN driver for new module clock control.
+ * .
+ *
+ * 02 16 2017 devin.yang
+ * [MOLY00229974] [System Service][PDN] Update PDN drivers for Bianco.
+ * .
+ *
+ * 11 23 2016 devin.yang
+ * [MOLY00204129] [System Service][PDN] Porting PDN drivers for MT6293.
+ * Update MT6293 PDN driver.
+ *
+ * 05 31 2016 alan-tl.lin
+ * [MOLY00174466] [UMOLYA] PLL porting
+ * Disable PDN function for build error
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __DRVPDN_INLINE_ELBRUS_H__
+#define __DRVPDN_INLINE_ELBRUS_H__
+
+/*******************************************************************************
+ * Locally Used Options
+ *******************************************************************************/
+#define EXTRA_EXPORT            0
+#define INTERRUPT_PROTECT       0
+
+#define DISABLE_PDN_FOR_ISSUE           (0) // Temporary for Issue Clarification, disable all PDN function.
+    #define DISABLE_PDN_MDINFRA         (0) /* Disable specified PDN function for debug */
+    #define DISABLE_PDN_MDPERI          (0) /* Disable specified PDN function for debug */
+    #define DISABLE_PDN_MDL1AO          (0) /* Disable specified PDN function for debug */
+    #define DISABLE_PDN_DEBUG_PERI_MISC (0) /* Disable specified PDN function for debug */
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "intrCtrl.h"
+#include "pdn_hw_mt6293_series.h"
+#include "sync_data.h"
+
+/* For Build pass */
+#define PDN_MDUART2 0
+#define PDN_LOGGDMA_HCLK 0
+#define PDN_L1_GDMA 0
+
+typedef enum {
+    /* MD INFRA */
+    PDN_MDUART1,
+    PDN_BUSMON,
+    PDN_SOE,
+    PDN_LOGTOP_BCLK,
+    PDN_MDINFRA_ELM_ACLK,
+    PDN_MDINFRA_ELM_FCLK,
+    PDN_MDINFRA_ELM_F26M,
+    PDN_FCS_SLV_DBCLK,
+    PDN_GCU_SLV_DBCLK,
+    PDN_TRACE_BUS2X,
+    PDN_PPPHA_CLK,
+    PDN_SDF_HCLK,
+    PDN_TRACE_PIPE,
+    PDN_TRACE_LINK,
+    PDN_TRACE_SWD,
+    PDN_LOGTOP_BUS2X,
+    PDN_MDINFRA_BUS,
+    PDN_MDINFRA_ATB_CK,
+    PDN_MDINFRA_DBG_CK,
+
+    /* MD PERI */
+    PDN_MDUART0,
+    PDN_MDGDMA,
+    PDN_MDGPTM,
+    PDN_USIM1_BCLK,
+    PDN_USIM2_BCLK,
+    PDN_MDEINT,
+    PDN_USIM1,
+    PDN_USIM2,
+    PDN_MDECT,
+    PDN_MDCIRQ,
+    PDN_THERM_SLOW,
+    PDN_MDPERI_DBG,
+    PDN_TRACE_26M,
+    PDN_MDGPTM_26M,
+    PDN_MDPERI_BUS,
+    PDN_MDDBGSYS_DCM,
+
+    /* MDL1AO */
+    PDN_C2KDO_TMR,
+    PDN_C2KDO_SLP,
+    PDN_C2K1X_TMR,
+    PDN_C2K1X_SLP, 
+    PDN_TDMA_SLP,
+    PDN_TDD_TMR,
+    PDN_TDD_SLP,
+    PDN_FDD_TMR, 
+    PDN_FDD_SLP,
+    PDN_LTE_TMR,
+    PDN_LTE_SLP,
+    PDN_IDC_CTRL,
+    PDN_BPI,
+    PDN_BSI,
+    PDN_IDC_UART,
+    PDN_DVFS_CTRL,
+    PDN_FREQM,
+    PDN_C1X_TTR,
+    PDN_CDO_TTR,
+
+    /* IA DEBUG PERI MISC */
+    PDN_RG_ASM_CK,
+    PDN_RG_PDA_MON_CK,
+    
+    PDN_MAX_DEV
+} PDN_DEVICE;
+
+#if defined(__MTK_TARGET__)
+/* spinlock for IA_DEBUG_PERI_MISC_CLK_CTRL */
+extern kal_spinlockid pdn_cg_spinlock;
+
+#define PDN_TAKE_SPINLOCK()    kal_take_spinlock(pdn_cg_spinlock, KAL_INFINITE_WAIT)
+#define PDN_GIVE_SPINLOCK()    kal_give_spinlock(pdn_cg_spinlock)
+#else
+
+#define PDN_TAKE_SPINLOCK()
+#define PDN_GIVE_SPINLOCK()
+#endif
+
+#if (DISABLE_PDN_FOR_ISSUE)
+
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_SET(PDN_DEVICE dev) {};
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_CLR(PDN_DEVICE dev) {};
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE kal_uint32 PDN_STS(PDN_DEVICE dev) {return 0;};
+
+#else // !DISABLE_PDN_FOR_ISSUE
+
+#define DRVPDN_REG(addr)                       *(volatile kal_uint32 *)(addr)
+
+/******************************************************************************
+ * Gate clock macros(Disable clock)
+ ******************************************************************************/
+
+#if !(DISABLE_PDN_MDINFRA)
+#define DRVPDN_MDINFRA_OFF(module) \
+    do { \
+        DRVPDN_REG(MD_INFRA_CKEN_CLR) = (kal_uint32)(CG_ ## module); \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDINFRA_OFF(module)
+#endif
+
+#if !(DISABLE_PDN_MDPERI)
+#define DRVPDN_MDPERI_OFF(module) \
+    do { \
+        DRVPDN_REG(MD_PERI_CKEN_CLR) = (kal_uint32)(CG_ ## module);\
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDPERI_OFF(module)
+#endif
+
+#if !(DISABLE_PDN_MDL1AO)
+#define DRVPDN_MDL1AO_OFF(module) \
+    do { \
+        DRVPDN_REG(MDL1AO_PDN_SET) = (kal_uint32)(CG_ ## module); \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDL1AO_PERI_OFF(module)
+#endif
+
+#if !(DISABLE_PDN_DEBUG_PERI_MISC)
+#define DRVPDN_DEBUG_PERI_MISC_OFF(module) \
+        do { \
+            DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) &= ~(kal_uint32)(CG_ ## module); \
+            MO_Sync(); \
+        } while(0);
+#else
+#define DRVPDN_DEBUG_PERI_MISC_OFF(module)
+#endif
+
+/******************************************************************************
+ * Un-gate clock macros(Enable clock)
+ ******************************************************************************/
+ 
+#if !(DISABLE_PDN_MDINFRA)
+#define DRVPDN_MDINFRA_ON(module) \
+    do { \
+        DRVPDN_REG(MD_INFRA_CKEN_SET) = (kal_uint32)(CG_ ## module); \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDINFRA_ON(module)
+#endif
+
+#if !(DISABLE_PDN_MDPERI)
+#define DRVPDN_MDPERI_ON(module) \
+    do { \
+        DRVPDN_REG(MD_PERI_CKEN_SET) = (kal_uint32)(CG_ ## module); \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDPERI_ON(module)
+#endif
+
+#if !(DISABLE_PDN_MDL1AO)
+#define DRVPDN_MDL1AO_ON(module) \
+    do { \
+        DRVPDN_REG(MDL1AO_PDN_CLR) = (kal_uint32)(CG_ ## module); \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDL1AO_PERI_ON(module)
+#endif
+
+#if !(DISABLE_PDN_DEBUG_PERI_MISC)
+#define DRVPDN_DEBUG_PERI_MISC_ON(module) \
+        do { \
+            DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) |= (kal_uint32)(CG_ ## module); \
+            MO_Sync(); \
+        } while(0);
+#else
+#define DRVPDN_DEBUG_PERI_MISC_ON(module)
+#endif
+
+/******************************************************************************
+ * Get clock status macros
+ ******************************************************************************/
+ 
+#define DRVPDN_MDINFRA_STS(module)            ((~(DRVPDN_REG(MD_INFRA_CKEN))) & (CG_ ## module))
+#define DRVPDN_MDPERI_STS(module)             ((~(DRVPDN_REG(MD_PERI_CKEN))) & (CG_ ## module))
+#define DRVPDN_MDL1AO_STS(module)             (DRVPDN_REG(MDL1AO_CON20) & (CG_ ## module))
+#define DRVPDN_DEBUG_PERI_MISC_STS(module)    ((~(DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL))) & (CG_ ## module))
+
+ /*------------------------------------------------------------------------
+ * void     PDN_SET(PDN_DEVICE dev)
+ * Purpose:	Disable clock of specified module.
+ * Parameters:
+ *    Input:	PDN_DEVICE dev: PDN_xxx, module index.
+ *    Output:	None
+ * returns :	None
+ * Note    :    None
+ *               
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_SET(PDN_DEVICE dev)
+{
+    #if INTERRUPT_PROTECT
+    kal_uint32 mask;
+    mask = SaveAndSetIRQMask();
+    #endif
+    
+    switch (dev)
+    { /* MD INFRA */
+      case PDN_MDUART1:
+        DRVPDN_MDINFRA_OFF(MDUART1);
+        break;      
+      case PDN_BUSMON:
+        DRVPDN_MDINFRA_OFF(BUSMON);
+        break;
+      case PDN_SOE:
+        DRVPDN_MDINFRA_OFF(SOE);
+        break;
+      case PDN_LOGTOP_BCLK:
+        DRVPDN_MDINFRA_OFF(LOGTOP_BCLK);
+        break;
+      case PDN_MDINFRA_ELM_ACLK:
+        DRVPDN_MDINFRA_OFF(MDINFRA_ELM_ACLK);
+        break;
+      case PDN_MDINFRA_ELM_FCLK:
+        DRVPDN_MDINFRA_OFF(MDINFRA_ELM_FCLK);
+        break;
+      case PDN_MDINFRA_ELM_F26M:
+        DRVPDN_MDINFRA_OFF(MDINFRA_ELM_F26M);
+        break;
+      case PDN_FCS_SLV_DBCLK:
+        DRVPDN_MDINFRA_OFF(FCS_SLV_DBCLK);
+        break;
+      case PDN_GCU_SLV_DBCLK:
+        DRVPDN_MDINFRA_OFF(GCU_SLV_DBCLK);
+        break;
+      case PDN_TRACE_BUS2X:
+        DRVPDN_MDINFRA_OFF(TRACE_BUS2X);
+        break;
+      case PDN_PPPHA_CLK:
+        DRVPDN_MDINFRA_OFF(PPPHA_CLK);
+        break;
+      case PDN_SDF_HCLK:
+        DRVPDN_MDINFRA_OFF(SDF_HCLK);
+        break;
+      case PDN_TRACE_PIPE:
+        DRVPDN_MDINFRA_OFF(TRACE_PIPE);
+        break;
+      case PDN_TRACE_LINK:
+        DRVPDN_MDINFRA_OFF(TRACE_LINK);
+        break;
+      case PDN_TRACE_SWD:
+        DRVPDN_MDINFRA_OFF(TRACE_SWD);
+        break;
+      case PDN_LOGTOP_BUS2X:
+        DRVPDN_MDINFRA_OFF(LOGTOP_BUS2X);
+        break;
+      case PDN_MDINFRA_BUS:
+        DRVPDN_MDINFRA_OFF(MDINFRA_BUS);
+        break;
+      case PDN_MDINFRA_ATB_CK:
+        DRVPDN_MDINFRA_OFF(MDINFRA_ATB_CK);
+        break;
+      case PDN_MDINFRA_DBG_CK:
+        DRVPDN_MDINFRA_OFF(MDINFRA_DBG_CK);
+        break;
+      
+      /* MD PERI */
+      case PDN_MDUART0:
+        DRVPDN_MDPERI_OFF(MDUART0);
+        break;
+      case PDN_MDGDMA:
+        DRVPDN_MDPERI_OFF(MDGDMA);
+        break;
+      case PDN_MDGPTM:
+        DRVPDN_MDPERI_OFF(MDGPTM);
+        break;
+      case PDN_USIM1_BCLK:
+        DRVPDN_MDPERI_OFF(USIM1_BCLK);
+        break;
+      case PDN_USIM2_BCLK:
+        DRVPDN_MDPERI_OFF(USIM2_BCLK);
+        break;
+      case PDN_MDEINT:
+        DRVPDN_MDPERI_OFF(MDEINT);
+        break;
+      case PDN_USIM1:
+        DRVPDN_MDPERI_OFF(USIM1);
+        break;
+      case PDN_USIM2:
+        DRVPDN_MDPERI_OFF(USIM2);
+        break;
+      case PDN_MDECT:
+        DRVPDN_MDPERI_OFF(MDECT);
+        break;
+      case PDN_MDCIRQ:
+        DRVPDN_MDPERI_OFF(MDCIRQ);
+        break;
+      case PDN_THERM_SLOW:
+        DRVPDN_MDPERI_OFF(THERM_SLOW);
+        break;
+      case PDN_MDPERI_DBG:
+        DRVPDN_MDPERI_OFF(MDPERI_DBG);
+        break;
+      case PDN_TRACE_26M:
+        DRVPDN_MDPERI_OFF(TRACE_26M);
+        break;
+      case PDN_MDGPTM_26M:
+        DRVPDN_MDPERI_OFF(MDGPTM_26M);
+        break;
+       case PDN_MDPERI_BUS:
+        DRVPDN_MDPERI_OFF(MDPERI_BUS);
+        break;    
+      case PDN_MDDBGSYS_DCM:
+        DRVPDN_MDPERI_OFF(MDDBGSYS_DCM);
+        break;
+
+      /* MDL1AO */
+      case PDN_C2KDO_TMR:
+        DRVPDN_MDL1AO_OFF(C2KDO_TMR);
+        break;
+      case PDN_C2KDO_SLP:
+        DRVPDN_MDL1AO_OFF(C2KDO_SLP);
+        break;
+      case PDN_C2K1X_TMR:
+        DRVPDN_MDL1AO_OFF(C2K1X_TMR);
+        break;
+      case PDN_C2K1X_SLP:
+        DRVPDN_MDL1AO_OFF(C2K1X_SLP);
+        break;
+      case PDN_TDMA_SLP:
+        DRVPDN_MDL1AO_OFF(TDMA_SLP);
+        break;
+      case PDN_TDD_TMR:
+        DRVPDN_MDL1AO_OFF(TDD_TMR);
+        break;
+      case PDN_TDD_SLP:
+        DRVPDN_MDL1AO_OFF(TDD_SLP);
+        break;
+      case PDN_FDD_TMR:
+        DRVPDN_MDL1AO_OFF(FDD_TMR);
+        break;
+      case PDN_FDD_SLP:
+        DRVPDN_MDL1AO_OFF(FDD_SLP);
+        break;
+      case PDN_LTE_TMR:
+        DRVPDN_MDL1AO_OFF(LTE_TMR);
+        break;
+      case PDN_LTE_SLP:
+        DRVPDN_MDL1AO_OFF(LTE_SLP);
+        break;
+      case PDN_IDC_CTRL:
+        DRVPDN_MDL1AO_OFF(IDC_CTRL);
+        break;
+      case PDN_BPI:
+        DRVPDN_MDL1AO_OFF(BPI);
+        break;
+      case PDN_BSI:
+        DRVPDN_MDL1AO_OFF(BSI);
+        break;
+      case PDN_IDC_UART:
+        DRVPDN_MDL1AO_OFF(IDC_UART);
+        break;
+      case PDN_DVFS_CTRL:
+        DRVPDN_MDL1AO_OFF(DVFS_CTRL);
+        break;
+      case PDN_FREQM:
+        DRVPDN_MDL1AO_OFF(FREQM);
+        break;
+      case PDN_C1X_TTR:
+        DRVPDN_MDL1AO_OFF(C1X_TTR);
+        break;
+      case PDN_CDO_TTR:
+        DRVPDN_MDL1AO_OFF(CDO_TTR);
+        break;
+        
+      /* IA DEBUG PERI MISC */
+      case PDN_RG_ASM_CK:
+        PDN_TAKE_SPINLOCK();
+        DRVPDN_DEBUG_PERI_MISC_OFF(RG_ASM_CK);
+        PDN_GIVE_SPINLOCK();
+        break;
+      case PDN_RG_PDA_MON_CK:
+        PDN_TAKE_SPINLOCK();
+        DRVPDN_DEBUG_PERI_MISC_OFF(RG_PDA_MON_CK);
+        PDN_GIVE_SPINLOCK();
+        break;  
+
+      case PDN_MAX_DEV:            
+            break;
+    }  
+    
+    #if INTERRUPT_PROTECT
+    RestoreIRQMask(mask);
+    #endif
+}
+
+ /*------------------------------------------------------------------------
+ * void     PDN_CLR(PDN_DEVICE dev)
+ * Purpose:	Enable clock of specified module.
+ * Parameters:
+ *    Input:	PDN_DEVICE dev: PDN_xxx, module index.
+ *    Output:	None
+ * returns :	None
+ * Note    :    None
+ *               
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_CLR(PDN_DEVICE dev)
+{
+    #if INTERRUPT_PROTECT
+    kal_uint32 mask;
+    mask = SaveAndSetIRQMask();
+    #endif
+    
+    switch (dev)
+    { /* MD INFRA */
+      case PDN_MDUART1:
+        DRVPDN_MDINFRA_ON(MDUART1);
+        break;      
+      case PDN_BUSMON:
+        DRVPDN_MDINFRA_ON(BUSMON);
+        break;
+      case PDN_SOE:
+        DRVPDN_MDINFRA_ON(SOE);
+        break;
+      case PDN_LOGTOP_BCLK:
+        DRVPDN_MDINFRA_ON(LOGTOP_BCLK);
+        break;
+      case PDN_MDINFRA_ELM_ACLK:
+        DRVPDN_MDINFRA_ON(MDINFRA_ELM_ACLK);
+        break;
+      case PDN_MDINFRA_ELM_FCLK:
+        DRVPDN_MDINFRA_ON(MDINFRA_ELM_FCLK);
+        break;
+      case PDN_MDINFRA_ELM_F26M:
+        DRVPDN_MDINFRA_ON(MDINFRA_ELM_F26M);
+        break;
+      case PDN_FCS_SLV_DBCLK:
+        DRVPDN_MDINFRA_ON(FCS_SLV_DBCLK);
+        break;
+      case PDN_GCU_SLV_DBCLK:
+        DRVPDN_MDINFRA_ON(GCU_SLV_DBCLK);
+        break;
+      case PDN_TRACE_BUS2X:
+        DRVPDN_MDINFRA_ON(TRACE_BUS2X);
+        break;
+      case PDN_PPPHA_CLK:
+        DRVPDN_MDINFRA_ON(PPPHA_CLK);
+        break;
+      case PDN_SDF_HCLK:
+        DRVPDN_MDINFRA_ON(SDF_HCLK);
+        break;
+      case PDN_TRACE_PIPE:
+        DRVPDN_MDINFRA_ON(TRACE_PIPE);
+        break;
+      case PDN_TRACE_LINK:
+        DRVPDN_MDINFRA_ON(TRACE_LINK);
+        break;
+      case PDN_TRACE_SWD:
+        DRVPDN_MDINFRA_ON(TRACE_SWD);
+        break;
+      case PDN_LOGTOP_BUS2X:
+        DRVPDN_MDINFRA_ON(LOGTOP_BUS2X);
+        break;
+      case PDN_MDINFRA_BUS:
+        DRVPDN_MDINFRA_ON(MDINFRA_BUS);
+        break;
+      case PDN_MDINFRA_ATB_CK:
+        DRVPDN_MDINFRA_ON(MDINFRA_ATB_CK);
+        break;
+      case PDN_MDINFRA_DBG_CK:
+        DRVPDN_MDINFRA_ON(MDINFRA_DBG_CK);
+        break;
+      
+      /* MD PERI */
+      case PDN_MDUART0:
+        DRVPDN_MDPERI_ON(MDUART0);
+        break;
+      case PDN_MDGDMA:
+        DRVPDN_MDPERI_ON(MDGDMA);
+        break;
+      case PDN_MDGPTM:
+        DRVPDN_MDPERI_ON(MDGPTM);
+        break;
+      case PDN_USIM1_BCLK:
+        DRVPDN_MDPERI_ON(USIM1_BCLK);
+        break;
+      case PDN_USIM2_BCLK:
+        DRVPDN_MDPERI_ON(USIM2_BCLK);
+        break;
+      case PDN_MDEINT:
+        DRVPDN_MDPERI_ON(MDEINT);
+        break;
+      case PDN_USIM1:
+        DRVPDN_MDPERI_ON(USIM1);
+        break;
+      case PDN_USIM2:
+        DRVPDN_MDPERI_ON(USIM2);
+        break;
+      case PDN_MDECT:
+        DRVPDN_MDPERI_ON(MDECT);
+        break;
+      case PDN_MDCIRQ:
+        DRVPDN_MDPERI_ON(MDCIRQ);
+        break;
+      case PDN_THERM_SLOW:
+        DRVPDN_MDPERI_ON(THERM_SLOW);
+        break;
+      case PDN_MDPERI_DBG:
+        DRVPDN_MDPERI_ON(MDPERI_DBG);
+        break;
+      case PDN_TRACE_26M:
+        DRVPDN_MDPERI_ON(TRACE_26M);
+        break;
+      case PDN_MDGPTM_26M:
+        DRVPDN_MDPERI_ON(MDGPTM_26M);
+        break;
+       case PDN_MDPERI_BUS:
+        DRVPDN_MDPERI_ON(MDPERI_BUS);
+        break;    
+      case PDN_MDDBGSYS_DCM:
+        DRVPDN_MDPERI_ON(MDDBGSYS_DCM);
+        break;
+
+      /* MDL1AO */
+      case PDN_C2KDO_TMR:
+        DRVPDN_MDL1AO_ON(C2KDO_TMR);
+        break;
+      case PDN_C2KDO_SLP:
+        DRVPDN_MDL1AO_ON(C2KDO_SLP);
+        break;
+      case PDN_C2K1X_TMR:
+        DRVPDN_MDL1AO_ON(C2K1X_TMR);
+        break;
+      case PDN_C2K1X_SLP:
+        DRVPDN_MDL1AO_ON(C2K1X_SLP);
+        break;
+      case PDN_TDMA_SLP:
+        DRVPDN_MDL1AO_ON(TDMA_SLP);
+        break;
+      case PDN_TDD_TMR:
+        DRVPDN_MDL1AO_ON(TDD_TMR);
+        break;
+      case PDN_TDD_SLP:
+        DRVPDN_MDL1AO_ON(TDD_SLP);
+        break;
+      case PDN_FDD_TMR:
+        DRVPDN_MDL1AO_ON(FDD_TMR);
+        break;
+      case PDN_FDD_SLP:
+        DRVPDN_MDL1AO_ON(FDD_SLP);
+        break;
+      case PDN_LTE_TMR:
+        DRVPDN_MDL1AO_ON(LTE_TMR);
+        break;
+      case PDN_LTE_SLP:
+        DRVPDN_MDL1AO_ON(LTE_SLP);
+        break;
+      case PDN_IDC_CTRL:
+        DRVPDN_MDL1AO_ON(IDC_CTRL);
+        break;
+      case PDN_BPI:
+        DRVPDN_MDL1AO_ON(BPI);
+        break;
+      case PDN_BSI:
+        DRVPDN_MDL1AO_ON(BSI);
+        break;
+      case PDN_IDC_UART:
+        DRVPDN_MDL1AO_ON(IDC_UART);
+        break;
+      case PDN_DVFS_CTRL:
+        DRVPDN_MDL1AO_ON(DVFS_CTRL);
+        break;
+      case PDN_FREQM:
+        DRVPDN_MDL1AO_ON(FREQM);
+        break;
+      case PDN_C1X_TTR:
+        DRVPDN_MDL1AO_ON(C1X_TTR);
+        break;
+      case PDN_CDO_TTR:
+        DRVPDN_MDL1AO_ON(CDO_TTR);
+        break;
+        
+      /* IA DEBUG PERI MISC */
+      case PDN_RG_ASM_CK:
+        PDN_TAKE_SPINLOCK();
+        DRVPDN_DEBUG_PERI_MISC_ON(RG_ASM_CK);
+        PDN_GIVE_SPINLOCK();
+        break;
+      case PDN_RG_PDA_MON_CK:
+        PDN_TAKE_SPINLOCK();
+        DRVPDN_DEBUG_PERI_MISC_ON(RG_PDA_MON_CK);
+        PDN_GIVE_SPINLOCK();
+        break;  
+
+      case PDN_MAX_DEV:            
+            break;
+    }  
+    
+    #if INTERRUPT_PROTECT
+    RestoreIRQMask(mask);
+    #endif
+}
+
+ /*------------------------------------------------------------------------
+ * kal_uint32     PDN_STS(PDN_DEVICE dev)
+ * Purpose:	Return the clock is enable/disable of specified module.
+ * Parameters:
+ *    Input:	PDN_DEVICE dev: PDN_xxx, module index.
+ *    Output:	None
+ * returns :	The clock is enable/disable of specified module.
+ * Note    :    None
+ *               
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE kal_uint32 PDN_STS(PDN_DEVICE dev)
+{
+    kal_uint32 ret = 0;
+    
+    #if INTERRUPT_PROTECT
+    kal_uint32 mask;
+    mask = SaveAndSetIRQMask();
+    #endif
+
+    switch (dev)
+    { /* MD INFRA */
+      case PDN_MDUART1:
+        ret = DRVPDN_MDINFRA_STS(MDUART1);
+        break;      
+      case PDN_BUSMON:
+        ret = DRVPDN_MDINFRA_STS(BUSMON);
+        break;
+      case PDN_SOE:
+        ret = DRVPDN_MDINFRA_STS(SOE);
+        break;
+      case PDN_LOGTOP_BCLK:
+        ret = DRVPDN_MDINFRA_STS(LOGTOP_BCLK);
+        break;
+      case PDN_MDINFRA_ELM_ACLK:
+        ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_ACLK);
+        break;
+      case PDN_MDINFRA_ELM_FCLK:
+        ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_FCLK);
+        break;
+      case PDN_MDINFRA_ELM_F26M:
+        ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_F26M);
+        break;
+      case PDN_FCS_SLV_DBCLK:
+        ret = DRVPDN_MDINFRA_STS(FCS_SLV_DBCLK);
+        break;
+      case PDN_GCU_SLV_DBCLK:
+        ret = DRVPDN_MDINFRA_STS(GCU_SLV_DBCLK);
+        break;
+      case PDN_TRACE_BUS2X:
+        ret = DRVPDN_MDINFRA_STS(TRACE_BUS2X);
+        break;
+      case PDN_PPPHA_CLK:
+        ret = DRVPDN_MDINFRA_STS(PPPHA_CLK);
+        break;
+      case PDN_SDF_HCLK:
+        ret = DRVPDN_MDINFRA_STS(SDF_HCLK);
+        break;
+      case PDN_TRACE_PIPE:
+        ret = DRVPDN_MDINFRA_STS(TRACE_PIPE);
+        break;
+      case PDN_TRACE_LINK:
+        ret = DRVPDN_MDINFRA_STS(TRACE_LINK);
+        break;
+      case PDN_TRACE_SWD:
+        ret = DRVPDN_MDINFRA_STS(TRACE_SWD);
+        break;
+      case PDN_LOGTOP_BUS2X:
+        ret = DRVPDN_MDINFRA_STS(LOGTOP_BUS2X);
+        break;
+      case PDN_MDINFRA_BUS:
+        ret = DRVPDN_MDINFRA_STS(MDINFRA_BUS);
+        break;
+      case PDN_MDINFRA_ATB_CK:
+        ret = DRVPDN_MDINFRA_STS(MDINFRA_ATB_CK);
+        break;
+      case PDN_MDINFRA_DBG_CK:
+        ret = DRVPDN_MDINFRA_STS(MDINFRA_DBG_CK);
+        break;
+      
+      /* MD PERI */
+      case PDN_MDUART0:
+        ret = DRVPDN_MDPERI_STS(MDUART0);
+        break;
+      case PDN_MDGDMA:
+        ret = DRVPDN_MDPERI_STS(MDGDMA);
+        break;
+      case PDN_MDGPTM:
+        ret = DRVPDN_MDPERI_STS(MDGPTM);
+        break;
+      case PDN_USIM1_BCLK:
+        ret = DRVPDN_MDPERI_STS(USIM1_BCLK);
+        break;
+      case PDN_USIM2_BCLK:
+        ret = DRVPDN_MDPERI_STS(USIM2_BCLK);
+        break;
+      case PDN_MDEINT:
+        ret = DRVPDN_MDPERI_STS(MDEINT);
+        break;
+      case PDN_USIM1:
+        ret = DRVPDN_MDPERI_STS(USIM1);
+        break;
+      case PDN_USIM2:
+        ret = DRVPDN_MDPERI_STS(USIM2);
+        break;
+      case PDN_MDECT:
+        ret = DRVPDN_MDPERI_STS(MDECT);
+        break;
+      case PDN_MDCIRQ:
+        ret = DRVPDN_MDPERI_STS(MDCIRQ);
+        break;
+      case PDN_THERM_SLOW:
+        ret = DRVPDN_MDPERI_STS(THERM_SLOW);
+        break;
+      case PDN_MDPERI_DBG:
+        ret = DRVPDN_MDPERI_STS(MDPERI_DBG);
+        break;
+      case PDN_TRACE_26M:
+        ret = DRVPDN_MDPERI_STS(TRACE_26M);
+        break;
+      case PDN_MDGPTM_26M:
+        ret = DRVPDN_MDPERI_STS(MDGPTM_26M);
+        break;
+       case PDN_MDPERI_BUS:
+        ret = DRVPDN_MDPERI_STS(MDPERI_BUS);
+        break;    
+      case PDN_MDDBGSYS_DCM:
+        ret = DRVPDN_MDPERI_STS(MDDBGSYS_DCM);
+        break;
+
+      /* MDL1AO */
+      case PDN_C2KDO_TMR:
+        ret = DRVPDN_MDL1AO_STS(C2KDO_TMR);
+        break;
+      case PDN_C2KDO_SLP:
+        ret = DRVPDN_MDL1AO_STS(C2KDO_SLP);
+        break;
+      case PDN_C2K1X_TMR:
+        ret = DRVPDN_MDL1AO_STS(C2K1X_TMR);
+        break;
+      case PDN_C2K1X_SLP:
+        ret = DRVPDN_MDL1AO_STS(C2K1X_SLP);
+        break;
+      case PDN_TDMA_SLP:
+        ret = DRVPDN_MDL1AO_STS(TDMA_SLP);
+        break;
+      case PDN_TDD_TMR:
+        ret = DRVPDN_MDL1AO_STS(TDD_TMR);
+        break;
+      case PDN_TDD_SLP:
+        ret = DRVPDN_MDL1AO_STS(TDD_SLP);
+        break;
+      case PDN_FDD_TMR:
+        ret = DRVPDN_MDL1AO_STS(FDD_TMR);
+        break;
+      case PDN_FDD_SLP:
+        ret = DRVPDN_MDL1AO_STS(FDD_SLP);
+        break;
+      case PDN_LTE_TMR:
+        ret = DRVPDN_MDL1AO_STS(LTE_TMR);
+        break;
+      case PDN_LTE_SLP:
+        ret = DRVPDN_MDL1AO_STS(LTE_SLP);
+        break;
+      case PDN_IDC_CTRL:
+        ret = DRVPDN_MDL1AO_STS(IDC_CTRL);
+        break;
+      case PDN_BPI:
+        ret = DRVPDN_MDL1AO_STS(BPI);
+        break;
+      case PDN_BSI:
+        ret = DRVPDN_MDL1AO_STS(BSI);
+        break;
+      case PDN_IDC_UART:
+        ret = DRVPDN_MDL1AO_STS(IDC_UART);
+        break;
+      case PDN_DVFS_CTRL:
+        ret = DRVPDN_MDL1AO_STS(DVFS_CTRL);
+        break;
+      case PDN_FREQM:
+        ret = DRVPDN_MDL1AO_STS(FREQM);
+        break;
+      case PDN_C1X_TTR:
+        ret = DRVPDN_MDL1AO_STS(C1X_TTR);
+        break;
+      case PDN_CDO_TTR:
+        ret = DRVPDN_MDL1AO_STS(CDO_TTR);
+        break;
+      
+      /* IA DEBUG PERI MISC */
+      case PDN_RG_ASM_CK:
+        ret = DRVPDN_DEBUG_PERI_MISC_STS(RG_ASM_CK);
+        break;
+      case PDN_RG_PDA_MON_CK:
+        ret = DRVPDN_DEBUG_PERI_MISC_STS(RG_PDA_MON_CK);
+        break;
+
+      case PDN_MAX_DEV:            
+            break;
+    }
+
+    #if INTERRUPT_PROTECT
+    RestoreIRQMask(mask);
+    #endif
+        
+    return ret;
+}
+
+#endif // DISABLE_PDN_FOR_ISSUE
+
+#endif /* !__DRVPDN_INLINE_ELBRUS_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6295.h b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6295.h
new file mode 100644
index 0000000..c1db04c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6295.h
@@ -0,0 +1,937 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   drvpdn_inline_mt6295.h
+ *
+ * Project:
+ * --------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   PDN Driver (C Inline Implementation) for MT6295
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 06 29 2018 devin.yang
+ * [MOLY00336176] [System Service] [PDN] [Gen95] Fix PDN driver potential bug.
+ * Comment out ASM and PDAmon PDN driver.
+ *
+ * 03 16 2018 devin.yang
+ * [MOLY00314076] [System Service][Gen97] Fix build error and build warning.
+ * .
+ *
+ * 11 08 2017 devin.yang
+ * [MOLY00287863] [System Service][PDN][Gen95][UMOLYA] Fixed PDN driver.
+ * .
+ *
+ * 09 22 2017 devin.yang
+ * [MOLY00244578] [System Service][MT6295M][PDN] Update PDN driver for MT6295M.
+ * Using atomic operation for ASM/PDAmon clock control instead of spinlock.
+ *
+ * 08 09 2017 devin.yang
+ * [MOLY00244578] [System Service][MT6295M][PDN] Update PDN driver for MT6295M.
+ * .
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __DRVPDN_INLINE_MT6295_H__
+#define __DRVPDN_INLINE_MT6295_H__
+
+/*******************************************************************************
+ * Locally Used Options
+ *******************************************************************************/
+//#define EXTRA_EXPORT            0
+//#define INTERRUPT_PROTECT       0
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "intrCtrl.h"
+#include "pdn_hw_mt6295_series.h"
+#include "sync_data.h"
+
+/*******************************************************************************
+ * Locally Used Options
+ *******************************************************************************/
+#define DISABLE_PDN_FOR_ISSUE           (0) /* Temporary for Issue Clarification, disable all PDN function. */
+    #define DISABLE_PDN_MDINFRA         (0) /* Disable specified PDN function for debug */
+    #define DISABLE_PDN_MDPERI          (0) /* Disable specified PDN function for debug */
+    #define DISABLE_PDN_MDL1AO          (0) /* Disable specified PDN function for debug */
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+    #define DISABLE_PDN_DEBUG_PERI_MISC (0) /* Disable specified PDN function for debug */
+#endif
+
+typedef enum {
+    /* MD INFRA */
+    PDN_MDUART1,
+    PDN_BUSMON,
+    PDN_SOE,
+    PDN_LOGTOP_BCLK,
+    PDN_MDINFRA_ELM_ACLK,
+    PDN_MDINFRA_ELM_FCLK,
+    PDN_MDINFRA_ELM_F26M,
+    PDN_FCS_SLV_DBCLK,
+    PDN_TRACE_BUS2X,
+    PDN_PPPHA_CLK,
+    PDN_SDF_HCLK,
+    PDN_TRACE_PIPE,
+    PDN_TRACE_SWD,
+    PDN_I2C_BCLK,
+    PDN_LOGTOP_BUS2X,
+    PDN_MDINFRA_BUS,
+    PDN_MDINFRA_ATB_CK,
+    PDN_MDINFRA_DBG_CK,
+
+    /* MD PERI */
+    PDN_MDUART0,
+    PDN_MDGDMA,
+    PDN_MDGPTM,
+    PDN_USIM1_BCLK,
+    PDN_USIM2_BCLK,
+    PDN_MDEINT,
+    PDN_LOW_PWR_DBG_MON,
+    PDN_USIM1,
+    PDN_USIM2,
+    PDN_MDECT,
+    PDN_MDCIRQ,
+    PDN_THERM_SLOW,
+    PDN_MDPERI_DBG,
+    PDN_TRACE_26M,
+    PDN_MDGPTM_26M,
+    PDN_MDPERI_BUS,
+    PDN_MDDBGSYS_BUS,
+
+    /* MDL1AO */
+    PDN_C2KDO_TMR,
+    PDN_C2KDO_SLP,
+    PDN_C2K1X_TMR,
+    PDN_C2K1X_SLP, 
+    PDN_TDMA_SLP,
+    PDN_TDD_TMR,
+    PDN_TDD_SLP,
+    PDN_FDD_TMR, 
+    PDN_FDD_SLP,
+    PDN_LTE_TMR,
+    PDN_LTE_SLP,
+    PDN_IDC_CTRL,
+    PDN_BPI,
+    PDN_BSI,
+    PDN_IDC_UART,
+    PDN_DVFS_CTRL,
+    PDN_FREQM,
+    PDN_C1X_TTR,
+    PDN_CDO_TTR,
+    PDN_MM_EVENTGEN,
+    PDN_CDO_EVENTGEN,
+    PDN_C1X_EVENTGEN,
+    PDN_TDD_EVENTGEN,
+    PDN_FDD_EVENTGEN,
+    PDN_LTE_EVENTGEN,
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+    /* IA DEBUG PERI MISC */
+    PDN_RG_ASM_CK,
+    PDN_RG_PDA_MON_CK,
+#endif
+    
+    PDN_MAX_DEV
+} PDN_DEVICE;
+
+
+#if (DISABLE_PDN_FOR_ISSUE)
+
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_SET(PDN_DEVICE dev) {};
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_CLR(PDN_DEVICE dev) {};
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE kal_bool PDN_STS(PDN_DEVICE dev) {return 0;};
+
+#else /* !DISABLE_PDN_FOR_ISSUE */
+
+#define DRVPDN_REG(addr)                       *(volatile kal_uint32 *)(addr)
+
+/******************************************************************************
+ * Gate clock macros (Disable clock)
+ ******************************************************************************/
+
+#if !(DISABLE_PDN_MDINFRA)
+#define DRVPDN_MDINFRA_OFF(module) \
+    do { \
+        DRVPDN_REG(MD_INFRA_CKEN_CLR) = (kal_uint32)module; \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDINFRA_OFF(module)
+#endif
+
+#if !(DISABLE_PDN_MDPERI)
+#define DRVPDN_MDPERI_OFF(module) \
+    do { \
+        DRVPDN_REG(MD_PERI_CKEN_CLR) = (kal_uint32)module; \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDPERI_OFF(module)
+#endif
+
+#if !(DISABLE_PDN_MDL1AO)
+#define DRVPDN_MDL1AO_OFF(module) \
+    do { \
+        DRVPDN_REG(MDL1AO_PDN_SET) = (kal_uint32)module; \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDL1AO_OFF(module)
+#endif
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+#if !(DISABLE_PDN_DEBUG_PERI_MISC)
+#define DRVPDN_DEBUG_PERI_MISC_OFF(module) \
+        do { \
+            DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) = DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) & (~module) \
+            MO_Sync(); \
+        } while(0);
+#else
+#define DRVPDN_DEBUG_PERI_MISC_OFF(module)
+#endif
+#endif
+
+/******************************************************************************
+ * Un-gate clock macros (Enable clock)
+ ******************************************************************************/
+ 
+#if !(DISABLE_PDN_MDINFRA)
+#define DRVPDN_MDINFRA_ON(module) \
+    do { \
+        DRVPDN_REG(MD_INFRA_CKEN_SET) = (kal_uint32)module; \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDINFRA_ON(module)
+#endif
+
+#if !(DISABLE_PDN_MDPERI)
+#define DRVPDN_MDPERI_ON(module) \
+    do { \
+        DRVPDN_REG(MD_PERI_CKEN_SET) = (kal_uint32)module; \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDPERI_ON(module)
+#endif
+
+#if !(DISABLE_PDN_MDL1AO)
+#define DRVPDN_MDL1AO_ON(module) \
+    do { \
+        DRVPDN_REG(MDL1AO_PDN_CLR) = (kal_uint32)module; \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDL1AO_ON(module)
+#endif
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+#if !(DISABLE_PDN_DEBUG_PERI_MISC)
+#define DRVPDN_DEBUG_PERI_MISC_ON(module) \
+        do { \
+            DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) = DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) | module \
+            MO_Sync(); \
+        } while(0);
+#else
+#define DRVPDN_DEBUG_PERI_MISC_ON(module)
+#endif
+#endif
+
+/******************************************************************************
+ * Get clock status macros
+ ******************************************************************************/
+ 
+#define DRVPDN_MDINFRA_STS(module)            !(!((~(DRVPDN_REG(MD_INFRA_CKEN))) & module))
+#define DRVPDN_MDPERI_STS(module)             !(!((~(DRVPDN_REG(MD_PERI_CKEN))) & module))
+#define DRVPDN_MDL1AO_STS(module)             !(!(DRVPDN_REG(MDL1AO_CON20) & module))
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+#define DRVPDN_DEBUG_PERI_MISC_STS(module)    !(!((~(DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL))) & module))
+#endif
+
+ /*------------------------------------------------------------------------
+ * void     PDN_SET(PDN_DEVICE dev)
+ * Purpose:	Disable clock of specified module.   
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_SET(PDN_DEVICE dev)
+{
+    switch (dev)
+    { /* MD INFRA */
+      case PDN_MDUART1:
+        DRVPDN_MDINFRA_OFF(MDUART1_CK);
+        break;      
+      case PDN_BUSMON:
+        DRVPDN_MDINFRA_OFF(BUSMON_CK);
+        break;
+      case PDN_SOE:
+        DRVPDN_MDINFRA_OFF(SOE_CK);
+        break;
+      case PDN_LOGTOP_BCLK:
+        DRVPDN_MDINFRA_OFF(LOGTOP_BCLK_CK);
+        break;
+      case PDN_MDINFRA_ELM_ACLK:
+        DRVPDN_MDINFRA_OFF(MDINFRA_ELM_ACLK_CK);
+        break;
+      case PDN_MDINFRA_ELM_FCLK:
+        DRVPDN_MDINFRA_OFF(MDINFRA_ELM_FCLK_CK);
+        break;
+      case PDN_MDINFRA_ELM_F26M:
+        DRVPDN_MDINFRA_OFF(MDINFRA_ELM_F26M_CK);
+        break;
+      case PDN_FCS_SLV_DBCLK:
+        DRVPDN_MDINFRA_OFF(FCS_SLV_DBCLK_CK);
+        break;
+      case PDN_TRACE_BUS2X:
+        DRVPDN_MDINFRA_OFF(TRACE_BUS2X_CK);
+        break;
+      case PDN_PPPHA_CLK:
+        DRVPDN_MDINFRA_OFF(PPPHA_CLK_CK);
+        break;
+      case PDN_SDF_HCLK:
+        DRVPDN_MDINFRA_OFF(SDF_HCLK_CK);
+        break;
+      case PDN_TRACE_PIPE:
+        DRVPDN_MDINFRA_OFF(TRACE_PIPE_CK);
+        break;
+      case PDN_TRACE_SWD:
+        DRVPDN_MDINFRA_OFF(TRACE_SWD_CK);
+        break;
+      case PDN_I2C_BCLK:
+        DRVPDN_MDINFRA_OFF(I2C_BCLK_CK);
+        break;
+      case PDN_LOGTOP_BUS2X:
+        DRVPDN_MDINFRA_OFF(LOGTOP_BUS2X_CK);
+        break;
+      case PDN_MDINFRA_BUS:
+        DRVPDN_MDINFRA_OFF(MDINFRA_BUS_CG);
+        break;
+      case PDN_MDINFRA_ATB_CK:
+        DRVPDN_MDINFRA_OFF(MDINFRA_ATB_CK);
+        break;
+      case PDN_MDINFRA_DBG_CK:
+        DRVPDN_MDINFRA_OFF(MDINFRA_DBG_CK);
+        break;
+      
+      /* MD PERI */
+      case PDN_MDUART0:
+        DRVPDN_MDPERI_OFF(MDUART0_CK);
+        break;
+      case PDN_MDGDMA:
+        DRVPDN_MDPERI_OFF(MDGDMA_CK);
+        break;
+      case PDN_MDGPTM:
+        DRVPDN_MDPERI_OFF(MDGPTM_CK);
+        break;
+      case PDN_USIM1_BCLK:
+        DRVPDN_MDPERI_OFF(USIM1_BCLK_CK);
+        break;
+      case PDN_USIM2_BCLK:
+        DRVPDN_MDPERI_OFF(USIM2_BCLK_CK);
+        break;
+      case PDN_MDEINT:
+        DRVPDN_MDPERI_OFF(MDEINT_CK);
+        break;
+      case PDN_LOW_PWR_DBG_MON:
+        DRVPDN_MDPERI_OFF(LOW_PWR_DBG_MON_CK);
+        break;
+      case PDN_USIM1:
+        DRVPDN_MDPERI_OFF(USIM1_CK);
+        break;
+      case PDN_USIM2:
+        DRVPDN_MDPERI_OFF(USIM2_CK);
+        break;
+      case PDN_MDECT:
+        DRVPDN_MDPERI_OFF(MDECT_CK);
+        break;
+      case PDN_MDCIRQ:
+        DRVPDN_MDPERI_OFF(MDCIRQ_CK);
+        break;
+      case PDN_THERM_SLOW:
+        DRVPDN_MDPERI_OFF(THERM_SLOW_CK);
+        break;
+      case PDN_MDPERI_DBG:
+        DRVPDN_MDPERI_OFF(MDPERI_DBG_CK);
+        break;
+      case PDN_TRACE_26M:
+        DRVPDN_MDPERI_OFF(TRACE_26M_CK);
+        break;
+      case PDN_MDGPTM_26M:
+        DRVPDN_MDPERI_OFF(MDGPTM_26M_CK);
+        break;
+       case PDN_MDPERI_BUS:
+        DRVPDN_MDPERI_OFF(MDPERI_BUS_CG);
+        break;    
+      case PDN_MDDBGSYS_BUS:
+        DRVPDN_MDPERI_OFF(MDDBGSYS_BUS_CK);
+        break;
+
+      /* MDL1AO */
+      case PDN_C2KDO_TMR:
+        DRVPDN_MDL1AO_OFF(C2KDO_TMR_CK);
+        break;
+      case PDN_C2KDO_SLP:
+        DRVPDN_MDL1AO_OFF(C2KDO_SLP_CK);
+        break;
+      case PDN_C2K1X_TMR:
+        DRVPDN_MDL1AO_OFF(C2K1X_TMR_CK);
+        break;
+      case PDN_C2K1X_SLP:
+        DRVPDN_MDL1AO_OFF(C2K1X_SLP_CK);
+        break;
+      case PDN_TDMA_SLP:
+        DRVPDN_MDL1AO_OFF(TDMA_SLP_CK);
+        break;
+      case PDN_TDD_TMR:
+        DRVPDN_MDL1AO_OFF(TDD_TMR_CK);
+        break;
+      case PDN_TDD_SLP:
+        DRVPDN_MDL1AO_OFF(TDD_SLP_CK);
+        break;
+      case PDN_FDD_TMR:
+        DRVPDN_MDL1AO_OFF(FDD_TMR_CK);
+        break;
+      case PDN_FDD_SLP:
+        DRVPDN_MDL1AO_OFF(FDD_SLP_CK);
+        break;
+      case PDN_LTE_TMR:
+        DRVPDN_MDL1AO_OFF(LTE_TMR_CK);
+        break;
+      case PDN_LTE_SLP:
+        DRVPDN_MDL1AO_OFF(LTE_SLP_CK);
+        break;
+      case PDN_IDC_CTRL:
+        DRVPDN_MDL1AO_OFF(IDC_CTRL_CK);
+        break;
+      case PDN_BPI:
+        DRVPDN_MDL1AO_OFF(BPI_CK);
+        break;
+      case PDN_BSI:
+        DRVPDN_MDL1AO_OFF(BSI_CK);
+        break;
+      case PDN_IDC_UART:
+        DRVPDN_MDL1AO_OFF(IDC_UART_CK);
+        break;
+      case PDN_DVFS_CTRL:
+        DRVPDN_MDL1AO_OFF(DVFS_CTRL_CK);
+        break;
+      case PDN_FREQM:
+        DRVPDN_MDL1AO_OFF(FREQM_CK);
+        break;
+      case PDN_C1X_TTR:
+        DRVPDN_MDL1AO_OFF(C1X_TTR_CK);
+        break;
+      case PDN_CDO_TTR:
+        DRVPDN_MDL1AO_OFF(CDO_TTR_CK);
+        break;
+      case PDN_MM_EVENTGEN:
+        DRVPDN_MDL1AO_OFF(MM_EVENTGEN_CK);
+        break;
+      case PDN_CDO_EVENTGEN:
+        DRVPDN_MDL1AO_OFF(CDO_EVENTGEN_CK);
+        break;
+      case PDN_C1X_EVENTGEN:
+        DRVPDN_MDL1AO_OFF(C1X_EVENTGEN_CK);
+        break;
+      case PDN_TDD_EVENTGEN:
+        DRVPDN_MDL1AO_OFF(TDD_EVENTGEN_CK);
+        break;
+      case PDN_FDD_EVENTGEN:
+        DRVPDN_MDL1AO_OFF(FDD_EVENTGEN_CK);
+        break;
+      case PDN_LTE_EVENTGEN:
+        DRVPDN_MDL1AO_OFF(LTE_EVENTGEN_CK);
+        break;
+
+        #if defined(PDN_ASM_PDAMON_SUPPORT)
+      /* IA DEBUG PERI MISC */
+      case PDN_RG_ASM_CK:
+        DRVPDN_DEBUG_PERI_MISC_OFF(RG_ASM_CK);
+        break;
+      case PDN_RG_PDA_MON_CK:
+        DRVPDN_DEBUG_PERI_MISC_OFF(RG_PDA_MON_CK);
+        break;
+        #endif
+        
+      case PDN_MAX_DEV:            
+            break;
+    }  
+
+}
+
+ /*------------------------------------------------------------------------
+ * void     PDN_CLR(PDN_DEVICE dev)
+ * Purpose:	Enable clock of specified module.
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_CLR(PDN_DEVICE dev)
+{
+    switch (dev)
+    { /* MD INFRA */
+      case PDN_MDUART1:
+        DRVPDN_MDINFRA_ON(MDUART1_CK);
+        break;      
+      case PDN_BUSMON:
+        DRVPDN_MDINFRA_ON(BUSMON_CK);
+        break;
+      case PDN_SOE:
+        DRVPDN_MDINFRA_ON(SOE_CK);
+        break;
+      case PDN_LOGTOP_BCLK:
+        DRVPDN_MDINFRA_ON(LOGTOP_BCLK_CK);
+        break;
+      case PDN_MDINFRA_ELM_ACLK:
+        DRVPDN_MDINFRA_ON(MDINFRA_ELM_ACLK_CK);
+        break;
+      case PDN_MDINFRA_ELM_FCLK:
+        DRVPDN_MDINFRA_ON(MDINFRA_ELM_FCLK_CK);
+        break;
+      case PDN_MDINFRA_ELM_F26M:
+        DRVPDN_MDINFRA_ON(MDINFRA_ELM_F26M_CK);
+        break;
+      case PDN_FCS_SLV_DBCLK:
+        DRVPDN_MDINFRA_ON(FCS_SLV_DBCLK_CK);
+        break;
+      case PDN_TRACE_BUS2X:
+        DRVPDN_MDINFRA_ON(TRACE_BUS2X_CK);
+        break;
+      case PDN_PPPHA_CLK:
+        DRVPDN_MDINFRA_ON(PPPHA_CLK_CK);
+        break;
+      case PDN_SDF_HCLK:
+        DRVPDN_MDINFRA_ON(SDF_HCLK_CK);
+        break;
+      case PDN_TRACE_PIPE:
+        DRVPDN_MDINFRA_ON(TRACE_PIPE_CK);
+        break;
+      case PDN_TRACE_SWD:
+        DRVPDN_MDINFRA_ON(TRACE_SWD_CK);
+        break;
+      case PDN_I2C_BCLK:
+        DRVPDN_MDINFRA_ON(I2C_BCLK_CK);
+        break;
+      case PDN_LOGTOP_BUS2X:
+        DRVPDN_MDINFRA_ON(LOGTOP_BUS2X_CK);
+        break;
+      case PDN_MDINFRA_BUS:
+        DRVPDN_MDINFRA_ON(MDINFRA_BUS_CG);
+        break;
+      case PDN_MDINFRA_ATB_CK:
+        DRVPDN_MDINFRA_ON(MDINFRA_ATB_CK);
+        break;
+      case PDN_MDINFRA_DBG_CK:
+        DRVPDN_MDINFRA_ON(MDINFRA_DBG_CK);
+        break;
+      
+      /* MD PERI */
+      case PDN_MDUART0:
+        DRVPDN_MDPERI_ON(MDUART0_CK);
+        break;
+      case PDN_MDGDMA:
+        DRVPDN_MDPERI_ON(MDGDMA_CK);
+        break;
+      case PDN_MDGPTM:
+        DRVPDN_MDPERI_ON(MDGPTM_CK);
+        break;
+      case PDN_USIM1_BCLK:
+        DRVPDN_MDPERI_ON(USIM1_BCLK_CK);
+        break;
+      case PDN_USIM2_BCLK:
+        DRVPDN_MDPERI_ON(USIM2_BCLK_CK);
+        break;
+      case PDN_MDEINT:
+        DRVPDN_MDPERI_ON(MDEINT_CK);
+        break;
+      case PDN_LOW_PWR_DBG_MON:
+        DRVPDN_MDPERI_ON(LOW_PWR_DBG_MON_CK);
+        break;
+      case PDN_USIM1:
+        DRVPDN_MDPERI_ON(USIM1_CK);
+        break;
+      case PDN_USIM2:
+        DRVPDN_MDPERI_ON(USIM2_CK);
+        break;
+      case PDN_MDECT:
+        DRVPDN_MDPERI_ON(MDECT_CK);
+        break;
+      case PDN_MDCIRQ:
+        DRVPDN_MDPERI_ON(MDCIRQ_CK);
+        break;
+      case PDN_THERM_SLOW:
+        DRVPDN_MDPERI_ON(THERM_SLOW_CK);
+        break;
+      case PDN_MDPERI_DBG:
+        DRVPDN_MDPERI_ON(MDPERI_DBG_CK);
+        break;
+      case PDN_TRACE_26M:
+        DRVPDN_MDPERI_ON(TRACE_26M_CK);
+        break;
+      case PDN_MDGPTM_26M:
+        DRVPDN_MDPERI_ON(MDGPTM_26M_CK);
+        break;
+       case PDN_MDPERI_BUS:
+        DRVPDN_MDPERI_ON(MDPERI_BUS_CG);
+        break;    
+      case PDN_MDDBGSYS_BUS:
+        DRVPDN_MDPERI_ON(MDDBGSYS_BUS_CK);
+        break;
+
+      /* MDL1AO */
+      case PDN_C2KDO_TMR:
+        DRVPDN_MDL1AO_ON(C2KDO_TMR_CK);
+        break;
+      case PDN_C2KDO_SLP:
+        DRVPDN_MDL1AO_ON(C2KDO_SLP_CK);
+        break;
+      case PDN_C2K1X_TMR:
+        DRVPDN_MDL1AO_ON(C2K1X_TMR_CK);
+        break;
+      case PDN_C2K1X_SLP:
+        DRVPDN_MDL1AO_ON(C2K1X_SLP_CK);
+        break;
+      case PDN_TDMA_SLP:
+        DRVPDN_MDL1AO_ON(TDMA_SLP_CK);
+        break;
+      case PDN_TDD_TMR:
+        DRVPDN_MDL1AO_ON(TDD_TMR_CK);
+        break;
+      case PDN_TDD_SLP:
+        DRVPDN_MDL1AO_ON(TDD_SLP_CK);
+        break;
+      case PDN_FDD_TMR:
+        DRVPDN_MDL1AO_ON(FDD_TMR_CK);
+        break;
+      case PDN_FDD_SLP:
+        DRVPDN_MDL1AO_ON(FDD_SLP_CK);
+        break;
+      case PDN_LTE_TMR:
+        DRVPDN_MDL1AO_ON(LTE_TMR_CK);
+        break;
+      case PDN_LTE_SLP:
+        DRVPDN_MDL1AO_ON(LTE_SLP_CK);
+        break;
+      case PDN_IDC_CTRL:
+        DRVPDN_MDL1AO_ON(IDC_CTRL_CK);
+        break;
+      case PDN_BPI:
+        DRVPDN_MDL1AO_ON(BPI_CK);
+        break;
+      case PDN_BSI:
+        DRVPDN_MDL1AO_ON(BSI_CK);
+        break;
+      case PDN_IDC_UART:
+        DRVPDN_MDL1AO_ON(IDC_UART_CK);
+        break;
+      case PDN_DVFS_CTRL:
+        DRVPDN_MDL1AO_ON(DVFS_CTRL_CK);
+        break;
+      case PDN_FREQM:
+        DRVPDN_MDL1AO_ON(FREQM_CK);
+        break;
+      case PDN_C1X_TTR:
+        DRVPDN_MDL1AO_ON(C1X_TTR_CK);
+        break;
+      case PDN_CDO_TTR:
+        DRVPDN_MDL1AO_ON(CDO_TTR_CK);
+        break;
+      case PDN_MM_EVENTGEN:
+        DRVPDN_MDL1AO_ON(MM_EVENTGEN_CK);
+        break;
+      case PDN_CDO_EVENTGEN:
+        DRVPDN_MDL1AO_ON(CDO_EVENTGEN_CK);
+        break;
+      case PDN_C1X_EVENTGEN:
+        DRVPDN_MDL1AO_ON(C1X_EVENTGEN_CK);
+        break;
+      case PDN_TDD_EVENTGEN:
+        DRVPDN_MDL1AO_ON(TDD_EVENTGEN_CK);
+        break;
+      case PDN_FDD_EVENTGEN:
+        DRVPDN_MDL1AO_ON(FDD_EVENTGEN_CK);
+        break;
+      case PDN_LTE_EVENTGEN:
+        DRVPDN_MDL1AO_ON(LTE_EVENTGEN_CK);
+        break;
+
+        #if defined(PDN_ASM_PDAMON_SUPPORT)
+      /* IA DEBUG PERI MISC */
+      case PDN_RG_ASM_CK:
+        DRVPDN_DEBUG_PERI_MISC_ON(RG_ASM_CK);
+        break;
+      case PDN_RG_PDA_MON_CK:
+        DRVPDN_DEBUG_PERI_MISC_ON(RG_PDA_MON_CK);
+        break;
+        #endif
+
+      case PDN_MAX_DEV:            
+            break;
+    }  
+
+}
+
+ /*------------------------------------------------------------------------
+ * kal_bool     PDN_STS(PDN_DEVICE dev)
+ * Purpose:	Return the clock is enable/disable of specified module.
+ * Return :
+ *           ret = 1. PDN is Set   (Clock is Disabled)
+ *           ret = 0. PDN is Clear (Clock is Enabled)
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE kal_bool PDN_STS(PDN_DEVICE dev)
+{
+    kal_bool ret = 0;
+
+    switch (dev)
+    { /* MD INFRA */
+      case PDN_MDUART1:
+        ret = DRVPDN_MDINFRA_STS(MDUART1_CK);
+        break;      
+      case PDN_BUSMON:
+        ret = DRVPDN_MDINFRA_STS(BUSMON_CK);
+        break;
+      case PDN_SOE:
+        ret = DRVPDN_MDINFRA_STS(SOE_CK);
+        break;
+      case PDN_LOGTOP_BCLK:
+        ret = DRVPDN_MDINFRA_STS(LOGTOP_BCLK_CK);
+        break;
+      case PDN_MDINFRA_ELM_ACLK:
+        ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_ACLK_CK);
+        break;
+      case PDN_MDINFRA_ELM_FCLK:
+        ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_FCLK_CK);
+        break;
+      case PDN_MDINFRA_ELM_F26M:
+        ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_F26M_CK);
+        break;
+      case PDN_FCS_SLV_DBCLK:
+        ret = DRVPDN_MDINFRA_STS(FCS_SLV_DBCLK_CK);
+        break;
+      case PDN_TRACE_BUS2X:
+        ret = DRVPDN_MDINFRA_STS(TRACE_BUS2X_CK);
+        break;
+      case PDN_PPPHA_CLK:
+        ret = DRVPDN_MDINFRA_STS(PPPHA_CLK_CK);
+        break;
+      case PDN_SDF_HCLK:
+        ret = DRVPDN_MDINFRA_STS(SDF_HCLK_CK);
+        break;
+      case PDN_TRACE_PIPE:
+        ret = DRVPDN_MDINFRA_STS(TRACE_PIPE_CK);
+        break;
+      case PDN_TRACE_SWD:
+        ret = DRVPDN_MDINFRA_STS(TRACE_SWD_CK);
+        break;
+      case PDN_I2C_BCLK:
+        ret = DRVPDN_MDINFRA_STS(I2C_BCLK_CK);
+        break;
+      case PDN_LOGTOP_BUS2X:
+        ret = DRVPDN_MDINFRA_STS(LOGTOP_BUS2X_CK);
+        break;
+      case PDN_MDINFRA_BUS:
+        ret = DRVPDN_MDINFRA_STS(MDINFRA_BUS_CG);
+        break;
+      case PDN_MDINFRA_ATB_CK:
+        ret = DRVPDN_MDINFRA_STS(MDINFRA_ATB_CK);
+        break;
+      case PDN_MDINFRA_DBG_CK:
+        ret = DRVPDN_MDINFRA_STS(MDINFRA_DBG_CK);
+        break;
+      
+      /* MD PERI */
+      case PDN_MDUART0:
+        ret = DRVPDN_MDPERI_STS(MDUART0_CK);
+        break;
+      case PDN_MDGDMA:
+        ret = DRVPDN_MDPERI_STS(MDGDMA_CK);
+        break;
+      case PDN_MDGPTM:
+        ret = DRVPDN_MDPERI_STS(MDGPTM_CK);
+        break;
+      case PDN_USIM1_BCLK:
+        ret = DRVPDN_MDPERI_STS(USIM1_BCLK_CK);
+        break;
+      case PDN_USIM2_BCLK:
+        ret = DRVPDN_MDPERI_STS(USIM2_BCLK_CK);
+        break;
+      case PDN_MDEINT:
+        ret = DRVPDN_MDPERI_STS(MDEINT_CK);
+        break;
+      case PDN_LOW_PWR_DBG_MON:
+        ret = DRVPDN_MDPERI_STS(LOW_PWR_DBG_MON_CK);
+        break;
+      case PDN_USIM1:
+        ret = DRVPDN_MDPERI_STS(USIM1_CK);
+        break;
+      case PDN_USIM2:
+        ret = DRVPDN_MDPERI_STS(USIM2_CK);
+        break;
+      case PDN_MDECT:
+        ret = DRVPDN_MDPERI_STS(MDECT_CK);
+        break;
+      case PDN_MDCIRQ:
+        ret = DRVPDN_MDPERI_STS(MDCIRQ_CK);
+        break;
+      case PDN_THERM_SLOW:
+        ret = DRVPDN_MDPERI_STS(THERM_SLOW_CK);
+        break;
+      case PDN_MDPERI_DBG:
+        ret = DRVPDN_MDPERI_STS(MDPERI_DBG_CK);
+        break;
+      case PDN_TRACE_26M:
+        ret = DRVPDN_MDPERI_STS(TRACE_26M_CK);
+        break;
+      case PDN_MDGPTM_26M:
+        ret = DRVPDN_MDPERI_STS(MDGPTM_26M_CK);
+        break;
+       case PDN_MDPERI_BUS:
+        ret = DRVPDN_MDPERI_STS(MDPERI_BUS_CG);
+        break;    
+      case PDN_MDDBGSYS_BUS:
+        ret = DRVPDN_MDPERI_STS(MDDBGSYS_BUS_CK);
+        break;
+
+      /* MDL1AO */
+      case PDN_C2KDO_TMR:
+        ret = DRVPDN_MDL1AO_STS(C2KDO_TMR_CK);
+        break;
+      case PDN_C2KDO_SLP:
+        ret = DRVPDN_MDL1AO_STS(C2KDO_SLP_CK);
+        break;
+      case PDN_C2K1X_TMR:
+        ret = DRVPDN_MDL1AO_STS(C2K1X_TMR_CK);
+        break;
+      case PDN_C2K1X_SLP:
+        ret = DRVPDN_MDL1AO_STS(C2K1X_SLP_CK);
+        break;
+      case PDN_TDMA_SLP:
+        ret = DRVPDN_MDL1AO_STS(TDMA_SLP_CK);
+        break;
+      case PDN_TDD_TMR:
+        ret = DRVPDN_MDL1AO_STS(TDD_TMR_CK);
+        break;
+      case PDN_TDD_SLP:
+        ret = DRVPDN_MDL1AO_STS(TDD_SLP_CK);
+        break;
+      case PDN_FDD_TMR:
+        ret = DRVPDN_MDL1AO_STS(FDD_TMR_CK);
+        break;
+      case PDN_FDD_SLP:
+        ret = DRVPDN_MDL1AO_STS(FDD_SLP_CK);
+        break;
+      case PDN_LTE_TMR:
+        ret = DRVPDN_MDL1AO_STS(LTE_TMR_CK);
+        break;
+      case PDN_LTE_SLP:
+        ret = DRVPDN_MDL1AO_STS(LTE_SLP_CK);
+        break;
+      case PDN_IDC_CTRL:
+        ret = DRVPDN_MDL1AO_STS(IDC_CTRL_CK);
+        break;
+      case PDN_BPI:
+        ret = DRVPDN_MDL1AO_STS(BPI_CK);
+        break;
+      case PDN_BSI:
+        ret = DRVPDN_MDL1AO_STS(BSI_CK);
+        break;
+      case PDN_IDC_UART:
+        ret = DRVPDN_MDL1AO_STS(IDC_UART_CK);
+        break;
+      case PDN_DVFS_CTRL:
+        ret = DRVPDN_MDL1AO_STS(DVFS_CTRL_CK);
+        break;
+      case PDN_FREQM:
+        ret = DRVPDN_MDL1AO_STS(FREQM_CK);
+        break;
+      case PDN_C1X_TTR:
+        ret = DRVPDN_MDL1AO_STS(C1X_TTR_CK);
+        break;
+      case PDN_CDO_TTR:
+        ret = DRVPDN_MDL1AO_STS(CDO_TTR_CK);
+        break;
+      case PDN_MM_EVENTGEN:
+        ret = DRVPDN_MDL1AO_STS(MM_EVENTGEN_CK);
+        break;
+      case PDN_CDO_EVENTGEN:
+        ret = DRVPDN_MDL1AO_STS(CDO_EVENTGEN_CK);
+        break;
+      case PDN_C1X_EVENTGEN:
+        ret = DRVPDN_MDL1AO_STS(C1X_EVENTGEN_CK);
+        break;
+      case PDN_TDD_EVENTGEN:
+        ret = DRVPDN_MDL1AO_STS(TDD_EVENTGEN_CK);
+        break;
+      case PDN_FDD_EVENTGEN:
+        ret = DRVPDN_MDL1AO_STS(FDD_EVENTGEN_CK);
+        break;
+      case PDN_LTE_EVENTGEN:
+        ret = DRVPDN_MDL1AO_STS(LTE_EVENTGEN_CK);
+        break;
+
+        #if defined(PDN_ASM_PDAMON_SUPPORT)
+      /* IA DEBUG PERI MISC */
+      case PDN_RG_ASM_CK:
+            ret = DRVPDN_DEBUG_PERI_MISC_STS(RG_ASM_CK);
+        break;
+      case PDN_RG_PDA_MON_CK:
+            ret = DRVPDN_DEBUG_PERI_MISC_STS(RG_PDA_MON_CK);
+        break;
+        #endif
+
+      case PDN_MAX_DEV:            
+            break;
+    }
+        
+    return ret;
+}
+
+#endif /* DISABLE_PDN_FOR_ISSUE */
+
+
+#endif /* !__DRVPDN_INLINE_MT6295_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6297.h b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6297.h
new file mode 100644
index 0000000..0f09a1e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6297.h
@@ -0,0 +1,1016 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   drvpdn_inline_mt6297.h
+ *
+ * Project:
+ * --------
+ *   UMOLYE
+ *
+ * Description:
+ * ------------
+ *   PDN Driver (C Inline Implementation) for MT6297
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 06 29 2018 devin.yang
+ * [MOLY00336176] [System Service] [PDN] [Gen95] Fix PDN driver potential bug.
+ * Comment out ASM and PDAmon PDN driver.
+ *
+ * 03 16 2018 devin.yang
+ * [MOLY00314076] [System Service][Gen97] Fix build error and build warning.
+ * .
+ *
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __DRVPDN_INLINE_MT6297_H__
+#define __DRVPDN_INLINE_MT6297_H__
+
+/*******************************************************************************
+ * Locally Used Options
+ *******************************************************************************/
+//#define EXTRA_EXPORT            0
+//#define INTERRUPT_PROTECT       0
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "intrCtrl.h"
+#include "pdn_hw_mt6297_series.h"
+#include "sync_data.h"
+
+/*******************************************************************************
+ * Locally Used Options
+ *******************************************************************************/
+#define DISABLE_PDN_FOR_ISSUE           (0) /* Temporary for Issue Clarification, disable all PDN function. */
+    #define DISABLE_PDN_MDINFRA         (0) /* Disable specified PDN function for debug */
+    #define DISABLE_PDN_MDPERI          (0) /* Disable specified PDN function for debug */
+    #define DISABLE_PDN_MDL1AO          (0) /* Disable specified PDN function for debug */
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+    #define DISABLE_PDN_DEBUG_PERI_MISC (0) /* Disable specified PDN function for debug */
+#endif
+
+typedef enum {
+    /* MD INFRA */
+    PDN_MDUART1,
+    PDN_BUSMON,
+    PDN_SOE,
+    PDN_LOGTOP_BCLK,
+    PDN_MDINFRA_ELM_ACLK,
+    PDN_MDINFRA_ELM_FCLK,
+    PDN_MDINFRA_ELM_F26M,
+    PDN_TRACE_BUS2X,
+    PDN_PPPHA_CLK,
+    PDN_SDF_HCLK,
+    PDN_TRACE_PIPE,
+    PDN_TRACE_SWD,
+    PDN_I2C_BCLK,
+    PDN_LOGTOP_BUS2X,
+    PDN_SDF_ATB_CPHY,
+    PDN_MDINFRA_BUS,
+    PDN_TRACE_ATB_CPHY,
+    PDN_MDINFRA_ATB_CK,
+    PDN_MDINFRA_DBG_CK,
+
+    /* MD PERI */
+    PDN_MDUART0,
+    PDN_MDGDMA,
+    PDN_MDGPTM,
+    PDN_MDGDMA_FORDSP,
+    PDN_USIM1_BCLK,
+    PDN_USIM2_BCLK,
+    PDN_MDEINT,
+    PDN_LOW_PWR_DBG_MON,
+    PDN_USIM1,
+    PDN_USIM2,
+    PDN_MDECT,
+    PDN_MDCIRQ,
+    PDN_THERM_SLOW,
+    PDN_MDPERI_DBG,
+    PDN_TRACE_26M,
+    PDN_MDGPTM_26M,
+    PDN_MDPERI_BUS,
+    PDN_MDDBGSYS_BUS,
+
+    /* MDL1AO */
+    PDN_C2KDO_TMR,
+    PDN_C2KDO_SLP,
+    PDN_C2K1X_TMR,
+    PDN_C2K1X_SLP, 
+    PDN_TDMA_SLP,
+    PDN_TDD_TMR,
+    PDN_TDD_SLP,
+    PDN_FDD_TMR, 
+    PDN_FDD_SLP,
+    PDN_LTE_TMR,
+    PDN_LTE_SLP,
+    PDN_IDC_CTRL,
+    PDN_BPI,
+    PDN_BSI,
+    PDN_IDC_UART,
+    PDN_DVFS_CTRL,
+    PDN_FREQM,
+    PDN_C1X_TTR,
+    PDN_CDO_TTR,
+    PDN_MM_EVENTGEN,
+    PDN_CDO_EVENTGEN,
+    PDN_C1X_EVENTGEN,
+    PDN_TDD_EVENTGEN,
+    PDN_FDD_EVENTGEN,
+    PDN_LTE_EVENTGEN,
+    PDN_MDL1_SLP_CTRL,
+    PDN_UCNT_D_TOP,
+    PDN_NR_TIMER,
+    PDN_NR_SLP,
+    PDN_NR_EVENTGEN,
+    PDN_DIGRF_MIPI,
+    PDN_RF_SLP_CTRL,
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+    /* IA DEBUG PERI MISC */
+    PDN_RG_ASM_CK,
+    PDN_RG_PDA_MON_CK,
+#endif
+
+    PDN_MAX_DEV
+} PDN_DEVICE;
+
+
+#if (DISABLE_PDN_FOR_ISSUE)
+
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_SET(PDN_DEVICE dev) {};
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_CLR(PDN_DEVICE dev) {};
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE kal_bool PDN_STS(PDN_DEVICE dev) {return 0;};
+
+#else /* !DISABLE_PDN_FOR_ISSUE */
+
+#define DRVPDN_REG(addr)                       *(volatile kal_uint32 *)(addr)
+
+/******************************************************************************
+ * Gate clock macros (Disable clock)
+ ******************************************************************************/
+
+#if !(DISABLE_PDN_MDINFRA)
+#define DRVPDN_MDINFRA_OFF(module) \
+    do { \
+        DRVPDN_REG(MD_INFRA_CKEN_CLR) = (kal_uint32)module; \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDINFRA_OFF(module)
+#endif
+
+#if !(DISABLE_PDN_MDPERI)
+#define DRVPDN_MDPERI_OFF(module) \
+    do { \
+        DRVPDN_REG(MD_PERI_CKEN_CLR) = (kal_uint32)module; \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDPERI_OFF(module)
+#endif
+
+#if !(DISABLE_PDN_MDL1AO)
+#define DRVPDN_MDL1AO_OFF(module) \
+    do { \
+        DRVPDN_REG(MDL1AO_PDN_SET) = (kal_uint32)module; \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDL1AO_OFF(module)
+#endif
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+#if !(DISABLE_PDN_DEBUG_PERI_MISC)
+#define DRVPDN_DEBUG_PERI_MISC_OFF(module) \
+        do { \
+            DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) = DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) & (~module) \
+            MO_Sync(); \
+        } while(0);
+#else
+#define DRVPDN_DEBUG_PERI_MISC_OFF(module)
+#endif
+#endif
+
+/******************************************************************************
+ * Un-gate clock macros (Enable clock)
+ ******************************************************************************/
+ 
+#if !(DISABLE_PDN_MDINFRA)
+#define DRVPDN_MDINFRA_ON(module) \
+    do { \
+        DRVPDN_REG(MD_INFRA_CKEN_SET) = (kal_uint32)module; \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDINFRA_ON(module)
+#endif
+
+#if !(DISABLE_PDN_MDPERI)
+#define DRVPDN_MDPERI_ON(module) \
+    do { \
+        DRVPDN_REG(MD_PERI_CKEN_SET) = (kal_uint32)module; \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDPERI_ON(module)
+#endif
+
+#if !(DISABLE_PDN_MDL1AO)
+#define DRVPDN_MDL1AO_ON(module) \
+    do { \
+        DRVPDN_REG(MDL1AO_PDN_CLR) = (kal_uint32)module; \
+        MO_Sync(); \
+    } while(0);
+#else
+#define DRVPDN_MDL1AO_ON(module)
+#endif
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+#if !(DISABLE_PDN_DEBUG_PERI_MISC)
+#define DRVPDN_DEBUG_PERI_MISC_ON(module) \
+        do { \
+            DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) = DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) | module \
+            MO_Sync(); \
+        } while(0);
+#else
+#define DRVPDN_DEBUG_PERI_MISC_ON(module)
+#endif
+#endif
+
+/******************************************************************************
+ * Get clock status macros
+ ******************************************************************************/
+ 
+#define DRVPDN_MDINFRA_STS(module)            !(!((~(DRVPDN_REG(MD_INFRA_CKEN))) & module))
+#define DRVPDN_MDPERI_STS(module)             !(!((~(DRVPDN_REG(MD_PERI_CKEN))) & module))
+#define DRVPDN_MDL1AO_STS(module)             !(!(DRVPDN_REG(MDL1AO_CON20) & module))
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+#define DRVPDN_DEBUG_PERI_MISC_STS(module)    !(!((~(DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL))) & module))
+#endif
+
+ /*------------------------------------------------------------------------
+ * void     PDN_SET(PDN_DEVICE dev)
+ * Purpose: Disable clock of specified module.   
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_SET(PDN_DEVICE dev)
+{
+    switch (dev)
+    {   /* MD INFRA */
+        case PDN_MDUART1:
+            DRVPDN_MDINFRA_OFF(MDUART1_CK);
+            break;      
+        case PDN_BUSMON:
+            DRVPDN_MDINFRA_OFF(BUSMON_CK);
+            break;
+        case PDN_SOE:
+            DRVPDN_MDINFRA_OFF(SOE_CK);
+            break;
+        case PDN_LOGTOP_BCLK:
+            DRVPDN_MDINFRA_OFF(LOGTOP_BCLK_CK);
+            break;
+        case PDN_MDINFRA_ELM_ACLK:
+            DRVPDN_MDINFRA_OFF(MDINFRA_ELM_ACLK_CK);
+            break;
+        case PDN_MDINFRA_ELM_FCLK:
+            DRVPDN_MDINFRA_OFF(MDINFRA_ELM_FCLK_CK);
+            break;
+        case PDN_MDINFRA_ELM_F26M:
+            DRVPDN_MDINFRA_OFF(MDINFRA_ELM_F26M_CK);
+            break;
+        case PDN_TRACE_BUS2X:
+            DRVPDN_MDINFRA_OFF(TRACE_BUS2X_CK);
+            break;
+        case PDN_PPPHA_CLK:
+            DRVPDN_MDINFRA_OFF(PPPHA_CLK_CK);
+            break;
+        case PDN_SDF_HCLK:
+            DRVPDN_MDINFRA_OFF(SDF_HCLK_CK);
+            break;
+        case PDN_TRACE_PIPE:
+            DRVPDN_MDINFRA_OFF(TRACE_PIPE_CK);
+            break;
+        case PDN_TRACE_SWD:
+            DRVPDN_MDINFRA_OFF(TRACE_SWD_CK);
+            break;
+        case PDN_I2C_BCLK:
+            DRVPDN_MDINFRA_OFF(I2C_BCLK_CK);
+            break;
+        case PDN_LOGTOP_BUS2X:
+            DRVPDN_MDINFRA_OFF(LOGTOP_BUS2X_CK);
+            break;
+        case PDN_SDF_ATB_CPHY:
+            DRVPDN_MDINFRA_OFF(SDF_ATB_CPHY_CK);
+            break;
+        case PDN_MDINFRA_BUS:
+            DRVPDN_MDINFRA_OFF(MDINFRA_BUS_CG);
+            break;
+        case PDN_TRACE_ATB_CPHY:
+            DRVPDN_MDINFRA_OFF(TRACE_ATB_CPHY_CK);
+            break;
+        case PDN_MDINFRA_ATB_CK:
+            DRVPDN_MDINFRA_OFF(MDINFRA_ATB_CK);
+            break;
+        case PDN_MDINFRA_DBG_CK:
+            DRVPDN_MDINFRA_OFF(MDINFRA_DBG_CK);
+            break;
+      
+        /* MD PERI */
+        case PDN_MDUART0:
+            DRVPDN_MDPERI_OFF(MDUART0_CK);
+            break;
+        case PDN_MDGDMA:
+            DRVPDN_MDPERI_OFF(MDGDMA_CK);
+            break;
+        case PDN_MDGPTM:
+            DRVPDN_MDPERI_OFF(MDGPTM_CK);
+            break;
+        case PDN_MDGDMA_FORDSP:
+            DRVPDN_MDPERI_OFF(MDGDMA_FORDSP_CK);
+            break;
+        case PDN_USIM1_BCLK:
+            DRVPDN_MDPERI_OFF(USIM1_BCLK_CK);
+            break;
+        case PDN_USIM2_BCLK:
+            DRVPDN_MDPERI_OFF(USIM2_BCLK_CK);
+            break;
+        case PDN_MDEINT:
+            DRVPDN_MDPERI_OFF(MDEINT_CK);
+            break;
+        case PDN_LOW_PWR_DBG_MON:
+            DRVPDN_MDPERI_OFF(LOW_PWR_DBG_MON_CK);
+            break;
+        case PDN_USIM1:
+            DRVPDN_MDPERI_OFF(USIM1_CK);
+            break;
+        case PDN_USIM2:
+            DRVPDN_MDPERI_OFF(USIM2_CK);
+            break;
+        case PDN_MDECT:
+            DRVPDN_MDPERI_OFF(MDECT_CK);
+            break;
+        case PDN_MDCIRQ:
+            DRVPDN_MDPERI_OFF(MDCIRQ_CK);
+            break;
+        case PDN_THERM_SLOW:
+            DRVPDN_MDPERI_OFF(THERM_SLOW_CK);
+            break;
+        case PDN_MDPERI_DBG:
+            DRVPDN_MDPERI_OFF(MDPERI_DBG_CK);
+            break;
+        case PDN_TRACE_26M:
+            DRVPDN_MDPERI_OFF(TRACE_26M_CK);
+            break;
+        case PDN_MDGPTM_26M:
+            DRVPDN_MDPERI_OFF(MDGPTM_26M_CK);
+            break;
+        case PDN_MDPERI_BUS:
+            DRVPDN_MDPERI_OFF(MDPERI_BUS_CG);
+            break;    
+        case PDN_MDDBGSYS_BUS:
+            DRVPDN_MDPERI_OFF(MDDBGSYS_BUS_CK);
+            break;
+
+        /* MDL1AO */
+        case PDN_C2KDO_TMR:
+            DRVPDN_MDL1AO_OFF(C2KDO_TMR_CG);
+            break;
+        case PDN_C2KDO_SLP:
+            DRVPDN_MDL1AO_OFF(C2KDO_SLP_CG);
+            break;
+        case PDN_C2K1X_TMR:
+            DRVPDN_MDL1AO_OFF(C2K1X_TMR_CG);
+            break;
+        case PDN_C2K1X_SLP:
+            DRVPDN_MDL1AO_OFF(C2K1X_SLP_CG);
+            break;
+        case PDN_TDMA_SLP:
+            DRVPDN_MDL1AO_OFF(TDMA_SLP_CG);
+            break;
+        case PDN_TDD_TMR:
+            DRVPDN_MDL1AO_OFF(TDD_TMR_CG);
+            break;
+        case PDN_TDD_SLP:
+            DRVPDN_MDL1AO_OFF(TDD_SLP_CG);
+            break;
+        case PDN_FDD_TMR:
+            DRVPDN_MDL1AO_OFF(FDD_TMR_CG);
+            break;
+        case PDN_FDD_SLP:
+            DRVPDN_MDL1AO_OFF(FDD_SLP_CG);
+            break;
+        case PDN_LTE_TMR:
+            DRVPDN_MDL1AO_OFF(LTE_TMR_CG);
+            break;
+        case PDN_LTE_SLP:
+            DRVPDN_MDL1AO_OFF(LTE_SLP_CG);
+            break;
+        case PDN_IDC_CTRL:
+            DRVPDN_MDL1AO_OFF(IDC_CTRL_CG);
+            break;
+        case PDN_BPI:
+            DRVPDN_MDL1AO_OFF(BPI_CG);
+            break;
+        case PDN_BSI:
+            DRVPDN_MDL1AO_OFF(BSI_CG);
+            break;
+        case PDN_IDC_UART:
+            DRVPDN_MDL1AO_OFF(IDC_UART_CG);
+            break;
+        case PDN_DVFS_CTRL:
+            DRVPDN_MDL1AO_OFF(DVFS_CTRL_CG);
+            break;
+        case PDN_FREQM:
+            DRVPDN_MDL1AO_OFF(FREQM_CG);
+            break;
+        case PDN_C1X_TTR:
+            DRVPDN_MDL1AO_OFF(C1X_TTR_CG);
+            break;
+        case PDN_CDO_TTR:
+            DRVPDN_MDL1AO_OFF(CDO_TTR_CG);
+            break;
+        case PDN_MM_EVENTGEN:
+            DRVPDN_MDL1AO_OFF(MM_EVENTGEN_CG);
+            break;
+        case PDN_CDO_EVENTGEN:
+            DRVPDN_MDL1AO_OFF(CDO_EVENTGEN_CG);
+            break;
+        case PDN_C1X_EVENTGEN:
+            DRVPDN_MDL1AO_OFF(C1X_EVENTGEN_CG);
+            break;
+        case PDN_TDD_EVENTGEN:
+            DRVPDN_MDL1AO_OFF(TDD_EVENTGEN_CG);
+            break;
+        case PDN_FDD_EVENTGEN:
+            DRVPDN_MDL1AO_OFF(FDD_EVENTGEN_CG);
+            break;
+        case PDN_LTE_EVENTGEN:
+            DRVPDN_MDL1AO_OFF(LTE_EVENTGEN_CG);
+            break;
+        case PDN_MDL1_SLP_CTRL:
+            DRVPDN_MDL1AO_OFF(MDL1_SLP_CTRL_CG);
+            break;
+        case PDN_UCNT_D_TOP:
+            DRVPDN_MDL1AO_OFF(UCNT_D_TOP_CG);
+            break;
+        case PDN_NR_TIMER:
+            DRVPDN_MDL1AO_OFF(NR_TIMER_CG);
+            break;
+        case PDN_NR_SLP:
+            DRVPDN_MDL1AO_OFF(NR_SLP_CG);
+            break;
+        case PDN_NR_EVENTGEN:
+            DRVPDN_MDL1AO_OFF(NR_EVENTGEN_CG);
+            break;
+        case PDN_DIGRF_MIPI:
+            DRVPDN_MDL1AO_OFF(DIGRF_MIPI_CG);
+            break;
+        case PDN_RF_SLP_CTRL:
+            DRVPDN_MDL1AO_OFF(RF_SLP_CTRL_CG);
+            break;
+
+        #if defined(PDN_ASM_PDAMON_SUPPORT)
+        /* IA DEBUG PERI MISC */
+        case PDN_RG_ASM_CK:
+            DRVPDN_DEBUG_PERI_MISC_OFF(RG_ASM_CK);
+            break;
+        case PDN_RG_PDA_MON_CK:
+            DRVPDN_DEBUG_PERI_MISC_OFF(RG_PDA_MON_CK);
+            break;
+        #endif
+        
+        case PDN_MAX_DEV:
+            break;
+    }  
+
+}
+
+ /*------------------------------------------------------------------------
+ * void     PDN_CLR(PDN_DEVICE dev)
+ * Purpose: Enable clock of specified module.
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_CLR(PDN_DEVICE dev)
+{
+    switch (dev)
+    {   /* MD INFRA */
+        case PDN_MDUART1:
+            DRVPDN_MDINFRA_ON(MDUART1_CK);
+            break;      
+        case PDN_BUSMON:
+            DRVPDN_MDINFRA_ON(BUSMON_CK);
+            break;
+        case PDN_SOE:
+            DRVPDN_MDINFRA_ON(SOE_CK);
+            break;
+        case PDN_LOGTOP_BCLK:
+            DRVPDN_MDINFRA_ON(LOGTOP_BCLK_CK);
+            break;
+        case PDN_MDINFRA_ELM_ACLK:
+            DRVPDN_MDINFRA_ON(MDINFRA_ELM_ACLK_CK);
+            break;
+        case PDN_MDINFRA_ELM_FCLK:
+            DRVPDN_MDINFRA_ON(MDINFRA_ELM_FCLK_CK);
+            break;
+        case PDN_MDINFRA_ELM_F26M:
+            DRVPDN_MDINFRA_ON(MDINFRA_ELM_F26M_CK);
+            break;
+        case PDN_TRACE_BUS2X:
+            DRVPDN_MDINFRA_ON(TRACE_BUS2X_CK);
+            break;
+        case PDN_PPPHA_CLK:
+            DRVPDN_MDINFRA_ON(PPPHA_CLK_CK);
+            break;
+        case PDN_SDF_HCLK:
+            DRVPDN_MDINFRA_ON(SDF_HCLK_CK);
+            break;
+        case PDN_TRACE_PIPE:
+            DRVPDN_MDINFRA_ON(TRACE_PIPE_CK);
+            break;
+        case PDN_TRACE_SWD:
+            DRVPDN_MDINFRA_ON(TRACE_SWD_CK);
+            break;
+        case PDN_I2C_BCLK:
+            DRVPDN_MDINFRA_ON(I2C_BCLK_CK);
+            break;
+        case PDN_LOGTOP_BUS2X:
+            DRVPDN_MDINFRA_ON(LOGTOP_BUS2X_CK);
+            break;
+        case PDN_SDF_ATB_CPHY:
+            DRVPDN_MDINFRA_ON(SDF_ATB_CPHY_CK);
+            break;
+        case PDN_MDINFRA_BUS:
+            DRVPDN_MDINFRA_ON(MDINFRA_BUS_CG);
+            break;
+        case PDN_TRACE_ATB_CPHY:
+            DRVPDN_MDINFRA_ON(TRACE_ATB_CPHY_CK);
+            break;
+        case PDN_MDINFRA_ATB_CK:
+            DRVPDN_MDINFRA_ON(MDINFRA_ATB_CK);
+            break;
+        case PDN_MDINFRA_DBG_CK:
+            DRVPDN_MDINFRA_ON(MDINFRA_DBG_CK);
+            break;
+      
+        /* MD PERI */
+        case PDN_MDUART0:
+            DRVPDN_MDPERI_ON(MDUART0_CK);
+            break;
+        case PDN_MDGDMA:
+            DRVPDN_MDPERI_ON(MDGDMA_CK);
+            break;
+        case PDN_MDGPTM:
+            DRVPDN_MDPERI_ON(MDGPTM_CK);
+            break;
+        case PDN_MDGDMA_FORDSP:
+            DRVPDN_MDPERI_ON(MDGDMA_FORDSP_CK);
+            break;
+        case PDN_USIM1_BCLK:
+            DRVPDN_MDPERI_ON(USIM1_BCLK_CK);
+            break;
+        case PDN_USIM2_BCLK:
+            DRVPDN_MDPERI_ON(USIM2_BCLK_CK);
+            break;
+        case PDN_MDEINT:
+            DRVPDN_MDPERI_ON(MDEINT_CK);
+            break;
+        case PDN_LOW_PWR_DBG_MON:
+            DRVPDN_MDPERI_ON(LOW_PWR_DBG_MON_CK);
+            break;
+        case PDN_USIM1:
+            DRVPDN_MDPERI_ON(USIM1_CK);
+            break;
+        case PDN_USIM2:
+            DRVPDN_MDPERI_ON(USIM2_CK);
+            break;
+        case PDN_MDECT:
+            DRVPDN_MDPERI_ON(MDECT_CK);
+            break;
+        case PDN_MDCIRQ:
+            DRVPDN_MDPERI_ON(MDCIRQ_CK);
+            break;
+        case PDN_THERM_SLOW:
+            DRVPDN_MDPERI_ON(THERM_SLOW_CK);
+            break;
+        case PDN_MDPERI_DBG:
+            DRVPDN_MDPERI_ON(MDPERI_DBG_CK);
+            break;
+        case PDN_TRACE_26M:
+            DRVPDN_MDPERI_ON(TRACE_26M_CK);
+            break;
+        case PDN_MDGPTM_26M:
+            DRVPDN_MDPERI_ON(MDGPTM_26M_CK);
+            break;
+        case PDN_MDPERI_BUS:
+            DRVPDN_MDPERI_ON(MDPERI_BUS_CG);
+            break;    
+        case PDN_MDDBGSYS_BUS:
+            DRVPDN_MDPERI_ON(MDDBGSYS_BUS_CK);
+            break;
+
+        /* MDL1AO */
+        case PDN_C2KDO_TMR:
+            DRVPDN_MDL1AO_ON(C2KDO_TMR_CG);
+            break;
+        case PDN_C2KDO_SLP:
+            DRVPDN_MDL1AO_ON(C2KDO_SLP_CG);
+            break;
+        case PDN_C2K1X_TMR:
+            DRVPDN_MDL1AO_ON(C2K1X_TMR_CG);
+            break;
+        case PDN_C2K1X_SLP:
+            DRVPDN_MDL1AO_ON(C2K1X_SLP_CG);
+            break;
+        case PDN_TDMA_SLP:
+            DRVPDN_MDL1AO_ON(TDMA_SLP_CG);
+            break;
+        case PDN_TDD_TMR:
+            DRVPDN_MDL1AO_ON(TDD_TMR_CG);
+            break;
+        case PDN_TDD_SLP:
+            DRVPDN_MDL1AO_ON(TDD_SLP_CG);
+            break;
+        case PDN_FDD_TMR:
+            DRVPDN_MDL1AO_ON(FDD_TMR_CG);
+            break;
+        case PDN_FDD_SLP:
+            DRVPDN_MDL1AO_ON(FDD_SLP_CG);
+            break;
+        case PDN_LTE_TMR:
+            DRVPDN_MDL1AO_ON(LTE_TMR_CG);
+            break;
+        case PDN_LTE_SLP:
+            DRVPDN_MDL1AO_ON(LTE_SLP_CG);
+            break;
+        case PDN_IDC_CTRL:
+            DRVPDN_MDL1AO_ON(IDC_CTRL_CG);
+            break;
+        case PDN_BPI:
+            DRVPDN_MDL1AO_ON(BPI_CG);
+            break;
+        case PDN_BSI:
+            DRVPDN_MDL1AO_ON(BSI_CG);
+            break;
+        case PDN_IDC_UART:
+            DRVPDN_MDL1AO_ON(IDC_UART_CG);
+            break;
+        case PDN_DVFS_CTRL:
+            DRVPDN_MDL1AO_ON(DVFS_CTRL_CG);
+            break;
+        case PDN_FREQM:
+            DRVPDN_MDL1AO_ON(FREQM_CG);
+            break;
+        case PDN_C1X_TTR:
+            DRVPDN_MDL1AO_ON(C1X_TTR_CG);
+            break;
+        case PDN_CDO_TTR:
+            DRVPDN_MDL1AO_ON(CDO_TTR_CG);
+            break;
+        case PDN_MM_EVENTGEN:
+            DRVPDN_MDL1AO_ON(MM_EVENTGEN_CG);
+            break;
+        case PDN_CDO_EVENTGEN:
+            DRVPDN_MDL1AO_ON(CDO_EVENTGEN_CG);
+            break;
+        case PDN_C1X_EVENTGEN:
+            DRVPDN_MDL1AO_ON(C1X_EVENTGEN_CG);
+            break;
+        case PDN_TDD_EVENTGEN:
+            DRVPDN_MDL1AO_ON(TDD_EVENTGEN_CG);
+            break;
+        case PDN_FDD_EVENTGEN:
+            DRVPDN_MDL1AO_ON(FDD_EVENTGEN_CG);
+            break;
+        case PDN_LTE_EVENTGEN:
+            DRVPDN_MDL1AO_ON(LTE_EVENTGEN_CG);
+            break;
+        case PDN_MDL1_SLP_CTRL:
+            DRVPDN_MDL1AO_ON(MDL1_SLP_CTRL_CG);
+            break;
+        case PDN_UCNT_D_TOP:
+            DRVPDN_MDL1AO_ON(UCNT_D_TOP_CG);
+            break;
+        case PDN_NR_TIMER:
+            DRVPDN_MDL1AO_ON(NR_TIMER_CG);
+            break;
+        case PDN_NR_SLP:
+            DRVPDN_MDL1AO_ON(NR_SLP_CG);
+            break;
+        case PDN_NR_EVENTGEN:
+            DRVPDN_MDL1AO_ON(NR_EVENTGEN_CG);
+            break;
+        case PDN_DIGRF_MIPI:
+            DRVPDN_MDL1AO_ON(DIGRF_MIPI_CG);
+            break;
+        case PDN_RF_SLP_CTRL:
+            DRVPDN_MDL1AO_ON(RF_SLP_CTRL_CG);
+            break;
+
+        #if defined(PDN_ASM_PDAMON_SUPPORT)
+        /* IA DEBUG PERI MISC */
+        case PDN_RG_ASM_CK:
+            DRVPDN_DEBUG_PERI_MISC_ON(RG_ASM_CK);
+            break;
+        case PDN_RG_PDA_MON_CK:
+            DRVPDN_DEBUG_PERI_MISC_ON(RG_PDA_MON_CK);
+            break;
+        #endif
+
+        case PDN_MAX_DEV:
+            break;
+    }  
+
+}
+
+ /*------------------------------------------------------------------------
+ * kal_bool     PDN_STS(PDN_DEVICE dev)
+ * Purpose: Return the clock is enable/disable of specified module.
+ * Return :
+ *           ret = 1. PDN is Set   (Clock is Disabled)
+ *           ret = 0. PDN is Clear (Clock is Enabled)
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE kal_bool PDN_STS(PDN_DEVICE dev)
+{
+    kal_bool ret = 0;
+
+    switch (dev)
+    {   /* MD INFRA */
+        case PDN_MDUART1:
+            ret = DRVPDN_MDINFRA_STS(MDUART1_CK);
+            break;      
+        case PDN_BUSMON:
+            ret = DRVPDN_MDINFRA_STS(BUSMON_CK);
+            break;
+        case PDN_SOE:
+            ret = DRVPDN_MDINFRA_STS(SOE_CK);
+            break;
+        case PDN_LOGTOP_BCLK:
+            ret = DRVPDN_MDINFRA_STS(LOGTOP_BCLK_CK);
+            break;
+        case PDN_MDINFRA_ELM_ACLK:
+            ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_ACLK_CK);
+            break;
+        case PDN_MDINFRA_ELM_FCLK:
+            ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_FCLK_CK);
+            break;
+        case PDN_MDINFRA_ELM_F26M:
+            ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_F26M_CK);
+            break;
+        case PDN_TRACE_BUS2X:
+            ret = DRVPDN_MDINFRA_STS(TRACE_BUS2X_CK);
+            break;
+        case PDN_PPPHA_CLK:
+            ret = DRVPDN_MDINFRA_STS(PPPHA_CLK_CK);
+            break;
+        case PDN_SDF_HCLK:
+            ret = DRVPDN_MDINFRA_STS(SDF_HCLK_CK);
+            break;
+        case PDN_TRACE_PIPE:
+            ret = DRVPDN_MDINFRA_STS(TRACE_PIPE_CK);
+            break;
+        case PDN_TRACE_SWD:
+            ret = DRVPDN_MDINFRA_STS(TRACE_SWD_CK);
+            break;
+        case PDN_I2C_BCLK:
+            ret = DRVPDN_MDINFRA_STS(I2C_BCLK_CK);
+            break;
+        case PDN_LOGTOP_BUS2X:
+            ret = DRVPDN_MDINFRA_STS(LOGTOP_BUS2X_CK);
+            break;
+        case PDN_SDF_ATB_CPHY:
+            ret = DRVPDN_MDINFRA_STS(SDF_ATB_CPHY_CK);
+            break;
+        case PDN_MDINFRA_BUS:
+            ret = DRVPDN_MDINFRA_STS(MDINFRA_BUS_CG);
+            break;
+        case PDN_TRACE_ATB_CPHY:
+            ret = DRVPDN_MDINFRA_STS(TRACE_ATB_CPHY_CK);
+            break;
+        case PDN_MDINFRA_ATB_CK:
+            ret = DRVPDN_MDINFRA_STS(MDINFRA_ATB_CK);
+            break;
+        case PDN_MDINFRA_DBG_CK:
+            ret = DRVPDN_MDINFRA_STS(MDINFRA_DBG_CK);
+            break;
+      
+        /* MD PERI */
+        case PDN_MDUART0:
+            ret = DRVPDN_MDPERI_STS(MDUART0_CK);
+            break;
+        case PDN_MDGDMA:
+            ret = DRVPDN_MDPERI_STS(MDGDMA_CK);
+            break;
+        case PDN_MDGPTM:
+            ret = DRVPDN_MDPERI_STS(MDGPTM_CK);
+            break;
+        case PDN_MDGDMA_FORDSP:
+            ret = DRVPDN_MDPERI_STS(MDGDMA_FORDSP_CK);
+            break;
+        case PDN_USIM1_BCLK:
+            ret = DRVPDN_MDPERI_STS(USIM1_BCLK_CK);
+            break;
+        case PDN_USIM2_BCLK:
+            ret = DRVPDN_MDPERI_STS(USIM2_BCLK_CK);
+            break;
+        case PDN_MDEINT:
+            ret = DRVPDN_MDPERI_STS(MDEINT_CK);
+            break;
+        case PDN_LOW_PWR_DBG_MON:
+            ret = DRVPDN_MDPERI_STS(LOW_PWR_DBG_MON_CK);
+            break;
+        case PDN_USIM1:
+            ret = DRVPDN_MDPERI_STS(USIM1_CK);
+            break;
+        case PDN_USIM2:
+            ret = DRVPDN_MDPERI_STS(USIM2_CK);
+            break;
+        case PDN_MDECT:
+            ret = DRVPDN_MDPERI_STS(MDECT_CK);
+            break;
+        case PDN_MDCIRQ:
+            ret = DRVPDN_MDPERI_STS(MDCIRQ_CK);
+            break;
+        case PDN_THERM_SLOW:
+            ret = DRVPDN_MDPERI_STS(THERM_SLOW_CK);
+            break;
+        case PDN_MDPERI_DBG:
+            ret = DRVPDN_MDPERI_STS(MDPERI_DBG_CK);
+            break;
+        case PDN_TRACE_26M:
+            ret = DRVPDN_MDPERI_STS(TRACE_26M_CK);
+            break;
+        case PDN_MDGPTM_26M:
+            ret = DRVPDN_MDPERI_STS(MDGPTM_26M_CK);
+            break;
+        case PDN_MDPERI_BUS:
+            ret = DRVPDN_MDPERI_STS(MDPERI_BUS_CG);
+            break;    
+        case PDN_MDDBGSYS_BUS:
+            ret = DRVPDN_MDPERI_STS(MDDBGSYS_BUS_CK);
+            break;
+
+        /* MDL1AO */
+        case PDN_C2KDO_TMR:
+            ret = DRVPDN_MDL1AO_STS(C2KDO_TMR_CG);
+            break;
+        case PDN_C2KDO_SLP:
+            ret = DRVPDN_MDL1AO_STS(C2KDO_SLP_CG);
+            break;
+        case PDN_C2K1X_TMR:
+            ret = DRVPDN_MDL1AO_STS(C2K1X_TMR_CG);
+            break;
+        case PDN_C2K1X_SLP:
+            ret = DRVPDN_MDL1AO_STS(C2K1X_SLP_CG);
+            break;
+        case PDN_TDMA_SLP:
+            ret = DRVPDN_MDL1AO_STS(TDMA_SLP_CG);
+            break;
+        case PDN_TDD_TMR:
+            ret = DRVPDN_MDL1AO_STS(TDD_TMR_CG);
+            break;
+        case PDN_TDD_SLP:
+            ret = DRVPDN_MDL1AO_STS(TDD_SLP_CG);
+            break;
+        case PDN_FDD_TMR:
+            ret = DRVPDN_MDL1AO_STS(FDD_TMR_CG);
+            break;
+        case PDN_FDD_SLP:
+            ret = DRVPDN_MDL1AO_STS(FDD_SLP_CG);
+            break;
+        case PDN_LTE_TMR:
+            ret = DRVPDN_MDL1AO_STS(LTE_TMR_CG);
+            break;
+        case PDN_LTE_SLP:
+            ret = DRVPDN_MDL1AO_STS(LTE_SLP_CG);
+            break;
+        case PDN_IDC_CTRL:
+            ret = DRVPDN_MDL1AO_STS(IDC_CTRL_CG);
+            break;
+        case PDN_BPI:
+            ret = DRVPDN_MDL1AO_STS(BPI_CG);
+            break;
+        case PDN_BSI:
+            ret = DRVPDN_MDL1AO_STS(BSI_CG);
+            break;
+        case PDN_IDC_UART:
+            ret = DRVPDN_MDL1AO_STS(IDC_UART_CG);
+            break;
+        case PDN_DVFS_CTRL:
+            ret = DRVPDN_MDL1AO_STS(DVFS_CTRL_CG);
+            break;
+        case PDN_FREQM:
+            ret = DRVPDN_MDL1AO_STS(FREQM_CG);
+            break;
+        case PDN_C1X_TTR:
+            ret = DRVPDN_MDL1AO_STS(C1X_TTR_CG);
+            break;
+        case PDN_CDO_TTR:
+            ret = DRVPDN_MDL1AO_STS(CDO_TTR_CG);
+            break;
+        case PDN_MM_EVENTGEN:
+            ret = DRVPDN_MDL1AO_STS(MM_EVENTGEN_CG);
+            break;
+        case PDN_CDO_EVENTGEN:
+            ret = DRVPDN_MDL1AO_STS(CDO_EVENTGEN_CG);
+            break;
+        case PDN_C1X_EVENTGEN:
+            ret = DRVPDN_MDL1AO_STS(C1X_EVENTGEN_CG);
+            break;
+        case PDN_TDD_EVENTGEN:
+            ret = DRVPDN_MDL1AO_STS(TDD_EVENTGEN_CG);
+            break;
+        case PDN_FDD_EVENTGEN:
+            ret = DRVPDN_MDL1AO_STS(FDD_EVENTGEN_CG);
+            break;
+        case PDN_LTE_EVENTGEN:
+            ret = DRVPDN_MDL1AO_STS(LTE_EVENTGEN_CG);
+            break;
+        case PDN_MDL1_SLP_CTRL:
+            ret = DRVPDN_MDL1AO_STS(MDL1_SLP_CTRL_CG);
+            break;
+        case PDN_UCNT_D_TOP:
+            ret = DRVPDN_MDL1AO_STS(UCNT_D_TOP_CG);
+            break;
+        case PDN_NR_TIMER:
+            ret = DRVPDN_MDL1AO_STS(NR_TIMER_CG);
+            break;
+        case PDN_NR_SLP:
+            ret = DRVPDN_MDL1AO_STS(NR_SLP_CG);
+            break;
+        case PDN_NR_EVENTGEN:
+            ret = DRVPDN_MDL1AO_STS(NR_EVENTGEN_CG);
+            break;
+        case PDN_DIGRF_MIPI:
+            ret = DRVPDN_MDL1AO_STS(DIGRF_MIPI_CG);
+            break;
+        case PDN_RF_SLP_CTRL:
+            ret = DRVPDN_MDL1AO_STS(RF_SLP_CTRL_CG);
+            break;
+
+        #if defined(PDN_ASM_PDAMON_SUPPORT)
+        /* IA DEBUG PERI MISC */
+        case PDN_RG_ASM_CK:
+            ret = DRVPDN_DEBUG_PERI_MISC_STS(RG_ASM_CK);
+            break;
+        case PDN_RG_PDA_MON_CK:
+            ret = DRVPDN_DEBUG_PERI_MISC_STS(RG_PDA_MON_CK);
+            break;
+        #endif
+
+        case PDN_MAX_DEV:
+            break;
+    }
+        
+    return ret;
+}
+
+#endif /* DISABLE_PDN_FOR_ISSUE */
+
+
+#endif /* !__DRVPDN_INLINE_MT6297_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/drvpdn_inline_username.h b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_username.h
new file mode 100644
index 0000000..93f0efa
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_username.h
@@ -0,0 +1,77 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   drvpdn_inline_username.h
+ *
+ * Project:
+ * --------
+ *   UMOLY
+ *
+ * Description:
+ * ------------
+ * remap user name to PDN spec name
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 11 23 2016 devin.yang
+ * [MOLY00204129] [System Service][PDN] Porting PDN drivers for MT6293.
+ * Update MT6293 PDN driver.
+ *
+ * 11 23 2016 devin.yang
+ * [MOLY00204129] [System Service][PDN] Porting PDN drivers for MT6293.
+ * Update MT6293 PDN driver.
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __DRVPDN_INLINE_USERNAME_H__
+#define __DRVPDN_INLINE_USERNAME_H__
+
+// SE7/SD6 Way Chen
+#define PDN_GPT PDN_MDGPTM
+
+// SE7/SD9 Yuke Ren
+#define PDN_UART0 PDN_MDUART0
+#define PDN_UART1 PDN_MDUART1
+
+#endif /* !__DRVPDN_INLINE_USERNAME_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6293_series.h b/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6293_series.h
new file mode 100644
index 0000000..318f4f2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6293_series.h
@@ -0,0 +1,155 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   pdn_hw_mt6293_series.h
+ *
+ * Project:
+ * --------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   PDN Driver Related HW Registers
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 10 2017 devin.yang
+ * [MOLY00269905] [System Service][PDN][Gen93][UMOLYA][LR12A.R2.MP] Update PDN driver for new module clock control.
+ * .
+ *
+ * 11 23 2016 devin.yang
+ * [MOLY00204129] [System Service][PDN] Porting PDN drivers for MT6293.
+ * Update MT6293 PDN driver.
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __PDN_HW_MT6293_SERIES_H__
+#define __PDN_HW_MT6293_SERIES_H__
+
+#include "reg_base.h"
+
+///////////////////////////////////////////////////////////////////////////////
+/// MDPERI_CLKCTL (0xA01C0000)
+///////////////////////////////////////////////////////////////////////////////
+
+#define MD_INFRA_CKEN_SET                   ((BASE_MADDR_CLK_CTRL+0x04))
+#define MD_INFRA_CKEN_CLR                   ((BASE_MADDR_CLK_CTRL+0x08))
+#define MD_INFRA_CKEN                       ((BASE_MADDR_CLK_CTRL+0x0C))
+    #define CG_MDUART1                         (1<<0)
+    #define CG_BUSMON                          (1<<2)
+    #define CG_SOE                             (1<<4)
+    #define CG_LOGTOP_BCLK                     (1<<8)
+    #define CG_MDINFRA_ELM_ACLK                (1<<10)
+    #define CG_MDINFRA_ELM_FCLK                (1<<11)
+    #define CG_MDINFRA_ELM_F26M                (1<<12)
+    #define CG_FCS_SLV_DBCLK                   (1<<15)
+    #define CG_GCU_SLV_DBCLK                   (1<<16)
+    #define CG_TRACE_BUS2X                     (1<<17)
+    #define CG_PPPHA_CLK                       (1<<18)
+    #define CG_SDF_HCLK                        (1<<19)
+    #define CG_TRACE_PIPE                      (1<<20)
+    #define CG_TRACE_LINK                      (1<<21)
+    #define CG_TRACE_SWD                       (1<<22)
+    #define CG_LOGTOP_BUS2X                    (1<<23)
+    #define CG_MDINFRA_BUS                     (1<<28)
+    #define CG_MDINFRA_ATB_CK                  (1<<30)
+    #define CG_MDINFRA_DBG_CK                  (1<<31)
+
+#define MD_PERI_CKEN_SET                    ((BASE_MADDR_CLK_CTRL+0x10))
+#define MD_PERI_CKEN_CLR                    ((BASE_MADDR_CLK_CTRL+0x14))
+#define MD_PERI_CKEN                        ((BASE_MADDR_CLK_CTRL+0x18))    
+    #define CG_MDUART0                         (1<<0)
+    #define CG_MDGDMA                          (1<<1)
+    #define CG_MDGPTM                          (1<<2)
+    #define CG_USIM1_BCLK                      (1<<4)
+    #define CG_USIM2_BCLK                      (1<<5)
+    #define CG_MDEINT                          (1<<6)
+    #define CG_USIM1                           (1<<8)
+    #define CG_USIM2                           (1<<9)
+    #define CG_MDECT                           (1<<10)
+    #define CG_MDCIRQ                          (1<<11)
+    #define CG_THERM_SLOW                      (1<<12)
+    #define CG_MDPERI_DBG                      (1<<13)
+    #define CG_TRACE_26M                       (1<<14)
+    #define CG_MDGPTM_26M                      (1<<15)
+    #define CG_MDPERI_BUS                      (1<<28)
+    #define CG_MDDBGSYS_DCM                    (1<<31)
+
+///////////////////////////////////////////////////////////////////////////////
+/// MODEML1_AO_CONFG (0xA6020000)
+///////////////////////////////////////////////////////////////////////////////
+#define MDL1AO_CON20                    ((L1_BASE_MADDR_AO_CONFG+0x50))
+#define MDL1AO_PDN_SET                  ((L1_BASE_MADDR_AO_CONFG+0x54))
+#define MDL1AO_PDN_CLR                  ((L1_BASE_MADDR_AO_CONFG+0x58)) 
+    #define CG_C2KDO_TMR                       (1<<0)
+    #define CG_C2KDO_SLP                       (1<<1)    
+    #define CG_C2K1X_TMR                       (1<<2)
+    #define CG_C2K1X_SLP                       (1<<3)  
+    #define CG_TDMA_SLP                        (1<<4)
+    #define CG_TDD_TMR                         (1<<5)    
+    #define CG_TDD_SLP                         (1<<6)
+    #define CG_FDD_TMR                         (1<<7)    
+    #define CG_FDD_SLP                         (1<<8)
+    #define CG_LTE_TMR                         (1<<9)    
+    #define CG_LTE_SLP                         (1<<10)
+    #define CG_IDC_CTRL                        (1<<11)
+    #define CG_BPI                             (1<<12)    
+    #define CG_BSI                             (1<<13)
+    #define CG_IDC_UART                        (1<<14) 
+    #define CG_DVFS_CTRL                       (1<<15)   
+    #define CG_FREQM                           (1<<16)
+    #define CG_C1X_TTR                         (1<<17)    
+    #define CG_CDO_TTR                         (1<<18)
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// IA_DEBUG_PERI_MISC (0xA0230000)
+///////////////////////////////////////////////////////////////////////////////
+#define IA_DEBUG_PERI_MISC_CLK_CTRL            ((BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF+0x4))
+    #define CG_RG_ASM_CK                       (1<<0)
+    #define CG_RG_PDA_MON_CK                   (1<<1) 
+
+   
+#endif  /* !__PDN_HW_ELBRUS_SERIES_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6295_series.h b/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6295_series.h
new file mode 100644
index 0000000..7276d28
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6295_series.h
@@ -0,0 +1,168 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   pdn_hw_mt6295_series.h
+ *
+ * Project:
+ * --------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   PDN Driver Related HW Registers
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 06 29 2018 devin.yang
+ * [MOLY00336176] [System Service] [PDN] [Gen95] Fix PDN driver potential bug.
+ * Comment out ASM and PDAmon PDN driver.
+ *
+ * 09 22 2017 devin.yang
+ * [MOLY00244578] [System Service][MT6295M][PDN] Update PDN driver for MT6295M.
+ * Using atomic operation for ASM/PDAmon clock control instead of spinlock.
+ *
+ * 08 09 2017 devin.yang
+ * [MOLY00244578] [System Service][MT6295M][PDN] Update PDN driver for MT6295M.
+ * .
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __PDN_HW_MT6295_SERIES_H__
+#define __PDN_HW_MT6295_SERIES_H__
+
+#include "reg_base.h"
+
+///////////////////////////////////////////////////////////////////////////////
+/// MDPERI_CLKCTL (0xA01C0000)
+///////////////////////////////////////////////////////////////////////////////
+#define MD_INFRA_CKEN_SET                      ((BASE_MADDR_CLK_CTRL+0x04))
+#define MD_INFRA_CKEN_CLR                      ((BASE_MADDR_CLK_CTRL+0x08))
+#define MD_INFRA_CKEN                          ((BASE_MADDR_CLK_CTRL+0x0C))
+    #define MDUART1_CK                         (1<<0)
+    #define BUSMON_CK                          (1<<2)
+    #define SOE_CK                             (1<<4)
+    #define LOGTOP_BCLK_CK                     (1<<8)
+    #define MDINFRA_ELM_ACLK_CK                (1<<10)
+    #define MDINFRA_ELM_FCLK_CK                (1<<11)
+    #define MDINFRA_ELM_F26M_CK                (1<<12)
+    #define FCS_SLV_DBCLK_CK                   (1<<15)
+    #define TRACE_BUS2X_CK                     (1<<17)
+    #define PPPHA_CLK_CK                       (1<<18)
+    #define SDF_HCLK_CK                        (1<<19)
+    #define TRACE_PIPE_CK                      (1<<20)
+    #define TRACE_SWD_CK                       (1<<21)
+    #define I2C_BCLK_CK                        (1<<22)
+    #define LOGTOP_BUS2X_CK                    (1<<23)
+    #define MDINFRA_BUS_CG                     (1<<28)
+    #define MDINFRA_ATB_CK                     (1<<30)
+    #define MDINFRA_DBG_CK                     (1<<31)
+
+#define MD_PERI_CKEN_SET                       ((BASE_MADDR_CLK_CTRL+0x10))
+#define MD_PERI_CKEN_CLR                       ((BASE_MADDR_CLK_CTRL+0x14))
+#define MD_PERI_CKEN                           ((BASE_MADDR_CLK_CTRL+0x18))    
+    #define MDUART0_CK                         (1<<0)
+    #define MDGDMA_CK                          (1<<1)
+    #define MDGPTM_CK                          (1<<2)
+    #define USIM1_BCLK_CK                      (1<<4)
+    #define USIM2_BCLK_CK                      (1<<5)
+    #define MDEINT_CK                          (1<<6)
+    #define LOW_PWR_DBG_MON_CK                 (1<<7)
+    #define USIM1_CK                           (1<<8)
+    #define USIM2_CK                           (1<<9)
+    #define MDECT_CK                           (1<<10)
+    #define MDCIRQ_CK                          (1<<11)
+    #define THERM_SLOW_CK                      (1<<12)
+    #define MDPERI_DBG_CK                      (1<<13)
+    #define TRACE_26M_CK                       (1<<14)
+    #define MDGPTM_26M_CK                      (1<<15)
+    #define MDPERI_BUS_CG                      (1<<28)
+    #define MDDBGSYS_BUS_CK                    (1<<31)
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// MODEML1_AO_CONFG (0xA6020000)
+///////////////////////////////////////////////////////////////////////////////
+#define MDL1AO_CON20                           ((L1_BASE_MADDR_AO_CONFG+0x50))
+#define MDL1AO_PDN_SET                         ((L1_BASE_MADDR_AO_CONFG+0x54))
+#define MDL1AO_PDN_CLR                         ((L1_BASE_MADDR_AO_CONFG+0x58)) 
+    #define C2KDO_TMR_CK                       (1<<0)
+    #define C2KDO_SLP_CK                       (1<<1)    
+    #define C2K1X_TMR_CK                       (1<<2)
+    #define C2K1X_SLP_CK                       (1<<3)  
+    #define TDMA_SLP_CK                        (1<<4)
+    #define TDD_TMR_CK                         (1<<5)    
+    #define TDD_SLP_CK                         (1<<6)
+    #define FDD_TMR_CK                         (1<<7)    
+    #define FDD_SLP_CK                         (1<<8)
+    #define LTE_TMR_CK                         (1<<9)    
+    #define LTE_SLP_CK                         (1<<10)
+    #define IDC_CTRL_CK                        (1<<11)
+    #define BPI_CK                             (1<<12)    
+    #define BSI_CK                             (1<<13)
+    #define IDC_UART_CK                        (1<<14) 
+    #define DVFS_CTRL_CK                       (1<<15)   
+    #define FREQM_CK                           (1<<16)
+    #define C1X_TTR_CK                         (1<<17)    
+    #define CDO_TTR_CK                         (1<<18)
+    #define MM_EVENTGEN_CK                     (1<<19)
+    #define CDO_EVENTGEN_CK                    (1<<20)
+    #define C1X_EVENTGEN_CK                    (1<<21)
+    #define TDD_EVENTGEN_CK                    (1<<22)
+    #define FDD_EVENTGEN_CK                    (1<<23)
+    #define LTE_EVENTGEN_CK                    (1<<24)
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+///////////////////////////////////////////////////////////////////////////////
+/// IA_DEBUG_PERI_MISC (0xA0230000)
+///////////////////////////////////////////////////////////////////////////////
+#define IA_DEBUG_PERI_MISC_CLK_CTRL            ((BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF+0x4))
+    #define RG_ASM_CK                          (1<<0)
+    //#define RG_ASM_CK                          (0)
+    #define RG_PDA_MON_CK                      (1<<1) 
+    //#define RG_PDA_MON_CK                      (1) 
+#endif
+
+   
+#endif  /* !__PDN_HW_ELBRUS_SERIES_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6297_series.h b/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6297_series.h
new file mode 100644
index 0000000..4c015cd
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6297_series.h
@@ -0,0 +1,170 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2012
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   pdn_hw_mt6297_series.h
+ *
+ * Project:
+ * --------
+ *   UMOLYE
+ *
+ * Description:
+ * ------------
+ *   PDN Driver Related HW Registers
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 06 29 2018 devin.yang
+ * [MOLY00336176] [System Service] [PDN] [Gen95] Fix PDN driver potential bug.
+ * Comment out ASM and PDAmon PDN driver.
+ *
+ * 09 22 2017 devin.yang
+ * [MOLY00244578] [System Service][MT6295M][PDN] Update PDN driver for MT6295M.
+ * Using atomic operation for ASM/PDAmon clock control instead of spinlock.
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __PDN_HW_MT6297_SERIES_H__
+#define __PDN_HW_MT6297_SERIES_H__
+
+#include "reg_base.h"
+
+/*
+ * MDPERI_CLKCTL (0xA01C0000)
+ */
+#define MD_INFRA_CKEN_SET                      ((BASE_MADDR_CLK_CTRL+0x04))
+#define MD_INFRA_CKEN_CLR                      ((BASE_MADDR_CLK_CTRL+0x08))
+#define MD_INFRA_CKEN                          ((BASE_MADDR_CLK_CTRL+0x0C))
+    #define MDUART1_CK                         (1<<0)
+    #define BUSMON_CK                          (1<<2)
+    #define SOE_CK                             (1<<4)
+    #define LOGTOP_BCLK_CK                     (1<<8)
+    #define MDINFRA_ELM_ACLK_CK                (1<<10)
+    #define MDINFRA_ELM_FCLK_CK                (1<<11)
+    #define MDINFRA_ELM_F26M_CK                (1<<12)
+    #define TRACE_BUS2X_CK                     (1<<17)
+    #define PPPHA_CLK_CK                       (1<<18)
+    #define SDF_HCLK_CK                        (1<<19)
+    #define TRACE_PIPE_CK                      (1<<20)
+    #define TRACE_SWD_CK                       (1<<21)
+    #define I2C_BCLK_CK                        (1<<22)
+    #define LOGTOP_BUS2X_CK                    (1<<23)
+    #define SDF_ATB_CPHY_CK                    (1<<27)
+    #define MDINFRA_BUS_CG                     (1<<28)
+    #define TRACE_ATB_CPHY_CK                  (1<<29)
+    #define MDINFRA_ATB_CK                     (1<<30)
+    #define MDINFRA_DBG_CK                     (1<<31)
+
+#define MD_PERI_CKEN_SET                       ((BASE_MADDR_CLK_CTRL+0x10))
+#define MD_PERI_CKEN_CLR                       ((BASE_MADDR_CLK_CTRL+0x14))
+#define MD_PERI_CKEN                           ((BASE_MADDR_CLK_CTRL+0x18))    
+    #define MDUART0_CK                         (1<<0)
+    #define MDGDMA_CK                          (1<<1)
+    #define MDGPTM_CK                          (1<<2)
+    #define MDGDMA_FORDSP_CK                   (1<<3)
+    #define USIM1_BCLK_CK                      (1<<4)
+    #define USIM2_BCLK_CK                      (1<<5)
+    #define MDEINT_CK                          (1<<6)
+    #define LOW_PWR_DBG_MON_CK                 (1<<7)
+    #define USIM1_CK                           (1<<8)
+    #define USIM2_CK                           (1<<9)
+    #define MDECT_CK                           (1<<10)
+    #define MDCIRQ_CK                          (1<<11)
+    #define THERM_SLOW_CK                      (1<<12)
+    #define MDPERI_DBG_CK                      (1<<13)
+    #define TRACE_26M_CK                       (1<<14)
+    #define MDGPTM_26M_CK                      (1<<15)
+    #define MDPERI_BUS_CG                      (1<<28)
+    #define MDDBGSYS_BUS_CK                    (1<<31)
+
+/*
+ * MODEML1_AO_CONFG (0xA8020000)
+ */
+#define MDL1AO_CON20                           ((L1_BASE_MADDR_AO_CONFG+0x50))
+#define MDL1AO_PDN_SET                         ((L1_BASE_MADDR_AO_CONFG+0x54))
+#define MDL1AO_PDN_CLR                         ((L1_BASE_MADDR_AO_CONFG+0x58)) 
+    #define C2KDO_TMR_CG                       (1<<0)
+    #define C2KDO_SLP_CG                       (1<<1)    
+    #define C2K1X_TMR_CG                       (1<<2)
+    #define C2K1X_SLP_CG                       (1<<3)  
+    #define TDMA_SLP_CG                        (1<<4)
+    #define TDD_TMR_CG                         (1<<5)    
+    #define TDD_SLP_CG                         (1<<6)
+    #define FDD_TMR_CG                         (1<<7)    
+    #define FDD_SLP_CG                         (1<<8)
+    #define LTE_TMR_CG                         (1<<9)    
+    #define LTE_SLP_CG                         (1<<10)
+    #define IDC_CTRL_CG                        (1<<11)
+    #define BPI_CG                             (1<<12)    
+    #define BSI_CG                             (1<<13)
+    #define IDC_UART_CG                        (1<<14) 
+    #define DVFS_CTRL_CG                       (1<<15)   
+    #define FREQM_CG                           (1<<16)
+    #define C1X_TTR_CG                         (1<<17)    
+    #define CDO_TTR_CG                         (1<<18)
+    #define MM_EVENTGEN_CG                     (1<<19)
+    #define CDO_EVENTGEN_CG                    (1<<20)
+    #define C1X_EVENTGEN_CG                    (1<<21)
+    #define TDD_EVENTGEN_CG                    (1<<22)
+    #define FDD_EVENTGEN_CG                    (1<<23)
+    #define LTE_EVENTGEN_CG                    (1<<24)
+    #define MDL1_SLP_CTRL_CG                   (1<<25)
+    #define UCNT_D_TOP_CG                      (1<<26)
+    #define NR_TIMER_CG                        (1<<27)
+    #define NR_SLP_CG                          (1<<28)
+    #define NR_EVENTGEN_CG                     (1<<29)
+    #define DIGRF_MIPI_CG                      (1<<30)
+    #define RF_SLP_CTRL_CG                     (1<<31)
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+/*
+ *  IA_DEBUG_PERI_MISC (0xA0230000)
+ */
+#define IA_DEBUG_PERI_MISC_CLK_CTRL            ((BASE_MADDR_MDMCU_IA_MACRO_MISC_REG+0x4))
+    #define RG_ASM_CK                          (1<<0)
+    #define RG_PDA_MON_CK                      (1<<1) 
+#endif
+
+   
+#endif  /* !__PDN_HW_MT6297_SERIES_H__ */
diff --git a/mcu/interface/driver/devdrv/pll/pll.h b/mcu/interface/driver/devdrv/pll/pll.h
new file mode 100644
index 0000000..16e17c7
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pll/pll.h
@@ -0,0 +1,141 @@
+/*******************************************************************************
+ *  Copyright Statement:
+ *  --------------------
+ *  This software is protected by Copyright and the information contained
+ *  herein is confidential. The software may not be copied and the information
+ *  contained herein may not be used or disclosed except with the written
+ *  permission of MediaTek Inc. (C) 2012
+ *
+ *  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ *  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ *  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ *  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ *  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ *  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ *  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ *  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ *  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ *  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ *  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ *  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ *  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ *  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ *  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ *  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ *  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ *  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ *  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ *  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ *  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   pll.h
+ *
+ * Project:
+ * --------
+ *   UMOLYE
+ *
+ * Description:
+ * ------------
+ *   PLL Related Functions
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ============================================================================
+ * $Log$
+ *
+ * 07 31 2019 jun-ying.huang
+ * [MOLY00425097] [VMOLY][FMA]Add __MD97P__ for Mercury build pass
+ * .
+ *
+ * 03 01 2018 jun-ying.huang
+ * [MOLY00310598] [95/97 re-arch]PLL co-branch for MT6295 & MT6297
+ * Add PLL for 97 - Only for Build pass, function and driver is not ready.
+ *
+ * 12 11 2017 jun-ying.huang
+ * [MOLY00295410] [PLL][MT3967] Add Macro for MT3967
+ * .
+ *
+ * 10 25 2017 jun-ying.huang
+ * [MOLY00285159] [PLL][DCM]Add Macro for MT6765(=Cervino)
+ * .
+ *
+ * 10 02 2017 jun-ying.huang
+ * [MOLY00281611] [93/95 re-arch]PLL co-branch for MT6293 & MT6295
+ * .
+ *
+ * 09 01 2017 jun-ying.huang
+ * [MOLY00275084] [6293]Add PLL_SEC Module related code to get SW version.
+ * .
+ *
+ * 08 21 2017 jun-ying.huang
+ * [MOLY00272509] [Sylvia][PLL]Add MT6771 Macro for PLL due to Sylvia MT6771 Call for check in
+ * .
+ *
+ * 06 09 2017 jun-ying.huang
+ * [MOLY00244484] [Zion]Add compile option for ZION in PLL.
+ * Add compile option for ZION and Workaround for CIRQ APB sync issue- Let BUS2x clock use MDBPIPLL_0/6 = 101 MHz
+ *
+ * 10 24 2016 jun-ying.huang
+ * [MOLY00209150] [System Service][PLL]Remove redundant files from UMOLYA PLL
+ * Remove redundant files from PLL
+ *
+ * 06 24 2016 alan-tl.lin
+ * [MOLY00173527] [PLL] Driver porting
+ * Fix build error
+ *
+ * 06 15 2016 alan-tl.lin
+ * [MOLY00173527] [PLL] Driver porting
+ * [PLL] PLL init first porting
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __PLL_H__
+#define __PLL_H__
+
+/*******************************************************************************
+ * Locally Used Options
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include header files
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "reg_base.h"
+
+#if defined(__MD93__)
+    #include "pll_gen93m17.h"
+#elif defined(__MD95__)
+    #include "pll_gen95.h"
+#elif defined(__MD97__)
+    #include "pll_gen97.h" 
+#elif defined(__MD97P__) 
+    #include "pll_gen97p.h"
+#else
+    #error "ERROR in PLL define (pll.h)"
+#endif
+
+/*******************************************************************************
+ * Define exported macro
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Define data structure
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Define exported function prototype
+ ******************************************************************************/
+extern void INT_SetPLL(void);
+
+#endif  /* !__PLL_H__ */
diff --git a/mcu/interface/driver/devdrv/pll/pll_gen93m17.h b/mcu/interface/driver/devdrv/pll/pll_gen93m17.h
new file mode 100644
index 0000000..1162dc6
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pll/pll_gen93m17.h
@@ -0,0 +1,478 @@
+/*******************************************************************************
+ *  Copyright Statement:
+ *  --------------------
+ *  This software is protected by Copyright and the information contained
+ *  herein is confidential. The software may not be copied and the information
+ *  contained herein may not be used or disclosed except with the written
+ *  permission of MediaTek Inc. (C) 2012
+ *
+ *  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ *  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ *  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ *  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ *  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ *  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ *  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ *  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ *  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ *  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ *  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ *  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ *  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ *  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ *  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ *  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ *  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ *  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ *  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ *  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ *  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   pll_gen93m17.h
+ *
+ * Project:
+ * --------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   PLL Related Functions
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ============================================================================
+ * $Log$
+ *
+ * 01 22 2018 jun-ying.huang
+ * [MOLY00303289] [Merlot call for check-in][PLL][DCM]Add Macro for MT6761(=Merlot)
+ * .
+ *
+ * 10 25 2017 jun-ying.huang
+ * [MOLY00285159] [PLL][DCM]Add Macro for MT6765(=Cervino)
+ * .
+ *
+ * 10 02 2017 jun-ying.huang
+ * [MOLY00281611] [93/95 re-arch]PLL co-branch for MT6293 & MT6295
+ * .
+ *
+ * 08 21 2017 jun-ying.huang
+ * [MOLY00272509] [Sylvia][PLL]Add MT6771 Macro for PLL due to Sylvia MT6771 Call for check in
+ * .
+ *
+ * 06 09 2017 jun-ying.huang
+ * [MOLY00244484] [Zion]Add compile option for ZION in PLL.
+ * Add compile option for ZION and Workaround for CIRQ APB sync issue- Let BUS2x clock use MDBPIPLL_0/6 = 101 MHz
+ *
+ * 12 16 2016 jun-ying.huang
+ * [MOLY00218782] [System service][PLL][6293]Add compile option for MT6763
+ * .
+ *
+ * 12 07 2016 jun-ying.huang
+ * [MOLY00217275] [System service][PLL][6293]Update PLL init flow and porting driver for user
+ * .
+ *
+ * 11 20 2016 jun-ying.huang
+ * [MOLY00214278] [System service][PLL][6293]Update PLL_FrequencyMeter_GetFreq() driver
+ * .
+ *
+ * 11 06 2016 jun-ying.huang
+ * [MOLY00211600] [System service][PLL]Add debug info in PLL driver
+ * .
+ *
+ * 10 14 2016 jun-ying.huang
+ * [MOLY00207095] [System service][PLL]Update PLL driver for DVFS users.
+ * Add PLL function for DVFS
+ *
+ * 09 19 2016 alan-tl.lin
+ * [MOLY00174466] [UMOLYA] PLL porting
+ * [PLL] Update register definition
+ *
+ * 08 02 2016 alan-tl.lin
+ * [MOLY00174466] [UMOLYA] PLL porting
+ * Fix build error
+ *
+ ****************************************************************************/
+
+#ifndef __PLL_MT6763_H__
+#define __PLL_MT6763_H__
+
+/*******************************************************************************
+ * Locally Used Options
+ ******************************************************************************/
+#define PLL_REG32(addr) *(volatile kal_uint32 *)(addr)
+#define PLL_TYPE        (volatile kal_uint32 *)
+
+/*******************************************************************************
+ * Define macro for boot code
+ ******************************************************************************/
+#define __SECTION__(S) __attribute__((__section__(#S)))
+#define __PLL_CODE_IN_BOOT__ __SECTION__(NONCACHED_ROCODE)
+
+/*******************************************************************************
+ * Register Define
+ ******************************************************************************/
+
+///////////////////////////////////////////////////////////////////////////////
+/// PLLMIXED (0xA0140000)
+///////////////////////////////////////////////////////////////////////////////
+/* ==========PLL setting========== */
+#define REG_MDTOP_PLLMIXED_CODA_VERSION             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x0))
+#define REG_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4))
+#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK          (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x8))
+#define REG_MDTOP_PLLMIXED_DCXO_MODE_CTL            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC))
+#define REG_MDTOP_PLLMIXED_PLL_ON_CTL               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL0              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x14))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL1              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x18))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL0             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL1             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x34))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL2             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x38))
+
+/* ==========PLL frequency control==> PCW & POSDIV========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x40))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x44))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL0           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x48))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL1           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x54))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_CTL0             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x58))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_CTL1             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x60))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x64))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL0               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x100))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL1               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x104))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL2               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x108))
+
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10C))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE2             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x110))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_RSTB             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x114))
+#define REG_MDTOP_PLLMIXED_PLL_FHCTL_RST            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x200))
+#define REG_MDTOP_PLLMIXED_CONN_DSNS_INTF           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x204))
+
+/* ==========PLL IRQ related========== */
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_IRQ    (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x300))
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_MASK   (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x304))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_IRQ      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x308))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_MASK     (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30C))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_ABNORM_STS       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x310))
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x314))
+    #define  PLLMIXED_MDMCUPLL_HP_RDY_IRQ_OFFSET   (1)
+    #define  PLLMIXED_MDVDSPPLL_HP_RDY_IRQ_OFFSET  (2)
+    #define  PLLMIXED_MDBRPPLL_HP_RDY_IRQ_OFFSET   (4)
+    #define  PLLMIXED_MDTXPLL_HP_RDY_IRQ_OFFSET    (5)
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x318))
+
+/* PLL IRQ related macro */
+#define  PLLMIXED_PLL_HP_RDY_IRQ_MASK              (0x1)/* mask bit numbers for each IRQ */
+
+/* ==========PLL FHCTL========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x400))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x404))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x408))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FHCTL          (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x410))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FRDDS_LMT      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x414))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_SW_GEAR        (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x418))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x430))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x434))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x438))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_FHCTL            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x440))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_FRDDS_LMT        (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x444))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_SW_GEAR          (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x448))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x450))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x454))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x458))
+
+/* ==========PLL Gear Set========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET0       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x500))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET1       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x504))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET2       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x508))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET3       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50C))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET0      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x540))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET1      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x544))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET2      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x548))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET3      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x54C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET0       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C0))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET1       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C4))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET2       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C8))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET3       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5CC))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET0        (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x600))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET1        (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x604))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET2        (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x608))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET3        (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x60C))
+
+/* ==========PLL Status========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC00))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_STS            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC04))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC08))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_STS              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC0C))
+#define REG_MDTOP_PLLMIXED_MDBPIBPLL_STS            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC10))
+#define REG_MDTOP_PLLMIXED_MDPLL1_STS               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC40))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY                (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF00))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY1               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF04))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY2               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF08))
+#define REG_MDTOP_PLLMIXED_PLL_STATUS               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF0C))
+
+/* PLL Status related macro */
+#define PLLMIXED_PLL_SFSTR_PRD_OFFSET           (14)
+#define PLLMIXED_PLL_SFSTR_PRD_MASK             (0x1)/* mask bit numbers for each SFSTR_PRD */
+#define PLLMIXED_PLL_SDM_PCW_OFFSET             (16)
+#define PLLMIXED_PLL_SDM_PCW_MASK               (0x7FFF)/* mask bit numbers([30:16] = 14bits) for each SDM_PCW */
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// CLKSW (0xA0150000)
+///////////////////////////////////////////////////////////////////////////////
+#define REG_MDTOP_CLKSW_CODA_VERSION	            (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x0))
+#define REG_MDTOP_CLKSW_MD_SLEEP_CNT	            (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4))
+#define REG_MDTOP_CLKSW_MDTOPSM_SW_CTL	            (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10))
+#define REG_MDTOP_CLKSW_L1TOPSM_SW_CTL	            (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x14))
+#define REG_MDTOP_CLKSW_CKOFF_CTL                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x1C))
+#define REG_MDTOP_CLKSW_CLKON_CTL                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x20))
+#define REG_MDTOP_CLKSW_CLKSEL_CTL                  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x24))
+
+/* ==========SDF clock control related========== */
+#define REG_MDTOP_CLKSW_SDF_CK_CTL                  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x28))
+#define REG_MDTOP_CLKSW_ATB_LOG_SDF_SW_CTL          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x2C))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL0             (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x30))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL1             (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x34))
+
+/* ==========FLEXCKGEN_SEL========== */
+#define REG_MDTOP_CLKSW_MDCORE_FLEXCKGEN_SEL        (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x40))
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x44))
+#define REG_MDTOP_CLKSW_VDSP_FLEXCKGEN_SEL          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x48))
+#define REG_MDTOP_CLKSW_BRP_FLEXCKGEN_SEL           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4C))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_SEL          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x50))
+#define REG_MDTOP_CLKSW_TXSYS_FLEXCKGEN_SEL         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x54))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_SEL         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x58))
+#define REG_MDTOP_CLKSW_MD2G_FLEXCKGEN_SEL          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x5C))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_SEL           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x60))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_SEL           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x64))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x68))
+
+/* ==========FLEXCKGEN_STS========== */
+#define REG_MDTOP_CLKSW_MDCORE_FLEXCKGEN_STS        (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x80))
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x84))
+#define REG_MDTOP_CLKSW_VDSP_FLEXCKGEN_STS          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x88))
+#define REG_MDTOP_CLKSW_BRP_FLEXCKGEN_STS           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x8C))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_STS          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x90))
+#define REG_MDTOP_CLKSW_TXSYS_FLEXCKGEN_STS         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x94))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_STS         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x98))
+#define REG_MDTOP_CLKSW_MD2G_FLEXCKGEN_STS          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x9C))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_STS           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA0))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_STS           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA4))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_STS       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA8))
+
+#define REG_MDTOP_CLKSW_CKMUX_STS                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC0))
+#define REG_MDTOP_CLKSW_PLL_STS	                    (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD0))
+
+/* ==========Frequency Meter========== */
+#define REG_MDTOP_CLKSW_CKMON_CTL                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x100))
+#define REG_MDTOP_CLKSW_FREQ_METER_CTL              (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x104))
+#define REG_MDTOP_CLKSW_FREQ_METER_XTAL_CNT         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x108))
+#define REG_MDTOP_CLKSW_FREQ_METER_CKMON_CNT        (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10C))
+#define REG_MDTOP_CLKSW_FREQ_METER_H                (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x110))
+#define REG_MDTOP_CLKSW_FREQ_METER_L                (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x114))
+
+/* ==========DUMMY & STATUS========== */
+#define REG_MDTOP_CLKSW_CLK_DUMMY                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF00))
+#define REG_MDTOP_CLKSW_CLK_STATUS                  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF04))
+
+
+/*******************************************************************************
+ * Define Macro
+ ******************************************************************************/
+#define MD_PLL_MAGIC_NUM 0x62930000
+
+/**
+ * PLL divider definition
+ */
+#if defined(MT6763) || defined(MT6771) || defined(MT6765) || defined(MT6761)/* BIANCO or SYLVIA or CERVINO or MERLOT */
+//    #define MDBPIPLL_DIVIDER      /4 /9 /7
+    #define MDTXPLL_DIVIDER      (8)
+    #define MDBRPPLL_DIVIDER     (9)
+    #define MDVDSPPLL_DIVIDER    (5)
+    #define MDMCUPLL_DIVIDER     (4)    
+#elif defined(MT6739)/* ZION */ 
+    #define MDTXPLL_DIVIDER      (4)
+    #define MDBRPPLL_DIVIDER     (6)
+    #define MDVDSPPLL_DIVIDER    (4)
+    #define MDMCUPLL_DIVIDER     (2)
+#else
+    #error "Unsupported Chip Target in PLL Module"
+#endif
+
+ /*------------------------------------------------------------------------
+ * Purpose:     Transfer PCW in xxxPLL_STS to Mhz. This macro is porting from md_dvfs_pll_freq_get(const PLL_SOURCE pll).
+ * Parameters:
+ *    Input:    pcw:    The PCW value in xxxPLL_STS.
+ *              divier: The divier for this PLL(EX: ICCPLL_DIVIDER, IMCPLL_DIVIDER...).
+ *    Output:   None.
+ * returns :    Mhz. 
+ * Note    :    This macr is only used to transfer pcw in xxxPLL_STS to Mhz. 
+ *              You should not used this macro to transfer pcw in xxxPLL_CTL0 to Mhz due to the meaning is different.
+ *              (PCW in xxxPLL_STS is bit [21:7] of xxxPLL_CTL0.)
+ *------------------------------------------------------------------------
+ */
+#define PLLMIXED_PLL_STS_SDM_PCW_TO_MHZ(pcw, divier)   ((((pcw) * 26) / (1 << 7)) / divier)
+
+/*******************************************************************************
+ * ENUM
+ ******************************************************************************/
+// frequency meter index list (debug only)
+typedef enum {
+    PLL_FM_SOURCE_START            = 0xA,
+    PLL_FM_TRACE_MON_CLOCK         = 0xA,
+    PLL_FM_MDSYS_208M_CLOCK        = 0xB,
+    PLL_FM_MDRXSYS_RAKE_CLOCK      = 0xC,
+    PLL_FM_MDRXSYS_BRP_CLOCK       = 0xD,
+    PLL_FM_MDRXSYS_VDSP_CLOCK      = 0xE,
+    PLL_FM_MDTOP_LOG_GTB_CLOCK     = 0xF,
+    PLL_FM_FESYS_CSYS_CLOCK        = 0x10,
+    PLL_FM_FESYS_TXSYS_CLOCK       = 0x11,
+    PLL_FM_FESYS_BSI_CLOCK         = 0x12, 
+    PLL_FM_MDSYS_MDCORE_CLOCK      = 0x13, 
+    PLL_FM_MDSYS_BUS2X_NODCM_CLOCK = 0x14, 
+    PLL_FM_MDSYS_BUS2X_CLOCK       = 0x15,
+    PLL_FM_MDTOP_DBG_CLOCK         = 0x16,
+    PLL_FM_MDTOP_F32K_CLOCK        = 0x17,
+    PLL_FM_MDBPI_PLL_0_DIV2        = 0x18,
+    PLL_FM_MDBPI_PLL_2             = 0x19,
+    PLL_FM_MDBPI_PLL_1             = 0x1A,
+    PLL_FM_MDBPI_PLL_0             = 0x1B,
+    PLL_FM_MDTX_PLL                = 0x1C,
+    PLL_FM_MDBRP_PLL               = 0x1D,
+    PLL_FM_MDVDSP_PLL              = 0x1E,
+    PLL_FM_MDMCU_PLL               = 0x1F,
+    PLL_FM_SOURCE_END              = 0x1F    
+} PLL_FM_SOURCE;
+
+typedef enum {
+    PLL_MDPLL1    = 0,
+    PLL_MDMCU     = 1,   
+    PLL_MDVDSP    = 2,  
+    PLL_MDBRP     = 3,   
+    PLL_MDTX      = 4,    
+    PLL_MDBPI     = 5,
+    PLL_END,
+} PLL_SOURCE;
+
+typedef enum {
+    CLKSW_FLEXCKGEN_START    = 0,
+    MDCORE_FLEXCKGEN    = 0,
+    MDSYS_BUS_FLEXCKGEN = 1,
+    VDSP_FLEXCKGEN      = 2,
+    BRP_FLEXCKGEN       = 3,
+    RAKE_FLEXCKGEN      = 4,    
+    TXSYS_FLEXCKGEN     = 5,
+    CSSYS_FLEXCKGEN     = 6,
+    MD2G_FLEXCKGEN      = 7,   
+    BSI_FLEXCKGEN       = 8,
+    DBG_FLEXCKGEN       = 9,
+    LOG_ATB_FLEXCKGEN  = 10,
+    CLKSW_FLEXCKGEN_END    
+} PLL_CLKSW_FLEXCKGEN;
+
+typedef enum {
+    CLKSW_FLEXCKGEN_DIV_1    = 0,
+    CLKSW_FLEXCKGEN_DIV_2    = 1,
+    CLKSW_FLEXCKGEN_DIV_3    = 2,
+    CLKSW_FLEXCKGEN_DIV_4    = 3,
+    CLKSW_FLEXCKGEN_DIV_5    = 4,    
+    CLKSW_FLEXCKGEN_DIV_6    = 5,
+    CLKSW_FLEXCKGEN_DIV_7    = 6,
+    CLKSW_FLEXCKGEN_DIV_8    = 7   
+} PLL_CLKSW_FLEXCKGEN_DIV;
+
+typedef enum {
+    CLKSW_FLEXCKGEN_PLL_SRC_0    = 0,
+    CLKSW_FLEXCKGEN_PLL_SRC_1    = 1,
+    CLKSW_FLEXCKGEN_PLL_SRC_2    = 2,
+    CLKSW_FLEXCKGEN_PLL_SRC_3    = 3  
+} PLL_CLKSW_FLEXCKGEN_PLL_SRC;
+
+typedef enum {
+    CLKSW_MDTOPSM_DBG_CK = 3,
+} PLL_CLKSW_MDTOPSM_SW_CTL_SRC;
+
+typedef enum {
+    CLKSW_SDF_SRC_BPIPLL_DIV8 = 0,
+    CLKSW_SDF_SRC_BPIPLL_DIV4 = 1,        
+    CLKSW_SDF_SRC_BPIPLL      = 2,  
+    CLKSW_SDF_SRC_BPIPLL_DIV2 = 3, 
+    /*CLKSW_SDF_SRC_USB_PhyLink = 4,*/ /* HW didn't support. */ 
+    CLKSW_SDF_SRC_26M,    
+    CLKSW_SDF_SRC_END    
+} PLL_CLKSW_SDF_SRC;
+
+/* Below for debugging */
+
+#define PLL_FM_NUM 30   /* Note: This number should also sync to EE owner. */
+typedef struct {
+    kal_uint32 clock_trace_mon;         /* 0 */
+    kal_uint32 clock_mdsys_208m;
+    kal_uint32 clock_mdrxsys_rake;
+    kal_uint32 clock_mdrxsys_brp;
+    kal_uint32 clock_mdrxsys_vdsp;
+    kal_uint32 clock_mdtop_log_gtb;     /* 5 */
+    kal_uint32 clock_fesys_csys;
+    kal_uint32 clock_fesys_txsys;
+    kal_uint32 clock_fesys_bsi;
+    kal_uint32 clock_mdsys_mdcore;
+    kal_uint32 clock_mdsys_bus2x_nodcm; /* 10 */
+    kal_uint32 clock_mdsys_bus2x;
+    kal_uint32 clock_mdtop_dbg;
+    kal_uint32 clock_mdtop_f32k;
+    kal_uint32 pll_MDBPI0_div2;    
+    kal_uint32 pll_MDBPI2;              /* 15 */
+    kal_uint32 pll_MDBPI1;
+    kal_uint32 pll_MDBPI0;
+    kal_uint32 pll_MDTX;
+    kal_uint32 pll_MDBRP;
+    kal_uint32 pll_MDVDSP;              /* 20 */
+    kal_uint32 pll_MDMCU;
+/* below no use */     
+    kal_uint32 NULL_22;
+    kal_uint32 NULL_23;
+    kal_uint32 NULL_24;   
+    kal_uint32 NULL_25;
+    kal_uint32 NULL_26;    
+    kal_uint32 NULL_27;
+    kal_uint32 NULL_28; 
+    kal_uint32 NULL_29;    
+} PLL_CLK_INFO;
+
+extern PLL_CLK_INFO g_pll_info;
+extern const char PLL_FM_clock[PLL_FM_NUM][32];
+
+/* Above for debugging */
+
+/*******************************************************************************
+ * Include header files
+ ******************************************************************************/
+extern void PLL_exception_dump(void);
+
+extern kal_uint32 PLL_FrequencyMeter_GetFreq(PLL_FM_SOURCE index);
+
+extern kal_bool PLL_PLLMIXED_PLL_ON_CTL(PLL_SOURCE pll, kal_bool force_on);
+
+extern void PLL_CLKSW_FLEXCKGEN_SEL_PLLSEL_Set(PLL_CLKSW_FLEXCKGEN module, PLL_CLKSW_FLEXCKGEN_PLL_SRC pll_sel);		
+extern void PLL_CLKSW_FLEXCKGEN_SEL_DIVSEL_Set(PLL_CLKSW_FLEXCKGEN module, PLL_CLKSW_FLEXCKGEN_DIV div_sel);
+extern void PLL_CLKSW_FLEXCKGEN_SEL_Get(PLL_CLKSW_FLEXCKGEN module, kal_uint32 *pll_sel, kal_uint32 *div_sel);
+extern void PLL_CLKSW_FLEXCKGEN_STS_Get(PLL_CLKSW_FLEXCKGEN module, kal_uint32 *ck_rdy, kal_uint32 *ckgen_state, kal_uint32 *pll_req);
+extern kal_bool PLL_CLKSW_MDTOPSM_SW_CTL(PLL_CLKSW_MDTOPSM_SW_CTL_SRC module, kal_bool force_on);
+
+extern kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Get();
+extern kal_bool PLL_CLKSW_SDF_SRC_CKSEL_Set(PLL_CLKSW_SDF_SRC src_ck);
+extern void PLL_CLKSW_SDF_CK_Req(kal_bool clk_req);
+
+#endif  /* !__PLL_MT6763_H__ */
+
diff --git a/mcu/interface/driver/devdrv/pll/pll_gen95.h b/mcu/interface/driver/devdrv/pll/pll_gen95.h
new file mode 100644
index 0000000..9857dcb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pll/pll_gen95.h
@@ -0,0 +1,448 @@
+/*******************************************************************************
+ *  Copyright Statement:
+ *  --------------------
+ *  This software is protected by Copyright and the information contained
+ *  herein is confidential. The software may not be copied and the information
+ *  contained herein may not be used or disclosed except with the written
+ *  permission of MediaTek Inc. (C) 2012
+ *
+ *  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ *  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ *  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ *  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ *  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ *  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ *  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ *  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ *  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ *  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ *  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ *  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ *  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ *  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ *  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ *  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ *  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ *  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ *  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ *  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ *  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   pll_gen95.h
+ *
+ * Project:
+ * --------
+ *   UMOLYA
+ *
+ * Description:
+ * ------------
+ *   PLL Related Functions
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ============================================================================
+ * $Log$
+ *
+ * 07 25 2018 jun-ying.huang
+ * [MOLY00342276] [MT6779]Add MT6779 macro for LATIFE
+ * .
+ *
+ * 05 30 2018 jun-ying.huang
+ * [MOLY00325066] [MT3967][PLL]Update PLL golden setting
+ * Remove redundant define
+ *
+ * 05 16 2018 jun-ying.huang
+ * [MOLY00325066] [MT3967][PLL]Update PLL golden setting
+ * Update 26M settle time and remove redundant function.
+ *
+ * 12 11 2017 jun-ying.huang
+ * [MOLY00295410] [PLL][MT3967] Add Macro for MT3967
+ * .
+ *
+ * 10 30 2017 jun-ying.huang
+ * [MOLY00286084] [MT6295][PLL] Update BR_EXT section for BootRom
+ * .
+ *
+ * 08 29 2017 jun-ying.huang
+ * [MOLY00261263] [MT6295M]Update PLL driver
+ * Add PLL driver for BootRom
+ *
+ * 07 10 2017 jun-ying.huang
+ * [MOLY00261263] [MT6295M]Update PLL driver
+ * 1st version for MT6295M=EIGER
+ *
+ * 05 23 2017 jun-ying.huang
+ * [MOLY00244448] [MT6295M]Update PLL driver for MT6295M
+ * Fix build error
+ *
+ * 05 15 2017 jun-ying.huang
+ * [MOLY00244448] [MT6295M]Update PLL driver for MT6295M
+ * .
+ *
+ * 04 28 2017 jun-ying.huang
+ * [MOLY00244448] [MT6295M]Update PLL driver for MT6295M
+ * temp driver for 6295
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __PLL_MT6295_H__
+#define __PLL_MT6295_H__
+
+/*******************************************************************************
+ * Locally Used Options
+ ******************************************************************************/
+#define PLL_REG32(addr) *(volatile kal_uint32 *)(addr)
+#define PLL_TYPE        (volatile kal_uint32 *)
+
+/*******************************************************************************
+ * Define macro for boot code
+ ******************************************************************************/
+#define __SECTION__(S) __attribute__((__section__(#S)))
+#define __PLL_CODE_IN_BOOT__ __SECTION__(BR_EXT)/* "BR_EXT" section for bootROM */
+
+/*******************************************************************************
+ * Register Define
+ ******************************************************************************/
+
+///////////////////////////////////////////////////////////////////////////////
+/// PLLMIXED (0xA0140000)
+///////////////////////////////////////////////////////////////////////////////
+/* ==========PLL setting========== */
+#define REG_MDTOP_PLLMIXED_CODA_VERSION             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x0))
+#define REG_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4))
+#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK          (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x8))
+#define REG_MDTOP_PLLMIXED_DCXO_MODE_CTL            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC))
+#define REG_MDTOP_PLLMIXED_PLL_ON_CTL               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL0              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x14))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL1              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x18))
+#define REG_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x1C))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL0             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL1             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x34))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL2             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x38))
+
+/* ==========PLL frequency control==> PCW & POSDIV========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x40))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x44))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL0           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x48))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL1           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x54))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_CTL0             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x58))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_CTL1             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x60))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x64))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL0               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x100))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL1               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x104))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL2               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x108))
+
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10C))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE2             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x110))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_RSTB             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x114))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_EN               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x118))
+#define REG_MDTOP_PLLMIXED_PLL_SRC_SEL              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x120))
+#define REG_MDTOP_PLLMIXED_PLL_FHCTL_RST            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x200))
+//#define REG_MDTOP_PLLMIXED_CONN_DSNS_INTF           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x204))
+
+/* ==========PLL IRQ related========== */
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_IRQ    (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x300))
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_MASK   (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x304))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_IRQ      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x308))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_MASK     (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30C))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_ABNORM_STS       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x310))
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x314))
+    #define  PLLMIXED_MDMCUPLL_HP_RDY_IRQ_OFFSET   (1)
+    #define  PLLMIXED_MDVDSPPLL_HP_RDY_IRQ_OFFSET  (2)
+    #define  PLLMIXED_MDBRPPLL_HP_RDY_IRQ_OFFSET   (4)
+
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x318))
+#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK_MASK     (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x31C))
+
+/* PLL IRQ related macro */
+#define  PLLMIXED_PLL_HP_RDY_IRQ_MASK              (0x1)/* mask bit numbers for each IRQ */
+
+/* ==========PLL FHCTL========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x400))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x404))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x408))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FHCTL          (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x410))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FRDDS_LMT      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x414))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_SW_GEAR        (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x418))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x430))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x434))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x438))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_FHCTL            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x440))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_FRDDS_LMT        (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x444))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_SW_GEAR          (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x448))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x450))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x454))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x458))
+
+/* ==========PLL Gear Set========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET0       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x500))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET1       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x504))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET2       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x508))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET3       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50C))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET0      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x540))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET1      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x544))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET2      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x548))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET3      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x54C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET0       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C0))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET1       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C4))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET2       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C8))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET3       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5CC))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET0        (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x600))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET1        (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x604))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET2        (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x608))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET3        (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x60C))
+
+/* ==========PLL Status========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC00))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_STS            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC04))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC08))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_STS              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC0C))
+#define REG_MDTOP_PLLMIXED_MDBPIBPLL_STS            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC10))
+
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC14))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_DA             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC18))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC1C))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC24))
+
+#define REG_MDTOP_PLLMIXED_MDPLL1_STS               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC40))
+#define REG_MDTOP_PLLMIXED_MDPLL1_DA                (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC44))
+
+#define REG_MDTOP_PLLMIXED_FRDDS_OFF_IRQ_MODE       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD00))
+#define REG_MDTOP_PLLMIXED_HP_RDY_OFF_IRQ_MODE      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD04))
+
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY                (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF00))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY1               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF04))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY2               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF08))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY3               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF0C))
+#define REG_MDTOP_PLLMIXED_PLL_STATUS               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF10))
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// CLKSW (0xA0150000)
+///////////////////////////////////////////////////////////////////////////////
+#define REG_MDTOP_CLKSW_CODA_VERSION	            (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x0))
+#define REG_MDTOP_CLKSW_MD_SLEEP_CNT	            (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4))
+#define REG_MDTOP_CLKSW_MDTOPSM_SW_CTL	            (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10))
+#define REG_MDTOP_CLKSW_L1TOPSM_SW_CTL	            (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x14))
+#define REG_MDTOP_CLKSW_CKOFF_CTL                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x1C))
+#define REG_MDTOP_CLKSW_CLKON_CTL                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x20))
+#define REG_MDTOP_CLKSW_CLKSEL_CTL                  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x24))
+
+/* ==========SDF clock control related========== */
+#define REG_MDTOP_CLKSW_SDF_CK_CTL                  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x28))
+#define REG_MDTOP_CLKSW_ATB_LOG_SDF_SW_CTL          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x2C))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL0             (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x30))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL1             (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x34))
+
+#define REG_MDTOP_CLKSW_EXTCK_CTL                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x3C))
+
+/* ==========FLEXCKGEN_SEL========== */
+#define REG_MDTOP_CLKSW_MDCORE_FLEXCKGEN_SEL        (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x40))
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x44))
+#define REG_MDTOP_CLKSW_VDSP_FLEXCKGEN_SEL          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x48))
+#define REG_MDTOP_CLKSW_BRP_FLEXCKGEN_SEL           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4C))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_SEL          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x50))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_SEL         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x54))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_SEL           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x58))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_SEL           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x5C))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x60))
+#define REG_MDTOP_CLKSW_MML2_FLEXCKGEN_SEL          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x64))
+#define REG_MDTOP_CLKSW_RXAGC_FLEXCKGEN_SEL         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x68))
+#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_SEL       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x6C))
+#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x70))
+#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_SEL       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x74))
+#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_SEL      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x78))
+#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_SEL       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x7C))
+
+/* ==========FLEXCKGEN_STS========== */
+#define REG_MDTOP_CLKSW_MDCORE_FLEXCKGEN_STS        (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA0))
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA4))
+#define REG_MDTOP_CLKSW_VDSP_FLEXCKGEN_STS          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA8))
+#define REG_MDTOP_CLKSW_BRP_FLEXCKGEN_STS           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xAC))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_STS          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB0))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_STS         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB4))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_STS           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB8))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_STS           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xBC))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_STS       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC0))
+#define REG_MDTOP_CLKSW_MML2_FLEXCKGEN_STS          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC4))
+#define REG_MDTOP_CLKSW_RXAGC_FLEXCKGEN_STS         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC8))
+#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_STS       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xCC))
+#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_STS      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE0))
+#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_STS       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE4))
+#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_STS      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE8))
+#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_STS       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xEC))
+
+#define REG_MDTOP_CLKSW_CKMUX_STS                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF0))
+#define REG_MDTOP_CLKSW_PLL_STS	                    (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF4))
+#define REG_MDTOP_CLKSW_DFS_STS	                    (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF8))
+
+/* ==========direct pll request========== */
+#define REG_MDTOP_CLKSW_MDMCU_DIRECT_PLLREQ         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x100))
+#define REG_MDTOP_CLKSW_MDBUS_DIRECT_PLLREQ         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x104))
+#define REG_MDTOP_CLKSW_VDSP_DIRECT_PLLREQ          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x108))
+#define REG_MDTOP_CLKSW_BRP_DIRECT_PLLREQ           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10C))
+
+/* ==========Frequency Meter========== */
+#define REG_MDTOP_CLKSW_CKMON_CTL                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x200))
+#define REG_MDTOP_CLKSW_FREQ_METER_CTL              (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x204))
+#define REG_MDTOP_CLKSW_FREQ_METER_XTAL_CNT         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x208))
+#define REG_MDTOP_CLKSW_FREQ_METER_CKMON_CNT        (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x20C))
+#define REG_MDTOP_CLKSW_FREQ_METER_H                (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x210))
+#define REG_MDTOP_CLKSW_FREQ_METER_L                (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x214))
+
+/* ==========DUMMY & STATUS========== */
+#define REG_MDTOP_CLKSW_CLK_DUMMY                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF00))
+#define REG_MDTOP_CLKSW_CLK_STATUS                  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF04))
+
+
+/*******************************************************************************
+ * Define Macro
+ ******************************************************************************/
+#define MD_PLL_MAGIC_NUM 0x62950000
+#define MD_PLL_MAGIC_26M 0x62950026
+#define MD_PLL_MAGIC_MD  0x62951111
+
+/**
+ * PLL divider definition
+ */
+#if defined(MT6295M) || defined(MT3967) || defined(MT6779)
+    #define MDBPIPLL_DIVIDER     (1) /* /2 /3 /4 /5 /6 /7 */
+    #define MDBRPPLL_DIVIDER     (6)
+    #define MDVDSPPLL_DIVIDER    (4) 
+    #define MDMCUPLL_DIVIDER     (4)    
+#else
+    #error "Unsupported Chip Target in PLL Module"
+#endif
+
+ /*------------------------------------------------------------------------
+ * Purpose:     Transfer PCW in xxxPLL_STS to Mhz. This macro is porting from md_dvfs_pll_freq_get(const PLL_SOURCE pll).
+ * Parameters:
+ *    Input:    pcw:    The PCW value in xxxPLL_STS.
+ *              divier: The divier for this PLL(EX: ICCPLL_DIVIDER, IMCPLL_DIVIDER...).
+ *    Output:   None.
+ * returns :    Mhz. 
+ * Note    :    This macr is only used to transfer pcw in xxxPLL_STS to Mhz. 
+ *              You should not used this macro to transfer pcw in xxxPLL_CTL0 to Mhz due to the meaning is different.
+ *              (PCW in xxxPLL_STS is bit [21:7] of xxxPLL_CTL0.)
+ *------------------------------------------------------------------------
+ */
+#define PLLMIXED_PLL_STS_SDM_PCW_TO_MHZ(pcw, divier)   ((((pcw) * 26) / (1 << 7)) / divier)
+
+/*******************************************************************************
+ * ENUM
+ ******************************************************************************/
+// frequency meter index list (debug only)
+typedef enum {
+    PLL_FM_SOURCE_START            = 0x4,
+    PLL_FM_MDBPI_PLL_D4            = 0x4, 
+    PLL_FM_MDBPI_PLL_D6            = 0x5,
+    PLL_FM_MDSYS_MML2_CLOCK        = 0x6,
+    PLL_FM_FESYS_RXAGC_CLOCK       = 0x7,
+    PLL_FM_MDRXSYS_DFESYNC_CLOCK   = 0x8,    
+    PLL_FM_FESYS_F208M_CLOCK       = 0x9,
+    PLL_FM_TRACE_MON_CLOCK         = 0xA,
+    PLL_FM_MDSYS_208M_CLOCK        = 0xB,
+    PLL_FM_MDRXSYS_RAKE_CLOCK      = 0xC,
+    PLL_FM_MDRXSYS_BRP_CLOCK       = 0xD,
+    PLL_FM_MDRXSYS_VDSP_CLOCK      = 0xE,
+    PLL_FM_MDTOP_LOG_ATB_CLOCK     = 0xF,
+    PLL_FM_FESYS_CSYS_CLOCK        = 0x10,
+//    PLL_FM_FESYS_TXSYS_CLOCK       = 0x11,
+    PLL_FM_FESYS_BSI_CLOCK         = 0x12, 
+    PLL_FM_MDSYS_MDCORE_CLOCK      = 0x13, 
+    PLL_FM_MDSYS_BUS2X_NODCM_CLOCK = 0x14, 
+    PLL_FM_MDSYS_BUS2X_CLOCK       = 0x15,
+    PLL_FM_MDTOP_DBG_CLOCK         = 0x16,
+    PLL_FM_MDTOP_F32K_CLOCK        = 0x17,
+    PLL_FM_AD_MDBPI_PLL_D7         = 0x18, /* AD means "analog to digital" */
+    PLL_FM_AD_MDBPI_PLL_D5         = 0x19,
+    PLL_FM_AD_MDBPI_PLL_D4         = 0x1A,
+    PLL_FM_AD_MDBPI_PLL_D3         = 0x1B,
+    PLL_FM_AD_MDBPI_PLL_D2         = 0x1C,
+    PLL_FM_AD_MDBRP_PLL            = 0x1D,
+    PLL_FM_AD_MDVDSP_PLL           = 0x1E,
+    PLL_FM_AD_MDMCU_PLL            = 0x1F,
+    PLL_FM_SOURCE_END              = 0x1F    
+} PLL_FM_SOURCE;
+
+typedef enum {
+    CLKSW_SDF_SRC_BPIPLL_DIV8 = 0,
+    CLKSW_SDF_SRC_BPIPLL_DIV4 = 1,        
+    CLKSW_SDF_SRC_BPIPLL      = 2,  
+    CLKSW_SDF_SRC_BPIPLL_DIV2 = 3, 
+    /*CLKSW_SDF_SRC_USB_PhyLink = 4,*/ /* HW didn't support. */ 
+    CLKSW_SDF_SRC_26M,    
+    CLKSW_SDF_SRC_END    
+} PLL_CLKSW_SDF_SRC;
+
+/* Below for debugging */
+
+#define PLL_FM_NUM 30   /* Note: This number should also sync to EE owner. */
+typedef struct {
+    kal_uint32 MDBPI_PLL_D4;             /* 0 */
+    kal_uint32 MDBPI_PLL_D6;
+    kal_uint32 MDSYS_MML2_CLOCK;
+    kal_uint32 FESYS_RXAGC_CLOCK;
+    kal_uint32 MDRXSYS_DFESYNC_CLOCK;
+    kal_uint32 FESYS_F208M_CLOCK;        /* 5 */
+    kal_uint32 TRACE_MON_CLOCK;
+    kal_uint32 MDSYS_208M_CLOCK;
+    kal_uint32 MDRXSYS_RAKE_CLOCK;
+    kal_uint32 MDRXSYS_BRP_CLOCK;
+    kal_uint32 MDRXSYS_VDSP_CLOCK;       /* 10 */
+    kal_uint32 MDTOP_LOG_ATB_CLOCK;
+    kal_uint32 FESYS_CSYS_CLOCK;
+    kal_uint32 FESYS_BSI_CLOCK;
+    kal_uint32 MDSYS_MDCORE_CLOCK;    
+    kal_uint32 MDSYS_BUS2X_NODCM_CLOCK;  /* 15 */
+    kal_uint32 MDSYS_BUS2X_CLOCK;
+    kal_uint32 MDTOP_DBG_CLOCK;
+    kal_uint32 AD_MDBPI_PLL_D7;
+    kal_uint32 AD_MDBPI_PLL_D5;
+    kal_uint32 AD_MDBPI_PLL_D4;          /* 20 */
+    kal_uint32 AD_MDBPI_PLL_D3;     
+    kal_uint32 AD_MDBPI_PLL_D2;
+    kal_uint32 AD_MDBRP_PLL;
+    kal_uint32 AD_MDVDSP_PLL;   
+    kal_uint32 AD_MDMCU_PLL;             /* 25 */
+/* below no use */    
+    kal_uint32 NULL_26;    
+    kal_uint32 NULL_27;
+    kal_uint32 NULL_28; 
+    kal_uint32 NULL_29;    
+} PLL_CLK_INFO;
+
+extern PLL_CLK_INFO g_pll_info;
+extern const char PLL_FM_clock[PLL_FM_NUM][32];
+
+/* Above for debugging */
+
+/*******************************************************************************
+ * Include header files
+ ******************************************************************************/
+extern void PLL_MD_Pll_Init(void);
+extern void PLL_Set_CLK_To_26M(void);
+
+extern void PLL_exception_dump(void);
+extern kal_uint32 PLL_FrequencyMeter_GetFreq(PLL_FM_SOURCE index);
+
+/* For SDF user in driver/sib_drv/sdf/src/md95/drv_sdf_95.c */
+extern kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Get();
+extern kal_bool PLL_CLKSW_SDF_SRC_CKSEL_Set(PLL_CLKSW_SDF_SRC src_ck);
+
+#endif  /* !__PLL_MT6295_H__ */
+
diff --git a/mcu/interface/driver/devdrv/pll/pll_gen97.h b/mcu/interface/driver/devdrv/pll/pll_gen97.h
new file mode 100644
index 0000000..bafaaf2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pll/pll_gen97.h
@@ -0,0 +1,642 @@
+/*******************************************************************************
+ *  Copyright Statement:
+ *  --------------------
+ *  This software is protected by Copyright and the information contained
+ *  herein is confidential. The software may not be copied and the information
+ *  contained herein may not be used or disclosed except with the written
+ *  permission of MediaTek Inc. (C) 2012
+ *
+ *  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ *  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ *  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ *  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ *  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ *  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ *  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ *  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ *  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ *  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ *  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ *  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ *  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ *  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ *  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ *  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ *  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ *  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ *  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ *  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ *  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   pll_gen97.h
+ *
+ * Project:
+ * --------
+ *   UMOLYE
+ *
+ * Description:
+ * ------------
+ *   PLL Related Functions
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ============================================================================
+ * $Log$
+ *
+ * 11 24 2020 e-lin.ho
+ * [MOLY00593429] [Gen97] Check-in debug code to get high precision MDPLL frequency in exception flow
+ * 	
+ * 	[Gen97] Check-in debug code to get high precision MDPLL frequency in exception flow
+ *
+ * 06 17 2020 jun-ying.huang
+ * [MOLY00535069] [MMRFD][UCNT] Read D die PLL CNT at exception flow
+ * Add PLL related function
+ *
+ * 11 05 2019 jun-ying.huang
+ * [MOLY00457260] [MARGAUX call for check-in]Update related driver for MARGAUX
+ * .
+ *
+ * 09 03 2019 jun-ying.huang
+ * [MOLY00431611] [VMOLY][Petrus]Update related driver for Petrus.
+ * Update AMIF&PLL driver
+ *
+ * 12 05 2018 jun-ying.huang
+ * [MOLY00370736] [MT6885]Update PLL for MT6885
+ * .
+ *
+ * 08 09 2018 jun-ying.huang
+ * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97
+ * .
+ *
+ * 07 13 2018 jun-ying.huang
+ * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97
+ * .
+ *
+ * 06 06 2018 jun-ying.huang
+ * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97
+ * .
+ *
+ * 05 30 2018 jun-ying.huang
+ * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97
+ * draft version
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __PLL_MT6297_H__
+#define __PLL_MT6297_H__
+
+/*******************************************************************************
+ * Locally Used Options
+ ******************************************************************************/
+#define PLL_REG32(addr) *(volatile kal_uint32 *)(addr)
+#define PLL_TYPE        (volatile kal_uint32 *)
+
+/*******************************************************************************
+ * Define macro for boot code
+ ******************************************************************************/
+#define __SECTION__(S) __attribute__((__section__(#S)))
+#define __PLL_CODE_IN_BOOT__ __SECTION__(BR_EXT)/* "BR_EXT" section for bootROM */
+
+/*******************************************************************************
+ * Register Define
+ ******************************************************************************/
+
+///////////////////////////////////////////////////////////////////////////////
+/// PLLMIXED (0xA0140000)
+///////////////////////////////////////////////////////////////////////////////
+/* ==========PLL setting========== */
+#define REG_MDTOP_PLLMIXED_CODA_VERSION             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x0))
+#define REG_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4))
+#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK          (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x8))
+#define REG_MDTOP_PLLMIXED_DCXO_MODE_CTL            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC))
+#define REG_MDTOP_PLLMIXED_PLL_ON_CTL               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL0              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x14))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL1              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x18))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL2              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x1C))
+#define REG_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x20))
+#define REG_MDTOP_PLLMIXED_RF_SETTLE_CTL            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x24))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL0             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL1             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x34))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL2             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x38))
+
+/* ==========PLL frequency control==> PCW & POSDIV========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x40))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x44))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL0           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x48))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL1           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x54))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x58))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x68))
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x6C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x70))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x74))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x78))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x7C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x80))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x84))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x88))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x8C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x90))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x94))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL0               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x98))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL1               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x9C))
+#define REG_MDTOP_PLLMIXED_MDPLLGP_RESERVE          (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xA0))
+
+#define REG_MDTOP_PLLMIXED_MDPLLGP1_CTL             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x100))
+#define REG_MDTOP_PLLMIXED_MDPLLGP2_CTL             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x104))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10C))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE2             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x110))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE3             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x114))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE4             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x118))
+
+#define REG_MDTOP_PLLMIXED_PLL_DIV_RSTB             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x120))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_EN0              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x124))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_EN2              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x12C))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_EN3              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x130))
+#define REG_MDTOP_PLLMIXED_PLL_SRC_SEL              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x140))
+
+#define REG_MDTOP_PLLMIXED_PLL_FHCTL_RST            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x200))
+
+/* ==========PLL IRQ related========== */
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_IRQ    (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x300))
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_MASK   (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x304))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_IRQ      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x308))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_MASK     (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30C))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_ABNORM_STS       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x310))
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x314))
+    #define  PLLMIXED_MDMCUPLL_HP_RDY_IRQ_OFFSET    (1)
+    #define  PLLMIXED_MDVDSPPLL_HP_RDY_IRQ_OFFSET   (2)
+    #define  PLLMIXED_MDBRPPLL_HP_RDY_IRQ_OFFSET    (3)
+
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x318))
+#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK_MASK     (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x31C))
+
+/* PLL IRQ related macro */
+#define  PLLMIXED_PLL_HP_RDY_IRQ_MASK               (0x1)/* mask bit numbers for each IRQ */
+
+/* ==========PLL FHCTL========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x400))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x404))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x408))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FHCTL          (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x410))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FRDDS_LMT      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x414))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_SW_GEAR        (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x418))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x420))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x424))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x428))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x430))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x434))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x438))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x450))
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x454))
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x458))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x460))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x464))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x468))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x470))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x474))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x478))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x480))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x484))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x488))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x490))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x494))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x498))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4A0))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4A4))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4A8))
+#define REG_MDTOP_PLLMIXED_MDPLL_FHCTL              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4B0))
+#define REG_MDTOP_PLLMIXED_MDPLL_FRDDS_LMT          (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4B4))
+#define REG_MDTOP_PLLMIXED_MDPLL_SW_GEAR            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4B8))
+
+/* ==========PLL Gear Set========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET0       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x500))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET1       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x504))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET2       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x508))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET3       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50C))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET0      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x510))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET1      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x514))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET2      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x518))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET3      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x51C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET0       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x520))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET1       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x524))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET2       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x528))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET3       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x52C))
+
+/* ==========PLL Status========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x800))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_STS            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x804))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x808))
+#define REG_MDTOP_PLLMIXED_MDBPIBPLL_STS            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x810))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x818))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x81C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x820))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x824))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x828))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x82C))
+#define REG_MDTOP_PLLMIXED_MDPLL_STS                (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x830))
+
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC14))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_DA             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC18))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC1C))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC20))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC28))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC2C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC30))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC34))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC38))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC3C))
+#define REG_MDTOP_PLLMIXED_MDPLL_DA                 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC40))
+
+#define REG_MDTOP_PLLMIXED_FRDDS_OFF_IRQ_MODE       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD00))
+#define REG_MDTOP_PLLMIXED_HP_RDY_OFF_IRQ_MODE      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD04))
+
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY                (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF00))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY1               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF04))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY2               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF08))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY3               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF0C))
+#define REG_MDTOP_PLLMIXED_PLL_STATUS               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF10))
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// CLKSW (0xA0150000)
+///////////////////////////////////////////////////////////////////////////////
+#define REG_MDTOP_CLKSW_CODA_VERSION                (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x0))
+#define REG_MDTOP_CLKSW_MD_SLEEP_CNT                (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4))
+#define REG_MDTOP_CLKSW_RFSLPC_SW_CTRL              (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x8))
+#define REG_MDTOP_CLKSW_MDTOPSM_SW_CTL	            (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10))
+#define REG_MDTOP_CLKSW_L1TOPSM_SW_CTL	            (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x14))
+#define REG_MDTOP_CLKSW_L1TOPSM_SW_CTL2             (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x18))
+#define REG_MDTOP_CLKSW_CKOFF_CTL                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x1C))
+#define REG_MDTOP_CLKSW_CLKON_CTL                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x20))
+#define REG_MDTOP_CLKSW_CLKSEL_CTL                  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x24))
+#define REG_MDTOP_CLKSW_CLKSEL_CTL_2                (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x28))
+
+/* ==========SDF clock control related========== */
+#define REG_MDTOP_CLKSW_SDF_ATB_CK_CTL              (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x2C))
+#define REG_MDTOP_CLKSW_ATB_LOG_SDF_SW_CTL          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x30))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL0             (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x34))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL1             (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x38))
+
+#define REG_MDTOP_CLKSW_EXTCK_CTL                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x40))
+
+/* ==========FLEXCKGEN_SEL========== */
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x44))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_SEL          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x48))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_SEL         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4C))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_SEL           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x50))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_SEL           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x54))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x58))
+#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_SEL       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x5C))
+#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x70))
+#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_SEL       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x74))
+#define REG_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_SEL   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x78))
+#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_SEL      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x7C))
+#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_SEL       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x80))
+
+#define REG_MDTOP_CLKSW_NR_CS_DFS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x84))
+#define REG_MDTOP_CLKSW_NR_CM_DFS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x88))
+#define REG_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_SEL      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x8C))
+#define REG_MDTOP_CLKSW_VCORE_DFS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x90))
+#define REG_MDTOP_CLKSW_MCORE_DFS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x94))
+#define REG_MDTOP_CLKSW_RXDDM_DFS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x98))
+#define REG_MDTOP_CLKSW_RXDBRP_DFS_FLEXCKGEN_SEL    (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x9C))
+#if defined(MT6297)/* Only support APOLLO */
+#define REG_MDTOP_CLKSW_RXCSI_DFS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA0))
+#endif
+#define REG_MDTOP_CLKSW_FETXBSRP_DFS_FLEXCKGEN_SEL  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA4))
+#define REG_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA8))
+#define REG_MDTOP_CLKSW_NR_RXT2F_DFS_FLEXCKGEN_SEL  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xAC))
+#define REG_MDTOP_CLKSW_CPC_FLEXCKGEN_SEL           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB0))
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB4))
+#if defined(MT6297) /* APOLLO */
+#define REG_MDTOP_CLKSW_IA_DFS_FLEXCKGEN_SEL        (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB8))
+#else/* MT6885 and later */
+#define REG_MDTOP_CLKSW_RXDFE_DFS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB8))
+#endif
+#define REG_MDTOP_CLKSW_BUS2X_NODCM_FLEXCKGEN_SEL   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xBC))
+#if defined(MT6297)/* APOLLO */
+/* APOLLO didn't support */
+#else/* MT6885 and later */
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FIXED_FLEXCKGEN_SEL   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC0))
+#endif
+
+/* ==========FLEXCKGEN_STS========== */
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xCC))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_STS          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD0))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_STS         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD4))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_STS           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD8))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_STS           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xDC))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_STS       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE0))
+#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_STS       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE4))
+#define REG_MDTOP_CLKSW_MDPLL_FLEXCKGEN_STS         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE8))
+
+#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_STS      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF0))
+#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_STS       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF4))
+#define REG_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_STS   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF8))
+#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_STS      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xFC))
+#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_STS       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x100))
+#define REG_MDTOP_CLKSW_NR_CS_DFS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x104))
+#define REG_MDTOP_CLKSW_NR_CM_DFS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x108))
+#define REG_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_STS      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10C))
+#define REG_MDTOP_CLKSW_VCORE_DFS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x110))
+#define REG_MDTOP_CLKSW_MCORE_DFS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x114))
+#define REG_MDTOP_CLKSW_RXDDM_DFS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x118))
+#define REG_MDTOP_CLKSW_RXDBRP_DFS_FLEXCKGEN_STS    (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x11C))
+#if defined(MT6297)/* Only support APOLLO */
+#define REG_MDTOP_CLKSW_RXCSI_DFS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x120))
+#endif
+#define REG_MDTOP_CLKSW_FETXBSRP_DFS_FLEXCKGEN_STS  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x124))
+#define REG_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x12C))
+#define REG_MDTOP_CLKSW_NR_RXT2F_DFS_FLEXCKGEN_STS  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x130))
+#define REG_MDTOP_CLKSW_CPC_FLEXCKGEN_STS           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x134))
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x138))
+#if defined(MT6297)/* APOLLO */
+#define REG_MDTOP_CLKSW_IA_DFS_FLEXCKGEN_STS        (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x13C))
+#else/* MT6885 and later */
+#define REG_MDTOP_CLKSW_RXDFE_DFS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x13C))
+#endif
+#define REG_MDTOP_CLKSW_BUS2X_NODCM_FLEXCKGEN_STS   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x140))
+#if defined(MT6297)/* APOLLO */
+/* APOLLO didn't support */
+#else/* MT6885 and later */
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FIXED_FLEXCKGEN_STS   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x144))
+#endif
+
+#define REG_MDTOP_CLKSW_CKMUX_STS                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x200))
+#define REG_MDTOP_CLKSW_PLL_STS	                    (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x210))
+#define REG_MDTOP_CLKSW_DFS_STS	                    (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x220))
+#define REG_MDTOP_CLKSW_DFS_STS_2                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x224))
+
+/* ==========direct pll request========== */
+#define REG_MDTOP_CLKSW_MDMCU_DIRECT_PLLREQ         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x300))
+#define REG_MDTOP_CLKSW_MDBUS_DIRECT_PLLREQ         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x304))
+#define REG_MDTOP_CLKSW_VDSP_DIRECT_PLLREQ          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x308))
+#define REG_MDTOP_CLKSW_BRP_DIRECT_PLLREQ           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x30C))
+
+/* ==========Frequency Meter========== */
+#define REG_MDTOP_CLKSW_CKMON_CTL                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x400))
+#define REG_MDTOP_CLKSW_FREQ_METER_CTL              (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x404))
+#define REG_MDTOP_CLKSW_FREQ_METER_XTAL_CNT         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x408))
+#define REG_MDTOP_CLKSW_FREQ_METER_CKMON_CNT        (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x40C))
+#define REG_MDTOP_CLKSW_FREQ_METER_H                (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x410))
+#define REG_MDTOP_CLKSW_FREQ_METER_L                (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x414))
+
+#define REG_MDTOP_CLKSW_CLK_REQ_MON                 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x500))
+#define REG_MDTOP_CLKSW_CLK_RDY_MON                 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x504))
+
+/* ==========DUMMY & STATUS========== */
+#define REG_MDTOP_CLKSW_CLK_DUMMY                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF00))
+#define REG_MDTOP_CLKSW_CLK_STATUS                  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF04))
+
+
+/*******************************************************************************
+ * Define Macro
+ ******************************************************************************/
+#define MD_PLL_MAGIC_NUM 0x62970000
+#define MD_PLL_MAGIC_26M 0x62970026
+#define MD_PLL_MAGIC_MD  0x62971111
+
+#define PLL_FM_WIMDOW       	(0x1FF)
+#define PLL_FM_WIMDOW_EX_MDPLL	(0x3F7A0)
+#define PLL_FM_SOURCE_OCCUPIED   12345678
+
+ /*------------------------------------------------------------------------
+ * Purpose:     Transfer PCW in xxxPLL_STS to Mhz. This macro is porting from md_dvfs_pll_freq_get(const PLL_SOURCE pll).
+ * Parameters:
+ *    Input:    pcw:    The PCW value in xxxPLL_STS.
+ *              divier: The divier for this PLL(EX: ICCPLL_DIVIDER, IMCPLL_DIVIDER...).
+ *    Output:   None.
+ * returns :    Mhz. 
+ * Note    :    This macr is only used to transfer pcw in xxxPLL_STS to Mhz. 
+ *              You should not used this macro to transfer pcw in xxxPLL_CTL0 to Mhz due to the meaning is different.
+ *              (PCW in xxxPLL_STS is bit [21:7] of xxxPLL_CTL0.)
+ *------------------------------------------------------------------------
+ */
+#define PLLMIXED_PLL_STS_SDM_PCW_TO_MHZ(pcw, divier)   ((((pcw) * 26) / (1 << 7)) / divier)
+
+/*******************************************************************************
+ * ENUM
+ ******************************************************************************/
+// frequency meter index list (debug only)
+typedef enum {
+    PLL_FM_SOURCE_START            = 0x0,
+    PLL_FM_AD_MDNRPLL5             = 0x0,
+    PLL_FM_AD_MDNRPLL4_1           = 0x1,
+    PLL_FM_AD_MDNRPLL4_0           = 0x2,
+    PLL_FM_AD_MDNRPLL3             = 0x3,    
+    PLL_FM_AD_MDNRPLL2             = 0x4, 
+    PLL_FM_AD_MDNRPLL1             = 0x5, 
+    PLL_FM_AD_MDNRPLL0             = 0x6, 
+    PLL_FM_MDSYS_NRL2_CLOCK        = 0x7, // NRL2 = MML2
+    PLL_FM_MDRXSYS_DFESYNC_CLOCK   = 0x8,
+#if defined(MT6297)/* APOLLO */
+    PLL_FM_MDTOP_F208M_CLOCK       = 0x9,
+    PLL_FM_TRACE_MON_CLOCK         = 0xA,
+    PLL_FM_MDSYS_208M_CLOCK        = 0xB,    
+#else/* MT6885 and later */    
+    PLL_FM_MDTOP_F216P7M_CLOCK     = 0x9,
+    PLL_FM_TRACE_MON_CLOCK         = 0xA,  
+    PLL_FM_MDSYS_216P7M_CLOCK      = 0xB,     
+#endif    
+    PLL_FM_MDRXSYS_RAKE_CLOCK      = 0xC,    
+    PLL_FM_MDRXSYS_BRP_CLOCK       = 0xD,
+    PLL_FM_MDRXSYS_VDSP_CLOCK      = 0xE,   
+    PLL_FM_MDTOP_LOG_ATB_CLOCK     = 0xF,
+    PLL_FM_FESYS_CSYS_CLOCK        = 0x10,
+    PLL_FM_MDSYS_SHAOLIN_CLOCK     = 0x11,
+    PLL_FM_FESYS_BSI_CLOCK         = 0x12,
+    PLL_FM_MDSYS_MDCORE_CLOCK      = 0x13, 
+    PLL_FM_MDSYS_BUS2X_NODCM_CLOCK = 0x14, 
+    PLL_FM_MDSYS_BUS4X_CLOCK       = 0x15,
+    PLL_FM_MDTOP_DBG_CLOCK         = 0x16,
+    PLL_FM_MDTOP_F32K_CLOCK        = 0x17,
+    PLL_FM_AD_MDBPI_PLL_D7         = 0x18, /* AD means "analog to digital" */
+    PLL_FM_AD_MDBPI_PLL_D5         = 0x19,
+    PLL_FM_AD_MDBPI_PLL_D4         = 0x1A,
+    PLL_FM_AD_MDBPI_PLL_D3         = 0x1B,
+    PLL_FM_AD_MDBPI_PLL_D2         = 0x1C, 
+    PLL_FM_AD_MDBRP_PLL            = 0x1D,
+    PLL_FM_AD_MDVDSP_PLL           = 0x1E,
+    PLL_FM_AD_MDMCU_PLL            = 0x1F,
+    /* CKMON_SRC_SEL2 = 1 */ 
+    PLL_FM_NULL                    = 0x20,
+    
+#if defined(MT6297)/* APOLLO */
+/* APOLLO didn't support */
+#else/* MT6885 and later */
+    PLL_FM_DFESYS_RXDFE_BB_CORE_CLOCK = 0x2E,
+    PLL_FM_AD_MDNRPLL4_2              = 0x2F,  
+    PLL_FM_MDTOP_BUS4X_FIXED_CLOCK    = 0x30,    
+    PLL_FM_DA_DRF_26M_CLOCK           = 0x31,    
+#endif
+    PLL_FM_MDTOP_BUS4X_CLOCK       = 0x32,
+    PLL_FM_RXCPC_CPC_CLOCK         = 0x33,
+#if defined(MT6297)/* Only APOLLO support. */    
+    PLL_FM_RXDDMBRP_RXCSI_CLOCK    = 0x34,
+#endif    
+    PLL_FM_RXDDMBRP_RXDBRP_CLOCK   = 0x35,
+    PLL_FM_RXDDMBRP_RXDDM_CLOCK    = 0x36,
+    PLL_FM_MCORE_MCORE_CLOCK       = 0x37, 
+    PLL_FM_VCOREHRAM_VCORE_CLOCK   = 0x38,
+    PLL_FM_VCOREHRAM_HRAM_CLOCK    = 0x39,
+    PLL_FM_FESYS_TXBSRP_CLOCK      = 0x3A,
+    PLL_FM_FESYS_MDPLL_CLOCK       = 0x3B,
+    PLL_FM_TX_CS_NR_RXT2F_NR_CLOCK = 0x3C,
+    PLL_FM_TX_CS_NR_TXBSRP_NR_CLOCK= 0x3D,
+    PLL_FM_TX_CS_NR_CM_NR_CLOCK    = 0x3E,
+    PLL_FM_TX_CS_NR_CS_NR_CLOCK    = 0x3F,
+#if defined(MT6297)/* Only APOLLO support. */     
+    PLL_FM_MDSYS_IA_CLOCK          = 0x40,   
+    PLL_FM_SOURCE_END              = 0x40    
+#else/* MT6885 and later */
+    PLL_FM_SOURCE_END                 = 0x3F
+#endif
+} PLL_FM_SOURCE;
+
+typedef enum {
+#if defined(MT6297)/* APOLLO */    
+    CLKSW_SDF_SRC_MDPLL_F624M = 0,
+    CLKSW_SDF_SRC_TOP_BUS4X   = 1,        
+    CLKSW_SDF_SRC_MDPLL_F312M = 2,  
+    CLKSW_SDF_SRC_MDPLL_F208M = 3, 
+#else/* MT6885 and later */
+    CLKSW_SDF_SRC_MDPLL_F650M   = 0,
+    CLKSW_SDF_SRC_TOP_BUS4X     = 1,        
+    CLKSW_SDF_SRC_MDPLL_F325M   = 2,  
+    CLKSW_SDF_SRC_MDPLL_F216P7M = 3,
+#endif
+    CLKSW_SDF_SRC_26M,    
+    CLKSW_SDF_SRC_END    
+} PLL_CLKSW_SDF_SRC;
+
+typedef enum {
+    CLKSW_SDF_SRC_DIV_1    = 0,
+    CLKSW_SDF_SRC_DIV_2    = 1,
+    CLKSW_SDF_SRC_DIV_3    = 2,
+    CLKSW_SDF_SRC_DIV_4    = 3  
+} PLL_CLKSW_SDF_SRC_DIV;
+
+/* Below for debugging */
+
+#define PLL_FM_NUM 48   /* Note: This number should also sync to EE owner. */
+typedef struct {
+    kal_uint32 AD_MDNRPLL5;             /* 0 */
+    kal_uint32 AD_MDNRPLL4_1;
+    kal_uint32 AD_MDNRPLL4_0;
+    kal_uint32 AD_MDNRPLL3;
+    kal_uint32 AD_MDNRPLL2;
+    kal_uint32 AD_MDNRPLL1;             /* 5 */
+    kal_uint32 AD_MDNRPLL0;
+    kal_uint32 MDSYS_NRL2_CLOCK;
+    kal_uint32 MDRXSYS_DFESYNC_CLOCK;
+#if defined(MT6297)/* APOLLO */    
+    kal_uint32 MDTOP_F208M_CLOCK;
+    kal_uint32 TRACE_MON_CLOCK;         /* 10 */
+    kal_uint32 MDSYS_208M_CLOCK;
+#else/* MT6885 and later */
+    kal_uint32 MDTOP_F216P7M_CLOCK;
+    kal_uint32 TRACE_MON_CLOCK;         /* 10 */
+    kal_uint32 MDSYS_216P7M_CLOCK;
+#endif
+    kal_uint32 MDRXSYS_RAKE_CLOCK;
+    kal_uint32 MDRXSYS_BRP_CLOCK;
+    kal_uint32 MDRXSYS_VDSP_CLOCK;    
+    kal_uint32 MDTOP_LOG_ATB_CLOCK;     /* 15 */
+    kal_uint32 FESYS_CSYS_CLOCK;
+    kal_uint32 MDSYS_SHAOLIN_CLOCK;
+    kal_uint32 FESYS_BSI_CLOCK;
+    kal_uint32 MDSYS_MDCORE_CLOCK;
+    kal_uint32 MDSYS_BUS2X_NODCM_CLOCK; /* 20 */
+    kal_uint32 MDSYS_BUS4X_CLOCK;     
+    kal_uint32 MDTOP_DBG_CLOCK;
+    kal_uint32 AD_MDBPI_PLL_D7;   
+    kal_uint32 AD_MDBPI_PLL_D5;                
+    kal_uint32 AD_MDBPI_PLL_D4;         /* 25 */    
+    kal_uint32 AD_MDBPI_PLL_D3;
+    kal_uint32 AD_MDBPI_PLL_D2; 
+    kal_uint32 AD_MDBRP_PLL;
+    kal_uint32 AD_MDVDSP_PLL;                     
+    kal_uint32 AD_MDMCU_PLL;            /* 30 */     
+#if defined(MT6297)/* APOLLO */
+    kal_uint32 MDTOP_BUS4X_CLOCK;   
+    kal_uint32 RXCPC_CPC_CLOCK; 
+    kal_uint32 RXDDMBRP_RXCSI_CLOCK;       
+    kal_uint32 RXDDMBRP_RXDBRP_CLOCK;   
+    kal_uint32 RXDDMBRP_RXDDM_CLOCK;    /* 35 */ 
+    kal_uint32 MCORE_MCORE_CLOCK;       
+    kal_uint32 VCOREHRAM_VCORE_CLOCK;   
+    kal_uint32 VCOREHRAM_HRAM_CLOCK;    
+    kal_uint32 FESYS_TXBSRP_CLOCK;   
+    kal_uint32 FESYS_MDPLL_CLOCK;       /* 40 */
+    kal_uint32 TX_CS_NR_RXT2F_NR_CLOCK;   
+    kal_uint32 TX_CS_NR_TXBSRP_NR_CLOCK;  
+    kal_uint32 TX_CS_NR_CM_NR_CLOCK;   
+    kal_uint32 TX_CS_NR_CS_NR_CLOCK;    
+    kal_uint32 NULL_45;
+    kal_uint32 NULL_46;  
+    kal_uint32 NULL_47;    
+#else/* MT6885 and later */
+    kal_uint32 DFESYS_RXDFE_BB_CORE_CLOCK; 
+    kal_uint32 AD_MDNRPLL4_2;  
+    kal_uint32 MDTOP_BUS4X_FIXED_CLOCK;    
+    kal_uint32 DA_DRF_26M_CLOCK;  
+    kal_uint32 MDTOP_BUS4X_CLOCK;       /* 35 */   
+    kal_uint32 RXCPC_CPC_CLOCK; 
+    kal_uint32 RXDDMBRP_RXDBRP_CLOCK;   
+    kal_uint32 RXDDMBRP_RXDDM_CLOCK;     
+    kal_uint32 MCORE_MCORE_CLOCK;       
+    kal_uint32 VCOREHRAM_VCORE_CLOCK;   /* 40 */
+    kal_uint32 VCOREHRAM_HRAM_CLOCK;    
+    kal_uint32 FESYS_TXBSRP_CLOCK;   
+    kal_uint32 FESYS_MDPLL_CLOCK;       
+    kal_uint32 TX_CS_NR_RXT2F_NR_CLOCK;   
+    kal_uint32 TX_CS_NR_TXBSRP_NR_CLOCK;/* 45 */  
+    kal_uint32 TX_CS_NR_CM_NR_CLOCK;   
+    kal_uint32 TX_CS_NR_CS_NR_CLOCK;
+    /* we couldn't add more PLL here... */
+#endif    
+    
+} PLL_CLK_INFO;
+
+extern PLL_CLK_INFO g_pll_info;
+extern const char PLL_FM_clock[PLL_FM_NUM][32];
+
+/* Above for debugging */
+
+/*******************************************************************************
+ * Include header files
+ ******************************************************************************/
+extern void PLL_MD_Pll_Init(void);
+extern void PLL_Set_CLK_To_26M(void);
+
+extern void PLL_Check_26M_ACK_Status(kal_uint32 identifier);
+extern void PLL_Clear_26M_ACK_Status(void);
+extern void PLL_exception_dump(void);
+extern kal_uint32 PLL_FrequencyMeter_GetFreq(PLL_FM_SOURCE index);
+extern kal_uint32 PLL_FrequencyMeter_GetCKMON_CNT(PLL_FM_SOURCE index, kal_uint32 xta_cnt, kal_uint32 *ckmon_cnt);
+
+/* For SDF user in driver/sib_drv/sdf/src/md97/drv_sdf_97.c */
+extern kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Get();
+extern kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Div_Get();
+extern kal_bool PLL_CLKSW_SDF_SRC_CKSEL_Set(PLL_CLKSW_SDF_SRC src_clk, PLL_CLKSW_SDF_SRC_DIV src_div);
+
+#endif  /* !__PLL_MT6297_H__ */
+
diff --git a/mcu/interface/driver/devdrv/pll/pll_gen97p.h b/mcu/interface/driver/devdrv/pll/pll_gen97p.h
new file mode 100644
index 0000000..0064305
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pll/pll_gen97p.h
@@ -0,0 +1,530 @@
+/*******************************************************************************
+ *  Copyright Statement:
+ *  --------------------
+ *  This software is protected by Copyright and the information contained
+ *  herein is confidential. The software may not be copied and the information
+ *  contained herein may not be used or disclosed except with the written
+ *  permission of MediaTek Inc. (C) 2012
+ *
+ *  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ *  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ *  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ *  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ *  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ *  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ *  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ *  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ *  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ *  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ *  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ *  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ *  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ *  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ *  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ *  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ *  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ *  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ *  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ *  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ *  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ *  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ *   pll_gen97p.h
+ *
+ * Project:
+ * --------
+ *   UMOLYE
+ *
+ * Description:
+ * ------------
+ *   PLL Related Functions
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ============================================================================
+ * $Log$
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __PLL_MT6297P_H__
+#define __PLL_MT6297P_H__
+//wolf: the code below is not ready, just for build pass~  
+/*******************************************************************************
+ * Locally Used Options
+ ******************************************************************************/
+#define PLL_REG32(addr) *(volatile kal_uint32 *)(addr)
+#define PLL_TYPE        (volatile kal_uint32 *)
+
+/*******************************************************************************
+ * Define macro for boot code
+ ******************************************************************************/
+#define __SECTION__(S) __attribute__((__section__(#S)))
+#define __PLL_CODE_IN_BOOT__ __SECTION__(BR_EXT)/* "BR_EXT" section for bootROM */
+
+/*******************************************************************************
+ * Register Define
+ ******************************************************************************/
+
+///////////////////////////////////////////////////////////////////////////////
+/// PLLMIXED (0xA0140000)
+///////////////////////////////////////////////////////////////////////////////
+/* ==========PLL setting========== */
+#define REG_MDTOP_PLLMIXED_CODA_VERSION             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x0))
+#define REG_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4))
+#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK          (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x8))
+#define REG_MDTOP_PLLMIXED_DCXO_MODE_CTL            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC))
+#define REG_MDTOP_PLLMIXED_PLL_ON_CTL               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL0              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x14))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL1              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x18))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL2              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x1C))
+#define REG_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x20))
+#define REG_MDTOP_PLLMIXED_RF_SETTLE_CTL            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x24))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL0             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL1             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x34))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL2             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x38))
+
+/* ==========PLL frequency control==> PCW & POSDIV========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x40))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x44))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL0           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x48))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL1           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x54))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x58))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x68))
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x6C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x70))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x74))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x78))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x7C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x80))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x84))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x88))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x8C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_CTL0            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x90))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_CTL1            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x94))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL0               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x98))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL1               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x9C))
+#define REG_MDTOP_PLLMIXED_MDPLLGP_RESERVE          (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xA0))
+
+#define REG_MDTOP_PLLMIXED_MDPLLGP1_CTL             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x100))
+#define REG_MDTOP_PLLMIXED_MDPLLGP2_CTL             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x104))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10C))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE2             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x110))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE3             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x114))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE4             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x118))
+
+#define REG_MDTOP_PLLMIXED_PLL_DIV_RSTB             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x120))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_EN0              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x124))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_EN2              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x12C))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_EN3              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x130))
+#define REG_MDTOP_PLLMIXED_PLL_SRC_SEL              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x140))
+
+#define REG_MDTOP_PLLMIXED_PLL_FHCTL_RST            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x200))
+
+/* ==========PLL IRQ related========== */
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_IRQ    (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x300))
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_MASK   (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x304))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_IRQ      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x308))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_MASK     (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30C))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_ABNORM_STS       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x310))
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x314))
+    #define  PLLMIXED_MDMCUPLL_HP_RDY_IRQ_OFFSET    (1)
+    #define  PLLMIXED_MDVDSPPLL_HP_RDY_IRQ_OFFSET   (2)
+    #define  PLLMIXED_MDBRPPLL_HP_RDY_IRQ_OFFSET    (3)
+
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x318))
+#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK_MASK     (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x31C))
+
+/* PLL IRQ related macro */
+#define  PLLMIXED_PLL_HP_RDY_IRQ_MASK               (0x1)/* mask bit numbers for each IRQ */
+
+/* ==========PLL FHCTL========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x400))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x404))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x408))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FHCTL          (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x410))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FRDDS_LMT      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x414))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_SW_GEAR        (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x418))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x420))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x424))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x428))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x430))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x434))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x438))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x450))
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x454))
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x458))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x460))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x464))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x468))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x470))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x474))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x478))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x480))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x484))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x488))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x490))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x494))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x498))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_FHCTL           (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4A0))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_FRDDS_LMT       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4A4))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_SW_GEAR         (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4A8))
+#define REG_MDTOP_PLLMIXED_MDPLL_FHCTL              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4B0))
+#define REG_MDTOP_PLLMIXED_MDPLL_FRDDS_LMT          (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4B4))
+#define REG_MDTOP_PLLMIXED_MDPLL_SW_GEAR            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4B8))
+
+/* ==========PLL Gear Set========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET0       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x500))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET1       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x504))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET2       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x508))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET3       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50C))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET0      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x510))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET1      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x514))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET2      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x518))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET3      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x51C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET0       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x520))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET1       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x524))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET2       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x528))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET3       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x52C))
+
+/* ==========PLL Status========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x800))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_STS            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x804))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x808))
+#define REG_MDTOP_PLLMIXED_MDBPIBPLL_STS            (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x810))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x818))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x81C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x820))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x824))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x828))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_STS             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x82C))
+#define REG_MDTOP_PLLMIXED_MDPLL_STS                (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x830))
+
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC14))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_DA             (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC18))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC1C))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC20))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC28))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC2C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC30))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC34))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC38))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_DA              (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC3C))
+#define REG_MDTOP_PLLMIXED_MDPLL_DA                 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC40))
+
+#define REG_MDTOP_PLLMIXED_FRDDS_OFF_IRQ_MODE       (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD00))
+#define REG_MDTOP_PLLMIXED_HP_RDY_OFF_IRQ_MODE      (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD04))
+
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY                (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF00))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY1               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF04))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY2               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF08))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY3               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF0C))
+#define REG_MDTOP_PLLMIXED_PLL_STATUS               (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF10))
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// CLKSW (0xA0150000)
+///////////////////////////////////////////////////////////////////////////////
+#define REG_MDTOP_CLKSW_CODA_VERSION                (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x0))
+#define REG_MDTOP_CLKSW_MD_SLEEP_CNT                (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4))
+#define REG_MDTOP_CLKSW_RFSLPC_SW_CTRL              (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x8))
+#define REG_MDTOP_CLKSW_MDTOPSM_SW_CTL	            (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10))
+#define REG_MDTOP_CLKSW_L1TOPSM_SW_CTL	            (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x14))
+#define REG_MDTOP_CLKSW_L1TOPSM_SW_CTL2             (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x18))
+#define REG_MDTOP_CLKSW_CKOFF_CTL                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x1C))
+#define REG_MDTOP_CLKSW_CLKON_CTL                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x20))
+#define REG_MDTOP_CLKSW_CLKSEL_CTL                  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x24))
+#define REG_MDTOP_CLKSW_CLKSEL_CTL_2                (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x28))
+
+/* ==========SDF clock control related========== */
+#define REG_MDTOP_CLKSW_SDF_ATB_CK_CTL              (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x2C))
+#define REG_MDTOP_CLKSW_ATB_LOG_SDF_SW_CTL          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x30))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL0             (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x34))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL1             (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x38))
+
+#define REG_MDTOP_CLKSW_EXTCK_CTL                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x40))
+
+/* ==========FLEXCKGEN_SEL========== */
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x44))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_SEL          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x48))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_SEL         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4C))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_SEL           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x50))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_SEL           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x54))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x58))
+#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_SEL       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x5C))
+#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x70))
+#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_SEL       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x74))
+#define REG_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_SEL   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x78))
+#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_SEL      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x7C))
+#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_SEL       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x80))
+
+#define REG_MDTOP_CLKSW_NR_CS_DFS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x84))
+#define REG_MDTOP_CLKSW_NR_CM_DFS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x88))
+#define REG_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_SEL      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x8C))
+#define REG_MDTOP_CLKSW_VCORE_DFS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x90))
+#define REG_MDTOP_CLKSW_MCORE_DFS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x94))
+#define REG_MDTOP_CLKSW_RXDDM_DFS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x98))
+#define REG_MDTOP_CLKSW_RXDBRP_DFS_FLEXCKGEN_SEL    (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x9C))
+
+#define REG_MDTOP_CLKSW_FETXBSRP_DFS_FLEXCKGEN_SEL  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA4))
+#define REG_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA8))
+#define REG_MDTOP_CLKSW_NR_RXT2F_DFS_FLEXCKGEN_SEL  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xAC))
+#define REG_MDTOP_CLKSW_CPC_FLEXCKGEN_SEL           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB0))
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB4))
+#define REG_MDTOP_CLKSW_RXDFE_DFS_FLEXCKGEN_SEL     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB8))
+#define REG_MDTOP_CLKSW_BUS2X_NODCM_FLEXCKGEN_SEL   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xBC))
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FIXED_FLEXCKGEN_SEL   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC0))
+
+/* ==========FLEXCKGEN_STS========== */
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xCC))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_STS          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD0))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_STS         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD4))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_STS           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD8))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_STS           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xDC))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_STS       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE0))
+#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_STS       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE4))
+#define REG_MDTOP_CLKSW_MDPLL_FLEXCKGEN_STS         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE8))
+
+#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_STS      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF0))
+#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_STS       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF4))
+#define REG_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_STS   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF8))
+#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_STS      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xFC))
+#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_STS       (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x100))
+#define REG_MDTOP_CLKSW_NR_CS_DFS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x104))
+#define REG_MDTOP_CLKSW_NR_CM_DFS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x108))
+#define REG_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_STS      (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10C))
+#define REG_MDTOP_CLKSW_VCORE_DFS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x110))
+#define REG_MDTOP_CLKSW_MCORE_DFS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x114))
+#define REG_MDTOP_CLKSW_RXDDM_DFS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x118))
+#define REG_MDTOP_CLKSW_RXDBRP_DFS_FLEXCKGEN_STS    (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x11C))
+
+#define REG_MDTOP_CLKSW_FETXBSRP_DFS_FLEXCKGEN_STS  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x124))
+#define REG_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x12C))
+#define REG_MDTOP_CLKSW_NR_RXT2F_DFS_FLEXCKGEN_STS  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x130))
+#define REG_MDTOP_CLKSW_CPC_FLEXCKGEN_STS           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x134))
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x138))
+#define REG_MDTOP_CLKSW_RXDFE_DFS_FLEXCKGEN_STS     (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x13C))
+#define REG_MDTOP_CLKSW_BUS2X_NODCM_FLEXCKGEN_STS   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x140))
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FIXED_FLEXCKGEN_STS   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x144))
+
+#define REG_MDTOP_CLKSW_CKMUX_STS                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x200))
+#define REG_MDTOP_CLKSW_PLL_STS	                    (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x210))
+#define REG_MDTOP_CLKSW_DFS_STS	                    (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x220))
+#define REG_MDTOP_CLKSW_DFS_STS_2                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x224))
+
+/* ==========direct pll request========== */
+#define REG_MDTOP_CLKSW_MDMCU_DIRECT_PLLREQ         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x300))
+#define REG_MDTOP_CLKSW_MDBUS_DIRECT_PLLREQ         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x304))
+#define REG_MDTOP_CLKSW_VDSP_DIRECT_PLLREQ          (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x308))
+#define REG_MDTOP_CLKSW_BRP_DIRECT_PLLREQ           (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x30C))
+
+/* ==========Frequency Meter========== */
+#define REG_MDTOP_CLKSW_CKMON_CTL                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x400))
+#define REG_MDTOP_CLKSW_FREQ_METER_CTL              (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x404))
+#define REG_MDTOP_CLKSW_FREQ_METER_XTAL_CNT         (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x408))
+#define REG_MDTOP_CLKSW_FREQ_METER_CKMON_CNT        (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x40C))
+#define REG_MDTOP_CLKSW_FREQ_METER_H                (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x410))
+#define REG_MDTOP_CLKSW_FREQ_METER_L                (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x414))
+
+#define REG_MDTOP_CLKSW_CLK_REQ_MON                 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x500))
+#define REG_MDTOP_CLKSW_CLK_RDY_MON                 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x504))
+
+/* ==========DUMMY & STATUS========== */
+#define REG_MDTOP_CLKSW_CLK_DUMMY                   (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF00))
+#define REG_MDTOP_CLKSW_CLK_STATUS                  (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF04))
+
+
+/*******************************************************************************
+ * Define Macro
+ ******************************************************************************/
+#define MD_PLL_MAGIC_NUM 0x62970000
+#define MD_PLL_MAGIC_26M 0x62970026
+#define MD_PLL_MAGIC_MD  0x62971111
+
+
+ /*------------------------------------------------------------------------
+ * Purpose:     Transfer PCW in xxxPLL_STS to Mhz. This macro is porting from md_dvfs_pll_freq_get(const PLL_SOURCE pll).
+ * Parameters:
+ *    Input:    pcw:    The PCW value in xxxPLL_STS.
+ *              divier: The divier for this PLL(EX: ICCPLL_DIVIDER, IMCPLL_DIVIDER...).
+ *    Output:   None.
+ * returns :    Mhz. 
+ * Note    :    This macr is only used to transfer pcw in xxxPLL_STS to Mhz. 
+ *              You should not used this macro to transfer pcw in xxxPLL_CTL0 to Mhz due to the meaning is different.
+ *              (PCW in xxxPLL_STS is bit [21:7] of xxxPLL_CTL0.)
+ *------------------------------------------------------------------------
+ */
+#define PLLMIXED_PLL_STS_SDM_PCW_TO_MHZ(pcw, divier)   ((((pcw) * 26) / (1 << 7)) / divier)
+
+/*******************************************************************************
+ * ENUM
+ ******************************************************************************/
+// frequency meter index list (debug only)
+typedef enum {
+    PLL_FM_SOURCE_START            = 0x0,
+    PLL_FM_AD_MDNRPLL5             = 0x0,
+    PLL_FM_AD_MDNRPLL4_1           = 0x1,
+    PLL_FM_AD_MDNRPLL4_0           = 0x2,
+    PLL_FM_AD_MDNRPLL3             = 0x3,    
+    PLL_FM_AD_MDNRPLL2             = 0x4, 
+    PLL_FM_AD_MDNRPLL1             = 0x5, 
+    PLL_FM_AD_MDNRPLL0             = 0x6, 
+    PLL_FM_MDSYS_NRL2_CLOCK        = 0x7, // NRL2 = MML2
+    PLL_FM_MDRXSYS_DFESYNC_CLOCK   = 0x8,    
+    PLL_FM_MDTOP_F216P7M_CLOCK     = 0x9,
+    PLL_FM_TRACE_MON_CLOCK         = 0xA,  
+    PLL_FM_MDSYS_216P7M_CLOCK      = 0xB,   
+    PLL_FM_MDRXSYS_RAKE_CLOCK      = 0xC,    
+    PLL_FM_MDRXSYS_BRP_CLOCK       = 0xD,
+    PLL_FM_MDRXSYS_VDSP_CLOCK      = 0xE,   
+    PLL_FM_MDTOP_LOG_ATB_CLOCK     = 0xF,
+    PLL_FM_FESYS_CSYS_CLOCK        = 0x10,
+    PLL_FM_MDSYS_SHAOLIN_CLOCK     = 0x11,
+    PLL_FM_FESYS_BSI_CLOCK         = 0x12,
+    PLL_FM_MDSYS_MDCORE_CLOCK      = 0x13, 
+    PLL_FM_MDSYS_BUS2X_NODCM_CLOCK = 0x14, 
+    PLL_FM_MDSYS_BUS4X_CLOCK       = 0x15,
+    PLL_FM_MDTOP_DBG_CLOCK         = 0x16,
+    PLL_FM_MDTOP_F32K_CLOCK        = 0x17,
+    PLL_FM_AD_MDBPI_PLL_D7         = 0x18, /* AD means "analog to digital" */
+    PLL_FM_AD_MDBPI_PLL_D5         = 0x19,
+    PLL_FM_AD_MDBPI_PLL_D4         = 0x1A,
+    PLL_FM_AD_MDBPI_PLL_D3         = 0x1B,
+    PLL_FM_AD_MDBPI_PLL_D2         = 0x1C, 
+    PLL_FM_AD_MDBRP_PLL            = 0x1D,
+    PLL_FM_AD_MDVDSP_PLL           = 0x1E,
+    PLL_FM_AD_MDMCU_PLL            = 0x1F,
+    /* CKMON_SRC_SEL2 = 1 */ 
+
+    PLL_FM_DFESYS_RXDFE_BB_CORE_CLOCK = 0x2E,
+    PLL_FM_AD_MDNRPLL4_2              = 0x2F,  
+    PLL_FM_MDTOP_BUS4X_FIXED_CLOCK    = 0x30,    
+    PLL_FM_DA_DRF_26M_CLOCK           = 0x31,    
+    PLL_FM_MDTOP_BUS4X_CLOCK       = 0x32,
+    PLL_FM_RXCPC_CPC_CLOCK         = 0x33,
+   
+    PLL_FM_RXDDMBRP_RXDBRP_CLOCK   = 0x35,
+    PLL_FM_RXDDMBRP_RXDDM_CLOCK    = 0x36,
+    PLL_FM_MCORE_MCORE_CLOCK       = 0x37, 
+    PLL_FM_VCOREHRAM_VCORE_CLOCK   = 0x38,
+    PLL_FM_VCOREHRAM_HRAM_CLOCK    = 0x39,
+    PLL_FM_FESYS_TXBSRP_CLOCK      = 0x3A,
+    PLL_FM_FESYS_MDPLL_CLOCK       = 0x3B,
+    PLL_FM_TX_CS_NR_RXT2F_NR_CLOCK = 0x3C,
+    PLL_FM_TX_CS_NR_TXBSRP_NR_CLOCK= 0x3D,
+    PLL_FM_TX_CS_NR_CM_NR_CLOCK    = 0x3E,
+    PLL_FM_TX_CS_NR_CS_NR_CLOCK    = 0x3F,
+    PLL_FM_SOURCE_END                 = 0x3F
+} PLL_FM_SOURCE;
+
+typedef enum {
+    CLKSW_SDF_SRC_MDPLL_F650M   = 0,
+    CLKSW_SDF_SRC_TOP_BUS4X     = 1,        
+    CLKSW_SDF_SRC_MDPLL_F325M   = 2,  
+    CLKSW_SDF_SRC_MDPLL_F216P7M = 3,
+    CLKSW_SDF_SRC_26M,    
+    CLKSW_SDF_SRC_END    
+} PLL_CLKSW_SDF_SRC;
+
+typedef enum {
+    CLKSW_SDF_SRC_DIV_1    = 0,
+    CLKSW_SDF_SRC_DIV_2    = 1,
+    CLKSW_SDF_SRC_DIV_3    = 2,
+    CLKSW_SDF_SRC_DIV_4    = 3  
+} PLL_CLKSW_SDF_SRC_DIV;
+
+/* Below for debugging */
+
+#define PLL_FM_NUM 48   /* Note: This number should also sync to EE owner. */
+typedef struct {
+    kal_uint32 AD_MDNRPLL5;             /* 0 */
+    kal_uint32 AD_MDNRPLL4_1;
+    kal_uint32 AD_MDNRPLL4_0;
+    kal_uint32 AD_MDNRPLL3;
+    kal_uint32 AD_MDNRPLL2;
+    kal_uint32 AD_MDNRPLL1;             /* 5 */
+    kal_uint32 AD_MDNRPLL0;
+    kal_uint32 MDSYS_NRL2_CLOCK;
+    kal_uint32 MDRXSYS_DFESYNC_CLOCK;
+    kal_uint32 MDTOP_F216P7M_CLOCK;
+    kal_uint32 TRACE_MON_CLOCK;         /* 10 */
+    kal_uint32 MDSYS_216P7M_CLOCK;
+    kal_uint32 MDRXSYS_RAKE_CLOCK;
+    kal_uint32 MDRXSYS_BRP_CLOCK;
+    kal_uint32 MDRXSYS_VDSP_CLOCK;    
+    kal_uint32 MDTOP_LOG_ATB_CLOCK;     /* 15 */
+    kal_uint32 FESYS_CSYS_CLOCK;
+    kal_uint32 MDSYS_SHAOLIN_CLOCK;
+    kal_uint32 FESYS_BSI_CLOCK;
+    kal_uint32 MDSYS_MDCORE_CLOCK;
+    kal_uint32 MDSYS_BUS2X_NODCM_CLOCK; /* 20 */
+    kal_uint32 MDSYS_BUS4X_CLOCK;     
+    kal_uint32 MDTOP_DBG_CLOCK;
+    kal_uint32 AD_MDBPI_PLL_D7;   
+    kal_uint32 AD_MDBPI_PLL_D5;                
+    kal_uint32 AD_MDBPI_PLL_D4;         /* 25 */    
+    kal_uint32 AD_MDBPI_PLL_D3;
+    kal_uint32 AD_MDBPI_PLL_D2; 
+    kal_uint32 AD_MDBRP_PLL;
+    kal_uint32 AD_MDVDSP_PLL;                     
+    kal_uint32 AD_MDMCU_PLL;            /* 30 */     
+    kal_uint32 DFESYS_RXDFE_BB_CORE_CLOCK; 
+    kal_uint32 AD_MDNRPLL4_2;  
+    kal_uint32 MDTOP_BUS4X_FIXED_CLOCK;    
+    kal_uint32 DA_DRF_26M_CLOCK;  
+    kal_uint32 MDTOP_BUS4X_CLOCK;       /* 35 */   
+    kal_uint32 RXCPC_CPC_CLOCK; 
+    kal_uint32 RXDDMBRP_RXDBRP_CLOCK;   
+    kal_uint32 RXDDMBRP_RXDDM_CLOCK;     
+    kal_uint32 MCORE_MCORE_CLOCK;       
+    kal_uint32 VCOREHRAM_VCORE_CLOCK;   /* 40 */
+    kal_uint32 VCOREHRAM_HRAM_CLOCK;    
+    kal_uint32 FESYS_TXBSRP_CLOCK;   
+    kal_uint32 FESYS_MDPLL_CLOCK;       
+    kal_uint32 TX_CS_NR_RXT2F_NR_CLOCK;   
+    kal_uint32 TX_CS_NR_TXBSRP_NR_CLOCK;/* 45 */  
+    kal_uint32 TX_CS_NR_CM_NR_CLOCK;   
+    kal_uint32 TX_CS_NR_CS_NR_CLOCK;
+    /* we couldn't add more PLL here... */   
+    
+} PLL_CLK_INFO;
+
+extern PLL_CLK_INFO g_pll_info;
+extern const char PLL_FM_clock[PLL_FM_NUM][32];
+
+/* Above for debugging */
+
+/*******************************************************************************
+ * Include header files
+ ******************************************************************************/
+extern void PLL_MD_Pll_Init(void);
+extern void PLL_Set_CLK_To_26M(void);
+
+extern void PLL_Check_26M_ACK_Status(kal_uint32 identifier);
+extern void PLL_exception_dump(void);
+extern kal_uint32 PLL_FrequencyMeter_GetFreq(PLL_FM_SOURCE index);
+
+/* For SDF user in driver/sib_drv/sdf/src/md97/drv_sdf_97.c */
+extern kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Get();
+extern kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Div_Get();
+extern kal_bool PLL_CLKSW_SDF_SRC_CKSEL_Set(PLL_CLKSW_SDF_SRC src_clk, PLL_CLKSW_SDF_SRC_DIV src_div);
+
+#endif  /* !__PLL_MT6297P_H__ */
+
diff --git a/mcu/interface/driver/devdrv/rstctl/drv_rstctl.h b/mcu/interface/driver/devdrv/rstctl/drv_rstctl.h
new file mode 100644
index 0000000..dfe834c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/rstctl/drv_rstctl.h
@@ -0,0 +1,427 @@
+#ifndef __DRV_RSTCTL_H__
+#define __DRV_RSTCTL_H__
+
+#include "cpu_info.h"   // for SYS_MCU_NUM_VPE
+
+/*Set wdt1 timeout interval as 30 sec(32768*15=0xF0000)*/
+/*Set wdt2 timeout interval as 40  secs (32768*16) = 0x80000*/
+/*Reason to change this vlaue: to distinguish system is WDT reset or simply reboot*/
+#define WDT_RSTINTERVAL_VALUE	(0x0F0000)
+#define WDT_RSTINTERVAL_VALUE2	(0x140000)
+
+#define VPE_NUM (SYS_MCU_NUM_VPE)
+
+typedef enum
+{
+ 	VPE0 = 0, 
+	VPE1,
+	VPE2,
+	VPE3,
+	VPE4,
+	VPE5,
+	VPE6,
+	VPE7,
+	VPE8,
+	VPE9,
+	VPE10,
+	VPE11,
+}vpeid_e;
+
+
+/*For RGU framework purpose. */
+
+typedef enum{
+    UT_REPORT_FAIL = -1,
+    UT_REPORT_PASS = 0,
+    UT_REPORT_NA
+}UT_REPORT_STATUS;
+
+
+typedef UT_REPORT_STATUS (*ut_testcase_fn_ptr)(kal_uint32 flags, void *param);
+
+
+typedef struct
+{
+    ut_testcase_fn_ptr _main_fn;
+    kal_uint32         flags;
+    void               *para;
+	kal_char           *description;
+	kal_char           *testplan_section;
+}ut_testcase_struct;
+
+
+typedef enum
+{
+ 	APSYS = 8, 
+	MD1SYS = 4, 
+	ARM7SYS = 2, 
+	L1SYS = 1
+}subsystem_e; 
+
+
+/*For software  reset purpose. */
+typedef enum
+{
+	RST_TARGET_MIN=0,
+
+    RST_IA_LOGGER,
+    RST_MDUART0,
+    RST_MDUART1,
+    RST_SOE,
+    RST_USIM1,
+    RST_USIM2,
+    RST_GPT,
+    RST_MDTOPSM,
+    RST_MDOST,
+    RST_TRACE,
+    RST_L1SYS,
+    RST_MML2,
+
+    /* Below enums in Gen93 is for dummy */
+	RST_MDGDMA,				//MDPERI:0
+	RST_MDGPTM,				//MDPERI:4
+	RST_MDMISC,				//MDPERI:5
+	RST_MDCIRQ,				//MDPERI:6
+	RST_I2C,				//MDPERI:7
+	RST_MDDBGSYS,			//MDPERI:8
+	RST_MDDBGSIB,			//MDPERI:9
+	//RST_GPIOMUX,			//Remove in ELBRUS
+	RST_MDEINT,				//MDPERI:10    New in ELBRUS
+	RST_MDCFGCTL,			//MDPERI:13
+	RST_MDECT,				//MDPERI:14  	!!NEW!!
+	RST_MDECTDBG,			//MDPERI:15  	!!NEW!!
+	RST_MDCLKBUS,			//MDPERI:16  	!!NEW!!
+	RST_MDCLK,				//MDPERI:17 	!!NEW!!
+	RST_PSLITE_GPT, 		//MDPERI:19   !!NEW!!
+	//RST_ARM7_PCCIF, 		//Remove in ELBRUS
+	RST_SDF,				//MDPERI:20	New in ELBRUS
+	RST_THERM,				//MDPERI:21	New in ELBRUS
+	RST_MDGPTM_L1,			//MDPERI:23	New in ELBRUS
+	RST_PSLITE_GPT_L1,		//MDPERI:24	New in ELBRUS
+
+	RST_MDINFRA_BUSMON,		//MDINFRA:0
+	//RST_MDINFRA_BOOTROM,	//Remove in ELBRUS
+	//RST_ABM,				//Remove in ELBRUS
+	RST_MDUART2, 			//MDINFRA:2
+	RST_PSPERI, 			//MDINFRA:3
+	RST_BUS_RECORD,			//MDINFRA:4
+	RST_MDMCU_PCCIF,		//MDINFRA:6		New in ELBRUS
+	RST_CK208M,				//MDINFRA:7		New in ELBRUS
+	RST_CK150M,				//MDINFRA:8		New in ELBRUS
+	RST_PPC,				//MDINFRA:9		New in ELBRUS
+	RST_MDINFRA_MDMISC,		//MDINFRA:10		New in ELBRUS
+	RST_LOGGDMA,			//MDINFRA:11		New in ELBRUS
+	RST_MDINFRA_ABM,		//MDINFRA:12		New in ELBRUS
+	RST_MDINFRA_ELM,		//MDINFRA:13		New in ELBRUS
+
+	RST_MIPS_DBG,			//MDMCU: 0
+	RST_MIPS_NRESET,			//MDMCU: 1
+	RST_MIPS_BUSMON,			//MDMCU: 2
+	//RST_PF,				//Remove in ELBRUS
+	//RST_PCMON_FIFO,		//Remove in ELBRUS
+	RST_PCMON_REG,			//MDMCU: 3
+	RST_ABM,				//MDMCU: 4	New in ELBRUS
+	RST_ELM,				//MDMCU: 5	New in ELBRUS
+	RST_MOBR,				//MDMCU: 6	New in ELBRUS
+	RST_MMBR,				//MDMCU: 7	New in ELBRUS
+	RST_L2SRAM,				//MDMCU: 8	New in ELBRUS
+	RST_ULS,				//MDMCU: 9	New in ELBRUS
+	RST_IOCU_ELM,			//MDMCU: 10	New in ELBRUS
+
+	RST_L2COP, 				//LTEL2: 0 	
+
+	RST_HSPAL2, 			//HSPAL2: 0
+	RST_TARGET_MAX,		/**< Maximum value of reset item : for correctness check */
+	RST_NULL,				//Used in drv_UT_within_RGU_framework. Some IPs do not tolerate software while programe is running. 
+	
+
+	RST_BSI_ALL,
+	RST_MDALL,
+
+	RST_MDALL_WO_SPI,
+	RST_MDALL_WO_USB,
+	RST_MDALL_WO_GPIO,
+	RST_CLDMA,			//for Yts'sreset CLDMA
+	RST_CLDMA_AO		//for Yts'sreset CLDMA
+} rst_target_e;
+
+typedef enum
+{
+	WDT_RESET,
+	WDT_IRQ_ONLY,
+} wdt_irq_e;
+
+typedef enum
+{
+	WDT,
+	AUX_WDT,
+} wdt_e;
+
+typedef enum
+{
+    RST_MIPS_LOCK = 0,
+    RST_MIPS_UNLOCK = 1,
+}rst_mips_lock_e;
+
+
+/*****************************************************************************
+ *						 function declaration                                *
+ *****************************************************************************/
+
+extern kal_bool drv_rstctl_sw_reset(rst_target_e targetIP);
+
+
+/*************************************************************************
+* FUNCTION
+*  drv_rstctl_wdt_reset
+*
+* DESCRIPTION
+*  This function is to do wdt reset
+*
+* PARAMETERS
+*    none
+*
+* RETURN VALUES
+*	none
+*
+*************************************************************************/
+extern void drv_rstctl_wdt_reset(void);
+
+extern void drv_rstctl_wdt_reset_aux(void);
+
+
+/*************************************************************************
+* FUNCTION
+*  drv_rstctl_wdt_abnReset
+*
+* DESCRIPTION
+*  This function is used to do abnormal reset
+*
+* PARAMETERS
+*    none
+*
+* RETURN VALUES
+*	none
+*
+*************************************************************************/
+extern void drv_rstctl_wdt_abnReset(void);
+
+/*************************************************************************
+* FUNCTION
+*  drv_rstctl_wdt_enableInterrupt
+*
+* DESCRIPTION
+*  This function is used to on/off irq mode
+*       reset or trigger interrupt while watchdog timout happening
+*
+* PARAMETERS
+*    none
+*
+* RETURN VALUES
+*	none
+*
+*************************************************************************/
+extern void drv_rstctl_wdt_enableInterrupt(kal_bool enable);
+
+extern void drv_rstctl_wdt_enableInterrupt_aux(kal_bool enable);
+
+
+/*************************************************************************
+* FUNCTION
+*  drv_rstctl_wd_clrSta
+*
+* DESCRIPTION
+*  This function is used to get wd timer interval(uint:512*T(32k))
+*
+* PARAMETERS
+*	none
+*
+* RETURN VALUES
+*	none
+*************************************************************************/
+extern kal_uint32 drv_rstctl_wd_getInterval(void);
+
+extern kal_uint32 drv_rstctl_wd_getInterval_aux(void);
+
+
+/*************************************************************************
+* FUNCTION
+*  drv_rstctl_wd_clrCnt
+*
+* DESCRIPTION
+*  This function is used to clear wdt cnt
+*
+* PARAMETERS
+*	cntMaskToClear
+*   0: clear both AP/MD WD Cnt
+*   MD_WDCNT_CLR: clear MD WD Cnt
+*   AP_WDCNT_CLR: clear AP WD Cnt
+*
+* RETURN VALUES
+*	none
+*************************************************************************/
+//extern void drv_rstctl_wd_clrCnt(kal_uint32 cntMaskToClear);
+
+/*************************************************************************
+* FUNCTION
+*  drv_rstctl_wdt_setInterval
+*
+* DESCRIPTION
+*  This function is used to set wd tiemr
+*
+* PARAMETERS
+*    none
+*
+* RETURN VALUES
+*	none
+*
+* NOTE
+*    Need to restart wdt timer to apply this value
+*************************************************************************/
+extern void drv_rstctl_wdt_setInterval(kal_uint32 wdtInterval);
+
+extern void drv_rstctl_wdt_setInterval_aux(kal_uint32 wdtInterval);
+
+
+/*************************************************************************
+* FUNCTION
+*  drv_rstctl_wd_kick
+*
+* DESCRIPTION
+*  This function is used to retart wd tiemr
+*
+* PARAMETERS
+*    none
+*
+* RETURN VALUES
+*	none
+*************************************************************************/
+extern void drv_rstctl_restartWDT(void);
+
+/*************************************************************************
+* FUNCTION
+*  drv_rstctl_wdt_init
+*
+* DESCRIPTION
+*  This function is to initialize the WDT module
+*
+* PARAMETERS
+*    none
+*
+* RETURN VALUES
+*	none
+*
+*************************************************************************/
+extern void drv_rstctl_wdt_init(void);
+
+extern void drv_rstctl_wdt_init_aux(void);
+
+
+/*************************************************************************
+* FUNCTION
+*  drv_rstctl_wdt_enableDebugMode
+*
+* DESCRIPTION
+*  This function is used to on/off debug mode
+*
+* PARAMETERS
+*	cntMaskToClear
+*   0: clear both AP/MD WD Cnt
+*   MD_WDCNT_CLR: clear MD WD Cnt
+*   AP_WDCNT_CLR: clear AP WD Cnt
+*
+* RETURN VALUES
+*	none
+*************************************************************************/
+extern void drv_rstctl_wdt_enableDebugMode(kal_bool enable);
+
+/*************************************************************************
+* FUNCTION
+*  drv_rstctl_wdt_enable
+*
+* DESCRIPTION
+*  This function is used to on/off wd timer
+*
+* PARAMETERS
+*    none
+*
+* RETURN VALUES
+*	none
+*
+* NOTE
+*    Need to restart wdt timer to apply this value
+*************************************************************************/
+extern void drv_rstctl_wdt_enable(kal_bool en);
+
+extern void drv_rstctl_wdt_enable_aux(kal_bool en);
+
+extern void drv_rstctl_set_check_bit(vpeid_e vpe);
+
+extern void drv_rstctl_clr_check_bit(vpeid_e vpe);
+
+extern void drv_rstctl_set_kick_bit(vpeid_e vpe);
+
+extern void drv_rstctl_clr_kick_bit(vpeid_e vpe);
+
+/*************************************************************************
+* FUNCTION
+*  drv_rstctl_disable_all_WDTs
+*
+* DESCRIPTION
+*  This function is used to disable all WDTs (APRGU, MDRGU, L1RGU, ARM7RGU)
+* 
+*
+* PARAMETERS
+*   None. 
+*
+* RETURN VALUES
+*	KAL_TRUE: SUCCESSFULY disable all WDTs. 
+*	KAL_FALSE: FAIL to disable all WDTs.  
+*
+* NOTE
+*************************************************************************/
+extern kal_bool drv_rstctl_disable_all_WDTs(void); 
+
+
+/*************************************************************************
+* FUNCTION
+*  drv_rstctl_A7_unlock
+*
+* DESCRIPTION
+*  This function is used to unlock ARM7 hrst
+*
+* PARAMETERS
+*	lock:   RST_A7_LOCK:
+*            RST_A7_UNLOCK:
+*
+* RETURN VALUES
+*	none
+*
+*************************************************************************/
+
+void drv_rstctl_MIPS_unlock(rst_mips_lock_e lock);
+
+extern void mips_isr_mdwdt_handler(void);
+
+extern void invalidate_WDTBASE(void);
+
+extern UT_REPORT_STATUS drv_UT_within_RGU_framework(rst_target_e targetIP, subsystem_e target_system, subsystem_e system_coverage,
+													   ut_testcase_struct *testcase_ptr, kal_uint32 test_items, kal_uint32 delay_cycles);
+/*
+kal_uint32 Get_WATCHDOG_BASE(void);
+
+kal_uint32 Get_WATCHDOG_RESTART_CMD(void);
+*/
+kal_bool Is_WDT_Init(void);
+
+void WDT_init(void);
+void wdt_enable(kal_bool en);
+
+extern const kal_uint32 g_WATCHDOG_RESTART_REG;
+extern const kal_uint32 g_WATCHDOG_CTL_REG;
+extern const kal_uint32 g_WATCHDOG_RESTART_VALUE;
+extern const kal_uint32 g_ABNORMAL_RST_REG;
+extern const kal_uint32 g_ABNORMAL_RST_VAL;
+
+#endif /* end of __DRV_RSTCLT_H__ */
+
diff --git a/mcu/interface/driver/devdrv/rstctl/drv_rstctl.inc b/mcu/interface/driver/devdrv/rstctl/drv_rstctl.inc
new file mode 100644
index 0000000..c0cda4b
--- /dev/null
+++ b/mcu/interface/driver/devdrv/rstctl/drv_rstctl.inc
@@ -0,0 +1,29 @@
+.macro WDT_BOOT_INIT
+.set noreorder
+
+    //mfc0    a0, C0_EBASE
+    //ext     a0, a0, 0, 4
+    //bnez    a0, WDT_BOOT_INIT_DONE
+    //nop
+
+    la      a0, g_WATCHDOG_CTL_REG
+    lw      a0, 0x0(a0)
+
+    /* Load WDTCR */
+    lw      a2, 0x0(a0)
+    /* Clear BIT_0 and BIT_1 */
+    lui	    a1, 0xffff
+    ori     a1, 0xfffc
+    and     a2, a1
+    /* Disable WDT timer */
+    li      a1, RSTCTL_WDTCR_KEY
+    addu    a2, a1
+    sw      a2, 0x0(a0)
+
+    sync    0x3
+    lui     t0, 0xA1FF
+    lw	    t1,0(t0)
+    sw	    t1,0(t0)
+WDT_BOOT_INIT_DONE:
+    nop
+.endm WDT_BOOT_INIT
diff --git a/mcu/interface/driver/devdrv/thermal/drv_thermal_protect.h b/mcu/interface/driver/devdrv/thermal/drv_thermal_protect.h
new file mode 100644
index 0000000..257467a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/thermal/drv_thermal_protect.h
@@ -0,0 +1,18 @@
+#ifndef __DRV_THERMAL_PROTECT_H__
+#define __DRV_THERMAL_PROTECT_H__
+
+#include "kal_general_types.h"
+
+typedef enum {
+    thermal_sensor_dram,    /* dram refresh rate */
+    thermal_sensor_md_ntc,  /* auxadc0 */
+    thermal_sensor_pa_ntc,  /* auxadc1 */
+    thermal_sensor_num,
+} thermal_sensor_type;
+
+extern void thermal_prot_init();
+extern kal_bool thermal_prot_run();
+extern kal_bool thermal_prot_stop();
+extern kal_bool thermal_prot_set_threshold(thermal_sensor_type sensor_type, kal_int16 threshold);
+
+#endif
diff --git a/mcu/interface/driver/devdrv/tia/tia_public.h b/mcu/interface/driver/devdrv/tia/tia_public.h
new file mode 100644
index 0000000..c8e2520
--- /dev/null
+++ b/mcu/interface/driver/devdrv/tia/tia_public.h
@@ -0,0 +1,114 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2017
+*
+*  BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+*  THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+*  RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+*  AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+*  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+*  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+*  NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+*  SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+*  SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+*  THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+*  NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+*  SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+*  BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+*  LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+*  AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+*  OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+*  MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+*  THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+*  WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+*  LAWS PRINCIPLES.  ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+*  RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+*  THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ *
+ * Filename:
+ * ---------
+ *    tia_public.h
+ *
+ * Project:
+ * --------
+ *    VMOLY
+ *
+ * Description:
+ * ------------
+ *    TIA (Thermal Information Acquisition) driver public header for MD thermal
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __TIA_PUBLIC_H__
+#define __TIA_PUBLIC_H__
+
+#include "kal_general_types.h"
+#include "thermal_public.h"
+
+#if defined(__MD_TFWK__) && defined(__MTK_TARGET__)
+/**
+ * tia_get_temp - get tia temperature by sensor id
+ * @sensor_id: [in] sensor id, refer to THERMAL_TIA_SENSOR_ID(n=0~) @thermal_public.h
+ * @temp: [in,out] temperature in 1/10th of Celsius Degree
+ * @return: error code, refer to THERMAL_ERR_XXX
+ */
+kal_int32 tia_get_temp(kal_uint32 sensor_id, kal_int32 *temp);
+
+/**
+ * tia_get_temp_all - get tia temperature info array
+ * @ninfo: [in] temperature info number, must be THERMAL_TIA_SENSOR_NUM @thermal_public.h
+ * @infos: [in,out] pointer to thermal_temp_info_t list
+ * @return error code, refer to THERMAL_ERR_XXX
+ */
+kal_int32 tia_get_temp_all(kal_uint32 ninfo, thermal_temp_info_t *infos);
+
+/**
+ * tia_atcmd_public - tia public atcmd handler
+ * @data_len: [in] atcmd data length
+ * @data_str: [in] atcmd data array
+ * @return KAL_TRUE: success, KAL_FALSE: failure
+ */
+kal_bool tia_atcmd_public(kal_uint32 data_len, kal_uint8 *data_str);
+
+#ifndef NVRAM_NOT_PRESENT
+#include "thermal_nvram_def.h"
+/**
+ * tia_nvram_read_sensor_info - tia read sensor info in nvram
+ * @sensor_id: [in] sensor id, refer to THERMAL_LVTS/TIA_SENSOR_ID(n=0~) @thermal_public.h
+ * @info: [in,out] pointer to nvram_thermal_sensor_info_struct
+ * @return KAL_TRUE: success, KAL_FALSE: failure
+ */
+kal_bool tia_nvram_read_sensor_info(kal_uint32 sensor_id, nvram_thermal_sensor_info_struct *info);
+#endif
+
+#else
+#define tia_get_temp(...)               ({THERMAL_ERR_SENSOR_ID;})
+#define tia_get_temp_all(...)           ({THERMAL_ERR_SENSOR_ID;})
+#define tia_atcmd_public(...)           ({KAL_FALSE;})
+#define tia_nvram_read_sensor_info(...) ({KAL_FALSE;})
+#endif
+#endif
diff --git a/mcu/interface/driver/devdrv/us_counter/us_timer.h b/mcu/interface/driver/devdrv/us_counter/us_timer.h
new file mode 100644
index 0000000..e58b849
--- /dev/null
+++ b/mcu/interface/driver/devdrv/us_counter/us_timer.h
@@ -0,0 +1,270 @@
+/*****************************************************************************
+*  Copyright Statement:
+*  --------------------
+*  This software is protected by Copyright and the information contained
+*  herein is confidential. The software may not be copied and the information
+*  contained herein may not be used or disclosed except with the written
+*  permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ *   us_timer.h
+ *
+ * Project:
+ * --------
+ *   UMOLYE
+ *
+ * Description:
+ * ------------
+ *   Header file for providing timer of microsecond precision.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ *             HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#if !defined(__US_TIMER_H__)
+#define __US_TIMER_H__
+
+#define __HW_US_TIMER_SUPPORT__ /* avoid build error and always support */
+
+/* If define __FMA_SUPPORT__, FRC would get from FMA, or it would get from source. */
+#define __FMA_SUPPORT__
+
+#if defined (__MD93__)
+    /* MT6293 didn't support FMA in CP0. */
+#elif defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+    /* if define __FMA_IN_CP0__ ==> FMA access from CP0. if not define __FMA_IN_CP0__ ==> FMA access from GCR. */
+    #define __FMA_IN_CP0__  /* only valid when define "__FMA_SUPPORT__" */
+#else    
+    #error "Unsupported FMA platform!"
+#endif
+
+#include "reg_base.h"
+#include "cpu.h"
+#include "drv_comm.h"
+#include "boot.h"
+#include "mips_ia_utils_public.h"
+
+//For L1 simulation
+#include "md2g_drv.h"
+
+/*******************************************************************************
+ * Define registers.
+ *******************************************************************************/
+#if 1/* for all MT6293/MT6295/MT6297 projects */
+    /* MD FRC */
+    #define BASE_MD_FRC_SOURCE          BASE_ADDR_MDTOPSM  /* MD TOPSM */
+    #define BASE_MD_FMA                 GCR_CUSTOM_ADDR    /* GIC base address 0x1F010000 in boot.h */
+
+    /* MD OSTD */
+    #define MD_OST_CON                  (BASE_ADDR_MDOSTIMER + 0x10U)  /* OS Timer Control Register */
+    #define MD_OST_FRM                  (BASE_ADDR_MDOSTIMER + 0x1CU)  /* OS Timer timetick unit Register  */
+    #define MD_OST_FRAME_CNT            (BASE_ADDR_MDOSTIMER + 0x38U)  /* Current OS Timer Number [31:0] */
+    #define MD_OSTD_CMD_MAGIC_VALUE     0x057D0000
+
+    #define MD_USCNT_CON                (BASE_MD_FRC_SOURCE + 0x0800)   /* MD TOPSM control register */
+    #define MD_FRC_SOURCE_VAL           (BASE_MD_FRC_SOURCE + 0x0830)   /* MD TOPSM FRC value register, unit: 1 us */
+    #define MD_FRC_SOURCE_VAL_HIGH      (BASE_MD_FRC_SOURCE + 0x0834)   /* MD TOPSM FRC high value register, unit: 1 us */
+    #define MD_TS_SOURCE_VAL            (BASE_MD_FRC_SOURCE + 0x0840)   /* MD TOPSM FRC global timestamp register, unit: 64 us */
+
+    /* FMA get from GCR */
+    #define FMA_MD_USCNTI_VAL           (BASE_MD_FMA + 0x40)
+    #define FMA_MD_USCNTI_VAL_HIGH      (BASE_MD_FMA + 0x44)	
+    #define FMA_MD_OS_TIME_VAL          (BASE_MD_FMA + 0x48)
+    #define FMA_MD_TIMESTAMP_VAL        (BASE_MD_FMA + 0x50)  
+
+    /* backward compatible */
+    #define USCNTI_VAL            (MD_USCNTI_VAL)  
+ 
+#else /* other project */
+/* under construction !*/
+#endif
+
+#define USCNT_WRAP         0xFFFFFFFF
+
+#ifdef ESIM_BUILD_CONFIG
+    #define USCNT_START_CODE   0x62900001
+    #define USCNT_STOP_CODE    0x62900000
+#endif /* ESIM_BUILD_CONFIG */
+
+/*******************************************************************************
+ * Define macros.
+ *******************************************************************************/
+#if defined(__HW_US_TIMER_SUPPORT__) 
+    extern void USC_Start( void );
+    extern void USC_Stop( void );
+
+    extern kal_uint32 USC_Get_TimeStamp( void );
+    #if defined(__LTE_L1SIM__)
+        #define ust_get_current_time()  HW_READ(((volatile kal_uint32*)MD_USCNTI_VAL))
+        #define fma_get_glb_ts()        (ust_get_current_time()>>6)
+    #elif defined(__UE_SIMULATOR__) || defined(ESIM_BUILD_CONFIG) /* == !__MTK_TARGET__ ? */
+        extern kal_uint32 osc_platform_us_counter_get(void);
+        extern kal_uint32 osc_platform_64us_counter_get(void);
+        #define ust_get_current_time()        osc_platform_us_counter_get()
+        #define ust_get_current_time_source() osc_platform_us_counter_get()
+        #define fma_get_glb_ts()              osc_platform_64us_counter_get()
+    #elif defined(__ESL_MASE__)
+        #define ust_get_current_time()                      DRV_Reg32(BASE_USCOUNTER)
+        #define ust_get_current_time_high()                 (0)
+        #define ust_get_current_time_source()               ust_get_current_time()
+        #define ust_get_current_time_source_high()          (0)
+        #define fma_get_glb_ts()                            DRV_Reg32(BASE_GLOBAL_TS)
+        #define ust_get_os_timer()                          (ust_get_current_time()/1000)
+        #define fma_sync_status()                           (1)/* Always return 1 in ESL MASE*/
+    #elif defined(__ESL_COSIM_LTE__)
+        #define ust_get_current_time()        DRV_Reg32(0xFFFF3000)
+        #define ust_get_current_time_source() ust_get_current_time()
+        #define fma_get_glb_ts()              (ust_get_current_time()>>6)
+    #elif !defined(__MTK_TARGET__) /* Pure OSCAR */
+        extern kal_uint32 osc_platform_us_counter_get(void);
+        extern kal_uint32 osc_platform_64us_counter_get(void);
+        #define ust_get_current_time()        osc_platform_us_counter_get()
+        #define ust_get_current_time_source() osc_platform_us_counter_get()
+        #define fma_get_glb_ts()              osc_platform_64us_counter_get()
+    #else /* real use in project */
+
+        #if defined(__FMA_SUPPORT__)/* Access FMA from GCR/CP0 Register */
+
+            #define fma_sync_status()         (DRV_Reg32((kal_uint32)(BASE_MD_FMA + 0x30)))/* if the value is 1, means the FMA function is ready after leaving WFI */
+            #if defined(__FMA_IN_CP0__)/* MT6295/MT6297 */ /* Access FMA from CP0 */
+                #define ust_get_current_time()                      miu_mfc0(MIU_C0_TRACECONTROL3)
+                #define ust_get_current_time_high()                 miu_mfc0(MIU_C0_TRACECONTROL2)
+                #define ust_get_os_timer()                          miu_mfc0(MIU_C0_USERTRACEDATA1)
+                #define fma_get_glb_ts()                            miu_mfc0(MIU_C0_USERTRACEDATA2)
+            #else/* MT6293 */ /* Access FMA from GCR Register */
+                #define ust_get_current_time()                      (DRV_Reg32((kal_uint32) FMA_MD_USCNTI_VAL))
+                #define ust_get_current_time_high()                 (DRV_Reg32((kal_uint32) FMA_MD_USCNTI_VAL_HIGH))
+                #define ust_get_os_timer()                          (DRV_Reg32((kal_uint32) FMA_MD_OS_TIME_VAL))
+                #define fma_get_glb_ts()                            (DRV_Reg32((kal_uint32) FMA_MD_TIMESTAMP_VAL))                
+            #endif
+            
+        #else/* Access FMA from source Register */
+        
+            #define fma_sync_status()                           (1)/* Since no FMA, always return 1 */         
+            #define ust_get_current_time()                      (DRV_Reg32((kal_uint32) MD_FRC_SOURCE_VAL))
+            #define ust_get_current_time_high()                 (DRV_Reg32((kal_uint32) MD_FRC_SOURCE_VAL_HIGH))
+            #define ust_get_os_timer()                          (DRV_Reg32((kal_uint32) MD_OST_FRAME_CNT))
+            #define fma_get_glb_ts()                            (DRV_Reg32((kal_uint32) MD_TS_SOURCE_VAL)) 
+            
+        #endif
+        
+        #define ust_get_current_time_source()               (DRV_Reg32((kal_uint32) MD_FRC_SOURCE_VAL))
+        #define ust_get_current_time_source_high()          (DRV_Reg32((kal_uint32) MD_FRC_SOURCE_VAL_HIGH))
+    			
+    #endif
+    
+    /* Get duration, unit = us */
+    #define ust_us_duration(start, end)   (((end) >= (start))? (((end) - (start))): ((USCNT_WRAP - (start) + (end) + 1)))
+
+#else   /* __HW_US_TIMER_SUPPORT__ */
+    #error "UMOLYA chips always support the HW US Timer"
+
+#endif  /* __HW_US_TIMER_SUPPORT__ */
+
+
+
+/**
+ * ust_busy_wait - a busy loop wait for a period
+ * @us: qbit to wait
+ *
+ * This macro contains a busy loop to wait a period of specified microsends.
+ * There is a maximal iteration count in the busy loop to prevent from infinite loop. 
+ * (EX: timer is not working.)
+ * ==> Update the design, if the ust does not work, CPU blocking at this macro.
+ *     Because it's hard to find the delay loop issue when FRC is stop.
+ */
+#if defined(__MTK_TARGET__)//Real use in target, function in uscounter.c
+extern void ust_us_busyloop(kal_uint32 us);
+#else/* for MoDIS and others */
+#define ust_us_busyloop(us)                                   \
+do {                                                          \
+    kal_uint32 t1, t2, zerocount = 0xFFFFF;                   \
+    if ((us) == 0) {break;}                                   \
+    t1 = ust_get_current_time();                              \
+    do {                                                      \
+        t2 = ust_get_current_time();                          \
+        if (t1 == t2) { zerocount--; }                        \
+        else if (ust_us_duration(t1, t2) >= (us)) { break; } \
+    } while (zerocount);                                      \
+    if(0==zerocount)                                          \
+    {                                                         \
+        kal_uint32 FRC_IS_NOT_INIT = 0;                       \
+        ASSERT(FRC_IS_NOT_INIT);                              \
+    }                                                         \
+} while (0)
+#endif
+
+#endif  /* !__US_TIMER_H__ */
+