[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/driver/devdrv/pdn/drvpdn.h b/mcu/interface/driver/devdrv/pdn/drvpdn.h
new file mode 100644
index 0000000..2192c27
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/drvpdn.h
@@ -0,0 +1,81 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * drvpdn.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * PDN Driver (C Include File)
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 04 09 2014 tungchieh.tsai
+ * [MOLY00061872] [UMOLY][TK6291][SYYSTEN SERVICE] TK6291 PDN driver porting (dummy version)
+ *
+ * Update header
+ *
+ * 03 31 2013 gh.huang
+ * [MOLY00012450] Replace sys_drv/pdn with devdrv/pdn
+ *
+ ****************************************************************************/
+
+#ifndef __DRVPDN_H__
+#define __DRVPDN_H__
+
+#include "kal_public_defs.h"
+
+#define DRVPDN_INLINE INLINE
+#define DRVPDN_INLINE_MODIFIER INLINE_MODIFIER
+
+#include "drvpdn_inline.h"
+
+#undef DRVPDN_INLINE
+#undef DRVPDN_INLINE_MODIFIER
+
+#define PDN_STATUS(dev, s, t) (s) = (t)PDN_STS((dev))
+
+#endif /* !__DRVPDN_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/drvpdn_inline.h b/mcu/interface/driver/devdrv/pdn/drvpdn_inline.h
new file mode 100644
index 0000000..497795a
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/drvpdn_inline.h
@@ -0,0 +1,116 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * drvpdn_inline.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * PDN Driver (C Inline Implementation)
+ * - PDN_SET(), PDN_CLR() is for Bus Clock Gating/Ungating
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 30 2019 devin.yang
+ * [MOLY00426701] [Mercury] [mmWare] [MD97P] Build error fix.
+ * Update PDN driver.
+ *
+ * 03 09 2018 devin.yang
+ * [MOLY00312408] [System Service] [Compile Option] Add compile option for Gen97.
+ * .
+ *
+ * 10 31 2017 devin.yang
+ * [MOLY00286526] [93/95 re-arch][System Service][PDN] Update PDN driver compile option for 93/95 re-arch.
+ * .
+ *
+ * 10 30 2017 devin.yang
+ * [MOLY00286061] [System Service][PDN][Gen93] Update PDN driver for Cervino.
+ * .
+ *
+ * 08 25 2017 devin.yang
+ * [MOLY00273777] [System Service][PDN][Gen93][MT6771][UMOLYA][LR12A.R2.MP] Update PDN driver for Sylvia.
+ * .
+ *
+ * 06 09 2017 devin.yang
+ * [MOLY00256219] [System Service][MT6739][PDN] Update PDN driver for MT6739.
+ * .
+ *
+ * 11 23 2016 devin.yang
+ * [MOLY00204129] [System Service][PDN] Porting PDN drivers for MT6293.
+ * Update MT6293 PDN driver.
+ *
+ * 09 20 2016 devin.yang
+ * [MOLY00204129] [System Service][PDN] Porting PDN drivers for MT6293.
+ * .
+ *
+ * 03 30 2016 alan-tl.lin
+ * [MOLY00171849] [GEN93] Fix build error
+ * [PLL/PDN] Add compile option for GEN93
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __DRVPDN_INLINE_H__
+#define __DRVPDN_INLINE_H__
+
+#if defined(__MD93__)
+ #include "drvpdn_inline_mt6293.h"
+ #include "drvpdn_inline_username.h"
+
+#elif defined(__MD95__)
+ #include "drvpdn_inline_mt6295.h"
+ #include "drvpdn_inline_username.h"
+
+#elif defined(__MD97__) || defined(__MD97P__)
+ #include "drvpdn_inline_mt6297.h"
+ #include "drvpdn_inline_username.h"
+
+#else
+ #error "Unsupported Chip Target in PDN Module"
+#endif
+
+#endif /* !__DRVPDN_INLINE_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6293.h b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6293.h
new file mode 100644
index 0000000..f39dc60
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6293.h
@@ -0,0 +1,932 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * drvpdn_inline_mt6293.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * PDN Driver (C Inline Implementation) for MT6293
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 03 16 2018 devin.yang
+ * [MOLY00314076] [System Service][Gen97] Fix build error and build warning.
+ * .
+ *
+ * 11 08 2017 devin.yang
+ * [MOLY00287863] [System Service][PDN][Gen95][UMOLYA] Fixed PDN driver.
+ * .
+ *
+ * 08 11 2017 devin.yang
+ * [MOLY00269905] [System Service][PDN][Gen93][UMOLYA][LR12A.R2.MP] Update PDN driver for new module clock control.
+ * .
+ *
+ * 08 10 2017 devin.yang
+ * [MOLY00269905] [System Service][PDN][Gen93][UMOLYA][LR12A.R2.MP] Update PDN driver for new module clock control.
+ * .
+ *
+ * 08 10 2017 devin.yang
+ * [MOLY00269905] [System Service][PDN][Gen93][UMOLYA][LR12A.R2.MP] Update PDN driver for new module clock control.
+ * .
+ *
+ * 02 16 2017 devin.yang
+ * [MOLY00229974] [System Service][PDN] Update PDN drivers for Bianco.
+ * .
+ *
+ * 11 23 2016 devin.yang
+ * [MOLY00204129] [System Service][PDN] Porting PDN drivers for MT6293.
+ * Update MT6293 PDN driver.
+ *
+ * 05 31 2016 alan-tl.lin
+ * [MOLY00174466] [UMOLYA] PLL porting
+ * Disable PDN function for build error
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __DRVPDN_INLINE_ELBRUS_H__
+#define __DRVPDN_INLINE_ELBRUS_H__
+
+/*******************************************************************************
+ * Locally Used Options
+ *******************************************************************************/
+#define EXTRA_EXPORT 0
+#define INTERRUPT_PROTECT 0
+
+#define DISABLE_PDN_FOR_ISSUE (0) // Temporary for Issue Clarification, disable all PDN function.
+ #define DISABLE_PDN_MDINFRA (0) /* Disable specified PDN function for debug */
+ #define DISABLE_PDN_MDPERI (0) /* Disable specified PDN function for debug */
+ #define DISABLE_PDN_MDL1AO (0) /* Disable specified PDN function for debug */
+ #define DISABLE_PDN_DEBUG_PERI_MISC (0) /* Disable specified PDN function for debug */
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "intrCtrl.h"
+#include "pdn_hw_mt6293_series.h"
+#include "sync_data.h"
+
+/* For Build pass */
+#define PDN_MDUART2 0
+#define PDN_LOGGDMA_HCLK 0
+#define PDN_L1_GDMA 0
+
+typedef enum {
+ /* MD INFRA */
+ PDN_MDUART1,
+ PDN_BUSMON,
+ PDN_SOE,
+ PDN_LOGTOP_BCLK,
+ PDN_MDINFRA_ELM_ACLK,
+ PDN_MDINFRA_ELM_FCLK,
+ PDN_MDINFRA_ELM_F26M,
+ PDN_FCS_SLV_DBCLK,
+ PDN_GCU_SLV_DBCLK,
+ PDN_TRACE_BUS2X,
+ PDN_PPPHA_CLK,
+ PDN_SDF_HCLK,
+ PDN_TRACE_PIPE,
+ PDN_TRACE_LINK,
+ PDN_TRACE_SWD,
+ PDN_LOGTOP_BUS2X,
+ PDN_MDINFRA_BUS,
+ PDN_MDINFRA_ATB_CK,
+ PDN_MDINFRA_DBG_CK,
+
+ /* MD PERI */
+ PDN_MDUART0,
+ PDN_MDGDMA,
+ PDN_MDGPTM,
+ PDN_USIM1_BCLK,
+ PDN_USIM2_BCLK,
+ PDN_MDEINT,
+ PDN_USIM1,
+ PDN_USIM2,
+ PDN_MDECT,
+ PDN_MDCIRQ,
+ PDN_THERM_SLOW,
+ PDN_MDPERI_DBG,
+ PDN_TRACE_26M,
+ PDN_MDGPTM_26M,
+ PDN_MDPERI_BUS,
+ PDN_MDDBGSYS_DCM,
+
+ /* MDL1AO */
+ PDN_C2KDO_TMR,
+ PDN_C2KDO_SLP,
+ PDN_C2K1X_TMR,
+ PDN_C2K1X_SLP,
+ PDN_TDMA_SLP,
+ PDN_TDD_TMR,
+ PDN_TDD_SLP,
+ PDN_FDD_TMR,
+ PDN_FDD_SLP,
+ PDN_LTE_TMR,
+ PDN_LTE_SLP,
+ PDN_IDC_CTRL,
+ PDN_BPI,
+ PDN_BSI,
+ PDN_IDC_UART,
+ PDN_DVFS_CTRL,
+ PDN_FREQM,
+ PDN_C1X_TTR,
+ PDN_CDO_TTR,
+
+ /* IA DEBUG PERI MISC */
+ PDN_RG_ASM_CK,
+ PDN_RG_PDA_MON_CK,
+
+ PDN_MAX_DEV
+} PDN_DEVICE;
+
+#if defined(__MTK_TARGET__)
+/* spinlock for IA_DEBUG_PERI_MISC_CLK_CTRL */
+extern kal_spinlockid pdn_cg_spinlock;
+
+#define PDN_TAKE_SPINLOCK() kal_take_spinlock(pdn_cg_spinlock, KAL_INFINITE_WAIT)
+#define PDN_GIVE_SPINLOCK() kal_give_spinlock(pdn_cg_spinlock)
+#else
+
+#define PDN_TAKE_SPINLOCK()
+#define PDN_GIVE_SPINLOCK()
+#endif
+
+#if (DISABLE_PDN_FOR_ISSUE)
+
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_SET(PDN_DEVICE dev) {};
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_CLR(PDN_DEVICE dev) {};
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE kal_uint32 PDN_STS(PDN_DEVICE dev) {return 0;};
+
+#else // !DISABLE_PDN_FOR_ISSUE
+
+#define DRVPDN_REG(addr) *(volatile kal_uint32 *)(addr)
+
+/******************************************************************************
+ * Gate clock macros(Disable clock)
+ ******************************************************************************/
+
+#if !(DISABLE_PDN_MDINFRA)
+#define DRVPDN_MDINFRA_OFF(module) \
+ do { \
+ DRVPDN_REG(MD_INFRA_CKEN_CLR) = (kal_uint32)(CG_ ## module); \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDINFRA_OFF(module)
+#endif
+
+#if !(DISABLE_PDN_MDPERI)
+#define DRVPDN_MDPERI_OFF(module) \
+ do { \
+ DRVPDN_REG(MD_PERI_CKEN_CLR) = (kal_uint32)(CG_ ## module);\
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDPERI_OFF(module)
+#endif
+
+#if !(DISABLE_PDN_MDL1AO)
+#define DRVPDN_MDL1AO_OFF(module) \
+ do { \
+ DRVPDN_REG(MDL1AO_PDN_SET) = (kal_uint32)(CG_ ## module); \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDL1AO_PERI_OFF(module)
+#endif
+
+#if !(DISABLE_PDN_DEBUG_PERI_MISC)
+#define DRVPDN_DEBUG_PERI_MISC_OFF(module) \
+ do { \
+ DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) &= ~(kal_uint32)(CG_ ## module); \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_DEBUG_PERI_MISC_OFF(module)
+#endif
+
+/******************************************************************************
+ * Un-gate clock macros(Enable clock)
+ ******************************************************************************/
+
+#if !(DISABLE_PDN_MDINFRA)
+#define DRVPDN_MDINFRA_ON(module) \
+ do { \
+ DRVPDN_REG(MD_INFRA_CKEN_SET) = (kal_uint32)(CG_ ## module); \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDINFRA_ON(module)
+#endif
+
+#if !(DISABLE_PDN_MDPERI)
+#define DRVPDN_MDPERI_ON(module) \
+ do { \
+ DRVPDN_REG(MD_PERI_CKEN_SET) = (kal_uint32)(CG_ ## module); \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDPERI_ON(module)
+#endif
+
+#if !(DISABLE_PDN_MDL1AO)
+#define DRVPDN_MDL1AO_ON(module) \
+ do { \
+ DRVPDN_REG(MDL1AO_PDN_CLR) = (kal_uint32)(CG_ ## module); \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDL1AO_PERI_ON(module)
+#endif
+
+#if !(DISABLE_PDN_DEBUG_PERI_MISC)
+#define DRVPDN_DEBUG_PERI_MISC_ON(module) \
+ do { \
+ DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) |= (kal_uint32)(CG_ ## module); \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_DEBUG_PERI_MISC_ON(module)
+#endif
+
+/******************************************************************************
+ * Get clock status macros
+ ******************************************************************************/
+
+#define DRVPDN_MDINFRA_STS(module) ((~(DRVPDN_REG(MD_INFRA_CKEN))) & (CG_ ## module))
+#define DRVPDN_MDPERI_STS(module) ((~(DRVPDN_REG(MD_PERI_CKEN))) & (CG_ ## module))
+#define DRVPDN_MDL1AO_STS(module) (DRVPDN_REG(MDL1AO_CON20) & (CG_ ## module))
+#define DRVPDN_DEBUG_PERI_MISC_STS(module) ((~(DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL))) & (CG_ ## module))
+
+ /*------------------------------------------------------------------------
+ * void PDN_SET(PDN_DEVICE dev)
+ * Purpose: Disable clock of specified module.
+ * Parameters:
+ * Input: PDN_DEVICE dev: PDN_xxx, module index.
+ * Output: None
+ * returns : None
+ * Note : None
+ *
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_SET(PDN_DEVICE dev)
+{
+ #if INTERRUPT_PROTECT
+ kal_uint32 mask;
+ mask = SaveAndSetIRQMask();
+ #endif
+
+ switch (dev)
+ { /* MD INFRA */
+ case PDN_MDUART1:
+ DRVPDN_MDINFRA_OFF(MDUART1);
+ break;
+ case PDN_BUSMON:
+ DRVPDN_MDINFRA_OFF(BUSMON);
+ break;
+ case PDN_SOE:
+ DRVPDN_MDINFRA_OFF(SOE);
+ break;
+ case PDN_LOGTOP_BCLK:
+ DRVPDN_MDINFRA_OFF(LOGTOP_BCLK);
+ break;
+ case PDN_MDINFRA_ELM_ACLK:
+ DRVPDN_MDINFRA_OFF(MDINFRA_ELM_ACLK);
+ break;
+ case PDN_MDINFRA_ELM_FCLK:
+ DRVPDN_MDINFRA_OFF(MDINFRA_ELM_FCLK);
+ break;
+ case PDN_MDINFRA_ELM_F26M:
+ DRVPDN_MDINFRA_OFF(MDINFRA_ELM_F26M);
+ break;
+ case PDN_FCS_SLV_DBCLK:
+ DRVPDN_MDINFRA_OFF(FCS_SLV_DBCLK);
+ break;
+ case PDN_GCU_SLV_DBCLK:
+ DRVPDN_MDINFRA_OFF(GCU_SLV_DBCLK);
+ break;
+ case PDN_TRACE_BUS2X:
+ DRVPDN_MDINFRA_OFF(TRACE_BUS2X);
+ break;
+ case PDN_PPPHA_CLK:
+ DRVPDN_MDINFRA_OFF(PPPHA_CLK);
+ break;
+ case PDN_SDF_HCLK:
+ DRVPDN_MDINFRA_OFF(SDF_HCLK);
+ break;
+ case PDN_TRACE_PIPE:
+ DRVPDN_MDINFRA_OFF(TRACE_PIPE);
+ break;
+ case PDN_TRACE_LINK:
+ DRVPDN_MDINFRA_OFF(TRACE_LINK);
+ break;
+ case PDN_TRACE_SWD:
+ DRVPDN_MDINFRA_OFF(TRACE_SWD);
+ break;
+ case PDN_LOGTOP_BUS2X:
+ DRVPDN_MDINFRA_OFF(LOGTOP_BUS2X);
+ break;
+ case PDN_MDINFRA_BUS:
+ DRVPDN_MDINFRA_OFF(MDINFRA_BUS);
+ break;
+ case PDN_MDINFRA_ATB_CK:
+ DRVPDN_MDINFRA_OFF(MDINFRA_ATB_CK);
+ break;
+ case PDN_MDINFRA_DBG_CK:
+ DRVPDN_MDINFRA_OFF(MDINFRA_DBG_CK);
+ break;
+
+ /* MD PERI */
+ case PDN_MDUART0:
+ DRVPDN_MDPERI_OFF(MDUART0);
+ break;
+ case PDN_MDGDMA:
+ DRVPDN_MDPERI_OFF(MDGDMA);
+ break;
+ case PDN_MDGPTM:
+ DRVPDN_MDPERI_OFF(MDGPTM);
+ break;
+ case PDN_USIM1_BCLK:
+ DRVPDN_MDPERI_OFF(USIM1_BCLK);
+ break;
+ case PDN_USIM2_BCLK:
+ DRVPDN_MDPERI_OFF(USIM2_BCLK);
+ break;
+ case PDN_MDEINT:
+ DRVPDN_MDPERI_OFF(MDEINT);
+ break;
+ case PDN_USIM1:
+ DRVPDN_MDPERI_OFF(USIM1);
+ break;
+ case PDN_USIM2:
+ DRVPDN_MDPERI_OFF(USIM2);
+ break;
+ case PDN_MDECT:
+ DRVPDN_MDPERI_OFF(MDECT);
+ break;
+ case PDN_MDCIRQ:
+ DRVPDN_MDPERI_OFF(MDCIRQ);
+ break;
+ case PDN_THERM_SLOW:
+ DRVPDN_MDPERI_OFF(THERM_SLOW);
+ break;
+ case PDN_MDPERI_DBG:
+ DRVPDN_MDPERI_OFF(MDPERI_DBG);
+ break;
+ case PDN_TRACE_26M:
+ DRVPDN_MDPERI_OFF(TRACE_26M);
+ break;
+ case PDN_MDGPTM_26M:
+ DRVPDN_MDPERI_OFF(MDGPTM_26M);
+ break;
+ case PDN_MDPERI_BUS:
+ DRVPDN_MDPERI_OFF(MDPERI_BUS);
+ break;
+ case PDN_MDDBGSYS_DCM:
+ DRVPDN_MDPERI_OFF(MDDBGSYS_DCM);
+ break;
+
+ /* MDL1AO */
+ case PDN_C2KDO_TMR:
+ DRVPDN_MDL1AO_OFF(C2KDO_TMR);
+ break;
+ case PDN_C2KDO_SLP:
+ DRVPDN_MDL1AO_OFF(C2KDO_SLP);
+ break;
+ case PDN_C2K1X_TMR:
+ DRVPDN_MDL1AO_OFF(C2K1X_TMR);
+ break;
+ case PDN_C2K1X_SLP:
+ DRVPDN_MDL1AO_OFF(C2K1X_SLP);
+ break;
+ case PDN_TDMA_SLP:
+ DRVPDN_MDL1AO_OFF(TDMA_SLP);
+ break;
+ case PDN_TDD_TMR:
+ DRVPDN_MDL1AO_OFF(TDD_TMR);
+ break;
+ case PDN_TDD_SLP:
+ DRVPDN_MDL1AO_OFF(TDD_SLP);
+ break;
+ case PDN_FDD_TMR:
+ DRVPDN_MDL1AO_OFF(FDD_TMR);
+ break;
+ case PDN_FDD_SLP:
+ DRVPDN_MDL1AO_OFF(FDD_SLP);
+ break;
+ case PDN_LTE_TMR:
+ DRVPDN_MDL1AO_OFF(LTE_TMR);
+ break;
+ case PDN_LTE_SLP:
+ DRVPDN_MDL1AO_OFF(LTE_SLP);
+ break;
+ case PDN_IDC_CTRL:
+ DRVPDN_MDL1AO_OFF(IDC_CTRL);
+ break;
+ case PDN_BPI:
+ DRVPDN_MDL1AO_OFF(BPI);
+ break;
+ case PDN_BSI:
+ DRVPDN_MDL1AO_OFF(BSI);
+ break;
+ case PDN_IDC_UART:
+ DRVPDN_MDL1AO_OFF(IDC_UART);
+ break;
+ case PDN_DVFS_CTRL:
+ DRVPDN_MDL1AO_OFF(DVFS_CTRL);
+ break;
+ case PDN_FREQM:
+ DRVPDN_MDL1AO_OFF(FREQM);
+ break;
+ case PDN_C1X_TTR:
+ DRVPDN_MDL1AO_OFF(C1X_TTR);
+ break;
+ case PDN_CDO_TTR:
+ DRVPDN_MDL1AO_OFF(CDO_TTR);
+ break;
+
+ /* IA DEBUG PERI MISC */
+ case PDN_RG_ASM_CK:
+ PDN_TAKE_SPINLOCK();
+ DRVPDN_DEBUG_PERI_MISC_OFF(RG_ASM_CK);
+ PDN_GIVE_SPINLOCK();
+ break;
+ case PDN_RG_PDA_MON_CK:
+ PDN_TAKE_SPINLOCK();
+ DRVPDN_DEBUG_PERI_MISC_OFF(RG_PDA_MON_CK);
+ PDN_GIVE_SPINLOCK();
+ break;
+
+ case PDN_MAX_DEV:
+ break;
+ }
+
+ #if INTERRUPT_PROTECT
+ RestoreIRQMask(mask);
+ #endif
+}
+
+ /*------------------------------------------------------------------------
+ * void PDN_CLR(PDN_DEVICE dev)
+ * Purpose: Enable clock of specified module.
+ * Parameters:
+ * Input: PDN_DEVICE dev: PDN_xxx, module index.
+ * Output: None
+ * returns : None
+ * Note : None
+ *
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_CLR(PDN_DEVICE dev)
+{
+ #if INTERRUPT_PROTECT
+ kal_uint32 mask;
+ mask = SaveAndSetIRQMask();
+ #endif
+
+ switch (dev)
+ { /* MD INFRA */
+ case PDN_MDUART1:
+ DRVPDN_MDINFRA_ON(MDUART1);
+ break;
+ case PDN_BUSMON:
+ DRVPDN_MDINFRA_ON(BUSMON);
+ break;
+ case PDN_SOE:
+ DRVPDN_MDINFRA_ON(SOE);
+ break;
+ case PDN_LOGTOP_BCLK:
+ DRVPDN_MDINFRA_ON(LOGTOP_BCLK);
+ break;
+ case PDN_MDINFRA_ELM_ACLK:
+ DRVPDN_MDINFRA_ON(MDINFRA_ELM_ACLK);
+ break;
+ case PDN_MDINFRA_ELM_FCLK:
+ DRVPDN_MDINFRA_ON(MDINFRA_ELM_FCLK);
+ break;
+ case PDN_MDINFRA_ELM_F26M:
+ DRVPDN_MDINFRA_ON(MDINFRA_ELM_F26M);
+ break;
+ case PDN_FCS_SLV_DBCLK:
+ DRVPDN_MDINFRA_ON(FCS_SLV_DBCLK);
+ break;
+ case PDN_GCU_SLV_DBCLK:
+ DRVPDN_MDINFRA_ON(GCU_SLV_DBCLK);
+ break;
+ case PDN_TRACE_BUS2X:
+ DRVPDN_MDINFRA_ON(TRACE_BUS2X);
+ break;
+ case PDN_PPPHA_CLK:
+ DRVPDN_MDINFRA_ON(PPPHA_CLK);
+ break;
+ case PDN_SDF_HCLK:
+ DRVPDN_MDINFRA_ON(SDF_HCLK);
+ break;
+ case PDN_TRACE_PIPE:
+ DRVPDN_MDINFRA_ON(TRACE_PIPE);
+ break;
+ case PDN_TRACE_LINK:
+ DRVPDN_MDINFRA_ON(TRACE_LINK);
+ break;
+ case PDN_TRACE_SWD:
+ DRVPDN_MDINFRA_ON(TRACE_SWD);
+ break;
+ case PDN_LOGTOP_BUS2X:
+ DRVPDN_MDINFRA_ON(LOGTOP_BUS2X);
+ break;
+ case PDN_MDINFRA_BUS:
+ DRVPDN_MDINFRA_ON(MDINFRA_BUS);
+ break;
+ case PDN_MDINFRA_ATB_CK:
+ DRVPDN_MDINFRA_ON(MDINFRA_ATB_CK);
+ break;
+ case PDN_MDINFRA_DBG_CK:
+ DRVPDN_MDINFRA_ON(MDINFRA_DBG_CK);
+ break;
+
+ /* MD PERI */
+ case PDN_MDUART0:
+ DRVPDN_MDPERI_ON(MDUART0);
+ break;
+ case PDN_MDGDMA:
+ DRVPDN_MDPERI_ON(MDGDMA);
+ break;
+ case PDN_MDGPTM:
+ DRVPDN_MDPERI_ON(MDGPTM);
+ break;
+ case PDN_USIM1_BCLK:
+ DRVPDN_MDPERI_ON(USIM1_BCLK);
+ break;
+ case PDN_USIM2_BCLK:
+ DRVPDN_MDPERI_ON(USIM2_BCLK);
+ break;
+ case PDN_MDEINT:
+ DRVPDN_MDPERI_ON(MDEINT);
+ break;
+ case PDN_USIM1:
+ DRVPDN_MDPERI_ON(USIM1);
+ break;
+ case PDN_USIM2:
+ DRVPDN_MDPERI_ON(USIM2);
+ break;
+ case PDN_MDECT:
+ DRVPDN_MDPERI_ON(MDECT);
+ break;
+ case PDN_MDCIRQ:
+ DRVPDN_MDPERI_ON(MDCIRQ);
+ break;
+ case PDN_THERM_SLOW:
+ DRVPDN_MDPERI_ON(THERM_SLOW);
+ break;
+ case PDN_MDPERI_DBG:
+ DRVPDN_MDPERI_ON(MDPERI_DBG);
+ break;
+ case PDN_TRACE_26M:
+ DRVPDN_MDPERI_ON(TRACE_26M);
+ break;
+ case PDN_MDGPTM_26M:
+ DRVPDN_MDPERI_ON(MDGPTM_26M);
+ break;
+ case PDN_MDPERI_BUS:
+ DRVPDN_MDPERI_ON(MDPERI_BUS);
+ break;
+ case PDN_MDDBGSYS_DCM:
+ DRVPDN_MDPERI_ON(MDDBGSYS_DCM);
+ break;
+
+ /* MDL1AO */
+ case PDN_C2KDO_TMR:
+ DRVPDN_MDL1AO_ON(C2KDO_TMR);
+ break;
+ case PDN_C2KDO_SLP:
+ DRVPDN_MDL1AO_ON(C2KDO_SLP);
+ break;
+ case PDN_C2K1X_TMR:
+ DRVPDN_MDL1AO_ON(C2K1X_TMR);
+ break;
+ case PDN_C2K1X_SLP:
+ DRVPDN_MDL1AO_ON(C2K1X_SLP);
+ break;
+ case PDN_TDMA_SLP:
+ DRVPDN_MDL1AO_ON(TDMA_SLP);
+ break;
+ case PDN_TDD_TMR:
+ DRVPDN_MDL1AO_ON(TDD_TMR);
+ break;
+ case PDN_TDD_SLP:
+ DRVPDN_MDL1AO_ON(TDD_SLP);
+ break;
+ case PDN_FDD_TMR:
+ DRVPDN_MDL1AO_ON(FDD_TMR);
+ break;
+ case PDN_FDD_SLP:
+ DRVPDN_MDL1AO_ON(FDD_SLP);
+ break;
+ case PDN_LTE_TMR:
+ DRVPDN_MDL1AO_ON(LTE_TMR);
+ break;
+ case PDN_LTE_SLP:
+ DRVPDN_MDL1AO_ON(LTE_SLP);
+ break;
+ case PDN_IDC_CTRL:
+ DRVPDN_MDL1AO_ON(IDC_CTRL);
+ break;
+ case PDN_BPI:
+ DRVPDN_MDL1AO_ON(BPI);
+ break;
+ case PDN_BSI:
+ DRVPDN_MDL1AO_ON(BSI);
+ break;
+ case PDN_IDC_UART:
+ DRVPDN_MDL1AO_ON(IDC_UART);
+ break;
+ case PDN_DVFS_CTRL:
+ DRVPDN_MDL1AO_ON(DVFS_CTRL);
+ break;
+ case PDN_FREQM:
+ DRVPDN_MDL1AO_ON(FREQM);
+ break;
+ case PDN_C1X_TTR:
+ DRVPDN_MDL1AO_ON(C1X_TTR);
+ break;
+ case PDN_CDO_TTR:
+ DRVPDN_MDL1AO_ON(CDO_TTR);
+ break;
+
+ /* IA DEBUG PERI MISC */
+ case PDN_RG_ASM_CK:
+ PDN_TAKE_SPINLOCK();
+ DRVPDN_DEBUG_PERI_MISC_ON(RG_ASM_CK);
+ PDN_GIVE_SPINLOCK();
+ break;
+ case PDN_RG_PDA_MON_CK:
+ PDN_TAKE_SPINLOCK();
+ DRVPDN_DEBUG_PERI_MISC_ON(RG_PDA_MON_CK);
+ PDN_GIVE_SPINLOCK();
+ break;
+
+ case PDN_MAX_DEV:
+ break;
+ }
+
+ #if INTERRUPT_PROTECT
+ RestoreIRQMask(mask);
+ #endif
+}
+
+ /*------------------------------------------------------------------------
+ * kal_uint32 PDN_STS(PDN_DEVICE dev)
+ * Purpose: Return the clock is enable/disable of specified module.
+ * Parameters:
+ * Input: PDN_DEVICE dev: PDN_xxx, module index.
+ * Output: None
+ * returns : The clock is enable/disable of specified module.
+ * Note : None
+ *
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE kal_uint32 PDN_STS(PDN_DEVICE dev)
+{
+ kal_uint32 ret = 0;
+
+ #if INTERRUPT_PROTECT
+ kal_uint32 mask;
+ mask = SaveAndSetIRQMask();
+ #endif
+
+ switch (dev)
+ { /* MD INFRA */
+ case PDN_MDUART1:
+ ret = DRVPDN_MDINFRA_STS(MDUART1);
+ break;
+ case PDN_BUSMON:
+ ret = DRVPDN_MDINFRA_STS(BUSMON);
+ break;
+ case PDN_SOE:
+ ret = DRVPDN_MDINFRA_STS(SOE);
+ break;
+ case PDN_LOGTOP_BCLK:
+ ret = DRVPDN_MDINFRA_STS(LOGTOP_BCLK);
+ break;
+ case PDN_MDINFRA_ELM_ACLK:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_ACLK);
+ break;
+ case PDN_MDINFRA_ELM_FCLK:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_FCLK);
+ break;
+ case PDN_MDINFRA_ELM_F26M:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_F26M);
+ break;
+ case PDN_FCS_SLV_DBCLK:
+ ret = DRVPDN_MDINFRA_STS(FCS_SLV_DBCLK);
+ break;
+ case PDN_GCU_SLV_DBCLK:
+ ret = DRVPDN_MDINFRA_STS(GCU_SLV_DBCLK);
+ break;
+ case PDN_TRACE_BUS2X:
+ ret = DRVPDN_MDINFRA_STS(TRACE_BUS2X);
+ break;
+ case PDN_PPPHA_CLK:
+ ret = DRVPDN_MDINFRA_STS(PPPHA_CLK);
+ break;
+ case PDN_SDF_HCLK:
+ ret = DRVPDN_MDINFRA_STS(SDF_HCLK);
+ break;
+ case PDN_TRACE_PIPE:
+ ret = DRVPDN_MDINFRA_STS(TRACE_PIPE);
+ break;
+ case PDN_TRACE_LINK:
+ ret = DRVPDN_MDINFRA_STS(TRACE_LINK);
+ break;
+ case PDN_TRACE_SWD:
+ ret = DRVPDN_MDINFRA_STS(TRACE_SWD);
+ break;
+ case PDN_LOGTOP_BUS2X:
+ ret = DRVPDN_MDINFRA_STS(LOGTOP_BUS2X);
+ break;
+ case PDN_MDINFRA_BUS:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_BUS);
+ break;
+ case PDN_MDINFRA_ATB_CK:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_ATB_CK);
+ break;
+ case PDN_MDINFRA_DBG_CK:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_DBG_CK);
+ break;
+
+ /* MD PERI */
+ case PDN_MDUART0:
+ ret = DRVPDN_MDPERI_STS(MDUART0);
+ break;
+ case PDN_MDGDMA:
+ ret = DRVPDN_MDPERI_STS(MDGDMA);
+ break;
+ case PDN_MDGPTM:
+ ret = DRVPDN_MDPERI_STS(MDGPTM);
+ break;
+ case PDN_USIM1_BCLK:
+ ret = DRVPDN_MDPERI_STS(USIM1_BCLK);
+ break;
+ case PDN_USIM2_BCLK:
+ ret = DRVPDN_MDPERI_STS(USIM2_BCLK);
+ break;
+ case PDN_MDEINT:
+ ret = DRVPDN_MDPERI_STS(MDEINT);
+ break;
+ case PDN_USIM1:
+ ret = DRVPDN_MDPERI_STS(USIM1);
+ break;
+ case PDN_USIM2:
+ ret = DRVPDN_MDPERI_STS(USIM2);
+ break;
+ case PDN_MDECT:
+ ret = DRVPDN_MDPERI_STS(MDECT);
+ break;
+ case PDN_MDCIRQ:
+ ret = DRVPDN_MDPERI_STS(MDCIRQ);
+ break;
+ case PDN_THERM_SLOW:
+ ret = DRVPDN_MDPERI_STS(THERM_SLOW);
+ break;
+ case PDN_MDPERI_DBG:
+ ret = DRVPDN_MDPERI_STS(MDPERI_DBG);
+ break;
+ case PDN_TRACE_26M:
+ ret = DRVPDN_MDPERI_STS(TRACE_26M);
+ break;
+ case PDN_MDGPTM_26M:
+ ret = DRVPDN_MDPERI_STS(MDGPTM_26M);
+ break;
+ case PDN_MDPERI_BUS:
+ ret = DRVPDN_MDPERI_STS(MDPERI_BUS);
+ break;
+ case PDN_MDDBGSYS_DCM:
+ ret = DRVPDN_MDPERI_STS(MDDBGSYS_DCM);
+ break;
+
+ /* MDL1AO */
+ case PDN_C2KDO_TMR:
+ ret = DRVPDN_MDL1AO_STS(C2KDO_TMR);
+ break;
+ case PDN_C2KDO_SLP:
+ ret = DRVPDN_MDL1AO_STS(C2KDO_SLP);
+ break;
+ case PDN_C2K1X_TMR:
+ ret = DRVPDN_MDL1AO_STS(C2K1X_TMR);
+ break;
+ case PDN_C2K1X_SLP:
+ ret = DRVPDN_MDL1AO_STS(C2K1X_SLP);
+ break;
+ case PDN_TDMA_SLP:
+ ret = DRVPDN_MDL1AO_STS(TDMA_SLP);
+ break;
+ case PDN_TDD_TMR:
+ ret = DRVPDN_MDL1AO_STS(TDD_TMR);
+ break;
+ case PDN_TDD_SLP:
+ ret = DRVPDN_MDL1AO_STS(TDD_SLP);
+ break;
+ case PDN_FDD_TMR:
+ ret = DRVPDN_MDL1AO_STS(FDD_TMR);
+ break;
+ case PDN_FDD_SLP:
+ ret = DRVPDN_MDL1AO_STS(FDD_SLP);
+ break;
+ case PDN_LTE_TMR:
+ ret = DRVPDN_MDL1AO_STS(LTE_TMR);
+ break;
+ case PDN_LTE_SLP:
+ ret = DRVPDN_MDL1AO_STS(LTE_SLP);
+ break;
+ case PDN_IDC_CTRL:
+ ret = DRVPDN_MDL1AO_STS(IDC_CTRL);
+ break;
+ case PDN_BPI:
+ ret = DRVPDN_MDL1AO_STS(BPI);
+ break;
+ case PDN_BSI:
+ ret = DRVPDN_MDL1AO_STS(BSI);
+ break;
+ case PDN_IDC_UART:
+ ret = DRVPDN_MDL1AO_STS(IDC_UART);
+ break;
+ case PDN_DVFS_CTRL:
+ ret = DRVPDN_MDL1AO_STS(DVFS_CTRL);
+ break;
+ case PDN_FREQM:
+ ret = DRVPDN_MDL1AO_STS(FREQM);
+ break;
+ case PDN_C1X_TTR:
+ ret = DRVPDN_MDL1AO_STS(C1X_TTR);
+ break;
+ case PDN_CDO_TTR:
+ ret = DRVPDN_MDL1AO_STS(CDO_TTR);
+ break;
+
+ /* IA DEBUG PERI MISC */
+ case PDN_RG_ASM_CK:
+ ret = DRVPDN_DEBUG_PERI_MISC_STS(RG_ASM_CK);
+ break;
+ case PDN_RG_PDA_MON_CK:
+ ret = DRVPDN_DEBUG_PERI_MISC_STS(RG_PDA_MON_CK);
+ break;
+
+ case PDN_MAX_DEV:
+ break;
+ }
+
+ #if INTERRUPT_PROTECT
+ RestoreIRQMask(mask);
+ #endif
+
+ return ret;
+}
+
+#endif // DISABLE_PDN_FOR_ISSUE
+
+#endif /* !__DRVPDN_INLINE_ELBRUS_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6295.h b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6295.h
new file mode 100644
index 0000000..c1db04c
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6295.h
@@ -0,0 +1,937 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * drvpdn_inline_mt6295.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * PDN Driver (C Inline Implementation) for MT6295
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 06 29 2018 devin.yang
+ * [MOLY00336176] [System Service] [PDN] [Gen95] Fix PDN driver potential bug.
+ * Comment out ASM and PDAmon PDN driver.
+ *
+ * 03 16 2018 devin.yang
+ * [MOLY00314076] [System Service][Gen97] Fix build error and build warning.
+ * .
+ *
+ * 11 08 2017 devin.yang
+ * [MOLY00287863] [System Service][PDN][Gen95][UMOLYA] Fixed PDN driver.
+ * .
+ *
+ * 09 22 2017 devin.yang
+ * [MOLY00244578] [System Service][MT6295M][PDN] Update PDN driver for MT6295M.
+ * Using atomic operation for ASM/PDAmon clock control instead of spinlock.
+ *
+ * 08 09 2017 devin.yang
+ * [MOLY00244578] [System Service][MT6295M][PDN] Update PDN driver for MT6295M.
+ * .
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __DRVPDN_INLINE_MT6295_H__
+#define __DRVPDN_INLINE_MT6295_H__
+
+/*******************************************************************************
+ * Locally Used Options
+ *******************************************************************************/
+//#define EXTRA_EXPORT 0
+//#define INTERRUPT_PROTECT 0
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "intrCtrl.h"
+#include "pdn_hw_mt6295_series.h"
+#include "sync_data.h"
+
+/*******************************************************************************
+ * Locally Used Options
+ *******************************************************************************/
+#define DISABLE_PDN_FOR_ISSUE (0) /* Temporary for Issue Clarification, disable all PDN function. */
+ #define DISABLE_PDN_MDINFRA (0) /* Disable specified PDN function for debug */
+ #define DISABLE_PDN_MDPERI (0) /* Disable specified PDN function for debug */
+ #define DISABLE_PDN_MDL1AO (0) /* Disable specified PDN function for debug */
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+ #define DISABLE_PDN_DEBUG_PERI_MISC (0) /* Disable specified PDN function for debug */
+#endif
+
+typedef enum {
+ /* MD INFRA */
+ PDN_MDUART1,
+ PDN_BUSMON,
+ PDN_SOE,
+ PDN_LOGTOP_BCLK,
+ PDN_MDINFRA_ELM_ACLK,
+ PDN_MDINFRA_ELM_FCLK,
+ PDN_MDINFRA_ELM_F26M,
+ PDN_FCS_SLV_DBCLK,
+ PDN_TRACE_BUS2X,
+ PDN_PPPHA_CLK,
+ PDN_SDF_HCLK,
+ PDN_TRACE_PIPE,
+ PDN_TRACE_SWD,
+ PDN_I2C_BCLK,
+ PDN_LOGTOP_BUS2X,
+ PDN_MDINFRA_BUS,
+ PDN_MDINFRA_ATB_CK,
+ PDN_MDINFRA_DBG_CK,
+
+ /* MD PERI */
+ PDN_MDUART0,
+ PDN_MDGDMA,
+ PDN_MDGPTM,
+ PDN_USIM1_BCLK,
+ PDN_USIM2_BCLK,
+ PDN_MDEINT,
+ PDN_LOW_PWR_DBG_MON,
+ PDN_USIM1,
+ PDN_USIM2,
+ PDN_MDECT,
+ PDN_MDCIRQ,
+ PDN_THERM_SLOW,
+ PDN_MDPERI_DBG,
+ PDN_TRACE_26M,
+ PDN_MDGPTM_26M,
+ PDN_MDPERI_BUS,
+ PDN_MDDBGSYS_BUS,
+
+ /* MDL1AO */
+ PDN_C2KDO_TMR,
+ PDN_C2KDO_SLP,
+ PDN_C2K1X_TMR,
+ PDN_C2K1X_SLP,
+ PDN_TDMA_SLP,
+ PDN_TDD_TMR,
+ PDN_TDD_SLP,
+ PDN_FDD_TMR,
+ PDN_FDD_SLP,
+ PDN_LTE_TMR,
+ PDN_LTE_SLP,
+ PDN_IDC_CTRL,
+ PDN_BPI,
+ PDN_BSI,
+ PDN_IDC_UART,
+ PDN_DVFS_CTRL,
+ PDN_FREQM,
+ PDN_C1X_TTR,
+ PDN_CDO_TTR,
+ PDN_MM_EVENTGEN,
+ PDN_CDO_EVENTGEN,
+ PDN_C1X_EVENTGEN,
+ PDN_TDD_EVENTGEN,
+ PDN_FDD_EVENTGEN,
+ PDN_LTE_EVENTGEN,
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+ /* IA DEBUG PERI MISC */
+ PDN_RG_ASM_CK,
+ PDN_RG_PDA_MON_CK,
+#endif
+
+ PDN_MAX_DEV
+} PDN_DEVICE;
+
+
+#if (DISABLE_PDN_FOR_ISSUE)
+
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_SET(PDN_DEVICE dev) {};
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_CLR(PDN_DEVICE dev) {};
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE kal_bool PDN_STS(PDN_DEVICE dev) {return 0;};
+
+#else /* !DISABLE_PDN_FOR_ISSUE */
+
+#define DRVPDN_REG(addr) *(volatile kal_uint32 *)(addr)
+
+/******************************************************************************
+ * Gate clock macros (Disable clock)
+ ******************************************************************************/
+
+#if !(DISABLE_PDN_MDINFRA)
+#define DRVPDN_MDINFRA_OFF(module) \
+ do { \
+ DRVPDN_REG(MD_INFRA_CKEN_CLR) = (kal_uint32)module; \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDINFRA_OFF(module)
+#endif
+
+#if !(DISABLE_PDN_MDPERI)
+#define DRVPDN_MDPERI_OFF(module) \
+ do { \
+ DRVPDN_REG(MD_PERI_CKEN_CLR) = (kal_uint32)module; \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDPERI_OFF(module)
+#endif
+
+#if !(DISABLE_PDN_MDL1AO)
+#define DRVPDN_MDL1AO_OFF(module) \
+ do { \
+ DRVPDN_REG(MDL1AO_PDN_SET) = (kal_uint32)module; \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDL1AO_OFF(module)
+#endif
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+#if !(DISABLE_PDN_DEBUG_PERI_MISC)
+#define DRVPDN_DEBUG_PERI_MISC_OFF(module) \
+ do { \
+ DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) = DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) & (~module) \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_DEBUG_PERI_MISC_OFF(module)
+#endif
+#endif
+
+/******************************************************************************
+ * Un-gate clock macros (Enable clock)
+ ******************************************************************************/
+
+#if !(DISABLE_PDN_MDINFRA)
+#define DRVPDN_MDINFRA_ON(module) \
+ do { \
+ DRVPDN_REG(MD_INFRA_CKEN_SET) = (kal_uint32)module; \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDINFRA_ON(module)
+#endif
+
+#if !(DISABLE_PDN_MDPERI)
+#define DRVPDN_MDPERI_ON(module) \
+ do { \
+ DRVPDN_REG(MD_PERI_CKEN_SET) = (kal_uint32)module; \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDPERI_ON(module)
+#endif
+
+#if !(DISABLE_PDN_MDL1AO)
+#define DRVPDN_MDL1AO_ON(module) \
+ do { \
+ DRVPDN_REG(MDL1AO_PDN_CLR) = (kal_uint32)module; \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDL1AO_ON(module)
+#endif
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+#if !(DISABLE_PDN_DEBUG_PERI_MISC)
+#define DRVPDN_DEBUG_PERI_MISC_ON(module) \
+ do { \
+ DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) = DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) | module \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_DEBUG_PERI_MISC_ON(module)
+#endif
+#endif
+
+/******************************************************************************
+ * Get clock status macros
+ ******************************************************************************/
+
+#define DRVPDN_MDINFRA_STS(module) !(!((~(DRVPDN_REG(MD_INFRA_CKEN))) & module))
+#define DRVPDN_MDPERI_STS(module) !(!((~(DRVPDN_REG(MD_PERI_CKEN))) & module))
+#define DRVPDN_MDL1AO_STS(module) !(!(DRVPDN_REG(MDL1AO_CON20) & module))
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+#define DRVPDN_DEBUG_PERI_MISC_STS(module) !(!((~(DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL))) & module))
+#endif
+
+ /*------------------------------------------------------------------------
+ * void PDN_SET(PDN_DEVICE dev)
+ * Purpose: Disable clock of specified module.
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_SET(PDN_DEVICE dev)
+{
+ switch (dev)
+ { /* MD INFRA */
+ case PDN_MDUART1:
+ DRVPDN_MDINFRA_OFF(MDUART1_CK);
+ break;
+ case PDN_BUSMON:
+ DRVPDN_MDINFRA_OFF(BUSMON_CK);
+ break;
+ case PDN_SOE:
+ DRVPDN_MDINFRA_OFF(SOE_CK);
+ break;
+ case PDN_LOGTOP_BCLK:
+ DRVPDN_MDINFRA_OFF(LOGTOP_BCLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_ACLK:
+ DRVPDN_MDINFRA_OFF(MDINFRA_ELM_ACLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_FCLK:
+ DRVPDN_MDINFRA_OFF(MDINFRA_ELM_FCLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_F26M:
+ DRVPDN_MDINFRA_OFF(MDINFRA_ELM_F26M_CK);
+ break;
+ case PDN_FCS_SLV_DBCLK:
+ DRVPDN_MDINFRA_OFF(FCS_SLV_DBCLK_CK);
+ break;
+ case PDN_TRACE_BUS2X:
+ DRVPDN_MDINFRA_OFF(TRACE_BUS2X_CK);
+ break;
+ case PDN_PPPHA_CLK:
+ DRVPDN_MDINFRA_OFF(PPPHA_CLK_CK);
+ break;
+ case PDN_SDF_HCLK:
+ DRVPDN_MDINFRA_OFF(SDF_HCLK_CK);
+ break;
+ case PDN_TRACE_PIPE:
+ DRVPDN_MDINFRA_OFF(TRACE_PIPE_CK);
+ break;
+ case PDN_TRACE_SWD:
+ DRVPDN_MDINFRA_OFF(TRACE_SWD_CK);
+ break;
+ case PDN_I2C_BCLK:
+ DRVPDN_MDINFRA_OFF(I2C_BCLK_CK);
+ break;
+ case PDN_LOGTOP_BUS2X:
+ DRVPDN_MDINFRA_OFF(LOGTOP_BUS2X_CK);
+ break;
+ case PDN_MDINFRA_BUS:
+ DRVPDN_MDINFRA_OFF(MDINFRA_BUS_CG);
+ break;
+ case PDN_MDINFRA_ATB_CK:
+ DRVPDN_MDINFRA_OFF(MDINFRA_ATB_CK);
+ break;
+ case PDN_MDINFRA_DBG_CK:
+ DRVPDN_MDINFRA_OFF(MDINFRA_DBG_CK);
+ break;
+
+ /* MD PERI */
+ case PDN_MDUART0:
+ DRVPDN_MDPERI_OFF(MDUART0_CK);
+ break;
+ case PDN_MDGDMA:
+ DRVPDN_MDPERI_OFF(MDGDMA_CK);
+ break;
+ case PDN_MDGPTM:
+ DRVPDN_MDPERI_OFF(MDGPTM_CK);
+ break;
+ case PDN_USIM1_BCLK:
+ DRVPDN_MDPERI_OFF(USIM1_BCLK_CK);
+ break;
+ case PDN_USIM2_BCLK:
+ DRVPDN_MDPERI_OFF(USIM2_BCLK_CK);
+ break;
+ case PDN_MDEINT:
+ DRVPDN_MDPERI_OFF(MDEINT_CK);
+ break;
+ case PDN_LOW_PWR_DBG_MON:
+ DRVPDN_MDPERI_OFF(LOW_PWR_DBG_MON_CK);
+ break;
+ case PDN_USIM1:
+ DRVPDN_MDPERI_OFF(USIM1_CK);
+ break;
+ case PDN_USIM2:
+ DRVPDN_MDPERI_OFF(USIM2_CK);
+ break;
+ case PDN_MDECT:
+ DRVPDN_MDPERI_OFF(MDECT_CK);
+ break;
+ case PDN_MDCIRQ:
+ DRVPDN_MDPERI_OFF(MDCIRQ_CK);
+ break;
+ case PDN_THERM_SLOW:
+ DRVPDN_MDPERI_OFF(THERM_SLOW_CK);
+ break;
+ case PDN_MDPERI_DBG:
+ DRVPDN_MDPERI_OFF(MDPERI_DBG_CK);
+ break;
+ case PDN_TRACE_26M:
+ DRVPDN_MDPERI_OFF(TRACE_26M_CK);
+ break;
+ case PDN_MDGPTM_26M:
+ DRVPDN_MDPERI_OFF(MDGPTM_26M_CK);
+ break;
+ case PDN_MDPERI_BUS:
+ DRVPDN_MDPERI_OFF(MDPERI_BUS_CG);
+ break;
+ case PDN_MDDBGSYS_BUS:
+ DRVPDN_MDPERI_OFF(MDDBGSYS_BUS_CK);
+ break;
+
+ /* MDL1AO */
+ case PDN_C2KDO_TMR:
+ DRVPDN_MDL1AO_OFF(C2KDO_TMR_CK);
+ break;
+ case PDN_C2KDO_SLP:
+ DRVPDN_MDL1AO_OFF(C2KDO_SLP_CK);
+ break;
+ case PDN_C2K1X_TMR:
+ DRVPDN_MDL1AO_OFF(C2K1X_TMR_CK);
+ break;
+ case PDN_C2K1X_SLP:
+ DRVPDN_MDL1AO_OFF(C2K1X_SLP_CK);
+ break;
+ case PDN_TDMA_SLP:
+ DRVPDN_MDL1AO_OFF(TDMA_SLP_CK);
+ break;
+ case PDN_TDD_TMR:
+ DRVPDN_MDL1AO_OFF(TDD_TMR_CK);
+ break;
+ case PDN_TDD_SLP:
+ DRVPDN_MDL1AO_OFF(TDD_SLP_CK);
+ break;
+ case PDN_FDD_TMR:
+ DRVPDN_MDL1AO_OFF(FDD_TMR_CK);
+ break;
+ case PDN_FDD_SLP:
+ DRVPDN_MDL1AO_OFF(FDD_SLP_CK);
+ break;
+ case PDN_LTE_TMR:
+ DRVPDN_MDL1AO_OFF(LTE_TMR_CK);
+ break;
+ case PDN_LTE_SLP:
+ DRVPDN_MDL1AO_OFF(LTE_SLP_CK);
+ break;
+ case PDN_IDC_CTRL:
+ DRVPDN_MDL1AO_OFF(IDC_CTRL_CK);
+ break;
+ case PDN_BPI:
+ DRVPDN_MDL1AO_OFF(BPI_CK);
+ break;
+ case PDN_BSI:
+ DRVPDN_MDL1AO_OFF(BSI_CK);
+ break;
+ case PDN_IDC_UART:
+ DRVPDN_MDL1AO_OFF(IDC_UART_CK);
+ break;
+ case PDN_DVFS_CTRL:
+ DRVPDN_MDL1AO_OFF(DVFS_CTRL_CK);
+ break;
+ case PDN_FREQM:
+ DRVPDN_MDL1AO_OFF(FREQM_CK);
+ break;
+ case PDN_C1X_TTR:
+ DRVPDN_MDL1AO_OFF(C1X_TTR_CK);
+ break;
+ case PDN_CDO_TTR:
+ DRVPDN_MDL1AO_OFF(CDO_TTR_CK);
+ break;
+ case PDN_MM_EVENTGEN:
+ DRVPDN_MDL1AO_OFF(MM_EVENTGEN_CK);
+ break;
+ case PDN_CDO_EVENTGEN:
+ DRVPDN_MDL1AO_OFF(CDO_EVENTGEN_CK);
+ break;
+ case PDN_C1X_EVENTGEN:
+ DRVPDN_MDL1AO_OFF(C1X_EVENTGEN_CK);
+ break;
+ case PDN_TDD_EVENTGEN:
+ DRVPDN_MDL1AO_OFF(TDD_EVENTGEN_CK);
+ break;
+ case PDN_FDD_EVENTGEN:
+ DRVPDN_MDL1AO_OFF(FDD_EVENTGEN_CK);
+ break;
+ case PDN_LTE_EVENTGEN:
+ DRVPDN_MDL1AO_OFF(LTE_EVENTGEN_CK);
+ break;
+
+ #if defined(PDN_ASM_PDAMON_SUPPORT)
+ /* IA DEBUG PERI MISC */
+ case PDN_RG_ASM_CK:
+ DRVPDN_DEBUG_PERI_MISC_OFF(RG_ASM_CK);
+ break;
+ case PDN_RG_PDA_MON_CK:
+ DRVPDN_DEBUG_PERI_MISC_OFF(RG_PDA_MON_CK);
+ break;
+ #endif
+
+ case PDN_MAX_DEV:
+ break;
+ }
+
+}
+
+ /*------------------------------------------------------------------------
+ * void PDN_CLR(PDN_DEVICE dev)
+ * Purpose: Enable clock of specified module.
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_CLR(PDN_DEVICE dev)
+{
+ switch (dev)
+ { /* MD INFRA */
+ case PDN_MDUART1:
+ DRVPDN_MDINFRA_ON(MDUART1_CK);
+ break;
+ case PDN_BUSMON:
+ DRVPDN_MDINFRA_ON(BUSMON_CK);
+ break;
+ case PDN_SOE:
+ DRVPDN_MDINFRA_ON(SOE_CK);
+ break;
+ case PDN_LOGTOP_BCLK:
+ DRVPDN_MDINFRA_ON(LOGTOP_BCLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_ACLK:
+ DRVPDN_MDINFRA_ON(MDINFRA_ELM_ACLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_FCLK:
+ DRVPDN_MDINFRA_ON(MDINFRA_ELM_FCLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_F26M:
+ DRVPDN_MDINFRA_ON(MDINFRA_ELM_F26M_CK);
+ break;
+ case PDN_FCS_SLV_DBCLK:
+ DRVPDN_MDINFRA_ON(FCS_SLV_DBCLK_CK);
+ break;
+ case PDN_TRACE_BUS2X:
+ DRVPDN_MDINFRA_ON(TRACE_BUS2X_CK);
+ break;
+ case PDN_PPPHA_CLK:
+ DRVPDN_MDINFRA_ON(PPPHA_CLK_CK);
+ break;
+ case PDN_SDF_HCLK:
+ DRVPDN_MDINFRA_ON(SDF_HCLK_CK);
+ break;
+ case PDN_TRACE_PIPE:
+ DRVPDN_MDINFRA_ON(TRACE_PIPE_CK);
+ break;
+ case PDN_TRACE_SWD:
+ DRVPDN_MDINFRA_ON(TRACE_SWD_CK);
+ break;
+ case PDN_I2C_BCLK:
+ DRVPDN_MDINFRA_ON(I2C_BCLK_CK);
+ break;
+ case PDN_LOGTOP_BUS2X:
+ DRVPDN_MDINFRA_ON(LOGTOP_BUS2X_CK);
+ break;
+ case PDN_MDINFRA_BUS:
+ DRVPDN_MDINFRA_ON(MDINFRA_BUS_CG);
+ break;
+ case PDN_MDINFRA_ATB_CK:
+ DRVPDN_MDINFRA_ON(MDINFRA_ATB_CK);
+ break;
+ case PDN_MDINFRA_DBG_CK:
+ DRVPDN_MDINFRA_ON(MDINFRA_DBG_CK);
+ break;
+
+ /* MD PERI */
+ case PDN_MDUART0:
+ DRVPDN_MDPERI_ON(MDUART0_CK);
+ break;
+ case PDN_MDGDMA:
+ DRVPDN_MDPERI_ON(MDGDMA_CK);
+ break;
+ case PDN_MDGPTM:
+ DRVPDN_MDPERI_ON(MDGPTM_CK);
+ break;
+ case PDN_USIM1_BCLK:
+ DRVPDN_MDPERI_ON(USIM1_BCLK_CK);
+ break;
+ case PDN_USIM2_BCLK:
+ DRVPDN_MDPERI_ON(USIM2_BCLK_CK);
+ break;
+ case PDN_MDEINT:
+ DRVPDN_MDPERI_ON(MDEINT_CK);
+ break;
+ case PDN_LOW_PWR_DBG_MON:
+ DRVPDN_MDPERI_ON(LOW_PWR_DBG_MON_CK);
+ break;
+ case PDN_USIM1:
+ DRVPDN_MDPERI_ON(USIM1_CK);
+ break;
+ case PDN_USIM2:
+ DRVPDN_MDPERI_ON(USIM2_CK);
+ break;
+ case PDN_MDECT:
+ DRVPDN_MDPERI_ON(MDECT_CK);
+ break;
+ case PDN_MDCIRQ:
+ DRVPDN_MDPERI_ON(MDCIRQ_CK);
+ break;
+ case PDN_THERM_SLOW:
+ DRVPDN_MDPERI_ON(THERM_SLOW_CK);
+ break;
+ case PDN_MDPERI_DBG:
+ DRVPDN_MDPERI_ON(MDPERI_DBG_CK);
+ break;
+ case PDN_TRACE_26M:
+ DRVPDN_MDPERI_ON(TRACE_26M_CK);
+ break;
+ case PDN_MDGPTM_26M:
+ DRVPDN_MDPERI_ON(MDGPTM_26M_CK);
+ break;
+ case PDN_MDPERI_BUS:
+ DRVPDN_MDPERI_ON(MDPERI_BUS_CG);
+ break;
+ case PDN_MDDBGSYS_BUS:
+ DRVPDN_MDPERI_ON(MDDBGSYS_BUS_CK);
+ break;
+
+ /* MDL1AO */
+ case PDN_C2KDO_TMR:
+ DRVPDN_MDL1AO_ON(C2KDO_TMR_CK);
+ break;
+ case PDN_C2KDO_SLP:
+ DRVPDN_MDL1AO_ON(C2KDO_SLP_CK);
+ break;
+ case PDN_C2K1X_TMR:
+ DRVPDN_MDL1AO_ON(C2K1X_TMR_CK);
+ break;
+ case PDN_C2K1X_SLP:
+ DRVPDN_MDL1AO_ON(C2K1X_SLP_CK);
+ break;
+ case PDN_TDMA_SLP:
+ DRVPDN_MDL1AO_ON(TDMA_SLP_CK);
+ break;
+ case PDN_TDD_TMR:
+ DRVPDN_MDL1AO_ON(TDD_TMR_CK);
+ break;
+ case PDN_TDD_SLP:
+ DRVPDN_MDL1AO_ON(TDD_SLP_CK);
+ break;
+ case PDN_FDD_TMR:
+ DRVPDN_MDL1AO_ON(FDD_TMR_CK);
+ break;
+ case PDN_FDD_SLP:
+ DRVPDN_MDL1AO_ON(FDD_SLP_CK);
+ break;
+ case PDN_LTE_TMR:
+ DRVPDN_MDL1AO_ON(LTE_TMR_CK);
+ break;
+ case PDN_LTE_SLP:
+ DRVPDN_MDL1AO_ON(LTE_SLP_CK);
+ break;
+ case PDN_IDC_CTRL:
+ DRVPDN_MDL1AO_ON(IDC_CTRL_CK);
+ break;
+ case PDN_BPI:
+ DRVPDN_MDL1AO_ON(BPI_CK);
+ break;
+ case PDN_BSI:
+ DRVPDN_MDL1AO_ON(BSI_CK);
+ break;
+ case PDN_IDC_UART:
+ DRVPDN_MDL1AO_ON(IDC_UART_CK);
+ break;
+ case PDN_DVFS_CTRL:
+ DRVPDN_MDL1AO_ON(DVFS_CTRL_CK);
+ break;
+ case PDN_FREQM:
+ DRVPDN_MDL1AO_ON(FREQM_CK);
+ break;
+ case PDN_C1X_TTR:
+ DRVPDN_MDL1AO_ON(C1X_TTR_CK);
+ break;
+ case PDN_CDO_TTR:
+ DRVPDN_MDL1AO_ON(CDO_TTR_CK);
+ break;
+ case PDN_MM_EVENTGEN:
+ DRVPDN_MDL1AO_ON(MM_EVENTGEN_CK);
+ break;
+ case PDN_CDO_EVENTGEN:
+ DRVPDN_MDL1AO_ON(CDO_EVENTGEN_CK);
+ break;
+ case PDN_C1X_EVENTGEN:
+ DRVPDN_MDL1AO_ON(C1X_EVENTGEN_CK);
+ break;
+ case PDN_TDD_EVENTGEN:
+ DRVPDN_MDL1AO_ON(TDD_EVENTGEN_CK);
+ break;
+ case PDN_FDD_EVENTGEN:
+ DRVPDN_MDL1AO_ON(FDD_EVENTGEN_CK);
+ break;
+ case PDN_LTE_EVENTGEN:
+ DRVPDN_MDL1AO_ON(LTE_EVENTGEN_CK);
+ break;
+
+ #if defined(PDN_ASM_PDAMON_SUPPORT)
+ /* IA DEBUG PERI MISC */
+ case PDN_RG_ASM_CK:
+ DRVPDN_DEBUG_PERI_MISC_ON(RG_ASM_CK);
+ break;
+ case PDN_RG_PDA_MON_CK:
+ DRVPDN_DEBUG_PERI_MISC_ON(RG_PDA_MON_CK);
+ break;
+ #endif
+
+ case PDN_MAX_DEV:
+ break;
+ }
+
+}
+
+ /*------------------------------------------------------------------------
+ * kal_bool PDN_STS(PDN_DEVICE dev)
+ * Purpose: Return the clock is enable/disable of specified module.
+ * Return :
+ * ret = 1. PDN is Set (Clock is Disabled)
+ * ret = 0. PDN is Clear (Clock is Enabled)
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE kal_bool PDN_STS(PDN_DEVICE dev)
+{
+ kal_bool ret = 0;
+
+ switch (dev)
+ { /* MD INFRA */
+ case PDN_MDUART1:
+ ret = DRVPDN_MDINFRA_STS(MDUART1_CK);
+ break;
+ case PDN_BUSMON:
+ ret = DRVPDN_MDINFRA_STS(BUSMON_CK);
+ break;
+ case PDN_SOE:
+ ret = DRVPDN_MDINFRA_STS(SOE_CK);
+ break;
+ case PDN_LOGTOP_BCLK:
+ ret = DRVPDN_MDINFRA_STS(LOGTOP_BCLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_ACLK:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_ACLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_FCLK:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_FCLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_F26M:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_F26M_CK);
+ break;
+ case PDN_FCS_SLV_DBCLK:
+ ret = DRVPDN_MDINFRA_STS(FCS_SLV_DBCLK_CK);
+ break;
+ case PDN_TRACE_BUS2X:
+ ret = DRVPDN_MDINFRA_STS(TRACE_BUS2X_CK);
+ break;
+ case PDN_PPPHA_CLK:
+ ret = DRVPDN_MDINFRA_STS(PPPHA_CLK_CK);
+ break;
+ case PDN_SDF_HCLK:
+ ret = DRVPDN_MDINFRA_STS(SDF_HCLK_CK);
+ break;
+ case PDN_TRACE_PIPE:
+ ret = DRVPDN_MDINFRA_STS(TRACE_PIPE_CK);
+ break;
+ case PDN_TRACE_SWD:
+ ret = DRVPDN_MDINFRA_STS(TRACE_SWD_CK);
+ break;
+ case PDN_I2C_BCLK:
+ ret = DRVPDN_MDINFRA_STS(I2C_BCLK_CK);
+ break;
+ case PDN_LOGTOP_BUS2X:
+ ret = DRVPDN_MDINFRA_STS(LOGTOP_BUS2X_CK);
+ break;
+ case PDN_MDINFRA_BUS:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_BUS_CG);
+ break;
+ case PDN_MDINFRA_ATB_CK:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_ATB_CK);
+ break;
+ case PDN_MDINFRA_DBG_CK:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_DBG_CK);
+ break;
+
+ /* MD PERI */
+ case PDN_MDUART0:
+ ret = DRVPDN_MDPERI_STS(MDUART0_CK);
+ break;
+ case PDN_MDGDMA:
+ ret = DRVPDN_MDPERI_STS(MDGDMA_CK);
+ break;
+ case PDN_MDGPTM:
+ ret = DRVPDN_MDPERI_STS(MDGPTM_CK);
+ break;
+ case PDN_USIM1_BCLK:
+ ret = DRVPDN_MDPERI_STS(USIM1_BCLK_CK);
+ break;
+ case PDN_USIM2_BCLK:
+ ret = DRVPDN_MDPERI_STS(USIM2_BCLK_CK);
+ break;
+ case PDN_MDEINT:
+ ret = DRVPDN_MDPERI_STS(MDEINT_CK);
+ break;
+ case PDN_LOW_PWR_DBG_MON:
+ ret = DRVPDN_MDPERI_STS(LOW_PWR_DBG_MON_CK);
+ break;
+ case PDN_USIM1:
+ ret = DRVPDN_MDPERI_STS(USIM1_CK);
+ break;
+ case PDN_USIM2:
+ ret = DRVPDN_MDPERI_STS(USIM2_CK);
+ break;
+ case PDN_MDECT:
+ ret = DRVPDN_MDPERI_STS(MDECT_CK);
+ break;
+ case PDN_MDCIRQ:
+ ret = DRVPDN_MDPERI_STS(MDCIRQ_CK);
+ break;
+ case PDN_THERM_SLOW:
+ ret = DRVPDN_MDPERI_STS(THERM_SLOW_CK);
+ break;
+ case PDN_MDPERI_DBG:
+ ret = DRVPDN_MDPERI_STS(MDPERI_DBG_CK);
+ break;
+ case PDN_TRACE_26M:
+ ret = DRVPDN_MDPERI_STS(TRACE_26M_CK);
+ break;
+ case PDN_MDGPTM_26M:
+ ret = DRVPDN_MDPERI_STS(MDGPTM_26M_CK);
+ break;
+ case PDN_MDPERI_BUS:
+ ret = DRVPDN_MDPERI_STS(MDPERI_BUS_CG);
+ break;
+ case PDN_MDDBGSYS_BUS:
+ ret = DRVPDN_MDPERI_STS(MDDBGSYS_BUS_CK);
+ break;
+
+ /* MDL1AO */
+ case PDN_C2KDO_TMR:
+ ret = DRVPDN_MDL1AO_STS(C2KDO_TMR_CK);
+ break;
+ case PDN_C2KDO_SLP:
+ ret = DRVPDN_MDL1AO_STS(C2KDO_SLP_CK);
+ break;
+ case PDN_C2K1X_TMR:
+ ret = DRVPDN_MDL1AO_STS(C2K1X_TMR_CK);
+ break;
+ case PDN_C2K1X_SLP:
+ ret = DRVPDN_MDL1AO_STS(C2K1X_SLP_CK);
+ break;
+ case PDN_TDMA_SLP:
+ ret = DRVPDN_MDL1AO_STS(TDMA_SLP_CK);
+ break;
+ case PDN_TDD_TMR:
+ ret = DRVPDN_MDL1AO_STS(TDD_TMR_CK);
+ break;
+ case PDN_TDD_SLP:
+ ret = DRVPDN_MDL1AO_STS(TDD_SLP_CK);
+ break;
+ case PDN_FDD_TMR:
+ ret = DRVPDN_MDL1AO_STS(FDD_TMR_CK);
+ break;
+ case PDN_FDD_SLP:
+ ret = DRVPDN_MDL1AO_STS(FDD_SLP_CK);
+ break;
+ case PDN_LTE_TMR:
+ ret = DRVPDN_MDL1AO_STS(LTE_TMR_CK);
+ break;
+ case PDN_LTE_SLP:
+ ret = DRVPDN_MDL1AO_STS(LTE_SLP_CK);
+ break;
+ case PDN_IDC_CTRL:
+ ret = DRVPDN_MDL1AO_STS(IDC_CTRL_CK);
+ break;
+ case PDN_BPI:
+ ret = DRVPDN_MDL1AO_STS(BPI_CK);
+ break;
+ case PDN_BSI:
+ ret = DRVPDN_MDL1AO_STS(BSI_CK);
+ break;
+ case PDN_IDC_UART:
+ ret = DRVPDN_MDL1AO_STS(IDC_UART_CK);
+ break;
+ case PDN_DVFS_CTRL:
+ ret = DRVPDN_MDL1AO_STS(DVFS_CTRL_CK);
+ break;
+ case PDN_FREQM:
+ ret = DRVPDN_MDL1AO_STS(FREQM_CK);
+ break;
+ case PDN_C1X_TTR:
+ ret = DRVPDN_MDL1AO_STS(C1X_TTR_CK);
+ break;
+ case PDN_CDO_TTR:
+ ret = DRVPDN_MDL1AO_STS(CDO_TTR_CK);
+ break;
+ case PDN_MM_EVENTGEN:
+ ret = DRVPDN_MDL1AO_STS(MM_EVENTGEN_CK);
+ break;
+ case PDN_CDO_EVENTGEN:
+ ret = DRVPDN_MDL1AO_STS(CDO_EVENTGEN_CK);
+ break;
+ case PDN_C1X_EVENTGEN:
+ ret = DRVPDN_MDL1AO_STS(C1X_EVENTGEN_CK);
+ break;
+ case PDN_TDD_EVENTGEN:
+ ret = DRVPDN_MDL1AO_STS(TDD_EVENTGEN_CK);
+ break;
+ case PDN_FDD_EVENTGEN:
+ ret = DRVPDN_MDL1AO_STS(FDD_EVENTGEN_CK);
+ break;
+ case PDN_LTE_EVENTGEN:
+ ret = DRVPDN_MDL1AO_STS(LTE_EVENTGEN_CK);
+ break;
+
+ #if defined(PDN_ASM_PDAMON_SUPPORT)
+ /* IA DEBUG PERI MISC */
+ case PDN_RG_ASM_CK:
+ ret = DRVPDN_DEBUG_PERI_MISC_STS(RG_ASM_CK);
+ break;
+ case PDN_RG_PDA_MON_CK:
+ ret = DRVPDN_DEBUG_PERI_MISC_STS(RG_PDA_MON_CK);
+ break;
+ #endif
+
+ case PDN_MAX_DEV:
+ break;
+ }
+
+ return ret;
+}
+
+#endif /* DISABLE_PDN_FOR_ISSUE */
+
+
+#endif /* !__DRVPDN_INLINE_MT6295_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6297.h b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6297.h
new file mode 100644
index 0000000..0f09a1e
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_mt6297.h
@@ -0,0 +1,1016 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * drvpdn_inline_mt6297.h
+ *
+ * Project:
+ * --------
+ * UMOLYE
+ *
+ * Description:
+ * ------------
+ * PDN Driver (C Inline Implementation) for MT6297
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 06 29 2018 devin.yang
+ * [MOLY00336176] [System Service] [PDN] [Gen95] Fix PDN driver potential bug.
+ * Comment out ASM and PDAmon PDN driver.
+ *
+ * 03 16 2018 devin.yang
+ * [MOLY00314076] [System Service][Gen97] Fix build error and build warning.
+ * .
+ *
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __DRVPDN_INLINE_MT6297_H__
+#define __DRVPDN_INLINE_MT6297_H__
+
+/*******************************************************************************
+ * Locally Used Options
+ *******************************************************************************/
+//#define EXTRA_EXPORT 0
+//#define INTERRUPT_PROTECT 0
+
+/*******************************************************************************
+ * Include header files
+ *******************************************************************************/
+#include "kal_general_types.h"
+#include "intrCtrl.h"
+#include "pdn_hw_mt6297_series.h"
+#include "sync_data.h"
+
+/*******************************************************************************
+ * Locally Used Options
+ *******************************************************************************/
+#define DISABLE_PDN_FOR_ISSUE (0) /* Temporary for Issue Clarification, disable all PDN function. */
+ #define DISABLE_PDN_MDINFRA (0) /* Disable specified PDN function for debug */
+ #define DISABLE_PDN_MDPERI (0) /* Disable specified PDN function for debug */
+ #define DISABLE_PDN_MDL1AO (0) /* Disable specified PDN function for debug */
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+ #define DISABLE_PDN_DEBUG_PERI_MISC (0) /* Disable specified PDN function for debug */
+#endif
+
+typedef enum {
+ /* MD INFRA */
+ PDN_MDUART1,
+ PDN_BUSMON,
+ PDN_SOE,
+ PDN_LOGTOP_BCLK,
+ PDN_MDINFRA_ELM_ACLK,
+ PDN_MDINFRA_ELM_FCLK,
+ PDN_MDINFRA_ELM_F26M,
+ PDN_TRACE_BUS2X,
+ PDN_PPPHA_CLK,
+ PDN_SDF_HCLK,
+ PDN_TRACE_PIPE,
+ PDN_TRACE_SWD,
+ PDN_I2C_BCLK,
+ PDN_LOGTOP_BUS2X,
+ PDN_SDF_ATB_CPHY,
+ PDN_MDINFRA_BUS,
+ PDN_TRACE_ATB_CPHY,
+ PDN_MDINFRA_ATB_CK,
+ PDN_MDINFRA_DBG_CK,
+
+ /* MD PERI */
+ PDN_MDUART0,
+ PDN_MDGDMA,
+ PDN_MDGPTM,
+ PDN_MDGDMA_FORDSP,
+ PDN_USIM1_BCLK,
+ PDN_USIM2_BCLK,
+ PDN_MDEINT,
+ PDN_LOW_PWR_DBG_MON,
+ PDN_USIM1,
+ PDN_USIM2,
+ PDN_MDECT,
+ PDN_MDCIRQ,
+ PDN_THERM_SLOW,
+ PDN_MDPERI_DBG,
+ PDN_TRACE_26M,
+ PDN_MDGPTM_26M,
+ PDN_MDPERI_BUS,
+ PDN_MDDBGSYS_BUS,
+
+ /* MDL1AO */
+ PDN_C2KDO_TMR,
+ PDN_C2KDO_SLP,
+ PDN_C2K1X_TMR,
+ PDN_C2K1X_SLP,
+ PDN_TDMA_SLP,
+ PDN_TDD_TMR,
+ PDN_TDD_SLP,
+ PDN_FDD_TMR,
+ PDN_FDD_SLP,
+ PDN_LTE_TMR,
+ PDN_LTE_SLP,
+ PDN_IDC_CTRL,
+ PDN_BPI,
+ PDN_BSI,
+ PDN_IDC_UART,
+ PDN_DVFS_CTRL,
+ PDN_FREQM,
+ PDN_C1X_TTR,
+ PDN_CDO_TTR,
+ PDN_MM_EVENTGEN,
+ PDN_CDO_EVENTGEN,
+ PDN_C1X_EVENTGEN,
+ PDN_TDD_EVENTGEN,
+ PDN_FDD_EVENTGEN,
+ PDN_LTE_EVENTGEN,
+ PDN_MDL1_SLP_CTRL,
+ PDN_UCNT_D_TOP,
+ PDN_NR_TIMER,
+ PDN_NR_SLP,
+ PDN_NR_EVENTGEN,
+ PDN_DIGRF_MIPI,
+ PDN_RF_SLP_CTRL,
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+ /* IA DEBUG PERI MISC */
+ PDN_RG_ASM_CK,
+ PDN_RG_PDA_MON_CK,
+#endif
+
+ PDN_MAX_DEV
+} PDN_DEVICE;
+
+
+#if (DISABLE_PDN_FOR_ISSUE)
+
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_SET(PDN_DEVICE dev) {};
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_CLR(PDN_DEVICE dev) {};
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE kal_bool PDN_STS(PDN_DEVICE dev) {return 0;};
+
+#else /* !DISABLE_PDN_FOR_ISSUE */
+
+#define DRVPDN_REG(addr) *(volatile kal_uint32 *)(addr)
+
+/******************************************************************************
+ * Gate clock macros (Disable clock)
+ ******************************************************************************/
+
+#if !(DISABLE_PDN_MDINFRA)
+#define DRVPDN_MDINFRA_OFF(module) \
+ do { \
+ DRVPDN_REG(MD_INFRA_CKEN_CLR) = (kal_uint32)module; \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDINFRA_OFF(module)
+#endif
+
+#if !(DISABLE_PDN_MDPERI)
+#define DRVPDN_MDPERI_OFF(module) \
+ do { \
+ DRVPDN_REG(MD_PERI_CKEN_CLR) = (kal_uint32)module; \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDPERI_OFF(module)
+#endif
+
+#if !(DISABLE_PDN_MDL1AO)
+#define DRVPDN_MDL1AO_OFF(module) \
+ do { \
+ DRVPDN_REG(MDL1AO_PDN_SET) = (kal_uint32)module; \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDL1AO_OFF(module)
+#endif
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+#if !(DISABLE_PDN_DEBUG_PERI_MISC)
+#define DRVPDN_DEBUG_PERI_MISC_OFF(module) \
+ do { \
+ DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) = DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) & (~module) \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_DEBUG_PERI_MISC_OFF(module)
+#endif
+#endif
+
+/******************************************************************************
+ * Un-gate clock macros (Enable clock)
+ ******************************************************************************/
+
+#if !(DISABLE_PDN_MDINFRA)
+#define DRVPDN_MDINFRA_ON(module) \
+ do { \
+ DRVPDN_REG(MD_INFRA_CKEN_SET) = (kal_uint32)module; \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDINFRA_ON(module)
+#endif
+
+#if !(DISABLE_PDN_MDPERI)
+#define DRVPDN_MDPERI_ON(module) \
+ do { \
+ DRVPDN_REG(MD_PERI_CKEN_SET) = (kal_uint32)module; \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDPERI_ON(module)
+#endif
+
+#if !(DISABLE_PDN_MDL1AO)
+#define DRVPDN_MDL1AO_ON(module) \
+ do { \
+ DRVPDN_REG(MDL1AO_PDN_CLR) = (kal_uint32)module; \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_MDL1AO_ON(module)
+#endif
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+#if !(DISABLE_PDN_DEBUG_PERI_MISC)
+#define DRVPDN_DEBUG_PERI_MISC_ON(module) \
+ do { \
+ DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) = DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL) | module \
+ MO_Sync(); \
+ } while(0);
+#else
+#define DRVPDN_DEBUG_PERI_MISC_ON(module)
+#endif
+#endif
+
+/******************************************************************************
+ * Get clock status macros
+ ******************************************************************************/
+
+#define DRVPDN_MDINFRA_STS(module) !(!((~(DRVPDN_REG(MD_INFRA_CKEN))) & module))
+#define DRVPDN_MDPERI_STS(module) !(!((~(DRVPDN_REG(MD_PERI_CKEN))) & module))
+#define DRVPDN_MDL1AO_STS(module) !(!(DRVPDN_REG(MDL1AO_CON20) & module))
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+#define DRVPDN_DEBUG_PERI_MISC_STS(module) !(!((~(DRVPDN_REG(IA_DEBUG_PERI_MISC_CLK_CTRL))) & module))
+#endif
+
+ /*------------------------------------------------------------------------
+ * void PDN_SET(PDN_DEVICE dev)
+ * Purpose: Disable clock of specified module.
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_SET(PDN_DEVICE dev)
+{
+ switch (dev)
+ { /* MD INFRA */
+ case PDN_MDUART1:
+ DRVPDN_MDINFRA_OFF(MDUART1_CK);
+ break;
+ case PDN_BUSMON:
+ DRVPDN_MDINFRA_OFF(BUSMON_CK);
+ break;
+ case PDN_SOE:
+ DRVPDN_MDINFRA_OFF(SOE_CK);
+ break;
+ case PDN_LOGTOP_BCLK:
+ DRVPDN_MDINFRA_OFF(LOGTOP_BCLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_ACLK:
+ DRVPDN_MDINFRA_OFF(MDINFRA_ELM_ACLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_FCLK:
+ DRVPDN_MDINFRA_OFF(MDINFRA_ELM_FCLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_F26M:
+ DRVPDN_MDINFRA_OFF(MDINFRA_ELM_F26M_CK);
+ break;
+ case PDN_TRACE_BUS2X:
+ DRVPDN_MDINFRA_OFF(TRACE_BUS2X_CK);
+ break;
+ case PDN_PPPHA_CLK:
+ DRVPDN_MDINFRA_OFF(PPPHA_CLK_CK);
+ break;
+ case PDN_SDF_HCLK:
+ DRVPDN_MDINFRA_OFF(SDF_HCLK_CK);
+ break;
+ case PDN_TRACE_PIPE:
+ DRVPDN_MDINFRA_OFF(TRACE_PIPE_CK);
+ break;
+ case PDN_TRACE_SWD:
+ DRVPDN_MDINFRA_OFF(TRACE_SWD_CK);
+ break;
+ case PDN_I2C_BCLK:
+ DRVPDN_MDINFRA_OFF(I2C_BCLK_CK);
+ break;
+ case PDN_LOGTOP_BUS2X:
+ DRVPDN_MDINFRA_OFF(LOGTOP_BUS2X_CK);
+ break;
+ case PDN_SDF_ATB_CPHY:
+ DRVPDN_MDINFRA_OFF(SDF_ATB_CPHY_CK);
+ break;
+ case PDN_MDINFRA_BUS:
+ DRVPDN_MDINFRA_OFF(MDINFRA_BUS_CG);
+ break;
+ case PDN_TRACE_ATB_CPHY:
+ DRVPDN_MDINFRA_OFF(TRACE_ATB_CPHY_CK);
+ break;
+ case PDN_MDINFRA_ATB_CK:
+ DRVPDN_MDINFRA_OFF(MDINFRA_ATB_CK);
+ break;
+ case PDN_MDINFRA_DBG_CK:
+ DRVPDN_MDINFRA_OFF(MDINFRA_DBG_CK);
+ break;
+
+ /* MD PERI */
+ case PDN_MDUART0:
+ DRVPDN_MDPERI_OFF(MDUART0_CK);
+ break;
+ case PDN_MDGDMA:
+ DRVPDN_MDPERI_OFF(MDGDMA_CK);
+ break;
+ case PDN_MDGPTM:
+ DRVPDN_MDPERI_OFF(MDGPTM_CK);
+ break;
+ case PDN_MDGDMA_FORDSP:
+ DRVPDN_MDPERI_OFF(MDGDMA_FORDSP_CK);
+ break;
+ case PDN_USIM1_BCLK:
+ DRVPDN_MDPERI_OFF(USIM1_BCLK_CK);
+ break;
+ case PDN_USIM2_BCLK:
+ DRVPDN_MDPERI_OFF(USIM2_BCLK_CK);
+ break;
+ case PDN_MDEINT:
+ DRVPDN_MDPERI_OFF(MDEINT_CK);
+ break;
+ case PDN_LOW_PWR_DBG_MON:
+ DRVPDN_MDPERI_OFF(LOW_PWR_DBG_MON_CK);
+ break;
+ case PDN_USIM1:
+ DRVPDN_MDPERI_OFF(USIM1_CK);
+ break;
+ case PDN_USIM2:
+ DRVPDN_MDPERI_OFF(USIM2_CK);
+ break;
+ case PDN_MDECT:
+ DRVPDN_MDPERI_OFF(MDECT_CK);
+ break;
+ case PDN_MDCIRQ:
+ DRVPDN_MDPERI_OFF(MDCIRQ_CK);
+ break;
+ case PDN_THERM_SLOW:
+ DRVPDN_MDPERI_OFF(THERM_SLOW_CK);
+ break;
+ case PDN_MDPERI_DBG:
+ DRVPDN_MDPERI_OFF(MDPERI_DBG_CK);
+ break;
+ case PDN_TRACE_26M:
+ DRVPDN_MDPERI_OFF(TRACE_26M_CK);
+ break;
+ case PDN_MDGPTM_26M:
+ DRVPDN_MDPERI_OFF(MDGPTM_26M_CK);
+ break;
+ case PDN_MDPERI_BUS:
+ DRVPDN_MDPERI_OFF(MDPERI_BUS_CG);
+ break;
+ case PDN_MDDBGSYS_BUS:
+ DRVPDN_MDPERI_OFF(MDDBGSYS_BUS_CK);
+ break;
+
+ /* MDL1AO */
+ case PDN_C2KDO_TMR:
+ DRVPDN_MDL1AO_OFF(C2KDO_TMR_CG);
+ break;
+ case PDN_C2KDO_SLP:
+ DRVPDN_MDL1AO_OFF(C2KDO_SLP_CG);
+ break;
+ case PDN_C2K1X_TMR:
+ DRVPDN_MDL1AO_OFF(C2K1X_TMR_CG);
+ break;
+ case PDN_C2K1X_SLP:
+ DRVPDN_MDL1AO_OFF(C2K1X_SLP_CG);
+ break;
+ case PDN_TDMA_SLP:
+ DRVPDN_MDL1AO_OFF(TDMA_SLP_CG);
+ break;
+ case PDN_TDD_TMR:
+ DRVPDN_MDL1AO_OFF(TDD_TMR_CG);
+ break;
+ case PDN_TDD_SLP:
+ DRVPDN_MDL1AO_OFF(TDD_SLP_CG);
+ break;
+ case PDN_FDD_TMR:
+ DRVPDN_MDL1AO_OFF(FDD_TMR_CG);
+ break;
+ case PDN_FDD_SLP:
+ DRVPDN_MDL1AO_OFF(FDD_SLP_CG);
+ break;
+ case PDN_LTE_TMR:
+ DRVPDN_MDL1AO_OFF(LTE_TMR_CG);
+ break;
+ case PDN_LTE_SLP:
+ DRVPDN_MDL1AO_OFF(LTE_SLP_CG);
+ break;
+ case PDN_IDC_CTRL:
+ DRVPDN_MDL1AO_OFF(IDC_CTRL_CG);
+ break;
+ case PDN_BPI:
+ DRVPDN_MDL1AO_OFF(BPI_CG);
+ break;
+ case PDN_BSI:
+ DRVPDN_MDL1AO_OFF(BSI_CG);
+ break;
+ case PDN_IDC_UART:
+ DRVPDN_MDL1AO_OFF(IDC_UART_CG);
+ break;
+ case PDN_DVFS_CTRL:
+ DRVPDN_MDL1AO_OFF(DVFS_CTRL_CG);
+ break;
+ case PDN_FREQM:
+ DRVPDN_MDL1AO_OFF(FREQM_CG);
+ break;
+ case PDN_C1X_TTR:
+ DRVPDN_MDL1AO_OFF(C1X_TTR_CG);
+ break;
+ case PDN_CDO_TTR:
+ DRVPDN_MDL1AO_OFF(CDO_TTR_CG);
+ break;
+ case PDN_MM_EVENTGEN:
+ DRVPDN_MDL1AO_OFF(MM_EVENTGEN_CG);
+ break;
+ case PDN_CDO_EVENTGEN:
+ DRVPDN_MDL1AO_OFF(CDO_EVENTGEN_CG);
+ break;
+ case PDN_C1X_EVENTGEN:
+ DRVPDN_MDL1AO_OFF(C1X_EVENTGEN_CG);
+ break;
+ case PDN_TDD_EVENTGEN:
+ DRVPDN_MDL1AO_OFF(TDD_EVENTGEN_CG);
+ break;
+ case PDN_FDD_EVENTGEN:
+ DRVPDN_MDL1AO_OFF(FDD_EVENTGEN_CG);
+ break;
+ case PDN_LTE_EVENTGEN:
+ DRVPDN_MDL1AO_OFF(LTE_EVENTGEN_CG);
+ break;
+ case PDN_MDL1_SLP_CTRL:
+ DRVPDN_MDL1AO_OFF(MDL1_SLP_CTRL_CG);
+ break;
+ case PDN_UCNT_D_TOP:
+ DRVPDN_MDL1AO_OFF(UCNT_D_TOP_CG);
+ break;
+ case PDN_NR_TIMER:
+ DRVPDN_MDL1AO_OFF(NR_TIMER_CG);
+ break;
+ case PDN_NR_SLP:
+ DRVPDN_MDL1AO_OFF(NR_SLP_CG);
+ break;
+ case PDN_NR_EVENTGEN:
+ DRVPDN_MDL1AO_OFF(NR_EVENTGEN_CG);
+ break;
+ case PDN_DIGRF_MIPI:
+ DRVPDN_MDL1AO_OFF(DIGRF_MIPI_CG);
+ break;
+ case PDN_RF_SLP_CTRL:
+ DRVPDN_MDL1AO_OFF(RF_SLP_CTRL_CG);
+ break;
+
+ #if defined(PDN_ASM_PDAMON_SUPPORT)
+ /* IA DEBUG PERI MISC */
+ case PDN_RG_ASM_CK:
+ DRVPDN_DEBUG_PERI_MISC_OFF(RG_ASM_CK);
+ break;
+ case PDN_RG_PDA_MON_CK:
+ DRVPDN_DEBUG_PERI_MISC_OFF(RG_PDA_MON_CK);
+ break;
+ #endif
+
+ case PDN_MAX_DEV:
+ break;
+ }
+
+}
+
+ /*------------------------------------------------------------------------
+ * void PDN_CLR(PDN_DEVICE dev)
+ * Purpose: Enable clock of specified module.
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE void PDN_CLR(PDN_DEVICE dev)
+{
+ switch (dev)
+ { /* MD INFRA */
+ case PDN_MDUART1:
+ DRVPDN_MDINFRA_ON(MDUART1_CK);
+ break;
+ case PDN_BUSMON:
+ DRVPDN_MDINFRA_ON(BUSMON_CK);
+ break;
+ case PDN_SOE:
+ DRVPDN_MDINFRA_ON(SOE_CK);
+ break;
+ case PDN_LOGTOP_BCLK:
+ DRVPDN_MDINFRA_ON(LOGTOP_BCLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_ACLK:
+ DRVPDN_MDINFRA_ON(MDINFRA_ELM_ACLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_FCLK:
+ DRVPDN_MDINFRA_ON(MDINFRA_ELM_FCLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_F26M:
+ DRVPDN_MDINFRA_ON(MDINFRA_ELM_F26M_CK);
+ break;
+ case PDN_TRACE_BUS2X:
+ DRVPDN_MDINFRA_ON(TRACE_BUS2X_CK);
+ break;
+ case PDN_PPPHA_CLK:
+ DRVPDN_MDINFRA_ON(PPPHA_CLK_CK);
+ break;
+ case PDN_SDF_HCLK:
+ DRVPDN_MDINFRA_ON(SDF_HCLK_CK);
+ break;
+ case PDN_TRACE_PIPE:
+ DRVPDN_MDINFRA_ON(TRACE_PIPE_CK);
+ break;
+ case PDN_TRACE_SWD:
+ DRVPDN_MDINFRA_ON(TRACE_SWD_CK);
+ break;
+ case PDN_I2C_BCLK:
+ DRVPDN_MDINFRA_ON(I2C_BCLK_CK);
+ break;
+ case PDN_LOGTOP_BUS2X:
+ DRVPDN_MDINFRA_ON(LOGTOP_BUS2X_CK);
+ break;
+ case PDN_SDF_ATB_CPHY:
+ DRVPDN_MDINFRA_ON(SDF_ATB_CPHY_CK);
+ break;
+ case PDN_MDINFRA_BUS:
+ DRVPDN_MDINFRA_ON(MDINFRA_BUS_CG);
+ break;
+ case PDN_TRACE_ATB_CPHY:
+ DRVPDN_MDINFRA_ON(TRACE_ATB_CPHY_CK);
+ break;
+ case PDN_MDINFRA_ATB_CK:
+ DRVPDN_MDINFRA_ON(MDINFRA_ATB_CK);
+ break;
+ case PDN_MDINFRA_DBG_CK:
+ DRVPDN_MDINFRA_ON(MDINFRA_DBG_CK);
+ break;
+
+ /* MD PERI */
+ case PDN_MDUART0:
+ DRVPDN_MDPERI_ON(MDUART0_CK);
+ break;
+ case PDN_MDGDMA:
+ DRVPDN_MDPERI_ON(MDGDMA_CK);
+ break;
+ case PDN_MDGPTM:
+ DRVPDN_MDPERI_ON(MDGPTM_CK);
+ break;
+ case PDN_MDGDMA_FORDSP:
+ DRVPDN_MDPERI_ON(MDGDMA_FORDSP_CK);
+ break;
+ case PDN_USIM1_BCLK:
+ DRVPDN_MDPERI_ON(USIM1_BCLK_CK);
+ break;
+ case PDN_USIM2_BCLK:
+ DRVPDN_MDPERI_ON(USIM2_BCLK_CK);
+ break;
+ case PDN_MDEINT:
+ DRVPDN_MDPERI_ON(MDEINT_CK);
+ break;
+ case PDN_LOW_PWR_DBG_MON:
+ DRVPDN_MDPERI_ON(LOW_PWR_DBG_MON_CK);
+ break;
+ case PDN_USIM1:
+ DRVPDN_MDPERI_ON(USIM1_CK);
+ break;
+ case PDN_USIM2:
+ DRVPDN_MDPERI_ON(USIM2_CK);
+ break;
+ case PDN_MDECT:
+ DRVPDN_MDPERI_ON(MDECT_CK);
+ break;
+ case PDN_MDCIRQ:
+ DRVPDN_MDPERI_ON(MDCIRQ_CK);
+ break;
+ case PDN_THERM_SLOW:
+ DRVPDN_MDPERI_ON(THERM_SLOW_CK);
+ break;
+ case PDN_MDPERI_DBG:
+ DRVPDN_MDPERI_ON(MDPERI_DBG_CK);
+ break;
+ case PDN_TRACE_26M:
+ DRVPDN_MDPERI_ON(TRACE_26M_CK);
+ break;
+ case PDN_MDGPTM_26M:
+ DRVPDN_MDPERI_ON(MDGPTM_26M_CK);
+ break;
+ case PDN_MDPERI_BUS:
+ DRVPDN_MDPERI_ON(MDPERI_BUS_CG);
+ break;
+ case PDN_MDDBGSYS_BUS:
+ DRVPDN_MDPERI_ON(MDDBGSYS_BUS_CK);
+ break;
+
+ /* MDL1AO */
+ case PDN_C2KDO_TMR:
+ DRVPDN_MDL1AO_ON(C2KDO_TMR_CG);
+ break;
+ case PDN_C2KDO_SLP:
+ DRVPDN_MDL1AO_ON(C2KDO_SLP_CG);
+ break;
+ case PDN_C2K1X_TMR:
+ DRVPDN_MDL1AO_ON(C2K1X_TMR_CG);
+ break;
+ case PDN_C2K1X_SLP:
+ DRVPDN_MDL1AO_ON(C2K1X_SLP_CG);
+ break;
+ case PDN_TDMA_SLP:
+ DRVPDN_MDL1AO_ON(TDMA_SLP_CG);
+ break;
+ case PDN_TDD_TMR:
+ DRVPDN_MDL1AO_ON(TDD_TMR_CG);
+ break;
+ case PDN_TDD_SLP:
+ DRVPDN_MDL1AO_ON(TDD_SLP_CG);
+ break;
+ case PDN_FDD_TMR:
+ DRVPDN_MDL1AO_ON(FDD_TMR_CG);
+ break;
+ case PDN_FDD_SLP:
+ DRVPDN_MDL1AO_ON(FDD_SLP_CG);
+ break;
+ case PDN_LTE_TMR:
+ DRVPDN_MDL1AO_ON(LTE_TMR_CG);
+ break;
+ case PDN_LTE_SLP:
+ DRVPDN_MDL1AO_ON(LTE_SLP_CG);
+ break;
+ case PDN_IDC_CTRL:
+ DRVPDN_MDL1AO_ON(IDC_CTRL_CG);
+ break;
+ case PDN_BPI:
+ DRVPDN_MDL1AO_ON(BPI_CG);
+ break;
+ case PDN_BSI:
+ DRVPDN_MDL1AO_ON(BSI_CG);
+ break;
+ case PDN_IDC_UART:
+ DRVPDN_MDL1AO_ON(IDC_UART_CG);
+ break;
+ case PDN_DVFS_CTRL:
+ DRVPDN_MDL1AO_ON(DVFS_CTRL_CG);
+ break;
+ case PDN_FREQM:
+ DRVPDN_MDL1AO_ON(FREQM_CG);
+ break;
+ case PDN_C1X_TTR:
+ DRVPDN_MDL1AO_ON(C1X_TTR_CG);
+ break;
+ case PDN_CDO_TTR:
+ DRVPDN_MDL1AO_ON(CDO_TTR_CG);
+ break;
+ case PDN_MM_EVENTGEN:
+ DRVPDN_MDL1AO_ON(MM_EVENTGEN_CG);
+ break;
+ case PDN_CDO_EVENTGEN:
+ DRVPDN_MDL1AO_ON(CDO_EVENTGEN_CG);
+ break;
+ case PDN_C1X_EVENTGEN:
+ DRVPDN_MDL1AO_ON(C1X_EVENTGEN_CG);
+ break;
+ case PDN_TDD_EVENTGEN:
+ DRVPDN_MDL1AO_ON(TDD_EVENTGEN_CG);
+ break;
+ case PDN_FDD_EVENTGEN:
+ DRVPDN_MDL1AO_ON(FDD_EVENTGEN_CG);
+ break;
+ case PDN_LTE_EVENTGEN:
+ DRVPDN_MDL1AO_ON(LTE_EVENTGEN_CG);
+ break;
+ case PDN_MDL1_SLP_CTRL:
+ DRVPDN_MDL1AO_ON(MDL1_SLP_CTRL_CG);
+ break;
+ case PDN_UCNT_D_TOP:
+ DRVPDN_MDL1AO_ON(UCNT_D_TOP_CG);
+ break;
+ case PDN_NR_TIMER:
+ DRVPDN_MDL1AO_ON(NR_TIMER_CG);
+ break;
+ case PDN_NR_SLP:
+ DRVPDN_MDL1AO_ON(NR_SLP_CG);
+ break;
+ case PDN_NR_EVENTGEN:
+ DRVPDN_MDL1AO_ON(NR_EVENTGEN_CG);
+ break;
+ case PDN_DIGRF_MIPI:
+ DRVPDN_MDL1AO_ON(DIGRF_MIPI_CG);
+ break;
+ case PDN_RF_SLP_CTRL:
+ DRVPDN_MDL1AO_ON(RF_SLP_CTRL_CG);
+ break;
+
+ #if defined(PDN_ASM_PDAMON_SUPPORT)
+ /* IA DEBUG PERI MISC */
+ case PDN_RG_ASM_CK:
+ DRVPDN_DEBUG_PERI_MISC_ON(RG_ASM_CK);
+ break;
+ case PDN_RG_PDA_MON_CK:
+ DRVPDN_DEBUG_PERI_MISC_ON(RG_PDA_MON_CK);
+ break;
+ #endif
+
+ case PDN_MAX_DEV:
+ break;
+ }
+
+}
+
+ /*------------------------------------------------------------------------
+ * kal_bool PDN_STS(PDN_DEVICE dev)
+ * Purpose: Return the clock is enable/disable of specified module.
+ * Return :
+ * ret = 1. PDN is Set (Clock is Disabled)
+ * ret = 0. PDN is Clear (Clock is Enabled)
+ *------------------------------------------------------------------------
+ */
+DRVPDN_INLINE_MODIFIER DRVPDN_INLINE kal_bool PDN_STS(PDN_DEVICE dev)
+{
+ kal_bool ret = 0;
+
+ switch (dev)
+ { /* MD INFRA */
+ case PDN_MDUART1:
+ ret = DRVPDN_MDINFRA_STS(MDUART1_CK);
+ break;
+ case PDN_BUSMON:
+ ret = DRVPDN_MDINFRA_STS(BUSMON_CK);
+ break;
+ case PDN_SOE:
+ ret = DRVPDN_MDINFRA_STS(SOE_CK);
+ break;
+ case PDN_LOGTOP_BCLK:
+ ret = DRVPDN_MDINFRA_STS(LOGTOP_BCLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_ACLK:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_ACLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_FCLK:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_FCLK_CK);
+ break;
+ case PDN_MDINFRA_ELM_F26M:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_ELM_F26M_CK);
+ break;
+ case PDN_TRACE_BUS2X:
+ ret = DRVPDN_MDINFRA_STS(TRACE_BUS2X_CK);
+ break;
+ case PDN_PPPHA_CLK:
+ ret = DRVPDN_MDINFRA_STS(PPPHA_CLK_CK);
+ break;
+ case PDN_SDF_HCLK:
+ ret = DRVPDN_MDINFRA_STS(SDF_HCLK_CK);
+ break;
+ case PDN_TRACE_PIPE:
+ ret = DRVPDN_MDINFRA_STS(TRACE_PIPE_CK);
+ break;
+ case PDN_TRACE_SWD:
+ ret = DRVPDN_MDINFRA_STS(TRACE_SWD_CK);
+ break;
+ case PDN_I2C_BCLK:
+ ret = DRVPDN_MDINFRA_STS(I2C_BCLK_CK);
+ break;
+ case PDN_LOGTOP_BUS2X:
+ ret = DRVPDN_MDINFRA_STS(LOGTOP_BUS2X_CK);
+ break;
+ case PDN_SDF_ATB_CPHY:
+ ret = DRVPDN_MDINFRA_STS(SDF_ATB_CPHY_CK);
+ break;
+ case PDN_MDINFRA_BUS:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_BUS_CG);
+ break;
+ case PDN_TRACE_ATB_CPHY:
+ ret = DRVPDN_MDINFRA_STS(TRACE_ATB_CPHY_CK);
+ break;
+ case PDN_MDINFRA_ATB_CK:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_ATB_CK);
+ break;
+ case PDN_MDINFRA_DBG_CK:
+ ret = DRVPDN_MDINFRA_STS(MDINFRA_DBG_CK);
+ break;
+
+ /* MD PERI */
+ case PDN_MDUART0:
+ ret = DRVPDN_MDPERI_STS(MDUART0_CK);
+ break;
+ case PDN_MDGDMA:
+ ret = DRVPDN_MDPERI_STS(MDGDMA_CK);
+ break;
+ case PDN_MDGPTM:
+ ret = DRVPDN_MDPERI_STS(MDGPTM_CK);
+ break;
+ case PDN_MDGDMA_FORDSP:
+ ret = DRVPDN_MDPERI_STS(MDGDMA_FORDSP_CK);
+ break;
+ case PDN_USIM1_BCLK:
+ ret = DRVPDN_MDPERI_STS(USIM1_BCLK_CK);
+ break;
+ case PDN_USIM2_BCLK:
+ ret = DRVPDN_MDPERI_STS(USIM2_BCLK_CK);
+ break;
+ case PDN_MDEINT:
+ ret = DRVPDN_MDPERI_STS(MDEINT_CK);
+ break;
+ case PDN_LOW_PWR_DBG_MON:
+ ret = DRVPDN_MDPERI_STS(LOW_PWR_DBG_MON_CK);
+ break;
+ case PDN_USIM1:
+ ret = DRVPDN_MDPERI_STS(USIM1_CK);
+ break;
+ case PDN_USIM2:
+ ret = DRVPDN_MDPERI_STS(USIM2_CK);
+ break;
+ case PDN_MDECT:
+ ret = DRVPDN_MDPERI_STS(MDECT_CK);
+ break;
+ case PDN_MDCIRQ:
+ ret = DRVPDN_MDPERI_STS(MDCIRQ_CK);
+ break;
+ case PDN_THERM_SLOW:
+ ret = DRVPDN_MDPERI_STS(THERM_SLOW_CK);
+ break;
+ case PDN_MDPERI_DBG:
+ ret = DRVPDN_MDPERI_STS(MDPERI_DBG_CK);
+ break;
+ case PDN_TRACE_26M:
+ ret = DRVPDN_MDPERI_STS(TRACE_26M_CK);
+ break;
+ case PDN_MDGPTM_26M:
+ ret = DRVPDN_MDPERI_STS(MDGPTM_26M_CK);
+ break;
+ case PDN_MDPERI_BUS:
+ ret = DRVPDN_MDPERI_STS(MDPERI_BUS_CG);
+ break;
+ case PDN_MDDBGSYS_BUS:
+ ret = DRVPDN_MDPERI_STS(MDDBGSYS_BUS_CK);
+ break;
+
+ /* MDL1AO */
+ case PDN_C2KDO_TMR:
+ ret = DRVPDN_MDL1AO_STS(C2KDO_TMR_CG);
+ break;
+ case PDN_C2KDO_SLP:
+ ret = DRVPDN_MDL1AO_STS(C2KDO_SLP_CG);
+ break;
+ case PDN_C2K1X_TMR:
+ ret = DRVPDN_MDL1AO_STS(C2K1X_TMR_CG);
+ break;
+ case PDN_C2K1X_SLP:
+ ret = DRVPDN_MDL1AO_STS(C2K1X_SLP_CG);
+ break;
+ case PDN_TDMA_SLP:
+ ret = DRVPDN_MDL1AO_STS(TDMA_SLP_CG);
+ break;
+ case PDN_TDD_TMR:
+ ret = DRVPDN_MDL1AO_STS(TDD_TMR_CG);
+ break;
+ case PDN_TDD_SLP:
+ ret = DRVPDN_MDL1AO_STS(TDD_SLP_CG);
+ break;
+ case PDN_FDD_TMR:
+ ret = DRVPDN_MDL1AO_STS(FDD_TMR_CG);
+ break;
+ case PDN_FDD_SLP:
+ ret = DRVPDN_MDL1AO_STS(FDD_SLP_CG);
+ break;
+ case PDN_LTE_TMR:
+ ret = DRVPDN_MDL1AO_STS(LTE_TMR_CG);
+ break;
+ case PDN_LTE_SLP:
+ ret = DRVPDN_MDL1AO_STS(LTE_SLP_CG);
+ break;
+ case PDN_IDC_CTRL:
+ ret = DRVPDN_MDL1AO_STS(IDC_CTRL_CG);
+ break;
+ case PDN_BPI:
+ ret = DRVPDN_MDL1AO_STS(BPI_CG);
+ break;
+ case PDN_BSI:
+ ret = DRVPDN_MDL1AO_STS(BSI_CG);
+ break;
+ case PDN_IDC_UART:
+ ret = DRVPDN_MDL1AO_STS(IDC_UART_CG);
+ break;
+ case PDN_DVFS_CTRL:
+ ret = DRVPDN_MDL1AO_STS(DVFS_CTRL_CG);
+ break;
+ case PDN_FREQM:
+ ret = DRVPDN_MDL1AO_STS(FREQM_CG);
+ break;
+ case PDN_C1X_TTR:
+ ret = DRVPDN_MDL1AO_STS(C1X_TTR_CG);
+ break;
+ case PDN_CDO_TTR:
+ ret = DRVPDN_MDL1AO_STS(CDO_TTR_CG);
+ break;
+ case PDN_MM_EVENTGEN:
+ ret = DRVPDN_MDL1AO_STS(MM_EVENTGEN_CG);
+ break;
+ case PDN_CDO_EVENTGEN:
+ ret = DRVPDN_MDL1AO_STS(CDO_EVENTGEN_CG);
+ break;
+ case PDN_C1X_EVENTGEN:
+ ret = DRVPDN_MDL1AO_STS(C1X_EVENTGEN_CG);
+ break;
+ case PDN_TDD_EVENTGEN:
+ ret = DRVPDN_MDL1AO_STS(TDD_EVENTGEN_CG);
+ break;
+ case PDN_FDD_EVENTGEN:
+ ret = DRVPDN_MDL1AO_STS(FDD_EVENTGEN_CG);
+ break;
+ case PDN_LTE_EVENTGEN:
+ ret = DRVPDN_MDL1AO_STS(LTE_EVENTGEN_CG);
+ break;
+ case PDN_MDL1_SLP_CTRL:
+ ret = DRVPDN_MDL1AO_STS(MDL1_SLP_CTRL_CG);
+ break;
+ case PDN_UCNT_D_TOP:
+ ret = DRVPDN_MDL1AO_STS(UCNT_D_TOP_CG);
+ break;
+ case PDN_NR_TIMER:
+ ret = DRVPDN_MDL1AO_STS(NR_TIMER_CG);
+ break;
+ case PDN_NR_SLP:
+ ret = DRVPDN_MDL1AO_STS(NR_SLP_CG);
+ break;
+ case PDN_NR_EVENTGEN:
+ ret = DRVPDN_MDL1AO_STS(NR_EVENTGEN_CG);
+ break;
+ case PDN_DIGRF_MIPI:
+ ret = DRVPDN_MDL1AO_STS(DIGRF_MIPI_CG);
+ break;
+ case PDN_RF_SLP_CTRL:
+ ret = DRVPDN_MDL1AO_STS(RF_SLP_CTRL_CG);
+ break;
+
+ #if defined(PDN_ASM_PDAMON_SUPPORT)
+ /* IA DEBUG PERI MISC */
+ case PDN_RG_ASM_CK:
+ ret = DRVPDN_DEBUG_PERI_MISC_STS(RG_ASM_CK);
+ break;
+ case PDN_RG_PDA_MON_CK:
+ ret = DRVPDN_DEBUG_PERI_MISC_STS(RG_PDA_MON_CK);
+ break;
+ #endif
+
+ case PDN_MAX_DEV:
+ break;
+ }
+
+ return ret;
+}
+
+#endif /* DISABLE_PDN_FOR_ISSUE */
+
+
+#endif /* !__DRVPDN_INLINE_MT6297_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/drvpdn_inline_username.h b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_username.h
new file mode 100644
index 0000000..93f0efa
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/drvpdn_inline_username.h
@@ -0,0 +1,77 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * drvpdn_inline_username.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * remap user name to PDN spec name
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 11 23 2016 devin.yang
+ * [MOLY00204129] [System Service][PDN] Porting PDN drivers for MT6293.
+ * Update MT6293 PDN driver.
+ *
+ * 11 23 2016 devin.yang
+ * [MOLY00204129] [System Service][PDN] Porting PDN drivers for MT6293.
+ * Update MT6293 PDN driver.
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __DRVPDN_INLINE_USERNAME_H__
+#define __DRVPDN_INLINE_USERNAME_H__
+
+// SE7/SD6 Way Chen
+#define PDN_GPT PDN_MDGPTM
+
+// SE7/SD9 Yuke Ren
+#define PDN_UART0 PDN_MDUART0
+#define PDN_UART1 PDN_MDUART1
+
+#endif /* !__DRVPDN_INLINE_USERNAME_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6293_series.h b/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6293_series.h
new file mode 100644
index 0000000..318f4f2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6293_series.h
@@ -0,0 +1,155 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * pdn_hw_mt6293_series.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * PDN Driver Related HW Registers
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 08 10 2017 devin.yang
+ * [MOLY00269905] [System Service][PDN][Gen93][UMOLYA][LR12A.R2.MP] Update PDN driver for new module clock control.
+ * .
+ *
+ * 11 23 2016 devin.yang
+ * [MOLY00204129] [System Service][PDN] Porting PDN drivers for MT6293.
+ * Update MT6293 PDN driver.
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __PDN_HW_MT6293_SERIES_H__
+#define __PDN_HW_MT6293_SERIES_H__
+
+#include "reg_base.h"
+
+///////////////////////////////////////////////////////////////////////////////
+/// MDPERI_CLKCTL (0xA01C0000)
+///////////////////////////////////////////////////////////////////////////////
+
+#define MD_INFRA_CKEN_SET ((BASE_MADDR_CLK_CTRL+0x04))
+#define MD_INFRA_CKEN_CLR ((BASE_MADDR_CLK_CTRL+0x08))
+#define MD_INFRA_CKEN ((BASE_MADDR_CLK_CTRL+0x0C))
+ #define CG_MDUART1 (1<<0)
+ #define CG_BUSMON (1<<2)
+ #define CG_SOE (1<<4)
+ #define CG_LOGTOP_BCLK (1<<8)
+ #define CG_MDINFRA_ELM_ACLK (1<<10)
+ #define CG_MDINFRA_ELM_FCLK (1<<11)
+ #define CG_MDINFRA_ELM_F26M (1<<12)
+ #define CG_FCS_SLV_DBCLK (1<<15)
+ #define CG_GCU_SLV_DBCLK (1<<16)
+ #define CG_TRACE_BUS2X (1<<17)
+ #define CG_PPPHA_CLK (1<<18)
+ #define CG_SDF_HCLK (1<<19)
+ #define CG_TRACE_PIPE (1<<20)
+ #define CG_TRACE_LINK (1<<21)
+ #define CG_TRACE_SWD (1<<22)
+ #define CG_LOGTOP_BUS2X (1<<23)
+ #define CG_MDINFRA_BUS (1<<28)
+ #define CG_MDINFRA_ATB_CK (1<<30)
+ #define CG_MDINFRA_DBG_CK (1<<31)
+
+#define MD_PERI_CKEN_SET ((BASE_MADDR_CLK_CTRL+0x10))
+#define MD_PERI_CKEN_CLR ((BASE_MADDR_CLK_CTRL+0x14))
+#define MD_PERI_CKEN ((BASE_MADDR_CLK_CTRL+0x18))
+ #define CG_MDUART0 (1<<0)
+ #define CG_MDGDMA (1<<1)
+ #define CG_MDGPTM (1<<2)
+ #define CG_USIM1_BCLK (1<<4)
+ #define CG_USIM2_BCLK (1<<5)
+ #define CG_MDEINT (1<<6)
+ #define CG_USIM1 (1<<8)
+ #define CG_USIM2 (1<<9)
+ #define CG_MDECT (1<<10)
+ #define CG_MDCIRQ (1<<11)
+ #define CG_THERM_SLOW (1<<12)
+ #define CG_MDPERI_DBG (1<<13)
+ #define CG_TRACE_26M (1<<14)
+ #define CG_MDGPTM_26M (1<<15)
+ #define CG_MDPERI_BUS (1<<28)
+ #define CG_MDDBGSYS_DCM (1<<31)
+
+///////////////////////////////////////////////////////////////////////////////
+/// MODEML1_AO_CONFG (0xA6020000)
+///////////////////////////////////////////////////////////////////////////////
+#define MDL1AO_CON20 ((L1_BASE_MADDR_AO_CONFG+0x50))
+#define MDL1AO_PDN_SET ((L1_BASE_MADDR_AO_CONFG+0x54))
+#define MDL1AO_PDN_CLR ((L1_BASE_MADDR_AO_CONFG+0x58))
+ #define CG_C2KDO_TMR (1<<0)
+ #define CG_C2KDO_SLP (1<<1)
+ #define CG_C2K1X_TMR (1<<2)
+ #define CG_C2K1X_SLP (1<<3)
+ #define CG_TDMA_SLP (1<<4)
+ #define CG_TDD_TMR (1<<5)
+ #define CG_TDD_SLP (1<<6)
+ #define CG_FDD_TMR (1<<7)
+ #define CG_FDD_SLP (1<<8)
+ #define CG_LTE_TMR (1<<9)
+ #define CG_LTE_SLP (1<<10)
+ #define CG_IDC_CTRL (1<<11)
+ #define CG_BPI (1<<12)
+ #define CG_BSI (1<<13)
+ #define CG_IDC_UART (1<<14)
+ #define CG_DVFS_CTRL (1<<15)
+ #define CG_FREQM (1<<16)
+ #define CG_C1X_TTR (1<<17)
+ #define CG_CDO_TTR (1<<18)
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// IA_DEBUG_PERI_MISC (0xA0230000)
+///////////////////////////////////////////////////////////////////////////////
+#define IA_DEBUG_PERI_MISC_CLK_CTRL ((BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF+0x4))
+ #define CG_RG_ASM_CK (1<<0)
+ #define CG_RG_PDA_MON_CK (1<<1)
+
+
+#endif /* !__PDN_HW_ELBRUS_SERIES_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6295_series.h b/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6295_series.h
new file mode 100644
index 0000000..7276d28
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6295_series.h
@@ -0,0 +1,168 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * pdn_hw_mt6295_series.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * PDN Driver Related HW Registers
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 06 29 2018 devin.yang
+ * [MOLY00336176] [System Service] [PDN] [Gen95] Fix PDN driver potential bug.
+ * Comment out ASM and PDAmon PDN driver.
+ *
+ * 09 22 2017 devin.yang
+ * [MOLY00244578] [System Service][MT6295M][PDN] Update PDN driver for MT6295M.
+ * Using atomic operation for ASM/PDAmon clock control instead of spinlock.
+ *
+ * 08 09 2017 devin.yang
+ * [MOLY00244578] [System Service][MT6295M][PDN] Update PDN driver for MT6295M.
+ * .
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __PDN_HW_MT6295_SERIES_H__
+#define __PDN_HW_MT6295_SERIES_H__
+
+#include "reg_base.h"
+
+///////////////////////////////////////////////////////////////////////////////
+/// MDPERI_CLKCTL (0xA01C0000)
+///////////////////////////////////////////////////////////////////////////////
+#define MD_INFRA_CKEN_SET ((BASE_MADDR_CLK_CTRL+0x04))
+#define MD_INFRA_CKEN_CLR ((BASE_MADDR_CLK_CTRL+0x08))
+#define MD_INFRA_CKEN ((BASE_MADDR_CLK_CTRL+0x0C))
+ #define MDUART1_CK (1<<0)
+ #define BUSMON_CK (1<<2)
+ #define SOE_CK (1<<4)
+ #define LOGTOP_BCLK_CK (1<<8)
+ #define MDINFRA_ELM_ACLK_CK (1<<10)
+ #define MDINFRA_ELM_FCLK_CK (1<<11)
+ #define MDINFRA_ELM_F26M_CK (1<<12)
+ #define FCS_SLV_DBCLK_CK (1<<15)
+ #define TRACE_BUS2X_CK (1<<17)
+ #define PPPHA_CLK_CK (1<<18)
+ #define SDF_HCLK_CK (1<<19)
+ #define TRACE_PIPE_CK (1<<20)
+ #define TRACE_SWD_CK (1<<21)
+ #define I2C_BCLK_CK (1<<22)
+ #define LOGTOP_BUS2X_CK (1<<23)
+ #define MDINFRA_BUS_CG (1<<28)
+ #define MDINFRA_ATB_CK (1<<30)
+ #define MDINFRA_DBG_CK (1<<31)
+
+#define MD_PERI_CKEN_SET ((BASE_MADDR_CLK_CTRL+0x10))
+#define MD_PERI_CKEN_CLR ((BASE_MADDR_CLK_CTRL+0x14))
+#define MD_PERI_CKEN ((BASE_MADDR_CLK_CTRL+0x18))
+ #define MDUART0_CK (1<<0)
+ #define MDGDMA_CK (1<<1)
+ #define MDGPTM_CK (1<<2)
+ #define USIM1_BCLK_CK (1<<4)
+ #define USIM2_BCLK_CK (1<<5)
+ #define MDEINT_CK (1<<6)
+ #define LOW_PWR_DBG_MON_CK (1<<7)
+ #define USIM1_CK (1<<8)
+ #define USIM2_CK (1<<9)
+ #define MDECT_CK (1<<10)
+ #define MDCIRQ_CK (1<<11)
+ #define THERM_SLOW_CK (1<<12)
+ #define MDPERI_DBG_CK (1<<13)
+ #define TRACE_26M_CK (1<<14)
+ #define MDGPTM_26M_CK (1<<15)
+ #define MDPERI_BUS_CG (1<<28)
+ #define MDDBGSYS_BUS_CK (1<<31)
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// MODEML1_AO_CONFG (0xA6020000)
+///////////////////////////////////////////////////////////////////////////////
+#define MDL1AO_CON20 ((L1_BASE_MADDR_AO_CONFG+0x50))
+#define MDL1AO_PDN_SET ((L1_BASE_MADDR_AO_CONFG+0x54))
+#define MDL1AO_PDN_CLR ((L1_BASE_MADDR_AO_CONFG+0x58))
+ #define C2KDO_TMR_CK (1<<0)
+ #define C2KDO_SLP_CK (1<<1)
+ #define C2K1X_TMR_CK (1<<2)
+ #define C2K1X_SLP_CK (1<<3)
+ #define TDMA_SLP_CK (1<<4)
+ #define TDD_TMR_CK (1<<5)
+ #define TDD_SLP_CK (1<<6)
+ #define FDD_TMR_CK (1<<7)
+ #define FDD_SLP_CK (1<<8)
+ #define LTE_TMR_CK (1<<9)
+ #define LTE_SLP_CK (1<<10)
+ #define IDC_CTRL_CK (1<<11)
+ #define BPI_CK (1<<12)
+ #define BSI_CK (1<<13)
+ #define IDC_UART_CK (1<<14)
+ #define DVFS_CTRL_CK (1<<15)
+ #define FREQM_CK (1<<16)
+ #define C1X_TTR_CK (1<<17)
+ #define CDO_TTR_CK (1<<18)
+ #define MM_EVENTGEN_CK (1<<19)
+ #define CDO_EVENTGEN_CK (1<<20)
+ #define C1X_EVENTGEN_CK (1<<21)
+ #define TDD_EVENTGEN_CK (1<<22)
+ #define FDD_EVENTGEN_CK (1<<23)
+ #define LTE_EVENTGEN_CK (1<<24)
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+///////////////////////////////////////////////////////////////////////////////
+/// IA_DEBUG_PERI_MISC (0xA0230000)
+///////////////////////////////////////////////////////////////////////////////
+#define IA_DEBUG_PERI_MISC_CLK_CTRL ((BASE_MADDR_MDMCU_IA_DEBUG_PERI_MISC_REG_ADR_IF+0x4))
+ #define RG_ASM_CK (1<<0)
+ //#define RG_ASM_CK (0)
+ #define RG_PDA_MON_CK (1<<1)
+ //#define RG_PDA_MON_CK (1)
+#endif
+
+
+#endif /* !__PDN_HW_ELBRUS_SERIES_H__ */
diff --git a/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6297_series.h b/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6297_series.h
new file mode 100644
index 0000000..4c015cd
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pdn/pdn_hw_mt6297_series.h
@@ -0,0 +1,170 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * pdn_hw_mt6297_series.h
+ *
+ * Project:
+ * --------
+ * UMOLYE
+ *
+ * Description:
+ * ------------
+ * PDN Driver Related HW Registers
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 06 29 2018 devin.yang
+ * [MOLY00336176] [System Service] [PDN] [Gen95] Fix PDN driver potential bug.
+ * Comment out ASM and PDAmon PDN driver.
+ *
+ * 09 22 2017 devin.yang
+ * [MOLY00244578] [System Service][MT6295M][PDN] Update PDN driver for MT6295M.
+ * Using atomic operation for ASM/PDAmon clock control instead of spinlock.
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __PDN_HW_MT6297_SERIES_H__
+#define __PDN_HW_MT6297_SERIES_H__
+
+#include "reg_base.h"
+
+/*
+ * MDPERI_CLKCTL (0xA01C0000)
+ */
+#define MD_INFRA_CKEN_SET ((BASE_MADDR_CLK_CTRL+0x04))
+#define MD_INFRA_CKEN_CLR ((BASE_MADDR_CLK_CTRL+0x08))
+#define MD_INFRA_CKEN ((BASE_MADDR_CLK_CTRL+0x0C))
+ #define MDUART1_CK (1<<0)
+ #define BUSMON_CK (1<<2)
+ #define SOE_CK (1<<4)
+ #define LOGTOP_BCLK_CK (1<<8)
+ #define MDINFRA_ELM_ACLK_CK (1<<10)
+ #define MDINFRA_ELM_FCLK_CK (1<<11)
+ #define MDINFRA_ELM_F26M_CK (1<<12)
+ #define TRACE_BUS2X_CK (1<<17)
+ #define PPPHA_CLK_CK (1<<18)
+ #define SDF_HCLK_CK (1<<19)
+ #define TRACE_PIPE_CK (1<<20)
+ #define TRACE_SWD_CK (1<<21)
+ #define I2C_BCLK_CK (1<<22)
+ #define LOGTOP_BUS2X_CK (1<<23)
+ #define SDF_ATB_CPHY_CK (1<<27)
+ #define MDINFRA_BUS_CG (1<<28)
+ #define TRACE_ATB_CPHY_CK (1<<29)
+ #define MDINFRA_ATB_CK (1<<30)
+ #define MDINFRA_DBG_CK (1<<31)
+
+#define MD_PERI_CKEN_SET ((BASE_MADDR_CLK_CTRL+0x10))
+#define MD_PERI_CKEN_CLR ((BASE_MADDR_CLK_CTRL+0x14))
+#define MD_PERI_CKEN ((BASE_MADDR_CLK_CTRL+0x18))
+ #define MDUART0_CK (1<<0)
+ #define MDGDMA_CK (1<<1)
+ #define MDGPTM_CK (1<<2)
+ #define MDGDMA_FORDSP_CK (1<<3)
+ #define USIM1_BCLK_CK (1<<4)
+ #define USIM2_BCLK_CK (1<<5)
+ #define MDEINT_CK (1<<6)
+ #define LOW_PWR_DBG_MON_CK (1<<7)
+ #define USIM1_CK (1<<8)
+ #define USIM2_CK (1<<9)
+ #define MDECT_CK (1<<10)
+ #define MDCIRQ_CK (1<<11)
+ #define THERM_SLOW_CK (1<<12)
+ #define MDPERI_DBG_CK (1<<13)
+ #define TRACE_26M_CK (1<<14)
+ #define MDGPTM_26M_CK (1<<15)
+ #define MDPERI_BUS_CG (1<<28)
+ #define MDDBGSYS_BUS_CK (1<<31)
+
+/*
+ * MODEML1_AO_CONFG (0xA8020000)
+ */
+#define MDL1AO_CON20 ((L1_BASE_MADDR_AO_CONFG+0x50))
+#define MDL1AO_PDN_SET ((L1_BASE_MADDR_AO_CONFG+0x54))
+#define MDL1AO_PDN_CLR ((L1_BASE_MADDR_AO_CONFG+0x58))
+ #define C2KDO_TMR_CG (1<<0)
+ #define C2KDO_SLP_CG (1<<1)
+ #define C2K1X_TMR_CG (1<<2)
+ #define C2K1X_SLP_CG (1<<3)
+ #define TDMA_SLP_CG (1<<4)
+ #define TDD_TMR_CG (1<<5)
+ #define TDD_SLP_CG (1<<6)
+ #define FDD_TMR_CG (1<<7)
+ #define FDD_SLP_CG (1<<8)
+ #define LTE_TMR_CG (1<<9)
+ #define LTE_SLP_CG (1<<10)
+ #define IDC_CTRL_CG (1<<11)
+ #define BPI_CG (1<<12)
+ #define BSI_CG (1<<13)
+ #define IDC_UART_CG (1<<14)
+ #define DVFS_CTRL_CG (1<<15)
+ #define FREQM_CG (1<<16)
+ #define C1X_TTR_CG (1<<17)
+ #define CDO_TTR_CG (1<<18)
+ #define MM_EVENTGEN_CG (1<<19)
+ #define CDO_EVENTGEN_CG (1<<20)
+ #define C1X_EVENTGEN_CG (1<<21)
+ #define TDD_EVENTGEN_CG (1<<22)
+ #define FDD_EVENTGEN_CG (1<<23)
+ #define LTE_EVENTGEN_CG (1<<24)
+ #define MDL1_SLP_CTRL_CG (1<<25)
+ #define UCNT_D_TOP_CG (1<<26)
+ #define NR_TIMER_CG (1<<27)
+ #define NR_SLP_CG (1<<28)
+ #define NR_EVENTGEN_CG (1<<29)
+ #define DIGRF_MIPI_CG (1<<30)
+ #define RF_SLP_CTRL_CG (1<<31)
+
+#if defined(PDN_ASM_PDAMON_SUPPORT)
+/*
+ * IA_DEBUG_PERI_MISC (0xA0230000)
+ */
+#define IA_DEBUG_PERI_MISC_CLK_CTRL ((BASE_MADDR_MDMCU_IA_MACRO_MISC_REG+0x4))
+ #define RG_ASM_CK (1<<0)
+ #define RG_PDA_MON_CK (1<<1)
+#endif
+
+
+#endif /* !__PDN_HW_MT6297_SERIES_H__ */