[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/driver/devdrv/pll/pll.h b/mcu/interface/driver/devdrv/pll/pll.h
new file mode 100644
index 0000000..16e17c7
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pll/pll.h
@@ -0,0 +1,141 @@
+/*******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2012
+ *
+ * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * pll.h
+ *
+ * Project:
+ * --------
+ * UMOLYE
+ *
+ * Description:
+ * ------------
+ * PLL Related Functions
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ============================================================================
+ * $Log$
+ *
+ * 07 31 2019 jun-ying.huang
+ * [MOLY00425097] [VMOLY][FMA]Add __MD97P__ for Mercury build pass
+ * .
+ *
+ * 03 01 2018 jun-ying.huang
+ * [MOLY00310598] [95/97 re-arch]PLL co-branch for MT6295 & MT6297
+ * Add PLL for 97 - Only for Build pass, function and driver is not ready.
+ *
+ * 12 11 2017 jun-ying.huang
+ * [MOLY00295410] [PLL][MT3967] Add Macro for MT3967
+ * .
+ *
+ * 10 25 2017 jun-ying.huang
+ * [MOLY00285159] [PLL][DCM]Add Macro for MT6765(=Cervino)
+ * .
+ *
+ * 10 02 2017 jun-ying.huang
+ * [MOLY00281611] [93/95 re-arch]PLL co-branch for MT6293 & MT6295
+ * .
+ *
+ * 09 01 2017 jun-ying.huang
+ * [MOLY00275084] [6293]Add PLL_SEC Module related code to get SW version.
+ * .
+ *
+ * 08 21 2017 jun-ying.huang
+ * [MOLY00272509] [Sylvia][PLL]Add MT6771 Macro for PLL due to Sylvia MT6771 Call for check in
+ * .
+ *
+ * 06 09 2017 jun-ying.huang
+ * [MOLY00244484] [Zion]Add compile option for ZION in PLL.
+ * Add compile option for ZION and Workaround for CIRQ APB sync issue- Let BUS2x clock use MDBPIPLL_0/6 = 101 MHz
+ *
+ * 10 24 2016 jun-ying.huang
+ * [MOLY00209150] [System Service][PLL]Remove redundant files from UMOLYA PLL
+ * Remove redundant files from PLL
+ *
+ * 06 24 2016 alan-tl.lin
+ * [MOLY00173527] [PLL] Driver porting
+ * Fix build error
+ *
+ * 06 15 2016 alan-tl.lin
+ * [MOLY00173527] [PLL] Driver porting
+ * [PLL] PLL init first porting
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __PLL_H__
+#define __PLL_H__
+
+/*******************************************************************************
+ * Locally Used Options
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Include header files
+ ******************************************************************************/
+#include "kal_general_types.h"
+#include "reg_base.h"
+
+#if defined(__MD93__)
+ #include "pll_gen93m17.h"
+#elif defined(__MD95__)
+ #include "pll_gen95.h"
+#elif defined(__MD97__)
+ #include "pll_gen97.h"
+#elif defined(__MD97P__)
+ #include "pll_gen97p.h"
+#else
+ #error "ERROR in PLL define (pll.h)"
+#endif
+
+/*******************************************************************************
+ * Define exported macro
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Define data structure
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Define exported function prototype
+ ******************************************************************************/
+extern void INT_SetPLL(void);
+
+#endif /* !__PLL_H__ */
diff --git a/mcu/interface/driver/devdrv/pll/pll_gen93m17.h b/mcu/interface/driver/devdrv/pll/pll_gen93m17.h
new file mode 100644
index 0000000..1162dc6
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pll/pll_gen93m17.h
@@ -0,0 +1,478 @@
+/*******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2012
+ *
+ * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * pll_gen93m17.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * PLL Related Functions
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ============================================================================
+ * $Log$
+ *
+ * 01 22 2018 jun-ying.huang
+ * [MOLY00303289] [Merlot call for check-in][PLL][DCM]Add Macro for MT6761(=Merlot)
+ * .
+ *
+ * 10 25 2017 jun-ying.huang
+ * [MOLY00285159] [PLL][DCM]Add Macro for MT6765(=Cervino)
+ * .
+ *
+ * 10 02 2017 jun-ying.huang
+ * [MOLY00281611] [93/95 re-arch]PLL co-branch for MT6293 & MT6295
+ * .
+ *
+ * 08 21 2017 jun-ying.huang
+ * [MOLY00272509] [Sylvia][PLL]Add MT6771 Macro for PLL due to Sylvia MT6771 Call for check in
+ * .
+ *
+ * 06 09 2017 jun-ying.huang
+ * [MOLY00244484] [Zion]Add compile option for ZION in PLL.
+ * Add compile option for ZION and Workaround for CIRQ APB sync issue- Let BUS2x clock use MDBPIPLL_0/6 = 101 MHz
+ *
+ * 12 16 2016 jun-ying.huang
+ * [MOLY00218782] [System service][PLL][6293]Add compile option for MT6763
+ * .
+ *
+ * 12 07 2016 jun-ying.huang
+ * [MOLY00217275] [System service][PLL][6293]Update PLL init flow and porting driver for user
+ * .
+ *
+ * 11 20 2016 jun-ying.huang
+ * [MOLY00214278] [System service][PLL][6293]Update PLL_FrequencyMeter_GetFreq() driver
+ * .
+ *
+ * 11 06 2016 jun-ying.huang
+ * [MOLY00211600] [System service][PLL]Add debug info in PLL driver
+ * .
+ *
+ * 10 14 2016 jun-ying.huang
+ * [MOLY00207095] [System service][PLL]Update PLL driver for DVFS users.
+ * Add PLL function for DVFS
+ *
+ * 09 19 2016 alan-tl.lin
+ * [MOLY00174466] [UMOLYA] PLL porting
+ * [PLL] Update register definition
+ *
+ * 08 02 2016 alan-tl.lin
+ * [MOLY00174466] [UMOLYA] PLL porting
+ * Fix build error
+ *
+ ****************************************************************************/
+
+#ifndef __PLL_MT6763_H__
+#define __PLL_MT6763_H__
+
+/*******************************************************************************
+ * Locally Used Options
+ ******************************************************************************/
+#define PLL_REG32(addr) *(volatile kal_uint32 *)(addr)
+#define PLL_TYPE (volatile kal_uint32 *)
+
+/*******************************************************************************
+ * Define macro for boot code
+ ******************************************************************************/
+#define __SECTION__(S) __attribute__((__section__(#S)))
+#define __PLL_CODE_IN_BOOT__ __SECTION__(NONCACHED_ROCODE)
+
+/*******************************************************************************
+ * Register Define
+ ******************************************************************************/
+
+///////////////////////////////////////////////////////////////////////////////
+/// PLLMIXED (0xA0140000)
+///////////////////////////////////////////////////////////////////////////////
+/* ==========PLL setting========== */
+#define REG_MDTOP_PLLMIXED_CODA_VERSION (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x0))
+#define REG_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4))
+#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x8))
+#define REG_MDTOP_PLLMIXED_DCXO_MODE_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC))
+#define REG_MDTOP_PLLMIXED_PLL_ON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x14))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x18))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x34))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x38))
+
+/* ==========PLL frequency control==> PCW & POSDIV========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x40))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x44))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x48))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x54))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x58))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x60))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x64))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x100))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x104))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x108))
+
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10C))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x110))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_RSTB (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x114))
+#define REG_MDTOP_PLLMIXED_PLL_FHCTL_RST (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x200))
+#define REG_MDTOP_PLLMIXED_CONN_DSNS_INTF (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x204))
+
+/* ==========PLL IRQ related========== */
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x300))
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x304))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x308))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30C))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_ABNORM_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x310))
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x314))
+ #define PLLMIXED_MDMCUPLL_HP_RDY_IRQ_OFFSET (1)
+ #define PLLMIXED_MDVDSPPLL_HP_RDY_IRQ_OFFSET (2)
+ #define PLLMIXED_MDBRPPLL_HP_RDY_IRQ_OFFSET (4)
+ #define PLLMIXED_MDTXPLL_HP_RDY_IRQ_OFFSET (5)
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x318))
+
+/* PLL IRQ related macro */
+#define PLLMIXED_PLL_HP_RDY_IRQ_MASK (0x1)/* mask bit numbers for each IRQ */
+
+/* ==========PLL FHCTL========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x400))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x404))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x408))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x410))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x414))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x418))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x430))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x434))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x438))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x440))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x444))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x448))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x450))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x454))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x458))
+
+/* ==========PLL Gear Set========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x500))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x504))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x508))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50C))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x540))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x544))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x548))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x54C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C0))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C4))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C8))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5CC))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x600))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x604))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x608))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x60C))
+
+/* ==========PLL Status========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC00))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC04))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC08))
+#define REG_MDTOP_PLLMIXED_MDTXPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC0C))
+#define REG_MDTOP_PLLMIXED_MDBPIBPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC10))
+#define REG_MDTOP_PLLMIXED_MDPLL1_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC40))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF00))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF04))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF08))
+#define REG_MDTOP_PLLMIXED_PLL_STATUS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF0C))
+
+/* PLL Status related macro */
+#define PLLMIXED_PLL_SFSTR_PRD_OFFSET (14)
+#define PLLMIXED_PLL_SFSTR_PRD_MASK (0x1)/* mask bit numbers for each SFSTR_PRD */
+#define PLLMIXED_PLL_SDM_PCW_OFFSET (16)
+#define PLLMIXED_PLL_SDM_PCW_MASK (0x7FFF)/* mask bit numbers([30:16] = 14bits) for each SDM_PCW */
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// CLKSW (0xA0150000)
+///////////////////////////////////////////////////////////////////////////////
+#define REG_MDTOP_CLKSW_CODA_VERSION (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x0))
+#define REG_MDTOP_CLKSW_MD_SLEEP_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4))
+#define REG_MDTOP_CLKSW_MDTOPSM_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10))
+#define REG_MDTOP_CLKSW_L1TOPSM_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x14))
+#define REG_MDTOP_CLKSW_CKOFF_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x1C))
+#define REG_MDTOP_CLKSW_CLKON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x20))
+#define REG_MDTOP_CLKSW_CLKSEL_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x24))
+
+/* ==========SDF clock control related========== */
+#define REG_MDTOP_CLKSW_SDF_CK_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x28))
+#define REG_MDTOP_CLKSW_ATB_LOG_SDF_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x2C))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x30))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x34))
+
+/* ==========FLEXCKGEN_SEL========== */
+#define REG_MDTOP_CLKSW_MDCORE_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x40))
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x44))
+#define REG_MDTOP_CLKSW_VDSP_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x48))
+#define REG_MDTOP_CLKSW_BRP_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4C))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x50))
+#define REG_MDTOP_CLKSW_TXSYS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x54))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x58))
+#define REG_MDTOP_CLKSW_MD2G_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x5C))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x60))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x64))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x68))
+
+/* ==========FLEXCKGEN_STS========== */
+#define REG_MDTOP_CLKSW_MDCORE_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x80))
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x84))
+#define REG_MDTOP_CLKSW_VDSP_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x88))
+#define REG_MDTOP_CLKSW_BRP_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x8C))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x90))
+#define REG_MDTOP_CLKSW_TXSYS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x94))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x98))
+#define REG_MDTOP_CLKSW_MD2G_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x9C))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA0))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA4))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA8))
+
+#define REG_MDTOP_CLKSW_CKMUX_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC0))
+#define REG_MDTOP_CLKSW_PLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD0))
+
+/* ==========Frequency Meter========== */
+#define REG_MDTOP_CLKSW_CKMON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x100))
+#define REG_MDTOP_CLKSW_FREQ_METER_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x104))
+#define REG_MDTOP_CLKSW_FREQ_METER_XTAL_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x108))
+#define REG_MDTOP_CLKSW_FREQ_METER_CKMON_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10C))
+#define REG_MDTOP_CLKSW_FREQ_METER_H (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x110))
+#define REG_MDTOP_CLKSW_FREQ_METER_L (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x114))
+
+/* ==========DUMMY & STATUS========== */
+#define REG_MDTOP_CLKSW_CLK_DUMMY (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF00))
+#define REG_MDTOP_CLKSW_CLK_STATUS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF04))
+
+
+/*******************************************************************************
+ * Define Macro
+ ******************************************************************************/
+#define MD_PLL_MAGIC_NUM 0x62930000
+
+/**
+ * PLL divider definition
+ */
+#if defined(MT6763) || defined(MT6771) || defined(MT6765) || defined(MT6761)/* BIANCO or SYLVIA or CERVINO or MERLOT */
+// #define MDBPIPLL_DIVIDER /4 /9 /7
+ #define MDTXPLL_DIVIDER (8)
+ #define MDBRPPLL_DIVIDER (9)
+ #define MDVDSPPLL_DIVIDER (5)
+ #define MDMCUPLL_DIVIDER (4)
+#elif defined(MT6739)/* ZION */
+ #define MDTXPLL_DIVIDER (4)
+ #define MDBRPPLL_DIVIDER (6)
+ #define MDVDSPPLL_DIVIDER (4)
+ #define MDMCUPLL_DIVIDER (2)
+#else
+ #error "Unsupported Chip Target in PLL Module"
+#endif
+
+ /*------------------------------------------------------------------------
+ * Purpose: Transfer PCW in xxxPLL_STS to Mhz. This macro is porting from md_dvfs_pll_freq_get(const PLL_SOURCE pll).
+ * Parameters:
+ * Input: pcw: The PCW value in xxxPLL_STS.
+ * divier: The divier for this PLL(EX: ICCPLL_DIVIDER, IMCPLL_DIVIDER...).
+ * Output: None.
+ * returns : Mhz.
+ * Note : This macr is only used to transfer pcw in xxxPLL_STS to Mhz.
+ * You should not used this macro to transfer pcw in xxxPLL_CTL0 to Mhz due to the meaning is different.
+ * (PCW in xxxPLL_STS is bit [21:7] of xxxPLL_CTL0.)
+ *------------------------------------------------------------------------
+ */
+#define PLLMIXED_PLL_STS_SDM_PCW_TO_MHZ(pcw, divier) ((((pcw) * 26) / (1 << 7)) / divier)
+
+/*******************************************************************************
+ * ENUM
+ ******************************************************************************/
+// frequency meter index list (debug only)
+typedef enum {
+ PLL_FM_SOURCE_START = 0xA,
+ PLL_FM_TRACE_MON_CLOCK = 0xA,
+ PLL_FM_MDSYS_208M_CLOCK = 0xB,
+ PLL_FM_MDRXSYS_RAKE_CLOCK = 0xC,
+ PLL_FM_MDRXSYS_BRP_CLOCK = 0xD,
+ PLL_FM_MDRXSYS_VDSP_CLOCK = 0xE,
+ PLL_FM_MDTOP_LOG_GTB_CLOCK = 0xF,
+ PLL_FM_FESYS_CSYS_CLOCK = 0x10,
+ PLL_FM_FESYS_TXSYS_CLOCK = 0x11,
+ PLL_FM_FESYS_BSI_CLOCK = 0x12,
+ PLL_FM_MDSYS_MDCORE_CLOCK = 0x13,
+ PLL_FM_MDSYS_BUS2X_NODCM_CLOCK = 0x14,
+ PLL_FM_MDSYS_BUS2X_CLOCK = 0x15,
+ PLL_FM_MDTOP_DBG_CLOCK = 0x16,
+ PLL_FM_MDTOP_F32K_CLOCK = 0x17,
+ PLL_FM_MDBPI_PLL_0_DIV2 = 0x18,
+ PLL_FM_MDBPI_PLL_2 = 0x19,
+ PLL_FM_MDBPI_PLL_1 = 0x1A,
+ PLL_FM_MDBPI_PLL_0 = 0x1B,
+ PLL_FM_MDTX_PLL = 0x1C,
+ PLL_FM_MDBRP_PLL = 0x1D,
+ PLL_FM_MDVDSP_PLL = 0x1E,
+ PLL_FM_MDMCU_PLL = 0x1F,
+ PLL_FM_SOURCE_END = 0x1F
+} PLL_FM_SOURCE;
+
+typedef enum {
+ PLL_MDPLL1 = 0,
+ PLL_MDMCU = 1,
+ PLL_MDVDSP = 2,
+ PLL_MDBRP = 3,
+ PLL_MDTX = 4,
+ PLL_MDBPI = 5,
+ PLL_END,
+} PLL_SOURCE;
+
+typedef enum {
+ CLKSW_FLEXCKGEN_START = 0,
+ MDCORE_FLEXCKGEN = 0,
+ MDSYS_BUS_FLEXCKGEN = 1,
+ VDSP_FLEXCKGEN = 2,
+ BRP_FLEXCKGEN = 3,
+ RAKE_FLEXCKGEN = 4,
+ TXSYS_FLEXCKGEN = 5,
+ CSSYS_FLEXCKGEN = 6,
+ MD2G_FLEXCKGEN = 7,
+ BSI_FLEXCKGEN = 8,
+ DBG_FLEXCKGEN = 9,
+ LOG_ATB_FLEXCKGEN = 10,
+ CLKSW_FLEXCKGEN_END
+} PLL_CLKSW_FLEXCKGEN;
+
+typedef enum {
+ CLKSW_FLEXCKGEN_DIV_1 = 0,
+ CLKSW_FLEXCKGEN_DIV_2 = 1,
+ CLKSW_FLEXCKGEN_DIV_3 = 2,
+ CLKSW_FLEXCKGEN_DIV_4 = 3,
+ CLKSW_FLEXCKGEN_DIV_5 = 4,
+ CLKSW_FLEXCKGEN_DIV_6 = 5,
+ CLKSW_FLEXCKGEN_DIV_7 = 6,
+ CLKSW_FLEXCKGEN_DIV_8 = 7
+} PLL_CLKSW_FLEXCKGEN_DIV;
+
+typedef enum {
+ CLKSW_FLEXCKGEN_PLL_SRC_0 = 0,
+ CLKSW_FLEXCKGEN_PLL_SRC_1 = 1,
+ CLKSW_FLEXCKGEN_PLL_SRC_2 = 2,
+ CLKSW_FLEXCKGEN_PLL_SRC_3 = 3
+} PLL_CLKSW_FLEXCKGEN_PLL_SRC;
+
+typedef enum {
+ CLKSW_MDTOPSM_DBG_CK = 3,
+} PLL_CLKSW_MDTOPSM_SW_CTL_SRC;
+
+typedef enum {
+ CLKSW_SDF_SRC_BPIPLL_DIV8 = 0,
+ CLKSW_SDF_SRC_BPIPLL_DIV4 = 1,
+ CLKSW_SDF_SRC_BPIPLL = 2,
+ CLKSW_SDF_SRC_BPIPLL_DIV2 = 3,
+ /*CLKSW_SDF_SRC_USB_PhyLink = 4,*/ /* HW didn't support. */
+ CLKSW_SDF_SRC_26M,
+ CLKSW_SDF_SRC_END
+} PLL_CLKSW_SDF_SRC;
+
+/* Below for debugging */
+
+#define PLL_FM_NUM 30 /* Note: This number should also sync to EE owner. */
+typedef struct {
+ kal_uint32 clock_trace_mon; /* 0 */
+ kal_uint32 clock_mdsys_208m;
+ kal_uint32 clock_mdrxsys_rake;
+ kal_uint32 clock_mdrxsys_brp;
+ kal_uint32 clock_mdrxsys_vdsp;
+ kal_uint32 clock_mdtop_log_gtb; /* 5 */
+ kal_uint32 clock_fesys_csys;
+ kal_uint32 clock_fesys_txsys;
+ kal_uint32 clock_fesys_bsi;
+ kal_uint32 clock_mdsys_mdcore;
+ kal_uint32 clock_mdsys_bus2x_nodcm; /* 10 */
+ kal_uint32 clock_mdsys_bus2x;
+ kal_uint32 clock_mdtop_dbg;
+ kal_uint32 clock_mdtop_f32k;
+ kal_uint32 pll_MDBPI0_div2;
+ kal_uint32 pll_MDBPI2; /* 15 */
+ kal_uint32 pll_MDBPI1;
+ kal_uint32 pll_MDBPI0;
+ kal_uint32 pll_MDTX;
+ kal_uint32 pll_MDBRP;
+ kal_uint32 pll_MDVDSP; /* 20 */
+ kal_uint32 pll_MDMCU;
+/* below no use */
+ kal_uint32 NULL_22;
+ kal_uint32 NULL_23;
+ kal_uint32 NULL_24;
+ kal_uint32 NULL_25;
+ kal_uint32 NULL_26;
+ kal_uint32 NULL_27;
+ kal_uint32 NULL_28;
+ kal_uint32 NULL_29;
+} PLL_CLK_INFO;
+
+extern PLL_CLK_INFO g_pll_info;
+extern const char PLL_FM_clock[PLL_FM_NUM][32];
+
+/* Above for debugging */
+
+/*******************************************************************************
+ * Include header files
+ ******************************************************************************/
+extern void PLL_exception_dump(void);
+
+extern kal_uint32 PLL_FrequencyMeter_GetFreq(PLL_FM_SOURCE index);
+
+extern kal_bool PLL_PLLMIXED_PLL_ON_CTL(PLL_SOURCE pll, kal_bool force_on);
+
+extern void PLL_CLKSW_FLEXCKGEN_SEL_PLLSEL_Set(PLL_CLKSW_FLEXCKGEN module, PLL_CLKSW_FLEXCKGEN_PLL_SRC pll_sel);
+extern void PLL_CLKSW_FLEXCKGEN_SEL_DIVSEL_Set(PLL_CLKSW_FLEXCKGEN module, PLL_CLKSW_FLEXCKGEN_DIV div_sel);
+extern void PLL_CLKSW_FLEXCKGEN_SEL_Get(PLL_CLKSW_FLEXCKGEN module, kal_uint32 *pll_sel, kal_uint32 *div_sel);
+extern void PLL_CLKSW_FLEXCKGEN_STS_Get(PLL_CLKSW_FLEXCKGEN module, kal_uint32 *ck_rdy, kal_uint32 *ckgen_state, kal_uint32 *pll_req);
+extern kal_bool PLL_CLKSW_MDTOPSM_SW_CTL(PLL_CLKSW_MDTOPSM_SW_CTL_SRC module, kal_bool force_on);
+
+extern kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Get();
+extern kal_bool PLL_CLKSW_SDF_SRC_CKSEL_Set(PLL_CLKSW_SDF_SRC src_ck);
+extern void PLL_CLKSW_SDF_CK_Req(kal_bool clk_req);
+
+#endif /* !__PLL_MT6763_H__ */
+
diff --git a/mcu/interface/driver/devdrv/pll/pll_gen95.h b/mcu/interface/driver/devdrv/pll/pll_gen95.h
new file mode 100644
index 0000000..9857dcb
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pll/pll_gen95.h
@@ -0,0 +1,448 @@
+/*******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2012
+ *
+ * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * pll_gen95.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * PLL Related Functions
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ============================================================================
+ * $Log$
+ *
+ * 07 25 2018 jun-ying.huang
+ * [MOLY00342276] [MT6779]Add MT6779 macro for LATIFE
+ * .
+ *
+ * 05 30 2018 jun-ying.huang
+ * [MOLY00325066] [MT3967][PLL]Update PLL golden setting
+ * Remove redundant define
+ *
+ * 05 16 2018 jun-ying.huang
+ * [MOLY00325066] [MT3967][PLL]Update PLL golden setting
+ * Update 26M settle time and remove redundant function.
+ *
+ * 12 11 2017 jun-ying.huang
+ * [MOLY00295410] [PLL][MT3967] Add Macro for MT3967
+ * .
+ *
+ * 10 30 2017 jun-ying.huang
+ * [MOLY00286084] [MT6295][PLL] Update BR_EXT section for BootRom
+ * .
+ *
+ * 08 29 2017 jun-ying.huang
+ * [MOLY00261263] [MT6295M]Update PLL driver
+ * Add PLL driver for BootRom
+ *
+ * 07 10 2017 jun-ying.huang
+ * [MOLY00261263] [MT6295M]Update PLL driver
+ * 1st version for MT6295M=EIGER
+ *
+ * 05 23 2017 jun-ying.huang
+ * [MOLY00244448] [MT6295M]Update PLL driver for MT6295M
+ * Fix build error
+ *
+ * 05 15 2017 jun-ying.huang
+ * [MOLY00244448] [MT6295M]Update PLL driver for MT6295M
+ * .
+ *
+ * 04 28 2017 jun-ying.huang
+ * [MOLY00244448] [MT6295M]Update PLL driver for MT6295M
+ * temp driver for 6295
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __PLL_MT6295_H__
+#define __PLL_MT6295_H__
+
+/*******************************************************************************
+ * Locally Used Options
+ ******************************************************************************/
+#define PLL_REG32(addr) *(volatile kal_uint32 *)(addr)
+#define PLL_TYPE (volatile kal_uint32 *)
+
+/*******************************************************************************
+ * Define macro for boot code
+ ******************************************************************************/
+#define __SECTION__(S) __attribute__((__section__(#S)))
+#define __PLL_CODE_IN_BOOT__ __SECTION__(BR_EXT)/* "BR_EXT" section for bootROM */
+
+/*******************************************************************************
+ * Register Define
+ ******************************************************************************/
+
+///////////////////////////////////////////////////////////////////////////////
+/// PLLMIXED (0xA0140000)
+///////////////////////////////////////////////////////////////////////////////
+/* ==========PLL setting========== */
+#define REG_MDTOP_PLLMIXED_CODA_VERSION (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x0))
+#define REG_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4))
+#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x8))
+#define REG_MDTOP_PLLMIXED_DCXO_MODE_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC))
+#define REG_MDTOP_PLLMIXED_PLL_ON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x14))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x18))
+#define REG_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x1C))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x34))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x38))
+
+/* ==========PLL frequency control==> PCW & POSDIV========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x40))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x44))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x48))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x54))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x58))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x60))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x64))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x100))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x104))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x108))
+
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10C))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x110))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_RSTB (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x114))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_EN (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x118))
+#define REG_MDTOP_PLLMIXED_PLL_SRC_SEL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x120))
+#define REG_MDTOP_PLLMIXED_PLL_FHCTL_RST (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x200))
+//#define REG_MDTOP_PLLMIXED_CONN_DSNS_INTF (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x204))
+
+/* ==========PLL IRQ related========== */
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x300))
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x304))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x308))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30C))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_ABNORM_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x310))
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x314))
+ #define PLLMIXED_MDMCUPLL_HP_RDY_IRQ_OFFSET (1)
+ #define PLLMIXED_MDVDSPPLL_HP_RDY_IRQ_OFFSET (2)
+ #define PLLMIXED_MDBRPPLL_HP_RDY_IRQ_OFFSET (4)
+
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x318))
+#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x31C))
+
+/* PLL IRQ related macro */
+#define PLLMIXED_PLL_HP_RDY_IRQ_MASK (0x1)/* mask bit numbers for each IRQ */
+
+/* ==========PLL FHCTL========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x400))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x404))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x408))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x410))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x414))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x418))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x430))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x434))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x438))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x440))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x444))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x448))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x450))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x454))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x458))
+
+/* ==========PLL Gear Set========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x500))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x504))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x508))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50C))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x540))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x544))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x548))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x54C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C0))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C4))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C8))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5CC))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x600))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x604))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x608))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x60C))
+
+/* ==========PLL Status========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC00))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC04))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC08))
+//#define REG_MDTOP_PLLMIXED_MDTXPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC0C))
+#define REG_MDTOP_PLLMIXED_MDBPIBPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC10))
+
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC14))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC18))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC1C))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC24))
+
+#define REG_MDTOP_PLLMIXED_MDPLL1_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC40))
+#define REG_MDTOP_PLLMIXED_MDPLL1_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC44))
+
+#define REG_MDTOP_PLLMIXED_FRDDS_OFF_IRQ_MODE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD00))
+#define REG_MDTOP_PLLMIXED_HP_RDY_OFF_IRQ_MODE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD04))
+
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF00))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF04))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF08))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF0C))
+#define REG_MDTOP_PLLMIXED_PLL_STATUS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF10))
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// CLKSW (0xA0150000)
+///////////////////////////////////////////////////////////////////////////////
+#define REG_MDTOP_CLKSW_CODA_VERSION (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x0))
+#define REG_MDTOP_CLKSW_MD_SLEEP_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4))
+#define REG_MDTOP_CLKSW_MDTOPSM_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10))
+#define REG_MDTOP_CLKSW_L1TOPSM_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x14))
+#define REG_MDTOP_CLKSW_CKOFF_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x1C))
+#define REG_MDTOP_CLKSW_CLKON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x20))
+#define REG_MDTOP_CLKSW_CLKSEL_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x24))
+
+/* ==========SDF clock control related========== */
+#define REG_MDTOP_CLKSW_SDF_CK_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x28))
+#define REG_MDTOP_CLKSW_ATB_LOG_SDF_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x2C))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x30))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x34))
+
+#define REG_MDTOP_CLKSW_EXTCK_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x3C))
+
+/* ==========FLEXCKGEN_SEL========== */
+#define REG_MDTOP_CLKSW_MDCORE_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x40))
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x44))
+#define REG_MDTOP_CLKSW_VDSP_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x48))
+#define REG_MDTOP_CLKSW_BRP_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4C))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x50))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x54))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x58))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x5C))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x60))
+#define REG_MDTOP_CLKSW_MML2_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x64))
+#define REG_MDTOP_CLKSW_RXAGC_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x68))
+#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x6C))
+#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x70))
+#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x74))
+#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x78))
+#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x7C))
+
+/* ==========FLEXCKGEN_STS========== */
+#define REG_MDTOP_CLKSW_MDCORE_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA0))
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA4))
+#define REG_MDTOP_CLKSW_VDSP_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA8))
+#define REG_MDTOP_CLKSW_BRP_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xAC))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB0))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB4))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB8))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xBC))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC0))
+#define REG_MDTOP_CLKSW_MML2_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC4))
+#define REG_MDTOP_CLKSW_RXAGC_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC8))
+#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xCC))
+#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE0))
+#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE4))
+#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE8))
+#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xEC))
+
+#define REG_MDTOP_CLKSW_CKMUX_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF0))
+#define REG_MDTOP_CLKSW_PLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF4))
+#define REG_MDTOP_CLKSW_DFS_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF8))
+
+/* ==========direct pll request========== */
+#define REG_MDTOP_CLKSW_MDMCU_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x100))
+#define REG_MDTOP_CLKSW_MDBUS_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x104))
+#define REG_MDTOP_CLKSW_VDSP_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x108))
+#define REG_MDTOP_CLKSW_BRP_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10C))
+
+/* ==========Frequency Meter========== */
+#define REG_MDTOP_CLKSW_CKMON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x200))
+#define REG_MDTOP_CLKSW_FREQ_METER_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x204))
+#define REG_MDTOP_CLKSW_FREQ_METER_XTAL_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x208))
+#define REG_MDTOP_CLKSW_FREQ_METER_CKMON_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x20C))
+#define REG_MDTOP_CLKSW_FREQ_METER_H (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x210))
+#define REG_MDTOP_CLKSW_FREQ_METER_L (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x214))
+
+/* ==========DUMMY & STATUS========== */
+#define REG_MDTOP_CLKSW_CLK_DUMMY (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF00))
+#define REG_MDTOP_CLKSW_CLK_STATUS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF04))
+
+
+/*******************************************************************************
+ * Define Macro
+ ******************************************************************************/
+#define MD_PLL_MAGIC_NUM 0x62950000
+#define MD_PLL_MAGIC_26M 0x62950026
+#define MD_PLL_MAGIC_MD 0x62951111
+
+/**
+ * PLL divider definition
+ */
+#if defined(MT6295M) || defined(MT3967) || defined(MT6779)
+ #define MDBPIPLL_DIVIDER (1) /* /2 /3 /4 /5 /6 /7 */
+ #define MDBRPPLL_DIVIDER (6)
+ #define MDVDSPPLL_DIVIDER (4)
+ #define MDMCUPLL_DIVIDER (4)
+#else
+ #error "Unsupported Chip Target in PLL Module"
+#endif
+
+ /*------------------------------------------------------------------------
+ * Purpose: Transfer PCW in xxxPLL_STS to Mhz. This macro is porting from md_dvfs_pll_freq_get(const PLL_SOURCE pll).
+ * Parameters:
+ * Input: pcw: The PCW value in xxxPLL_STS.
+ * divier: The divier for this PLL(EX: ICCPLL_DIVIDER, IMCPLL_DIVIDER...).
+ * Output: None.
+ * returns : Mhz.
+ * Note : This macr is only used to transfer pcw in xxxPLL_STS to Mhz.
+ * You should not used this macro to transfer pcw in xxxPLL_CTL0 to Mhz due to the meaning is different.
+ * (PCW in xxxPLL_STS is bit [21:7] of xxxPLL_CTL0.)
+ *------------------------------------------------------------------------
+ */
+#define PLLMIXED_PLL_STS_SDM_PCW_TO_MHZ(pcw, divier) ((((pcw) * 26) / (1 << 7)) / divier)
+
+/*******************************************************************************
+ * ENUM
+ ******************************************************************************/
+// frequency meter index list (debug only)
+typedef enum {
+ PLL_FM_SOURCE_START = 0x4,
+ PLL_FM_MDBPI_PLL_D4 = 0x4,
+ PLL_FM_MDBPI_PLL_D6 = 0x5,
+ PLL_FM_MDSYS_MML2_CLOCK = 0x6,
+ PLL_FM_FESYS_RXAGC_CLOCK = 0x7,
+ PLL_FM_MDRXSYS_DFESYNC_CLOCK = 0x8,
+ PLL_FM_FESYS_F208M_CLOCK = 0x9,
+ PLL_FM_TRACE_MON_CLOCK = 0xA,
+ PLL_FM_MDSYS_208M_CLOCK = 0xB,
+ PLL_FM_MDRXSYS_RAKE_CLOCK = 0xC,
+ PLL_FM_MDRXSYS_BRP_CLOCK = 0xD,
+ PLL_FM_MDRXSYS_VDSP_CLOCK = 0xE,
+ PLL_FM_MDTOP_LOG_ATB_CLOCK = 0xF,
+ PLL_FM_FESYS_CSYS_CLOCK = 0x10,
+// PLL_FM_FESYS_TXSYS_CLOCK = 0x11,
+ PLL_FM_FESYS_BSI_CLOCK = 0x12,
+ PLL_FM_MDSYS_MDCORE_CLOCK = 0x13,
+ PLL_FM_MDSYS_BUS2X_NODCM_CLOCK = 0x14,
+ PLL_FM_MDSYS_BUS2X_CLOCK = 0x15,
+ PLL_FM_MDTOP_DBG_CLOCK = 0x16,
+ PLL_FM_MDTOP_F32K_CLOCK = 0x17,
+ PLL_FM_AD_MDBPI_PLL_D7 = 0x18, /* AD means "analog to digital" */
+ PLL_FM_AD_MDBPI_PLL_D5 = 0x19,
+ PLL_FM_AD_MDBPI_PLL_D4 = 0x1A,
+ PLL_FM_AD_MDBPI_PLL_D3 = 0x1B,
+ PLL_FM_AD_MDBPI_PLL_D2 = 0x1C,
+ PLL_FM_AD_MDBRP_PLL = 0x1D,
+ PLL_FM_AD_MDVDSP_PLL = 0x1E,
+ PLL_FM_AD_MDMCU_PLL = 0x1F,
+ PLL_FM_SOURCE_END = 0x1F
+} PLL_FM_SOURCE;
+
+typedef enum {
+ CLKSW_SDF_SRC_BPIPLL_DIV8 = 0,
+ CLKSW_SDF_SRC_BPIPLL_DIV4 = 1,
+ CLKSW_SDF_SRC_BPIPLL = 2,
+ CLKSW_SDF_SRC_BPIPLL_DIV2 = 3,
+ /*CLKSW_SDF_SRC_USB_PhyLink = 4,*/ /* HW didn't support. */
+ CLKSW_SDF_SRC_26M,
+ CLKSW_SDF_SRC_END
+} PLL_CLKSW_SDF_SRC;
+
+/* Below for debugging */
+
+#define PLL_FM_NUM 30 /* Note: This number should also sync to EE owner. */
+typedef struct {
+ kal_uint32 MDBPI_PLL_D4; /* 0 */
+ kal_uint32 MDBPI_PLL_D6;
+ kal_uint32 MDSYS_MML2_CLOCK;
+ kal_uint32 FESYS_RXAGC_CLOCK;
+ kal_uint32 MDRXSYS_DFESYNC_CLOCK;
+ kal_uint32 FESYS_F208M_CLOCK; /* 5 */
+ kal_uint32 TRACE_MON_CLOCK;
+ kal_uint32 MDSYS_208M_CLOCK;
+ kal_uint32 MDRXSYS_RAKE_CLOCK;
+ kal_uint32 MDRXSYS_BRP_CLOCK;
+ kal_uint32 MDRXSYS_VDSP_CLOCK; /* 10 */
+ kal_uint32 MDTOP_LOG_ATB_CLOCK;
+ kal_uint32 FESYS_CSYS_CLOCK;
+ kal_uint32 FESYS_BSI_CLOCK;
+ kal_uint32 MDSYS_MDCORE_CLOCK;
+ kal_uint32 MDSYS_BUS2X_NODCM_CLOCK; /* 15 */
+ kal_uint32 MDSYS_BUS2X_CLOCK;
+ kal_uint32 MDTOP_DBG_CLOCK;
+ kal_uint32 AD_MDBPI_PLL_D7;
+ kal_uint32 AD_MDBPI_PLL_D5;
+ kal_uint32 AD_MDBPI_PLL_D4; /* 20 */
+ kal_uint32 AD_MDBPI_PLL_D3;
+ kal_uint32 AD_MDBPI_PLL_D2;
+ kal_uint32 AD_MDBRP_PLL;
+ kal_uint32 AD_MDVDSP_PLL;
+ kal_uint32 AD_MDMCU_PLL; /* 25 */
+/* below no use */
+ kal_uint32 NULL_26;
+ kal_uint32 NULL_27;
+ kal_uint32 NULL_28;
+ kal_uint32 NULL_29;
+} PLL_CLK_INFO;
+
+extern PLL_CLK_INFO g_pll_info;
+extern const char PLL_FM_clock[PLL_FM_NUM][32];
+
+/* Above for debugging */
+
+/*******************************************************************************
+ * Include header files
+ ******************************************************************************/
+extern void PLL_MD_Pll_Init(void);
+extern void PLL_Set_CLK_To_26M(void);
+
+extern void PLL_exception_dump(void);
+extern kal_uint32 PLL_FrequencyMeter_GetFreq(PLL_FM_SOURCE index);
+
+/* For SDF user in driver/sib_drv/sdf/src/md95/drv_sdf_95.c */
+extern kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Get();
+extern kal_bool PLL_CLKSW_SDF_SRC_CKSEL_Set(PLL_CLKSW_SDF_SRC src_ck);
+
+#endif /* !__PLL_MT6295_H__ */
+
diff --git a/mcu/interface/driver/devdrv/pll/pll_gen97.h b/mcu/interface/driver/devdrv/pll/pll_gen97.h
new file mode 100644
index 0000000..bafaaf2
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pll/pll_gen97.h
@@ -0,0 +1,642 @@
+/*******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2012
+ *
+ * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * pll_gen97.h
+ *
+ * Project:
+ * --------
+ * UMOLYE
+ *
+ * Description:
+ * ------------
+ * PLL Related Functions
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ============================================================================
+ * $Log$
+ *
+ * 11 24 2020 e-lin.ho
+ * [MOLY00593429] [Gen97] Check-in debug code to get high precision MDPLL frequency in exception flow
+ *
+ * [Gen97] Check-in debug code to get high precision MDPLL frequency in exception flow
+ *
+ * 06 17 2020 jun-ying.huang
+ * [MOLY00535069] [MMRFD][UCNT] Read D die PLL CNT at exception flow
+ * Add PLL related function
+ *
+ * 11 05 2019 jun-ying.huang
+ * [MOLY00457260] [MARGAUX call for check-in]Update related driver for MARGAUX
+ * .
+ *
+ * 09 03 2019 jun-ying.huang
+ * [MOLY00431611] [VMOLY][Petrus]Update related driver for Petrus.
+ * Update AMIF&PLL driver
+ *
+ * 12 05 2018 jun-ying.huang
+ * [MOLY00370736] [MT6885]Update PLL for MT6885
+ * .
+ *
+ * 08 09 2018 jun-ying.huang
+ * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97
+ * .
+ *
+ * 07 13 2018 jun-ying.huang
+ * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97
+ * .
+ *
+ * 06 06 2018 jun-ying.huang
+ * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97
+ * .
+ *
+ * 05 30 2018 jun-ying.huang
+ * [MOLY00329887] [MT6297][APOLLO]Update PLL driver for Gen97
+ * draft version
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __PLL_MT6297_H__
+#define __PLL_MT6297_H__
+
+/*******************************************************************************
+ * Locally Used Options
+ ******************************************************************************/
+#define PLL_REG32(addr) *(volatile kal_uint32 *)(addr)
+#define PLL_TYPE (volatile kal_uint32 *)
+
+/*******************************************************************************
+ * Define macro for boot code
+ ******************************************************************************/
+#define __SECTION__(S) __attribute__((__section__(#S)))
+#define __PLL_CODE_IN_BOOT__ __SECTION__(BR_EXT)/* "BR_EXT" section for bootROM */
+
+/*******************************************************************************
+ * Register Define
+ ******************************************************************************/
+
+///////////////////////////////////////////////////////////////////////////////
+/// PLLMIXED (0xA0140000)
+///////////////////////////////////////////////////////////////////////////////
+/* ==========PLL setting========== */
+#define REG_MDTOP_PLLMIXED_CODA_VERSION (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x0))
+#define REG_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4))
+#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x8))
+#define REG_MDTOP_PLLMIXED_DCXO_MODE_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC))
+#define REG_MDTOP_PLLMIXED_PLL_ON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x14))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x18))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x1C))
+#define REG_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x20))
+#define REG_MDTOP_PLLMIXED_RF_SETTLE_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x24))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x34))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x38))
+
+/* ==========PLL frequency control==> PCW & POSDIV========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x40))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x44))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x48))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x54))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x58))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x68))
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x6C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x70))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x74))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x78))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x7C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x80))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x84))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x88))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x8C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x90))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x94))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x98))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x9C))
+#define REG_MDTOP_PLLMIXED_MDPLLGP_RESERVE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xA0))
+
+#define REG_MDTOP_PLLMIXED_MDPLLGP1_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x100))
+#define REG_MDTOP_PLLMIXED_MDPLLGP2_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x104))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10C))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x110))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x114))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE4 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x118))
+
+#define REG_MDTOP_PLLMIXED_PLL_DIV_RSTB (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x120))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_EN0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x124))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_EN2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x12C))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_EN3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x130))
+#define REG_MDTOP_PLLMIXED_PLL_SRC_SEL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x140))
+
+#define REG_MDTOP_PLLMIXED_PLL_FHCTL_RST (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x200))
+
+/* ==========PLL IRQ related========== */
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x300))
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x304))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x308))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30C))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_ABNORM_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x310))
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x314))
+ #define PLLMIXED_MDMCUPLL_HP_RDY_IRQ_OFFSET (1)
+ #define PLLMIXED_MDVDSPPLL_HP_RDY_IRQ_OFFSET (2)
+ #define PLLMIXED_MDBRPPLL_HP_RDY_IRQ_OFFSET (3)
+
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x318))
+#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x31C))
+
+/* PLL IRQ related macro */
+#define PLLMIXED_PLL_HP_RDY_IRQ_MASK (0x1)/* mask bit numbers for each IRQ */
+
+/* ==========PLL FHCTL========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x400))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x404))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x408))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x410))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x414))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x418))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x420))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x424))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x428))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x430))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x434))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x438))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x450))
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x454))
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x458))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x460))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x464))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x468))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x470))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x474))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x478))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x480))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x484))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x488))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x490))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x494))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x498))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4A0))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4A4))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4A8))
+#define REG_MDTOP_PLLMIXED_MDPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4B0))
+#define REG_MDTOP_PLLMIXED_MDPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4B4))
+#define REG_MDTOP_PLLMIXED_MDPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4B8))
+
+/* ==========PLL Gear Set========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x500))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x504))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x508))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50C))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x510))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x514))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x518))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x51C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x520))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x524))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x528))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x52C))
+
+/* ==========PLL Status========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x800))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x804))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x808))
+#define REG_MDTOP_PLLMIXED_MDBPIBPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x810))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x818))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x81C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x820))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x824))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x828))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x82C))
+#define REG_MDTOP_PLLMIXED_MDPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x830))
+
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC14))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC18))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC1C))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC20))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC28))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC2C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC30))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC34))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC38))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC3C))
+#define REG_MDTOP_PLLMIXED_MDPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC40))
+
+#define REG_MDTOP_PLLMIXED_FRDDS_OFF_IRQ_MODE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD00))
+#define REG_MDTOP_PLLMIXED_HP_RDY_OFF_IRQ_MODE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD04))
+
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF00))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF04))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF08))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF0C))
+#define REG_MDTOP_PLLMIXED_PLL_STATUS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF10))
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// CLKSW (0xA0150000)
+///////////////////////////////////////////////////////////////////////////////
+#define REG_MDTOP_CLKSW_CODA_VERSION (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x0))
+#define REG_MDTOP_CLKSW_MD_SLEEP_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4))
+#define REG_MDTOP_CLKSW_RFSLPC_SW_CTRL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x8))
+#define REG_MDTOP_CLKSW_MDTOPSM_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10))
+#define REG_MDTOP_CLKSW_L1TOPSM_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x14))
+#define REG_MDTOP_CLKSW_L1TOPSM_SW_CTL2 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x18))
+#define REG_MDTOP_CLKSW_CKOFF_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x1C))
+#define REG_MDTOP_CLKSW_CLKON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x20))
+#define REG_MDTOP_CLKSW_CLKSEL_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x24))
+#define REG_MDTOP_CLKSW_CLKSEL_CTL_2 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x28))
+
+/* ==========SDF clock control related========== */
+#define REG_MDTOP_CLKSW_SDF_ATB_CK_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x2C))
+#define REG_MDTOP_CLKSW_ATB_LOG_SDF_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x30))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x34))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x38))
+
+#define REG_MDTOP_CLKSW_EXTCK_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x40))
+
+/* ==========FLEXCKGEN_SEL========== */
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x44))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x48))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4C))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x50))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x54))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x58))
+#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x5C))
+#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x70))
+#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x74))
+#define REG_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x78))
+#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x7C))
+#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x80))
+
+#define REG_MDTOP_CLKSW_NR_CS_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x84))
+#define REG_MDTOP_CLKSW_NR_CM_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x88))
+#define REG_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x8C))
+#define REG_MDTOP_CLKSW_VCORE_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x90))
+#define REG_MDTOP_CLKSW_MCORE_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x94))
+#define REG_MDTOP_CLKSW_RXDDM_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x98))
+#define REG_MDTOP_CLKSW_RXDBRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x9C))
+#if defined(MT6297)/* Only support APOLLO */
+#define REG_MDTOP_CLKSW_RXCSI_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA0))
+#endif
+#define REG_MDTOP_CLKSW_FETXBSRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA4))
+#define REG_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA8))
+#define REG_MDTOP_CLKSW_NR_RXT2F_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xAC))
+#define REG_MDTOP_CLKSW_CPC_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB0))
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB4))
+#if defined(MT6297) /* APOLLO */
+#define REG_MDTOP_CLKSW_IA_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB8))
+#else/* MT6885 and later */
+#define REG_MDTOP_CLKSW_RXDFE_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB8))
+#endif
+#define REG_MDTOP_CLKSW_BUS2X_NODCM_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xBC))
+#if defined(MT6297)/* APOLLO */
+/* APOLLO didn't support */
+#else/* MT6885 and later */
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FIXED_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC0))
+#endif
+
+/* ==========FLEXCKGEN_STS========== */
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xCC))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD0))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD4))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD8))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xDC))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE0))
+#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE4))
+#define REG_MDTOP_CLKSW_MDPLL_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE8))
+
+#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF0))
+#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF4))
+#define REG_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF8))
+#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xFC))
+#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x100))
+#define REG_MDTOP_CLKSW_NR_CS_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x104))
+#define REG_MDTOP_CLKSW_NR_CM_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x108))
+#define REG_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10C))
+#define REG_MDTOP_CLKSW_VCORE_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x110))
+#define REG_MDTOP_CLKSW_MCORE_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x114))
+#define REG_MDTOP_CLKSW_RXDDM_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x118))
+#define REG_MDTOP_CLKSW_RXDBRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x11C))
+#if defined(MT6297)/* Only support APOLLO */
+#define REG_MDTOP_CLKSW_RXCSI_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x120))
+#endif
+#define REG_MDTOP_CLKSW_FETXBSRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x124))
+#define REG_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x12C))
+#define REG_MDTOP_CLKSW_NR_RXT2F_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x130))
+#define REG_MDTOP_CLKSW_CPC_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x134))
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x138))
+#if defined(MT6297)/* APOLLO */
+#define REG_MDTOP_CLKSW_IA_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x13C))
+#else/* MT6885 and later */
+#define REG_MDTOP_CLKSW_RXDFE_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x13C))
+#endif
+#define REG_MDTOP_CLKSW_BUS2X_NODCM_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x140))
+#if defined(MT6297)/* APOLLO */
+/* APOLLO didn't support */
+#else/* MT6885 and later */
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FIXED_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x144))
+#endif
+
+#define REG_MDTOP_CLKSW_CKMUX_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x200))
+#define REG_MDTOP_CLKSW_PLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x210))
+#define REG_MDTOP_CLKSW_DFS_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x220))
+#define REG_MDTOP_CLKSW_DFS_STS_2 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x224))
+
+/* ==========direct pll request========== */
+#define REG_MDTOP_CLKSW_MDMCU_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x300))
+#define REG_MDTOP_CLKSW_MDBUS_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x304))
+#define REG_MDTOP_CLKSW_VDSP_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x308))
+#define REG_MDTOP_CLKSW_BRP_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x30C))
+
+/* ==========Frequency Meter========== */
+#define REG_MDTOP_CLKSW_CKMON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x400))
+#define REG_MDTOP_CLKSW_FREQ_METER_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x404))
+#define REG_MDTOP_CLKSW_FREQ_METER_XTAL_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x408))
+#define REG_MDTOP_CLKSW_FREQ_METER_CKMON_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x40C))
+#define REG_MDTOP_CLKSW_FREQ_METER_H (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x410))
+#define REG_MDTOP_CLKSW_FREQ_METER_L (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x414))
+
+#define REG_MDTOP_CLKSW_CLK_REQ_MON (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x500))
+#define REG_MDTOP_CLKSW_CLK_RDY_MON (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x504))
+
+/* ==========DUMMY & STATUS========== */
+#define REG_MDTOP_CLKSW_CLK_DUMMY (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF00))
+#define REG_MDTOP_CLKSW_CLK_STATUS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF04))
+
+
+/*******************************************************************************
+ * Define Macro
+ ******************************************************************************/
+#define MD_PLL_MAGIC_NUM 0x62970000
+#define MD_PLL_MAGIC_26M 0x62970026
+#define MD_PLL_MAGIC_MD 0x62971111
+
+#define PLL_FM_WIMDOW (0x1FF)
+#define PLL_FM_WIMDOW_EX_MDPLL (0x3F7A0)
+#define PLL_FM_SOURCE_OCCUPIED 12345678
+
+ /*------------------------------------------------------------------------
+ * Purpose: Transfer PCW in xxxPLL_STS to Mhz. This macro is porting from md_dvfs_pll_freq_get(const PLL_SOURCE pll).
+ * Parameters:
+ * Input: pcw: The PCW value in xxxPLL_STS.
+ * divier: The divier for this PLL(EX: ICCPLL_DIVIDER, IMCPLL_DIVIDER...).
+ * Output: None.
+ * returns : Mhz.
+ * Note : This macr is only used to transfer pcw in xxxPLL_STS to Mhz.
+ * You should not used this macro to transfer pcw in xxxPLL_CTL0 to Mhz due to the meaning is different.
+ * (PCW in xxxPLL_STS is bit [21:7] of xxxPLL_CTL0.)
+ *------------------------------------------------------------------------
+ */
+#define PLLMIXED_PLL_STS_SDM_PCW_TO_MHZ(pcw, divier) ((((pcw) * 26) / (1 << 7)) / divier)
+
+/*******************************************************************************
+ * ENUM
+ ******************************************************************************/
+// frequency meter index list (debug only)
+typedef enum {
+ PLL_FM_SOURCE_START = 0x0,
+ PLL_FM_AD_MDNRPLL5 = 0x0,
+ PLL_FM_AD_MDNRPLL4_1 = 0x1,
+ PLL_FM_AD_MDNRPLL4_0 = 0x2,
+ PLL_FM_AD_MDNRPLL3 = 0x3,
+ PLL_FM_AD_MDNRPLL2 = 0x4,
+ PLL_FM_AD_MDNRPLL1 = 0x5,
+ PLL_FM_AD_MDNRPLL0 = 0x6,
+ PLL_FM_MDSYS_NRL2_CLOCK = 0x7, // NRL2 = MML2
+ PLL_FM_MDRXSYS_DFESYNC_CLOCK = 0x8,
+#if defined(MT6297)/* APOLLO */
+ PLL_FM_MDTOP_F208M_CLOCK = 0x9,
+ PLL_FM_TRACE_MON_CLOCK = 0xA,
+ PLL_FM_MDSYS_208M_CLOCK = 0xB,
+#else/* MT6885 and later */
+ PLL_FM_MDTOP_F216P7M_CLOCK = 0x9,
+ PLL_FM_TRACE_MON_CLOCK = 0xA,
+ PLL_FM_MDSYS_216P7M_CLOCK = 0xB,
+#endif
+ PLL_FM_MDRXSYS_RAKE_CLOCK = 0xC,
+ PLL_FM_MDRXSYS_BRP_CLOCK = 0xD,
+ PLL_FM_MDRXSYS_VDSP_CLOCK = 0xE,
+ PLL_FM_MDTOP_LOG_ATB_CLOCK = 0xF,
+ PLL_FM_FESYS_CSYS_CLOCK = 0x10,
+ PLL_FM_MDSYS_SHAOLIN_CLOCK = 0x11,
+ PLL_FM_FESYS_BSI_CLOCK = 0x12,
+ PLL_FM_MDSYS_MDCORE_CLOCK = 0x13,
+ PLL_FM_MDSYS_BUS2X_NODCM_CLOCK = 0x14,
+ PLL_FM_MDSYS_BUS4X_CLOCK = 0x15,
+ PLL_FM_MDTOP_DBG_CLOCK = 0x16,
+ PLL_FM_MDTOP_F32K_CLOCK = 0x17,
+ PLL_FM_AD_MDBPI_PLL_D7 = 0x18, /* AD means "analog to digital" */
+ PLL_FM_AD_MDBPI_PLL_D5 = 0x19,
+ PLL_FM_AD_MDBPI_PLL_D4 = 0x1A,
+ PLL_FM_AD_MDBPI_PLL_D3 = 0x1B,
+ PLL_FM_AD_MDBPI_PLL_D2 = 0x1C,
+ PLL_FM_AD_MDBRP_PLL = 0x1D,
+ PLL_FM_AD_MDVDSP_PLL = 0x1E,
+ PLL_FM_AD_MDMCU_PLL = 0x1F,
+ /* CKMON_SRC_SEL2 = 1 */
+ PLL_FM_NULL = 0x20,
+
+#if defined(MT6297)/* APOLLO */
+/* APOLLO didn't support */
+#else/* MT6885 and later */
+ PLL_FM_DFESYS_RXDFE_BB_CORE_CLOCK = 0x2E,
+ PLL_FM_AD_MDNRPLL4_2 = 0x2F,
+ PLL_FM_MDTOP_BUS4X_FIXED_CLOCK = 0x30,
+ PLL_FM_DA_DRF_26M_CLOCK = 0x31,
+#endif
+ PLL_FM_MDTOP_BUS4X_CLOCK = 0x32,
+ PLL_FM_RXCPC_CPC_CLOCK = 0x33,
+#if defined(MT6297)/* Only APOLLO support. */
+ PLL_FM_RXDDMBRP_RXCSI_CLOCK = 0x34,
+#endif
+ PLL_FM_RXDDMBRP_RXDBRP_CLOCK = 0x35,
+ PLL_FM_RXDDMBRP_RXDDM_CLOCK = 0x36,
+ PLL_FM_MCORE_MCORE_CLOCK = 0x37,
+ PLL_FM_VCOREHRAM_VCORE_CLOCK = 0x38,
+ PLL_FM_VCOREHRAM_HRAM_CLOCK = 0x39,
+ PLL_FM_FESYS_TXBSRP_CLOCK = 0x3A,
+ PLL_FM_FESYS_MDPLL_CLOCK = 0x3B,
+ PLL_FM_TX_CS_NR_RXT2F_NR_CLOCK = 0x3C,
+ PLL_FM_TX_CS_NR_TXBSRP_NR_CLOCK= 0x3D,
+ PLL_FM_TX_CS_NR_CM_NR_CLOCK = 0x3E,
+ PLL_FM_TX_CS_NR_CS_NR_CLOCK = 0x3F,
+#if defined(MT6297)/* Only APOLLO support. */
+ PLL_FM_MDSYS_IA_CLOCK = 0x40,
+ PLL_FM_SOURCE_END = 0x40
+#else/* MT6885 and later */
+ PLL_FM_SOURCE_END = 0x3F
+#endif
+} PLL_FM_SOURCE;
+
+typedef enum {
+#if defined(MT6297)/* APOLLO */
+ CLKSW_SDF_SRC_MDPLL_F624M = 0,
+ CLKSW_SDF_SRC_TOP_BUS4X = 1,
+ CLKSW_SDF_SRC_MDPLL_F312M = 2,
+ CLKSW_SDF_SRC_MDPLL_F208M = 3,
+#else/* MT6885 and later */
+ CLKSW_SDF_SRC_MDPLL_F650M = 0,
+ CLKSW_SDF_SRC_TOP_BUS4X = 1,
+ CLKSW_SDF_SRC_MDPLL_F325M = 2,
+ CLKSW_SDF_SRC_MDPLL_F216P7M = 3,
+#endif
+ CLKSW_SDF_SRC_26M,
+ CLKSW_SDF_SRC_END
+} PLL_CLKSW_SDF_SRC;
+
+typedef enum {
+ CLKSW_SDF_SRC_DIV_1 = 0,
+ CLKSW_SDF_SRC_DIV_2 = 1,
+ CLKSW_SDF_SRC_DIV_3 = 2,
+ CLKSW_SDF_SRC_DIV_4 = 3
+} PLL_CLKSW_SDF_SRC_DIV;
+
+/* Below for debugging */
+
+#define PLL_FM_NUM 48 /* Note: This number should also sync to EE owner. */
+typedef struct {
+ kal_uint32 AD_MDNRPLL5; /* 0 */
+ kal_uint32 AD_MDNRPLL4_1;
+ kal_uint32 AD_MDNRPLL4_0;
+ kal_uint32 AD_MDNRPLL3;
+ kal_uint32 AD_MDNRPLL2;
+ kal_uint32 AD_MDNRPLL1; /* 5 */
+ kal_uint32 AD_MDNRPLL0;
+ kal_uint32 MDSYS_NRL2_CLOCK;
+ kal_uint32 MDRXSYS_DFESYNC_CLOCK;
+#if defined(MT6297)/* APOLLO */
+ kal_uint32 MDTOP_F208M_CLOCK;
+ kal_uint32 TRACE_MON_CLOCK; /* 10 */
+ kal_uint32 MDSYS_208M_CLOCK;
+#else/* MT6885 and later */
+ kal_uint32 MDTOP_F216P7M_CLOCK;
+ kal_uint32 TRACE_MON_CLOCK; /* 10 */
+ kal_uint32 MDSYS_216P7M_CLOCK;
+#endif
+ kal_uint32 MDRXSYS_RAKE_CLOCK;
+ kal_uint32 MDRXSYS_BRP_CLOCK;
+ kal_uint32 MDRXSYS_VDSP_CLOCK;
+ kal_uint32 MDTOP_LOG_ATB_CLOCK; /* 15 */
+ kal_uint32 FESYS_CSYS_CLOCK;
+ kal_uint32 MDSYS_SHAOLIN_CLOCK;
+ kal_uint32 FESYS_BSI_CLOCK;
+ kal_uint32 MDSYS_MDCORE_CLOCK;
+ kal_uint32 MDSYS_BUS2X_NODCM_CLOCK; /* 20 */
+ kal_uint32 MDSYS_BUS4X_CLOCK;
+ kal_uint32 MDTOP_DBG_CLOCK;
+ kal_uint32 AD_MDBPI_PLL_D7;
+ kal_uint32 AD_MDBPI_PLL_D5;
+ kal_uint32 AD_MDBPI_PLL_D4; /* 25 */
+ kal_uint32 AD_MDBPI_PLL_D3;
+ kal_uint32 AD_MDBPI_PLL_D2;
+ kal_uint32 AD_MDBRP_PLL;
+ kal_uint32 AD_MDVDSP_PLL;
+ kal_uint32 AD_MDMCU_PLL; /* 30 */
+#if defined(MT6297)/* APOLLO */
+ kal_uint32 MDTOP_BUS4X_CLOCK;
+ kal_uint32 RXCPC_CPC_CLOCK;
+ kal_uint32 RXDDMBRP_RXCSI_CLOCK;
+ kal_uint32 RXDDMBRP_RXDBRP_CLOCK;
+ kal_uint32 RXDDMBRP_RXDDM_CLOCK; /* 35 */
+ kal_uint32 MCORE_MCORE_CLOCK;
+ kal_uint32 VCOREHRAM_VCORE_CLOCK;
+ kal_uint32 VCOREHRAM_HRAM_CLOCK;
+ kal_uint32 FESYS_TXBSRP_CLOCK;
+ kal_uint32 FESYS_MDPLL_CLOCK; /* 40 */
+ kal_uint32 TX_CS_NR_RXT2F_NR_CLOCK;
+ kal_uint32 TX_CS_NR_TXBSRP_NR_CLOCK;
+ kal_uint32 TX_CS_NR_CM_NR_CLOCK;
+ kal_uint32 TX_CS_NR_CS_NR_CLOCK;
+ kal_uint32 NULL_45;
+ kal_uint32 NULL_46;
+ kal_uint32 NULL_47;
+#else/* MT6885 and later */
+ kal_uint32 DFESYS_RXDFE_BB_CORE_CLOCK;
+ kal_uint32 AD_MDNRPLL4_2;
+ kal_uint32 MDTOP_BUS4X_FIXED_CLOCK;
+ kal_uint32 DA_DRF_26M_CLOCK;
+ kal_uint32 MDTOP_BUS4X_CLOCK; /* 35 */
+ kal_uint32 RXCPC_CPC_CLOCK;
+ kal_uint32 RXDDMBRP_RXDBRP_CLOCK;
+ kal_uint32 RXDDMBRP_RXDDM_CLOCK;
+ kal_uint32 MCORE_MCORE_CLOCK;
+ kal_uint32 VCOREHRAM_VCORE_CLOCK; /* 40 */
+ kal_uint32 VCOREHRAM_HRAM_CLOCK;
+ kal_uint32 FESYS_TXBSRP_CLOCK;
+ kal_uint32 FESYS_MDPLL_CLOCK;
+ kal_uint32 TX_CS_NR_RXT2F_NR_CLOCK;
+ kal_uint32 TX_CS_NR_TXBSRP_NR_CLOCK;/* 45 */
+ kal_uint32 TX_CS_NR_CM_NR_CLOCK;
+ kal_uint32 TX_CS_NR_CS_NR_CLOCK;
+ /* we couldn't add more PLL here... */
+#endif
+
+} PLL_CLK_INFO;
+
+extern PLL_CLK_INFO g_pll_info;
+extern const char PLL_FM_clock[PLL_FM_NUM][32];
+
+/* Above for debugging */
+
+/*******************************************************************************
+ * Include header files
+ ******************************************************************************/
+extern void PLL_MD_Pll_Init(void);
+extern void PLL_Set_CLK_To_26M(void);
+
+extern void PLL_Check_26M_ACK_Status(kal_uint32 identifier);
+extern void PLL_Clear_26M_ACK_Status(void);
+extern void PLL_exception_dump(void);
+extern kal_uint32 PLL_FrequencyMeter_GetFreq(PLL_FM_SOURCE index);
+extern kal_uint32 PLL_FrequencyMeter_GetCKMON_CNT(PLL_FM_SOURCE index, kal_uint32 xta_cnt, kal_uint32 *ckmon_cnt);
+
+/* For SDF user in driver/sib_drv/sdf/src/md97/drv_sdf_97.c */
+extern kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Get();
+extern kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Div_Get();
+extern kal_bool PLL_CLKSW_SDF_SRC_CKSEL_Set(PLL_CLKSW_SDF_SRC src_clk, PLL_CLKSW_SDF_SRC_DIV src_div);
+
+#endif /* !__PLL_MT6297_H__ */
+
diff --git a/mcu/interface/driver/devdrv/pll/pll_gen97p.h b/mcu/interface/driver/devdrv/pll/pll_gen97p.h
new file mode 100644
index 0000000..0064305
--- /dev/null
+++ b/mcu/interface/driver/devdrv/pll/pll_gen97p.h
@@ -0,0 +1,530 @@
+/*******************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2012
+ *
+ * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * pll_gen97p.h
+ *
+ * Project:
+ * --------
+ * UMOLYE
+ *
+ * Description:
+ * ------------
+ * PLL Related Functions
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ============================================================================
+ * $Log$
+ *
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __PLL_MT6297P_H__
+#define __PLL_MT6297P_H__
+//wolf: the code below is not ready, just for build pass~
+/*******************************************************************************
+ * Locally Used Options
+ ******************************************************************************/
+#define PLL_REG32(addr) *(volatile kal_uint32 *)(addr)
+#define PLL_TYPE (volatile kal_uint32 *)
+
+/*******************************************************************************
+ * Define macro for boot code
+ ******************************************************************************/
+#define __SECTION__(S) __attribute__((__section__(#S)))
+#define __PLL_CODE_IN_BOOT__ __SECTION__(BR_EXT)/* "BR_EXT" section for bootROM */
+
+/*******************************************************************************
+ * Register Define
+ ******************************************************************************/
+
+///////////////////////////////////////////////////////////////////////////////
+/// PLLMIXED (0xA0140000)
+///////////////////////////////////////////////////////////////////////////////
+/* ==========PLL setting========== */
+#define REG_MDTOP_PLLMIXED_CODA_VERSION (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x0))
+#define REG_MDTOP_PLLMIXED_DCXO_PLL_SETTLE_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4))
+#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x8))
+#define REG_MDTOP_PLLMIXED_DCXO_MODE_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC))
+#define REG_MDTOP_PLLMIXED_PLL_ON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x14))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x18))
+#define REG_MDTOP_PLLMIXED_PLL_SW_CTL2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x1C))
+#define REG_MDTOP_PLLMIXED_PLL_SETTLE_26M_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x20))
+#define REG_MDTOP_PLLMIXED_RF_SETTLE_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x24))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x34))
+#define REG_MDTOP_PLLMIXED_PLL_DLY_CTL2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x38))
+
+/* ==========PLL frequency control==> PCW & POSDIV========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x40))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x44))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x48))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x54))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x58))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x5C))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x68))
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x6C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x70))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x74))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x78))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x7C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x80))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x84))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x88))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x8C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x90))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x94))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x98))
+#define REG_MDTOP_PLLMIXED_MDPLL_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x9C))
+#define REG_MDTOP_PLLMIXED_MDPLLGP_RESERVE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xA0))
+
+#define REG_MDTOP_PLLMIXED_MDPLLGP1_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x100))
+#define REG_MDTOP_PLLMIXED_MDPLLGP2_CTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x104))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x10C))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x110))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x114))
+#define REG_MDTOP_PLLMIXED_PLL_RESERVE4 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x118))
+
+#define REG_MDTOP_PLLMIXED_PLL_DIV_RSTB (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x120))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_EN0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x124))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_EN2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x12C))
+#define REG_MDTOP_PLLMIXED_PLL_DIV_EN3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x130))
+#define REG_MDTOP_PLLMIXED_PLL_SRC_SEL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x140))
+
+#define REG_MDTOP_PLLMIXED_PLL_FHCTL_RST (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x200))
+
+/* ==========PLL IRQ related========== */
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x300))
+#define REG_MDTOP_PLLMIXED_PLL_ABNORM_GEARHP_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x304))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x308))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_WO_DCXO_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x30C))
+#define REG_MDTOP_PLLMIXED_PLL_REQ_ABNORM_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x310))
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x314))
+ #define PLLMIXED_MDMCUPLL_HP_RDY_IRQ_OFFSET (1)
+ #define PLLMIXED_MDVDSPPLL_HP_RDY_IRQ_OFFSET (2)
+ #define PLLMIXED_MDBRPPLL_HP_RDY_IRQ_OFFSET (3)
+
+#define REG_MDTOP_PLLMIXED_PLL_HP_RDY_IRQ_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x318))
+#define REG_MDTOP_PLLMIXED_DCXO_RDY_WO_ACK_MASK (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x31C))
+
+/* PLL IRQ related macro */
+#define PLLMIXED_PLL_HP_RDY_IRQ_MASK (0x1)/* mask bit numbers for each IRQ */
+
+/* ==========PLL FHCTL========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x400))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x404))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x408))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x410))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x414))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x418))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x420))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x424))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x428))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x430))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x434))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x438))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x450))
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x454))
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x458))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x460))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x464))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x468))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x470))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x474))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x478))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x480))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x484))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x488))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x490))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x494))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x498))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4A0))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4A4))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4A8))
+#define REG_MDTOP_PLLMIXED_MDPLL_FHCTL (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4B0))
+#define REG_MDTOP_PLLMIXED_MDPLL_FRDDS_LMT (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4B4))
+#define REG_MDTOP_PLLMIXED_MDPLL_SW_GEAR (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x4B8))
+
+/* ==========PLL Gear Set========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x500))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x504))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x508))
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x50C))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x510))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x514))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x518))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x51C))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET0 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x520))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x524))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x528))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_GEAR_SET3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x52C))
+
+/* ==========PLL Status========== */
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x800))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x804))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x808))
+#define REG_MDTOP_PLLMIXED_MDBPIBPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x810))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x818))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x81C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x820))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x824))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x828))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x82C))
+#define REG_MDTOP_PLLMIXED_MDPLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0x830))
+
+#define REG_MDTOP_PLLMIXED_MDMCUPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC14))
+#define REG_MDTOP_PLLMIXED_MDVDSPPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC18))
+#define REG_MDTOP_PLLMIXED_MDBRPPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC1C))
+#define REG_MDTOP_PLLMIXED_MDBPIPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC20))
+
+#define REG_MDTOP_PLLMIXED_MDNRPLL0_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC28))
+#define REG_MDTOP_PLLMIXED_MDNRPLL1_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC2C))
+#define REG_MDTOP_PLLMIXED_MDNRPLL2_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC30))
+#define REG_MDTOP_PLLMIXED_MDNRPLL3_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC34))
+#define REG_MDTOP_PLLMIXED_MDNRPLL4_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC38))
+#define REG_MDTOP_PLLMIXED_MDNRPLL5_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC3C))
+#define REG_MDTOP_PLLMIXED_MDPLL_DA (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xC40))
+
+#define REG_MDTOP_PLLMIXED_FRDDS_OFF_IRQ_MODE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD00))
+#define REG_MDTOP_PLLMIXED_HP_RDY_OFF_IRQ_MODE (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xD04))
+
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF00))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY1 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF04))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY2 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF08))
+#define REG_MDTOP_PLLMIXED_PLL_DUMMY3 (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF0C))
+#define REG_MDTOP_PLLMIXED_PLL_STATUS (PLL_TYPE(BASE_MADDR_MDTOP_PLLMIXED+0xF10))
+
+
+///////////////////////////////////////////////////////////////////////////////
+/// CLKSW (0xA0150000)
+///////////////////////////////////////////////////////////////////////////////
+#define REG_MDTOP_CLKSW_CODA_VERSION (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x0))
+#define REG_MDTOP_CLKSW_MD_SLEEP_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4))
+#define REG_MDTOP_CLKSW_RFSLPC_SW_CTRL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x8))
+#define REG_MDTOP_CLKSW_MDTOPSM_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10))
+#define REG_MDTOP_CLKSW_L1TOPSM_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x14))
+#define REG_MDTOP_CLKSW_L1TOPSM_SW_CTL2 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x18))
+#define REG_MDTOP_CLKSW_CKOFF_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x1C))
+#define REG_MDTOP_CLKSW_CLKON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x20))
+#define REG_MDTOP_CLKSW_CLKSEL_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x24))
+#define REG_MDTOP_CLKSW_CLKSEL_CTL_2 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x28))
+
+/* ==========SDF clock control related========== */
+#define REG_MDTOP_CLKSW_SDF_ATB_CK_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x2C))
+#define REG_MDTOP_CLKSW_ATB_LOG_SDF_SW_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x30))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL0 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x34))
+#define REG_MDTOP_CLKSW_LOG_ATB_CK_CTL1 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x38))
+
+#define REG_MDTOP_CLKSW_EXTCK_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x40))
+
+/* ==========FLEXCKGEN_SEL========== */
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x44))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x48))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x4C))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x50))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x54))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x58))
+#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x5C))
+#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x70))
+#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x74))
+#define REG_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x78))
+#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x7C))
+#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x80))
+
+#define REG_MDTOP_CLKSW_NR_CS_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x84))
+#define REG_MDTOP_CLKSW_NR_CM_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x88))
+#define REG_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x8C))
+#define REG_MDTOP_CLKSW_VCORE_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x90))
+#define REG_MDTOP_CLKSW_MCORE_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x94))
+#define REG_MDTOP_CLKSW_RXDDM_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x98))
+#define REG_MDTOP_CLKSW_RXDBRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x9C))
+
+#define REG_MDTOP_CLKSW_FETXBSRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA4))
+#define REG_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xA8))
+#define REG_MDTOP_CLKSW_NR_RXT2F_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xAC))
+#define REG_MDTOP_CLKSW_CPC_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB0))
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB4))
+#define REG_MDTOP_CLKSW_RXDFE_DFS_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xB8))
+#define REG_MDTOP_CLKSW_BUS2X_NODCM_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xBC))
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FIXED_FLEXCKGEN_SEL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xC0))
+
+/* ==========FLEXCKGEN_STS========== */
+#define REG_MDTOP_CLKSW_MDSYS_BUS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xCC))
+#define REG_MDTOP_CLKSW_RAKE_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD0))
+#define REG_MDTOP_CLKSW_CSSYS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD4))
+#define REG_MDTOP_CLKSW_BSI_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xD8))
+#define REG_MDTOP_CLKSW_DBG_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xDC))
+#define REG_MDTOP_CLKSW_LOG_ATB_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE0))
+#define REG_MDTOP_CLKSW_DFESYNC_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE4))
+#define REG_MDTOP_CLKSW_MDPLL_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xE8))
+
+#define REG_MDTOP_CLKSW_MML2_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF0))
+#define REG_MDTOP_CLKSW_MCU_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF4))
+#define REG_MDTOP_CLKSW_SHAOLIN_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF8))
+#define REG_MDTOP_CLKSW_VDSP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xFC))
+#define REG_MDTOP_CLKSW_BRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x100))
+#define REG_MDTOP_CLKSW_NR_CS_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x104))
+#define REG_MDTOP_CLKSW_NR_CM_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x108))
+#define REG_MDTOP_CLKSW_HRAM_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x10C))
+#define REG_MDTOP_CLKSW_VCORE_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x110))
+#define REG_MDTOP_CLKSW_MCORE_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x114))
+#define REG_MDTOP_CLKSW_RXDDM_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x118))
+#define REG_MDTOP_CLKSW_RXDBRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x11C))
+
+#define REG_MDTOP_CLKSW_FETXBSRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x124))
+#define REG_MDTOP_CLKSW_NR_TXBSRP_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x12C))
+#define REG_MDTOP_CLKSW_NR_RXT2F_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x130))
+#define REG_MDTOP_CLKSW_CPC_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x134))
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x138))
+#define REG_MDTOP_CLKSW_RXDFE_DFS_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x13C))
+#define REG_MDTOP_CLKSW_BUS2X_NODCM_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x140))
+#define REG_MDTOP_CLKSW_TOP_BUS4X_FIXED_FLEXCKGEN_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x144))
+
+#define REG_MDTOP_CLKSW_CKMUX_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x200))
+#define REG_MDTOP_CLKSW_PLL_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x210))
+#define REG_MDTOP_CLKSW_DFS_STS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x220))
+#define REG_MDTOP_CLKSW_DFS_STS_2 (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x224))
+
+/* ==========direct pll request========== */
+#define REG_MDTOP_CLKSW_MDMCU_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x300))
+#define REG_MDTOP_CLKSW_MDBUS_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x304))
+#define REG_MDTOP_CLKSW_VDSP_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x308))
+#define REG_MDTOP_CLKSW_BRP_DIRECT_PLLREQ (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x30C))
+
+/* ==========Frequency Meter========== */
+#define REG_MDTOP_CLKSW_CKMON_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x400))
+#define REG_MDTOP_CLKSW_FREQ_METER_CTL (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x404))
+#define REG_MDTOP_CLKSW_FREQ_METER_XTAL_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x408))
+#define REG_MDTOP_CLKSW_FREQ_METER_CKMON_CNT (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x40C))
+#define REG_MDTOP_CLKSW_FREQ_METER_H (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x410))
+#define REG_MDTOP_CLKSW_FREQ_METER_L (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x414))
+
+#define REG_MDTOP_CLKSW_CLK_REQ_MON (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x500))
+#define REG_MDTOP_CLKSW_CLK_RDY_MON (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0x504))
+
+/* ==========DUMMY & STATUS========== */
+#define REG_MDTOP_CLKSW_CLK_DUMMY (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF00))
+#define REG_MDTOP_CLKSW_CLK_STATUS (PLL_TYPE(BASE_MADDR_MDTOP_CLKSW+0xF04))
+
+
+/*******************************************************************************
+ * Define Macro
+ ******************************************************************************/
+#define MD_PLL_MAGIC_NUM 0x62970000
+#define MD_PLL_MAGIC_26M 0x62970026
+#define MD_PLL_MAGIC_MD 0x62971111
+
+
+ /*------------------------------------------------------------------------
+ * Purpose: Transfer PCW in xxxPLL_STS to Mhz. This macro is porting from md_dvfs_pll_freq_get(const PLL_SOURCE pll).
+ * Parameters:
+ * Input: pcw: The PCW value in xxxPLL_STS.
+ * divier: The divier for this PLL(EX: ICCPLL_DIVIDER, IMCPLL_DIVIDER...).
+ * Output: None.
+ * returns : Mhz.
+ * Note : This macr is only used to transfer pcw in xxxPLL_STS to Mhz.
+ * You should not used this macro to transfer pcw in xxxPLL_CTL0 to Mhz due to the meaning is different.
+ * (PCW in xxxPLL_STS is bit [21:7] of xxxPLL_CTL0.)
+ *------------------------------------------------------------------------
+ */
+#define PLLMIXED_PLL_STS_SDM_PCW_TO_MHZ(pcw, divier) ((((pcw) * 26) / (1 << 7)) / divier)
+
+/*******************************************************************************
+ * ENUM
+ ******************************************************************************/
+// frequency meter index list (debug only)
+typedef enum {
+ PLL_FM_SOURCE_START = 0x0,
+ PLL_FM_AD_MDNRPLL5 = 0x0,
+ PLL_FM_AD_MDNRPLL4_1 = 0x1,
+ PLL_FM_AD_MDNRPLL4_0 = 0x2,
+ PLL_FM_AD_MDNRPLL3 = 0x3,
+ PLL_FM_AD_MDNRPLL2 = 0x4,
+ PLL_FM_AD_MDNRPLL1 = 0x5,
+ PLL_FM_AD_MDNRPLL0 = 0x6,
+ PLL_FM_MDSYS_NRL2_CLOCK = 0x7, // NRL2 = MML2
+ PLL_FM_MDRXSYS_DFESYNC_CLOCK = 0x8,
+ PLL_FM_MDTOP_F216P7M_CLOCK = 0x9,
+ PLL_FM_TRACE_MON_CLOCK = 0xA,
+ PLL_FM_MDSYS_216P7M_CLOCK = 0xB,
+ PLL_FM_MDRXSYS_RAKE_CLOCK = 0xC,
+ PLL_FM_MDRXSYS_BRP_CLOCK = 0xD,
+ PLL_FM_MDRXSYS_VDSP_CLOCK = 0xE,
+ PLL_FM_MDTOP_LOG_ATB_CLOCK = 0xF,
+ PLL_FM_FESYS_CSYS_CLOCK = 0x10,
+ PLL_FM_MDSYS_SHAOLIN_CLOCK = 0x11,
+ PLL_FM_FESYS_BSI_CLOCK = 0x12,
+ PLL_FM_MDSYS_MDCORE_CLOCK = 0x13,
+ PLL_FM_MDSYS_BUS2X_NODCM_CLOCK = 0x14,
+ PLL_FM_MDSYS_BUS4X_CLOCK = 0x15,
+ PLL_FM_MDTOP_DBG_CLOCK = 0x16,
+ PLL_FM_MDTOP_F32K_CLOCK = 0x17,
+ PLL_FM_AD_MDBPI_PLL_D7 = 0x18, /* AD means "analog to digital" */
+ PLL_FM_AD_MDBPI_PLL_D5 = 0x19,
+ PLL_FM_AD_MDBPI_PLL_D4 = 0x1A,
+ PLL_FM_AD_MDBPI_PLL_D3 = 0x1B,
+ PLL_FM_AD_MDBPI_PLL_D2 = 0x1C,
+ PLL_FM_AD_MDBRP_PLL = 0x1D,
+ PLL_FM_AD_MDVDSP_PLL = 0x1E,
+ PLL_FM_AD_MDMCU_PLL = 0x1F,
+ /* CKMON_SRC_SEL2 = 1 */
+
+ PLL_FM_DFESYS_RXDFE_BB_CORE_CLOCK = 0x2E,
+ PLL_FM_AD_MDNRPLL4_2 = 0x2F,
+ PLL_FM_MDTOP_BUS4X_FIXED_CLOCK = 0x30,
+ PLL_FM_DA_DRF_26M_CLOCK = 0x31,
+ PLL_FM_MDTOP_BUS4X_CLOCK = 0x32,
+ PLL_FM_RXCPC_CPC_CLOCK = 0x33,
+
+ PLL_FM_RXDDMBRP_RXDBRP_CLOCK = 0x35,
+ PLL_FM_RXDDMBRP_RXDDM_CLOCK = 0x36,
+ PLL_FM_MCORE_MCORE_CLOCK = 0x37,
+ PLL_FM_VCOREHRAM_VCORE_CLOCK = 0x38,
+ PLL_FM_VCOREHRAM_HRAM_CLOCK = 0x39,
+ PLL_FM_FESYS_TXBSRP_CLOCK = 0x3A,
+ PLL_FM_FESYS_MDPLL_CLOCK = 0x3B,
+ PLL_FM_TX_CS_NR_RXT2F_NR_CLOCK = 0x3C,
+ PLL_FM_TX_CS_NR_TXBSRP_NR_CLOCK= 0x3D,
+ PLL_FM_TX_CS_NR_CM_NR_CLOCK = 0x3E,
+ PLL_FM_TX_CS_NR_CS_NR_CLOCK = 0x3F,
+ PLL_FM_SOURCE_END = 0x3F
+} PLL_FM_SOURCE;
+
+typedef enum {
+ CLKSW_SDF_SRC_MDPLL_F650M = 0,
+ CLKSW_SDF_SRC_TOP_BUS4X = 1,
+ CLKSW_SDF_SRC_MDPLL_F325M = 2,
+ CLKSW_SDF_SRC_MDPLL_F216P7M = 3,
+ CLKSW_SDF_SRC_26M,
+ CLKSW_SDF_SRC_END
+} PLL_CLKSW_SDF_SRC;
+
+typedef enum {
+ CLKSW_SDF_SRC_DIV_1 = 0,
+ CLKSW_SDF_SRC_DIV_2 = 1,
+ CLKSW_SDF_SRC_DIV_3 = 2,
+ CLKSW_SDF_SRC_DIV_4 = 3
+} PLL_CLKSW_SDF_SRC_DIV;
+
+/* Below for debugging */
+
+#define PLL_FM_NUM 48 /* Note: This number should also sync to EE owner. */
+typedef struct {
+ kal_uint32 AD_MDNRPLL5; /* 0 */
+ kal_uint32 AD_MDNRPLL4_1;
+ kal_uint32 AD_MDNRPLL4_0;
+ kal_uint32 AD_MDNRPLL3;
+ kal_uint32 AD_MDNRPLL2;
+ kal_uint32 AD_MDNRPLL1; /* 5 */
+ kal_uint32 AD_MDNRPLL0;
+ kal_uint32 MDSYS_NRL2_CLOCK;
+ kal_uint32 MDRXSYS_DFESYNC_CLOCK;
+ kal_uint32 MDTOP_F216P7M_CLOCK;
+ kal_uint32 TRACE_MON_CLOCK; /* 10 */
+ kal_uint32 MDSYS_216P7M_CLOCK;
+ kal_uint32 MDRXSYS_RAKE_CLOCK;
+ kal_uint32 MDRXSYS_BRP_CLOCK;
+ kal_uint32 MDRXSYS_VDSP_CLOCK;
+ kal_uint32 MDTOP_LOG_ATB_CLOCK; /* 15 */
+ kal_uint32 FESYS_CSYS_CLOCK;
+ kal_uint32 MDSYS_SHAOLIN_CLOCK;
+ kal_uint32 FESYS_BSI_CLOCK;
+ kal_uint32 MDSYS_MDCORE_CLOCK;
+ kal_uint32 MDSYS_BUS2X_NODCM_CLOCK; /* 20 */
+ kal_uint32 MDSYS_BUS4X_CLOCK;
+ kal_uint32 MDTOP_DBG_CLOCK;
+ kal_uint32 AD_MDBPI_PLL_D7;
+ kal_uint32 AD_MDBPI_PLL_D5;
+ kal_uint32 AD_MDBPI_PLL_D4; /* 25 */
+ kal_uint32 AD_MDBPI_PLL_D3;
+ kal_uint32 AD_MDBPI_PLL_D2;
+ kal_uint32 AD_MDBRP_PLL;
+ kal_uint32 AD_MDVDSP_PLL;
+ kal_uint32 AD_MDMCU_PLL; /* 30 */
+ kal_uint32 DFESYS_RXDFE_BB_CORE_CLOCK;
+ kal_uint32 AD_MDNRPLL4_2;
+ kal_uint32 MDTOP_BUS4X_FIXED_CLOCK;
+ kal_uint32 DA_DRF_26M_CLOCK;
+ kal_uint32 MDTOP_BUS4X_CLOCK; /* 35 */
+ kal_uint32 RXCPC_CPC_CLOCK;
+ kal_uint32 RXDDMBRP_RXDBRP_CLOCK;
+ kal_uint32 RXDDMBRP_RXDDM_CLOCK;
+ kal_uint32 MCORE_MCORE_CLOCK;
+ kal_uint32 VCOREHRAM_VCORE_CLOCK; /* 40 */
+ kal_uint32 VCOREHRAM_HRAM_CLOCK;
+ kal_uint32 FESYS_TXBSRP_CLOCK;
+ kal_uint32 FESYS_MDPLL_CLOCK;
+ kal_uint32 TX_CS_NR_RXT2F_NR_CLOCK;
+ kal_uint32 TX_CS_NR_TXBSRP_NR_CLOCK;/* 45 */
+ kal_uint32 TX_CS_NR_CM_NR_CLOCK;
+ kal_uint32 TX_CS_NR_CS_NR_CLOCK;
+ /* we couldn't add more PLL here... */
+
+} PLL_CLK_INFO;
+
+extern PLL_CLK_INFO g_pll_info;
+extern const char PLL_FM_clock[PLL_FM_NUM][32];
+
+/* Above for debugging */
+
+/*******************************************************************************
+ * Include header files
+ ******************************************************************************/
+extern void PLL_MD_Pll_Init(void);
+extern void PLL_Set_CLK_To_26M(void);
+
+extern void PLL_Check_26M_ACK_Status(kal_uint32 identifier);
+extern void PLL_exception_dump(void);
+extern kal_uint32 PLL_FrequencyMeter_GetFreq(PLL_FM_SOURCE index);
+
+/* For SDF user in driver/sib_drv/sdf/src/md97/drv_sdf_97.c */
+extern kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Get();
+extern kal_uint32 PLL_CLKSW_SDF_SRC_CKSEL_Div_Get();
+extern kal_bool PLL_CLKSW_SDF_SRC_CKSEL_Set(PLL_CLKSW_SDF_SRC src_clk, PLL_CLKSW_SDF_SRC_DIV src_div);
+
+#endif /* !__PLL_MT6297P_H__ */
+