[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/driver/hif/hif_cldmadev/hif_cldma.h b/mcu/interface/driver/hif/hif_cldmadev/hif_cldma.h
new file mode 100644
index 0000000..f31aa57
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_cldmadev/hif_cldma.h
@@ -0,0 +1,200 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hif_cldma.h
+ *
+ * Project:
+ * --------
+ * MT6763
+ *
+ * Description:
+ * ------------
+ * driver header of CLDMA device IP
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 11 11 2020 flamingo.wang
+ * [MOLY00526005] [Colgin] CLDMA driver code porting
+ * CLDMA driver porting to MD700.MP
+ *
+ * 09 28 2018 kun.niu
+ * [MOLY00348810] [6297][CLDMA][VMOLY] Gen97 driver and driver test porting
+ * Gen97 cldmadev driver porting.
+ *
+ * 05 02 2017 cw.wang
+ * [MOLY00245572] [CLDMA HW issue] LHIF & CLDMA SW workaround
+ * [CLDMA] add ap ip busy check for LHIF
+ *
+ * 11 10 2016 cw.wang
+ * [MOLY00212464] [CLDMA] modify CLDMADEV & CLDMACORE
+ *
+ * add for 93 cldma
+ *
+ *
+ ****************************************************************************/
+
+
+#ifndef __HIF_CLDMA_H__
+#define __HIF_CLDMA_H__
+
+#if defined(__MD95__)
+
+typedef kal_bool (*cldma_isr_callback_t)(void);
+
+
+/*!
+ * @brief to ack wakeup event, to make sure MD can sleep
+ *
+ */
+kal_uint32 hifcldma_ack_wakeup(void);
+
+/*!
+ * @brief cldma init, register ISR & unmask interrupt & reg callback
+ *
+ */
+void hifcldma_init(cldma_isr_callback_t callback);
+
+/*!
+ * @brief unmask cldma irq
+ *
+ */
+void hifcldma_irq_unmask(void);
+
+/*!
+ * @brief to get ap ip busy status
+ *
+ */
+kal_uint32 hifcldma_ap_ip_busy(void);
+
+#endif
+
+#if defined(__MD97__)
+#if defined(MT6297)||(CHIP10992)
+
+#define HIFCLDMA_MAX_ULQ_NUM 8
+#define HIFCLDMA_MAX_DLQ_NUM 8
+
+typedef struct _hifcldma_isr_status{
+ kal_uint32 L2TISAR0;
+ kal_uint32 L2TISAR1;
+ kal_uint32 L3TISAR0;
+ kal_uint32 L3TISAR1;
+ kal_uint32 L2RISAR0;
+ kal_uint32 L2RISAR1;
+ kal_uint32 L3RISAR0;
+ kal_uint32 L3RISAR1;
+ kal_uint32 L3TISAR2;
+} hifcldma_isr_status_t;
+
+typedef struct _hifcldma_property {
+
+ /*!
+ * @brief total UL QMU queues requested to configure
+ */
+ kal_uint8 ulq_num;
+ /*!
+ * @brief total DL QMU queues requested to configure
+ */
+ kal_uint8 dlq_num;
+ /*!
+ * @brief reserve for 4 bytes alignment
+ */
+ kal_uint8 reserve[2];
+
+ /*!
+ * @brief set the checksum function of QMU is enable or not
+ */
+ kal_uint8 checksum_ul_ch_en;
+ kal_uint8 checksum_dl_ch_en;
+
+ /*!
+ * @brief set the checksum bytes, KAL_FALSE = use 12bytes checksum
+ * Notice : the CLDMA IP only has 16bytes checksum now, 12bytes ability will be added in future.
+ */
+ kal_bool checksum_ul_16bytes;
+ kal_bool checksum_dl_16bytes;
+
+ /*!
+ * @brief set whether IOC function of DL queue is diable or not
+ * (if disable, the interrupt will occurs when each GPD is transfered done no matter the IOC bit of GPD)
+ */
+ kal_bool dl_ioc_dis[HIFCLDMA_MAX_DLQ_NUM];
+
+ /*!
+ * @brief cldma_isr_cb_func is the call back function for ISR
+ */
+ void (*cldma_isr_cb_func)(hifcldma_isr_status_t cldma_int_status);
+
+} hifcldma_property_t;
+
+/*!
+ * @brief initialize cldma hif driver
+ * @param
+ * @return KAL_TRUE if initial success ,
+ KAL_FALSE if initial failure.
+ */
+kal_bool hifcldma_init();
+
+/*!
+ * @brief ask cldma hif driver to set this property
+ * @param property the property cldmacore will set
+ * @return KAL_TRUE if the property can be satisfied, otherwise KAL_FALSE
+ */
+kal_bool hifcldma_set_property(hifcldma_property_t* p_cldma_property);
+
+/*!
+ * @brief to inform host that function is ready, so host can transfer normal data
+ * upper application can call this function after GPDs initial is complete.
+ */
+void hifcldma_set_func_ready();
+
+/*!
+ * @brief to check cldma hardware error statue, it will assert when error occurs
+ *
+ */
+void hifcldma_err_check();
+
+#endif
+#endif
+
+#endif
diff --git a/mcu/interface/driver/hif/hif_cldmadev/hif_cldma_except.h b/mcu/interface/driver/hif/hif_cldmadev/hif_cldma_except.h
new file mode 100644
index 0000000..ae5c775
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_cldmadev/hif_cldma_except.h
@@ -0,0 +1,128 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hif_cldma_except.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * This is the CLDMA exception handler driver API head file.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 11 11 2020 flamingo.wang
+ * [MOLY00526005] [Colgin] CLDMA driver code porting
+ * CLDMA driver porting to MD700.MP
+ *
+ * 04 03 2013 vend_mick.lin
+ * [MOLY00011933] Develop CLDMA driver
+ * MT6290 exception handle of CLDMA driver
+ *
+ * 02 04 2013 wei-de.chen
+ * [MOLY00009921] Rename project name to MT6290
+ * Change project name to MT6290
+ *
+ * 01 07 2013 wei-de.chen
+ * [MOLY00008347] [MT6290] [CCCI] CCCI re-Architecture
+ * update hifcldma_init_phase2 & API in except
+ ****************************************************************************/
+
+#ifndef __HIF_CLDMA_EXCEPT__
+#define __HIF_CLDMA_EXCEPT__
+
+#if defined(__MD97__)
+#if defined(MT6297)||(CHIP10992)
+
+#include "hif_cldma.h"
+
+
+#define EXCEPT_CLDMA_UL_QUE 0
+#define EXCEPT_CLDMA_DL_QUE 0
+
+
+/*!
+ * @brief simply delay us function ,
+ * @param delay_us , delay period in us
+ * @return
+ */
+void hifcldma_except_delay_us(kal_uint32 delay_us);
+
+/*!
+ * @brief See the sw interrupt occurs or not in polling mode
+ * @param sw_int_no , the interrupt number form 0~15
+ * @param timeout_ms , the period of polling time
+ *
+ * @return KAL_TRUE : interrupt happen in the period,
+ * KAL_FALSE : interrupt not happen in the period.
+ */
+kal_bool hifcldma_except_sw_int_poll(kal_uint8 sw_int_no, kal_uint32 timeout_ms);
+
+/*!
+ * @brief simply send a GPD,
+ * @param queue_no , the queue number form 0~n
+ * @param send_gpd , the GPD which want to send
+ * @param timeout_ms , the time interval which host should read this packet
+ * If the user do not have timeout value, set it to 0.
+ * @return KAL_TRUE : send gpd success,
+ * KAL_FALSE : send gpd fail and should not call this API again.
+ */
+kal_bool hifcldma_simple_send_gpd(kal_uint8 queue_no, qbm_gpd* send_gpd, kal_uint32 timeout_ms);
+
+/*!
+ * @brief simply receive a GPD,
+ * @param queue_no , the queue number form 0~n
+ * @param send_gpd , the GPD which want to receive
+ * @param timeout_ms , the time interval which host should read this packet
+ * If the user do not have timeout value, set it to 0.
+ * @return KAL_TRUE : receive gpd success,
+ * KAL_FALSE : receive gpd fail and should not call this API again.
+ */
+kal_bool hifcldma_simple_receive_gpd(kal_uint8 queue_no, qbm_gpd* recv_gpd, kal_uint32 timeout_ms);
+
+#endif
+#endif
+
+#endif
diff --git a/mcu/interface/driver/hif/hif_common.h b/mcu/interface/driver/hif/hif_common.h
new file mode 100644
index 0000000..b0b5abe
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_common.h
@@ -0,0 +1,560 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hif_common.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * This is the HIF data path driver API head file for both USB2.0/USB3.0/SDIO.
+ *
+ * Author:
+ * -------
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 11 16 2020 zhiqiang.yu
+ * [MOLY00595466] [Colgin]USBDRV Patchback From T700 Branch
+ *
+ * .
+ *
+ * 10 08 2018 gang.lei
+ * [MOLY00351431] DPMAIF DL Patch USB driver changes
+ * .
+ *
+ * 11 16 2017 gang.lei
+ * [MOLY00277303] [Eiger][SSUSB] UDLQ and Generator driver/test cases checkin
+ * Eiger SSUSB UDLQ driver checkin.
+ *
+ * 10 11 2017 gang.lei
+ * [MOLY00282646] [93/95 re-arch]usb driver checkin
+ * [93/95 re-arch]usb driver checkin
+ *
+ * 10 11 2017 gang.lei
+ * [MOLY00282642] [Gen93/95 Co-CodeBase]USB driver check in
+ * Gen93/95 Co-CodeBase USB driver checkin
+ *
+ * 03 28 2017 shenghui.shi
+ * [MOLY00236724] update USB DLQ driver
+ * update usb driver for merge UMOLY to UMOLYA
+ *
+ * 03 22 2017 gang.lei
+ * [MOLY00223010] UMOLYA USB Driver Checkin
+ * for ULQ type MACRO remove
+ *
+ * 03 06 2017 shenghui.shi
+ * [MOLY00233213] [SE2 Internal Test][93][BRINGUP.DEV][Sanity][20170302][1][core0,vpe0,tc0(vpe0)] Fatal Error (0x1d, 0x95c00170, 0x90221344) - USB_HIS
+ * fix DLQ flush API bug
+ *
+ * 02 21 2017 shenghui.shi
+ * [MOLY00226854] UMOLYA USB driver update
+ * drb cache align
+ *
+ * 02 21 2017 shenghui.shi
+ * [MOLY00226854] UMOLYA USB driver update
+ * udpate usb DRB flush API and add debug log
+ *
+ * 02 08 2017 gang.lei
+ * [MOLY00223010] UMOLYA USB Driver Checkin
+ * 1.fix dlq cs err issue
+ * 2.fix ulq cache flush issue
+ *
+ * 02 06 2017 gang.lei
+ * [MOLY00223010] UMOLYA USB Driver Checkin
+ * fix UDLQ Driver issue
+ *
+ * 02 15 2017 gang.lei
+ * [MOLY00223010] UMOLYA USB Driver Checkin
+ * Merge from Bringup DEV to Trunk
+ *
+ * 02 07 2017 shenghui.shi
+ * [MOLY00226854] UMOLYA USB driver update
+ * update MUSB DRB driver for cache flush issue.
+ *
+ * 01 05 2017 gang.lei
+ * [MOLY00223010] UMOLYA USB Driver Checkin
+ * <saved by Perforce>
+ ****************************************************************************/
+
+
+
+#ifndef __HIF_COMMON_H__
+#define __HIF_COMMON_H__
+
+#include "qmu_bm.h"
+//#include "kal_internal_api.h"
+
+typedef enum _hif_flush_type{
+ /*
+ * @brief set entire queue hwo=0 and return the head/tail/number
+ */
+ HIFQ_FLUSH_DEQ = 0,
+ /*
+ * @brief directly destroy whole queue and return the head/tail/number
+ */
+ HIFQ_FLUSH_FREE,
+}hif_flush_type_e;
+
+typedef enum _hif_queue_type{
+ HIFQ_TYPE_MIN = 0,
+ HIFQ_TYPE_TX, //default use the BPS
+ HIFQ_TYPE_RX, //default don't use BPS
+ HIFQ_TYPE_TX_WO_BPS, // for test only
+ HIFQ_TYPE_RX_W_BPS, // for test only
+ HIFQ_TYPE_TX_NO_FLUSH, //conjunction with HIF_QCFG_BM_TX_EMPTY_ENQ, it transmits GPD's without checksum calcuation and cache flush operations
+ HIFQ_TYPE_MAX,
+}hif_queue_type_e;
+
+typedef enum _hif_deq_type{
+ HIFQ_DEQ = 0,
+ HIFQ_FREEQ,
+ HIFQ_DEQ_TYPE2,
+#ifdef SDIO_TST
+ HIFQ_SDIO_TEST_FREEQ,
+#endif
+}hif_deq_type_e;
+
+typedef struct _hif_deq_info{
+ hif_queue_type_e q_type;
+ kal_uint8 que_no;
+ hif_deq_type_e deq_type;
+ kal_uint8 reserve[1];
+}hif_deq_info_t;
+
+/****************************************************************************
+ 93 ULDL XIT/DRB Format
+ ****************************************************************************/
+
+/****************************************************************************
+ * Structure of UL XIT
+ ****************************************************************************/
+typedef struct _usbq_ul_xit usbq_ul_xit;
+
+struct _usbq_ul_xit
+{
+ kal_uint16 ul_xfer_length;
+ kal_uint16 reserved;
+ void *p_ul_xfer_start_addr;
+};
+
+
+#define HIFUSB_QMU_GET_CURRENT_XIT_ADDR(_q) hifusbq_get_xit_start_address(_q)
+#define USBQ_GET_XIT_PTR(_q,_idx) ((usbq_ul_xit *)(HIFUSB_QMU_GET_CURRENT_XIT_ADDR(_q) ) + _idx)
+
+#define USBQ_XIT_GET_XFER_LEN(_q,_idx) USBQ_GET_XIT_PTR(_q,_idx) -> ul_xfer_length
+#define USBQ_XIT_GET_XFER_START_ADDR(_q,_idx) USBQ_GET_XIT_PTR(_q,_idx) -> p_ul_xfer_start_addr
+
+#define USB_UL_XIT_ENTRY_SIZE 512
+#define USB_UL_XIT_SIZE (USB_UL_XIT_ENTRY_SIZE*8)
+/****************************************************************************
+ * Structure of DL DRB
+ ****************************************************************************/
+typedef struct _usbq_dl_ph_drb usbq_dl_ph_drb;
+
+struct _usbq_dl_ph_drb
+{
+ kal_uint8 drb_flag;
+ kal_uint8 padding_length;
+ kal_uint16 dl_data_length;
+ kal_uint32 rh_data;
+};
+
+typedef struct _usbq_dl_pd_drb usbq_dl_pd_drb;
+
+struct _usbq_dl_pd_drb
+{
+ kal_uint8 drb_flag;
+ kal_uint8 padding_length;
+ kal_uint16 dl_data_length;
+ void *p_dl_data_addr;
+};
+
+typedef struct _usbq_dl_td_drb usbq_dl_td_drb;
+
+struct _usbq_dl_td_drb
+{
+ kal_uint8 drb_flag;
+ kal_uint8 reserved1;
+ kal_uint16 dl_xfer_length;
+ kal_uint32 reserved2;
+};
+
+typedef struct _usbq_dl_fh_drb usbq_dl_fh_drb;
+
+struct _usbq_dl_fh_drb
+{
+ kal_uint16 fh_index;
+ kal_uint16 dl_fh_length;
+ void *p_dl_fh_addr;
+};
+
+#define HIFUSBQ_QBM_BPS_BUF_SZ QBM_QUEUE_GET_MEM_SIZE(QBM_SIZE_TGPD_BPS, HIFUSBQ_QBM_BPS_NUM)
+
+#define USB_DL_DRB_REV_SIZE 1024
+#define USB_DL_DRB_SIZE 4096
+#define USB_DL_DRB_TOTAL_SIZE (USB_DL_DRB_SIZE + USB_DL_DRB_REV_SIZE)*8
+
+#define USB_DL_DRB_ENTRY_SIZE 4096
+#define USB_DL_DRB_MAX_COUNT 4096
+#define USB_DL_DLQ_FH_MAX_SIZE 256
+extern kal_uint8 hifusb_dlq_drb[USB_DL_DRB_TOTAL_SIZE];
+extern kal_uint8 hifusb_dlq_sw_drb[USB_DL_DRB_TOTAL_SIZE];
+
+#define HIFUSB_QMU_GET_START_PH_ADDR(_q) hifusbq_get_drb_start_address(_q)
+#define USBQ_GET_DRB_PH_PTR(_q,_idx) ((usbq_dl_ph_drb*)(HIFUSB_QMU_GET_START_PH_ADDR(_q))+(_idx))
+
+#define HIFUSB_QMU_GET_START_PD_ADDR(_q) hifusbq_get_drb_start_address(_q)
+#define USBQ_GET_DRB_PD_PTR(_q,_idx) ((usbq_dl_pd_drb*)(HIFUSB_QMU_GET_START_PD_ADDR(_q))+(_idx))
+
+#define HIFUSB_QMU_GET_START_TD_ADDR(_q) hifusbq_get_drb_start_address(_q)
+#define USBQ_GET_DRB_TD_PTR(_q,_idx) ((usbq_dl_td_drb*)(HIFUSB_QMU_GET_START_TD_ADDR(_q))+(_idx))
+
+#define HIFUSB_QMU_GET_RELEASE_TYPE_ADDR(_q) hifusbq_get_sw_drb_start_address(_q)
+#define USBQ_GET_DRB_REL_TYPE(_q,_idx) ((usbq_dl_pd_drb*)(HIFUSB_QMU_GET_RELEASE_TYPE_ADDR(_q))+(_idx))
+
+#define HIFUSB_QMU_GET_RELEASE_OFFSET_ADDR(_q) hifusbq_get_sw_drb_start_address(_q)
+#define USBQ_GET_DRB_REL_OFFSET(_q,_idx) ((usbq_dl_pd_drb*)(HIFUSB_QMU_GET_RELEASE_OFFSET_ADDR(_q))+(_idx))
+
+//DRB Flag
+#define DRB_FLAG_BIT_DTYP_MSK 0x03
+#define DRB_FLAG_DTYP_TH 0x00
+#define DRB_FLAG_DTYP_PL 0x01
+#define DRB_FLAG_DTYP_PH 0x02
+#define DRB_FLAG_BIT_AH 0x08
+
+#define DRB_FLAG_BIT_TYPE_MSK 0xFF
+
+#define DRB_FLAG_BIT_FHTYP_MSK 0x70
+#define DRB_FLAG_FHTYP_NONE 0x00
+#define DRB_FLAG_FHTYP_TYPE1 0x10
+#define DRB_FLAG_FHTYP_TYPE2 0x20
+#define DRB_FLAG_FHTYP_TYPE3 0x30
+#define DRB_FLAG_FHTYP_TYPE4 0x40
+#define DRB_FLAG_FHTYP_TYPE5 0x50
+#define DRB_FLAG_FHTYP_TYPE6 0x60
+#define DRB_FLAG_FHTYP_TYPE7 0x70
+
+#define DRB_FLAG_BIT_EOT 0x80
+
+#define DRB_FLAG_BIT_XTYP_MSK 0x70
+#define DRB_FLAG_XTYP_NONE 0x00
+#define DRB_FLAG_XTYP_RNDIS 0x10
+#define DRB_FLAG_XTYP_ECM 0x20
+#define DRB_FLAG_XTYP_MBIM 0x30
+#define DRB_FLAG_XTYP_NCM 0x40
+
+#define DRB_FLAG_BTYP_PRB 0x01
+#define DRB_FLAG_BTYP_VRB 0x02
+#define DRB_FLAG_BTYP_DPMAIF 0x03
+#define DRB_FLAG_BTYP_DPMAIF_FRAG 0x04
+
+//Packet header Descriptor part
+#define USBQ_DRB_PH_RESET(_q,_idx) \
+ kal_mem_set(USBQ_GET_DRB_PH_PTR(_q,_idx), 0, sizeof(usbq_dl_ph_drb))
+
+
+//Packet header Descriptor part
+#define USBQ_DRB_PH_SET_DTYP(_q,_idx,_v) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_DTYP_MSK); \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->drb_flag |= (_v))
+
+#define USBQ_DRB_PH_CLR_DTYP(_q,_idx) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_DTYP_MSK)
+
+#define USBQ_DRB_PH_GET_DTYP(_q,_idx) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->drb_flag & DRB_FLAG_BIT_DTYP_MSK)
+
+#define USBQ_DRB_PH_SET_AH(_q,_idx) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->drb_flag |= DRB_FLAG_BIT_AH)
+
+#define USBQ_DRB_PH_CLR_AH(_q,_idx) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_AH)
+
+#define USBQ_DRB_PH_GET_AH(_q,_idx) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->drb_flag & DRB_FLAG_BIT_AH)
+
+#define USBQ_DRB_PH_SET_FHTYP(_q,_idx,_v) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_FHTYP_MSK); \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->drb_flag |= ((_v)<<4))
+
+#define USBQ_DRB_PH_CLR_FHTYP(_q,_idx) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_FHTYP_MSK)
+
+#define USBQ_DRB_PH_GET_FHTYP(_q,_idx) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->drb_flag & DRB_FLAG_BIT_FHTYP_MSK)
+
+#define USBQ_DRB_PH_SET_EOT(_q,_idx) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->drb_flag |= DRB_FLAG_BIT_EOT)
+
+#define USBQ_DRB_PH_CLR_EOT(_q,_idx) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_EOT)
+
+#define USBQ_DRB_PH_GET_EOT(_q,_idx) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->drb_flag & DRB_FLAG_BIT_EOT)
+
+#define USBQ_DRB_PH_GET_PAD_LEN(_q,_idx) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->padding_length)
+
+#define USBQ_DRB_PH_SET_PAD_LEN(_q,_idx,_len) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->padding_length = (kal_uint8)(_len))
+
+#define USBQ_DRB_PH_GET_DATA_LEN(_q,_idx) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->dl_data_length)
+
+#define USBQ_DRB_PH_SET_DATA_LEN(_q,_idx,_len) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->dl_data_length = (kal_uint16)(_len))
+
+#define USBQ_DRB_PH_GET_RH_DATA(_q,_idx) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->rh_data)
+
+#define USBQ_DRB_PH_SET_RH_DATA(_q,_idx,_rh_data) \
+ (USBQ_GET_DRB_PH_PTR(_q,_idx)->rh_data = (kal_uint32)(_rh_data))
+
+
+//Payload Descriptor part
+#define USBQ_DRB_PD_RESET(_q,_idx) \
+ kal_mem_set(USBQ_GET_DRB_PD_PTR(_q,_idx), 0, sizeof(usbq_dl_pd_drb))
+
+
+//Payload Descriptor part
+#define USBQ_DRB_PD_SET_BTYP(_q,_idx,_v) \
+ (USBQ_GET_DRB_REL_TYPE(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_TYPE_MSK); \
+ (USBQ_GET_DRB_REL_TYPE(_q,_idx)->drb_flag |= (_v))
+
+#define USBQ_DRB_PD_CLR_BTYP(_q,_idx) \
+ (USBQ_GET_DRB_REL_TYPE(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_TYPE_MSK)
+
+#define USBQ_DRB_PD_GET_BTYP(_q,_idx) \
+ (USBQ_GET_DRB_REL_TYPE(_q,_idx)->drb_flag & DRB_FLAG_BIT_TYPE_MSK)
+
+#define USBQ_DRB_PD_SET_OFFSET(_q,_idx,_offset) \
+ (USBQ_GET_DRB_REL_OFFSET(_q,_idx)->padding_length = (_offset))
+
+#define USBQ_DRB_PD_GET_OFFSET(_q,_idx) \
+ (USBQ_GET_DRB_REL_OFFSET(_q,_idx)->padding_length)
+
+#define USBQ_DRB_PD_SET_DTYP(_q,_idx,_v) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_DTYP_MSK); \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->drb_flag |= (_v))
+
+#define USBQ_DRB_PD_CLR_DTYP(_q,_idx) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_DTYP_MSK)
+
+#define USBQ_DRB_PD_GET_DTYP(_q,_idx) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->drb_flag & DRB_FLAG_BIT_DTYP_MSK)
+
+#define USBQ_DRB_PD_SET_AH(_q,_idx) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->drb_flag |= DRB_FLAG_BIT_AH)
+
+#define USBQ_DRB_PD_CLR_AH(_q,_idx) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_AH)
+
+#define USBQ_DRB_PD_GET_AH(_q,_idx) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->drb_flag & DRB_FLAG_BIT_AH)
+
+#define USBQ_DRB_PD_SET_FHTYP(_q,_idx,_v) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_FHTYP_MSK); \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->drb_flag |= ((_v)<<4))
+
+#define USBQ_DRB_PD_CLR_FHTYP(_q,_idx) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_FHTYP_MSK)
+
+#define USBQ_DRB_PD_GET_FHTYP(_q,_idx) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->drb_flag & DRB_FLAG_BIT_FHTYP_MSK)
+
+#define USBQ_DRB_PD_SET_EOT(_q,_idx) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->drb_flag |= DRB_FLAG_BIT_EOT)
+
+#define USBQ_DRB_PD_CLR_EOT(_q,_idx) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_EOT)
+
+#define USBQ_DRB_PD_GET_EOT(_q,_idx) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->drb_flag & DRB_FLAG_BIT_EOT)
+
+#define USBQ_DRB_PD_GET_PAD_LEN(_q,_idx) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->padding_length)
+
+#define USBQ_DRB_PD_SET_PAD_LEN(_q,_idx,_len) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->padding_length = (kal_uint8)(_len))
+
+#define USBQ_DRB_PD_GET_DATA_LEN(_q,_idx) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->dl_data_length)
+
+#define USBQ_DRB_PD_SET_DATA_LEN(_q,_idx,_len) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->dl_data_length = (kal_uint16)(_len))
+
+#define USBQ_DRB_PD_GET_DATA_ADDR(_q,_idx) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->p_dl_data_addr)
+
+#define USBQ_DRB_PD_SET_DATA_ADDR(_q,_idx,_dp) \
+ (USBQ_GET_DRB_PD_PTR(_q,_idx)->p_dl_data_addr = (kal_uint32*)(_dp))
+
+//Transfer Header Descriptor part
+#define USBQ_DRB_TD_SET_DTYP(_q,_idx,_v) \
+ (USBQ_GET_DRB_TD_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_DTYP_MSK); \
+ (USBQ_GET_DRB_TD_PTR(_q,_idx)->drb_flag |= (_v))
+
+#define USBQ_DRB_TD_CLR_DTYP(_q,_idx) \
+ (USBQ_GET_DRB_TD_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_DTYP_MSK)
+
+#define USBQ_DRB_TD_GET_DTYP(_q,_idx) \
+ (USBQ_GET_DRB_TD_PTR(_q,_idx)->drb_flag & DRB_FLAG_BIT_DTYP_MSK)
+
+#define USBQ_DRB_TD_SET_AH(_q,_idx) \
+ (USBQ_GET_DRB_TD_PTR(_q,_idx)->drb_flag |= DRB_FLAG_BIT_AH)
+
+#define USBQ_DRB_TD_CLR_AH(_q,_idx) \
+ (USBQ_GET_DRB_TD_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_AH)
+
+#define USBQ_DRB_TD_GET_AH(_q,_idx) \
+ (USBQ_GET_DRB_TD_PTR(_q,_idx)->drb_flag & DRB_FLAG_BIT_AH)
+
+#define USBQ_DRB_TD_SET_XTYP(_q,_idx,_v) \
+ (USBQ_GET_DRB_TD_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_XTYP_MSK); \
+ (USBQ_GET_DRB_TD_PTR(_q,_idx)->drb_flag |= ((_v)<<4))
+
+#define USBQ_DRB_TD_CLR_XTYP(_q,_idx) \
+ (USBQ_GET_DRB_TD_PTR(_q,_idx)->drb_flag &=~ DRB_FLAG_BIT_XTYP_MSK)
+
+#define USBQ_DRB_TD_GET_XTYP(_q,_idx) \
+ (USBQ_GET_DRB_TD_PTR(_q,_idx)->drb_flag & DRB_FLAG_BIT_XTYP_MSK)
+
+#define USBQ_DRB_TD_GET_XFER_LEN(_q,_idx) \
+ (USBQ_GET_DRB_TD_PTR(_q,_idx)->dl_xfer_length)
+
+#define USBQ_DRB_TD_SET_XFER_LEN(_q,_idx,_len) \
+ (USBQ_GET_DRB_TD_PTR(_q,_idx)->dl_xfer_length = (kal_uint16)(_len))
+
+//Transfer Header Descriptor part
+#define USBQ_DRB_TD_RESET(_q,_idx) \
+ kal_mem_set(USBQ_GET_DRB_TD_PTR(_q,_idx), 0, sizeof(usbq_dl_td_drb))
+
+
+/*!
+ * @brief the queue configuration bit-map
+ * @param HIF_QCFG_BM_TX_EMPTY_ENQ , set one and the set_gpd flow would follow non-bps enq flow
+ */
+#define HIF_QCFG_BM_TX_EMPTY_ENQ (0x1 << 0)
+
+typedef enum
+{
+ USB_HEADER_RULE_RNDIS = 0,
+ USB_HEADER_RULE_MBIM,
+} usb_header_rule_enum;
+
+typedef struct
+{
+ void *ph_start_ptr;
+ void *xh_start_ptr;
+ kal_uint16 ph_size;
+ kal_uint16 xh_size;
+} usb_header_rule_data_t;
+
+
+
+/*!
+ * @brief ask hif driver to set GPD buffer into QMU
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return KAL_TRUE : set gpd success,
+ KAL_FALSE : set gpd fail and upper module should re-submit or free the queue list
+ */
+kal_bool hif_set_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, qbm_gpd* first_gpd, qbm_gpd* last_gpd);
+
+
+/*!
+ * @brief ask hif driver to flush all GPD buffer from QMU
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param flush type the flush type wished
+ * @param pp_head the head pointer of flush list
+ * @param pp_tail the tail pointer of flush list
+ * @return return total flushed gpd number
+ */
+kal_uint32 hif_flush_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, hif_flush_type_e flush_type , void **pp_head, void **pp_tail);
+
+
+/*!
+ * @brief poll specified QMU queue to see if any GPD complete
+ * deq_type == HIFQ_FREEQ, (use qbmt_free_q_hwo())
+ * would free the used queue after this function and return the deq number
+ * deq_type == HIF_DEQ,
+ * would just deq and return the deq list and the deq number
+ * use use qbmt_de_q() if generic buffer type
+ * use deqmt_deq_hif_ul_type1() if QBM_TYPE_HIF_UL_TYPE1
+ * use deqmt_deq_hif_ul_type2() if QBM_TYPE_HIF_UL_TYPE2
+ * @param deq_info the que number , que type and deq type
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return return the deq number
+ */
+kal_uint32 hif_poll_queue(hif_deq_info_t deq_info, void **first_gpd, void **last_gpd);
+
+/*!
+ * @brief initial hif_common.c private structure and variable
+ * @return return KAL_TRUE if success , KAL_FALSE if failure
+ */
+kal_bool hif_common_qmu_init(void);
+
+/*!
+ * @brief get currently que list
+ * @param is_tx, KAL_TRUE for txq , KAL_FALSE for rxq
+ * @param q_no , the queue number form 0~n
+ * @param pp_head , return the currently queue head
+ * @param pp_tail , return the currently queue tail
+ */
+void hif_get_que_list(kal_bool is_tx , kal_uint8 q_no, void **pp_head, void **pp_tail);
+
+/*!
+ * @brief configure specific queue operation option with bit-map config
+ * @param is_tx, KAL_TRUE for txq , KAL_FALSE for rxq
+ * @param q_no , the queue number form 0~n
+ * @param que_cfg , the bit-map configuration , ex. HIF_QCFG_BM_TX_EMPTY_ENQ
+ * @return KAL_TRUE if success, KAL_FALSE if configure not valid
+ */
+kal_bool hif_set_que_cfg(kal_bool is_tx , kal_uint8 q_no, kal_uint16 que_cfg);
+
+#endif
diff --git a/mcu/interface/driver/hif/hif_common_except.h b/mcu/interface/driver/hif/hif_common_except.h
new file mode 100644
index 0000000..5386b61
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_common_except.h
@@ -0,0 +1,132 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hif_common_except.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * This is the HIF data path exception handler driver head file for both USB2.0/USB3.0.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 02 04 2013 ming.hsieh
+ * [MOLY00006951] MT7208 U2/U3 driver and test driver maintain
+ * .modify project name as MT6290 and change all comment or log for new model name
+ *
+ * 01 15 2013 ming.hsieh
+ * [MOLY00006951] MT6290 U2/U3 driver and test driver maintain
+ * .separate USB/SDIO/CLDMA from hif_common.c for multi-hif request
+ * -- USB (ming.hsieh)
+ * -- SDIO (Wei-De/mick.lin)
+ * -- CLDMA (TH.Cheng)
+ * .resolve SDIO BPS TX/RX test case fail issue
+ ****************************************************************************/
+
+#ifndef __HIF_COMMON_EXCEPT_H__
+#define __HIF_COMMON_EXCEPT_H__
+
+#include "hif_common.h"
+
+/*!
+ * @brief initial the exception HIF driver, only support empty enqueue flow in exception
+*/
+kal_bool hif_except_initial(void);
+/*!
+ * @brief ask hif driver to flush all GPD buffer from QMU
+ * this API only used to stop exception mode to go back normal mode
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param flush type the flush type wished
+ * @param pp_head the head pointer of flush list
+ * @param pp_tail the tail pointer of flush list
+ * @return return total flushed gpd number
+ */
+kal_uint32 hif_except_flush_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, hif_flush_type_e flush_type , void **pp_head, void **pp_tail);
+/*!
+ * @brief stop the queue and flush USB pipe fifo for following debug log
+ * HIF layer don't care remain GPD and upper layer could parsing their resource
+ * to handle remain data re-send flow (DHL would re-send remain data after using this API)
+ * @param q_type , define the queue tx/rx direction
+ * @param q_num , define the channel which using the queue number
+*/
+void hif_except_clear_q(hif_queue_type_e q_type, kal_uint8 q_num);
+/*!
+ * @brief ask hif driver to set GPD buffer into QMU
+ * don't handle critical section protection becuase in the single thread exception handler
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return KAL_TRUE : set gpd success,
+ KAL_FALSE : set gpd fail and upper module should re-submit or free the queue list
+ */
+kal_bool hif_except_set_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, qbm_gpd* first_gpd, qbm_gpd* last_gpd);
+/*!
+ * @brief poll specified QMU queue to see if any GPD complete
+ * deq_type == HIFQ_FREEQ, (use qbmt_free_q_hwo())
+ * would free the used queue after this function and return the deq number
+ * deq_type == HIF_DEQ,
+ * would just deq and return the deq list and the deq number
+ * use use qbmt_de_q() if generic buffer type
+ * use deqmt_deq_hif_ul_type1() if QBM_TYPE_HIF_UL_TYPE1
+ * use deqmt_deq_hif_ul_type2() if QBM_TYPE_HIF_UL_TYPE2
+ * @param deq_info the que number , que type and deq type
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return return the deq number
+ */
+kal_uint32 hif_except_poll_queue(hif_deq_info_t deq_info, void **pp_first_gpd, void **pp_last_gpd);
+
+/*!
+ * @brief hif driver would count the timeout for TX queue not progressing
+ * upper driver should check this the status when they found channel abnormal
+ * @param q_num, the tx queue number to check status
+ * @return Return the hif driver counter of txq stall time in millisecond (ms)
+*/
+kal_uint32 hif_except_get_txq_timeout(kal_uint8 q_num);
+
+#endif
diff --git a/mcu/interface/driver/hif/hif_cscdev/cscd_if.h b/mcu/interface/driver/hif/hif_cscdev/cscd_if.h
new file mode 100644
index 0000000..12516fc
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_cscdev/cscd_if.h
@@ -0,0 +1,71 @@
+/*****************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2012
+ *
+ * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ *****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * cscd_if.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ *
+ ****************************************************************************/
+#ifndef _CSCD_IF_H_
+#define _CSCD_IF_H_
+
+#include "kal_public_api.h"
+#include <winsock2.h>
+
+SOCKET *cscd_create_socket(kal_int32 port, char *ip);
+void cscd_close_socket(SOCKET *skt);
+kal_uint32 cscd_write_data(SOCKET *connection, char *buffer, kal_int32 len_send, kal_int32 timeout_ms);
+kal_uint32 cscd_read_data(SOCKET *connection, char *buffer, kal_int32 len_buf, kal_int32 timeout_ms);
+
+void cscd_dev_utmain(void);
+
+#endif // _CSCD_IF_H_
diff --git a/mcu/interface/driver/hif/hif_dpmaifdev/hif_dpmaifdev.h b/mcu/interface/driver/hif/hif_dpmaifdev/hif_dpmaifdev.h
new file mode 100644
index 0000000..1284e3f
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_dpmaifdev/hif_dpmaifdev.h
@@ -0,0 +1,480 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hif_dpmaifdev.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * driver header of DPMAIF device IP
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 12 18 2020 hsin-hao.huang
+ * [MOLY00609969] [Colgin] UL Traffic Shaping (UL TRAS) for PCIe
+ *
+ * EWSP0000194974 MD700 TRAS UL interface
+ *
+ * 12 01 2020 hsin-hao.huang
+ * [MOLY00595474] [MD700] DPMAIF/LHIF T700 code merge
+ * .MD700 merge back interface from T700
+ *
+ * 11 16 2020 hsin-hao.huang
+ * [MOLY00595474] [MD700] DPMAIF/LHIF T700 code merge
+ * .MD700 interface merge
+ *
+ * 09 21 2020 hsin-hao.huang
+ * [MOLY00570294] [block][MT6880][Colgin][M.2][MP6][SQC][Internal][FT][China][Shanghai][Self-Cer][5GMM][SA][Data Card Self-Cer][Data card_Self-Cer_FT_08_007][IS:CMCC]Assert fail: Line 935 Code 0xe00 0x100 0x0 Filename: coresonic/msonic/modem/brp/nr/nr_brp/src/nr_br
+ * .T700 infra power down interface issue
+ *
+ * 09 11 2020 hsin-hao.huang
+ * [MOLY00569123] [MT6880][Colgin][MP6][SQC][MTBF][SH][PCIE][MiTA][1][core0,vpe1,tc2(vpe1)] Assert fail: mml2_hisr_97arch.c 192 - (LISR)NRL2 EXCEP
+ * .T700 interface for PCIE lowpower
+ *
+ * 08 06 2020 hsin-hao.huang
+ * [MOLY00541625] [Colgin][SB] DPMAIF code merge
+ * colgin code merge
+ *
+ * 08 04 2020 hsin-hao.huang
+ * [MOLY00541625] [Colgin][SB] DPMAIF code merge
+ * DL issue interface
+ *
+ * 07 20 2020 hsin-hao.huang
+ * [MOLY00541625] [Colgin][SB] DPMAIF code merge
+ * .UL queue hang interface
+ *
+ * 07 07 2020 hsin-hao.huang
+ * [MOLY00541625] [Colgin][SB] DPMAIF code merge
+ * PCIE support interface porting
+ *
+ * 07 06 2020 hsin-hao.huang
+ * [MOLY00541625] [Colgin][SB] DPMAIF code merge
+ * interface porting
+ *
+ * 07 06 2020 hsin-hao.huang
+ * [MOLY00541625] [Colgin][SB] DPMAIF code merge
+ * .DPMAIF porting interface
+ *
+ * 05 21 2020 grass.chang
+ * [MOLY00521430] [Colgin] DPMAIF SW merge from mercury
+ * .
+ * [Colgin SB][DEV]porting
+ *
+ * 03 03 2020 hsin-hao.huang
+ * [MOLY00502966] [MT6873][Margaux][Q0][MP2][SQC][HQ][MTBF][Lab][Ericsson][ErrorTimes:1]md1:(MSONIC0) [ASSERT] file:dsp3/coresonic/msonic/modem/common/nr/nr_schd/src/nr_schd_mc_lisr_entry.c line:1024
+ * .DPMAIF queue hang workaround interface
+ *
+ * 02 25 2020 hsin-hao.huang
+ * [MOLY00501471] [HCR][Top Issue][MT6873][Margaux][Q0][MP2][SQC][HQ][MTBF][Lab][Ericsson][ErrorTimes:4]md1:(MSONIC0) [ASSERT] file:dsp3/coresonic/msonic/modem/common/nr/nr_schd/src/nr_schd_mc_lisr_entry.c line:1024
+ * .VMOLY dpmaif reorder enhance interface
+ *
+ * 02 19 2020 hsin-hao.huang
+ * [MOLY00500501] [Blocking][CMCC MTBF][MT6873][Margaux][Q0][ASSERT] file:dsp3/coresonic/msonic/modem/common/nr/nr_schd/src/nr_schd_mc_lisr_entry.c line:1024
+ * .DPMAIF dummy reorder interface
+ *
+ * 02 10 2020 hsin-hao.huang
+ * [MOLY00498768] [MT6873][Margaux][Q0][MP3][SQC][VDF][FT][UK][London][NSA][MDST][SWIFT]Assert fail: Line 1024 Code 0x0 0x0 0x0
+ * .DPMAIF vcore/clk ehance interface
+ *
+ * 01 16 2020 hsin-hao.huang
+ * [MOLY00474941] [MT6885][Petrus][MP1][IODT][EIOT][Taiwan][NSA][5G][B2+N41_NR.MB.2.12.1.85][1][core0,vpe0,tc0(vpe0)] Assert fail: errc_chm_main.c 9724 0x0 0x1 0x0 - ERRC
+ * .DPMAIF LHIF reorder ehance interface
+ *
+ * 12 04 2019 hsin-hao.huang
+ * [MOLY00458388] add data path exception path by LHIF API
+ * .DPMAIF restore issue interface
+ *
+ * 10 24 2019 hsin-hao.huang
+ * [MOLY00454554] [MT6885][Petrus][SQC][MP1][HQ][MTBF][Lab][NSA][Ericsson][ErrorTimes:1]md1:(MCU_core0.vpe0.tc0(VPE0)) [ASSERT] file:mcu/driver/dpcopro/src/dpcopro_common.c line:724
+ * LHIF enable disabe issue interface
+ *
+ * 09 11 2019 hsin-hao.huang
+ * [MOLY00439255] [Need Patch](LTE domain) VMOLY.MERCURY.19Q2.DEV build error for MERCURY_FPGA(NLWCTG_MODEM)
+ * Mercury warning porting
+ *
+ * 07 23 2019 hsin-hao.huang
+ * [MOLY00424123] [MT6297][Apollo][Sanity Fail][VMOLY][20190722][Hangzhou FT Sanity]Index：2094078，Modem warning:[1][MOD_ENPDCP]npdcp_dl_pit_handler.c #249;
+ * .add addr info fo PDCP interface
+ *
+ * 03 26 2019 hsin-hao.huang
+ * [MOLY00393777] [MT6297][Phone Call][NSA FullStack][Huawei][Shanghai][5G][VMOLY][1][core2,vpe0,tc0(vpe6)] Assert fail: nrlcdl_data.c 1697 - NL2DL
+ * .IPF full and mtu 9k issue interface
+ *
+ * 03 14 2019 hsin-hao.huang
+ * [MOLY00390308] [MT6297][Apollo][EVB][PS Performance][NSA][NSIOT] Assert fail: nrlcdl_data.c 1633 - NL2DL when HW path was tested
+ * .DPMAIF/LHIF 5G reorder tput interface enhance
+ *
+ * 01 10 2019 hsin-hao.huang
+ * [MOLY00374594] [Gen97][5G reorder] L2SW / IPCORE / IPFCORE / LHIF driver integration patch
+ * .5G reorder IT interface test
+ *
+ * 08 20 2018 hsin-hao.huang
+ * [MOLY00346950] [VMOLY] Gen97 porting to VMOLY
+ * .DPMAIF driver porting
+ *
+ * 08 17 2018 hsin-hao.huang
+ * [MOLY00328631] [6297][DPMAIF] Gen97 driver and driver test porting
+ * .97 driver porting
+ *
+ * 09 04 2017 hsin-hao.huang
+ * [MOLY00266261] [MT6295][DEV][DPMAIF] Add DPMAIF MD driver
+ * 95 LHIF/DPMAIF
+ *
+ *
+ ****************************************************************************/
+
+#ifndef __HIF_DPMAIFDEV_H__
+#define __HIF_DPMAIFDEV_H__
+
+
+#if defined(__MTK_TARGET__)
+#if defined(__HIF_PCIE_SUPPORT__)
+#define __HIF_DPMAIF_PCIE_SUPPORT__
+#endif
+#endif
+
+typedef kal_bool (*dpmaif_isr_callback_t)(void);
+
+void hifdpmaif_init(dpmaif_isr_callback_t callback);
+void hifdpmaif_unmask_irq_and_clear(void);
+
+#if defined(__MD97__) || defined(__MD98__)
+/*97 reorder DLQ0/DLQ1 issue*/
+#define DP_TEST_DUMMY_RB 20
+#define DP_TEST_DUMMY_RESERVED_PIT 1024
+#define DP_TEST_DUMMY_THRED_PIT 100
+#define DP_TEST_DUMMY_MAX_AP_PIT 0x3fffff
+
+#define DP_TEST_DUMMY_A_IDX 15
+#define DP_TEST_DUMMY_B_IDX 15
+#define DP_TEST_DUMMY_RELOAD_IDX 47
+
+#define DP_TEST_DUMMY_INIT_WIDX 49
+
+#define DP_TP_PKT_BASE_ENTRY 32
+#define DP_TP_PKT_PIT_ENTRY 2 //M+P
+#define DP_TP_PKT_BYTE_SIZE DP_TP_PKT_PIT_ENTRY*16
+#define DP_TP_BM_BYTE_SIZE 1
+
+typedef enum {
+ DP_TPSIZE_CFG_NONE=0,
+ DP_TPSIZE_CFG_32=1, // 32B(PIT SZ(M+P))*32(PKT num) = 1024 bytes
+ DP_TPSIZE_CFG_64=2,
+ DP_TPSIZE_CFG_128=4,
+ DP_TPSIZE_CFG_256=8,
+ DP_TPSIZE_CFG_512=16,
+ DP_TPSIZE_CFG_640=20, // 32B(PIT SZ(M+P))*(32*20)(PKT num) = 20,480 bytes
+ DP_TPSIZE_CFG_768=24,
+ DP_TPSIZE_CFG_1024=32, // 32B(PIT SZ(M+P))*(32*32)(PKT num) = 32,768 bytes
+ DP_TPSIZE_CFG_2048=64, // 32B(PIT SZ(M+P))*(32*64)(PKT num) = 65,536 bytes
+ DP_TPSIZE_CFG_4K=128, // 32B(PIT SZ(M+P))*(32*128)(PKT num) = 131,072 bytes
+ DP_TPSIZE_CFG_8K=256, // 32B(PIT SZ(M+P))*(32*256)(PKT num) = 262,144 bytes
+ DP_TPSIZE_CFG_16K=512, // 32B(PIT SZ(M+P))*(32*512)(PKT num) = 524,288 bytes
+ DP_TPSIZE_CFG_NUM,
+}DP_TPSIZE_CFG;
+
+void dpmaif_drv_reorder_mml2_cfg_en(kal_uint16 rb_idx, DP_TPSIZE_CFG rb_32_entry);
+void dpmaif_drv_reorder_mml2_cfg_dis(kal_uint16 rb_idx);
+void dpmaif_drv_dl_rb_get_rw(kal_uint8 rb_id, kal_uint32*rd_idx, kal_uint32*wr_idx);
+kal_uint32 dpmaif_drv_dl_rb_get_remain(kal_uint32 rb_id);
+void dpmaif_drv_force_dl_en(kal_bool enable);
+
+kal_uint32 dpmaif_drv_ap_dl_pit_info(kal_uint32*entry_num, kal_uint32*rd_idx, kal_uint32*wr_idx);
+kal_uint32 dpmaif_drv_ap_dl_bat_info(kal_uint32*entry_num, kal_uint32*rd_idx, kal_uint32*wr_idx);
+kal_uint32 dpmaif_drv_ap_dl_frg_info(kal_uint32*entry_num, kal_uint32*rd_idx, kal_uint32*wr_idx);
+
+void* drv_dp_dl_rb_base(kal_uint8 rb_id);
+kal_uint32 drv_dp_dl_rb_sw_size(kal_uint8 rb_id);
+
+kal_bool dpmaif_drv_restore_hw(void);
+kal_bool dpamif_drv_set_wdma_ultra(kal_bool _en);
+kal_bool dpamif_drv_check_wdma_ultra(void);
+kal_bool dpamif_drv_set_ck_vc(kal_bool _en, kal_uint32* vcore_sts);
+kal_bool dpamif_drv_get_wdma_idle(void);
+kal_bool dpamif_drv_get_dl_hw_idle(void);
+
+
+kal_bool dpmaif_drv_check_dummy_pit_entry(kal_uint32*ap_entry_num,kal_uint32*md_entry_num,kal_uint32*md_chk_num);
+kal_bool dpmaif_drv_check_ap_reload_en(void);
+
+void dpmaif_drv_set_dl_idle(kal_bool set_en);
+void dpmaif_drv_en_ul_arb(kal_bool _en);
+kal_bool dpmaif_drv_chk_ul_wordcnt_idle(void);
+kal_bool dpmaif_drv_chk_rb_idx(kal_uint8 rb_id, kal_uint32 chk_idx,kal_uint32 pre_rd, kal_uint32 pre_wr);
+
+kal_bool dpmaif_drv_get_ulq_arb_sts(void);
+void dpmaif_drv_en_ulq_swarb(kal_bool _en, kal_uint16 q_id);
+kal_uint16 dpmaif_drv_get_ulq_size(kal_uint16 q_id);
+void dpmaif_drv_en_ulq_arb(kal_bool _en, kal_uint16 q_id);
+kal_uint16 dpmaif_drv_get_ulq_hw_size(kal_uint16 q_id);
+kal_uint16 dpmaif_drv_get_ulq_rdidx(kal_uint16 q_id);
+kal_uint16 dpmaif_drv_get_ulq_wridx(kal_uint16 q_id);
+kal_uint16 dpmaif_drv_get_ulq_wordcnt(kal_uint16 q_id);
+
+#if defined(__MD98__)
+void* drv_dp_dl_hp_base(kal_uint8 hp_id);
+kal_uint32 drv_dp_dl_hp_sw_size(kal_uint8 hp_id);
+#endif
+
+kal_bool dpmmaif_drv_check_pcie_mode(void);
+
+#if !defined(PETRUS)
+typedef struct dpmaif_md_normal_pit_t {
+
+ kal_uint32 packet_type:1;
+ kal_uint32 c_bit:1;
+ kal_uint32 buffer_type:1;
+ kal_uint32 buffer_id:13;
+ kal_uint32 data_len:16;
+
+ void *p_data_addr;
+
+ kal_uint32 data_addr_ext:8;
+ kal_uint32 reserved:24;
+
+ kal_uint32 pit_seq:16;
+ kal_uint32 ig:1;
+ kal_uint32 reserved2:7;
+ kal_uint32 ulq_done:6;
+ kal_uint32 dlq_done:2;
+
+}dpmaif_md_normal_pit;
+#else
+typedef struct dpmaif_md_normal_pit_t {
+
+ kal_uint32 packet_type:1;
+ kal_uint32 c_bit:1;
+ kal_uint32 buffer_type:1;
+ kal_uint32 buffer_id:13;
+ kal_uint32 data_len:16;
+
+ void *p_data_addr;
+
+ kal_uint32 data_addr_ext:8;
+ kal_uint32 reserved:24;
+
+ kal_uint32 pit_seq:16;
+ kal_uint32 ig:1;
+ kal_uint32 bi_f:2;
+ kal_uint32 reserved2:5;
+ kal_uint32 ulq_done:6;
+ kal_uint32 dlq_done:2;
+
+}dpmaif_md_normal_pit;
+#endif /*_DPMAIF_GEN97_MT6885_HW_*/
+
+#if !defined(PETRUS)
+typedef struct dpmaif_md_msg_pit_t {
+
+ kal_uint32 packet_type:1;
+ kal_uint32 c_bit:1;
+ kal_uint32 check_sum:2;
+ kal_uint32 error_bit:1;
+ kal_uint32 src_qid:3;
+ kal_uint32 reserved:8;
+ kal_uint32 channel_id:8;
+ kal_uint32 network_type:3;
+ kal_uint32 reserved2:4;
+ kal_uint32 dp:1;
+
+ kal_uint32 count_l:16;
+ kal_uint32 flow:5;
+ kal_uint32 reserved3:3;
+ kal_uint32 cmd:3;
+ kal_uint32 reserved4:5;
+
+ kal_uint32 reserved5:3;
+ kal_uint32 vbid:13;
+ kal_uint32 reserved6:16;
+
+ kal_uint32 pit_seq:16;
+ kal_uint32 ig:1;
+ kal_uint32 reserved7:7;
+ kal_uint32 ulq_done:6;
+ kal_uint32 dlq_done:2;
+
+}dpmaif_md_msg_pit;
+#else
+typedef struct dpmaif_md_msg_pit_t {
+
+ kal_uint32 packet_type:1;
+ kal_uint32 c_bit:1;
+ kal_uint32 check_sum:2;
+ kal_uint32 error_bit:1;
+ kal_uint32 src_qid:3;
+ kal_uint32 reserved:8;
+ kal_uint32 channel_id:8;
+ kal_uint32 network_type:3;
+ kal_uint32 reserved2:4;
+ kal_uint32 dp:1;
+
+ kal_uint32 count_l:16;
+ kal_uint32 flow:5;
+ kal_uint32 reserved3:3;
+ kal_uint32 cmd:3;
+ kal_uint32 reserved4:5;
+
+ kal_uint32 reserved5:3;
+ kal_uint32 vbid:13;
+ kal_uint32 pro:2;
+ kal_uint32 reserved6:14;
+
+ kal_uint32 pit_seq:16;
+ kal_uint32 ig:1;
+ kal_uint32 reserved7:7;
+ kal_uint32 ulq_done:6;
+ kal_uint32 dlq_done:2;
+
+}dpmaif_md_msg_pit;
+#endif
+
+#define DP_NOL_PIT_PTR(_ptr, _p) ((dpmaif_md_normal_pit*)(_ptr) + _p)
+#define DP_MSG_PIT_PTR(_ptr, _p) ((dpmaif_md_msg_pit*)(_ptr) + _p)
+
+#endif /*__MD97__*/
+
+#if defined(__MD95__)
+kal_bool hifdpmaif_mdint_clr_and_sts(void);
+void hifdpmaif_ul_arb_en(kal_bool en);
+kal_uint32 hifdpmaif_mdint_sts(void);
+kal_uint32 hifdpmaif_debug_rg_sts(void);
+#endif
+
+#if defined(__HIF_DPMAIF_PCIE_SUPPORT__)
+/*
+ Non POST USER will hanlde suspend/resume event in callback
+ and do ack to DPMAIF driver
+*/
+typedef enum {
+ DPMAIF_PCIE_NPU_IPCORE=0,
+ DPMAIF_PCIE_NPU_END,
+}DPMAIF_PCIE_NOPOST_USER;
+
+/*
+ POST USER will hanlde suspend/resume event in callback
+ and dont ack to DPMAIF driver
+*/
+typedef enum {
+ DPMAIF_PCIE_PU_LHIFDRV=0,
+ DPMAIF_PCIE_PU_END,
+}DPMAIF_PCIE_POST_USER;
+
+/*
+ POST USER will hanlde suspend/resume event in callback
+ and dont ack to DPMAIF driver
+*/
+typedef enum {
+ DPMAIF_PCIE_DONE_LHIFDRV=0,
+ DPMAIF_PCIE_DONE_END,
+}DPMAIF_PCIE_DONE_USER;
+
+/*
+ WAKE DPMAIF/PCIE USER
+*/
+typedef enum {
+ DPMAIF_PCIE_WAKE_LHIFDRV=0,
+ DPMAIF_PCIE_WAKE_END,
+}DPMAIF_PCIE_WAKE_USER;
+
+typedef int (*hifdpmaif_suspend_callback)(void *param, void *user_param);
+typedef int (*hifdpmaif_resume_callback)(void *param, void *user_param);
+
+/*!
+ * @brief suspend call back form PCIE and user non post handle. SW need ack by hifdpmaif_suspend_user_ack
+ * @param
+ * @return
+ */
+kal_bool hifdpmaif_register_suspend_non_post_callback(DPMAIF_PCIE_NOPOST_USER user, hifdpmaif_suspend_callback callback, void *param);
+
+/*!
+ * @brief suspend call back form PCIE and user post handle. SW donnt need ack
+ * @param
+ * @return
+ */
+kal_bool hifdpmaif_register_suspend_post_callback(DPMAIF_PCIE_POST_USER user, hifdpmaif_suspend_callback callback, void *param);
+
+/*!
+ * @brief resume call back form PCIE and user non post handle. SW need ack by hifdpmaif_suspend_user_ack
+ * @param
+ * @return
+ */
+kal_bool hifdpmaif_register_resume_non_post_callback(DPMAIF_PCIE_NOPOST_USER user, hifdpmaif_resume_callback callback, void *param);
+
+/*!
+ * @brief resume call back form PCIE and user post handle. SW donnt need ack
+ * @param
+ * @return
+ */
+kal_bool hifdpmaif_register_resume_post_callback(DPMAIF_PCIE_POST_USER user, hifdpmaif_resume_callback callback, void *param);
+
+/*!
+ * @brief SW need ack when non post suspend callback
+ * @param
+ * @return
+ */
+void hifdpmaif_suspend_user_ack(DPMAIF_PCIE_NOPOST_USER user);
+
+/*!
+ * @brief SW need ack when non post resume callback
+ * @param
+ * @return
+ */
+void hifdpmaif_resume_user_ack(DPMAIF_PCIE_NOPOST_USER user);
+
+/*!
+ * @brief Trigger PCIE remote wake
+ * @param
+ * @return
+ */
+void hifdpmaif_remote_wake(DPMAIF_PCIE_WAKE_USER user);
+
+kal_bool hifdpmaif_register_suspend_done_callback(DPMAIF_PCIE_DONE_USER user, hifdpmaif_suspend_callback callback, void *param);
+
+kal_bool hifdpmaif_register_resume_done_callback(DPMAIF_PCIE_DONE_USER user, hifdpmaif_resume_callback callback, void *param);
+
+#endif /*__HIF_DPMAIF_PCIE_SUPPORT__*/
+
+#endif /*__HIF_DPMAIFDEV_H__*/
diff --git a/mcu/interface/driver/hif/hif_dpmaifdev/hif_dpmaifdrv_dp.h b/mcu/interface/driver/hif/hif_dpmaifdev/hif_dpmaifdrv_dp.h
new file mode 100644
index 0000000..f0a9755
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_dpmaifdev/hif_dpmaifdrv_dp.h
@@ -0,0 +1,96 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hif_dpmaifdrv_dp.h
+ *
+ * Project:
+ * --------
+ * Gen97
+ *
+ * Description:
+ * ------------
+ * Interface of DPMAIF DL Data Path driver
+ *
+ * Author:
+ * -------
+ *
+ *
+ * ==========================================================================
+
+ ****************************************************************************/
+
+#ifndef __HIF_DPMAIFDRV_DP_H__
+#define __HIF_DPMAIFDRV_DP_H__
+
+#include "kal_general_types.h"
+
+#define DPMAIF_BUF_TYPE_BAT (1)
+#define DPMAIF_BUF_TYPE_FRAGBAT (2)
+
+
+/******************************************************************************
+ * FUNCTION
+ * dpmaif_buf_release
+ * DESCRIPTION
+ * Release the buffer that allocated by prbm_allocate().
+ * PARAMETERS
+ * addr : [IN] memory address that to be release.
+ * type : [IN] indicate it is BAT or FRAGBAT.
+ * RETURN VALUES
+ * KAL_TRUE : Indicate buffer release successfully.
+ * KAL_FALSE : Indicate buffer release unsuccessfully.
+******************************************************************************/
+kal_bool dpmaif_buf_release(void* addr, kal_uint8 type);
+
+
+
+/******************************************************************************
+ * FUNCTION
+ * dpmaif_dp_init
+ * DESCRIPTION
+ * Initialize dpmaif driver.
+ * PARAMETERS
+ * None
+ * RETURN VALUES
+ * KAL_TRUE : dpmaif init successfully.
+ * KAL_FALSE : dpmaif init unsuccessfully.
+******************************************************************************/
+kal_bool dpmaif_dp_init();
+
+
+#endif
diff --git a/mcu/interface/driver/hif/hif_lhifdev/hif_lhif.h b/mcu/interface/driver/hif/hif_lhifdev/hif_lhif.h
new file mode 100644
index 0000000..d4e2507
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_lhifdev/hif_lhif.h
@@ -0,0 +1,715 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hif_lhif.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * lhif driver public API
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 12 30 2020 hsin-hao.huang
+ * [MOLY00589715] [Blocking][MT6880][Colgin][M.2][TMO-US][Data Card][SQC][HQ][R&S][LAA_5CC][998.501]UL is not up to standard
+ * .MD700 meta merge
+ *
+ * 12 18 2020 hsin-hao.huang
+ * [MOLY00609969] [Colgin] UL Traffic Shaping (UL TRAS) for PCIe
+ *
+ * EWSP0000194974 MD700 TRAS UL interface
+ *
+ * 12 01 2020 hsin-hao.huang
+ * [MOLY00595474] [MD700] DPMAIF/LHIF T700 code merge
+ * .MD700 merge back interface from T700
+ *
+ * 11 16 2020 hsin-hao.huang
+ * [MOLY00595474] [MD700] DPMAIF/LHIF T700 code merge
+ * .MD700 interface merge
+ *
+ * 09 11 2020 hsin-hao.huang
+ * [MOLY00569123] [MT6880][Colgin][MP6][SQC][MTBF][SH][PCIE][MiTA][1][core0,vpe1,tc2(vpe1)] Assert fail: mml2_hisr_97arch.c 192 - (LISR)NRL2 EXCEP
+ * .T700 interface for PCIE lowpower
+ *
+ * 09 10 2020 hsin-hao.huang
+ * [MOLY00547318] [Colgin] Feature development: Latency Tolerance Report (LTR) and Traffic Shaping (TRAS) for PCIe
+ * .T700 TRAS interface
+ *
+ * 09 05 2020 hsin-hao.huang
+ * [MOLY00560599] [HCR][Top Issue][MT6880][Colgin][M.2][MP6][SQC][MTBF][HQ][Ericsson][PCIE][ErrorTimes:6][core1,vpe0,tc0(vpe3)] Fatal Error (Cross Core Exception) Triggered by MSONIC0_TH0 : ECT status(0x00010010): (0x3101,@_@
+ * .
+ *
+ * 08 07 2020 hsin-hao.huang
+ * [MOLY00541625] [Colgin][SB] DPMAIF code merge
+ *
+ * .T700 LTR interface
+ *
+ * 08 06 2020 hsin-hao.huang
+ * [MOLY00541625] [Colgin][SB] DPMAIF code merge
+ * colgin code merge
+ *
+ * 07 07 2020 hsin-hao.huang
+ * [MOLY00541625] [Colgin][SB] DPMAIF code merge
+ * PCIE support interface porting
+ *
+ * 07 06 2020 hsin-hao.huang
+ * [MOLY00541625] [Colgin][SB] DPMAIF code merge
+ * interface porting
+ *
+ * 05 08 2020 hsin-hao.huang
+ * [MOLY00518935] [1.7 VTF][MT6873][Margaux][Q0][MP2][SQC][5G FT][NSA][5GMM][China][CMCC][FT][CMCC FT][Chip Test][RT][5G-FT-NSA-1.7][Beijing]MT6873 DL average TPUT(229.99Mbps) is worse than MT6889(264.9Mbps) when DL parallel testing.
+ * .R3 ack full interface
+ *
+ * 03 31 2020 grass.chang
+ * [MOLY00508937] 2885562：【19131】【DVT】【NSA】【广场场测】19131CMCC主+CU（5GIMS+IMS），关闭wifi使用卡1移动数据出现数据图标下行置灰，无法上网，飞模恢复，概率1/10 (suspect ZTE gNB issue)
+ * .
+ * [vmoly]ipf_match_api interface
+ *
+ * 02 25 2020 hsin-hao.huang
+ * [MOLY00501471] [HCR][Top Issue][MT6873][Margaux][Q0][MP2][SQC][HQ][MTBF][Lab][Ericsson][ErrorTimes:4]md1:(MSONIC0) [ASSERT] file:dsp3/coresonic/msonic/modem/common/nr/nr_schd/src/nr_schd_mc_lisr_entry.c line:1024
+ * .VMOLY dpmaif reorder enhance interface
+ *
+ * 02 10 2020 hsin-hao.huang
+ * [MOLY00498768] [MT6873][Margaux][Q0][MP3][SQC][VDF][FT][UK][London][NSA][MDST][SWIFT]Assert fail: Line 1024 Code 0x0 0x0 0x0
+ * .DPMAIF vcore/clk ehance interface
+ *
+ * 12 04 2019 hsin-hao.huang
+ * [MOLY00458388] add data path exception path by LHIF API
+ * .LHIF dtapath assert interface
+ *
+ * 09 11 2019 hsin-hao.huang
+ * [MOLY00439255] [Need Patch](LTE domain) VMOLY.MERCURY.19Q2.DEV build error for MERCURY_FPGA(NLWCTG_MODEM)
+ * Mercury warning porting
+ *
+ * 07 23 2019 hsin-hao.huang
+ * [MOLY00424123] [MT6297][Apollo][Sanity Fail][VMOLY][20190722][Hangzhou FT Sanity]Index：2094078，Modem warning:[1][MOD_ENPDCP]npdcp_dl_pit_handler.c #249;
+ * .add addr info fo PDCP interface
+ *
+ * 07 12 2019 hsin-hao.huang
+ * [MOLY00417255] [MT6297][Apollo][MP1][SQC][FT][China][Shenzhen][4GMM][Dongle][1][core1,vpe0,tc0(vpe3)] Assert fail: epdcp_main.c 2155 - IPCORE
+ * change protocol idx number
+ *
+ * 05 15 2019 hsin-hao.huang
+ * [MOLY00406246] [Gaming][KoG][L2] Gen97 Gaming enhancement
+ * .lhif vrb check interface
+ *
+ * 03 14 2019 hsin-hao.huang
+ * [MOLY00390308] [MT6297][Apollo][EVB][PS Performance][NSA][NSIOT] Assert fail: nrlcdl_data.c 1633 - NL2DL when HW path was tested
+ * .DPMAIF/LHIF 5G reorder tput interface enhance
+ *
+ * 11 29 2018 hsin-hao.huang
+ * [MOLY00346950] [VMOLY] Gen97 porting to VMOLY
+ * LHIF petrus log
+ *
+ * 11 07 2018 hsin-hao.huang
+ * [MOLY00346950] [VMOLY] Gen97 porting to VMOLY
+ * .5G IPF porting
+ *
+ * 11 07 2018 hsin-hao.huang
+ * [MOLY00346950] [VMOLY] Gen97 porting to VMOLY
+ * .IPF 5G handler
+ *
+ * 09 07 2018 hsin-hao.huang
+ * [MOLY00346950] [VMOLY] Gen97 porting to VMOLY
+ * .97 reorder porting
+ *
+ * 08 24 2018 hsin-hao.huang
+ * [MOLY00346950] [VMOLY] Gen97 porting to VMOLY
+ * .build err
+ *
+ * 07 31 2018 hsin-hao.huang
+ * [MOLY00327112] [6297][DEV] LHIF driver porting for Gen97
+ * .lhif driver porting
+ *
+ * 07 19 2018 hsin-hao.huang
+ * [MOLY00327112] [6297][DEV] LHIF driver porting for Gen97
+ * .lhif 97 DVT
+ *
+ * 05 30 2018 hsin-hao.huang
+ * [MOLY00327112] [6297][DEV] LHIF driver porting for Gen97
+ * .97 DEV porting
+ *
+ * 05 18 2018 hsin-hao.huang
+ * [MOLY00327112] [6297][DEV] LHIF driver porting for Gen97
+ * .Gen97 driver porting
+ *
+ * 04 17 2018 kaisar.haque
+ * [MOLY00320422] [Gen97][L234 NW-UE SIM][NotTarget] L2 C-model development
+ * Bringing in 97 UPP and Cipher C-model changes from
+ * //UMOLYE_CBr/UMOLYE.GEN97.PS/UMOLYE.GEN97.PS.kaisar.haque_UPP.dev/...
+ * To //UMOLYE/DEV/UMOLYE.GEN97.DEV/...
+ *
+ * 04 17 2018 kaisar.haque
+ * [MOLY00320422] [Gen97][L234 NW-UE SIM][NotTarget] L2 C-model development
+ * Integrate //UMOLYE_CBr/UMOLYE.GEN97.PS/UMOLYE.GEN97.PS.kaisar.haque_UPP.dev/... to //UMOLYE/DEV/UMOLYE.GEN97.DEV/...
+ *
+ * 03 29 2018 hsin-hao.huang
+ * [MOLY00316937] [6297][DEV] LHIF driver porting
+ * .
+ *
+ * 03 29 2018 hsin-hao.huang
+ * [MOLY00316937] [6297][DEV] LHIF driver porting
+ * build error
+ *
+ * 03 29 2018 hsin-hao.huang
+ * [MOLY00316937] [6297][DEV] LHIF driver porting
+ * .build error
+ *
+ * 03 13 2018 hsin-hao.huang
+ * [MOLY00309357] [UMOLYE][6295] LHIF DVT test code porting
+ * .MDT interface porting
+ *
+ * 01 12 2018 hsin-hao.huang
+ * [MOLY00301952] [MT6763][Bianco][O1][MP2.0][MP2 Regression][SWIFT][Overnight][SZ][CU+CU][4GMM][4GMM][ASSERT] file:mcu/common/driver/dpcopro/src/dpcopro_hisr.c line:568
+ * Lhif log isr state race condition
+ *
+ * 01 12 2018 hsin-hao.huang
+ * [MOLY00301952] [MT6763][Bianco][O1][MP2.0][MP2 Regression][SWIFT][Overnight][SZ][CU+CU][4GMM][4GMM][ASSERT] file:mcu/common/driver/dpcopro/src/dpcopro_hisr.c line:568
+ * .log isr race condition
+ *
+ * 01 09 2018 hsin-hao.huang
+ * [MOLY00288868] [UMOLYA][6293/6295][LHIF] LHIF driver re-design for 93/95
+ * .DL IPF enhance
+ *
+ * 01 09 2018 hsin-hao.huang
+ * [MOLY00288868] [UMOLYA][6293/6295][LHIF] LHIF driver re-design for 93/95
+ * .DL IPF enhance
+ *
+ * 11 21 2017 hsin-hao.huang
+ * [MOLY00288868] [UMOLYA][6293/6295][LHIF] LHIF driver re-design for 93/95
+ * 95 MODIS issue
+ *
+ * 11 14 2017 hsin-hao.huang
+ * [MOLY00288868] [UMOLYA][6293/6295][LHIF] LHIF driver re-design for 93/95
+ * .
+ *
+ * 11 14 2017 hsin-hao.huang
+ * [MOLY00288868] [UMOLYA][6293/6295][LHIF] LHIF driver re-design for 93/95
+ * .LHIF driver/core define
+ *
+ * 11 10 2017 hsin-hao.huang
+ * [MOLY00288868] [UMOLYA][6293/6295][LHIF] LHIF driver re-design for 93/95
+ * .MODIS error
+ *
+ * 11 10 2017 hsin-hao.huang
+ * [MOLY00288868] [UMOLYA][6293/6295][LHIF] LHIF driver re-design for 93/95
+ * .
+ *
+ * 11 10 2017 hsin-hao.huang
+ * [MOLY00288860] [6293][R3] LHIF driver re-design for 93/95 co-codebase
+ * R3 LHIF 93/95 co-code base
+ *
+ * 08 02 2017 hsin-hao.huang
+ * [MOLY00267433] [BIANCO][MT6763][RDIT][L+L][MTBF][PHONE][Overnight][HQ][Lab][Ericsson][ASSERT] file:mcu/common/driver/dpcopro/src/dpcopro_hisr.c line:430
+ * UMOLYA merge
+ *
+ * 06 27 2017 hsin-hao.huang
+ * [MOLY00259861] [Rose][Telephony switch][Bianco][N1]Externel (EE),0,0,99,/data/core/,1,modem,Trigger time:[2017-06-26 15:02:36.261168]md1:(MCU_core1.vpe1.tc1(VPE3)) [Fatal error(task)] err_code1:0x00000B34 err_code2:0x902404A9 err_code3:0xCCCCCCCC CaDeFa Supported.
+ * LHIF lock hw register issue in back up funciton
+ *
+ * 05 11 2017 hsin-hao.huang
+ * [MOLY00248647] [BIANCO][LHIF] LHIF driver re-organization from LHIF core
+ * LHIF dirver re-organization from LHIF core
+ *
+ * 04 21 2017 hsin-hao.huang
+ * [MOLY00243828] [BIANCO][MT6763][RDIT][PHONE][Overnight][HQ][MTBF][Lab][Ericsson][ASSERT] file:mcu/pcore/modem/el2/el2h/erlcdl/src/erlcdl_reasm.c line:560
+ * LHIF check CLDMA DL ready
+ *
+ * 08 23 2016 cs.huang
+ * [MOLY00189147] [LHIF] Add LHIFCORE & LHIFDEV
+ * [LHIF] Change L2Copro wri ptr and start API
+ *
+ * 08 19 2016 cs.huang
+ * [MOLY00189147] [LHIF] Add LHIFCORE & LHIFDEV
+ * [LHIF] fix modis build error
+ *
+ * 08 19 2016 cs.huang
+ * [MOLY00189147] [LHIF] Add LHIFCORE & LHIFDEV
+ * [LHIF DEV] fix modis build error
+ *
+ * 07 18 2016 cs.huang
+ * [MOLY00189147] [LHIF] Add LHIFCORE & LHIFDEV
+ * [LHIF] Fix MoDIS build error
+ *
+ * 07 13 2016 cs.huang
+ * [MOLY00189147] [LHIF] Add LHIFCORE & LHIFDEV
+ * [LHIF] Update LHIF register
+ *
+ * 07 12 2016 cs.huang
+ * [MOLY00189147] [LHIF] Add LHIFCORE & LHIFDEV
+ * [LHIF] Fix build warnings
+ *
+ ****************************************************************************/
+#ifndef _HIF_LHIF_H
+#define _HIF_LHIF_H
+
+#if defined(__MD93__)
+#define _LHIF_GEN93_HW_
+//#define _LHIF_93SW_NO_CO_CB_
+#elif defined(__MD95__)
+#define _LHIF_GEN95_HW_
+#elif defined(__MD97__)
+#define _LHIF_GEN97_HW_
+//#define _MT6885_HW_LOG_
+#elif defined(__MD97P__)
+#define _LHIF_GEN97_HW_
+#else
+#error
+#endif
+
+//#define _LHIF_LOG_MODE0_
+//#define _LHIF_LOG_MODE1_
+#define _LHIF_LOG_MODE2_
+//#define _LHIF_LOG_MODE3_
+
+#ifdef _LHIF_93SW_NO_CO_CB_
+#include "dpcopro_router.h"
+#endif
+
+#if defined(__MTK_TARGET__)
+#if defined(__HIF_PCIE_SUPPORT__)
+#define __HIF_LHIF_PCIE_SUPPORT__
+#endif
+
+#if defined(__HIF_PCIE_SUPPORT__) && defined(__HIF_DPMAIF_DP_SUPPORT__)
+#if defined(CHIP10992)
+#define __LHIF_DUALIPC__
+#endif
+#endif
+
+#endif
+
+#if defined(__MTK_TARGET__)
+#if defined(__PCIE_LTR_SUPPORT__)
+#define __LHIF_PCIE_LTR_SUPPORT__
+#endif
+
+#define __LHIF_UT_LOOPBACK_TST__
+#endif
+
+#define __LHIF_HW_IOCU_TABLE__
+
+/***********************************************************************
+ * define module ID of copro power unit
+ *
+ ***********************************************************************/
+
+#define LHIF_DRV_PWD_ID_AP_UL DPCOPRO_PWR_MOD_AP_UL_LHIF
+#define LHIF_DRV_PWD_ID_SW_UL DPCOPRO_PWR_MOD_SW_UL_LHIF
+
+
+/***********************************************************************
+ * LHIF driver power state
+ *
+ ***********************************************************************/
+typedef enum
+{
+ LHIF_DRIVER_HW_STATUS_NOT_INIT =0,
+ LHIF_DRIVER_HW_STATUS_INIT,
+ LHIF_DRIVER_HW_STATUS_L2_INIT,
+ LHIF_DRIVER_HW_STATUS_CAN_BE_USED,
+ LHIF_DRIVER_HW_STATUS_CAN_NOT_BE_USED,
+ LHIF_DRIVER_HW_STATUS_DO_NOT_INIT,
+
+}LHIF_DRIVER_HW_STATUS;
+
+typedef enum
+{
+ LHIF_PWR_OFF = 0,
+ LHIF_PWRON_SW_UL,
+ LHIF_PWRON_AP_UL,
+ LHIF_PWRON_SW_DL,
+ LHIF_PWR_OFF_LOG,
+ LHIF_PWR_MAX,
+
+}LHIF_HW_PWR_STS;
+
+/***********************************************************************
+ * ul meta table macro / ul nat descriptor
+ *
+ ***********************************************************************/
+#ifdef _LHIF_GEN93_HW_
+#ifndef _LHIF_93SW_NO_CO_CB_
+typedef struct
+{
+ kal_uint32 psn:16;
+ kal_uint32 protocol_idx:3;
+ kal_uint32 pdn:5;
+ kal_uint32 net_if:5;
+ kal_uint32 net_type:3;
+ kal_uint32 length:16;
+ kal_uint32 drb:8; // LWA only
+ kal_uint32 reserved2:7;
+ kal_uint32 ignore:1; // 1: ignore
+ kal_uint8* vrb_addr;
+}lhif_meta_tbl_t;
+#endif
+#endif
+
+#if defined(_LHIF_GEN95_HW_) || defined(_LHIF_GEN97_HW_)
+typedef struct
+{
+ kal_uint32 psn:16;
+ kal_uint32 channel_id:8;
+ kal_uint32 net_type:3;
+ kal_uint32 reserved1:4;
+ kal_uint32 ignore:1; // 1: ignore
+ kal_uint32 length:16;
+ kal_uint32 drb:8; // LWA only
+ kal_uint32 pdn:6;
+ kal_uint32 protocol_idx:2;
+ kal_uint8* vrb_addr;
+ kal_uint32 match_index:8;
+ kal_uint32 mr:3;
+ kal_uint32 reserved2:1;
+ kal_uint32 ip:1;
+ kal_uint32 ea:1;
+ kal_uint32 reserved3:2;
+ kal_uint32 tcp_flags:8;
+ kal_uint32 tos_traffic_class:8;
+ //kal_uint32 net_if[0]; //test
+}lhif_meta_tbl_t;
+
+typedef struct
+{
+ kal_uint32 count_l:16;
+ kal_uint32 channel_id:8;
+ kal_uint32 net_type:3;
+ kal_uint32 ipid:1;
+ kal_uint32 reserved1:2;
+ kal_uint32 add:1;
+ kal_uint32 nat:1;
+ kal_uint32 pub_local_port:16;
+ kal_uint32 prv_local_ip:8;
+ kal_uint32 protocol:8;
+ kal_uint32 remote_ip:32;
+ kal_uint32 prv_local_port:16;
+ kal_uint32 remote_port:16;
+}lhif_ul_nat_inband_data_t;
+#endif
+
+/***********************************************************************
+ * ul meta MR filed
+ *
+ ***********************************************************************/
+#if defined(_LHIF_GEN95_HW_) || defined(_LHIF_GEN97_HW_)
+typedef enum
+{
+ LHIF_META_MR_HPC_MATCH=0,
+ LHIF_META_MR_HPC_NEW,
+ LHIF_META_MR_NAT_MATCH,
+ LHIF_META_MR_NAT_MATCH_NO_TRAN,
+ LHIF_META_MR_NAT_DEL_MATCH,
+ LHIF_META_MR_NAT_DEL_NO_MATCH,
+ LHIF_META_MR_NAT_ADD,
+ LHIF_META_MR_UNKNOWN,
+ LHIF_META_MR_NUM,
+
+}LHIF_DRV_META_MR;
+#endif
+
+/***********************************************************************
+ * log mode define
+ *
+ ***********************************************************************/
+#define LHIF_LOG_MODE0_TIME_STAMP 20 // 2^n us
+
+typedef enum
+{
+ LHIF_HW_LOG_MODE0 = 0, // 4bytes + time
+ LHIF_HW_LOG_MODE1 = 1, // 12 bytes
+ LHIF_HW_LOG_MODE2 = 2, // 12+54 = 64 bytes
+ LHIF_HW_LOG_MODE3 = 3, // 4 bytes only
+ LHIF_HW_LOG_MODE4 = 4, // 2+54 = 64 bytes IPF log
+ LHIF_HW_LOG_MODE_MAX = 5,
+
+}LHIF_DRIVER_HW_LOG_MODE;
+
+#define LHIF_DRV_LOG_WIDX_ADV_BIT (1 << 0)
+#define LHIF_DRV_LOG_FULL_BIT (1 << 1)
+
+/***********************************************************************
+ * L2 interrupt define
+ *
+ ***********************************************************************/
+#define L2_EVENT_LHIF_AP_UL (1<<0)
+#define L2_EVENT_LHIF_LWA_DL (1<<1)
+#define L2_EVENT_LHIF_DL (1<<2)
+#define L2_EVENT_LHIF_ERROR (1<<3)
+#define L2_EVENT_LHIF_LOG (1<<4)
+#define L2_EVENT_LHIF_LOG_FULL (1<<5)
+
+/***********************************************************************
+ * LHIF driver property format for LHIFcore init
+ *
+ ***********************************************************************/
+
+typedef struct _lhif_property {
+
+ kal_uint32 lhif_mtu;
+ kal_bool lhif_hw_log_en;
+ LHIF_DRIVER_HW_LOG_MODE lhif_hw_log_mode;
+ kal_uint32 lhif_hw_log_size;
+ void *lhif_hw_log_base;
+ kal_uint32 lhif_hw_log_reserved_len;
+
+ void (*l2_lhif_interrupt_cb)(kal_uint32 event);
+ void (*lhif_pwr_interrupt_cb)(LHIF_HW_PWR_STS state);
+ void (*lhif_log_init_cb)(void);
+
+}lhif_property_t;
+
+/***********************************************************************
+ * 97 Cipher meta/UPP meta last entry format
+ *
+ ***********************************************************************/
+#if defined(_LHIF_GEN97_HW_)
+typedef struct
+{
+ kal_uint32 meta_idx:16;
+ kal_uint32 last_pit_num:8;
+ kal_uint32 reserved1:4;
+ kal_uint32 dest:3;
+ kal_uint32 reserved2:1;
+
+}lhif_nr_dl_reorder_t;
+#endif
+
+/***********************************************************************
+ * LHIF driver related function definition
+ *
+ * The function description please see the C file
+ ***********************************************************************/
+void lhif_drv_init(lhif_property_t *p_property);
+void lhif_drv_init_hw_log(lhif_property_t *p_property);
+
+kal_bool lhif_drv_meta_table_polling(kal_uint32 meta_id, kal_uint16 *r_idx,kal_uint16 *w_idx);
+kal_bool lhif_drv_log_table_polling(kal_uint16 *r_idx,kal_uint16 *w_idx);
+
+
+kal_bool lhif_drv_dl_enable(kal_bool enable);
+kal_bool lhif_drv_ul_enable(kal_bool enable);
+
+void lhif_l2_drv_init(void);
+void lhif_drv_hw_backup(void);
+void lhif_drv_hw_restore(void);
+
+#if defined(_LHIF_GEN95_HW_) || defined(_LHIF_GEN97_HW_)
+void lhif_ipf_drv_init(void(*reg_cb)(kal_uint32 meta_id,kal_bool en));
+kal_bool lhif_ipf_drv_meta_table_polling(kal_uint32 meta_id, kal_uint16 *r_idx, kal_uint16 *w_idx);
+#endif
+
+void lhif_drv_ccci_datapath_error(void);
+kal_bool lhif_drv_chk_ap_dma_idle(void);
+
+void lhif_drv_set_mtu(kal_uint16 size);
+kal_uint16 lhif_drv_get_mtu();
+kal_uint32 lhif_drv_get_error();
+void lhif_drv_clr_error();
+void lhif_drv_mask_all_error();
+void lhif_drv_unmask_all_error();
+void lhif_drv_force_md_error();
+void lhif_drv_force_ap_error();
+void lhif_drv_backup_all_reg();
+void lhif_drv_restore_all_reg();
+kal_bool lhif_drv_log_enable(kal_bool enable);
+kal_uint32 lhif_drv_log_get_base();
+void lhif_drv_log_set_base(kal_uint32 log_base);
+kal_uint32 lhif_drv_log_get_entry_num();
+void lhif_drv_log_set_entry_num(kal_uint32 entry_num);
+kal_uint16 lhif_drv_log_get_entry_size();
+void lhif_drv_log_set_entry_size(kal_uint16 entry_size);
+kal_uint16 lhif_drv_log_get_data_len();
+void lhif_drv_log_set_data_len(kal_uint16 data_len);
+kal_uint16 lhif_drv_log_get_read_idx();
+kal_uint16 lhif_drv_log_get_hw_read_idx();
+void lhif_drv_log_set_read_idx(kal_uint16 read_idx);
+kal_uint16 lhif_drv_log_get_write_idx();
+kal_uint16 lhif_drv_log_get_hw_write_idx();
+void lhif_drv_log_set_write_idx(kal_uint16 write_idx);
+kal_uint16 lhif_drv_log_get_log_seq();
+void lhif_drv_log_set_log_seq(kal_uint16 log_seq);
+kal_uint16 lhif_drv_log_get_sw_reserved_room();
+void lhif_drv_log_set_sw_reserved_room(kal_uint16 room_size);
+kal_uint32 lhif_drv_log_get_log_full();
+kal_uint32 lhif_drv_check_meta_full();
+kal_uint32 lhif_drv_check_vrb_shortage();
+void lhif_drv_log_int_clr_notify(kal_uint32 notify);
+kal_uint32 lhif_drv_log_int_get_notify();
+void lhif_drv_log_int_set_mask(kal_uint32 mask);
+kal_uint32 lhif_drv_log_int_get_mask();
+kal_bool lhif_drv_dl_cldma_ready_check(void);
+kal_bool lhif_drv_meta_query_next_rw_idx(kal_uint32 meta_id, kal_uint16 *r_idx,kal_uint16 *w_idx);
+void lhif_drv_meta_rel_entry(kal_uint32 meta_id, kal_uint16 rel_entry_num);
+kal_uint32* lhif_drv_meta_get_base(kal_uint32 meta_id);
+kal_uint16 lhif_drv_meta_get_tbl_entry_num(kal_uint32 meta_id);
+kal_uint32* lhif_drv_desc_get_wri_ptr(kal_uint32 desc_id, kal_uint16 *remain_cont_word_num);
+kal_uint32* lhif_drv_desc_inc_wri_ptr_and_start(kal_uint32 qid, kal_uint16 inc_num);
+void lhif_drv_set_ib_desc_cksum(kal_uint32 *ib_desc);
+void lhif_drv_copro_vrb_release(void* addr, kal_uint16 len, kal_uint8 task_id);
+void lhif_drv_dpcopro_power_on(kal_uint8 mod_id);
+void lhif_drv_dpcopro_power_down(kal_uint8 mod_id);
+void lhif_drv_dpcopro_event_cb_reg(void(*reg_cb)(kal_uint32 event),kal_uint32 reg_event);
+void lhif_drv_dpcopro_cb_event_update(kal_uint32 reg_event);
+
+kal_uint32 lhif_drv_get_all_dp_power_status(void);
+void lhif_drv_dpcopro_event_reg(kal_uint32 reg_event);
+void lhif_drv_dpcopro_event_dereg(kal_uint32 reg_event);
+
+void lhif_drv_data_write_dl_inband_desc(void *desc_ptr,kal_uint8 c_bit,kal_uint16 net_type,kal_uint16 net_if,kal_uint8 flush_cmd,kal_uint8 flow,kal_uint16 count_l);
+void lhif_drv_data_write_ul_inband_desc(void *desc_ptr,kal_uint8 c_bit,kal_uint16 net_type,kal_uint16 net_if,kal_uint8 flush_cmd,kal_uint8 flow,kal_uint16 count_l);
+void lhif_drv_data_write_normal_desc(void *desc_ptr,kal_uint8 c_bit,kal_uint16 offset,kal_uint8 f_bit,kal_uint16 length,void *address);
+
+#if defined(_LHIF_GEN95_HW_) || defined(_LHIF_GEN97_HW_)
+void lhif_drv_data_write_ul_nat_inband_desc(void *desc_ptr, lhif_ul_nat_inband_data_t *data_ptr);
+#endif
+
+kal_bool lhif_drv_vrb_chk_buf(void* addr);
+
+#if defined(_LHIF_GEN97_HW_)
+//kal_uint32 lhif_drv_data_add_dl_reorder(void *tbl_ptr, kal_uint32 entry_num);
+/*********************************************************************************
+ * lhif_drv_data_add_dl_reorder_rb:
+ * Brief: Deliver reorder cmd to AP DPMAIF.HW transfer temp pit to final pit
+ * Input: meta pointer, meta entry number, rb index
+ * return: success enqueue entry number to HW
+ *********************************************************************************/
+kal_uint32 lhif_drv_data_add_dl_reorder_rb(void *tbl_ptr, kal_uint32 entry_num, kal_uint8 rb_idx);
+
+/*********************************************************************************
+ * lhif_drv_data_add_dl_reorder_rb_drop:
+ * Brief: Deliver reorder cmd to AP DPMAIF.HW transfer temp pit to final pit
+ * Input: meta pointer, meta entry number, rb index
+ * return: success enqueue entry number to HW
+ *********************************************************************************/
+kal_uint32 lhif_drv_data_add_dl_reorder_rb_drop(void *tbl_ptr, kal_uint32 entry_num, kal_uint8 rb_idx);
+
+/*********************************************************************************
+ * lhif_drv_data_chk_dpmaif_resource:
+ * Brief: chk dpmaif bat/pit/tempit remain entry
+ * Input: rb_idx (valid value range: 0 ~ 15)
+ * return: bat num, pit num, tmppit num
+ *********************************************************************************/
+void lhif_drv_data_chk_dpmaif_resource(kal_uint32 rb_idx, kal_uint32*bat_num, kal_uint32*pit_num, kal_uint32*tmppit_num);
+
+/*********************************************************************************
+ * lhif_drv_data_dl_addr_info:
+ * Brief: chk data dest. addr
+ * Input: rb_idx (valid value range: 0 ~ 15),cipher last word
+ * return: addr
+ *********************************************************************************/
+void* lhif_drv_data_dl_addr_info(kal_uint16 rb_idx, kal_uint32 last_value);
+kal_bool lhif_drv_data_dl_ipf_match_result(kal_uint32 last_value,kal_uint8*mr_result);
+
+
+kal_uint32 lhif_drv_get_reorder_ib_only_en(void);
+void lhif_drv_set_reorder_ib_only_en(kal_bool en);
+kal_uint16 lhif_drv_data_get_real_meta_id(kal_uint32 sw_meta_id);
+void lhif_drv_data_set_dpmaif_ck_vc(kal_bool first_start,kal_bool en);
+void lhif_drv_dpcopro_task_handle(void);
+void lhif_drv_ccci_datapath_notify(void);
+
+void lhif_drv_reg_shortage_cb(void(*reg_cb)(kal_uint32));
+
+#endif
+
+#if defined(__LHIF_PCIE_LTR_SUPPORT__)
+kal_uint32 lhif_ltr_tras_query_pkt_cnt(void);
+void lhif_ltr_tras_force_not_ready(kal_bool force_not_ready);
+kal_bool lhif_ltr_tras_delivery_notif(void);
+kal_bool lhif_ltr_tras_delivery_check(void);
+void lhif_drv_ltr_add_qp_pkt_cnt(kal_uint32 cnt);
+
+
+void lhif_ltr_tras_ul_q_cfg(kal_bool en,kal_uint32 q_id);
+kal_uint32 lhif_ltr_tras_ul_query_pkt_cnt(kal_uint32 q_id);
+kal_uint32 lhif_ltr_tras_ul_desc_rem_wc(kal_uint32 q_id);
+kal_bool lhif_ltr_tras_ul_delivery_check(kal_uint32 q_id);
+#endif
+
+#ifdef __LHIF_UT_LOOPBACK_TST__
+void lhif_drv_set_loopback_enable(kal_bool _en);
+#endif
+
+
+#if defined(__MTK_TARGET__)
+#else // MODIS
+#include "dpcopro_router.h"
+//#include "lhif_if.h"
+
+typedef struct{
+ kal_uint32* tbl_base; // must cache(32 byte) align
+ kal_uint16 entry_num;
+ kal_uint8 entry_size;
+ kal_uint8 ch_idx;// only use for DL Cipher & 3G DL
+}lhif_meta_tbl_config_t;
+
+// Should be replaced to QP format
+kal_uint32 lhif_drv_ut_get_hw_reg_base();
+kal_uint32 lhif_drv_ut_get_hw_log_reg_base();
+kal_uint32 lhif_drv_ut_get_meta_base();
+kal_uint32 lhif_drv_ut_get_qp_base();
+void lhif_drv_ut_writereg32(kal_uint32 reg_addr, kal_uint32 value);
+kal_uint32 lhif_drv_ut_readreg32(kal_uint32 reg_addr);
+kal_bool lhif_drv_ut_dl_enable(kal_bool enable);
+kal_bool lhif_drv_ut_ul_enable(kal_bool enable);
+void lhif_qp_ut_meta_config(kal_uint32 meta_id, lhif_meta_tbl_config_t *meta);
+kal_bool lhif_qp_ut_meta_query(kal_uint32 meta_id, kal_uint16 *read_idx, kal_uint16 *end_idx);
+kal_uint32* lhif_qp_ut_get_tbl_base(kal_uint32 meta_id);
+kal_uint16 lhif_qp_ut_get_tbl_size(kal_uint32 meta_id);
+void lhif_qp_ut_meta_rel_entry(kal_uint32 meta_id, kal_uint16 rel_entry_num);
+kal_uint32* lhif_qp_ut_inc_wri_ptr(kal_uint32 desc_id, kal_uint16 desc_word_num);
+kal_uint32* lhif_qp_ut_get_wri_ptr(kal_uint32 desc_id, kal_uint16 *remain_cont_word_num);
+kal_uint32* lhif_qp_ut_inc_wri_ptr_and_start(kal_uint32 desc_id, kal_uint16 desc_word_num);
+void lhif_qp_ut_start(kal_uint32 desc_id, kal_uint16 desc_word_num);
+void lhif_qp_ut_set_checksum(inband_desc_hdr_t *hdr);
+kal_uint16 lhif_qp_ut_inc_wri_idx_and_start(kal_uint32 desc_id, kal_uint16 desc_word_num);
+void lhif_drv_ut_log_set_read_idx(kal_uint16 read_idx);
+void lhif_drv_ut_log_set_write_idx(kal_uint16 write_idx);
+void lhif_drv_ut_log_set_log_seq(kal_uint16 log_seq);
+#endif
+
+#endif //_HIF_LHIF_H
diff --git a/mcu/interface/driver/hif/hif_lhifdev/lhif_desc_arch.h b/mcu/interface/driver/hif/hif_lhifdev/lhif_desc_arch.h
new file mode 100644
index 0000000..bb08e96
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_lhifdev/lhif_desc_arch.h
@@ -0,0 +1,829 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * lhif_desc_arch.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * LHIF desc driver API
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 11 16 2020 hsin-hao.huang
+ * [MOLY00595474] [MD700] DPMAIF/LHIF T700 code merge
+ * .MD700 interface merge
+ *
+ * 10 06 2020 grass.chang
+ * [MOLY00578271] [MT6833][Palmer][LHIF]reorder workaround disable
+ *
+ * .
+ * [nr15.r3.mp][MT6833][Palmer][LHIF]reorder workaround disable
+ *
+ * 03 03 2020 hsin-hao.huang
+ * [MOLY00502966] [MT6873][Margaux][Q0][MP2][SQC][HQ][MTBF][Lab][Ericsson][ErrorTimes:1]md1:(MSONIC0) [ASSERT] file:dsp3/coresonic/msonic/modem/common/nr/nr_schd/src/nr_schd_mc_lisr_entry.c line:1024
+ * .DPMAIF queue hang workaround interface
+ *
+ * 02 19 2020 hsin-hao.huang
+ * [MOLY00500501] [Blocking][CMCC MTBF][MT6873][Margaux][Q0][ASSERT] file:dsp3/coresonic/msonic/modem/common/nr/nr_schd/src/nr_schd_mc_lisr_entry.c line:1024
+ * .DPMAIF dummy reorder interface
+ *
+ * 01 16 2020 hsin-hao.huang
+ * [MOLY00474941] [MT6885][Petrus][MP1][IODT][EIOT][Taiwan][NSA][5G][B2+N41_NR.MB.2.12.1.85][1][core0,vpe0,tc0(vpe0)] Assert fail: errc_chm_main.c 9724 0x0 0x1 0x0 - ERRC
+ * .DPMAIF LHIF reorder ehance interface
+ *
+ * 05 09 2019 hsin-hao.huang
+ * [MOLY00401354] [MT6297][Phone Call][NSA FullStack][Huawei][Shanghai][5G][VMOLY]Assert fail: el2_sec_utility.c 327 - IPCORE
+ * .LHIF/DPMAIF reorder ehance interface
+ *
+ * 03 22 2019 hsin-hao.huang
+ * [MOLY00392407] [MT6297][Apollo][Sanity Fail][VMOLY][NR][Anritsu NSA][20190316][0200] UDP DL transmission fail
+ * .reorder full issue interface
+ *
+ * 12 27 2018 hsin-hao.huang
+ * [MOLY00374594] [Gen97][5G reorder] L2SW / IPCORE / IPFCORE / LHIF driver integration patch
+ * .95 NR reorder IT
+ *
+ * 10 30 2018 hsin-hao.huang
+ * [MOLY00346950] [VMOLY] Gen97 porting to VMOLY
+ * .VMOLY porting
+ *
+ * 09 07 2018 hsin-hao.huang
+ * [MOLY00346950] [VMOLY] Gen97 porting to VMOLY
+ * .97 reorder porting
+ *
+ * 08 20 2018 wen-zhi.huang
+ * [MOLY00252913] MT6295 MML2 driver porting
+ * [VMOLY] merge driver code back with UMOLYE.TRUNK & 97.DEV
+ *
+ * 07 19 2018 hsin-hao.huang
+ * [MOLY00327112] [6297][DEV] LHIF driver porting for Gen97
+ * .97 porting
+ *
+ * 07 19 2018 hsin-hao.huang
+ * [MOLY00327112] [6297][DEV] LHIF driver porting for Gen97
+ * .lhif 97 DVT
+ *
+ * 06 20 2018 hsin-hao.huang
+ * [MOLY00327112] [6297][DEV] LHIF driver porting for Gen97
+ * .DL LHIF meta format
+ *
+ * 05 30 2018 hsin-hao.huang
+ * [MOLY00327112] [6297][DEV] LHIF driver porting for Gen97
+ * .97 DEV porting
+ *
+ * 01 09 2018 hsin-hao.huang
+ * [MOLY00288868] [UMOLYA][6293/6295][LHIF] LHIF driver re-design for 93/95
+ * .DL IPF enhance
+ *
+ * 01 09 2018 hsin-hao.huang
+ * [MOLY00288868] [UMOLYA][6293/6295][LHIF] LHIF driver re-design for 93/95
+ * .DL IPF enhance
+ *
+ * 10 16 2017 hsin-hao.huang
+ * [MOLY00266206] [6295][DEV] LHIF driver re-design for Gen93/Gen95 co-branch
+ * new change
+ *
+ * 09 26 2017 hsin-hao.huang
+ * [MOLY00266206] [6295][DEV] LHIF driver re-design for Gen93/Gen95 co-branch
+ * .
+ *
+ * 09 20 2017 hsin-hao.huang
+ * [MOLY00266206] [6295][DEV] LHIF driver re-design for Gen93/Gen95 co-branch
+ * .LHIF 95
+ *
+ * 09 11 2017 hsin-hao.huang
+ * [MOLY00266206] [6295][DEV] LHIF driver re-design for Gen93/Gen95 co-branch
+ * .LHIF/DPMAIF drver design
+ *
+ *
+ ****************************************************************************/
+#ifndef _LHIF_DESC_DEV_H
+#define _LHIF_DESC_DEV_H
+
+#include "dpcopro_router.h"
+#include "hif_lhif.h"
+#include "cache_sw.h"
+
+/***********************************************************************
+ * Driver feature compiler option
+ * Auther: HH.Huang
+ * Brief:
+ ***********************************************************************/
+#if defined(_LHIF_GEN97_HW_)
+ #if defined(ATEST_DRV_ENABLE) && !defined(ATEST_DRV_LHIF)
+ /*DPCOPRO driver test dont use*/
+ #define __LHIF_REORDER_EN_WORKAROUND__
+ #else /*ATEST_DRV_LHIF*/
+ #define __LHIF_DPMAIF_ULTRA_PATCH__
+ #if defined (__HIF_DPMAIF_SUPPORT__) && defined(__MTK_TARGET__)
+ #if defined(CHIP10992)
+ //#define __LHIF_DUMMY_REORDER_EN__
+ //#define __LHIF_REORDER_EN_WORKAROUND__
+ #define __LHIF_REORDER_BURST_EN__
+ #else
+ //#define __LHIF_DUMMY_REORDER_EN__
+ #define __LHIF_REORDER_EN_WORKAROUND__
+ //#define __LHIF_REORDER_BURST_EN__
+ #endif
+ #endif
+ #endif /*ATEST_DRV_LHIF*/
+
+#define __LHIF_2CC_WRITE_REORDER_DATA__
+#endif /*_LHIF_GEN97_HW_*/
+
+/***********************************************************************
+ * lhif DL VRB meta format
+ * Auther: HH.Huang
+ * Brief: LHIF HW log mode definition
+ ***********************************************************************/
+#if defined(_LHIF_GEN97_HW_)
+
+typedef struct
+{
+ kal_uint32 count_l:16;
+ kal_uint32 channel_id:8;
+ kal_uint32 net_type:3;
+ kal_uint32 reserved1:5;
+ kal_uint32 length:16;
+ kal_uint32 flow:5;
+ kal_uint32 reserved2:11;
+ kal_uint8* vrb_addr;
+}lhif_dl_meta_tbl_t;
+
+#endif
+
+/***********************************************************************
+ * lhif_hw_log_mode
+ *
+ * Auther: CS.Huang (2016/5/4)
+ * Brief: LHIF HW log mode definition
+ ***********************************************************************/
+typedef enum
+{
+ LHIF_HW_LOG_RAW_DATA_MODE =0,
+ LHIF_HW_LOG_PARSING_MODE =1,
+}lhif_hw_log_mode;
+
+#ifdef _LHIF_GEN93_HW_
+#ifndef _LHIF_93SW_NO_CO_CB_
+typedef struct{
+ kal_uint32 length:14;
+ kal_uint32 log_seq:14;
+ kal_uint32 frc_bit:1;
+ kal_uint32 dir:3;
+ kal_uint16 count_l; // psn
+ kal_uint16 flow:4;
+ kal_uint16 flush_cmd:3;
+ kal_uint16 mode:1;
+ kal_uint16 net_if:5;
+ kal_uint16 net_type:3;
+ kal_uint32 frc; // free run counter
+ kal_uint8 data[52]; // data part
+}lhif_hw_log_format_t;
+#endif
+#endif /*_LHIF_GEN93_HW_*/
+
+#if defined(_LHIF_GEN95_HW_) || defined(_LHIF_GEN97_HW_)
+#ifdef _LHIF_LOG_MODE0_
+typedef struct{
+ kal_uint32 header_mode:2;
+ kal_uint32 reserved1:2;
+ kal_uint32 t_stamp:1;
+ kal_uint32 que_type:3;
+ kal_uint32 flow:4; // psn
+ kal_uint32 flush_cmd:3;
+ kal_uint32 reserved2:1;
+ kal_uint16 count_l;
+}lhif_hw_log_format_t;
+#endif
+#ifdef _LHIF_LOG_MODE1_
+typedef struct{
+ kal_uint32 header_mode:2;
+ kal_uint32 reserved1:2;
+ kal_uint32 t_stamp:1;
+ kal_uint32 que_type:3;
+ kal_uint32 flow:4; // psn
+ kal_uint32 flush_cmd:3;
+ kal_uint32 reserved2:1;
+ kal_uint16 count_l;
+ kal_uint32 reserved3:16;
+ kal_uint32 channel_id:8;
+ kal_uint32 net_type:3;
+ kal_uint32 reserved4:5;
+ kal_uint16 frc_stamp_time;
+ kal_uint16 log_seq;
+}lhif_hw_log_format_t;
+#endif
+#ifdef _LHIF_LOG_MODE2_
+typedef struct{
+ kal_uint32 header_mode:2;
+ kal_uint32 reserved1:2;
+ kal_uint32 t_stamp:1;
+ kal_uint32 que_type:3;
+ kal_uint32 flow:4; // psn
+ kal_uint32 flush_cmd:3;
+ kal_uint32 reserved2:1;
+ kal_uint16 count_l;
+ kal_uint32 reserved3:16;
+ kal_uint32 channel_id:8;
+ kal_uint32 net_type:3;
+ kal_uint32 reserved4:5;
+ kal_uint16 frc_stamp_time;
+ kal_uint16 log_seq;
+ kal_uint8 data[52]; // data part
+}lhif_hw_log_format_t;
+#endif
+#ifdef _LHIF_LOG_MODE3_
+typedef struct{
+ kal_uint32 header_mode:2;
+ kal_uint32 reserved1:2;
+ kal_uint32 t_stamp:1;
+ kal_uint32 que_type:3;
+ kal_uint32 flow:4; // psn
+ kal_uint32 flush_cmd:3;
+ kal_uint32 reserved2:1;
+ kal_uint16 count_l;
+ kal_uint16 frc_stamp_time;
+ kal_uint16 log_seq;
+}lhif_hw_log_format_t;
+#endif
+
+
+#if defined(ATEST_DRV_ENABLE)
+// Log mode common define
+typedef struct{
+ kal_uint32 header_mode:2;
+ kal_uint32 reserved1:2;
+ kal_uint32 t_stamp:1;
+ kal_uint32 que_type:3;
+ kal_uint32 flow:4; // psn
+ kal_uint32 flush_cmd:3;
+ kal_uint32 reserved2:1;
+ kal_uint16 count_l;
+}lhif_hw_log_mode0_format_t;
+
+typedef struct{
+ kal_uint16 frc_stamp_time;
+ kal_uint16 log_seq;
+}lhif_hw_log_mode0_time_format_t;
+
+typedef struct{
+ kal_uint32 header_mode:2;
+ kal_uint32 reserved1:2;
+ kal_uint32 t_stamp:1;
+ kal_uint32 que_type:3;
+ kal_uint32 flow:4; // psn
+ kal_uint32 flush_cmd:3;
+ kal_uint32 reserved2:1;
+ kal_uint16 count_l;
+ kal_uint32 reserved3:16;
+ kal_uint32 channel_id:8;
+ kal_uint32 net_type:3;
+ kal_uint32 reserved4:5;
+ kal_uint16 frc_stamp_time;
+ kal_uint16 log_seq;
+}lhif_hw_log_mode1_format_t;
+
+typedef struct{
+ kal_uint32 header_mode:2;
+ kal_uint32 reserved1:2;
+ kal_uint32 t_stamp:1;
+ kal_uint32 que_type:3;
+ kal_uint32 flow:4; // psn
+ kal_uint32 flush_cmd:3;
+ kal_uint32 reserved2:1;
+ kal_uint16 count_l;
+ kal_uint32 reserved3:16;
+ kal_uint32 channel_id:8;
+ kal_uint32 net_type:3;
+ kal_uint32 reserved4:5;
+ kal_uint16 frc_stamp_time;
+ kal_uint16 log_seq;
+ kal_uint8 data[52]; // data part
+}lhif_hw_log_mode2_format_t;
+#endif /*ATEST_DRV_ENABLE*/
+
+#endif /*_LHIF_GEN95_HW_*/
+
+/***********************************************************************
+ * IPF hw compress log
+ *
+ *
+ ***********************************************************************/
+#if defined(_LHIF_GEN97_HW_)
+#define IPF_HW_IR_LOG 0
+#define IPF_HW_CD_LOG 1
+#define IPF_HW_CT_LOG 2
+
+#define IPF_HW_QUE_CIPHER 0
+#define IPF_HW_QUE_AP_UL 1
+#define IPF_HW_QUE_SW_DL 2
+#define IPF_HW_QUE_SW_UL 3
+#define IPF_HW_QUE_AP_UL_HP 6
+
+#define IPF_HW_D_AP 0
+#define IPF_HW_D_FO 2
+#define IPF_HW_D_NAT 3
+#define IPF_HW_D_VRB 4
+
+typedef struct{
+ kal_uint32 ir:2;
+ kal_uint32 ir_rp_idx:2;
+ kal_uint32 ir_tbl_idx:4;
+ kal_uint32 que_type:3;
+ kal_uint32 flow:5;
+ kal_uint32 psn:16;
+}ipf_hw_log_header_format_t;
+
+typedef struct{
+ ipf_hw_log_header_format_t log_header;
+ kal_uint32 data_len:16;
+ kal_uint32 log_pkt_seq:16;
+ kal_uint32 dest:3;
+ kal_uint32 m:1;
+ kal_uint32 c:1;
+ kal_uint32 reserved:27;
+ kal_uint32 frc;
+ kal_uint8 data[48]; // data part
+
+}ipf_hw_ir_log_format_t;
+
+typedef struct{
+
+ ipf_hw_log_header_format_t log_header;
+ kal_uint32 frc_stamp_time:16;
+ kal_uint32 log_pkt_seq:16;
+ kal_uint32 pid0:2;
+ kal_uint32 pid1:2;
+ kal_uint32 pid2:2;
+ kal_uint32 pid3:2;
+ kal_uint32 pid4:2;
+ kal_uint32 pid5:2;
+ kal_uint32 pid6:2;
+ kal_uint32 pid7:2;
+ kal_uint32 utid0:2;
+ kal_uint32 utid1:2;
+ kal_uint32 utid2:2;
+ kal_uint32 utid3:2;
+ kal_uint32 utid4:2;
+ kal_uint32 utid5:2;
+ kal_uint32 utid6:2;
+ kal_uint32 utid7:2;
+ kal_uint32 data[36]; // data part
+
+}ipf_hw_cd_log_format_t;
+
+typedef struct{
+ ipf_hw_log_header_format_t log_header;
+ kal_uint32 frc_stamp_time:16;
+ kal_uint32 log_pkt_seq:16;
+}ipf_hw_ct_log_format_t;
+
+#endif
+/***********************************************************************
+ * ul/dl inbnad data macro
+ *
+ ***********************************************************************/
+#ifdef _LHIF_GEN93_HW_
+#ifndef _LHIF_93SW_NO_CO_CB_
+typedef struct
+{
+ kal_uint32 count_l:16;
+ kal_uint32 flow:4;
+ kal_uint32 flush:3;
+ kal_uint32 reserved3:1;
+ kal_uint32 net_if:5;
+ kal_uint32 net_type:3;
+}lhif_inband_data_t;
+#endif
+
+typedef struct
+{
+ kal_uint32 count_l:16;
+ kal_uint32 flow:4;
+ kal_uint32 flush:3;
+ kal_uint32 reserved3:1;
+ kal_uint32 net_if:5;
+ kal_uint32 net_type:3;
+}lhif_dl_inband_data_t;
+
+typedef struct
+{
+ kal_uint32 count_l:16;
+ kal_uint32 flow:4;
+ kal_uint32 flush:3;
+ kal_uint32 reserved3:1;
+ kal_uint32 net_if:5;
+ kal_uint32 net_type:3;
+}lhif_ul_inband_data_t;
+
+#endif
+#if defined(_LHIF_GEN95_HW_)
+typedef struct
+{
+ kal_uint32 count_l:16;
+ kal_uint32 channel_id:8;
+ kal_uint32 net_type:3;
+ kal_uint32 reserved1:5;
+ kal_uint32 reserved2:16;
+ kal_uint32 flow:4;
+ kal_uint32 cmd:3;
+ kal_uint32 reserved3:9;
+}lhif_dl_inband_data_t;
+
+typedef struct
+{
+ kal_uint32 count_l:16;
+ kal_uint32 channel_id:8;
+ kal_uint32 net_type:3;
+ kal_uint32 reserved1:4;
+ kal_uint32 nat:1;
+}lhif_ul_inband_data_t;
+#endif
+#if defined(_LHIF_GEN97_HW_)
+typedef struct
+{
+ kal_uint32 count_l:16;
+ kal_uint32 channel_id:8;
+ kal_uint32 net_type:3;
+ kal_uint32 reserved1:5;
+ kal_uint32 qid:3;
+ kal_uint32 reserved2:13;
+ kal_uint32 flow:5;
+ kal_uint32 reserved3:3;
+ kal_uint32 cmd:3;
+ kal_uint32 reserved4:5;
+}lhif_dl_inband_data_t;
+
+typedef struct
+{
+ kal_uint32 count_l:16;
+ kal_uint32 channel_id:8;
+ kal_uint32 net_type:3;
+ kal_uint32 reserved1:4;
+ kal_uint32 nat:1;
+ kal_uint32 reserved2;
+}lhif_ul_inband_data_t;
+#endif
+
+/***********************************************************************
+ * ul/dl normal descriptor data macro
+ *
+ ***********************************************************************/
+#ifndef _LHIF_93SW_NO_CO_CB_
+typedef struct
+{
+ normal_desc_t normal_hdr;
+}lhif_normal_t;
+#endif
+
+/***********************************************************************
+ * ul/dl descriptor macro
+ *
+ ***********************************************************************/
+typedef struct
+{
+ inband_desc_hdr_t inband_hdr;
+ lhif_dl_inband_data_t inband_data;
+}lhif_dl_inband_t;
+
+typedef struct
+{
+ inband_desc_hdr_t inband_hdr;
+ lhif_ul_inband_data_t inband_data;
+}lhif_ul_inband_t;
+
+#ifdef _LHIF_GEN93_HW_
+#ifndef _LHIF_93SW_NO_CO_CB_
+typedef struct
+{
+ inband_desc_hdr_t inband_hdr;
+ lhif_inband_data_t inband_data;
+}lhif_inband_t;
+#endif
+#endif
+
+#if defined(_LHIF_GEN95_HW_) || defined(_LHIF_GEN97_HW_)
+typedef struct
+{
+ inband_desc_hdr_t inband_hdr;
+ lhif_ul_nat_inband_data_t inband_data;
+}lhif_ul_nat_inband_t;
+#endif
+
+#ifdef _LHIF_GEN93_HW_
+#ifndef _LHIF_93SW_NO_CO_CB_
+static __inline lhif_inband_data_t LHIF_DRV_DATA_WRITE_INBAND_DATA(kal_uint8 NET_TYPE, kal_uint8 NET_IF, kal_uint8 FLUSH, kal_uint8 FLOW, kal_uint16 COUNT_L)
+{
+ lhif_inband_data_t __data;
+ ((lhif_inband_data_t *)(&__data))->count_l = COUNT_L;
+ ((lhif_inband_data_t *)(&__data))->flow = FLOW;
+ ((lhif_inband_data_t *)(&__data))->flush = FLUSH;
+ ((lhif_inband_data_t *)(&__data))->reserved3 = 0;
+ ((lhif_inband_data_t *)(&__data))->net_if = NET_IF;
+ ((lhif_inband_data_t *)(&__data))->net_type = NET_TYPE;
+ return __data;
+}
+#endif
+#endif
+#if defined(_LHIF_GEN95_HW_)
+static __inline lhif_ul_inband_data_t LHIF_DRV_DATA_WRITE_UL_INBAND_DATA(kal_uint8 NET_TYPE, kal_uint8 NET_IF, kal_uint8 FLUSH, kal_uint8 FLOW, kal_uint16 COUNT_L)
+{
+ lhif_ul_inband_data_t __data;
+ ((lhif_ul_inband_data_t *)(&__data))->count_l = COUNT_L;
+ ((lhif_ul_inband_data_t *)(&__data))->channel_id = NET_IF;
+ ((lhif_ul_inband_data_t *)(&__data))->net_type = NET_TYPE;
+ ((lhif_ul_inband_data_t *)(&__data))->reserved1 = 0;
+ ((lhif_ul_inband_data_t *)(&__data))->nat = 0;
+ return __data;
+}
+
+static __inline lhif_dl_inband_data_t LHIF_DRV_DATA_WRITE_DL_INBAND_DATA(kal_uint8 NET_TYPE, kal_uint8 NET_IF, kal_uint8 FLUSH, kal_uint8 FLOW, kal_uint16 COUNT_L)
+{
+ lhif_dl_inband_data_t __data;
+ ((lhif_dl_inband_data_t *)(&__data))->count_l = COUNT_L;
+ ((lhif_dl_inband_data_t *)(&__data))->channel_id = NET_IF;
+ ((lhif_dl_inband_data_t *)(&__data))->net_type = NET_TYPE;
+ ((lhif_dl_inband_data_t *)(&__data))->reserved1 = 0;
+ ((lhif_dl_inband_data_t *)(&__data))->reserved2 = 0;
+ ((lhif_dl_inband_data_t *)(&__data))->flow = FLOW;
+ ((lhif_dl_inband_data_t *)(&__data))->cmd = FLUSH;
+ ((lhif_dl_inband_data_t *)(&__data))->reserved3 = 0;
+
+ return __data;
+}
+#endif
+#if defined(_LHIF_GEN97_HW_)
+static __inline lhif_ul_inband_data_t LHIF_DRV_DATA_WRITE_UL_INBAND_DATA(kal_uint8 NET_TYPE, kal_uint8 NET_IF, kal_uint8 FLUSH, kal_uint8 FLOW, kal_uint16 COUNT_L)
+{
+ lhif_ul_inband_data_t __data;
+ ((lhif_ul_inband_data_t *)(&__data))->count_l = COUNT_L;
+ ((lhif_ul_inband_data_t *)(&__data))->channel_id = NET_IF;
+ ((lhif_ul_inband_data_t *)(&__data))->net_type = NET_TYPE;
+ ((lhif_ul_inband_data_t *)(&__data))->reserved1 = 0;
+ ((lhif_ul_inband_data_t *)(&__data))->nat = 0;
+ ((lhif_ul_inband_data_t *)(&__data))->reserved2 = 0;
+ return __data;
+}
+
+static __inline lhif_dl_inband_data_t LHIF_DRV_DATA_WRITE_DL_INBAND_DATA(kal_uint8 NET_TYPE, kal_uint8 NET_IF, kal_uint8 FLUSH, kal_uint8 FLOW, kal_uint16 COUNT_L)
+{
+ lhif_dl_inband_data_t __data;
+ ((lhif_dl_inband_data_t *)(&__data))->count_l = COUNT_L;
+ ((lhif_dl_inband_data_t *)(&__data))->channel_id = NET_IF;
+ ((lhif_dl_inband_data_t *)(&__data))->net_type = NET_TYPE;
+ ((lhif_dl_inband_data_t *)(&__data))->reserved1 = 0;
+ ((lhif_dl_inband_data_t *)(&__data))->qid = 0x4;
+ ((lhif_dl_inband_data_t *)(&__data))->reserved2 = 0;
+ ((lhif_dl_inband_data_t *)(&__data))->flow = FLOW;
+ ((lhif_dl_inband_data_t *)(&__data))->reserved3 = 0;
+ ((lhif_dl_inband_data_t *)(&__data))->cmd = FLUSH;
+ ((lhif_dl_inband_data_t *)(&__data))->reserved4 = 0;
+
+ return __data;
+}
+#endif
+#if defined(_LHIF_GEN97_HW_)
+
+typedef enum{
+ REORDER_ID_PCIE=0,
+ REORDER_ID_5G_IPF,
+ REORDER_ID_NUM
+}REORDER_META_TBL_ID;
+
+typedef struct _lhif_drv_pbuf_st{
+ kal_uint32 meta_id;
+
+ void* meta_base_addr;
+ void* meta_mask_addr;
+
+ kal_uint32 meta_entry_num;
+ kal_uint32 meta_mask_entry_num;
+
+ kal_uint16 rd_start_idx;
+ kal_uint16 rd_end_idx;
+ kal_uint16 rd_rel_idx;
+ kal_uint16 reserved;
+
+}lhif_drv_pbuf_st_t;
+
+typedef struct _lhif_drv_reorder_t{
+
+ kal_uint32 re_len;
+ kal_uint32 re_buf_len;
+ kal_uint32 re_cnt;
+ kal_uint8* re_start_buf_ptr;
+ kal_uint8* re_cur_buf_ptr;
+
+}lhif_drv_reorder_t;
+
+typedef struct
+{
+ kal_uint32 count_l:16;
+ kal_uint32 ch_id:8;
+ kal_uint32 net_type:3;
+ kal_uint32 reserved1:5;
+ kal_uint32 length:16;
+ kal_uint32 rbid:5;
+ kal_uint32 reserved2:11;
+ void* vrb_address;
+}lhif_nr_dl_pcie_meta_t;
+
+#define NR_DL_IB_COUNTL 0x3A3A
+#define NR_DL_NOR_LENGTH 4
+
+#define NR_DL_DEST_AP 0
+#define NR_DL_DEST_PCIE 1
+#define NR_DL_DEST_FILTER 2
+#define NR_DL_DEST_DROP 3
+
+typedef struct
+{
+ kal_uint32 pit_idx:16;
+ kal_uint32 last_pit_num:4;
+ kal_uint32 reserved2:8;
+ kal_uint32 dest:2;
+ kal_uint32 reserved3:1;
+ kal_uint32 drop:1;
+
+}lhif_nr_dl_dpmaif_meta_t;
+
+typedef struct
+{
+ kal_uint16 count;
+ kal_uint8 channel_id;
+ kal_uint8 net_type:3;
+ kal_uint8 resv:5;
+ kal_uint16 len;
+ kal_uint8 rbid;
+ kal_uint8 pdn_sim_id;
+ kal_uint32 addr;
+ kal_uint8 match_idx;
+ kal_uint8 mr:3;
+ kal_uint8 rsv0:1;
+ kal_uint8 ip:1;
+ kal_uint8 fil_tog:2;
+ kal_uint8 rsv1:1;
+ kal_uint8 tcp_flag;
+ kal_uint8 filter_idx;
+}lhif_ipf_dl_meta_t;
+
+typedef struct
+{
+ kal_uint32 count_l:16;
+ kal_uint32 channel_id:8;
+ kal_uint32 net_type:3;
+ kal_uint32 reserved1:4;
+ kal_uint32 reorder:1;
+ kal_uint32 qid:3;
+ kal_uint32 reserved2:13;
+ kal_uint32 flow:5;
+ kal_uint32 reserved3:3;
+ kal_uint32 cmd:3;
+ kal_uint32 reserved4:5;
+}lhif_dl_re_inband_data_t;
+
+typedef struct
+{
+ kal_uint32 first_pit_idx:16;
+ kal_uint32 pkt_num:10;
+ kal_uint32 drop:1;
+ kal_uint32 rb_idx:5;
+ kal_uint32 reserved;
+
+}lhif_dl_re_in_only_data_t;
+
+typedef struct
+{
+ inband_desc_hdr_t inband_hdr;
+ lhif_dl_re_inband_data_t inband_data;
+}lhif_dl_re_inband_t;
+
+typedef struct
+{
+ inband_desc_hdr_t inband_hdr;
+ lhif_dl_re_in_only_data_t inband_data;
+}lhif_dl_re_in_only_t;
+
+static __inline lhif_dl_re_inband_data_t LHIF_DRV_DATA_WRITE_DL_IB_NR_DATA(kal_uint16 COUNT_L)
+{
+ lhif_dl_re_inband_data_t __data;
+ ((lhif_dl_re_inband_data_t *)(&__data))->count_l = COUNT_L;
+ ((lhif_dl_re_inband_data_t *)(&__data))->channel_id = 0;
+ ((lhif_dl_re_inband_data_t *)(&__data))->net_type = 0;
+ ((lhif_dl_re_inband_data_t *)(&__data))->reserved1 = 0;
+ ((lhif_dl_re_inband_data_t *)(&__data))->reorder = 1;
+ ((lhif_dl_re_inband_data_t *)(&__data))->qid = 0;
+ ((lhif_dl_re_inband_data_t *)(&__data))->reserved2 = 0;
+ ((lhif_dl_re_inband_data_t *)(&__data))->flow = 0;
+ ((lhif_dl_re_inband_data_t *)(&__data))->reserved3 = 0;
+ ((lhif_dl_re_inband_data_t *)(&__data))->cmd = 0;
+ ((lhif_dl_re_inband_data_t *)(&__data))->reserved4 = 0;
+
+ return __data;
+}
+
+static __inline lhif_dl_re_in_only_data_t LHIF_DRV_DATA_WRITE_DL_IB_ONLY_NR_DATA(kal_uint8 RB_IDX, kal_uint8 DROP, kal_uint16 PKT_NUM, kal_uint16 PIT_IDX)
+{
+ lhif_dl_re_in_only_data_t __data;
+ ((lhif_dl_re_in_only_data_t *)(&__data))->first_pit_idx = PIT_IDX;
+ ((lhif_dl_re_in_only_data_t *)(&__data))->pkt_num = PKT_NUM;
+ ((lhif_dl_re_in_only_data_t *)(&__data))->drop = DROP;
+ ((lhif_dl_re_in_only_data_t *)(&__data))->rb_idx = RB_IDX;
+ ((lhif_dl_re_in_only_data_t *)(&__data))->reserved = 0;
+
+ return __data;
+}
+
+static __inline lhif_dl_re_inband_data_t LHIF_DRV_DATA_WRITE_DL_IB_NR_DATA_PCIE(kal_uint16 COUNT_L,kal_uint16 CH_ID,kal_uint8 NET_TYPE,kal_uint8 FLOW)
+{
+ lhif_dl_re_inband_data_t __data;
+ ((lhif_dl_re_inband_data_t *)(&__data))->count_l = COUNT_L;
+ ((lhif_dl_re_inband_data_t *)(&__data))->channel_id = CH_ID;
+ ((lhif_dl_re_inband_data_t *)(&__data))->net_type = NET_TYPE;
+ ((lhif_dl_re_inband_data_t *)(&__data))->reserved1 = 0;
+ ((lhif_dl_re_inband_data_t *)(&__data))->reorder = 0;
+ ((lhif_dl_re_inband_data_t *)(&__data))->qid = 0x4;
+ ((lhif_dl_re_inband_data_t *)(&__data))->reserved2 = 0;
+ ((lhif_dl_re_inband_data_t *)(&__data))->flow = FLOW;
+ ((lhif_dl_re_inband_data_t *)(&__data))->reserved3 = 0;
+ ((lhif_dl_re_inband_data_t *)(&__data))->cmd = 0;
+ ((lhif_dl_re_inband_data_t *)(&__data))->reserved4 = 0;
+
+ return __data;
+}
+void lhif_drv_data_write_dl_ib_nr_desc(void *desc_ptr,kal_uint8 c_bit,kal_uint16 count_l);
+void lhif_drv_data_write_dl_ib_nr_pcie_desc(void *desc_ptr,kal_uint8 c_bit,kal_uint16 count_l,kal_uint16 ch_id,kal_uint8 net_type,kal_uint8 flow);
+void lhif_drv_data_write_dl_ib_only_nr_desc(void *desc_ptr,kal_uint8 rb_idx, kal_uint8 drop, kal_uint16 pkt_num, kal_uint16 pit_idx);
+//kal_bool lhif_drv_data_add_nr_desc(lhif_nr_dl_dpmaif_meta_t *p_meta);
+kal_bool lhif_drv_data_add_nr_pcie(lhif_nr_dl_dpmaif_meta_t *p_meta , kal_uint8 drop);
+kal_bool lhif_drv_data_add_nr_desc_pcie(lhif_nr_dl_pcie_meta_t *p_meta);
+kal_bool lhif_drv_data_add_nr_desc(kal_uint8 rb_idx, kal_uint8 drop, kal_uint16 pkt_num, kal_uint16 pit_idx);
+void lhif_drv_data_rel_nr_pcie_meta(void);
+void lhif_drv_data_rel_nr_ipf_no_meta(void);
+void lhif_drv_data_rel_nr_ipf(kal_uint16 start_idx,kal_uint16 end_idx);
+void lhif_drv_data_reorder_full_handler(void);
+kal_uint16 lhif_drv_data_chk_vrb_cnt(kal_uint16 rd_idx, kal_uint16 wr_idx);
+kal_bool lhif_drv_data_chk_drop_vrb(void);
+void lhif_drv_data_set_dpmaif_ultra(kal_bool en);
+
+
+kal_bool lhif_drv_data_add_nr_ipf(lhif_nr_dl_dpmaif_meta_t *p_meta , kal_uint8 drop);
+kal_bool lhif_drv_data_alloc_sw_meta_ipf(kal_uint16 real_meta_idx);
+void lhif_drv_data_rel_sw_meta_ipf(kal_uint32 rel_entry_num);
+void lhif_drv_data_rel_meta_ipf(kal_uint16 real_meta_idx);
+void lhif_drv_data_rel_meta_ipf_all(void);
+kal_bool lhif_drv_data_query_sw_meta_ipf(kal_uint16 *r_idx,kal_uint16 *w_idx);
+
+#if defined(ATEST_DRV_ENABLE) && !defined(ATEST_DRV_LHIF)
+typedef kal_bool (*lhif_vrb_drop_cb_t)(kal_uint16, kal_uint16);
+void lhif_dev_drop_init(lhif_vrb_drop_cb_t drop_cb);
+#endif
+
+#endif /*_LHIF_GEN97_HW_*/
+
+#endif //_LHIF_DESC_DEV_H
diff --git a/mcu/interface/driver/hif/hif_mhccifdev/mhccif_if.h b/mcu/interface/driver/hif/hif_mhccifdev/mhccif_if.h
new file mode 100644
index 0000000..07e2e8d
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_mhccifdev/mhccif_if.h
@@ -0,0 +1,81 @@
+#ifndef __MHCCIF_IF_H__
+#define __MHCCIF_IF_H__
+#include "reg_base.h"
+#include "devdrv_ls.h"
+kal_bool mhccif_init(void);
+kal_bool DEVDRV_LS_DRAM_EX_ROCODE hifmhccif_except_sw_int_poll(kal_uint8 sw_int_no, kal_uint32 timeout_ms);
+kal_int32 mhccif_except_set(kal_uint32 ch);
+kal_uint32 mhccif_valid_state(void) ;
+void mhccif_except_ack(kal_uint32 ch);
+kal_uint32 mhccif_read_ep_reg(kal_uint8 ch);
+kal_uint32 mhccif_read_rc_reg(kal_uint8 ch);
+void mhccif_write_ep_reg(kal_uint8 ch,kal_uint32 val);
+void mhccif_write_rc_reg(kal_uint8 ch,kal_uint32 val);
+void mhccif_register_hisr_callback(kal_uint32 event_ch, void(*reg_callback)(void* params));
+void mhccif_clr_mdmcu_mask(kal_uint32 ch);
+void mhccif_set_mdmcu_mask(kal_uint32 ch);
+void mhccif_ack_channel(kal_uint32 ch);
+void mhccif_set_channel(kal_uint32 ch);
+kal_uint32 mhccif_get_int_sts(void);
+
+/**************************************************
+* MHCCIF Channel Number, Host to Device
+***************************************************/
+/*Host to Device*/
+#define MHCCIF_H2D_INT_except_ack (1)
+#define MHCCIF_H2D_INT_except_clearQ_ack (2)
+//PCIE/PM
+#define MHCCIF_H2D_INT_PCIE_DS_LOCK (3)
+#define MHCCIF_H2D_RESERVED_FOR_CLDMA0 (4)
+#define MHCCIF_H2D_RESERVED_FOR_CLDMA1 (5)
+#define MHCCIF_H2D_RESERVED_FOR_CLDMA3 (6)
+#define MHCCIF_H2D_RESERVED_FOR_CLDMA2 (7)
+#define MHCCIF_H2D_RESERVED_FOR_DPMAIF (8)
+
+#define MHCCIF_H2D_INT_PCIE_PM_SUSPEND_REQ (9)
+#define MHCCIF_H2D_INT_PCIE_PM_RESUME_REQ (10)
+
+#define MHCCIF_H2D_INT_PCIE_PM_SUSPEND_REQ_AP (11)
+#define MHCCIF_H2D_INT_PCIE_PM_RESUME_REQ_AP (12)
+#define MHCCIF_H2D_INT_DEVICE_RESET (13)
+
+
+/**************************************************
+* MHCCIF Channel Number, Device to Host
+***************************************************/
+#define MHCCIF_D2H_INT_PCIE_DS_LOCK_ACK (0)
+
+#define MHCCIF_D2H_INT_except_init (1)
+#define MHCCIF_D2H_INT_except_init_done (2)
+#define MHCCIF_D2H_INT_except_clearQ_done (3)
+#define MHCCIF_D2H_INT_except_allQ_reset (4)
+#define MHCCIF_BOOT_FLOW_SYNC (5)
+//PCIE/PM
+#define MHCCIF_D2H_RESERVED_FOR_CLDMA0 (6)
+#define MHCCIF_D2H_RESERVED_FOR_CLDMA1 (7)
+#define MHCCIF_D2H_RESERVED_FOR_CLDMA3 (8)
+#define MHCCIF_D2H_RESERVED_FOR_CLDMA2 (9)
+#define MHCCIF_D2H_RESERVED_FOR_DPMAIF (10)
+#define MHCCIF_D2H_INT_PCIE_PM_SUSPEND_ACK (11)
+#define MHCCIF_D2H_INT_PCIE_PM_RESUME_ACK (12)
+#define MHCCIF_D2H_INT_PCIE_PM_SUSPEND_ACK_AP (13)
+#define MHCCIF_D2H_INT_PCIE_PM_RESUME_ACK_AP (14)
+#define MHCCIF_D2H_INT_ASYNC_HS_NOTIFY_SAP (15)
+#define MHCCIF_D2H_INT_ASYNC_HS_NOTIFY_MD (16)
+
+/**************************************************
+* MHCCIF Spare Register Number, Host to Device
+***************************************************/
+#define MHCCIF_H2D_REG_EXCEPTION_MSG (0)
+#define MHCCIF_H2D_REG_PCIE_PM_MSG (1)
+#define MHCCIF_H2D_REG_PCIE_PM_MSG_AP (2)
+#define MHCCIF_H2D_REG_PCIE_PM_COUNTER (3)
+/**************************************************
+* MHCCIF Spare Register Number, Device to Host
+***************************************************/
+#define MHCCIF_D2H_REG_PCIE_PM_MSG (1)
+#define MHCCIF_D2H_REG_PCIE_PM_MSG_AP (2)
+
+
+
+#endif /*__MHCCIF_H__*/
diff --git a/mcu/interface/driver/hif/hif_pccif4dev/pccif4_if.h b/mcu/interface/driver/hif/hif_pccif4dev/pccif4_if.h
new file mode 100644
index 0000000..46c4eed
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_pccif4dev/pccif4_if.h
@@ -0,0 +1,96 @@
+/*****************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2012
+ *
+ * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ *****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * pccif4_if.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ *
+ ****************************************************************************/
+#ifndef __PCCIF4_IF__
+#define __PCCIF4_IF__
+
+#include "reg_base.h"
+#include "devdrv_ls.h"
+
+//#define PCCIF0_IRQ1_CHANNEL_BASE (15)
+//#define H2D_FORCE_ASSERT_INT (PCCIF0_IRQ1_CHANNEL_BASE+3)
+
+
+typedef void (*PCCIF4_IRQ_CB)(void);
+
+void pccif4_init(void);
+kal_int32 pccif4_set(kal_uint32 ch);
+kal_uint32 pccif4_valid_state(void);
+kal_uint32 pccif4_start_state(void);
+void pccif4_ack(kal_uint32 ch);
+void pccif4_irq0_mask(void);
+void pccif4_irq0_unmask(void);
+void pccif4_irq1_mask(void);
+void pccif4_irq1_unmask(void);
+void pccif4_isr_init(void);
+
+//dummy register for RX sttatus flag
+/* APPCCIF4_DUMMY1 */
+#define AP_PCCIF4_PWR_ON_OFFSET 0
+#define AP_PCCIF4_SW_READY_OFFSET 1
+/* MDPCCIF4_DUMMY1 */
+#define MD_PCCIF4_PWR_ON_OFFSET 0 //controlled by AP CCCI
+#define MD_PCCIF4_SW_READY_OFFSET 1
+
+void pccif4_dummy1_set(kal_uint32 value);
+kal_uint32 pccif4_dummy1_get(void);
+kal_uint32 pccif4_ap_dummy1_get(void);
+
+void pccif4_register_irq0_callback(PCCIF4_IRQ_CB func_cb_ptr);
+
+//void DEVDRV_LS_DRAM_EX_ROCODE hifpccif0_except_delay_us(kal_uint32 delay_us);
+//kal_bool DEVDRV_LS_DRAM_EX_ROCODE hifpccif0_except_sw_int_poll(kal_uint8 sw_int_no, kal_uint32 timeout_ms);
+
+#endif // __PCCIF_IF__
diff --git a/mcu/interface/driver/hif/hif_pccif5dev/pccif5_if.h b/mcu/interface/driver/hif/hif_pccif5dev/pccif5_if.h
new file mode 100644
index 0000000..0683990
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_pccif5dev/pccif5_if.h
@@ -0,0 +1,96 @@
+/*****************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2012
+ *
+ * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ *****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * pccif5_if.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ *
+ ****************************************************************************/
+#ifndef __PCCIF5_IF__
+#define __PCCIF5_IF__
+
+#include "reg_base.h"
+#include "devdrv_ls.h"
+
+//#define PCCIF0_IRQ1_CHANNEL_BASE (15)
+//#define H2D_FORCE_ASSERT_INT (PCCIF0_IRQ1_CHANNEL_BASE+3)
+
+
+typedef void (*PCCIF5_IRQ_CB)(void);
+
+void pccif5_init(void);
+kal_int32 pccif5_set(kal_uint32 ch);
+kal_uint32 pccif5_valid_state(void);
+kal_uint32 pccif5_start_state(void);
+void pccif5_ack(kal_uint32 ch);
+void pccif5_irq0_mask(void);
+void pccif5_irq0_unmask(void);
+void pccif5_irq1_mask(void);
+void pccif5_irq1_unmask(void);
+void pccif5_isr_init(void);
+
+//dummy register for RX sttatus flag
+/* APPCCIF5_DUMMY1 */
+#define AP_PCCIF5_PWR_ON_OFFSET 0
+#define AP_PCCIF5_SW_READY_OFFSET 1
+/* MDPCCIF5_DUMMY1 */
+#define MD_PCCIF5_PWR_ON_OFFSET 0 //controlled by AP CCCI
+#define MD_PCCIF5_SW_READY_OFFSET 1
+
+void pccif5_dummy1_set(kal_uint32 value);
+kal_uint32 pccif5_dummy1_get(void);
+kal_uint32 pccif5_ap_dummy1_get(void);
+
+void pccif5_register_irq0_callback(PCCIF5_IRQ_CB func_cb_ptr);
+
+//void DEVDRV_LS_DRAM_EX_ROCODE hifpccif0_except_delay_us(kal_uint32 delay_us);
+//kal_bool DEVDRV_LS_DRAM_EX_ROCODE hifpccif0_except_sw_int_poll(kal_uint8 sw_int_no, kal_uint32 timeout_ms);
+
+#endif // __PCCIF_IF__
diff --git a/mcu/interface/driver/hif/hif_pccifdev/pccif_if.h b/mcu/interface/driver/hif/hif_pccifdev/pccif_if.h
new file mode 100644
index 0000000..e09e410
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_pccifdev/pccif_if.h
@@ -0,0 +1,128 @@
+/*****************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2012
+ *
+ * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ *****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * pccif_if.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ *
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 07 03 2018 alva.li
+ * [MOLY00336614] [Gen97] add PCCIF sAP exception channel
+ * add sAP exception to CCIF exception channel
+ *
+ * 05 10 2017 alva.li
+ * [MOLY00248273] [UMOLYA] handle possible deadlock in exception flow
+ *
+ * update pccif driver for exception flow
+ *
+ * 04 19 2017 alva.li
+ * [MOLY00243355] [UMOLYA][PCCIF]build warning removal
+ * update for build warning
+ *
+ *
+ ****************************************************************************/
+#ifndef __PCCIF_IF__
+#define __PCCIF_IF__
+
+#include "reg_base.h"
+#include "devdrv_ls.h"
+
+#define PCCIF0_IRQ1_CHANNEL_BASE (15)
+#define H2D_FORCE_ASSERT_INT (PCCIF0_IRQ1_CHANNEL_BASE+3)
+#define H2D_RMPU_FATAL_INT (PCCIF0_IRQ1_CHANNEL_BASE+4)
+#define H2D_WAKEUP_INT (PCCIF0_IRQ1_CHANNEL_BASE+5)
+#define D2H_WAKEUP_INT (PCCIF0_IRQ1_CHANNEL_BASE+5)
+#define D2H_SEQ_ERR_INT (PCCIF0_IRQ1_CHANNEL_BASE+6)
+#define H2D_SEQ_ERR_INT (PCCIF0_IRQ1_CHANNEL_BASE+6)
+#define H2D_SAP_EXCP_INT (PCCIF0_IRQ1_CHANNEL_BASE+7)
+
+#define MDCCIF_DATA_SIZE 512
+
+/* SRAM, FIXME: DL 0~247, UL 248~495, last 16 byte for boot up trace */
+#if defined(BASE_MADDR_PCCIF0_MD)
+#define MDPCCIF0_TXCHDATA (BASE_MADDR_PCCIF0_MD + 0x0100)
+#define MDPCCIF0_RXCHDATA (BASE_MADDR_PCCIF0_MD + 0x01F0)
+#else
+ #error "no ccif base define!!"
+#endif
+#define MDPCCIF0_TXRXCHDATA_SIZE 238
+
+typedef void (*AP_CCCI_ASSERT_CB)(void);
+
+void pccif0_init(void);
+kal_int32 pccif0_set(kal_uint32 ch);
+kal_int32 pccif0_except_set(kal_uint32 ch);
+kal_uint32 pccif0_valid_state(void);
+kal_uint32 pccif0_except_valid_state(void);
+kal_uint32 pccif0_start_state(void);
+kal_uint32 pccif0_get_data_addr(void);
+void pccif0_write_seq(kal_uint32 seq);
+void pccif0_ack(kal_uint32 ch);
+void pccif0_except_ack(kal_uint32 ch);
+void pccif0_ccb_ack(void);
+void pccif0_irq0_mask(void);
+void pccif0_irq0_unmask(void);
+void pccif0_irq1_mask(void);
+void pccif0_irq1_unmask(void);
+void pccif0_ccb_mask_irq(void);
+void pccif0_ccb_unmask_irq(void);
+void pccif0_isr_init(void);
+void ccism_log_tx(kal_uint32 chnum);
+void ccism_log_rx(kal_uint32 chnum);
+
+// for CCCI debug with sequence error
+void pccif_seq_err_D2H_int();
+void pccif_write_seq(kal_uint32 seq);
+void pccif_register_seq_err_assert_callback(AP_CCCI_ASSERT_CB func_cb_ptr);
+
+void DEVDRV_LS_DRAM_EX_ROCODE hifpccif0_except_delay_us(kal_uint32 delay_us);
+kal_bool DEVDRV_LS_DRAM_EX_ROCODE hifpccif0_except_sw_int_poll(kal_uint8 sw_int_no, kal_uint32 timeout_ms);
+
+#endif // __PCCIF_IF__
diff --git a/mcu/interface/driver/hif/hif_pciedev/hif_pcie.h b/mcu/interface/driver/hif/hif_pciedev/hif_pcie.h
new file mode 100644
index 0000000..4369b77
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_pciedev/hif_pcie.h
@@ -0,0 +1,281 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hif_pcie.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * driver header of pcie device IP
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 10 25 2021 elliott.chiang
+ * [MOLY00672418] support for MBIM_CID_MS_WAKE_REASON is needed
+ * MBIM WAKE REASON
+ *
+ * 04 13 2021 bernie.chang
+ * [MOLY00626658] [WIN] M80 shouldn't send host a LTR value greater than the LTR Max Latency register setting
+ *
+ * Check LTR in config space before set LTR value
+ *
+ * 11 11 2020 cindy.tu
+ * [MOLY00520457] [PCIE][Colgin] PCIE driver
+ *
+ * Sync to MD700.
+ *
+ * 08 06 2020 cindy.tu
+ * [MOLY00520457] [PCIE][Colgin] PCIE driver
+ * LTR API.
+ *
+ * 08 06 2020 cindy.tu
+ * [MOLY00520457] [PCIE][Colgin] PCIE driver
+ * PERST detection with EINT.
+ *
+ * 08 04 2020 cindy.tu
+ * [MOLY00520457] [PCIE][Colgin] PCIE driver
+ *
+ * Merge PCIE driver to T700 branch
+ *
+ * 07 06 2020 cindy.tu
+ * [MOLY00520457] [PCIE][Colgin] PCIE driver
+ *
+ * Sync PCIE to MT6880 MP.
+ *
+ * 06 05 2020 cindy.tu
+ * [MOLY00520457] [PCIE][Colgin] PCIE driver
+ *
+ * Sync PCIE wake service for AP
+ *
+ * 05 05 2020 cindy.tu
+ * [MOLY00520457] [PCIE][Colgin] PCIE driver
+ *
+ * 04 30 2020 cindy.tu
+ * [MOLY00518788] [PCIE][Mercury] PCIE link API
+ * EWSP0000108141
+ *
+ * 04 16 2020 cindy.tu
+ * [MOLY00503259] [PCIE][M70] PCIE link API
+ *
+ * [PCIE] Integrate with MHCCIF and add test cases.
+ *
+ * 04 10 2020 cindy.tu
+ * [MOLY00503259] [PCIE][M70] PCIE link API
+ * Rename wake API and do not unmask PCIE IRQ.
+ *
+ * 04 10 2020 cindy.tu
+ * [MOLY00503259] [PCIE][M70] PCIE link API
+ * Fix typo.
+ *
+ * 04 09 2020 cindy.tu
+ * [MOLY00503259] [PCIE][M70] PCIE link API
+ * PCIE prototype ready.
+ *
+ * 04 07 2020 cindy.tu
+ * [MOLY00503259] [PCIE][M70] PCIE link API
+ * Merge PCIE rearch.
+ *
+ *
+ ****************************************************************************/
+#ifndef __HIF_PCIE_H__
+#define __HIF_PCIE_H__
+
+#define LTR_HIGH_TPUT_VALUE_MS 1
+#define LTR_LOW_TPUT_VALUE_MS 10
+
+typedef enum _pcie_err{
+ PCIE_ERR_NONE = 0,
+ PCIE_ERR_LTR_SCALE,
+ PCIE_ERR_LTR_LATENCY,
+ PCIE_ERR_LTR_LESS_500US,
+ PCIE_ERR_LTR_NOT_IN_L0,
+}pcie_err_e;
+
+typedef enum _hifpcie_user{
+ HIFPCIE_USER_DPMAIF = 0,
+ HIFPCIE_USER_MDCLDMA,
+ HIFPCIE_USER_MD_L5,
+ HIFPCIE_USER_MD_END,
+ HIFPCIE_USER_AP = HIFPCIE_USER_MD_END,
+ HIFPCIE_USER_END
+}hifpcie_user_e;
+
+typedef enum _hifpcie_state {
+ HIFPCIE_STATE_MIN = 0,
+ HIFPCIE_STATE_PWROFF,
+ //HIFPCIE_STATE_PWRON,
+ //HIFPCIE_STATE_ATTACHED,
+ //HIFPCIE_STATE_NEW_RST,
+ //HIFPCIE_STATE_DEFAULT,
+ //HIFPCIE_STATE_ADDR,
+ //HIFPCIE_STATE_CONFIG,
+ //HIFPCIE_STATE_SUSPENDED,
+ //HIFPCIE_STATE_RESUME,
+ HIFPCIE_STATE_LPM_D0,
+ HIFPCIE_STATE_LPM_D1,
+ HIFPCIE_STATE_LPM_D2,
+ HIFPCIE_STATE_LPM_D3,
+ HIFPCIE_STATE_MAX,
+} hifpcie_state_e;
+
+/*!
+ * @brief used to record the bootup information for power saving power down or watchdog reset
+ */
+typedef enum _hifpcie_boot_type {
+ HIFPCIE_BOOT_PWRON_RST = 0,
+ HIFPCIE_BOOT_SUSPEND,
+ HIFPCIE_BOOT_UNKNOWN = 255,
+} hifpcie_boot_type_e;
+
+/*!
+ * @brief used to record the bootup information for power saving power down or watchdog reset
+ */
+typedef struct _hifpcie_boot_info {
+ hifpcie_boot_type_e boot_type;
+ kal_uint8 pcie_speed;
+ kal_uint8 pcie_addr;
+ kal_uint8 pcie_config_val;
+} hifpcie_boot_info_t;
+
+/*!
+ * @brief hifusb_hw_info_t is used to record the USB IP information
+ */
+typedef struct _hifpcie_hw_info{
+
+ kal_uint32 pcie_hw_datecode;
+
+ kal_uint16 pcie_hw_vendor_id;
+
+ kal_uint16 pcie_hw_device_id;
+
+ kal_uint8 pcie_hw_revsion_id;
+
+ kal_uint32 pcie_hw_classcode;
+
+ kal_uint16 pcie_hw_sys_vendor_id;
+
+ kal_uint16 pcie_hw_sys_device_id;
+
+ kal_uint32 pcie_hw_sku[2];
+
+} hifpcie_hw_info_t;
+
+typedef struct _hifpcie_property {
+
+
+
+} hifpcie_property_t;
+
+typedef int (*hifpcie_intr_callback)(void *param);
+typedef int (*hifpcie_suspend_callback)(void *param, void *user_param);
+typedef int (*hifpcie_resume_callback)(void *param, void *user_param);
+
+/*!
+ * @brief PCIE LTR setting
+ * @param
+ * @return
+ */
+kal_uint32 hifpcie_update_ltr(kal_bool required, kal_uint16 latency_ms, kal_uint32 timer_cnt, kal_bool force);
+
+/*!
+ * @brief Trigger PCIE remote wake
+ * @param
+ * @return
+ */
+void hifpcie_remote_wake(hifpcie_user_e user);
+
+/*!
+ * @brief Exception init for PCIE
+ * @param
+ * @return
+ */
+kal_bool hifpcie_exception_init(void);
+
+/*!
+ * @brief Register pcie suspend callback.
+ * @param
+ * @return
+ */
+kal_bool hifpcie_register_suspend_callback(hifpcie_user_e user, hifpcie_suspend_callback callback, void *param);
+
+/*!
+ * @brief Register pcie suspend callback.
+ * @param
+ * @return
+ */
+kal_bool hifpcie_register_resume_callback(hifpcie_user_e user, hifpcie_suspend_callback callback, void *param);
+
+/*!
+ * @brief Register pcie user suspend ack API.
+ * @param
+ * @return
+ */
+void hifpcie_suspend_user_ack(hifpcie_user_e user);
+
+/*!
+ * @brief Register pcie user suspend ack API.
+ * @param
+ * @return
+ */
+void hifpcie_resume_user_ack(hifpcie_user_e user);
+
+/*!
+ * @brief initialize pcie hif driver
+ * @param
+ * @return KAL_TRUE if initial success ,
+ KAL_FALSE if initial failure.
+ */
+kal_bool hifpcie_init(void);
+
+/*!
+ * @brief initialize pcie hif driver (after eint init)
+ * @param
+ * @return KAL_TRUE if initial success ,
+ KAL_FALSE if initial failure.
+ */
+kal_bool hifpcie_init_2(void);
+
+#endif
diff --git a/mcu/interface/driver/hif/hif_sdiodev/hif_sdio.h b/mcu/interface/driver/hif/hif_sdiodev/hif_sdio.h
new file mode 100644
index 0000000..ab77e88
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_sdiodev/hif_sdio.h
@@ -0,0 +1,347 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hif_sdio.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * driver header of SDIO device IP
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 12 03 2013 wei-de.chen
+ * [MOLY00047337] Add reset signal at SDIO SLT load
+ * Add flag to ENABLE_FORMAL_SLEEP_SDIO
+ *
+ * 10 21 2013 wei-de.chen
+ * [MOLY00042735] Sleep flow code submit of SDIO
+ * SDIO sleep related code submit
+ *
+ * 10 06 2013 wei-de.chen
+ * [MOLY00040338] Add some normal parameter initial at exception iinit stage
+ * Add normal parameter init in extcept init API
+ *
+ * 02 04 2013 wei-de.chen
+ * [MOLY00009921] Rename project name to MT6290
+ * Change project name to MT6290
+ *
+ * 01 30 2013 wei-de.chen
+ * [MOLY00006983] Driver code development of MT6290
+ * modify the way of setting int mask to reduce times of DL int
+ * Add a API of check UL done to reduce MIPS
+ *
+ * 01 07 2013 wei-de.chen
+ * [MOLY00008347] [MT6290] [CCCI] CCCI re-Architecture
+ * update hifsdio_init_phase2 & API in except
+ ****************************************************************************/
+
+
+#ifndef __HIF_SDIO_H__
+#define __HIF_SDIO_H__
+
+#include "kal_public_api.h"
+
+#define HIFSDIO_MAX_ULQ_NUM 7
+#define HIFSDIO_MAX_DLQ_NUM 4
+
+#ifdef MTK_SLEEP_ENABLE
+#define ENABLE_FORMAL_SLEEP_SDIO
+#endif
+
+#define SDIOReg_Write8(addr,data) \
+ (*((volatile kal_uint8 *)(addr))) = data
+
+#define SDIOReg_Write16(addr,data) \
+ (*((volatile kal_uint16 *)(addr))) = data
+
+#define SDIOReg_Write32(addr,data) \
+ (*((volatile kal_uint32 *)(addr))) = data
+
+#define SDIOReg_Read8(addr) \
+ *(volatile kal_uint8 *)(addr)
+
+#define SDIOReg_Read16(addr) \
+ *(volatile kal_uint16 *)(addr)
+
+#define SDIOReg_Read32(addr) \
+ *(volatile kal_uint32 *)(addr)
+
+
+/*!
+ * @brief hifsdio_isr_mask is used to record the interrupt enable bitmap mask
+ */
+typedef struct _hifsdio_isr_en_mask{
+ kal_uint32 GLO_INTR_En_Msk;
+ kal_uint16 SW_INTR_En_Msk;
+ kal_uint16 FW_INTR_En_Msk;
+ kal_uint32 UL0_INTR_En_Msk;
+ kal_uint32 DL0_INTR_En_Msk;
+ kal_uint32 DL1_INTR_En_Msk;
+
+} hifsdio_isr_en_mask_t;
+
+
+typedef struct _hifsdio_isr_status{
+ kal_uint32 GLO_INTR_Status;
+ kal_uint16 SW_INTR_Status;
+ kal_uint16 FW_INTR_Status;
+ kal_uint32 UL0_INTR_Status;
+ kal_uint32 DL0_INTR_Status;
+ kal_uint32 DL1_INTR_Status;
+
+} hifsdio_isr_status_t;
+
+
+typedef enum _hifsdio_isr_mask_code{
+ GLO_INTR_Msk = 0,
+ SW_INTR_Msk,
+ FW_INTR_Msk,
+ UL0_INTR_Set_Msk,
+ UL0_INTR_Clr_Msk,
+ DL0_INTR_Msk,
+ DL1_INTR_Msk,
+ SET_ALL_Msk = 0xFF,
+}hifsdio_isr_mask_e;
+
+
+typedef struct _hifsdio_queue_config {
+ /*!
+ * @brief the head pointer of the GPD which preserve in FW, not hang on the QMU HW yet.
+ */
+ void *head_ptr_preserve;
+
+ /*!
+ * @brief the tail pointer of the GPD which preserve in FW, not hang on the QMU HW yet.
+ */
+ void *tail_ptr_preserve;
+
+ /*!
+ * @brief the total number of GPDs which preserve in FW, not hang on the QMU HW yet.
+ */
+ kal_uint32 num_preserve;
+
+} hifsdio_queue_config_t;
+
+
+
+typedef struct _hifsdio_property {
+
+ /*!
+ * @brief total UL QMU queues requested to configure
+ */
+ kal_uint8 ulq_num;
+ /*!
+ * @brief total DL QMU queues requested to configure
+ */
+ kal_uint8 dlq_num;
+ /*!
+ * @brief reserve for 4 bytes alignment
+ */
+ kal_uint8 reserve[2];
+
+ /*!
+ * @brief set the checksum function of QMU is enable or not
+ */
+ kal_bool checksum_en;
+
+ /*!
+ * @brief set the checksum bytes, KAL_FALSE = use 12bytes checksum
+ * Notice : the SDIO IP only has 16bytes checksum now, 12bytes ability will be added in future.
+ */
+ kal_bool checksum_16bytes;
+
+ /*!
+ * @brief set whether IOC function of DL queue is diable or not
+ * (if disable, the interrupt will occurs when each GPD is transfered done no matter the IOC bit of GPD)
+ */
+ kal_bool dl_ioc_dis[HIFSDIO_MAX_DLQ_NUM];
+
+
+ /*!
+ * @brief sdio_isr_cb_func is the call back function for ISR
+ */
+ void (*sdio_isr_cb_func)(hifsdio_isr_status_t sdio_int_status);
+
+} hifsdio_property_t;
+
+
+
+
+/*!
+ * @brief initialize sdio hif driver
+ * @param
+ * @return KAL_TRUE if initial success ,
+ KAL_FALSE if initial failure.
+ */
+kal_bool hifsdio_init();
+
+/*!
+ * @brief initialize sdio hif driver phase2, which related to qbm & ISR
+ * @param
+ * @return KAL_TRUE if initial success ,
+ KAL_FALSE if initial failure.
+ */
+kal_bool hifsdio_init_phase2();
+
+/*!
+ * @brief ask sdio hif driver to set this property
+ * @param property the property sdiocore will set
+ * @return KAL_TRUE if the property can be satisfied, otherwise KAL_FALSE
+ */
+kal_bool hifsdio_set_property(hifsdio_property_t* p_sdio_property);
+
+
+/*!
+ * @brief shutdown sdio hif driver, detach LISR/HISR ,
+ * need to re-initial sdio driver after shut down
+ */
+void hifsdio_shutdown();
+
+/*!
+ * @brief record and log the sdio ip hardware information.
+ * @param p_hw_inof , used to record the hw info
+ */
+// void hifsdio_get_hw_info(hifsdio_hw_info_t* p_hw_info);
+
+/*!
+ * @brief set D2H interrupt (SW interrupt to host)
+ * @param set_fw_own_back , if want to set fw own back int
+ * @param sw_int_num , the number of the sw interrupt which want to be set
+ * (if want to set sw int, the set_fw_own_back param must be KAL_FALSE)
+ */
+void hifsdio_set_D2H_int(kal_bool set_fw_own_back, kal_uint8 sw_int_num);
+
+
+/*!
+ * @brief read H2D mailbox
+ * @param H2D_mb_num , the mailbox number which want to read
+ * @param mb_content , the data pointer of read mailbox value
+ */
+void hifsdio_read_mb(kal_uint8 H2D_mb_num, kal_uint32 *mb_content);
+
+
+/*!
+ * @brief read H2D mailbox
+ * @param D2H_mb_num , the mailbox number which want to write
+ * @param mb_content , the data pointer of read mailbox value
+ */
+void hifsdio_write_mb(kal_uint8 D2H_mb_num, kal_uint32 *mb_content);
+
+/*!
+ * @brief check whether it back to FW site.
+ * @return KAL_TRUE if the ownership is back to FW site.
+ */
+kal_bool hifsdio_check_fw_own(void);
+
+/*!
+ * @brief give the ownership to host driver
+ */
+void hifsdio_give_fw_own(void);
+
+
+/*!
+ * @brief enable sleep function when host give own back
+ */
+void hifsdio_enable_sleep(void);
+
+
+/*!
+ * @brief read the FW side interrupt mask value now.
+ * @return the interrupt mask setting now.
+ */
+hifsdio_isr_en_mask_t hifsdio_read_int_mask();
+
+
+/*!
+ * @brief set the FW side interrupt mask of SDIO
+ * @param p_isr_mask , the pointer of the mask value we want to set
+ * @param mask_set , select which interrupt mask we want to set
+ */
+void hifsdio_set_int_mask(hifsdio_isr_en_mask_t *p_isr_mask, hifsdio_isr_mask_e mask_set);
+
+
+/*!
+ * @brief to inform host that function is ready, so host can transfer normal data
+ * upper application can call this function after GPDs initial is complete.
+ */
+void hifsdio_set_func_ready();
+
+
+/*!
+ * @brief check whether UL que has new packet received.
+ * @return the UL que status in bitwise. 0x1 means only que0, 0x3 means que0 & que1 have new packet received.
+ */
+kal_uint8 hifsdio_check_UL_newpkt(void);
+
+
+/*!
+ * @brief check the initial phase now when exception happens at boot.
+ * @return 0 for SDIO has not init, 1 for phase1 init done, 2 for phase2 init done.
+ */
+kal_uint8 hifsdio_except_check_init_stage(void);
+
+
+/*!
+* @brief ask sdio hif driver to set STALL for specified queue
+* stop queue, flush fifo(?) , record current GPD pointer (not supported by HW now)
+* @param is_tx KAL_TRUE for tx (D2H), KAL_FALSE for rx(H2D)
+* @param nQueue Queue number in request command
+*/
+// TODO: has not implement, temprarily marked.
+//void hifsdio_set_stop(kal_bool is_tx, kal_uint8 nQueue);
+
+
+/*!
+* @brief ask sdio hif driver to recover for specified queue
+* restore queue, resume queue,
+* @param is_tx KAL_TRUE for tx (D2H), KAL_FALSE for rx(H2D)
+* @param nQueue Queue number in request command
+*/
+// TODO: has not implement, temprarily marked.
+//void hifsdio_set_recover(kal_bool is_tx ,kal_uint8 nQueue);
+
+#endif
diff --git a/mcu/interface/driver/hif/hif_sdiodev/hif_sdio_except.h b/mcu/interface/driver/hif/hif_sdiodev/hif_sdio_except.h
new file mode 100644
index 0000000..c0a8db6
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_sdiodev/hif_sdio_except.h
@@ -0,0 +1,118 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hif_sdio_except.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * This is the SDIO exception handler driver API head file.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 04 03 2013 vend_mick.lin
+ * [MOLY00011933] Develop SDIO driver
+ * MT6290 exception handle of SDIO driver
+ *
+ * 02 04 2013 wei-de.chen
+ * [MOLY00009921] Rename project name to MT6290
+ * Change project name to MT6290
+ *
+ * 01 07 2013 wei-de.chen
+ * [MOLY00008347] [MT6290] [CCCI] CCCI re-Architecture
+ * update hifsdio_init_phase2 & API in except
+ ****************************************************************************/
+
+#ifndef __HIF_SDIO_EXCEPT__
+#define __HIF_SDIO_EXCEPT__
+
+#include "hif_sdio.h"
+
+
+#define EXCEPT_SDIO_UL_QUE 0
+#define EXCEPT_SDIO_DL_QUE 0
+
+
+/*!
+ * @brief simply delay us function ,
+ * @param delay_us , delay period in us
+ * @return
+ */
+void hifsdio_except_delay_us(kal_uint32 delay_us);
+
+/*!
+ * @brief See the sw interrupt occurs or not in polling mode
+ * @param sw_int_no , the interrupt number form 0~15
+ * @param timeout_ms , the period of polling time
+ *
+ * @return KAL_TRUE : interrupt happen in the period,
+ * KAL_FALSE : interrupt not happen in the period.
+ */
+kal_bool hifsdio_except_sw_int_poll(kal_uint8 sw_int_no, kal_uint32 timeout_ms);
+
+/*!
+ * @brief simply send a GPD,
+ * @param queue_no , the queue number form 0~n
+ * @param send_gpd , the GPD which want to send
+ * @param timeout_ms , the time interval which host should read this packet
+ * If the user do not have timeout value, set it to 0.
+ * @return KAL_TRUE : send gpd success,
+ * KAL_FALSE : send gpd fail and should not call this API again.
+ */
+kal_bool hifsdio_simple_send_gpd(kal_uint8 queue_no, qbm_gpd* send_gpd, kal_uint32 timeout_ms);
+
+/*!
+ * @brief simply receive a GPD,
+ * @param queue_no , the queue number form 0~n
+ * @param send_gpd , the GPD which want to receive
+ * @param timeout_ms , the time interval which host should read this packet
+ * If the user do not have timeout value, set it to 0.
+ * @return KAL_TRUE : receive gpd success,
+ * KAL_FALSE : receive gpd fail and should not call this API again.
+ */
+kal_bool hifsdio_simple_receive_gpd(kal_uint8 queue_no, qbm_gpd* recv_gpd, kal_uint32 timeout_ms);
+
+#endif
diff --git a/mcu/interface/driver/hif/hif_secpccifdev/secpccif_def.h b/mcu/interface/driver/hif/hif_secpccifdev/secpccif_def.h
new file mode 100644
index 0000000..f3272a9
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_secpccifdev/secpccif_def.h
@@ -0,0 +1,45 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2015
+*
+*****************************************************************************/
+
+/*****************************************************************************
+*
+ * Filename:
+ * ---------
+ * secpccif_dev.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * Header file of SECPCCIF.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+*/
+
+#ifndef __SECPCCIF_DEF_H__
+#define __SECPCCIF_DEF_H__
+#include "reg_base.h"
+//#include "devdrv_ls.h"
+#define SECPCCIF_AMMS_SRAM_BASE_ADDR (BASE_MADDR_PCCIF1_MD + 0x100)
+#define SECPCCIF_AMMS_SRAM_MAX_SIZE 64
+#define SECPCCIF_SRAM_MAX_SIZE 256
+#define SECPCCIF_AMMS_CH0 0
+#define SECPCCIF_SRAM_ALIGN 4
+
+#endif
diff --git a/mcu/interface/driver/hif/hif_secpccifdev/secpccif_if.h b/mcu/interface/driver/hif/hif_secpccifdev/secpccif_if.h
new file mode 100644
index 0000000..39ada16
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_secpccifdev/secpccif_if.h
@@ -0,0 +1,60 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2015
+*
+*****************************************************************************/
+
+/*****************************************************************************
+*
+ * Filename:
+ * ---------
+ * secpccif_dev.h
+ *
+ * Project:
+ * --------
+ * UMOLY
+ *
+ * Description:
+ * ------------
+ * Header file of SECPCCIF.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+*/
+
+#ifndef __SECPCCIF_IF_H__
+#define __SECPCCIF_IF_H__
+#include "secpccif_def.h"
+
+typedef void (*secpccif_lisr_callback)(kal_uint32 ch_bitmap);
+
+
+/* interface API */
+void secpccif_irq0_mask(void);
+void secpccif_irq0_unmask(void);
+void secpccif_irq1_mask(void);
+void secpccif_irq1_unmask(void);
+kal_int32 secpccif_set(kal_uint32 ch);
+kal_uint32 secpccif_get_rx_ch(void);
+kal_uint32 secpccif_start_state(void);
+void secpccif_ack(kal_uint32 ch);
+kal_uint32 secpccif_AMMS_ch0_start_state(void);
+void secpccif_ack_AP(kal_uint32 ch);
+void secpccif_assert(void);
+void secpccif_init(void);
+void secpccif_irq0_lisr_callback_register(secpccif_lisr_callback cb);
+void secpccif_isr_init(void);
+void secpccif_read_sram(kal_uint32 dest_buf[], kal_uint32 sram_offset, kal_uint32 length);
+void secpccif_write_sram(kal_uint32 sram_offset, kal_uint32 src_buf[], kal_uint32 length);
+kal_uint32 secpccif_AMMS_ch0_rx_state(void);
+#endif
diff --git a/mcu/interface/driver/hif/hif_usbdev/hif_usb.h b/mcu/interface/driver/hif/hif_usbdev/hif_usb.h
new file mode 100644
index 0000000..0a323cd
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_usbdev/hif_usb.h
@@ -0,0 +1,870 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hif_usb.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * This is the USB driver API head file for both USB2.0/USB3.0.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 02 11 2022 yuhao.ye
+ * [MOLY00764790] [FBC][FM350-GL][NA][NA][USB]fm350 iot USB suspend and resume problem
+ *
+ * USB lowpower feature.
+ *
+ * 12 21 2021 yuhao.ye
+ * [MOLY00784691] [Colgin] MBIM over USB feature check in to MP branch
+ *
+ * MBIM over USB USB driver change.
+ *
+ * 12 15 2021 yuhao.ye
+ * [MOLY00784691] [Colgin] MBIM over USB feature check in to MP branch
+ * MBIM over USB USB driver checkin.
+ *
+ * 01 13 2021 zhiqiang.yu
+ * [MOLY00604973] [MT6880][Colgin][M.2][PV2][SQC][Data Performance][Colgin VTF/SF][Performance Test][SA][CMCC][Live][Hangzhou][Perf_5G_SA_PingLatency_001]Colgin ping latency lose REF Petrus-P (51.2 vs. 38.2 ms)
+ *
+ * .
+ *
+ * 11 16 2020 zhiqiang.yu
+ * [MOLY00595466] [Colgin]USBDRV Patchback From T700 Branch
+ *
+ * .
+ *
+ * 04 15 2019 zhiqiang.yu
+ * [MOLY00395020] [MT6297][Apollo][PreSQC][MP0.5][NVIOT][Nokia][Oulu][4G][3CC_10] After idle to connected mode always happen Assert fail: dpcopro_hisr.c 726 - (LISR)mml2_excep_lisr
+ *
+ * .
+ *
+ * 04 05 2017 gang.lei
+ * [MOLY00223010] UMOLYA USB Driver Checkin,md directtethering driver checkin
+ *
+ * 01 05 2017 gang.lei
+ * [MOLY00223010] UMOLYA USB Driver Checkin
+ * <saved by Perforce>
+ *
+ * 09 25 2014 ming.hsieh
+ * [MOLY00064103] UMOLY build error fix for hif driver
+ * . add enable SPD configure for each queue
+ * . fix driver test environment issue
+ *
+ * 08 22 2013 ming.hsieh
+ * [MOLY00033827] SSUSB suspend power save feature
+ * . add ip layer power save handle for upper layer driver use when gate all tx/rx
+ *
+ * 04 02 2013 ming.hsieh
+ * [MOLY00006951] MT7208 U2/U3 driver and test driver maintain
+ * . add call back handle for reset from suspend case without u3 ip link interrupt
+ *
+ * 03 01 2013 ming.hsieh
+ * [MOLY00006951] MT7208 U2/U3 driver and test driver maintain
+ * .add dev request U1/U2 and function remote wakeup notfiy for usb driver
+ *
+ * 02 04 2013 ming.hsieh
+ * [MOLY00006951] MT7208 U2/U3 driver and test driver maintain
+ * .modify project name as MT6290 and change all comment or log for new model name
+ *
+ * 11 20 2012 ming.hsieh
+ * [MOLY00006416] Update Driver for MT6290 FPGA 20121105_MD_a4_b12_cx
+ * .Merge MSBB latest code of USB2.0/USB3.0 to Moly trunk
+ ****************************************************************************/
+
+#ifndef __HIF_USB_H__
+#define __HIF_USB_H__
+
+#include "kal_public_api.h"
+
+/*!
+ * @brief define the USB EP0 standard field
+*/
+/* EP0 data stage direction */
+#define HIFUSB_DIR_MASK (0x80)
+#define HIFUSB_DIR_OUT (0)
+#define HIFUSB_DIR_IN (0x80)
+
+
+
+#define HIFUSB_SS_EP0_MPS (512)
+#define HIFUSB_HS_EP0_MPS (64)
+#define HIFUSB_FS_EP0_MPS (64)
+
+/*!
+ * @brief hifusb_notify_evt_e enumerate possible states of usb device
+ * @param HIFUSB_NOTIFY_EVT_MIN pseudo state
+ * @param HIFUSB_NOTIFY_EVT_ATTACHED attach to usb bus
+ * @param HIFUSB_NOTIFY_EVT_DETACHING start detaching from usb bus
+ * @param HIFUSB_NOTIFY_EVT_DETACHED detach from usb bus already
+ * @param HIFUSB_NOTIFY_EVT_SUSPENDING start suspending
+ * @param HIFUSB_NOTIFY_EVT_SUSPENDED suspend already
+ * @param HIFUSB_NOTIFY_EVT_RESUME recevie usb resume signal
+ * @param HIFUSB_NOTIFY_EVT_RESET recevie usb bus reset
+ * @param HIFUSB_NOTIFY_EVT_MAX pseudo state
+ */
+typedef enum _hifusb_notify_evt {
+ HIFUSB_NOTIFY_EVT_MIN = 0,
+ HIFUSB_NOTIFY_EVT_ATTACH = 1,
+ HIFUSB_NOTIFY_EVT_DETACH = 2,
+ HIFUSB_NOTIFY_EVT_SUSPEND = 3,
+ HIFUSB_NOTIFY_EVT_RESUME = 4,
+ HIFUSB_NOTIFY_EVT_RESET = 5,
+ HIFUSB_NOTIFY_EVT_WAKEUP = 6,
+ HIFUSB_NOTIFY_EVT_MAX = 7,
+} hifusb_notify_evt_e;
+
+
+/*!
+ * @brief hifusb_state_e enumerate possible states of usb device
+ * @param HIFUSB_STATE_MIN pseudo state
+ * @param HIFUSB_STATE_PWROFF USB initial state , before VBUS valid
+ * @param HIFUSB_STATE_PWRON after VBUS valid , before attach
+ * @param HIFUSB_STATE_ATTACHED after attach, before USB reset
+ * @param HIFUSB_STATE_DEFAULT after USB reset , this is the default normal state
+ * @param HIFUSB_STATE_ADDR after USB reset and set address
+ * @param HIFUSB_STATE_CONFIG after set address and set configure
+ * @param HIFUSB_STATE_SUSPENDED after default state and stay in suspend
+ * @param HIFUSB_STATE_RESUME when receive resume, return to default immediately
+ * @param HIFUSB_STATE_MAX psuduo state
+ */
+typedef enum _hifusb_state {
+ HIFUSB_STATE_MIN = 0,
+ HIFUSB_STATE_PWROFF,
+ HIFUSB_STATE_PWRON,
+ HIFUSB_STATE_ATTACHED,
+ HIFUSB_STATE_NEW_RST,
+ HIFUSB_STATE_DEFAULT,
+ HIFUSB_STATE_ADDR,
+ HIFUSB_STATE_CONFIG,
+ HIFUSB_STATE_SUSPENDED,
+ HIFUSB_STATE_RESUME,
+ HIFUSB_STATE_LPM_SUSPEND,
+ HIFUSB_STATE_MAX,
+} hifusb_state_e;
+
+/*!
+ * @brief hifusb_usb_speed_e enumerate possible speed of usb device
+ * @param HIFUSB_USB_SPEED_MIN pseudo speed
+ * @param HIFUSB_USB_SPEED_USB11 usb 1.1 full speed
+ * @param HIFUSB_USB_SPEED_USB20 usb 2.0 high speed
+ * @param HIFUSB_USB_SPEED_USB30 usb 3.0 super speed
+ * @param HIFUSB_USB_SPEED_MAX pseudo speed
+ */
+typedef enum hifusb_usb_speed {
+ HIFUSB_USB_SPEED_MIN = 0,
+ HIFUSB_USB_SPEED_USB11 = 1,
+ HIFUSB_USB_SPEED_USB20 = 2,
+ HIFUSB_USB_SPEED_USB30 = 3,
+ HIFUSB_USB_SPEED_MAX = 4,
+} hifusb_usb_speed_e;
+
+
+/*!
+ * @brief hifusb_request_owner_e enumerate all possible types of usb control
+ * request type
+ * @param HIFUSB_CONTROL_REQUEST_TYPE_MIN pseudo type
+ @param HIFUSB_CONTROL_REQUEST_TYPE_NODATA request no data
+ * @param HIFUSB_CONTROL_REQUEST_TYPE_SEND request to send, Device->Host
+ * @param HIFUSB_CONTROL_REQUEST_TYPE_RECEIVE request to receive, Host->Device
+ * @param HIFUSB_CONTROL_REQUEST_TYPE_STALL request to stall
+ * @param HIFUSB_CONTROL_REQUEST_TYPE_MAX pseudo type
+ */
+typedef enum _hifusb_control_request_type {
+ HIFUSB_CONTROL_REQUEST_TYPE_MIN = 0,
+ HIFUSB_CONTROL_REQUEST_TYPE_SEND = 1,
+ HIFUSB_CONTROL_REQUEST_TYPE_RECEIVE = 2,
+ HIFUSB_CONTROL_REQUEST_TYPE_STALL = 3,
+ HIFUSB_CONTROL_REQUEST_TYPE_MAX = 4,
+} hifusb_control_request_type_e;
+
+
+/*!
+ * @brief hifusb_hw_info_t is used to record the USB IP information
+ */
+typedef struct _hifusb_hw_info{
+ /*!
+ * @brief usb_hw_ver is the hardware USB IP version
+ */
+ kal_uint8 usb_hw_ver;
+ /*!
+ * @brief usb_hw_subver is the hardware USB IP subversion
+ */
+ kal_uint8 usb_hw_subver;
+ /*!
+ * @brief usb20_drc_ip_valid ,presents that USB2.0 Dual-Role IP valid
+ */
+ kal_bool usb20_drc_ip_valid;
+ /*!
+ * @brief usb30_dev_ip_valid ,presents that USB3.0 device IP valid
+ */
+ kal_bool usb30_dev_ip_valid;
+ /*!
+ * @brief usb_max_speed , presents that current max usb speed supported
+ */
+ hifusb_usb_speed_e usb_max_speed;
+ /*!
+ * @brief hub_hw_support presents that if the HUB supported in host mode
+ */
+ kal_bool hub_hw_support;
+ /*!
+ * @brief qmu_hw_support presents that if the QMU supported
+ */
+ kal_bool qmu_hw_support;
+ /*!
+ * @brief usb_hw_outepnum presents the hardware OUT EP numbers
+ */
+ kal_uint8 usb_hw_outepnum;
+ /*!
+ * @brief usb_hw_inepnum presents the hardware IN EP numbers
+ */
+ kal_uint8 usb_hw_inepnum;
+ /*!
+ * @brief usb_hw_dmachnum presents the hardware DMA channel numbers
+ */
+ kal_uint8 usb_hw_dmachnum;
+ /*!
+ * @brief usb_hw_fifo_sz presents the hardware dynamic fifo size in bytes
+ */
+ kal_uint32 usb_hw_fifo_sz;
+ /*!
+ * @brief usb_hw_fifo_sz presents the hardware dynamic fifo size in bytes
+ */
+ kal_uint32 usb_hw_ep0_fifo_sz;
+ /*!
+ * @brief usb_hw_fifo_sz presents the hardware dynamic fifo size in bytes
+ */
+ kal_uint32 usb_hw_in_fifo_sz;
+ /*!
+ * @brief usb_hw_fifo_sz presents the hardware dynamic fifo size in bytes
+ */
+ kal_uint32 usb_hw_out_fifo_sz;
+ /*!
+ * @brief usb_reg_config_data presents the hardware register of CONFIGDATA.
+ */
+ kal_uint16 usb_reg_config_data;
+} hifusb_hw_info_t;
+
+/*!
+ * @brief hifusb_setup_packet_t describe the detail field definition of
+ * control setup packet
+ */
+typedef struct _hifusb_setup_packet {
+ /*!
+ * @brief request type of setup packet
+ * Bit 7: Request direction
+ * (0=Host to device - Out, 1=Device to host - In)
+ * Bits 5-6: Request type
+ * (0=standard, 1=class, 2=vendor, 3=reserved)
+ * Bits 0-4: Recipient
+ * (0=device, 1=interface, 2=endpoint,3=other)
+ */
+ kal_uint8 bmRequestType;
+ /*!
+ * @brief the actual request, see the Standard Device Request Codes table
+ */
+ kal_uint8 bRequest;
+ /*!
+ * @brief a word-size value that varies according to the request
+ */
+ kal_uint16 wValue;
+ /*!
+ * @brief a word-size value that varies according to the request,
+ * the index is generally used to specify an endpoint or
+ * an interface.
+ */
+ kal_uint16 wIndex;
+ /*!
+ * @brief a word-size value that indicates the number of bytes to be
+ * transferred if there is a data stage
+ */
+ kal_uint16 wLength;
+} hifusb_setup_packet_t;
+
+
+/*!
+ * @brief used to record the bootup information for power saving power down or watchdog reset
+ */
+typedef enum _hifusb_boot_type {
+ HIFUSB_BOOT_PWRON_RST = 0,
+ HIFUSB_BOOT_SUSPEND,
+ HIFUSB_BOOT_UNKNOWN = 255,
+} hifusb_boot_type_e;
+
+/*!
+ * @brief used to record the bootup information for power saving power down or watchdog reset
+ */
+typedef struct _hifusb_boot_info {
+ hifusb_boot_type_e boot_type;
+ hifusb_usb_speed_e usb_speed;
+ kal_uint8 usb_addr;
+ kal_uint8 usb_config_val;
+} hifusb_boot_info_t;
+
+
+/*the max ep number of USB spec*/
+#define HIFUSB_USB_MAX_EP_NUM 15
+
+/*!
+ * @brief hifusb_usb_xfer_type enumerate all possible types of USB
+ * transfer type
+ * @param HIFUSB_EP_XFER_TYPE_MIN pseudo type
+ * @param HIFUSB_EP_XFER_TYPE_CONTROL Control Transfer
+ * @param HIFUSB_EP_XFER_TYPE_ISOC Isochronous Transfer
+ * @param HIFUSB_EP_XFER_TYPE_BULK Bulk Transfer
+ * @param HIFUSB_EP_XFER_TYPE_INT Interrupt Out Transfer
+ * @param HIFUSB_EP_XFER_TYPE_MAX pseudo type
+ */
+typedef enum _hifusb_usb_xfer_type {
+ HIFUSB_EP_XFER_TYPE_MIN = 0,
+ HIFUSB_EP_XFER_TYPE_CONTROL,
+ HIFUSB_EP_XFER_TYPE_ISOC,
+ HIFUSB_EP_XFER_TYPE_BULK,
+ HIFUSB_EP_XFER_TYPE_INT,
+ HIFUSB_EP_XFER_TYPE_MAX
+}hifusb_usb_xfer_type_e;
+
+/*!
+ * @brief hifusb_test_mode , the test mode which host expect,
+ * the number sync the USB2.0 Test Mode Selector
+ * The test mode only used in USB2.0 transfer
+ */
+typedef enum _hifusb_test_mode {
+ HIFUSB_HSET_NONE = 0,
+ HIFUSB_HSET_TEST_J,
+ HIFUSB_HSET_TEST_K,
+ HIFUSB_HSET_TEST_SE0_NAK,
+ HIFUSB_HSET_TEST_PACKET,
+}hifusb_test_mode_e;
+
+#define HIFUSB_MAX_QUE_NUM 15
+
+/*
+ * bit-map of hifusb_property.qmu_config (32bits) for global qmu configuration
+*/
+#define HIFUSB_QMU_CS16 (0x1 << 0)
+
+/*
+ * bit-map of hifusb_qmu_queue.config (32bits) for per-queue configuration
+*/
+#define HIFUSB_QMU_EN (0x1 << 0) // set 1 for qmu enable , set 0 for dma mode
+#define HIFUSB_QMU_CS_EN (0x1 << 1)
+#define HIFUSB_QMU_RXQ_ZLP (0x1 << 2)
+#define HIFUSB_QMU_TXQ_ZLP (0x1 << 3)
+#define HIFUSB_QMU_TXQ_EMPTY_ENQ (0x1 << 4)
+#define HIFUSB_QMU_TXQ_SPD_EN (0x1 << 5)
+#define HIFUSB_QMU_TXQ_SPD2_PAD_EN (0x1 << 6)
+
+
+#define HIFUSB_QMU_RXQ_UL_PRB_XIT_EN (0x1 << 9)
+#define HIFUSB_QMU_TXQ_DL_DRB_EN (0x1 << 10)
+
+#define HIFUSB_QMU_DLQ_XLEN_CK_EN (0x1 << 11)
+#define HIFUSB_QMU_DLQ_EOT_CK_EN (0x1 << 12)
+
+#define HIFUSB_QMU_DLQ_EN HIFUSB_QMU_TXQ_DL_DRB_EN
+#define HIFUSB_QMU_ULQ_EN HIFUSB_QMU_RXQ_UL_PRB_XIT_EN
+/*!
+ * @brief hifusb_qmu_queue_t describe per QMU-queue property that usbcore
+ * will set into usb hif driver
+ */
+typedef struct _hifusb_qmu_queue {
+ /*!
+ * @brief endpoint number of this queue
+ */
+ kal_uint8 ep_no;
+ /*!
+ * @brief queue number , shall always be ep_no-1
+ */
+ kal_uint8 que_no;
+ /*!
+ * @brief endpoint type of this queue
+ */
+ hifusb_usb_xfer_type_e type;
+ /*!
+ * @brief request fifo type of this queue is DOUBLE FIFO or not
+ */
+ kal_bool double_fifo;
+ /*!
+ * @brief queue configuration
+ */
+ kal_uint32 config;
+ /*!
+ * @brief maximun packet size of this queue
+ */
+ kal_uint16 max_packet_size;
+ /*!
+ * @brief allocate the FIFO count for this queue and also imply the U3 burst number
+ * if upper module set 0, the FIFO count is depended on the double_fifo setting
+ */
+ kal_uint8 u2_fifo_u3_burst;
+ /*!
+ * @brief reserve for 4 byte align
+ */
+ kal_uint8 reserve[1];
+} hifusb_qmu_queue_t;
+
+
+
+/*!
+ * @brief hifusb_property_t describe the property parameters that
+ * usbcore will set into usb hif driver
+ * Note : The the components commented with exception are mandatory for exception configuration
+ */
+typedef struct _hifusb_property {
+ /*!
+ * @brief desired usb speed
+ */
+ hifusb_usb_speed_e speed;
+ /*!
+ * @brief total RX QMU queues requested to configure
+ * Note : Exception Mandatory
+ */
+ kal_uint8 rxq_num;
+ /*!
+ * @brief total TX QMU queues requested to configure
+ * Note : Exception Mandatory
+ */
+ kal_uint8 txq_num;
+ /*!
+ * @brief reserve for 4 bytes alignment
+ */
+ kal_uint8 reserve[1];
+ /*!
+ * @brief QMU global configuration
+ */
+ kal_uint32 qmu_config;
+ /*!
+ * @brief QMU per queue property
+ * Note : Exception Mandatory
+ */
+ hifusb_qmu_queue_t rx_que[HIFUSB_USB_MAX_EP_NUM];
+ /*!
+ * @brief QMU per queue property
+ * Note : Exception Mandatory
+ */
+ hifusb_qmu_queue_t tx_que[HIFUSB_USB_MAX_EP_NUM];
+ /*!
+ * @brief callback function while usb state changed
+ */
+ void (*notify_usb_evt)(hifusb_notify_evt_e evt , void* p_data);
+ /*!
+ * @brief callback function while control tranfer happens for this device
+ * is received
+ * @return KAL_TRUE if the control transfer has been handled in this callback function;
+ * KAL_FALSE if the control transfer will be handled in task context later.
+ */
+ kal_bool (*notify_control_setup_packet)(hifusb_setup_packet_t* p_setup);
+ /*!
+ * @brief callback function while control tranfer is complete
+ */
+ void (*notify_control_complete)();
+ /*!
+ * @brief callback function while set pwr flag
+ */
+ void (*notify_clock_gate_flag)(kal_bool flag);
+} hifusb_property_t;
+
+typedef enum _hifusb_ufp_state {
+ HIFUSB_UFP_STATE_MIN = 0,
+ HIFUSB_UFP_STATE_PWROFF,
+ HIFUSB_UFP_STATE_PWRON,
+ HIFUSB_UFP_STATE_ATTACHED,
+ HIFUSB_UFP_STATE_NEW_RST,
+ HIFUSB_UFP_STATE_DEFAULT,
+ HIFUSB_UFP_STATE_ADDR,
+ HIFUSB_UFP_STATE_CONFIG,
+ HIFUSB_UFP_STATE_SUSPENDED,
+ HIFUSB_UFP_STATE_RESUME,
+ HIFUSB_UFP_STATE_LPM_SUSPEND,
+ HIFUSB_UFP_STATE_MAX = 0xFF,
+} hifusb_ufp_state_e;
+
+typedef enum _hifusbq_ufp_state {
+ HIFUSBQ_UFP_MIN = 0,
+ HIFUSBQ_UFP_DISABLE,
+ HIFUSBQ_UFP_ENABLE,
+ HIFUSBQ_UFP_MAX
+}hifusbq_ufp_state_e;
+
+/*!
+ * @brief hifusb_ufp_priv_t used to define the usb fast path private information.
+ */
+typedef struct _hifusb_ufp_usb_info {
+
+ kal_uint32 mode;
+ kal_uint8 usb_address;
+ kal_uint8 config_num;
+ kal_uint8 reserve[2];
+ kal_uint64 ap_usb_domain_id;
+ kal_uint64 md_cldma_domain_id;
+ kal_uint64 membank0__base_addr;
+ kal_uint64 membank0_size;
+ kal_uint64 membank4_base_addr;
+ kal_uint64 membank4_size;
+
+}hifusb_ufp_usb_info_t;
+
+/*!
+ * @brief hifusb_ufp_qmu_queue_t describe the qmu queue parameters
+ */
+typedef struct _hifusb_ufp_qmu_queue {
+ /*!
+ * @brief reserve for 4 byte align
+ */
+ kal_bool que_valid;
+ /*!
+ * @brief endpoint number of this queue
+ */
+ kal_uint8 ep_no;
+ /*!
+ * @brief queue number , shall always be ep_no-1
+ */
+ kal_uint8 que_no;
+ /*!
+ * @brief endpoint type of this queue
+ */
+ hifusb_usb_xfer_type_e type;
+ /*!
+ * @brief request fifo type of this queue is DOUBLE FIFO or not
+ */
+ kal_bool double_fifo;
+ /*!
+ * @brief queue configuration
+ */
+ kal_uint32 config;
+ /*!
+ * @brief maximun packet size of this queue
+ */
+ kal_uint16 max_packet_size;
+ /*!
+ * @brief ufp que state
+ */
+ hifusbq_ufp_state_e ufp_que_state;
+
+} hifusb_ufp_qmu_queue_t;
+
+
+/*!
+ * @brief hifusb_ufp_property_t describe the property parameters
+ */
+typedef struct _hifusb_ufp_property {
+ /*!
+ * @brief desired usb speed
+ */
+ hifusb_usb_speed_e speed;
+ /*!
+ * @brief total RX QMU queues requested to configure
+ */
+ kal_uint8 rxq_num;
+ /*!
+ * @brief total TX QMU queues requested to configure
+ */
+ kal_uint8 txq_num;
+ /*!
+ * @brief reserve for 4 bytes alignment
+ */
+ kal_uint8 reserve[1];
+ /*!
+ * @brief QMU global configuration
+ */
+ kal_uint32 qmu_config;
+ /*!
+ * @brief QMU per queue property
+ */
+ hifusb_ufp_qmu_queue_t rx_que[HIFUSB_USB_MAX_EP_NUM];
+ /*!
+ * @brief QMU per queue property
+ */
+ hifusb_ufp_qmu_queue_t tx_que[HIFUSB_USB_MAX_EP_NUM];
+
+} hifusb_ufp_property_t;
+
+
+/*!
+ * @brief hifusb_ufp_info_t used to define the usb fast path information.
+ */
+typedef struct _hifusb_ufp_info {
+
+ hifusb_ufp_usb_info_t usb_ufp_info;
+ hifusb_ufp_property_t usb_ufp_property;
+
+}hifusb_ufp_info_t;
+
+
+/*!
+ * @brief initialize usb hif driver, must call hifusb_init() and hifusb_set_property()
+ * to finish the initialization before hifusb_set_connect()
+ * @param usb_max_speed , the max speed upper driver wanted
+ * @return KAL_TRUE if initial success ,
+ KAL_FALSE if initial failure, or the speed don't match currently hardware
+ */
+kal_bool hifusb_init(hifusb_usb_speed_e usb_max_speed);
+
+/*!
+ * @brief ask usb hif driver to set this property
+ * @param property the property usbcore will set
+ * @return KAL_TRUE if the property can be satisfied, otherwise KAL_FALSE
+ */
+kal_bool hifusb_set_property(hifusb_property_t* p_property);
+
+/*!
+ * @brief ask usb hif driver to connect to Host
+ * @return KAL_TRUE if all settting correct , KAL_FALSE if setting not incorrect
+ */
+kal_bool hifusb_set_connect(void);
+
+/*!
+ * @brief ask usb hif driver to disconnect from Host
+ * @return KAL_TRUE if success , KAL_FALSE if fail
+ */
+kal_bool hifusb_set_disconnect(void);
+
+/*!
+ * @brief ask usb hif driver to set control transfer type and status in HISR context
+ * @param buffer pointer to byte array to send or receive data
+ * @param length length of buffer to send, or to receive
+ * @param type send or receive or stall
+ */
+void hifusb_set_control_request_in_hisr(kal_uint8* buffer, kal_uint32 length, hifusb_control_request_type_e type);
+
+/*!
+ * @brief ask usb hif driver to set control transfer type and status in task context
+ * @param buffer pointer to byte array to send or receive data
+ * @param length length of buffer to send, or to receive
+ * @param type send or receive or stall
+ */
+void hifusb_set_control_request_in_task(kal_uint8* buffer, kal_uint32 length, hifusb_control_request_type_e type);
+
+/*!
+ * @brief ask usb hif driver to set usb address into USB IP
+ * @param address address to be set
+ */
+void hifusb_set_usb_address(kal_uint8 address);
+
+
+/*!
+ * @brief inform usb hif driver that set configuration standard request has
+ * been received
+ * @param configuration configuration to be set
+ */
+void hifusb_set_usb_configuration(kal_uint8 configuration);
+
+/*!
+ * @brief configure the test mode when upper layer driver receive the
+ * SetFeature with the Test Mode selector
+ * @param testmode the test parsed from the ep0 request command
+ * @return KAL_TRUE when the ep0 stage and USB2.0 transfer , KAL_FALSE fail
+ */
+kal_bool hifusb_set_usb_testmode(hifusb_test_mode_e testmode);
+
+
+/*!
+ * @brief shutdown usb hif driver, detach LISR/HISR , detach USB ,shut USB PHY
+ * need to re-initial usb driver after shut down
+ */
+void hifusb_shutdown(void);
+
+/*!
+ * @brief record and log the usb ip hardware information.
+ * @param p_hw_inof , used to record the hw info
+ */
+void hifusb_get_hw_info(hifusb_hw_info_t* p_hw_info);
+
+/*!
+* @brief ask usb hif driver to set endpoint STALL for specified endpoint and queue
+* stop queue, set ep stall, flush fifo , record current GPD pointer
+* @param is_tx KAL_TRUE for tx (IN)ep , KAL_FALSE for rx (OUT)ep
+* @param nEnd endpoint number descript in ep0 request command
+*/
+void hifusb_set_stall(kal_bool is_tx, kal_uint8 nEnd);
+
+
+/*!
+* @brief ask usb hif driver to clear endpoint STALL for specified endpoint and queue
+* restore queue, start queue , clear stall
+* @param is_tx KAL_TRUE for tx (IN)ep , KAL_FALSE for rx (OUT)ep
+* @param nEnd endpoint number descript in ep0 request command
+*/
+void hifusb_clear_stall(kal_bool is_tx ,kal_uint8 nEnd);
+/*!
+* @brief ask usb hif driver to reset endpoint for flush EP FIFO,sequence number and data toggle
+* @param is_tx KAL_TRUE for tx (IN)ep , KAL_FALSE for rx (OUT)ep
+* @param nEnd endpoint number descript in ep0 request command
+*/
+void hifusb_rst_ep(kal_bool is_tx ,kal_uint8 nEnd);
+
+
+/*!
+* @brief flush the USB FIFO of specific queue endpoint
+* @param is_tx KAL_TRUE for tx (IN)ep , KAL_FALSE for rx (OUT)ep
+* @param nEnd endpoint number descript in ep0 request command
+*/
+void hifusb_flush_fifo(kal_bool is_tx, kal_uint8 q_num);
+
+
+/*!
+ * @brief use this API to trigger USB device send remote wakeup signal to host
+ * upper driver should wait resume event callback to confirm the resume flow completed
+ * @return KAL_TRUE: success, KAL_FALSE: failure
+*/
+kal_bool hifusb_remote_wakeup(void);
+
+/*!
+ * @brief use this API to trigger USB device send LPM remote wakeup signal to host
+ * upper driver should wait resume event callback to confirm the resume flow completed
+ * @return KAL_TRUE: success, KAL_FALSE: failure
+*/
+kal_bool hifusb_lpm_remote_wakeup(void);
+
+/********************************************************
+ USB SUSPEND power down reboot related flow and API Note
+*********************************************************
+ When USB SUSPEND power down issued on MT6290, whole system
+ will reboot with USB IP non-reset state.
+ USB low layer driver and high layer driver should emulate some
+ USB enumeration flow to make the software state sync current
+ hardware state.
+ Upper layer driver should follow following flow to emulate.
+ 1. hifusb_init()
+ 2. hifusb_get_boot_info()
+ ==> if the boot_type == HIFUSB_BOOT_SUSPEND plz issue follow steps
+ ==> upper driver should not hifusb_set_connect(), hifusb_set_disconnect()
+ 3. hifusb_reset_isr_emulate()
+ 4. hifusb_set_property_emulate()
+ 5. hifusb_set_usb_address_emulate()
+ 6. hifusb_set_usb_configuration_emulate()
+*********************************************************/
+/*!
+ * @brief use this function to get boot information to check if system boot from
+ * SUSPEND power down
+ * @param p_boot_info, the variable to return the boot information
+*/
+void hifusb_get_boot_info(hifusb_boot_info_t *p_boot_info);
+
+/*!
+ * @brief this function is used to emulate reset interrupt function for boot from suspend case
+ * usb driver will set private software state for link up state
+*/
+void hifusb_reset_isr_emulate(void);
+
+/*!
+ * @brief upper driver should configure the correct property with to speed mode
+ * info in the boot info get by hifusb_get_boot_info().
+ * @param p_property, the property to configure by speed mode
+ * @return KAL_TRUE: success, KAL_FALSE : failure
+*/
+kal_bool hifusb_set_property_emulate(hifusb_property_t* p_property);
+
+/*!
+ * @brief upper driver set emulate set address flow with the address in the boot info
+ * got by hifusb_get_boot_info()
+ * @param address, the current address
+*/
+void hifusb_set_usb_address_emulate(kal_uint8 address);
+
+/*!
+ * @brief upper driver set emulate set configure flow with the configuration value in the boot info
+ * got by hifusb_get_boot_info()
+ * @param configuration, the current configuration value
+*/
+void hifusb_set_usb_configuration_emulate(kal_uint8 configuration);
+
+/*!
+ * @brief used to enable/disable device auto request enter U1 state
+ * @param is_en, KAL_TRUE : enable , KAL_FALSE : disable
+ */
+void hifusb_ss_dev_init_u1_en(kal_bool is_en);
+
+/*!
+ * @brief used to enable/disable device auto request enter U2 state
+ * @param is_en, KAL_TRUE : enable , KAL_FALSE : disable
+ */
+void hifusb_ss_dev_init_u2_en(kal_bool is_en);
+
+/*!
+ * @brief send device function wakeup notify after remote wakeup issued
+ * @param if_num, the interface number which trigger remote wakeup in supre-speed
+ * @return KAL_TRUE is success, KAL_FALSE is failure
+*/
+kal_bool hifusb_ss_func_wk_notify(kal_uint8 if_num);
+
+/*!
+ * @brief suspend IP layer power save flow
+ * this function will make access IP register hang because IP clock off
+ * usbcore create a very low prioriy task to issue this function after gate all set/poll gpd instants
+ */
+void hifusb_suspend_done_handle(void);
+void hifusb_ip_pwrdn(void);
+void hifusb_set_clock_cg(kal_bool enable);
+void hifusb_mask_usb_wakeup_event(kal_bool mask);
+/*MACRO for USB EP/QUE operation*/
+
+/*!
+* @brief translate the endpoint number to queue number
+* @param nEnd endpoint number
+*/
+#define HIFUSB_EPNO_2_QNO(nEnd) (nEnd - 1)
+
+
+/*MDT Common API for USBcore*/
+kal_bool hifusb_init_ufp(void);
+
+kal_bool hifusb_ufp_enable(hifusb_ufp_info_t* p_ufp_info);
+
+kal_bool hifusb_ufp_disable(hifusb_ufp_info_t* p_ufp_info);
+
+kal_bool hifusb_ufp_bus_evt_update(hifusb_ufp_state_e* p_ufp_state);
+
+kal_bool hifusb_chk_que_empty(kal_bool is_tx, kal_uint8 q_num);
+void hifusb_start_dlq(kal_uint8 q_num);
+void hifusb_start_ulq(kal_uint8 q_num);
+kal_bool hifusb_sw_block_slp(void);
+
+void hifusb_mask_usb_intr(void);
+void hifusb_unmask_usb_intr(void);
+void hifusb_mask_mac_intr(kal_bool mask);
+#endif
diff --git a/mcu/interface/driver/hif/hif_usbdev/hif_usb_except.h b/mcu/interface/driver/hif/hif_usbdev/hif_usb_except.h
new file mode 100644
index 0000000..53540ff
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_usbdev/hif_usb_except.h
@@ -0,0 +1,133 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hif_usb.c
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * This is the USB exception handler driver API head file for both USB2.0/USB3.0.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ ****************************************************************************/
+
+#ifndef __HIF_USB_EXCEPT__
+#define __HIF_USB_EXCEPT__
+
+#include "hif_usb.h"
+
+#define HIFUSB_EXCEPT_EP_BUF_SZ 2048
+
+typedef struct _hifusb_except_cb {
+ /*!
+ * @brief callback function while usb state changed (Exception Handler Only)
+ * @param evt, the USB related event including USB bus event
+ * @param *p_data, the information to inform upper driver,
+ * Currenlty, only the USB Speed mode(hifusb_usb_speed_e) when HIFUSB_NOTIFY_EVT_RESET
+ */
+ void (*notify_usb_except_evt)(hifusb_notify_evt_e evt , void* p_data);
+ /*!
+ * @brief callback function while control data in transfer SETUP packet
+ * is received (Exception Handler Only)
+ * @param p_setup, the SETUP request 8 byte data buffer
+ * @param p_buf, the buffer which callback function shall fill data in
+ * @param p_len, the expect IN data stage data length callback function shall fill
+ * @return return STALL or not
+ */
+ hifusb_control_request_type_e (*notify_usb_except_control_in)(hifusb_setup_packet_t* p_setup, void *p_buf, kal_uint32 *p_len);
+ /*!
+ * @brief callback function while control data out or no data transfer
+ * data stage complete(Exception Handler Only)
+ * @param p_setup, the SETUP request 8 byte data buffer
+ * @param p_buf, the buffer which USB driver fill the recieved data in and callback function could parse
+ * @param len, the recieved data length USB driver filled
+ * @return return STALL or not
+ */
+ hifusb_control_request_type_e (*notify_usb_except_control_out)(hifusb_setup_packet_t* p_setup, void *p_buf, kal_uint32 len);
+
+}hifusb_except_cb_t;
+
+
+/*!
+ * @brief Change the channel configuration when exception happen
+ * Currently, system would only enumerate the ACM as logging and debug channel
+ * USB driver dettach and attach to re-enumerate
+ * @param p_except_cb, all the callback function upper driver should register
+*/
+kal_bool hifusb_except_change_ch(hifusb_except_cb_t *p_except_cb);
+
+/*!
+ * @brief upper driver should use this function to set the USB deivce and each endpoint
+ * property and the parameters commented with Exception Mandatory are required.
+ * @param p_property, the property of USB device and each endpoint
+*/
+kal_bool hifusb_except_set_property(hifusb_property_t *p_property);
+
+/*!
+ * @brief upper layer driver call this API to trigger USB related ISR handler
+ * The USB enumeration flow should use this function.
+*/
+void hifusb_except_poll_isr(void);
+
+/*!
+ * @brief ask usb hif driver to set control transfer type and status
+ * This is the USB exception handler internal used API, upper driver could ignore this API.
+ * @param length length of buffer to send, or to receive
+ * @param type send or receive or stall
+ */
+void hifusb_except_set_control_request(kal_uint32 length, hifusb_control_request_type_e type);
+/*!
+ * @brief upper layer driver set the address when received SET_ADDRESS command
+ * @param address : the address host assigned
+*/
+void hifusb_except_set_usb_address(kal_uint8 address);
+/*!
+ * @brief upper layer driver set the configuration value when received SET_CONFIGURE command
+ * @param configuration : the configure value host assigned
+*/
+void hifusb_except_set_usb_configuration(kal_uint8 configuration);
+
+#endif
diff --git a/mcu/interface/driver/hif/hif_wccif2dev/wccif2_if.h b/mcu/interface/driver/hif/hif_wccif2dev/wccif2_if.h
new file mode 100644
index 0000000..5b7e9d1
--- /dev/null
+++ b/mcu/interface/driver/hif/hif_wccif2dev/wccif2_if.h
@@ -0,0 +1,70 @@
+/*****************************************************************************
+ * Copyright Statement:
+ * --------------------
+ * This software is protected by Copyright and the information contained
+ * herein is confidential. The software may not be copied and the information
+ * contained herein may not be used or disclosed except with the written
+ * permission of MediaTek Inc. (C) 2012
+ *
+ * BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+ * AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+ * NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+ * SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+ * SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+ * THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+ * NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+ * SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+ *
+ * BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+ * LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+ * AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+ * OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+ * MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+ * WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+ * LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+ * RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+ * THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+ *
+ *****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * wccif2_if.h
+ *
+ * Project:
+ * --------
+ * UMOLYA
+ *
+ * Description:
+ * ------------
+ * Define the HIF CCISM APIs
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ *
+ ****************************************************************************/
+#ifndef _WCCIF2_IF_H_
+#define _WCCIF2_IF_H_
+
+kal_uint32 wccif2_valid_state(void);
+void wccif2_irq_mask(void);
+void wccif2_irq_unmask(void);
+void wccif2_ack(unsigned ch);
+void wccif2_reg_init(void);
+void wccif2_set(kal_uint32 ch);
+void wccif2_clear_tx(kal_uint32 ch);
+void wccif2_isr_init(void);
+
+#endif // _WCCIF2_IF_H_
diff --git a/mcu/interface/driver/hif/hifcldma_qmu.h b/mcu/interface/driver/hif/hifcldma_qmu.h
new file mode 100644
index 0000000..b0437a0
--- /dev/null
+++ b/mcu/interface/driver/hif/hifcldma_qmu.h
@@ -0,0 +1,164 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hifcldma_qmu.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * This is the HIF data path driver API head file for CLDMA
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 11 11 2020 flamingo.wang
+ * [MOLY00526005] [Colgin] CLDMA driver code porting
+ * CLDMA driver porting to MD700.MP
+ *
+ * 06 02 2017 da.li
+ * [MOLY00254661] [MT6758][VINSON][N1][Cat7][PHONE][Overnight][HQ][MTBF][Lab][Ericsson][Gemini][ASSERT] file:mcu/common/driver/sleep_drv/internal/src/ostd.c line:3058
+ * Bypass TXQ2 check, always enable sleep after poll queue done
+ *
+ * 05 11 2017 da.li
+ * [MOLY00245917] [MT6799][WHITNEY][MP2][PHONE][Overnight][HQ][MTBF][Lab][Ericsson][Gemini]Externel (EE),0,0,99,/data/core/,1,modem,md3: [Others] MD long time no response
+ * Check TX backup list before enable sleep and unmask CLDMA interrupt.
+ *
+ * 02 04 2013 ming.hsieh
+ * [MOLY00006951] MT7208 U2/U3 driver and test driver maintain
+ * .modify project name as MT6290 and change all comment or log for new model name
+ *
+ * 01 15 2013 ming.hsieh
+ * [MOLY00006951] MT6290 U2/U3 driver and test driver maintain
+ * .separate USB/SDIO/CLDMA from hif_common.c for multi-hif request
+ * -- USB (ming.hsieh)
+ * -- SDIO (Wei-De/mick.lin)
+ * -- CLDMA (TH.Cheng)
+ * .resolve SDIO BPS TX/RX test case fail issue
+ ****************************************************************************/
+
+
+
+#ifndef __HIFCLDMA_QMU_H__
+#define __HIFCLDMA_QMU_H__
+
+#if defined(__MD97__)
+#if defined(MT6297)||(CHIP10992)
+
+#include "qmu_bm.h"
+//#include "kal_internal_api.h"
+#include "hif_common.h"
+
+
+/*!
+ * @brief ask hif driver to set GPD buffer into QMU
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return KAL_TRUE : set gpd success,
+ KAL_FALSE : set gpd fail and upper module should re-submit or free the queue list
+ */
+kal_bool hifcldmaq_set_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, qbm_gpd* first_gpd, qbm_gpd* last_gpd);
+
+
+/*!
+ * @brief ask hif driver to flush all GPD buffer from QMU
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param flush type the flush type wished
+ * @param pp_head the head pointer of flush list
+ * @param pp_tail the tail pointer of flush list
+ * @return return total flushed gpd number
+ */
+kal_uint32 hifcldmaq_flush_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, hif_flush_type_e flush_type , void **pp_head, void **pp_tail);
+
+
+/*!
+ * @brief poll specified QMU queue to see if any GPD complete
+ * deq_type == HIFQ_FREEQ, (use qbmt_free_q_hwo())
+ * would free the used queue after this function and return the deq number
+ * deq_type == HIF_DEQ,
+ * would just deq and return the deq list and the deq number
+ * use use qbmt_de_q() if generic buffer type
+ * use deqmt_deq_hif_ul_type1() if QBM_TYPE_HIF_UL_TYPE1
+ * use deqmt_deq_hif_ul_type2() if QBM_TYPE_HIF_UL_TYPE2
+ * @param deq_info the que number , que type and deq type
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return return the deq number
+ */
+kal_uint32 hifcldmaq_poll_queue(hif_deq_info_t deq_info, void **first_gpd, void **last_gpd);
+
+/*!
+ * @brief initial hif_common.c private structure and variable
+ * @return return KAL_TRUE if success , KAL_FALSE if failure
+ */
+kal_bool hifcldmaq_common_qmu_init(void);
+
+/*!
+ * @brief get currently que list
+ * @param is_tx, KAL_TRUE for txq , KAL_FALSE for rxq
+ * @param q_no , the queue number form 0~n
+ * @param pp_head , return the currently queue head
+ * @param pp_tail , return the currently queue tail
+ */
+void hifcldmaq_get_que_list(kal_bool is_tx , kal_uint8 q_no, void **pp_head, void **pp_tail);
+
+/*!
+ * @brief configure specific queue operation option with bit-map config
+ * @param is_tx, KAL_TRUE for txq , KAL_FALSE for rxq
+ * @param q_no , the queue number form 0~n
+ * @param que_cfg , the bit-map configuration , ex. HIF_QCFG_BM_TX_EMPTY_ENQ
+ * @return KAL_TRUE if success, KAL_FALSE if configure not valid
+ */
+kal_bool hifcldmaq_set_que_cfg(kal_bool is_tx , kal_uint8 q_no, kal_uint16 que_cfg);
+
+kal_bool hifcldma_is_tx_bkp_list_empty(kal_uint8 q_no);
+kal_bool hifcldma_is_tx_slp_en(kal_uint8 q_no);
+
+#endif
+#endif
+
+#endif
diff --git a/mcu/interface/driver/hif/hifcldma_qmu_except.h b/mcu/interface/driver/hif/hifcldma_qmu_except.h
new file mode 100644
index 0000000..b5591e9
--- /dev/null
+++ b/mcu/interface/driver/hif/hifcldma_qmu_except.h
@@ -0,0 +1,135 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hifcldma_qmu_except.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * This is interface of the HIF data path exception handler driver for CLDMA
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ ****************************************************************************/
+#ifndef __HIFCLDMA_QMU_EXCEPT_H__
+#define __HIFCLDMA_QMU_EXCEPT_H__
+
+#if defined(__MD97__)
+#if defined(MT6297)||(CHIP10992)
+
+#include "hif_common.h"
+
+
+/*!
+ * @brief initial the exception HIF driver, only support empty enqueue flow in exception
+ * @param nonstopq set n'th bit as 1 if n'th queue not stop while init, [0:15] for DL [16:31] for UP
+ * @param exceptq set queues would be used in exception mode, [0:15] for DL [16:31] for UP
+ * @return excute pass or fail
+ */
+kal_bool hifcldmaq_except_initial(kal_uint32 nonstopq, kal_uint32 exceptq);
+
+/*!
+ * @brief clear the queue and flush CLDMA SW fifo for following using
+ * HIF layer don't care remain GPD and upper layer could parsing their resource
+ * to handle remain data re-send flow (DHL would re-send remain data after using this API)
+ *
+ */
+void hifcldmaq_except_clear_q(void);
+
+
+/*!
+ * @brief ask hif driver to set GPD buffer into QMU
+ * don't handle critical section protection becuase in the single thread exception handler
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return KAL_TRUE : set gpd success,
+ * KAL_FALSE : set gpd fail and upper module should re-submit or free the queue list
+ */
+kal_bool hifcldmaq_except_set_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, qbm_gpd* first_gpd, qbm_gpd* last_gpd);
+/*!
+ * @brief poll specified QMU queue to see if any GPD complete
+ * deq_type == HIFQ_FREEQ, (use qbmt_free_q_hwo())
+ * would free the used queue after this function and return the deq number
+ * deq_type == HIF_DEQ,
+ * would just deq and return the deq list and the deq number
+ * use use qbmt_de_q() if generic buffer type
+ *
+ * @param deq_info the que number , que type and deq type
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return return the deq number
+ */
+
+kal_uint32 hifcldmaq_except_poll_queue(hif_deq_info_t deq_info, void **pp_first_gpd, void **pp_last_gpd);
+
+/*!
+ * @brief hif driver would count the timeout for TX queue not progressing
+ * upper driver should check this the status when they found channel abnormal
+ * @param q_num, the tx queue number to check status
+ * @return Return the hif driver counter of txq stall time in millisecond (ms)
+*/
+kal_uint32 hifcldmaq_except_get_txq_timeout(kal_uint8 q_num);
+
+
+/*!
+ * @brief CLDMA upper layer would call this function to drive HIF to do something
+ *
+*/
+void hifcldmaq_except_poll_isr(void);
+
+/*!
+ * @brief get currently que list for debug
+ * @param is_tx, KAL_TRUE for txq , KAL_FALSE for rxq
+ * @param q_no , the queue number form 0~n
+ * @param pp_head , return the currently queue head
+ * @param pp_tail , return the currently queue tail
+ */
+void hifcldmaq_except_get_que_list(kal_bool is_tx , kal_uint8 q_no, void **pp_head, void **pp_tail);
+
+#endif
+#endif
+
+#endif
diff --git a/mcu/interface/driver/hif/hifsdio_qmu.h b/mcu/interface/driver/hif/hifsdio_qmu.h
new file mode 100644
index 0000000..a5d1830
--- /dev/null
+++ b/mcu/interface/driver/hif/hifsdio_qmu.h
@@ -0,0 +1,143 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hifsdio_qmu.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * This is the HIF data path driver API head file for SDIO.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 02 04 2013 ming.hsieh
+ * [MOLY00006951] MT7208 U2/U3 driver and test driver maintain
+ * .modify project name as MT6290 and change all comment or log for new model name
+ *
+ * 01 15 2013 ming.hsieh
+ * [MOLY00006951] MT6290 U2/U3 driver and test driver maintain
+ * .separate USB/SDIO/CLDMA from hif_common.c for multi-hif request
+ * -- USB (ming.hsieh)
+ * -- SDIO (Wei-De/mick.lin)
+ * -- CLDMA (TH.Cheng)
+ * .resolve SDIO BPS TX/RX test case fail issue
+ ****************************************************************************/
+
+
+
+#ifndef __HIFSDIO_QMU_H__
+#define __HIFSDIO_QMU_H__
+
+#include "qmu_bm.h"
+//#include "kal_internal_api.h"
+#include "hif_common.h"
+
+
+/*!
+ * @brief ask hif driver to set GPD buffer into QMU
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return KAL_TRUE : set gpd success,
+ KAL_FALSE : set gpd fail and upper module should re-submit or free the queue list
+ */
+kal_bool hifsdioq_set_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, qbm_gpd* first_gpd, qbm_gpd* last_gpd);
+
+
+/*!
+ * @brief ask hif driver to flush all GPD buffer from QMU
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param flush type the flush type wished
+ * @param pp_head the head pointer of flush list
+ * @param pp_tail the tail pointer of flush list
+ * @return return total flushed gpd number
+ */
+kal_uint32 hifsdioq_flush_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, hif_flush_type_e flush_type , void **pp_head, void **pp_tail);
+
+
+/*!
+ * @brief poll specified QMU queue to see if any GPD complete
+ * deq_type == HIFQ_FREEQ, (use qbmt_free_q_hwo())
+ * would free the used queue after this function and return the deq number
+ * deq_type == HIF_DEQ,
+ * would just deq and return the deq list and the deq number
+ * use use qbmt_de_q() if generic buffer type
+ * use deqmt_deq_hif_ul_type1() if QBM_TYPE_HIF_UL_TYPE1
+ * use deqmt_deq_hif_ul_type2() if QBM_TYPE_HIF_UL_TYPE2
+ * @param deq_info the que number , que type and deq type
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return return the deq number
+ */
+kal_uint32 hifsdioq_poll_queue(hif_deq_info_t deq_info, void **first_gpd, void **last_gpd);
+
+/*!
+ * @brief initial hif_common.c private structure and variable
+ * @return return KAL_TRUE if success , KAL_FALSE if failure
+ */
+kal_bool hifsdioq_common_qmu_init(void);
+
+/*!
+ * @brief get currently que list
+ * @param is_tx, KAL_TRUE for txq , KAL_FALSE for rxq
+ * @param q_no , the queue number form 0~n
+ * @param pp_head , return the currently queue head
+ * @param pp_tail , return the currently queue tail
+ */
+void hifsdioq_get_que_list(kal_bool is_tx , kal_uint8 q_no, void **pp_head, void **pp_tail);
+
+/*!
+ * @brief configure specific queue operation option with bit-map config
+ * @param is_tx, KAL_TRUE for txq , KAL_FALSE for rxq
+ * @param q_no , the queue number form 0~n
+ * @param que_cfg , the bit-map configuration , ex. HIF_QCFG_BM_TX_EMPTY_ENQ
+ * @return KAL_TRUE if success, KAL_FALSE if configure not valid
+ */
+kal_bool hifsdioq_set_que_cfg(kal_bool is_tx , kal_uint8 q_no, kal_uint16 que_cfg);
+
+#endif
diff --git a/mcu/interface/driver/hif/hifsdio_qmu_except.h b/mcu/interface/driver/hif/hifsdio_qmu_except.h
new file mode 100644
index 0000000..19ba0b2
--- /dev/null
+++ b/mcu/interface/driver/hif/hifsdio_qmu_except.h
@@ -0,0 +1,136 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hifsdio_qmu_except.h
+ *
+ * Project:
+ * --------
+ * MOLY
+ *
+ * Description:
+ * ------------
+ * This is interface of the HIF data path exception handler driver for SDIO
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 04 03 2013 vend_mick.lin
+ * [MOLY00011933] Develop SDIO driver
+ * MT6290 exception handle of SDIO driver
+ *
+ *
+ ****************************************************************************/
+#ifndef __HIFSDIO_QMU_EXCEPT_H__
+#define __HIFSDIO_QMU_EXCEPT_H__
+
+#include "hif_common.h"
+
+
+/*!
+ * @brief initial the exception HIF driver, only support empty enqueue flow in exception
+ * @param nonstopq set n'th bit as 1 if n'th queue not stop while init, [0:15] for DL [16:31] for UP
+ * @param exceptq set queues would be used in exception mode, [0:15] for DL [16:31] for UP
+ * @return excute pass or fail
+ */
+kal_bool hifsdioq_except_initial(kal_uint32 nonstopq, kal_uint32 exceptq);
+
+/*!
+ * @brief clear the queue and flush SDIO SW fifo for following using
+ * HIF layer don't care remain GPD and upper layer could parsing their resource
+ * to handle remain data re-send flow (DHL would re-send remain data after using this API)
+ *
+ */
+void hifsdioq_except_clear_q(void);
+
+
+/*!
+ * @brief ask hif driver to set GPD buffer into QMU
+ * don't handle critical section protection becuase in the single thread exception handler
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return KAL_TRUE : set gpd success,
+ * KAL_FALSE : set gpd fail and upper module should re-submit or free the queue list
+ */
+kal_bool hifsdioq_except_set_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, qbm_gpd* first_gpd, qbm_gpd* last_gpd);
+/*!
+ * @brief poll specified QMU queue to see if any GPD complete
+ * deq_type == HIFQ_FREEQ, (use qbmt_free_q_hwo())
+ * would free the used queue after this function and return the deq number
+ * deq_type == HIF_DEQ,
+ * would just deq and return the deq list and the deq number
+ * use use qbmt_de_q() if generic buffer type
+ *
+ * @param deq_info the que number , que type and deq type
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return return the deq number
+ */
+
+kal_uint32 hifsdioq_except_poll_queue(hif_deq_info_t deq_info, void **pp_first_gpd, void **pp_last_gpd);
+
+/*!
+ * @brief hif driver would count the timeout for TX queue not progressing
+ * upper driver should check this the status when they found channel abnormal
+ * @param q_num, the tx queue number to check status
+ * @return Return the hif driver counter of txq stall time in millisecond (ms)
+*/
+kal_uint32 hifsdioq_except_get_txq_timeout(kal_uint8 q_num);
+
+
+/*!
+ * @brief SDIO upper layer would call this function to drive HIF to do something
+ *
+*/
+void hifsdioq_except_poll_isr(void);
+
+/*!
+ * @brief get currently que list for debug
+ * @param is_tx, KAL_TRUE for txq , KAL_FALSE for rxq
+ * @param q_no , the queue number form 0~n
+ * @param pp_head , return the currently queue head
+ * @param pp_tail , return the currently queue tail
+ */
+void hifsdioq_except_get_que_list(kal_bool is_tx , kal_uint8 q_no, void **pp_head, void **pp_tail);
+
+#endif
diff --git a/mcu/interface/driver/hif/hifusb_qmu.h b/mcu/interface/driver/hif/hifusb_qmu.h
new file mode 100644
index 0000000..a2c189d
--- /dev/null
+++ b/mcu/interface/driver/hif/hifusb_qmu.h
@@ -0,0 +1,236 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hifusb_qmu.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * This is the HIF data path driver API head file for both USB2.0/USB3.0
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ ****************************************************************************/
+
+
+
+#ifndef __HIFUSB_QMU_H__
+#define __HIFUSB_QMU_H__
+
+#include "qmu_bm.h"
+//#include "kal_internal_api.h"
+#include "hif_common.h"
+
+
+/*!
+ * @brief ask hif driver to set GPD buffer into QMU
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return KAL_TRUE : set gpd success,
+ KAL_FALSE : set gpd fail and upper module should re-submit or free the queue list
+ */
+kal_bool hifusbq_set_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, qbm_gpd* first_gpd, qbm_gpd* last_gpd);
+
+
+/*!
+ * @brief ask hif driver to flush all GPD buffer from QMU
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param flush type the flush type wished
+ * @param pp_head the head pointer of flush list
+ * @param pp_tail the tail pointer of flush list
+ * @return return total flushed gpd number
+ */
+kal_uint32 hifusbq_flush_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, hif_flush_type_e flush_type , void **pp_head, void **pp_tail);
+
+
+/*!
+ * @brief poll specified QMU queue to see if any GPD complete
+ * deq_type == HIFQ_FREEQ, (use qbmt_free_q_hwo())
+ * would free the used queue after this function and return the deq number
+ * deq_type == HIF_DEQ,
+ * would just deq and return the deq list and the deq number
+ * use use qbmt_de_q() if generic buffer type
+ * use deqmt_deq_hif_ul_type1() if QBM_TYPE_HIF_UL_TYPE1
+ * use deqmt_deq_hif_ul_type2() if QBM_TYPE_HIF_UL_TYPE2
+ * @param deq_info the que number , que type and deq type
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return return the deq number
+ */
+kal_uint32 hifusbq_poll_queue(hif_deq_info_t deq_info, void **first_gpd, void **last_gpd);
+
+/*!
+ * @brief initial hif_common.c private structure and variable
+ * @return return KAL_TRUE if success , KAL_FALSE if failure
+ */
+kal_bool hifusbq_common_qmu_init(void);
+
+/*!
+ * @brief get currently que list
+ * @param is_tx, KAL_TRUE for txq , KAL_FALSE for rxq
+ * @param q_no , the queue number form 0~n
+ * @param pp_head , return the currently queue head
+ * @param pp_tail , return the currently queue tail
+ */
+void hifusbq_get_que_list(kal_bool is_tx , kal_uint8 q_no, void **pp_head, void **pp_tail);
+
+/*!
+ * @brief configure specific queue operation option with bit-map config
+ * @param is_tx, KAL_TRUE for txq , KAL_FALSE for rxq
+ * @param q_no , the queue number form 0~n
+ * @param que_cfg , the bit-map configuration , ex. HIF_QCFG_BM_TX_EMPTY_ENQ
+ * @return KAL_TRUE if success, KAL_FALSE if configure not valid
+ */
+kal_bool hifusbq_set_que_cfg(kal_bool is_tx , kal_uint8 q_no, kal_uint16 que_cfg);
+
+/*!
+ * @brief upper layer use this light weight api to query if new ul packet valid
+ * @return return bit-mask of valid ul packet exist queue number
+ */
+kal_uint32 hifusbq_check_ul_newpkt(void);
+
+/*!
+ * @brief upper layer use this light weight api to query if new dl packet valid
+ * @return return bit-mask of valid dl packet exist queue number
+ */
+kal_uint32 hifusbq_check_dl_newpkt(void);
+
+/*!
+ * @brief ask hif driver to buffer gpd when USB related pwr or clock off (SUSPEND)
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return KAL_TRUE : set gpd success,
+ KAL_FALSE : set gpd fail and upper module should re-submit or free the queue list
+ */
+kal_bool hifusbq_pwrsave_buffer_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, qbm_gpd* first_gpd, qbm_gpd* last_gpd);
+
+/*!
+ * @brief ask hif driver to configure gpd which bufferred when USB related pwr or clock off (SUSPEND) after resumed
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @return KAL_TRUE : set gpd success,
+ KAL_FALSE : set gpd fail and upper module should re-submit or free the queue list
+ */
+kal_bool hifusbq_pwrsave_restore_gpd(hif_queue_type_e q_type, kal_uint8 queue_no);
+
+
+/*!
+ * @brief ask hif driver to flush all GPD bufferred when USB related pwr or clock off (SUSPEND)
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param flush type the flush type wished
+ * @param pp_head the head pointer of flush list
+ * @param pp_tail the tail pointer of flush list
+ * @return return total flushed gpd number
+ */
+kal_uint32 hifusbq_pwrsave_flush_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, hif_flush_type_e flush_type , void **pp_head, void **pp_tail);
+
+/*!
+ * @brief ask hif driver to get UL/DL infotmation in init stage
+ */
+void hifusbq_get_ul_xit_base (kal_uint8 q_num , void **ul_xit_start_ptr, kal_uint32* ul_xit_count);
+void hifusbq_get_dl_drb_base (kal_uint8 q_num , void **dl_drb_start_ptr, kal_uint32* dl_drb_count, kal_uint32* dl_drb_reserv_count);
+
+/*!
+ * @brief ask hif driver to set DL fix header in init stage
+ */
+kal_bool hifusbq_set_dl_fh (kal_uint8 dl_fh_num, void *dl_fh_start_ptr, kal_uint8 dl_fh_size );
+
+/*!
+ * @brief poll specified 93 ring buffer to see if any xit/drb complete
+ */
+kal_uint32 hifusbq_poll_ul_xit (kal_uint8 q_num,kal_uint16 *ul_xit_first_idx,kal_uint16 *ul_xit_last_idx,kal_uint16 *ul_xit_last_release_idx );
+kal_uint32 hifusbq_poll_dl_drb ( kal_uint8 q_num , kal_uint32 *dl_drb_first_idx, kal_uint32 *dl_drb_last_idx );
+
+/*!
+ * @brief ask hif driver to flush all XIT/DRB buffer from USB driver
+ */
+kal_bool hifusbq_flush_ul_xit (kal_uint8 q_num, kal_uint32 *ul_xit_first_idx, kal_uint32 *ul_xit_last_idx, kal_uint32 *ul_xit_flush_count);
+kal_bool hifusbq_flush_dl_drb (kal_uint8 q_num , kal_uint32* dl_drb_first_idx, kal_uint32* dl_drb_last_idx, kal_uint32 *dl_drb_flush_count);
+
+/*!
+ * @brief ask hif driver to create/set DL DRB from USB driver
+ */
+kal_bool hifusbq_create_dl_drb ( kal_uint8 q_num , kal_uint32 *dl_drb_create_start_idx, kal_uint16 *dl_drb_create_count );
+kal_bool hifusbq_set_dl_drb (kal_uint8 q_num, kal_uint32 dl_drb_start_idx, kal_uint32 dl_drb_count);
+
+/*!
+ * @brief ask hif driver to release XIT buffer from USB driver
+ */
+kal_bool hifusbq_ul_xit_release(kal_uint8 q_num,kal_uint16 ul_xit_rel_end_idx,kal_uint16 ul_xit_count );
+
+/*!
+ * @brief Corppro call back function to release PRB buffer
+ */
+kal_bool hifusbq_ul_prb_release_func(void *ul_prb_release_start, kal_uint32 size);
+kal_bool hifusbq_ul_prb_release(void *ul_prb_release_start, void *ul_prb_release_end);
+
+/*!
+ * @brief USB driver release DL DRB in polling stage
+ */
+kal_bool hifusbq_release_dl_drb (kal_uint8 q_num , kal_uint32 dl_drb_rel_first_idx , kal_uint32 dl_drb_count );
+
+/*!
+ * @brief USB driver set header generator rule
+ */
+kal_bool hifusbq_set_header_rule (usb_header_rule_enum header_rule, usb_header_rule_data_t *rule_data);
+
+void hifusbq_init_ul_prb(kal_uint8 q_num);
+void hifusbq_init_dl_fh();
+void hifusbq_init_dl_drb(kal_uint8 q_num);
+kal_uint32 hifusbq_get_dlq_xfer_num(kal_uint8 q_num , kal_uint32 dl_drb_first_idx, kal_uint32 dl_drb_last_idx);
+
+void hifusbq_common_udq_init (void);
+kal_uint32* hifusbq_get_xit_start_address(kal_uint8 q_num);
+kal_uint32* hifusbq_get_drb_start_address(kal_uint8 q_num);
+kal_uint32* hifusbq_get_sw_drb_start_address(kal_uint8 q_num);
+kal_bool hifusbq_check_que_empty(kal_bool is_tx, kal_uint8 q_num);
+kal_bool hifusbq_ulq_block_slp(void);
+
+
+#endif
diff --git a/mcu/interface/driver/hif/hifusb_qmu_except.h b/mcu/interface/driver/hif/hifusb_qmu_except.h
new file mode 100644
index 0000000..96d6d2a
--- /dev/null
+++ b/mcu/interface/driver/hif/hifusb_qmu_except.h
@@ -0,0 +1,138 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2012
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * hifusb_qmu_except.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * This is the HIF data path exception handler driver head file for both USB2.0/USB3.0
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ * ==========================================================================
+ * $Log$
+ *
+ * 02 04 2013 ming.hsieh
+ * [MOLY00006951] MT7208 U2/U3 driver and test driver maintain
+ * .modify project name as MT6290 and change all comment or log for new model name
+ *
+ * 01 15 2013 ming.hsieh
+ * [MOLY00006951] MT6290 U2/U3 driver and test driver maintain
+ * .separate USB/SDIO/CLDMA from hif_common.c for multi-hif request
+ * -- USB (ming.hsieh)
+ * -- SDIO (Wei-De/mick.lin)
+ * -- CLDMA (TH.Cheng)
+ * .resolve SDIO BPS TX/RX test case fail issue
+ ****************************************************************************/
+
+#ifndef __HIFUSB_QMU_EXCEPT_H__
+#define __HIFUSB_QMU_EXCEPT_H__
+
+#include "hif_common.h"
+
+typedef struct _hifusbq_txq_timeout{
+ kal_uint32 start_time;
+ kal_uint32 duration_ms;
+ void *pre_cur_ptr;
+}hifusbq_txq_timeout_t;
+
+/*!
+ * @brief initial the exception HIF driver, only support empty enqueue flow in exception
+*/
+kal_bool hifusbq_except_initial(void);
+/*!
+ * @brief ask hif driver to flush all GPD buffer from QMU
+ * this API only used to stop exception mode to go back normal mode
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param flush type the flush type wished
+ * @param pp_head the head pointer of flush list
+ * @param pp_tail the tail pointer of flush list
+ * @return return total flushed gpd number
+ */
+kal_uint32 hifusbq_except_flush_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, hif_flush_type_e flush_type , void **pp_head, void **pp_tail);
+/*!
+ * @brief stop the queue and flush USB pipe fifo for following debug log
+ * HIF layer don't care remain GPD and upper layer could parsing their resource
+ * to handle remain data re-send flow (DHL would re-send remain data after using this API)
+ * @param q_type , define the queue tx/rx direction
+ * @param q_num , define the channel which using the queue number
+*/
+void hifusbq_except_clear_q(hif_queue_type_e q_type, kal_uint8 q_num);
+/*!
+ * @brief ask hif driver to set GPD buffer into QMU
+ * don't handle critical section protection becuase in the single thread exception handler
+ * @param q_type the queue type
+ * @param queue_no QMU queue no
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return KAL_TRUE : set gpd success,
+ KAL_FALSE : set gpd fail and upper module should re-submit or free the queue list
+ */
+kal_bool hifusbq_except_set_gpd(hif_queue_type_e q_type, kal_uint8 queue_no, qbm_gpd* first_gpd, qbm_gpd* last_gpd);
+/*!
+ * @brief poll specified QMU queue to see if any GPD complete
+ * deq_type == HIFQ_FREEQ, (use qbmt_free_q_hwo())
+ * would free the used queue after this function and return the deq number
+ * deq_type == HIF_DEQ,
+ * would just deq and return the deq list and the deq number
+ * use use qbmt_de_q() if generic buffer type
+ * use deqmt_deq_hif_ul_type1() if QBM_TYPE_HIF_UL_TYPE1
+ * use deqmt_deq_hif_ul_type2() if QBM_TYPE_HIF_UL_TYPE2
+ * @param deq_info the que number , que type and deq type
+ * @param first_gpd first GPD of a single GPD or GPD list
+ * @param last_gpd last GPD of a single GPD or GPD list
+ * @return return the deq number
+ */
+kal_uint32 hifusbq_except_poll_queue(hif_deq_info_t deq_info, void **pp_first_gpd, void **pp_last_gpd);
+
+/*!
+ * @brief hif driver would count the timeout for TX queue not progressing
+ * upper driver should check this the status when they found channel abnormal
+ * @param q_num, the tx queue number to check status
+ * @return Return the hif driver counter of txq stall time in millisecond (ms)
+*/
+kal_uint32 hifusbq_except_get_txq_timeout(kal_uint8 q_num);
+
+#endif