[Feature][Modem]Update MTK MODEM V1.6 baseline version: MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6
MTK modem version: MT2735_IVT_MOLY.NR15.R3.MD700.IVT.MP1MR3.MP.V1.6.tar.gz
RF modem version: NA
Change-Id: I45a4c2752fa9d1a618beacd5d40737fb39ab64fb
diff --git a/mcu/interface/driver/peripheral/DclH_kbd.h b/mcu/interface/driver/peripheral/DclH_kbd.h
new file mode 100644
index 0000000..b82dfe2
--- /dev/null
+++ b/mcu/interface/driver/peripheral/DclH_kbd.h
@@ -0,0 +1,284 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_kbd.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for KBD.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifdef DCL_DEFINITION_STRUCT
+
+#ifndef __DCLH_KBD_H_STRUCT__
+#define __DCLH_KBD_H_STRUCT__
+
+
+#define DCL_HKBD_MAGIC_NUM 0x40000000
+
+
+#ifdef __BUILD_DOM__
+/*keypad hw event */
+typedef enum
+{
+ DCL_EVENT_HKBD_STATUS_CHANGE = 0x01, /*keypad hw status change for the normal keypad hw matrix*/
+ DCL_EVENT_HKBD_EX_STATUS_CHANGE = 0X02,/*keypad extension direction key status change ex: jogball*/
+ DCL_EVENT_HKBD_MAX = 0XFF,/*the max keypad hw event id*/
+
+}KBDH_EVENTS;
+#else
+#define KBDH_EVENTS \
+ DCL_EVENT_HKBD_STATUS_CHANGE = 0x01, \
+ DCL_EVENT_HKBD_EX_STATUS_CHANGE = 0X02,\
+ DCL_EVENT_HKBD_MAX = 0XFF,\
+
+#endif
+
+
+#ifdef __BUILD_DOM__
+/*keypad hw control commands*/
+typedef enum
+{
+ HKBD_CMD_GET_KEY_NUMBER, /*the command to get the total key number*/
+ HKBD_CMD_GET_KEY_STA_MAP,/*get the keypad hw status register table*/
+ HKBD_CMD_GET_KEY_STATUS, /*Query the key is pressed or released status*/
+ HKBD_CMD_GET_POWER_KEY_STATUS,/*Query the power key status*/
+
+}KBDH_CMDS;
+#else
+#define KBDH_CMDS \
+ HKBD_CMD_GET_KEY_NUMBER, \
+ HKBD_CMD_GET_KEY_STA_MAP,\
+ HKBD_CMD_GET_KEY_STATUS,\
+ HKBD_CMD_GET_POWER_KEY_STATUS,
+#endif
+
+
+#ifdef __BUILD_DOM__
+/*define the data structure type for every command*/
+typedef union
+{
+ HKBD_CTRL_KNUM_T rKBDCtrlKNUM; /*keypad number structure*/
+ HKBD_CTRL_STA_MAP_T rKBDCtrlStaMap; /*keypad stauts register structure*/
+ HKBD_CTRL_KEY_STA_T rKBDCtrlKeySta; /*key status structure*/
+ HKBD_CTRL_POWKEY_T rKBDCtrlPowerKeySta;/*power key status structure*/
+}KBDH_CTRLS;
+
+#else
+#define KBDH_CTRLS \
+ HKBD_CTRL_KNUM_T rKBDCtrlKNUM; \
+ HKBD_CTRL_STA_MAP_T rKBDCtrlStaMap;\
+ HKBD_CTRL_KEY_STA_T rKBDCtrlKeySta;\
+ HKBD_CTRL_POWKEY_T rKBDCtrlPowerKeySta;
+#endif
+
+
+//HKBD_CMD_GET_KEY_NUMBER
+/*the control command data for command:HKBD_CMD_GET_KEY_NUMBER*/
+typedef struct
+{
+ DCL_UINT16 u2KeyNum;/*key number*/
+} HKBD_CTRL_KNUM_T;
+
+//HKBD_CMD_GET_KEY_STA_MAP
+/*the control command data for command:HKBD_CMD_GET_KEY_STA_MAP*/
+typedef struct
+{
+ DCL_UINT32 kbdmap_reg;/*the lowest 32bit register value, every bit indicates one key status*/
+ DCL_UINT32 kbdmap_reg1;/*the middle 32bit register value, every bit indicates one key status*/
+ DCL_UINT32 kbdmap_reg2;/*the highest 32bit register value, every bit indicates one key status*/
+} HKBD_CTRL_STA_MAP_T;
+
+/*the control command data for command:HKBD_CMD_GET_KEY_STATUS*/
+typedef struct
+{
+ DCL_BOOL sta;/*key stauts:KAL_TURE indicates the key is pressed, KAL_FALSE indicates the key is released*/
+ DCL_UINT8 key;/*key index number, which is defined in the kbd_table.h */
+}HKBD_CTRL_KEY_STA_T;
+
+/*the control command data for command:HKBD_CMD_GET_POWER_KEY_STATUS*/
+typedef struct
+{
+ DCL_BOOL fgPKP;/*KAL_TURE indicates the key is pressed, KAL_FALSE indicates the key is released*/
+} HKBD_CTRL_POWKEY_T;
+
+#endif
+#endif
+
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_HKBD_H_PROTOTYPE__
+#define __DCL_HKBD_H_PROTOTYPE__
+
+
+/*************************************************************************
+*<GROUP CallBackFunctions>
+* FUNCTION
+* KBDH_EVENT_FUNC
+*
+* DESCRIPTION
+* This function is the callback function for the hw status change.
+*
+* PARAMETERS
+* event: the keypad hw event, it can be the enum value KBDH_EVENTS.
+* param: the optional parameter.
+*
+* RETURNS
+* NONE
+*
+*************************************************************************/
+typedef void (*KBDH_EVENT_FUNC)(DCL_EVENT event, void* param) ;
+
+/*************************************************************************
+* FUNCTION
+* DclHKBD_Initialize
+*
+* DESCRIPTION
+* This function is to initialize keypad hardware module, It is called during the driver initialization and the user is not needed to call it.
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclHKBD_Initialize(void);
+
+/*************************************************************************
+* FUNCTION
+* DclHKBD_Open
+*
+* DESCRIPTION
+* This function is to open the keypad hw module and return a handle.
+*
+* PARAMETERS
+* dev:keypad device ID. it should be DCL_KBD.
+* flags:User of keypad driver. It should be the user module id, if the user does not module id, it can be set 0.
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Incorrect device ID.
+* Other value: A valid handle
+*
+* EXAMPLE
+* <code>
+* DCL_HANDLE kbd_handle;
+* kbd_handle = DclHKBD_Open(DCL_KBD, MOD_DRVKBD);
+* </code>
+*************************************************************************/
+extern DCL_HANDLE DclHKBD_Open(DCL_DEV dev, DCL_FLAGS flags);
+
+/*************************************************************************
+* FUNCTION
+* DclHKBD_Control
+*
+* DESCRIPTION
+* This function is to control the keypad driver, the user can call the interface to get the keypad driver services through the different commands.
+*
+* PARAMETERS
+* handle: the user handler of the keypad, which is returned by the DclHKBD_Open function.
+* cmd: the keypad driver control commands, the values can be get from the enum KBDH_CMDS.
+* data: the data which is corresponed to the commands, the data type can beone of the enum KBDH_CTRLS.
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Incorrect device ID.
+* STATUS_OK: return successfully.
+*
+* EXAMPLE
+* <code>
+* DCL_HANDLE kbdhandle;
+* DCL_CTRL_DATA_T reg;
+* kbdhandle = DclHKBD_Open(DCL_KBD, MOD_DRVKBD);
+* DclHKBD_Control(kbdhandle, HKBD_CMD_GET_KEY_STA_MAP, (DCL_CTRL_DATA_T*)®);
+* pkeypad_status->kbdmap_reg = reg.rKBDCtrlStaMap.kbdmap_reg;
+* pkeypad_status->kbdmap_reg1= reg.rKBDCtrlStaMap.kbdmap_reg1;
+* pkeypad_status->kbdmap_reg2= reg.rKBDCtrlStaMap.kbdmap_reg2;
+* </code>
+*
+*************************************************************************/
+extern DCL_STATUS DclHKBD_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+
+
+/*************************************************************************
+* FUNCTION
+* DclHKBD_Close
+*
+* DESCRIPTION
+* This function is to close the keypad driver.
+*
+* PARAMETERS
+* handle: the user handler of the keypad, which is returned by the DclHKBD_Open function.
+*
+* RETURNS
+* STATUS_OK: return successfully.
+*
+*************************************************************************/
+extern DCL_STATUS DclHKBD_Close(DCL_HANDLE handle);
+
+/*************************************************************************
+* FUNCTION
+* DclHKBD_RegisterCallback
+*
+* DESCRIPTION
+* This function is to register the hardware event callback function.
+*
+* PARAMETERS
+* handle: the user handler of the keypad, which is returned by the DclHKBD_Open function.
+* event: the keypad hardware event.It can be one of the value in the enum KBDH_EVENTS.
+* callback: the callback function pointer.
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Incorrect device ID.
+* STATUS_INVALID_EVENT: the event parameter is not valid for the keypad.
+* STATUS_OK: return successfully.
+*
+* EXAMPLE
+* <code>
+* DCL_HANDLE handle ;
+* handle = DclHKBD_Open(DCL_KBD, 0);
+* DclHKBD_RegisterCallback(handle, DCL_EVENT_HKBD_STATUS_CHANGE, &Kbd_hw_event_Callback);
+* </code>
+*
+*************************************************************************/
+extern DCL_STATUS DclHKBD_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, KBDH_EVENT_FUNC callback);
+
+#endif
+#endif
+
diff --git a/mcu/interface/driver/peripheral/DclS_kbd.h b/mcu/interface/driver/peripheral/DclS_kbd.h
new file mode 100644
index 0000000..6a0c5f3
--- /dev/null
+++ b/mcu/interface/driver/peripheral/DclS_kbd.h
@@ -0,0 +1,327 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_kbd.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for KBD.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifdef DCL_DEFINITION_STRUCT
+
+ #ifndef __DCLS_KBD_H_STRUCT__
+#define __DCLS_KBD_H_STRUCT__
+
+#ifdef __BUILD_DOM__
+/*keypad driver control commands which is related with software layer*/
+typedef enum
+{
+ KBD_CMD_SET_LONG_PRESS_TIME, /*Set the long press key time*/
+ KBD_CMD_SET_REPEAT_PRESS_TIME, /*Set the repeat press key time*/
+ KBD_CMD_SET_DETECTION_MODE, /*Set the key detection mode*/
+ KBD_CMD_GET_KEY_DATA, /*get the press key data*/
+ KBD_CMD_PEEK_KEY_DATA,/*peek the press key data*/
+ KBD_CMD_GET_DETECTION_MODE,/*get the current key detection mode*/
+ KBD_CMD_CTRL_KEY_SUPPORT,/*query the key is support or not */
+ KBD_CMD_CTRL_KEY_MULTIPLE,/*query the key is multiple key or not*/
+ KBD_CMD_GET_KEY_EVENT_CNT,/*get the key event in the buffer*/
+ KBD_CMD_PUT_KEY_DATA,/*put the key press data to the upper layer*/
+
+}KBD_CMDS;
+
+#else
+#define KBD_CMDS \
+ KBD_CMD_SET_LONG_PRESS_TIME, \
+ KBD_CMD_SET_REPEAT_PRESS_TIME, \
+ KBD_CMD_SET_DETECTION_MODE, \
+ KBD_CMD_GET_KEY_DATA, \
+ KBD_CMD_PEEK_KEY_DATA,\
+ KBD_CMD_GET_DETECTION_MODE,\
+ KBD_CMD_CTRL_KEY_SUPPORT,\
+ KBD_CMD_CTRL_KEY_MULTIPLE,\
+ KBD_CMD_GET_KEY_EVENT_CNT,\
+ KBD_CMD_PUT_KEY_DATA,\
+ KBD_CMD_FIND_TWO_STEP,
+
+#endif
+
+/*keypad events to the upper layer*/
+typedef enum {
+ DCL_kbd_onekey_press=0,/*one key press event*/
+ DCL_kbd_onekey_release,/*one key release event*/
+#ifdef TWO_KEY_ENABLE
+ DCL_kbd_twokey_press, /*two key press event, which has been phase out now */
+ DCL_kbd_twokey_release,/*two key release event, which has been phase out now*/
+#endif /*TWO_KEY_ENABLE*/
+ DCL_kbd_onekey_longpress,/*one long press key event*/
+ DCL_kbd_onekey_repeated,/*one repeated press key event*/
+ DCL_kbd_onekey_fullpress,/*two step key function: one key full press event*/
+ DCL_kbd_twokey_detection_enable,/*enable two key detection mode*/
+ DCL_kbd_threekey_detection_enable,/*enable three key detection mode*/
+ DCL_kbd_multikey_detection_disable/*multiple key detection mode is disable, default is one key detection mode*/
+} DCL_KBD_EVENT;
+
+/*key detection mode*/
+typedef enum {
+ DCL_kbd_1_key_det_mode = 0, /*one key detection mode*/
+ DCL_kbd_2_keys_det_mode,/*two key detection mode */
+ DCL_kbd_3_keys_det_mode /*three key detection mode*/
+}DCL_kbd_key_det_mode;
+
+/*the control command data for command:KBD_CMD_SET_DETECTION_MODE and KBD_CMD_GET_DETECTION_MODE */
+typedef struct
+{
+ DCL_BOOL bFlag;/*the return flag to indicate whether switch mode successfully*/
+ DCL_UINT8 Det_Mode;/*the detection mode value*/
+} SKBD_CTRL_MODE_T;
+
+/*the control command data for command:KBD_CMD_GET_KEY_EVENT_CNT*/
+typedef struct
+{
+ DCL_UINT8 keycnt;/*the key event count in the buffer*/
+}SKBD_CTRL_KEY_CNT_T;
+
+/*the control command data for command:KBD_CMD_GET_KEY_DATA*/
+typedef struct
+{
+ DCL_KBD_EVENT Keyevent;/*the key event*/
+#ifdef TWO_KEY_ENABLE
+ DCL_UINT8 Keydata[2];/*the key data*/
+#else /*!TWO_KEY_ENABLE*/
+ DCL_UINT8 Keydata[1];/*the key data*/
+#endif /*TWO_KEY_ENABLE*/
+#if defined(__TC01__)
+ DCL_UINT32 keytimestamp;/*the key time stamp*/
+#endif
+
+} SKBD_CTRL_KEYDATA_T;
+
+/*the control command data for command:KBD_CMD_PEEK_KEY_DATA*/
+typedef struct
+{
+ SKBD_CTRL_KEYDATA_T* keydata;/*the key data */
+ DCL_BOOL specify_read; /*specify whether to read the data in the position of read_pointerl; KAL_TURE:specify to peek the data
+ in the position:read_pointer;KAL_FALSE: return the current read pointer data to the upper layer*/
+ DCL_UINT32 read_pointer;/*the read position in the buffer, the max value is buff_size;*/
+ DCL_UINT32* current_read_pointer;/*return the data in the structure position*/
+
+}SKBD_CTRL_PEEKDATA_T;
+
+
+/*the control command data for command:KBD_CMD_CTRL_KEY_MULTIPLE*/
+typedef struct
+{
+ DCL_BOOL fgIMK;/*the return value to indicate whether the ukey is a multiple key*/
+ DCL_UINT8 uKey; /*the input parameter to indicate the key index*/
+} SKBD_CTRL_MULTIKEY_T;
+
+
+/*the control command data for command:KBD_CMD_CTRL_KEY_SUPPORT*/
+typedef struct
+{
+ DCL_UINT8 uKey;/*the input parameter to indicate the key index*/
+ DCL_BOOL fgIKBS;/*the return flag to indicate whether the ukey *is supported*/
+} SKBD_CTRL_KEYSUPPORT_T;
+
+/*the control command data for command:KBD_CMD_SET_LONG_PRESS_TIME and KBD_CMD_SET_REPEAT_PRESS_TIME*/
+typedef struct
+{
+ DCL_UINT32 u4Tick;/*the time unit is ms.*/
+} SKBD_CTRL_TIME_T;
+
+/*the control command data for command:KBD_CMD_PUT_KEY_DATA */
+typedef struct
+{
+ DCL_UINT8 keydata;/*the key index number*/
+}SKBD_CTRL_PUTKEY_T;
+
+typedef struct
+{
+ DCL_UINT32 *number;
+ DCL_UINT8 *two_step;
+}SKBD_CTRL_FIND_TWO_STEP_T;
+
+
+#ifdef __BUILD_DOM__
+/*define the data structure type for every command*/*/
+typedef union
+{
+ SKBD_CTRL_TIME_T rKBDCtrTime; /*the long press and repeat press time */
+ SKBD_CTRL_KEYSUPPORT_T rKBDCtrlKeySupport; /*the key support structure*/
+ SKBD_CTRL_MULTIKEY_T rKBDCtrlMultiple; /*the multiply key structure*/
+ SKBD_CTRL_PEEKDATA_T rKBDCtrPeekData; /*peek key data command control data structure*/
+ SKBD_CTRL_KEYDATA_T rKBDCtrGetData; /*get key data command control data structure*/
+ SKBD_CTRL_MODE_T rKBDCtrMode; /*detection command control data structure*/
+ SKBD_CTRL_KEY_CNT_T rKBDCtrkeyCnt;/*get key event count command control data structure*/
+ SKBD_CTRL_PUTKEY_T rKBDCtrPutKey;/*put key data command control data structure*/
+ SKBD_CTRL_FIND_TWO_STEP_T rKBDCtrlFindTwoStepKey;
+
+}KBDS_CTRLS;
+
+#else
+#define KBDS_CTRLS \
+ SKBD_CTRL_TIME_T rKBDCtrTime; \
+ SKBD_CTRL_KEYSUPPORT_T rKBDCtrlKeySupport; \
+ SKBD_CTRL_MULTIKEY_T rKBDCtrlMultiple; \
+ SKBD_CTRL_PEEKDATA_T rKBDCtrPeekData; \
+ SKBD_CTRL_KEYDATA_T rKBDCtrGetData; \
+ SKBD_CTRL_MODE_T rKBDCtrMode;\
+ SKBD_CTRL_KEY_CNT_T rKBDCtrkeyCnt;\
+ SKBD_CTRL_PUTKEY_T rKBDCtrPutKey;\
+ SKBD_CTRL_FIND_TWO_STEP_T rKBDCtrlFindTwoStepKey;
+#endif
+
+#endif
+#endif
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_SKBD_H_PROTOTYPE__
+#define __DCL_SKBD_H_PROTOTYPE__
+
+/*************************************************************************
+* FUNCTION
+* DclSKBD_Initialize
+*
+* DESCRIPTION
+* This function is to initialize keypad hardware module, It is called during the driver initialization.
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclSKBD_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclSKBD_Open
+*
+* DESCRIPTION
+* This function is to open the keypad hw module and return a handle.
+*
+* PARAMETERS
+* dev: keypad device ID. it should be DCL_KBD.
+* flags: User of keypad driver. It should be the user module id, if the user does not module id, it can be set 0.
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Incorrect device ID.
+* Other value: A valid handle
+*
+* EXAMPLE
+* <code>
+* DCL_HANDLE kbd_handle;
+* kbd_handle = DclSKBD_Open(DCL_KBD, MOD_DRVKBD);
+* </code>
+*
+*************************************************************************/
+extern DCL_HANDLE DclSKBD_Open(DCL_DEV dev, DCL_FLAGS flags);
+
+/*************************************************************************
+* FUNCTION
+* DclSKBD_Close
+*
+* DESCRIPTION
+* This function is to close the keypad driver.
+*
+* PARAMETERS
+* handle: the user handler of the keypad, which is returned by the DclSKBD_Close function.
+*
+* RETURNS
+* STATUS_OK: return successfully.
+*
+*************************************************************************/
+extern DCL_STATUS DclSKBD_Close(DCL_HANDLE handle);
+/*************************************************************************
+* FUNCTION
+* DclSKBD_Control
+*
+* DESCRIPTION
+* This function is to control the keypad driver, the user can call the interface to get the keypad driver services through the different commands.
+* the control services is responsible for the software related services, the keypad hardware related services can be accessed through the DCLH** interface.
+* PARAMETERS
+* handle: the user handler of the keypad, which is returned by the DclSKBD_Open function.
+* cmd: the keypad driver control commands, the values can be get from the enum KBD_CMDS.
+* data: the data which is corresponed to the commands, the data type can beone of the enum KBDS_CTRLS.
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Incorrect device ID.
+*STATUS_BUFFER_EMPTY:indicate the buffer is empty, when the command KBD_CMD_GET_KEY_DATA or KBD_CMD_PEEK_KEY_DATA is used.
+* STATUS_OK: return successfully.
+*
+* EXAMPLE
+* <code>
+* DCL_CTRL_DATA_T sta;
+* DCL_HANDLE handle1;
+* handle1 = DclSKBD_Open(DCL_KBD, MOD_MMI);
+* DclSKBD_Control(handle1,KBD_CMD_GET_KEY_EVENT_CNT , (DCL_CTRL_DATA_T*)&sta);
+*return sta.rKBDCtrkeyCnt.keycnt;
+* </code>
+*
+*************************************************************************/
+extern DCL_STATUS DclSKBD_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+
+/*************************************************************************
+* FUNCTION
+* DclSKBD_RegisterCallback
+*
+* DESCRIPTION
+* This function is to register the hardware event callback function.
+*
+* PARAMETERS
+* handle: the user handler of the keypad, which is returned by the DclHKBD_Open function.
+* event: Reserved.
+* callback: the callback function pointer.
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Incorrect device ID.
+* STATUS_INVALID_EVENT: the event parameter is not valid for the keypad.
+* STATUS_OK: return successfully.
+*
+*************************************************************************/
+extern DCL_STATUS DclSKBD_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event,PFN_DCL_CALLBACK callback);
+#endif
+#endif
+
diff --git a/mcu/interface/driver/peripheral/accessory_sw.h b/mcu/interface/driver/peripheral/accessory_sw.h
new file mode 100644
index 0000000..19db30f
--- /dev/null
+++ b/mcu/interface/driver/peripheral/accessory_sw.h
@@ -0,0 +1,131 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * accessory_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for accessory detector driver and adaption.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef ACCESSSORY_SW_H
+#define ACCESSSORY_SW_H
+
+#include "kal_general_types.h"
+
+typedef struct
+{
+ // This API is for aux task to register HISR handler for earphone
+ // PWIC will use det_earphone_present() to determine whether it is in/out
+ void (*reg_earphone_hisr)(void (earphone_hisr_callback)(void));
+
+ // This API is for aux task to register HISR handler for tvout
+ // PWIC will use det_earphone_present() to determine whether it is in/out
+ void (*reg_tvout_hisr)(void (tvout_hisr_callback)(void));
+
+ // This API is for aux task to register HISR handler for earphone key
+ // PWIC will use det_earphone_present() to determine whether it is in/out
+ void (*reg_key_hisr)(void (key_hisr_callback)(void));
+
+ // This API is to set S/W debounce time for earphone cable
+ // The uint of deb_time is in 10ms (GPT tick)
+ void (*set_earphone_in_deb_time)(kal_uint32 deb_time);
+
+ // This API is to set S/W debounce time for earphone cable
+ // The uint of deb_time is in 10ms (GPT tick)
+ void (*set_earphone_out_deb_time)(kal_uint32 deb_time);
+
+ // This API is to set S/W debounce time for tvout cable
+ // The uint of deb_time is in 10ms (GPT tick)
+ void (*set_tvout_in_deb_time)(kal_uint32 deb_time);
+
+ // This API is to set S/W debounce time for tvout cable
+ // The uint of deb_time is in 10ms (GPT tick)
+ void (*set_tvout_out_deb_time)(kal_uint32 deb_time);
+
+ // This API is to set S/W debounce time for key press
+ // The uint of deb_time is in 10ms (GPT tick)
+ void (*set_key_press_deb_time)(kal_uint32 deb_time);
+
+ // This API is to set S/W debounce time for key release
+ // The uint of deb_time is in 10ms (GPT tick)
+ void (*set_key_release_deb_time)(kal_uint32 deb_time);
+
+ // Init the external accessory detection mechanism
+ // The API is called at boot phase
+ void (*drv_init)(void);
+
+ // The API is called at driver init phase
+ void (*enable_intr)(void);
+
+}aux_ext_accessory_det;
+
+typedef struct
+{
+ void (*aux_plug_in)(void);
+ void (*aux_plug_out)(void);
+ void (*aux_uart_func)(kal_bool enable);
+ void (*aux_HSTV_func)(kal_bool enable);
+}aux_func_struct;
+
+
+
+#if defined(__DRV_EXT_ACCESSORY_DETECTION__ )
+extern aux_ext_accessory_det *aux_ext_acc_det;
+extern aux_ext_accessory_det *aux_custom_get_ext_accessory_det(void);
+#endif // #if defined(__DRV_EXT_ACCESSORY_DETECTION__ )
+
+
+
+#endif//#define ACCESSSORY_SW_H
diff --git a/mcu/interface/driver/peripheral/adc.h b/mcu/interface/driver/peripheral/adc.h
new file mode 100644
index 0000000..a800215
--- /dev/null
+++ b/mcu/interface/driver/peripheral/adc.h
@@ -0,0 +1,508 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * adc.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for GPT driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _ADC_H
+#define _ADC_H
+
+//#include "adc_hw.h"
+//#include "adc_sw.h"
+//#include "adc_channel.h" //remove this when check in MAUI. remind UEM not use ADC_VBAT
+
+//#include "drv_features.h"
+//#include "adc_channel.h"
+//
+//typedef enum {
+// vbat_adc_channel=0,
+// visense_adc_channel,
+// vbattmp_adc_channel,
+// battype_adc_channel,
+// vcharger_adc_channel,
+// pcbtmp_adc_channel,
+// aux_adc_channel,
+// chr_usb_adc_channel,
+// otg_vbus_adc_channel,
+// rftmp_adc_channel
+//} adc_channel_type;
+//
+///*
+//1. Check bit of ADC (1b), *(0x80000020)[18]=[210]
+//2. ADC_B (6b), *(0x80000020)[17:12]=[209:204]
+//3. ADC_A (7b), *(0x80000020)[11:5]=[203:197]
+//*/
+//#define EFUSE_ADC_BASE 0x80000020
+//#define EFUSE_ADC_A 0x80000020
+//#define EFUSE_ADC_B 0x80000020
+//#define EFUSE_ADC_ENABLE 0x40000
+//#define EFUSE_ADC_A_MASK 0xFE0
+//#define EFUSE_ADC_B_MASK 0x3F000
+//#define EFUSE_ADC_A_SHIFT 5
+//#define EFUSE_ADC_B_SHIFT 12
+//
+//
+//#if defined(DRV_ADC_LIMIT_REG) || defined(FPGA)
+//#if !defined(DRV_ADC_OFF)
+// /*******************
+// * GPADC Registers *
+// *******************/
+// #define AUXADC_DATA (AUXADC_base+0x0000) /* Sampled data */
+// #define AUXADC_CTRL (AUXADC_base+0x0004) /* Control of A/D Converter */
+// #define AUXADC_STAT (AUXADC_base+0x0008) /* A/D Status..reg=0,if write AUXADC_CTRL reg*/
+// #define AUXADC_CTRL2 (AUXADC_base+0x000c) /* Special Control of A/D Converter */
+//
+// #define AUXADC_STAT_RDY 0x0001 /*ADC ready*/
+//
+// #define AUXADC_CTRL2_CALI 0x0001 /*ADC Calibration*/
+// #define AUXADC_CTRL2_MON 0x0020 /*DACMON*/
+// #define AUXADC_CTRL2_BYP 0x0040 /*DACBYP*/
+//#endif // #if !defined(DRV_ADC_OFF)
+//
+// /*ADC pin selection, ADC phy. channel*/
+//
+// #define ADC_MAX_CHANNEL 5
+// #define ADC_ERR_CHANNEL_NO 50
+//#endif /*(DRV_ADC_LIMIT_REG,FPGA)*/
+///*************************************************************************/
+//#if defined(DRV_ADC_BASIC_REG)
+//#if !defined(DRV_ADC_OFF)
+// #define AUXADC_SYNC (AUXADC_base+0x0000)
+// #define AUXADC_IMM (AUXADC_base+0x0004)
+// #define AUXADC_SYN (AUXADC_base+0x0008)
+// #define AUXADC_CON (AUXADC_base+0x000c)
+// #define AUXADC_DAT(_line) (AUXADC_base+0x0010+(4*_line))
+//
+// /*AUXADC_SYNC*/
+// #define AUXADC_SYNC_CHAN(_line) (0x0001<<_line) /*Time event 1*/
+//
+// /*AUXADC_IMM*/
+// #define AUXADC_IMM_CHAN(_line) (0x0001<<_line)
+//
+// /*AUXADC_SYN*/
+// #define AUXADC_SYN_BIT (0x0001) /*Time event 0*/
+//
+// /*AUXADC_CON*/
+// #define AUXADC_CON_RUN (0x0001)
+//#ifndef DRV_ADC_NO_TEST_DACMON
+// #define AUXADC_CON_CALI_MASK (0x007c)
+// #define AUXADC_CON_TESTDACMON (0x0080)
+//#endif // #ifndef DRV_ADC_NO_TEST_DACMON
+//#if defined(DRV_ADC_SW_RESET)
+// #define AUXADC_CON_SW_RESET (0x0080)
+//#endif // #if defined(DRV_ADC_SW_RESET)
+// #define AUXADC_CON_AUTOCLR0 (0x0100)
+// #define AUXADC_CON_AUTOCLR1 (0x0200)
+// #define AUXADC_CON_PUWAIT_EN (0x0800)
+// #define AUXADC_CON_AUTOSET (0x8000)
+//#endif // #if !defined(DRV_ADC_OFF)
+//
+//
+//
+// #if defined(DRV_ADC_MAX_CH_5)
+// #define ADC_MAX_CHANNEL 5
+// #endif /*DRV_ADC_MAX_CH_5*/
+//
+// #if defined(DRV_ADC_MAX_CH_6)
+// #define ADC_MAX_CHANNEL 6
+// #endif /*DRV_ADC_MAX_CH_6*/
+//
+// #if defined(DRV_ADC_MAX_CH_7)
+// #define ADC_MAX_CHANNEL 7
+// #endif /*DRV_ADC_MAX_CH_7*/
+//
+// #if defined(DRV_ADC_MAX_CH_8)
+// #define ADC_MAX_CHANNEL 8
+// #endif /*DRV_ADC_MAX_CH_8*/
+//
+// #if defined(DRV_ADC_MAX_CH_9)
+// #define ADC_MAX_CHANNEL 9
+// #endif /*DRV_ADC_MAX_CH_9*/
+//
+// #if defined(DRV_ADC_MAX_CH_10)
+// #define ADC_MAX_CHANNEL 10
+// #endif /*DRV_ADC_MAX_CH_10*/
+//
+// #if defined(DRV_ADC_MAX_CH_13)
+// #define ADC_MAX_CHANNEL 13
+// #endif /*DRV_ADC_MAX_CH_10*/
+//
+// #define ADC_ERR_CHANNEL_NO 50
+//#endif /*(MT6205B,MT6218)*/
+//
+//#if ( defined(DRV_ADC_BASIC_REG) || defined(DRV_ADC_TDMA_TIME) )
+//#if !defined(DRV_ADC_OFF)
+// #if defined(DRV_ADC_TDMA_EVENT_REG_POS1)
+// #define AUXADC_TDMA_EVENT0 (TDMA_base+0x1c0)
+// #define AUXADC_TDMA_EVENT1 (TDMA_base+0x1c4)
+// #elif defined(DRV_ADC_TDMA_EVENT_REG_POS2)
+// #define AUXADC_TDMA_EVENT0 (TDMA_base+0x400)
+//
+// #if defined(MT6229_S00)
+// #define AUXADC_TDMA_EVENT1 (TDMA_base+0x400)/*HW bug*/
+// #else
+// #define AUXADC_TDMA_EVENT1 (TDMA_base+0x404)/**/
+// #endif
+//
+// #else
+// #define AUXADC_TDMA_EVENT0 (TDMA_base+0x1b0)
+// #define AUXADC_TDMA_EVENT1 (TDMA_base+0x1b4)
+// #endif
+//
+// #if defined(DRV_ADC_TDMA_EN_REG_POS1)
+// #define AUXADC_TDMA_EN (TDMA_base+0x16C)
+// #else
+// #define AUXADC_TDMA_EN (TDMA_base+0x164)
+// #endif
+// /*AUXADC_TDMA_EN*/
+// #define AUXADC_TDMA_EN_EVT0 (0x0001)
+// #define AUXADC_TDMA_EN_EVT1 (0x0002)
+//#endif // #if !defined(DRV_ADC_OFF)
+//#endif // #if ( defined(DRV_ADC_BASIC_REG) || defined(DRV_ADC_TDMA_TIME) )
+//
+//
+//#if defined(DRV_ADC_NOT_EXIST)
+// #define ADC_MAX_CHANNEL 1
+// #define ADC_ERR_CHANNEL_NO 50
+//#endif // #if defined(DRV_ADC_NOT_EXIST)
+//
+//#if !defined(DRV_ADC_OFF)
+//#if !defined(ADC_MAX_CHANNEL)
+// #define ADC_MAX_CHANNEL 1
+// #define ADC_ERR_CHANNEL_NO 50
+//#endif // #if defined(DRV_ADC_NOT_EXIST)
+//#endif // #if !defined(DRV_ADC_OFF)
+//
+//#if 1
+// typedef struct
+// {
+// kal_int32 ADCSlope[ADC_MAX_CHANNEL];
+// kal_int32 ADCOffset[ADC_MAX_CHANNEL];
+// }ADC_CALIDATA;
+//#else
+// typedef struct
+// {
+// kal_int32 ADCSlope[ADC_MAX_CHANNEL];
+// kal_int32 ADCOffset[ADC_MAX_CHANNEL];
+// }ADC_CALIDATA;
+//#endif
+///*************************************************************************/
+//#if defined(DRV_MISC_ADC_MEASURE_REMOVE_IRQMASK)
+//// Define to perform ADC race condition check when processing critical data process
+//#define ADC_RACE_CONDITION_CHECK
+//// Define to remove IRQ mask/restore for ADC measurement
+//#define ADC_REMOVE_IRQMASK
+//#endif // #if defined(DRV_MISC_ADC_MEASURE_REMOVE_IRQMASK)
+//
+//#if defined(ADC_RACE_CONDITION_CHECK)
+//extern kal_bool gADC_RC_Check;
+//// MoDIS parser skip start
+//// The following two APIs are private APIs, NOT exported as public APIs
+//extern void ADCRCCheckAndLock(void);
+//extern void ADCRCRelease(void);
+//// MoDIS parser skip end
+//#endif // #if defined(ADC_RACE_CONDITION_CHECK)
+//
+//#if defined(ADC_REMOVE_IRQMASK)
+//#define ADCSAVEANDSETIRQMASK(mask) {}
+//#define ADCRESTOREIRQMASK(mask) {}
+//#else // #if defined(ADC_REMOVE_IRQMASK)
+//#define ADCSAVEANDSETIRQMASK(mask) {mask = SaveAndSetIRQMask();}
+//#define ADCRESTOREIRQMASK(mask) RestoreIRQMask(mask)
+//#endif // #if defined(ADC_REMOVE_IRQMASK)
+//
+///*************************************************************************/
+//
+//// MoDIS parser skip start
+//// The following APIs are private APIs
+//extern kal_uint16 ADC_GetData(kal_uint8 sel);
+//// adc.c
+//extern kal_uint16 ADC_IMM_Data(kal_uint16 channel);
+//extern kal_uint16 ADC_SYNC_Data(kal_uint16 channel);
+//extern void ADC_Init(void);
+//
+//// MoDIS parser skip end
+//
+//#if !defined(DRV_ADC_OFF)
+//#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_ADC_REG_DBG__)
+//#define DRV_ADC_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+//#define DRV_ADC_Reg(addr) DRV_DBG_Reg(addr)
+//#define DRV_ADC_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+//#define DRV_ADC_Reg32(addr) DRV_DBG_Reg32(addr)
+//#define DRV_ADC_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+//#define DRV_ADC_Reg8(addr) DRV_DBG_Reg8(addr)
+//#define DRV_ADC_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+//#define DRV_ADC_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+//#define DRV_ADC_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+//#define DRV_ADC_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+//#define DRV_ADC_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+//#define DRV_ADC_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+//#define DRV_ADC_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+//#define DRV_ADC_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+//#define DRV_ADC_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+//#else
+//#define DRV_ADC_WriteReg(addr,data) DRV_WriteReg(addr,data)
+//#define DRV_ADC_Reg(addr) DRV_Reg(addr)
+//#define DRV_ADC_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+//#define DRV_ADC_Reg32(addr) DRV_Reg32(addr)
+//#define DRV_ADC_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+//#define DRV_ADC_Reg8(addr) DRV_Reg8(addr)
+//#define DRV_ADC_ClearBits(addr,data) DRV_ClearBits(addr,data)
+//#define DRV_ADC_SetBits(addr,data) DRV_SetBits(addr,data)
+//#define DRV_ADC_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+//#define DRV_ADC_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+//#define DRV_ADC_SetBits32(addr,data) DRV_SetBits32(addr,data)
+//#define DRV_ADC_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+//#define DRV_ADC_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+//#define DRV_ADC_SetBits8(addr,data) DRV_SetBits8(addr,data)
+//#define DRV_ADC_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+//#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_ADC_REG_DBG__)
+//
+//#else //!defined(DRV_ADC_OFF)
+//
+//#define DRV_ADC_WriteReg(addr,data)
+//#define DRV_ADC_Reg(addr) drv_dummy_return()
+//#define DRV_ADC_WriteReg32(addr,data)
+//#define DRV_ADC_Reg32(addr) drv_dummy_return()
+//#define DRV_ADC_WriteReg8(addr,data)
+//#define DRV_ADC_Reg8(addr) drv_dummy_return()
+//#define DRV_ADC_ClearBits(addr,data)
+//#define DRV_ADC_SetBits(addr,data)
+//#define DRV_ADC_SetData(addr, bitmask, value)
+//#define DRV_ADC_ClearBits32(addr,data)
+//#define DRV_ADC_SetBits32(addr,data)
+//#define DRV_ADC_SetData32(addr, bitmask, value)
+//#define DRV_ADC_ClearBits8(addr,data)
+//#define DRV_ADC_SetBits8(addr,data)
+//#define DRV_ADC_SetData8(addr, bitmask, value)
+//
+//#endif //!defined(DRV_ADC_OFF)
+
+#endif /*_ADC_H*/
+
diff --git a/mcu/interface/driver/peripheral/adc_cali.h b/mcu/interface/driver/peripheral/adc_cali.h
new file mode 100644
index 0000000..bf37971
--- /dev/null
+++ b/mcu/interface/driver/peripheral/adc_cali.h
@@ -0,0 +1,89 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * adc_cali.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for adc calibration structure.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _ADC_CALI_H
+#define _ADC_CALI_H
+
+#include "drv_features_adc.h"
+
+typedef struct
+{
+//Because of Android may update modem version on user side.
+//Do not change this structure !!
+ kal_int32 ADCSlope[ADC_MAX_CHANNEL];
+ kal_int32 ADCOffset[ADC_MAX_CHANNEL];
+}ADC_CALIDATA;
+
+#endif /*_ADC_CALI_H*/
+
diff --git a/mcu/interface/driver/peripheral/alerter_sw.h b/mcu/interface/driver/peripheral/alerter_sw.h
new file mode 100644
index 0000000..e963b62
--- /dev/null
+++ b/mcu/interface/driver/peripheral/alerter_sw.h
@@ -0,0 +1,238 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * alerter_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for alerter driver and melody adaption.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef ALERTER_SW_H
+#define ALERTER_SW_H
+#include "dcl.h"
+/*
+* The output of Alerter has to sources:
+* one is the enhanced pwm output signal,which is implemented embedded in Alerter module;
+* the other is PDM signal from DSP domain directly.
+*/
+#define pwm 0
+#define pdm 1
+
+/*Select PWM Waveform clock*/
+typedef enum
+{
+ c13_1MHZ, /*13M Hz*/
+ c13_2MHZ, /*13/2M Hz*/
+ c13_4MHZ, /*13/4M Hz*/
+ c13_8MHZ /*13/8M Hz*/
+}ALClock;
+/*
+* select Alerter mode
+* In mode 1, the polarity of alerter output signal according to the relationship between internal counter1 and the programmed threshold will be inverted each time internal
+* counter2 reaches zero.
+*
+* In mode2, each time the internal counter2 count backwards to zero the alerter output signal is normal
+* pwm signal (i.e. signal is low as long as the internal counter1 value is greater than or equals to ALERTER_THRES, and it
+* is high when the internal counter1 is less than ALERTER_THRES) or low state by turns.
+
+* In mode3, the value of internal counter2 has no effect on output signal, i.e. the alerter output signal is low as long as the internal counter1 value is above
+* the programmed threshold and is high the internal counter1 is less than ALERTER_THRES when no matter what value the
+* internal counter2 is.
+*/
+typedef enum
+{
+ m1, /*Mode 1 select*/
+ m2, /*Mode 2 select*/
+ m3 /*Mode 3 select*/
+}ALMode;
+
+typedef void (*DCL_ALERTER_CONFIGURE)(kal_uint32 freq, kal_uint8 duty);
+typedef void (*DCL_ALERTER_START)(void);
+typedef void (*DCL_ALERTER_STOP)(void);
+typedef void (*DCL_ALERTER_PWROPEN)(kal_bool ENABLE);
+typedef void (*DCL_ALERTER_OUTPUT)(kal_uint8 outtype);
+typedef void (*DCL_ALERTER_PLAYALTERNOTES)(kal_bool (*GetNotecallbac)(BuzNoteStruct *Buz), void (*endofAlter)(void));
+typedef void (*DCL_ALERTER_STOPALERTERNOTES)(void);
+typedef void (*DCL_ALERTER_SETBUZVOLUME)(kal_uint8 volumn);
+typedef void (*DCL_ALERTER_CONFIG)(ALMode mode, ALClock Clock);
+typedef void (*DCL_ALERTER_GETCURRENT_LEVEL)(void);
+
+typedef struct
+{
+ DCL_ALERTER_CONFIGURE configure;
+ DCL_ALERTER_START start;
+ DCL_ALERTER_STOP stop;
+ DCL_ALERTER_PWROPEN pwropen;
+ DCL_ALERTER_OUTPUT output;
+ DCL_ALERTER_PLAYALTERNOTES playnotes;
+ DCL_ALERTER_STOPALERTERNOTES stopnotes;
+ DCL_ALERTER_SETBUZVOLUME setbuzvolume;
+ DCL_ALERTER_GETCURRENT_LEVEL getlevel;
+}AlerterDriver_t;
+
+extern void ALERTER_Output(kal_uint8 outtype);
+extern void PlayAlterNotes(kal_bool (*GetNotecallbac)(BuzNoteStruct *Buz), void (*endofAlter)(void));
+extern void StopAlterNotes(void);
+extern void SetBuzVolume(kal_uint8 volumn);
+extern void ALERTER_Config(ALMode mode, ALClock Clock);
+
+
+// MoDIS parser skip start
+// The following APIs are implemented in other dummy API files
+extern void Alter_Configure(kal_uint32 freq, kal_uint8 duty);
+extern void Alter_Start(void);
+extern void Alter_Stop(void);
+extern void ALERTER_PWROPEN(kal_bool ENABLE);
+// MoDIS parser skip end
+
+#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_ALERTER_REG_DBG__)
+#define DRV_ALERTER_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+#define DRV_ALERTER_Reg(addr) DRV_DBG_Reg(addr)
+#define DRV_ALERTER_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define DRV_ALERTER_Reg32(addr) DRV_DBG_Reg32(addr)
+#define DRV_ALERTER_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+#define DRV_ALERTER_Reg8(addr) DRV_DBG_Reg8(addr)
+#define DRV_ALERTER_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+#define DRV_ALERTER_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+#define DRV_ALERTER_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#define DRV_ALERTER_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+#define DRV_ALERTER_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+#define DRV_ALERTER_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+#define DRV_ALERTER_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+#define DRV_ALERTER_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+#define DRV_ALERTER_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+#else
+#define DRV_ALERTER_WriteReg(addr,data) DRV_WriteReg(addr,data)
+#define DRV_ALERTER_Reg(addr) DRV_Reg(addr)
+#define DRV_ALERTER_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define DRV_ALERTER_Reg32(addr) DRV_Reg32(addr)
+#define DRV_ALERTER_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+#define DRV_ALERTER_Reg8(addr) DRV_Reg8(addr)
+#define DRV_ALERTER_ClearBits(addr,data) DRV_ClearBits(addr,data)
+#define DRV_ALERTER_SetBits(addr,data) DRV_SetBits(addr,data)
+#define DRV_ALERTER_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define DRV_ALERTER_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+#define DRV_ALERTER_SetBits32(addr,data) DRV_SetBits32(addr,data)
+#define DRV_ALERTER_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+#define DRV_ALERTER_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+#define DRV_ALERTER_SetBits8(addr,data) DRV_SetBits8(addr,data)
+#define DRV_ALERTER_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+#endif //#if defined(__DRV_COMM_REG_DBG__) && defined(__DRV_ALERTER_REG_DBG__)
+#endif
+
diff --git a/mcu/interface/driver/peripheral/bmd.h b/mcu/interface/driver/peripheral/bmd.h
new file mode 100644
index 0000000..7e72532
--- /dev/null
+++ b/mcu/interface/driver/peripheral/bmd.h
@@ -0,0 +1,356 @@
+ /*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * bmd.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for ring-buffer API.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef BMD_H
+#define BMD_H
+
+#include "drv_comm.h"
+
+typedef struct __BUFFER_INFO
+{
+ volatile kal_uint16 Read; /* @field Current Read index. */
+ volatile kal_uint16 Write; /* @field Current Write index. */
+ volatile kal_uint16 Length; /* @field Length of buffer */
+ volatile kal_uint8 *CharBuffer; /* @field Start of buffer */
+}BUFFER_INFO;
+
+#define ResetFifo(Buffer) (Buffer.Write = Buffer.Read = 0)
+#define BWrite(Buffer) (Buffer->Write)
+#define BRead(Buffer) (Buffer->Read)
+#define BLength(Buffer) (Buffer->Length)
+#define BStartAddr(Buffer) (Buffer->CharBuffer)
+#define BuffWrite(Buffer) (Buffer->CharBuffer+Buffer->Write)
+#define BuffRead(Buffer) (Buffer->CharBuffer+Buffer->Read)
+
+#define BWrite_addr(Buffer) (Buffer.Write)
+#define BRead_addr(Buffer) (Buffer.Read)
+#define BLength_addr(Buffer) (Buffer.Length)
+#define BuffWrite_addr(Buffer) (Buffer.CharBuffer+Buffer.Write)
+#define BuffRead_addr(Buffer) (Buffer.CharBuffer+Buffer.Read)
+#define Buff_EndAddr(Buffer) (Buffer.CharBuffer+Buffer.Length-1)
+#define Buff_StartAddr(Buffer) (Buffer.CharBuffer)
+
+#define Buff_isEmpty 1
+#define Buff_notEmpty 0
+#define Buff_isFull 1
+#define Buff_notFull 0
+#define Buff_PushOK 0
+#define Buff_PushErr 1
+#define Buff_PopOK 0
+#define Buff_PopErr 1
+
+#define Buf_init(_Buffer,_Buffaddr,_uTotalSize) \
+{\
+ BUFFER_INFO *_Buf=_Buffer;\
+ _Buf->Read = 0;\
+ _Buf->Write = 0;\
+ _Buf->Length = _uTotalSize;\
+ _Buf->CharBuffer = _Buffaddr;\
+}\
+
+#define Buf_IsFull(_Buffer,_result) \
+{\
+ BUFFER_INFO *_Buf=_Buffer;\
+ kal_uint16 _tmp = BRead(_Buf);\
+ if (_tmp == 0)\
+ _tmp = BLength(_Buf);\
+ if ( (_tmp-BWrite(_Buf)) == 1)\
+ {\
+ _result = Buff_isFull;\
+ }\
+ else\
+ {\
+ _result = Buff_notFull;\
+ }\
+}\
+
+#define Buf_GetRoomLeft(_Buffer,_RoomLeft) \
+{\
+ BUFFER_INFO *_Buf=_Buffer;\
+ if ( BRead(_Buf) <= BWrite(_Buf) ) \
+ {\
+ _RoomLeft = BLength(_Buf) - BWrite(_Buf) + BRead(_Buf) - 1;\
+ }\
+ else\
+ {\
+ _RoomLeft = BRead(_Buf) - BWrite(_Buf) - 1;\
+ }\
+}\
+
+#define Buf_Push_Multi(_Buffer,_pushDataPointer,_multi,offset) \
+{\
+ BUFFER_INFO *_Buf=_Buffer;\
+ if( (BWrite(_Buf) + _multi) >= BLength(_Buf) ){\
+ kal_mem_cpy(BuffWrite(_Buf), _pushDataPointer + offset, (BLength(_Buf) - BWrite(_Buf))*sizeof(kal_uint8));\
+ kal_mem_cpy(BStartAddr(_Buf) , _pushDataPointer + offset + (BLength(_Buf) - BWrite(_Buf)), (_multi- (BLength(_Buf) - BWrite(_Buf)))*sizeof(kal_uint8));\
+ BWrite(_Buf) = (BWrite(_Buf) + _multi) - BLength(_Buf);\
+ }\
+ else{\
+ kal_mem_cpy(BuffWrite(_Buf), _pushDataPointer + offset, _multi*sizeof(kal_uint8));\
+ BWrite(_Buf) += _multi;\
+}\
+}\
+
+#define Buf_Push(_Buffer,_pushData) \
+{\
+ BUFFER_INFO *_Buf=_Buffer;\
+ *BuffWrite(_Buf) = _pushData;\
+ if(BWrite(_Buf) >= (BLength(_Buf) - 1))\
+ {\
+ BWrite(_Buf) = 0;\
+ }\
+ else\
+ {\
+ BWrite(_Buf)++;\
+ }\
+}\
+
+#define Buf_GetBytesAvail(_Buffer,_BytesAvail) \
+{\
+ BUFFER_INFO *_Buf = _Buffer;\
+ _BytesAvail = 0;\
+ if (BWrite(_Buf) >= BRead(_Buf))\
+ _BytesAvail = BWrite(_Buf) - BRead(_Buf);\
+ else\
+ _BytesAvail = BLength(_Buf) - BRead(_Buf) + BWrite(_Buf); \
+}\
+
+#define Buf_GetBytesAvail_DMA(_Buffer,_BytesAvail) \
+{\
+ BUFFER_INFO *_Buf = _Buffer;\
+ _BytesAvail = 0;\
+ if (BWrite(_Buf) >= BRead(_Buf))\
+ _BytesAvail = BWrite(_Buf) - BRead(_Buf);\
+ else\
+ _BytesAvail = BLength(_Buf) - BRead(_Buf); \
+}\
+
+#define Buf_Pop_Multi(_Buffer,_popDataPointer,_multi,offset) \
+{\
+ BUFFER_INFO *_Buf=_Buffer;\
+ if( (BRead(_Buf) + _multi) >= BLength(_Buf) ){\
+ kal_mem_cpy(_popDataPointer + offset, BuffRead(_Buf), (BLength(_Buf) - BRead(_Buf))*sizeof(kal_uint8));\
+ kal_mem_cpy(_popDataPointer + offset + (BLength(_Buf) - BRead(_Buf)), BStartAddr(_Buf), (_multi- (BLength(_Buf) - BRead(_Buf)))*sizeof(kal_uint8));\
+ BRead(_Buf) = BRead(_Buf) + _multi - BLength(_Buf) ;)\
+ else{\
+ kal_mem_cpy(_popDataPointer + offset, BuffRead(_Buf), _multi);\
+ BRead(_Buf) += _multi;}\
+}\
+
+#define Buf_Pop(_Buffer,_popData) \
+{\
+ BUFFER_INFO *_Buf = _Buffer;\
+ _popData= *BuffRead(_Buf);\
+ BRead(_Buf)++;\
+ if (BRead(_Buf) >= BLength(_Buf))\
+ {\
+ BRead(_Buf) -= BLength(_Buf);\
+ }\
+}\
+
+/* should be deleted */
+#define Buf_IsEmpty(_Buffer,_result) \
+{\
+ BUFFER_INFO *_Buf = _Buffer;\
+ if ( BRead(_Buf) == BWrite(_Buf) ) \
+ {\
+ _result = Buff_isEmpty;\
+ }\
+ else\
+ {\
+ _result = Buff_notEmpty;\
+ }\
+}\
+
+/* void Get32FromBuff(BUFFER_INFO *Buf,kal_uint32 DATA) */
+#define Get32FromBuf(_Buffer,_DATA) \
+{\
+ BUFFER_INFO *_Buf = _Buffer;\
+ kal_uint8 _tmp,_index;\
+ kal_uint32 _tmp32;\
+ _DATA =0;\
+ for (_index =0;_index < 4;_index++)\
+ {\
+ Buff_Pop(_Buf,&_tmp);\
+ _tmp32 = (kal_uint32)_tmp;\
+ (_DATA) |= (_tmp32 << (8*_index));\
+ }\
+}\
+
+/*void Put32toBuff(BUFFER_INFO *Buf,kal_uint32 *DATA)*/
+#define Put32toBuf(_Buffer,_DATA) \
+{\
+ BUFFER_INFO *_Buf = _Buffer;\
+ kal_uint8 _tmp,_index;\
+ kal_uint32 _tmp32;\
+ for (_index =0;_index < 4;_index++)\
+ {\
+ _tmp32 = ((*_DATA) >> (8*_index));\
+ _tmp = (kal_uint8)_tmp32;\
+ Buff_Push(_Buf,&_tmp);\
+ }\
+}\
+
+#define Buf_Flush(_Buffer) \
+{\
+ BUFFER_INFO *_Buf = _Buffer;\
+ _Buf->Write = _Buf->Read = 0;\
+}
+
+#define Buf_look(_Buffer,_popData,_num) \
+{\
+ BUFFER_INFO *_Buf = _Buffer;\
+ kal_uint8 _index;\
+ kal_uint16 _tmp;\
+ _tmp = BRead(Buf);\
+ for(_index=0;_index<_num;_index++)\
+ {\
+ *_popData= *(Buf->CharBuffer+_tmp);\
+ _tmp++;\
+ if (_tmp >= BLength(Buf))\
+ {\
+ _tmp -= BLength(Buf);\
+ }\
+ }\
+}
+
+// MoDIS parser skip start
+#if 1
+extern void Buff_init(BUFFER_INFO *Buf,kal_uint8 *Buffaddr, kal_uint16 uTotalSize);
+extern void Buff_Push(BUFFER_INFO *Buf,kal_uint8 *pushData);
+extern void Buff_Pop(BUFFER_INFO *Buf,kal_uint8 *popData);
+extern kal_uint8 Buff_IsEmpty(BUFFER_INFO *Buf);
+extern kal_uint8 Buff_IsFull (BUFFER_INFO *Buf);
+extern kal_uint16 Buff_GetRoomLeft (BUFFER_INFO *Buf);
+extern kal_uint16 Buff_GetBytesAvail (BUFFER_INFO *Buf);
+extern kal_uint16 Buff_GetLength(BUFFER_INFO *Buf);
+extern void Buff_Flush (BUFFER_INFO *Buf);
+extern void Buff_look(BUFFER_INFO *Buf,kal_uint8 *popData,kal_uint8 num);
+extern void Get32FromBuff(BUFFER_INFO *Buf,kal_uint32 *DATA);
+extern void Put32toBuff(BUFFER_INFO *Buf,kal_uint32 *DATA);
+extern void MemCPY(kal_uint8 *dst,kal_uint8 *src,kal_uint32 len);
+extern void MemSET(kal_uint8 *dst,kal_uint8 data,kal_uint32 len);
+#endif
+// MoDIS parser skip end
+
+#endif
+
diff --git a/mcu/interface/driver/peripheral/bmt.h b/mcu/interface/driver/peripheral/bmt.h
new file mode 100644
index 0000000..df34a3f
--- /dev/null
+++ b/mcu/interface/driver/peripheral/bmt.h
@@ -0,0 +1,857 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * bmt.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for Battery Management Task.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _BMT_H
+#define _BMT_H
+
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "dcl.h"
+#include "adc_cali.h"
+
+#define ADC_BMT_VBAT 0
+#define ADC_BMT_VISENSE 1
+#define ADC_BMT_VBATTMP 2
+#define ADC_BMT_VCHARGER 3
+#define ADC_BMT_MAX_CHANNEL_TOTAL 4
+//#define BMT_MAX_CHANNEL_TOTAL ADC_BMT_MAX_CHANNEL_TOTAL // backward compatible
+
+/*
+#ifdef __BMT_CHECK_CHARGER__
+#define BMT_MAX_CHANNEL 4
+#else
+#define BMT_MAX_CHANNEL 3
+#endif
+*/
+#define BMT_ADC_VBAT 0
+#define BMT_ADC_VISENSE 1
+#define BMT_ADC_VBATTMP 2
+#define BMT_ADC_VCHARGER 3
+#define BMT_ADC_MAX_CHANNEL_TOTAL 4
+
+/*precharge threshold*/
+#define BMT_PRECHARGE_THRESHOLD 3300000
+
+#if defined(__TC01__)
+#define DRV_BMT_NONE_USB_POWER_ON /* use charging power on instead of USB power on*/
+#define __DRV_BMT_PRECHARGE_TO_FULL_DIRECTLY__
+#endif // #if defined(__TC01__)
+
+/*BatType*/
+#define LIBAT 0
+#define NIBAT 1
+
+/*extern charger state*/
+#define DETECTCHRIN 0x0
+#define DETECTCHROUT !DETECTCHRIN
+
+/*BMT Minor STATE. When Charger is plugged in, charge is enable or not?*/
+#define PMIC_CHARGEOFF 0 /*pmictrl_state*/
+#define PMIC_CHARGEON 1
+
+/*MS Mode*/
+#define idle_mode 0
+#define talk_mode 1
+#define swoff_mode 2
+
+
+#define BMT_HIGH_VCHG_THRESHOLD 100000
+
+#if defined(DRV_BMT_HIGH_VCHG_ADAPTIVE_CHARGE_CURRENT_SUPPORT)
+#define VCHG_VOL_LEVEL 7
+#define VCHG_PARAMTER_COUNT 3
+
+typedef struct{
+ kal_uint32 VCHG_HV_VTH;
+ kal_int32 HIGH_VCHG_TABLE[VCHG_VOL_LEVEL][VCHG_PARAMTER_COUNT];
+}bmt_customized_high_vchg_struct;
+
+extern kal_bool High_Vchg_Safety_Timer_Set;
+extern bmt_customized_high_vchg_struct *bmt_high_vchg_para;
+extern kal_uint32 bmt_total_charge_time;
+extern kal_bool bmt_safety_timer_config;
+extern kal_int32 Pre_VCharge_AVG;
+extern kal_int32 Cur_VCharge_MAX;
+extern bmt_customized_high_vchg_struct *bmt_get_customized_high_vchg_para(void);
+
+#endif // End of #if defined(DRV_BMT_HIGH_VCHG_ADAPTIVE_CHARGE_CURRENT_SUPPORT)
+
+typedef enum{
+ CHARGER_PRESENT,
+//#if defined(__CHINA_CHARGER_STANDARD__)
+ CHARGER_PRESENT_NON,
+//#endif
+ USB_PRESENT,
+ NO_PRESENT
+}charger_usb_present_enum;
+
+typedef enum{
+ BMT_AC_CHR,
+ BMT_USB_CHR
+}bmt_charger_type;
+
+typedef enum {
+ bmt_chr_in=0,
+ bmt_chr_out,
+ bmt_chr_uninit = 0xff
+}Charger_Status;
+
+typedef enum {
+ VBAT_UEM_CHR_OUT=0,
+ VBAT_UEM_CHR_OUT_FIRST=1,
+ VBAT_UEM_CHR_IN=2,
+ VBAT_UEM_CHR_IN_FISRT=3
+}VBAT_UEM_CHR_ENUM;
+
+typedef enum
+{
+ CHR_CURRENT_50=0,
+ CHR_CURRENT_90,
+ CHR_CURRENT_150,
+ CHR_CURRENT_225,
+ CHR_CURRENT_300,
+ CHR_CURRENT_450,
+ CHR_CURRENT_650,
+ CHR_CURRENT_800
+}pmic_charging_current;
+
+typedef struct {
+ kal_uint8 bat_state;
+ kal_uint8 pmictrl_state; /*pmic control on,off*/
+ kal_uint8 call_state; /*mobile state*/
+ // kal_uint8 PWRon;
+ kal_uint8 BatType;
+ kal_uint8 EINT2STATE;
+ kal_uint8 highfull;
+ VBAT_UEM_CHR_ENUM VBAT_UEM; // state of UEM VBAT measurement
+ kal_hisrid hisr;
+} BMTStruct;
+
+typedef struct {
+ kal_int32 VBAT;
+ kal_int32 ICHARGE;
+ kal_int32 BATTMP;
+ kal_int32 VCHARGER;
+ kal_int32 ISense_Offset;
+ //kal_uint8 BATTYPE;
+} BATPHYStruct;
+
+
+// For external charger mechanism integration
+
+// The enum is to indicate whether the charging factor is measured by HOST or Charger device
+typedef enum
+{
+ CHR_FACTOR_MEASURE_NONE = 0x00000000, // Both NOT support, TBD
+ CHR_FACTOR_MEASURE_BY_HOST = 0x00000001, // BIT00, HOST measure the specific charging factor
+ CHR_FACTOR_MEASURE_BY_CHARGER_DEV = 0x00000002 // BIT01, Charger device measure the specific charging factor
+
+}bmt_chr_fac_measure_support_enum;
+
+// The enum is to indicate whether the charging factor error check is done by HOST or charger device
+typedef enum
+{
+ BMT_CHR_FACTOR_CHECK_NONE = 0x00000000, // Both NOT support, TBD
+ BMT_CHR_FACTOR_CHECK_BY_HOST = 0x00000001, // BIT00, HOST perform charging factor error check
+ BMT_CHR_FACTOR_CHECK_BY_CHARGER_DEV = 0x00000002 // BIT01, Charger device perform charging facotr error check
+
+}bmt_chr_fac_check_support_enum;
+
+// The enum defines the charging factors that charging process need to check
+typedef enum
+{
+ BMT_CHR_FACTOR_VBAT, // Charging factor: VBAT
+ BMT_CHR_FACTOR_ISENSE, // Charging factor: VISENSE
+ BMT_CHR_FACTOR_BATTMP, // Charging factor: VBAT temperature
+ BMT_CHR_FACTOR_VCHARGER, // Charging factor: VCHARGER
+ BMT_CHR_FACTOR_CHARGER_OVP, // Charging factor: Charger OVP
+ BMT_CHR_FACTOR_CHARGE_FULL, // Charging factor: Charge full
+ BMT_CHR_FACTOR_UNDER_EXTREMETMP, // Charging factor: Extreme temperature
+ BMT_CHR_FACTOR_CHARGE_EXTREMETMP_FULL, // Charging factor: Charge full under extreme temperature
+ BMT_CHR_FACTOR_CHARGE_EXTREMETMP_RECHARGE, // Charging factor: Should recharge under extreme temperature
+ BMT_CHR_FACTOR_HOLD, // Charging factor: Charging hold
+ BMT_CHR_FACTOR_CHR_BATT_STATE, // Charging factor: charging state: PRE, FAST(CC), TOPOFF(CV), FULL ...
+
+ BMT_CHR_FACTOR_MAX
+}bmt_chr_fac_enum;
+
+typedef struct
+{
+
+ // Driver init
+ // Called at drv init phase
+ void (*drv_init)(void);
+
+ // Called at pmic adpt layer init phase
+ // The phase what scheduler is running(BMT task is created)
+ void (*enable_intr)(void);
+
+ // Control charge enable/disable
+ // Called at any time, any context
+ kal_bool (*charge_enable)(kal_bool enable);
+
+ // The unit is in mA ==> 1000 means 1A
+ // Called at any time, any context
+ // a most close, but not exceeded charge current will be selected
+ // 500mA means can NOT large than 500mA, but most close to 500mA
+ kal_bool (*set_charge_current)(kal_int32 charge_current);
+
+ // Whether the external charger can measure the passed-in charging factor
+ bmt_chr_fac_measure_support_enum (*get_chr_fac_measure_support)(bmt_chr_fac_enum chr_fac);
+
+ // Whether the external charger can check the passed-in charging factor
+ bmt_chr_fac_check_support_enum (*get_chr_fac_check_support)(bmt_chr_fac_enum chr_fac);
+
+ // Pass information to charger device
+ // Charger device can calculate the charger status through the passed-in info
+ void (*check_chr_status)(BATPHYStruct *pBatPhysStat);
+
+ // Charger return calculated charger status
+ // Usually, charger device should keep the chr status before reset_chr_status() is called
+ // The return kal_uint32 is union of all charging factors status
+ kal_uint32 (*get_chr_status)(void);
+
+ // The return unit is uV ==> 1000000 means 1.0V
+ // The passed-in parameter is the information measured by HOST,
+ // ext charger driver need this info to calculate
+ kal_int32 (*get_vbat)(BATPHYStruct *pBatPhysStat);
+
+ // The return unit is uA ==> 1000000 means 1A
+ // The passed-in parameter is the information measured by HOST,
+ // ext charger driver need this info to calculate
+ kal_int32 (*get_isense)(BATPHYStruct *pBatPhysStat);
+
+ // The return unit is uV ==> 1000000 means 1.0V
+ // The passed-in parameter is the information measured by HOST,
+ // ext charger driver need this info to calculate
+ kal_int32 (*get_vcharger)(BATPHYStruct *pBatPhysStat);
+
+ // Return the calculated NTC value of battery temperature
+ // The passed-in parameter is the information measured by HOST,
+ // ext charger driver need this info to calculate
+ kal_int32 (*get_bat_temp)(BATPHYStruct *pBatPhysStat);
+
+ // Return if charge full
+ // The unit is vbat is uV ==> 1000000 means 1.0V
+ // Return KAL_TRUE: Charge full
+ // Return KAL_FALSE: Not charge full
+ kal_bool (*get_charge_full)(kal_int32 vbat);
+
+ // Return if it's under extreme temperature
+ // Return KAL_TRUE: It's under extreme temperature
+ // Return KAL_FALSE: It's NOT under extreme temperature
+ kal_bool (*get_charge_under_extremetmp)(kal_int32 battmp);
+
+ // Return if charge full when under extreme temperature
+ // The unit is vbat is uV ==> 1000000 means 1.0V
+ // Return KAL_TRUE: Charge full
+ // Return KAL_FALSE: Not charge full
+ kal_bool (*get_charge_extremetmp_full)(kal_int32 vbat);
+
+ // Return if charge should recharge when under extreme temperature
+ // The unit is vbat is uV ==> 1000000 means 1.0V
+ // Return KAL_TRUE: Should recharge
+ // Return KAL_FALSE: Should NT recharge
+ kal_bool (*get_charge_extremetmp_recharge)(kal_int32 vbat);
+
+ // Return KAL_TRUE: Need to hold charging
+ // Return KAL_FALSE: Do NOT need to hold charging
+ // The condition to hold charging: Talking mode ...
+ kal_bool (*get_charge_hold)(BATPHYStruct *pBatPhysStat);
+
+ // Whether the external charger can handle the specific charging battery state
+ bmt_chr_fac_check_support_enum(*get_chr_batt_state_transit_support)(kal_uint32 curr_chr_batt_state);
+
+ // Perform charging battery state transit
+ // curr_chr_batt_state: Current state
+ // chr_on: Current CHR_EN state
+ void (*chr_batt_state_transit)(kal_uint32 curr_chr_batt_state, kal_bool chr_en);
+
+ // Get current charging battery state PRE, FAST(CC), TOPOFF(CV), FULL, ...
+ kal_uint32 (*get_curr_chr_batt_state)(BATPHYStruct *pBatPhysStat);
+
+ // Get custom charge current according to specific charger
+ kal_uint32 (*get_specific_chr_current)(bmt_charger_type charger);
+
+ // Whether the vbat is higher than specific full check vaule or not
+ // Return KAL_TRUE: higher than specific full voltage
+ // Return KAL_FALSE: lower than specific full voltage
+ kal_bool (*get_vbat_specific_full_voltage_state)(kal_int32 vbat); //__DRV_BMT_CHARGING_COMPLETE_MSG__
+
+}bmt_ext_charger;
+
+// External charger custom table V1.0
+typedef struct{
+ // Control enable/disable charger
+ void (*charge_enable)(kal_bool enable);
+
+ // Set charge current
+ // The unit is mA ==> 1000 means 1A
+ void (*charge_current)(kal_int32 current);
+
+ // Return KAL_TRUE: Charger think battery is full
+ // Return KAL_FALSE: Charger think battery is NOT full
+ kal_bool (*charge_full_ind)(kal_int32 vbat);
+
+ // Return KAL_TRUE: Charger thing it's under extreme temperature
+ // Return KAL_FALSE: Charger thing it's NOT under extreme temperature
+ kal_bool (*charge_under_extremetmp_ind)(kal_int32 battmp);
+
+ // Return KAL_TRUE: Charger think battery is full if it's under extreme temperature
+ // Return KAL_FALSE: Charger think battery is NOT if it's full under extreme temperature
+ kal_bool (*charge_extremetmp_full_ind)(kal_int32 vbat);
+
+ // Return KAL_TRUE: Charger think battery should be recharged if it's under extreme temperature
+ // Return KAL_FALSE: Charger think battery should NOT be recharged if it's under extreme temperature
+ kal_bool (*charge_extremetmp_recharge_ind)(kal_int32 vbat);
+
+ // Number of charge current level (Ex: 100mA, 150mA, 500mA ...)
+ kal_uint32 charge_current_num;
+
+ // The current must be listed from largest to smallest
+ // Ex: 0: 500mA; 1: 250mA; 2: 100mA ...
+ kal_uint32 *charge_current_table;
+
+ // Return the custom charge current for specific charger type, the unit is mA
+ kal_uint32 (*get_custom_charge_current)(bmt_charger_type charger);
+
+ // Whether the charge source is good
+ // Return KAL_TRUE: Charge source is good
+ // Return KAL_FALSE: Charge source is NOT good
+ kal_bool (*charge_source_good)(void);
+
+ // Whether the vbat is higher than specific full check vaule or not
+ // Return KAL_TRUE: higher than specific full voltage
+ // Return KAL_FALSE: lower than specific full voltage
+ kal_bool (*vbat_specific_full_check_voltage)(kal_int32 vbat); //__DRV_BMT_CHARGING_COMPLETE_MSG__
+
+}bmt_ext_charger_custom_config;
+
+
+// For external charger mechanism integration
+
+
+// For external charger detection integration
+typedef struct
+{
+ // This API report charger in/out and AC or USB type together
+ // This API may be called at anytime
+ // Ex: Before scheduler is running (Boot init phase)
+ // Called at boot time (No scheduler is running)
+ // Called in HISR (Drv_HISR and system HISR)
+ // Called in Task
+ charger_usb_present_enum (*det_charger_present)(void);
+
+ // This API is for PWIC to register HISR handler for charger
+ // PWIC will use det_charger_present() to determine whether it is in/out
+ void (*reg_chr_hisr)(void (chr_hisr_callback)(void));
+
+ // This API is for PWIC to register HISR handler for usb
+ // PWIC will use det_charger_present() to determine whether it is in/out
+ void (*reg_usb_hisr)(void (usb_hisr_callback)(void));
+
+ // This API is to set S/W debounce time for charger cable
+ // The uint of deb_time is in 10ms (GPT tick)
+ void (*set_chr_deb_time)(kal_uint32 deb_time);
+
+ // This API is to set S/W debounce time for usb cable
+ // The uint of deb_time is in 10ms (GPT tick)
+ void (*set_usb_deb_time)(kal_uint32 deb_time);
+
+ // This API is to report whether USB detection is supported or NOT
+ kal_bool (*support_usb_det)(void);
+
+ // Init the external charger detection mechanism
+ // The API is called at boot phase
+ // After this call, we should be able to call det_charger_present()
+ // Provider need to guarantee this
+ void (*drv_init)(void);
+
+ // The API is called at pmic adpt layer init phase
+ void (*enable_intr)(void);
+
+}bmt_ext_charger_det;
+
+typedef enum
+{
+ EXT_CABLE_PATH_CHARGER,
+ EXT_CABLE_PATH_STD_USB,
+ EXT_CABLE_PATH_HIGH_CURRENT_USB,
+ EXT_CABLE_PATH_UART,
+ EXT_CABLE_PATH_EARPHONE,
+ EXT_CABLE_PATH_TV_OUT,
+ EXT_CABLE_PATH_USB_OTG,
+ EXT_CABLE_PATH_FAC_UART,
+ EXT_CABLE_PATH_FAC_USB,
+ EXT_CABLE_PATH_CS_CHARGER, // Customer specific charger
+ EXT_CABLE_PATH_MAX
+}ext_cable_path_enum;
+
+typedef struct
+{
+ // Factory mode API
+ // Force switch external cable to specific path for test
+ void (*set_path)(ext_cable_path_enum path);
+
+ // Factory mode API
+ // Return current external cable path
+ ext_cable_path_enum (*get_curr_path)(void);
+
+ // ASSERT mode API
+ // Called when system enter ASSERT,
+ // the ext cable mechanism should switch cable path for memory dump
+ void (*ext_cable_force_set_path)(ext_cable_path_enum path);
+
+ // API for specific workaround: Turn on/off ext cable path
+ void (*ext_cable_WA_set_path)(ext_cable_path_enum path, kal_bool on);
+
+}ext_cable_det_fac_if;
+
+
+// For external charger detection integration
+
+extern kal_uint8 bmt_bmtid_adc_handle[BMT_ADC_MAX_CHANNEL_TOTAL];
+extern kal_uint8 bmt_adc_handle;
+
+// MoDIS parser skip start
+// The following APIs are impmemented in custom folder, which will be inclucded in MoDIS
+/*usb charge*/
+extern kal_bool bmt_support_usb_charge(void);
+extern kal_int32 bmt_get_chr_usb_detect_volt(void);
+// MoDIS parser skip end
+
+// MoDIS parser skip start
+/*charing parameters*/
+// MoDIS parser skip end
+
+#if defined(__GENERAL_EXTERNAL_CHARGER__)
+extern bmt_ext_charger *ext_charger; // Variable in pwic.c
+extern bmt_ext_charger *bmt_get_ext_charger(void);
+extern bmt_ext_charger_custom_config *bmt_ext_charger_get_custom_config(void);
+#endif // #if defined(__GENERAL_EXTERNAL_CHARGER__)
+
+extern ext_cable_det_fac_if *custom_get_ext_cable_fac(void);
+
+#if defined(__DRV_EXT_CHARGER_DETECTION__)
+extern bmt_ext_charger_det *ext_charger_det;
+extern bmt_ext_charger_det *bmt_custom_get_ext_charger_det(void);
+#endif // #if defined(__DRV_EXT_CHARGER_DETECTION__)
+
+extern kal_uint8 BMT_MAX_CHANNEL; // The ADC channel number in BMT (Used for charging factor monitoring)
+extern BMTStruct BMT;
+
+#if defined(DRV_ADC_CALIBRATION_EFUSE)
+extern kal_bool bmt_read_calibration_data(ADC_CALIDATA *adc_cali);
+#endif //#if defined(DRV_ADC_CALIBRATION_EFUSE)
+
+extern void BMT_VbatInHISR(void);
+extern kal_bool bmt_is_bat_on(void);
+
+extern kal_bool BMT_ObtainBMTPHYSTAT(BATPHYStruct *BATPHYS);
+extern void bmt_chr_force_enable(kal_bool enable);
+extern kal_bool bmt_is_chr_valid(void);
+extern kal_bool bmt_get_chr_cv_det(void);
+#endif // End of #ifndef _BMT_H
+
diff --git a/mcu/interface/driver/peripheral/dcl.h b/mcu/interface/driver/peripheral/dcl.h
new file mode 100644
index 0000000..3ec8dfd
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl.h
@@ -0,0 +1,1395 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer).
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __DCL_H__
+#define __DCL_H__
+
+
+#if !defined(GEN_FOR_PC) && !defined(NVRAM_AUTO_GEN)
+#ifdef __CATEGORY_MODEM__
+//#error drv_features.h include by modem detection
+#endif
+#endif //!defined(GEN_FOR_PC) && !defined(NVRAM_AUTO_GEN)
+
+
+
+
+/* For solve build error after defined __CATEGORY_MODEM__ */
+/*
+#ifdef __CATEGORY_MODEM__ // doesn't need to include these module
+//#define NONE_MODEM_BMT
+//#define NONE_MODEM_RTC
+#define NONE_MODEM_I2C
+#define NONE_MODEM_AUX
+//#define NONE_MODEM_KBDH
+//#define NONE_MODEM_KBD
+#define NONE_MODEM_PWM
+#define NONE_MODEM_ALERTER
+#define NONE_MODEM_TS
+#define NONE_MODEM_SD
+#define NONE_MODEM_USBD
+#define NONE_MODEM_OTG
+#define NONE_MODEM_IRDA
+//#define NONE_MODEM_PW
+#define NONE_MODEM_PXS
+#endif
+*/
+
+//#define NONE_MODEM_IDC
+
+//ZTE73
+//#ifdef __MODEM_COMPONENT__ // doesn't need to include these module in modem ip
+//#define NONE_MODEM_BMT // l4misc
+//#define NONE_MODEM_RTC // l4misc
+//#define NONE_MODEM_KBDH // l4_classb
+//#define NONE_MODEM_KBD // l4_classb
+//#define NONE_MODEM_PW // l4_classb
+//#endif
+
+//NAMI76
+//#ifdef __MODEM_PRODUCT__ // doesn't need to include these module in modem product
+//#define NONE_MODEM_BMT // l4misc
+//#define NONE_MODEM_RTC // l4misc
+//#define NONE_MODEM_KBDH // l4misc l4_calssb
+//#define NONE_MODEM_KBD // l4misc l4_classb
+//#define NONE_MODEM_PW // l4misc peripheral l4_classb
+//#endif
+
+
+
+typedef char DCL_CHAR;
+typedef signed char DCL_INT8;
+typedef signed short DCL_INT16;
+typedef signed long DCL_INT32;
+
+typedef unsigned char DCL_UCHAR;
+typedef unsigned char DCL_UINT8;
+typedef unsigned short DCL_UINT16;
+typedef unsigned long DCL_UINT32;
+
+#if !defined(GEN_FOR_PC) && defined(_MSC_VER)
+ typedef signed __int64 DCL_INT64;
+typedef unsigned __int64 DCL_UINT64;
+#else
+ typedef unsigned long long DCL_UINT64;
+ typedef signed long long DCL_INT64;
+#endif
+
+typedef double DCL_DOUBLE;
+typedef int DCL_INT;
+
+//typedef int DCL_BOOL;
+typedef enum
+{
+ DCL_FALSE = 0,
+ DCL_TRUE
+}DCL_BOOLEAN;
+
+#define DCL_BOOL DCL_BOOLEAN
+
+#define DCL_DEFINITION_STRUCT
+
+#ifndef NONE_MODEM_GPT
+#include "dcl_gpt.h"
+#endif
+#ifndef NONE_MODEM_GPIO
+#include "dcl_gpio.h"
+#endif
+#ifndef NONE_MODEM_UART
+#include "dcl_uart.h"
+#endif
+#ifndef NONE_MODEM_WDT
+#include "dcl_wdt.h"
+#endif
+#ifndef NONE_MODEM_ADC
+#include "dcl_adc.h"
+#endif
+#ifndef NONE_MODEM_BMT
+#include "dcl_bmt.h"
+#endif
+#ifndef NONE_MODEM_PFC
+#include "dcl_pfc.h"
+#endif
+#ifndef NONE_MODEM_RTC
+#include "dcl_rtc.h"
+#endif
+#ifndef NONE_MODEM_I2C
+#include "dcl_i2c.h"
+#endif
+#ifndef NONE_MODEM_AUX
+#include "dcl_aux.h"
+#endif
+#if !defined(NONE_MODEM_PWM) && !defined(NONE_MODEM_ALERTER)
+#include "dcl_pwm.h"
+#endif
+#ifndef NONE_MODEM_KBDH
+#include "DclH_kbd.h"
+#endif
+#ifndef NONE_MODEM_KBD
+#include "DclS_kbd.h"
+#endif
+#ifndef NONE_MODEM_STS
+#include "dcl_sts.h"
+#endif
+#ifndef NONE_MODEM_MSDC
+#include "dcl_msdc.h"
+#endif
+#ifndef NONE_MODEM_USB
+#include "dcl_usb_drv.h"
+#endif
+#ifndef NONE_MODEM_USBD
+#include "dcl_usb_hcd.h"
+#endif
+#ifndef NONE_MODEM_OTG
+#include "dcl_otg_drv.h"
+#endif
+#ifndef NONE_MODEM_IRDA
+#include "dcl_irda.h"
+#endif
+#ifndef NONE_MODEM_SIM
+#include "dcl_sim.h"
+#endif
+#ifndef NONE_MODEM_PMU
+#include "dcl_pmu.h"
+#endif
+#ifndef NONE_MODEM_PW
+#include "dcl_pw.h"
+#endif
+#ifndef NONE_MODEM_CHR_USB_DET
+#include "dcl_chr_det.h"
+#endif
+#ifndef NONE_MODEM_SPMI
+#include "dcl_spmi.h"
+#endif
+#ifndef NONE_MODEM_PXS
+#include "dcl_pxs.h"
+#endif
+#ifndef NONE_MODEM_SIM_GPIO
+#include "dcl_sim_gpio.h"
+#endif
+#ifndef NONE_MODEM_F32K_CLK
+#include "dcl_f32k_clk.h"
+#endif
+#ifndef NONE_MODEM_IDC
+#include "dcl_idc.h"
+#endif
+#ifndef NONE_MTAD
+#include "dcl_mtad.h"
+#endif
+
+
+/*******************************************************************************
+ * DCL_STATUS
+ *******************************************************************************/
+#if defined(STATUS_OK)
+#undef STATUS_OK
+#endif
+
+#if defined(STATUS_FAIL)
+#undef STATUS_FAIL
+#endif
+
+typedef DCL_INT32 DCL_STATUS;
+typedef enum
+{
+ STATUS_OK = 0,
+ STATUS_FAIL = -1,
+ STATUS_INVALID_CMD = -2,
+ STATUS_UNSUPPORTED = -3,
+ STATUS_NOT_OPENED = -4,
+ STATUS_INVALID_EVENT = -5,
+ STATUS_INVALID_DCL_HANDLE = -6,
+ STATUS_INVALID_CTRL_DATA = -7,
+ STATUS_INVALID_CONFIGURATION = -8,
+ STATUS_INVALID_ARGUMENT = -9,
+ STATUS_ERROR_TIMEOUT = -10,
+ STATUS_ERROR_CRCERROR = -11,
+ STATUS_ERROR_READONLY = -12,
+ STATUS_ERROR_WRONG_STATE = -13,
+ STATUS_INVALID_DEVICE = -14,
+ STATUS_ALREADY_OPENED = -15,
+ STATUS_SET_VFIFO_FAIL = -16,
+ STATUS_INVALID_OPERATION = -17,
+ STATUS_DEVICE_NOT_EXIST = -18,
+
+ //*/ I2C DCL added /*//
+ STATUS_DEVICE_NOT_SUPPORT_DMA = -19,
+ STATUS_DEVICE_IS_BUSY = -20,
+ STATUS_ACKERR = -21,
+ STATUS_HS_NACKERR = -22,
+
+ STATUS_BUFFER_EMPTY = 1
+} DCL_STATUS_T;
+
+/*******************************************************************************
+ * DCL_DEV
+ *******************************************************************************/
+typedef DCL_UINT16 DCL_DEV;
+typedef enum
+{
+#ifndef NONE_MODEM_UART
+ DCL_UART_GROUP_START = 0,
+ DCL_UART_DEV // Marco defined in dcl_uart.h
+#endif
+#ifndef NONE_MODEM_GPIO
+ DCL_GPIO_GROUP_START = 0x100,
+ DCL_GPIO,
+ DCL_GPO,
+ DCL_GPIO_CLK,
+#endif
+#ifndef NONE_MODEM_GPT
+ DCL_GPT_GROUP_START = 0x200,
+ DCL_GPT_CB,
+ DCL_GPT_CB2,
+ DCL_GPT_BusyWait,
+ DCL_GPT_FreeRUN3,
+ DCL_GPT_FreeRUN4,
+ DCL_GPT_DEBUG,
+ DCL_XGPT,
+ DCL_GPT_CB_MS, /* dongming add for 1ms GPT */
+ DCL_LITEGPT_CB_ETMR, /* way add for ETMR */
+ DCL_GPT_CB_LOGGING, /* way add for LOGGING 1ms GPT */
+ DCL_GPT_C2K_OS, /* way add for C2K 1us OneShot timer */
+ DCL_GPT_C2K_AR, /* way add for C2K 1us Auto Repeat timer */
+ DCL_GPT_DSP, /* way add for DSP 1us OneShot timer */
+ DCL_GPT_DSCC_0, /* Alva add for DSCC 1us OneShot timer */
+ DCL_GPT_DSCC_1, /* Alva add for DSCC 1us OneShot timer */
+ DCL_GPT_DPCOPRO,
+#endif
+#ifndef NONE_MODEM_PWM
+ DCL_PWM_GROUP_START = 0x300,
+ DCL_PWM1,
+ DCL_PWM2,
+ DCL_PWM3,
+ DCL_PWM4,
+ DCL_PWM5,
+ DCL_PWM6,
+#endif
+ DCL_PWM_GROUP_END = 0x400,
+ DCL_REST_GROUP_START = DCL_PWM_GROUP_END,
+#ifndef NONE_MODEM_BMT
+ DCL_BMT_GROUP_START = 0x500,
+ DCL_BMT,
+#endif
+#ifndef NONE_MODEM_PFC
+ DCL_PFC_GROUP_START = 0x600,
+ DCL_PFC,
+#endif
+#ifndef NONE_MODEM_RTC
+ DCL_RTC_GROUP_START = 0x700,
+ DCL_RTC,
+#endif
+#ifndef NONE_MODEM_ADC
+ DCL_ADC_GROUP_START = 0x800,
+ DCL_ADC,
+#endif
+#ifndef NONE_MODEM_PMU
+ DCL_PMU_GROUP_START = 0x900,
+ DCL_PMU,
+#endif
+#ifndef NONE_MODEM_PW
+ DCL_PW_GROUP_START = 0xA00,
+ DCL_PW,
+#endif
+#ifndef NONE_MODEM_CHR_USB_DET
+ DCL_CHR_USB_DET_GROUP_START = 0xB00,
+ DCL_CHR_USB_DET,
+#endif
+#ifndef NONE_MODEM_ALERTER
+ DCL_ALERTER_GROUP_START = 0xC00,
+ DCL_ALERTER,
+#endif
+#ifndef NONE_MODEM_KBD
+ DCL_KBD_GROUP_START = 0xD00,
+ DCL_KBD,
+#endif
+#ifndef NONE_MODEM_TS
+ DCL_TS_GROUP_START = 0xE00,
+ DCL_TS,
+#endif
+#ifndef NONE_MODEM_I2C
+ DCL_I2C_GROUP_START = 0xF00,
+ DCL_I2C,
+#endif
+/* Moly have no ACCDET*/
+#if 0
+#ifndef NONE_MODEM_AUX
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+#ifndef NONE_MODEM_WDT
+ DCL_WDT_GROUP_START = 0x1100,
+ DCL_WDT,
+#endif
+#ifndef NONE_MODEM_IRDA
+ DCL_IRDA_GROUP_START = 0x1200,
+ DCL_IRDA,
+#endif
+#ifndef NONE_MODEM_USB
+ DCL_USB_GROUP_START = 0x1300,
+ DCL_USB,
+#endif
+#ifndef NONE_MODEM_SIM
+ DCL_SIM_GROUP_START = 0x1400,
+ DCL_SIM,
+#endif
+#ifndef NONE_MODEM_SD
+ DCL_SD_GROUP_START = 0x1500,
+ DCL_SD,
+#endif
+#ifndef NONE_MODEM_MS
+ DCL_MS_GROUP_START = 0x1600,
+ DCL_MS,
+#endif
+#ifndef NONE_MODEM_SDIO
+ DCL_SDIO_GROUP_START = 0x1700,
+ DCL_SDIO,
+#endif
+#ifndef NONE_MODEM_ONEW
+ DCL_ONEW_GROUP_START = 0x1800,
+ DCL_ONEW, //1-wire
+#endif
+#ifndef NONE_MODEM_HDQ
+ DCL_HDQ_GROUP_START = 0x1900,
+ DCL_HDQ,
+#endif
+#ifndef NONE_MODEM_PXS
+ DCL_PXS_GROUP_START = 0x1A00,
+ DCL_PXS,
+#endif
+#ifndef NONE_MODEM_SIM_GPIO
+ DCL_SIM_GPIO_GROUP_START = 0x1B00,
+ DCL_SIM_GPIO,
+#endif
+#ifndef NONE_MODEM_SIM_GPI
+ DCL_SIM_GPI_GROUP_START = 0x1C00,
+ DCL_SIM_GPI,
+#endif
+#ifndef NONE_MODEM_F32K_CLK
+ DCL_F32K_CLK_GROUP_START = 0x1D00,
+ DCL_F32K_CLK,
+#endif
+#ifndef NONE_MODEM_IDC
+ DCL_IDC_GROUP_START = 0x1E00,
+ DCL_IDC,
+#endif
+#ifndef NONE_MTAD
+ DCL_MTAD_GROUP_START = 0x1F00,
+ DCL_MTAD,
+#endif
+#ifndef NONE_MODEM_SPMI
+ DCL_SPMI_GROUP_START = 0x2000,
+ DCL_SPMI
+#endif
+
+} DCL_DEV_T;
+
+/*******************************************************************************
+ * DCL_FLAGS
+ *******************************************************************************/
+typedef DCL_UINT32 DCL_FLAGS;
+typedef enum
+{
+ FLAGS_NONE = 0,
+#ifndef NONE_MODEM_PMU
+ /* Below is the command for PMU */
+ PMU_FLAGS_START = 0x100,
+ PMU_FLAGS //Please see dcl_pmu.h
+#endif
+ FLAGS_END
+} DCL_FLAGS_T;
+
+
+/*******************************************************************************
+ * DCL_OPTIONS
+ *******************************************************************************/
+typedef DCL_UINT32 DCL_OPTIONS;
+typedef enum
+{
+ OPTIONS_NONE = 0,
+#ifndef NONE_MODEM_GPT
+ GPT_OPTIONS_START = OPTIONS_NONE,
+ GPT_OPTIONS //Please see dcl_gpt.h
+#endif
+#ifndef NONE_MODEM_GPIO
+ GPIO_OPTIONS_START = 0x100,
+ GPIO_OPTIONS //Please see dcl_gpio.h
+#endif
+#ifndef NONE_MODEM_ADC
+ ADC_OPTIONS_START = 0x200,
+ ADC_OPTIONS //Please see dcl_adc.h
+#endif
+#ifndef NONE_MODEM_WDT
+ WDT_OPTIONS_START = 0x300,
+ WDT_OPTIONS //Please see dcl_wdt.h
+#endif
+#ifndef NONE_MODEM_BMT
+ BMT_OPTIONS_START = 0x400,
+ BMT_OPTIONS // Please see dcl_bmt.h
+#endif
+#ifndef NONE_MODEM_PFC
+ PFC_OPTIONS_START = 0x500,
+ PFC_OPTIONS // Please see dcl_pfc.h
+#endif
+#ifndef NONE_MODEM_RTC
+ RTC_OPTIONS_START = 0x600,
+ RTC_OPTIONS // Please see dcl_rtc.h
+#endif
+#ifndef NONE_MODEM_I2C
+ I2C_OPTIONS_START = 0x700,
+ I2C_OPTIONS //Please see dcl_i2c.h
+#endif
+#if 0
+#ifndef NONE_MODEM_AUX
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+#ifndef NONE_MODEM_TS
+ TS_OPTIONS_START = 0x900,
+ TS_OPTIONS//Please see dcl_ts.h
+#endif
+#ifndef NONE_MODEM_USB
+ USB_DRV_OPTIONS_START = 0xA00,
+ USB_DRV_OPTIONS//Please see dcl_usb_drv.h
+#endif
+#ifndef NONE_MODEM_USBD
+ USB_HCD_OPTIONS_START = 0xB00,
+ USB_HCD_OPTIONS//Please see dcl_usb_hcd.h
+#endif
+#ifndef NONE_MODEM_OTG
+ OTG_DRV_OPTIONS_START = 0xC00,
+ OTG_DRV_OPTIONS//Please see dcl_otg_drv.h
+#endif
+#ifndef NONE_MODEM_IRDA
+ IRDA_OPTIONS_START = 0xD00,
+ IRDA_OPTIONS//Please see dcl_irda.h
+#endif
+#ifndef NONE_MODEM_PMU
+ PMU_OPTIONS_START = 0xE00,
+ PMU_OPTIONS // Please see dcl_pmu.h
+#endif
+#ifndef NONE_MODEM_PW
+ PW_OPTIONS_START = 0xF00,
+ PW_OPTIONS // Please see dcl_pw.h
+#endif
+#ifndef NONE_MODEM_CHR_USB_DET
+ CHR_DET_OPTIONS_START = 0x1000,
+ CHR_DET_OPTIONS // Please see dcl_chr_usb_det.h
+#endif
+#ifndef NONE_MODEM_SPMI
+ SPMI_OPTIONS_START = 0x1100,
+ SPMI_OPTIONS // Please see dcl_spmi.h
+#endif
+#ifndef NONE_MODEM_PXS
+ PXS_OPTIONS_START = 0x2000,
+ PXS_OPTIONS // Please see dcl_pxs.h
+#endif
+#ifndef NONE_MODEM_F32K_CLK
+ F32K_CLK_OPTIONS_START = 0x4000,
+ F32K_CLK_OPTIONS // Please see dcl_f32k_clk.h
+#endif
+#ifndef NONE_MODEM_IDC
+ IDC_OPTIONS_START = 0x5000,
+ IDC_OPTIONS // Please see dcl_idc.h
+#endif
+ OPTIONS_MAX
+} DCL_OPTIONS_T;
+
+/*******************************************************************************
+ * DCL_HANDLE
+ *******************************************************************************/
+typedef DCL_INT32 DCL_HANDLE;
+#define DCL_HANDLE_NONE (0)
+#define DCL_HANDLE_INVALID (-1)
+#define DCL_HANDLE_OCCUPIED (-2)
+
+/*******************************************************************************
+ * DCL_BUFF
+ *******************************************************************************/
+typedef DCL_UINT8 DCL_BUFF;
+typedef DCL_UINT32 DCL_BUFF_LEN;
+
+/*******************************************************************************
+ * DCL_CONFIGURE_T
+ *******************************************************************************/
+typedef union
+{
+#ifndef NONE_MODEM_PWM
+ PWM_CONFIGS//Please see dcl_PWM.h
+#endif
+#ifndef NONE_MODEM_ADC
+ // For ADC, please see dcl_adc.h
+ ADC_CONFIGS
+#endif
+#ifndef NONE_MODEM_BMT
+ // For BMT, please see dcl_bmt.h
+ BMT_CONFIGS
+#endif
+#ifndef NONE_MODEM_PFC
+ // For PFC, please see dcl_pfc.h
+ PFC_CONFIGS
+#endif
+#ifndef NONE_MODEM_RTC
+ // For RTC, please see dcl_rtc.h
+ RTC_CONFIGS
+#endif
+#ifndef NONE_MODEM_WDT
+ // For WDT, please see dcl_wdt.h
+ WDT_CONFIGS
+#endif
+#ifndef NONE_MODEM_I2C
+ // For I2C, please see dcl_i2c.h
+ I2C_CONFIGS
+#endif
+#if 0
+#ifndef NONE_MODEM_AUX
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+#ifndef NONE_MODEM_USB
+ // For USB_DRV, please see dcl_usb_drv.h
+ USB_DRV_CONFIGS
+#endif
+#ifndef NONE_MODEM_USBD
+ // For USB_HCD, please see dcl_usb_hcd.h
+ USB_HCD_CONFIGS
+#endif
+#ifndef NONE_MODEM_OTG
+ // For OTG_DRV, please see dcl_otg_drv.h
+ OTG_DRV_CONFIGS
+#endif
+#ifndef NONE_MODEM_IRDA
+ // For IRDA, please see dcl_irda.h
+ IRDA_CONFIGS
+#endif
+#ifndef NONE_MODEM_PMU
+ // For PMU, please see dcl_pmu.h
+ PMU_CONFIGS
+#endif
+#ifndef NONE_MODEM_PW
+ // For PW, please see dcl_pw.h
+ PW_CONFIGS
+#endif
+#ifndef NONE_MODEM_CHR_USB_DET
+ // For CHR&USB detection , please see dcl_chr_usb_det.h
+ CHR_DET_CONFIGS
+#endif
+#ifndef NONE_MODEM_SPMI
+ // For SPMI, please see dcl_spmi.h
+ SPMI_CONFIGS
+#endif
+#ifndef NONE_MODEM_SIM
+ // For SIM, please see dcl_sim.h
+ SIM_CONFIGS
+#endif
+#ifndef NONE_MODEM_TS
+ //for TS, please see dcl_ts.h
+ TS_CONFIGS
+#endif
+#ifndef NONE_MODEM_PXS
+ // For PXS, please see dcl_pxs.h
+ PXS_CONFIGS
+#endif
+#ifndef NONE_MODEM_F32K_CLK
+ // For F32K_CLK, please see dcl_f32k_clk.h
+ F32K_CLK_CONFIGS
+#endif
+#ifndef NONE_MODEM_IDC
+ // For IDC, please see dcl_idc.h
+ IDC_CONFIGS
+#endif
+} DCL_CONFIGURE_T;
+
+
+/*******************************************************************************
+ * DCL_EVENT
+ *******************************************************************************/
+typedef DCL_UINT32 DCL_EVENT;
+typedef enum
+{
+ EVENT_NULL = 0,
+#ifndef NONE_MODEM_GPT
+ // For HGPT, please see dcl_gpt.h
+ GPT_EVENTS_START = EVENT_NULL,
+ GPT_EVENTS
+#endif
+#ifndef NONE_MODEM_GPIO
+ //for GPIO, please see dcl_gpio.h
+ GPIO_EVENTS_START = 0x100,
+ GPIO_EVENTS
+#endif
+#ifndef NONE_MODEM_BMT
+ // For BMT, please see dcl_bmt.h
+ BMT_EVENTS_START = 0x200,
+ BMT_EVENTS
+#endif
+#ifndef NONE_MODEM_PFC
+ // For PFC, please see dcl_pfc.h
+ PFC_EVENTS_START = 0x300,
+ PFC_EVENTS
+#endif
+#ifndef NONE_MODEM_RTC
+ // For RTC, please see dcl_rtc.h
+ RTC_EVENTS_START = 0x400,
+ RTC_EVENTS
+#endif
+#ifndef NONE_MODEM_WDT
+ // For WDT, please see dcl_wdt.h
+ WDT_EVENTS_START = 0x500,
+ WDT_EVENTS
+#endif
+#ifndef NONE_MODEM_ADC
+ // For ADC, please see dcl_adc.h
+ ADC_EVENTS_START = 0x600,
+ ADC_EVENTS
+#endif
+#ifndef NONE_MODEM_I2C
+ // For I2C, please see dcl_i2c.h
+ I2C_EVENTS_START = 0x700,
+ I2C_EVENTS
+#endif
+#if 0
+#ifndef NONE_MODEM_AUX
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+#ifndef NONE_MODEM_KBDH
+ //For Keypad, Please see dcl_kbd.h
+ KBDH_EVENTS_START = 0x900,
+ KBDH_EVENTS
+#endif
+#ifndef NONE_MODEM_TS
+ //For TS, Please see dcl_ts.h
+ TS_EVENTS_START = 0xA00,
+ TS_EVENTS
+#endif
+#ifndef NONE_MODEM_USB
+ //For USB_DRV, please see dcl_usb_drv.h
+ USB_DRV_EVENTS_START = 0xB00,
+ USB_DRV_EVENTS
+#endif
+#ifndef NONE_MODEM_USBD
+ //For USB_HCD, please see dcl_usb_hcd.h
+ USB_HCD_EVENTS_START = 0xC00,
+ USB_HCD_EVENTS
+#endif
+#ifndef NONE_MODEM_OTG
+ //For OTG_DRV, please see dcl_otg_drv.h
+ OTG_DRV_EVENTS_START = 0xD00,
+ OTG_DRV_EVENTS
+#endif
+#ifndef NONE_MODEM_IRDA
+ // For IrDA, please see dcl_irda.h
+ IRDA_EVENTS_START = 0xE00,
+ IRDA_EVENTS
+#endif
+#ifndef NONE_MODEM_PMU
+ // For pmu, please see dcl_pmu.h
+ PMU_EVENTS_START = 0xF00,
+ PMU_EVENTS
+#endif
+#ifndef NONE_MODEM_PW
+ // For pw, please see dcl_pw.h
+ PW_EVENTS_START = 0x1000,
+ PW_EVENTS
+#endif
+#ifndef NONE_MODEM_CHR_USB_DET
+ // For Chr&USB detection , please see dcl_chr_usb_det.h
+ CHR_DET_EVENTS_START = 0x1100,
+ CHR_DET_EVENTS
+#endif
+#ifndef NONE_MODEM_PXS
+ // For PXS, please see dcl_pxs.h
+ PXS_EVENTS_START = 0x1200,
+ PXS_EVENTS
+#endif
+#ifndef NONE_MODEM_F32K_CLK
+ // For F32K_CLK, please see dcl_f32k_clk.h
+ F32K_CLK_EVENTS_START = 0x1300,
+ F32K_CLK_EVENTS
+#endif
+#ifndef NONE_MODEM_IDC
+ // For IDC, please see dcl_idc.h
+ IDC_EVENTS_START = 0x1400,
+ IDC_EVENTS
+#endif
+#ifndef NONE_MODEM_SPMI
+ // For spmi, please see dcl_spmi.h
+ SPMI_EVENTS_START = 0x1500,
+ SPMI_EVENTS
+#endif
+ EVENT_END
+} DCL_EVENT_T;
+
+/*******************************************************************************
+ * PFN_DCL_CALLBACK
+ *******************************************************************************/
+typedef void (*PFN_DCL_CALLBACK)(DCL_EVENT event);
+
+/*******************************************************************************
+ * DCL_CTRL_CMD
+ *******************************************************************************/
+#if defined(CMD_END)
+#undef CMD_END
+#endif
+typedef DCL_UINT32 DCL_CTRL_CMD;
+typedef enum
+{
+ CMDS_START = 0,
+ /* Below is the command for GPIO */
+#ifndef NONE_MODEM_GPIO
+ //please make sure GPIO Command start from zero! [drv_tool genertate a char type variable]
+ GPIO_CMDS_START = CMDS_START,
+ GPIO_CMDS //please see dcl_gpio.h
+#endif
+#ifndef NONE_MODEM_UART
+ /* Below is the command for UART */
+ UART_CMDS_START = 0x100,
+ UART_CMDS //please see dcl_uart.h
+#endif
+#ifndef NONE_MODEM_GPT
+ /* Below is the command for GPT */
+ GPT_CMDS_START = 0x200,
+ GPT_CMDS //please see dcl_gpt.h
+#endif
+#ifndef NONE_MODEM_ADC
+ /* Below is the command for ADC */
+ /* Exported adc schedule APIs */
+ ADC_CMDS_START = 0x300,
+ ADC_CMDS
+ /* Interfac for Hardware ADC */
+ HADC_CMDS_START = 0x400,
+ HADC_CMDS
+#endif
+#ifndef NONE_MODEM_WDT
+ /* Below is the command for WDT */
+ WDT_CMDS_START = 0x500,
+ WDT_CMDS
+#endif
+#ifndef NONE_MODEM_BMT
+ /* Below is the command for BMT */
+ BMT_CMDS_START = 0x600,
+ BMT_CMDS // Please see dcl_bmt.h
+#endif
+#ifndef NONE_MODEM_PFC
+ /* Below is the command for PFC */
+ PFC_CMDS_START = 0x700,
+ PFC_CMDS // Please see dcl_pfc.h
+#endif
+#ifndef NONE_MODEM_RTC
+ /* Below is the command for RTC */
+ RTC_CMDS_START = 0x800,
+ RTC_CMDS // Please see dcl_rtc.h
+#endif
+#ifndef NONE_MODEM_I2C
+ /* Below is the command for I2C */
+ I2C_CMDS_START = 0x900,
+ I2C_CMDS
+#endif
+#if 0
+#ifndef NONE_MODEM_AUX
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+#ifndef NONE_MODEM_KBDH
+ /* Below is the command for KBD */
+ KBDH_CMDS_START = 0xB00,
+ KBDH_CMDS
+#endif
+#ifndef NONE_MODEM_KBD
+ KBD_CMDS_START = 0xC00,
+ KBD_CMDS//Please see dcl_kbd.h
+#endif
+#ifndef NONE_MODEM_PWM
+ /* Below is the command for OWM */
+ PWM_CMDS_START = 0xD00,
+ PWM_CMDS//Please see dcl_PWM.h
+#endif
+#ifndef NONE_MODEM_ALERTER
+ ALERTER_CMDS_START = 0xE00,
+ ALERTER_CMDS //please see dcl_pwm.h
+#endif
+#ifndef NONE_MODEM_TS
+ /* Below is the command for TS */
+ TS_CMDS_START = 0xF00,
+ TS_CMDS//Please see dcl_ts.h
+#endif
+#ifndef NONE_MODEM_SD
+ /* Below is the command for SD*/
+ SD_CMDS_START = 0x1000,
+ SD_CMDS//Please see dcl_msdc.h
+#endif
+#ifndef NONE_MODEM_SDIO
+ /* Below is the command for SDIO*/
+ SDIO_CMDS_START = 0x1100,
+ SDIO_CMDS//Please see dcl_msdc.h
+#endif
+#ifndef NONE_MODEM_USB
+ /* Below is the commands for USB_DRV, please see dcl_usb_drv.h */
+ USB_DRV_CMDS_START = 0x1300,
+ USB_DRV_CMDS
+#endif
+#ifndef NONE_MODEM_USBD
+ /* Below is the commands for USB_HCD, please see dcl_usb_hcd.h */
+ USB_HCD_CMDS_START = 0x1400,
+ USB_HCD_CMDS
+#endif
+#ifndef NONE_MODEM_OTG
+ /* Below is the commands for OTG_DRV, please see dcl_otg_drv.h */
+ OTG_DRV_CMDS_START = 0x1500,
+ OTG_DRV_CMDS
+#endif
+#ifndef NONE_MODEM_IRDA
+ /* Below is the command for IRDA*/
+ IRDA_CMDS_START = 0x1600,
+ IRDA_CMDS//Please see dcl_irda.h
+#endif
+#ifndef NONE_MODEM_SIM
+ /* Below is the command for SIM*/
+ SIM_CMDS_START = 0x1700,
+ SIM_CMDS//Please see dcl_msdc.h
+#endif
+#ifndef NONE_MODEM_PMU
+ /* Below is the command for PMU */
+ PMU_CMDS_START = 0x1800,
+ PMU_CMDS //Please see dcl_pmu.h
+#endif
+#ifndef NONE_MODEM_PW
+ /* Below is the command for PW */
+ PW_CMDS_START = 0x1900,
+ PW_CMDS //Please see dcl_pw.h
+#endif
+#ifndef NONE_MODEM_CHR_USB_DET
+ /* Below is the command for CHR USB DETECT */
+ CHR_DET_CMDS_START = 0x1A00,
+ CHR_DET_CMDS //Please see dcl_chr_usb_det.h
+#endif
+#ifndef NONE_MODEM_PXS
+ /* Below is the command for PXS */
+ PXS_CMDS_START = 0x1B00,
+ PXS_CMDS //Please see dcl_pxs.h
+#endif
+#ifndef NONE_MODEM_SIM_GPIO
+ /* Below is the command for SIM GPIO */
+ SIMGPIO_CMDS_START = 0x1C00,
+ SIMGPIO_CMDS //Please see dcl_sim_gpio.h
+#endif
+#ifndef NONE_MODEM_F32K_CLK
+ /* Below is the command for F32K_CLK */
+ F32K_CLK_CMDS_START = 0x1D00,
+ F32K_CLK_CMDS //please see dcl_f32k_clk.h
+#endif
+#ifndef NONE_MODEM_IDC
+ /* Below is the command for IDC */
+ IDC_CMDS_START = 0x1E00,
+ IDC_CMDS // Please see dcl_idc.h
+#endif
+#ifndef NONE_MODEM_SPMI
+ /* Below is the command for SPMI */
+ SPMI_CMDS_START = 0x1F00,
+ SPMI_CMDS //Please see dcl_spmi.h
+#endif
+ CMD_END
+} DCL_CTRL_CMD_T;
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+typedef union
+{
+#ifndef NONE_MODEM_GPT
+ /* GPT control datas, please see dcl_gpt.h */
+ GPT_CTRLS
+#endif
+#ifndef NONE_MODEM_UART
+ /* UART control datas, please see dcl_uart.h */
+ UART_CTRLS
+#endif
+#ifndef NONE_MODEM_GPIO
+ /* GPIO control datas, please see dcl_gpio.h */
+ GPIO_CTRLS
+#endif
+#ifndef NONE_MODEM_ADC
+ /* ADC control datas, please see dcl_adc.h */
+ ADC_CTRLS
+#endif
+#ifndef NONE_MODEM_WDT
+ /* WDT control datas, please see dcl_wdt.h */
+ WDT_CTRLS
+#endif
+#ifndef NONE_MODEM_BMT
+ /* Below is the ctrl structures for BMT */
+ BMT_CTRLS //Please see dcl_bmt.h
+#endif
+#ifndef NONE_MODEM_PFC
+ /* Below is the ctrl structures for PFC */
+ PFC_CTRLS // Please see dcl_pfc.h
+#endif
+#ifndef NONE_MODEM_RTC
+ /* RTC control datas, please see dcl_rtc.h */
+ RTC_CTRLS // Please see dcl_rtc.h
+#endif
+#ifndef NONE_MODEM_I2C
+ /* I2C control datas, please see dcl_i2c.h */
+ I2C_CTRLS
+#endif
+#if 0
+#ifndef NONE_MODEM_AUX
+/* under construction !*/
+/* under construction !*/
+#endif
+#endif
+#ifndef NONE_MODEM_KBD
+ /* KBD control datas, please see dcl_kbd.h */
+ KBDS_CTRLS//Please see dcl_kbd.h
+#endif
+#ifndef NONE_MODEM_KBDH
+ KBDH_CTRLS
+#endif
+#ifndef NONE_MODEM_PWM
+ /* PWM control datas, please see dcl_PWM.h */
+ PWM_CTRLS//Please see dcl_PWM.h
+#endif
+#ifndef NONE_MODEM_ALERTER
+ ALERTER_CTRLS
+#endif
+#ifndef NONE_MODEM_TS
+ /* TS control datas, please see dcl_ts.h */
+ TS_CTRLS//Please see dcl_ts.h
+#endif
+#ifndef NONE_MODEM_SD
+ /* Below is the ctrl structures for SD*/
+ SD_CTRLS//Please see dcl_msdc.h
+#endif
+#ifndef NONE_MODEM_SDIO
+ /* Below is the ctrl structures for SDIO*/
+ SDIO_CTRLS//Please see dcl_msdc.h
+#endif
+#ifndef NONE_MODEM_USB
+ /* Below is the control data structures for USB_DRV, please see dcl_usb_drv.h */
+ USB_DRV_CTRLS
+#endif
+#ifndef NONE_MODEM_USBD
+ /* Below is the control data structures for USB_HCD, please see dcl_usb_hcd.h */
+ USB_HCD_CTRLS
+#endif
+#ifndef NONE_MODEM_OTG
+ /* Below is the control data structures for OTG_DRV, please see dcl_otg_drv.h */
+ OTG_DRV_CTRLS
+#endif
+#ifndef NONE_MODEM_IRDA
+ /* Below is the ctrl structures for IRDA*/
+ IRDA_CTRLS//Please see dcl_irda.h
+#endif
+#ifndef NONE_MODEM_SIM
+ /* Below is the ctrl structures for SIM*/
+ SIM_CTRLS//Please see dcl_sim.h
+#endif
+#ifndef NONE_MODEM_PMU
+ /* Below is the ctrl structures for PMU */
+ PMU_CTRLS//Please see dcl_pmu.h
+#endif
+#ifndef NONE_MODEM_PW
+ /* Below is the ctrl structures for Power up reason */
+ PW_CTRLS//Please see dcl_pW.h
+#endif
+#ifndef NONE_MODEM_CHR_USB_DET
+ /* Below is the ctrl structures for Chr & USB detection */
+ CHR_DET_CTRLS//Please see dcl_chr_usb_det.h
+#endif
+#ifndef NONE_MODEM_SPMI
+ /* Below is the ctrl structures for SPMI */
+ SPMI_CTRLS//Please see dcl_spmi.h
+#endif
+#ifndef NONE_MODEM_PXS
+ /* Below is the ctrl structures for PXS */
+ PXS_CTRLS//Please see dcl_pxs.h
+#endif
+#ifndef NONE_MODEM_SIM_GPIO
+ /* Below is the ctrl structures for SIM_GPIO */
+ SIMGPIO_CTRLS//Please see dcl_sim_gpio.h
+#endif
+#ifndef NONE_MODEM_F32K_CLK
+ /* Below is the ctrl structures for SIM_GPIO */
+ F32K_CLK_CTRLS//please see dcl_f32k_clk.h
+#endif
+#ifndef NONE_MODEM_IDC
+ /* Below is the ctrl structures for IDC */
+ IDC_CTRLS//please see dcl_idc.h
+#endif
+#ifndef NONE_MTAD
+ /* Below is the ctrl structures for MTAD */
+ MTAD_CTRLS//please check dcl_mtad.h
+#endif
+} DCL_CTRL_DATA_T;
+
+
+/*definitions of structures are finished, undefine DCL_DEFINITION_STRUCT*/
+#undef DCL_DEFINITION_STRUCT
+#define DCL_DEFINITION_PROTOTYPE
+
+#ifndef NONE_MODEM_GPT
+#include "dcl_gpt.h"
+#endif
+#ifndef NONE_MODEM_GPIO
+#include "dcl_gpio.h"
+#endif
+#ifndef NONE_MODEM_UART
+#include "dcl_uart.h"
+#endif
+#ifndef NONE_MODEM_WDT
+#include "dcl_wdt.h"
+#endif
+#ifndef NONE_MODEM_ADC
+#include "dcl_adc.h"
+#endif
+#ifndef NONE_MODEM_BMT
+#include "dcl_bmt.h"
+#endif
+#ifndef NONE_MODEM_PFC
+#include "dcl_pfc.h"
+#endif
+#ifndef NONE_MODEM_RTC
+#include "dcl_rtc.h"
+#endif
+#ifndef NONE_MODEM_I2C
+#include "dcl_i2c.h"
+#endif
+#ifndef NONE_MODEM_AUX
+#include "dcl_aux.h"
+#endif
+#if !defined(NONE_MODEM_PWM) && !defined(NONE_MODEM_ALERTER)
+#include "dcl_pwm.h"
+#endif
+#ifndef NONE_MODEM_KBDH
+#include "DclH_kbd.h"
+#endif
+#ifndef NONE_MODEM_KBD
+#include "DclS_kbd.h"
+#endif
+#ifndef NONE_MODEM_STS
+#include "dcl_sts.h"
+#endif
+#ifndef NONE_MODEM_MSDC
+#include "dcl_msdc.h"
+#endif
+#ifndef NONE_MODEM_USB
+#include "dcl_usb_drv.h"
+#endif
+#ifndef NONE_MODEM_USBD
+#include "dcl_usb_hcd.h"
+#endif
+#ifndef NONE_MODEM_OTG
+#include "dcl_otg_drv.h"
+#endif
+#ifndef NONE_MODEM_IRDA
+#include "dcl_irda.h"
+#endif
+#ifndef NONE_MODEM_SIM
+#include "dcl_sim.h"
+#endif
+#ifndef NONE_MODEM_PMU
+#include "dcl_pmu.h"
+#endif
+#ifndef NONE_MODEM_PW
+#include "dcl_pw.h"
+#endif
+#ifndef NONE_MODEM_CHR_USB_DET
+#include "dcl_chr_det.h"
+#endif
+#ifndef NONE_MODEM_SPMI
+#include "dcl_spmi.h"
+#endif
+#ifndef NONE_MODEM_PXS
+#include "dcl_pxs.h"
+#endif
+#ifndef NONE_MODEM_SIM_GPIO
+#include "dcl_sim_gpio.h"
+#endif
+#ifndef NONE_MODEM_F32K_CLK
+#include "dcl_f32k_clk.h"
+#endif
+#ifndef NONE_MODEM_IDC
+#include "dcl_idc.h"
+#endif
+#ifndef NONE_MTAD
+#define DCL_DEFINITION_PROTOTYPE
+#include "dcl_mtad.h"
+#endif
+
+#undef DCL_DEFINITION_PROTOTYPE
+
+
+#endif /* __DCL_H__ */
diff --git a/mcu/interface/driver/peripheral/dcl_15_segment.h b/mcu/interface/driver/peripheral/dcl_15_segment.h
new file mode 100644
index 0000000..0462585
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_15_segment.h
@@ -0,0 +1,83 @@
+#ifndef __DCL_15_SEGMENT_H__
+#define __DCL_15_SEGMENT_H__
+#include "dcl.h"
+
+/****************************************************/
+
+typedef enum {
+ GPIO_LED1,
+ GPIO_LED2
+}LED_NUM;
+
+typedef enum{
+ LED_CMD_FLICKER,
+ LED_CMD_DIMMING,
+ LED_CMD_BRIGHTING
+
+}LED_CTRL_CMD;
+
+typedef struct
+{
+ kal_uint8 Char_D;
+ kal_uint8 Char_C;
+ kal_uint8 Char_B;
+ kal_uint8 Char_A;
+}char_to_display;
+
+/****************************************************/
+extern DCL_STATUS gpio_led_init(void);
+
+/*************************************************************************
+* FUNCTION
+* gpio_led_control
+*
+* DESCRIPTION
+* This function is to control led display
+*
+* PARAMETERS
+*
+*
+* RETURN VALUES:
+* STATUS_OK
+*
+*************************************************************************/
+
+extern DCL_STATUS gpio_led_control(LED_NUM led_num, LED_CTRL_CMD cmd, kal_uint16 freq);
+
+/*************************************************************************
+* FUNCTION
+* gpio_15_segment_led_init
+*
+* DESCRIPTION
+* This function is to init 15-segment
+*
+* PARAMETERS
+*
+*
+* RETURN VALUES:
+* STATUS_OK
+*
+*************************************************************************/
+
+extern DCL_STATUS gpio_15_segment_led_init(void);
+
+/*************************************************************************
+* FUNCTION
+* gpio_15_segment_led_control
+*
+* DESCRIPTION
+* This function is to control 15-segment
+*
+* PARAMETERS
+*
+*
+* RETURN VALUES:
+* STATUS_OK
+*
+*************************************************************************/
+
+extern DCL_STATUS gpio_15_segment_led_control(kal_uint8 word1, kal_uint8 word2);
+
+
+
+#endif
diff --git a/mcu/interface/driver/peripheral/dcl_adc.h b/mcu/interface/driver/peripheral/dcl_adc.h
new file mode 100644
index 0000000..643502d
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_adc.h
@@ -0,0 +1,693 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_adc.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for ADC.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_ADC_H_STRUCT__
+#define __DCL_ADC_H_STRUCT__
+
+#define DCL_ADC_ERR_CHANNEL_NO 50
+/*******************************************************************************
+ * DCL_OPTIONS for ADC
+ *******************************************************************************/
+#define ADC_OPTIONS
+
+ /*******************************************************************************
+ * DCL_CONFIGURE_T for ADC
+ *******************************************************************************/
+
+#define ADC_CONFIGS
+
+/*******************************************************************************
+ * DCL_EVENT for ADC
+ *******************************************************************************/
+#define ADC_EVENTS
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for ADC
+ *******************************************************************************/
+#define ADC_CMDS \
+ ADC_CMD_CREATE_OBJECT, \
+ ADC_CMD_MODIFY_PARAM, \
+ ADC_CMD_START_MEASURE, \
+ ADC_CMD_STOP_MEASURE, \
+ ADC_CMD_SET_TIMER_PAGE_ALIGN, \
+ ADC_CMD_REGISTER_MEASURE_CB, \
+ ADC_CMD_REGISTER_COMPLETE_CB, \
+ ADC_CMD_GET_CHANNEL, \
+ ADC_CMD_SCHE_ID_GET_HANDLE, \
+ ADC_CMD_TRANSFORM_INTO_VOLT, \
+ ADC_CMD_TRANSFORM_INTO_TEMP, \
+ ADC_CMD_TRANSFORM_INTO_CURR, \
+ ADC_CMD_GET_SCHEDULER_PARAMETER, \
+ ADC_CMD_SET_CALIBRATION_DATA, \
+ ADC_CMD_READ_CALIBRATION_DATA, \
+ ADC_CMD_READ_CALIBRATION_INFORM_IN_USBBOOT, \
+ ADC_CMD_SET_MULTI_CHANNEL_READ,
+
+#define HADC_CMDS \
+ ADC_CMD_IMM_MEASURE, \
+ ADC_CMD_SYNC_MEASURE, \
+ ADC_CMD_TDMA_SYNC_SETUP, \
+ ADC_CMD_POWER, \
+ ADC_CMD_GET_DATA_2_META, \
+ ADC_CMD_GET_DATA, \
+ ADC_CMD_GET_META_DATA, \
+ ADC_CMD_GET_MAX_PHYSICAL_CH, \
+ ADC_CMD_GET_IMM_DATA_ON_BOOTING, \
+ ADC_CMD_GET_TEMP, \
+ ADC_CMD_GET_PHYSICAL_CHANNEL,
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+/* For ADC_CMD_CREATE_OBJECT command. */
+typedef struct
+{
+ DCL_UINT32 u4Period; // Measurement period (Uint is in Tick)
+ DCL_UINT32 u4Sapid;
+ DCL_UINT8 u1OwnerId; // Indicate the module to for ADC driver to notify the result
+ DCL_UINT8 u1AdcChannel; // To be measured physical ADC channel
+ DCL_UINT8 u1EvaluateCount; // Measurement count
+ DCL_BOOL fgSendPrimitive; // Whether to send message to owner module or NOT
+} ADC_CTRL_CREATE_OBJECT_T;
+
+/* For ADC_CMD_MODIFY_PARAM command. */
+typedef struct
+{
+ DCL_UINT32 u4Period; // Measurement period (Uint is in Tick)
+ DCL_UINT8 u1EvaluateCount; // Measurement count
+} ADC_CTRL_MODIFY_PARAM_T;
+/* For ADC_CMD_START_MEASURE command. */
+// ADC_CMD_START_MEASURE does NOT need parameters
+/* For ADC_CMD_STOP_MEASURE command. */
+// ADC_CMD_STOP_MEASURE does NOT need parameters
+/* For ADC_CMD_IMM_MEASURE command. */
+typedef struct
+{
+ DCL_UINT16 u2Channel; // The channel to be measured
+ DCL_UINT16 u2ADCValue; // Measured ADC value
+} ADC_CTRL_IMM_MEASURE_T;
+/* For ADC_CMD_SYNC_MEASURE command. */
+typedef struct
+{
+ DCL_UINT16 u2Channel; // The channel to be measured
+ DCL_UINT16 u2ADCValue; // Measured ADC value
+} ADC_CTRL_SYNC_MEASURE_T;
+/* For ADC_CMD_TDMA_SYNC_SETUP command. */
+typedef struct
+{
+ DCL_UINT16 u2Event0; // Event 0
+ DCL_UINT16 u2Event1; // Event 1
+} ADC_CTRL_TDMA_SYNC_SETUP_T;
+/* For ADC_CMD_POWER command. */
+typedef struct
+{
+ DCL_BOOL fgEnable; // TRUE: Power on ADC module, FALSE: Power off ADC module
+} ADC_CTRL_POWER_T;
+
+/* For ADC_CMD_GET_DATA_2_META command. */
+typedef struct
+{
+ DCL_UINT8 u1Channel; //measure physical channel
+ DCL_UINT16 u2MeaCount; //the counts of measurement
+ DCL_UINT32 u4ADCData; //return ADC value
+} ADC_CTRL_GET_DATA_2_META_T;
+
+/* For ADC_CMD_GET_DATA command. */
+typedef struct
+{
+ DCL_UINT8 u1Channel; //measure physical channel
+ DCL_UINT32 u4ADCData; //return ADC value
+} ADC_CTRL_GET_DATA_T;
+
+/* For ADC_CMD_GET_META_DATA command. */
+typedef struct
+{
+ DCL_UINT8 u1Channel; //measure physical channel
+ DCL_UINT16 u2MeaCount; //the counts of measurement
+ DCL_UINT32 u4ADCData; //return ADC value
+} ADC_CTRL_GET_META_DATA_T;
+
+/* For ADC_CMD_GET_IMM_DATA_ON_BOOTING command. */
+typedef struct
+{
+ DCL_UINT32 u4Channel; // Measure physical channel
+ DCL_UINT32 u4MeaCount; // The counts of measurement
+ DCL_UINT16 *u2ADCData; // Store ADC Value
+} ADC_CTRL_GET_IMM_DATA_ON_BOOTING_T;
+
+/* For ADC_CMD_GET_TEMP command. */
+typedef struct
+{
+ DCL_UINT16 u2Channel;
+ DCL_INT16 i2Temp; /* Signed integer for temperature show */
+} ADC_CTRL_GET_TEMP_T;
+
+//ADC_CMD_SET_TIMER_PAGE_ALIGN
+typedef struct
+{
+ DCL_BOOL fgPageAlign; // TRUE: set stack timer page alignment
+} ADC_CTRL_TIMER_ALIGN_T;
+
+//ADC_CMD_GET_CHANNEL
+typedef enum {
+ DCL_VBAT_ADC_CHANNEL = 0,
+ DCL_VISENSE_ADC_CHANNEL,
+ DCL_VBATTMP_ADC_CHANNEL,
+ DCL_BATTYPE_ADC_CHANNEL,
+ DCL_VCHARGER_ADC_CHANNEL,
+ DCL_PCBTMP_ADC_CHANNEL,
+ DCL_AUX_ADC_CHANNEL,
+ DCL_CHR_USB_ADC_CHANNEL,
+ DCL_OTG_VBUS_ADC_CHANNEL,
+ DCL_RFTMP_ADC_CHANNEL,
+ DCL_MDTMP_ADC_CHANNEL,
+ DCL_PMICTMP_ADC_CHANNEL,
+ DCL_MAX_ADC_CHANNEL
+} DCL_ADC_CHANNEL_TYPE_ENUM;
+
+typedef struct
+{
+ DCL_UINT8 u1AdcPhyCh;
+ DCL_UINT16 u2AdcName;
+} ADC_CTRL_GET_PHYSICAL_CHANNEL_T;
+
+//ADC_CMD_TRANSFORM_INTO_VOLT
+typedef struct
+{
+ DCL_DOUBLE d8AdcValue;
+ DCL_UINT32 u4Volt;
+ DCL_UINT8 u1AdcPhyCh;
+} ADC_CTRL_TRANSFORM_INTO_VOLT_T;
+
+//ADC_CMD_TRANSFORM_INTO_TEMP
+typedef struct
+{
+ DCL_UINT32 u4Volt;
+ DCL_UINT32 u4Temp;
+} ADC_CTRL_TRANSFORM_INTO_TEMP_T;
+
+//ADC_CMD_TRANSFORM_INTO_CURR
+typedef struct
+{
+ DCL_UINT32 u4Volt;
+ DCL_UINT32 u4Curr;
+} ADC_CTRL_TRANSFORM_INTO_CURR_T;
+
+//typedef void (*PFN_DCLSADC_MEASURE_CALLBACK)(DCL_INT32 handle);
+//ADC_CMD_REGISTER_MEASURE_CB
+typedef struct
+{
+ kal_timer_func_ptr pfMeasure_cb;
+} ADC_CTRL_REGISTER_MEASURE_CB_T;
+
+typedef void (*PFN_DCLSADC_COMPLETE_CALLBACK)(DCL_INT32 handle, DCL_INT32 volt_result, DCL_DOUBLE adc_result);
+typedef void (*PFN_DCLSADC_COMPLETE_MULTI_CALLBACK)(DCL_INT32 handle, DCL_INT32 *volt_array_result, DCL_DOUBLE *adc_array_result);
+//ADC_CMD_REGISTER_COMPLETE_CB;
+typedef struct
+{
+ PFN_DCLSADC_COMPLETE_CALLBACK pfComplete_cb;
+} ADC_CTRL_REGISTER_COMPLETE_CB_T;
+
+typedef struct
+{
+ PFN_DCLSADC_COMPLETE_MULTI_CALLBACK pfComplete_cb;
+} ADC_CTRL_REGISTER_COMPLETE_MULTI_CB_T;
+
+
+//ADC_CMD_GET_SCHEDULER_PARAMETER
+typedef struct{
+ DCL_UINT32 u4Ownerid;
+ DCL_UINT32 u4Sapid;
+ DCL_UINT32 u4Period;
+ DCL_UINT8 u1Adc_phy_id;
+ DCL_UINT8 u1Adc_logic_id;
+ DCL_UINT8 u1Evaluate_count; /*how many to average*/
+ DCL_BOOL bSend_primitive;
+ DCL_BOOL bConti_measure;
+ DCL_UINT32 u4Adc_sche_event_id;
+ void (*complete)(DCL_INT32 adc_handle, DCL_INT32 volt_result, DCL_DOUBLE adc_result);/*callback for upper layer*/
+}DCL_ADC_SCHEDULER_PARA_T;
+typedef struct
+{
+ DCL_UINT32 u4Handle;
+ DCL_ADC_SCHEDULER_PARA_T pPara;
+} ADC_CTRL_GET_SCHEDULER_PARAMETER_T;
+
+//ADC_CMD_GET_MAX_PHYSICAL_CH
+typedef struct
+{
+ DCL_UINT32 u4Adc_max_ch;
+} ADC_CTRL_GET_MAX_PHYSICAL_CH_T;
+
+//ADC_CMD_SET_CALIBRATION_DATA:
+typedef struct
+{
+ void *ilm_ptr;
+}ADC_CTRL_SET_CALIBRATION_DATA_T;
+
+//ADC_CMD_READ_CALIBRATION_DATA
+typedef struct
+{
+ DCL_INT32 i4ADCSlope[16]; //we do not want to include adc_hw.h here
+ DCL_INT32 i4ADCOffset[16]; //use 16 instead of ADC_MAX_CHANNEL
+}ADC_CTRL_READ_CALIBRATION_DATA_T;
+
+//ADC_CMD_SCHE_ID_GET_HANDLE
+typedef struct{
+ DCL_UINT32 u4Handle;
+ DCL_UINT32 u4Adc_sche_id;
+}DCL_CTRL_SCHE_ID_GET_HANDLE_T;
+
+typedef struct{
+ DCL_UINT8 bEnable;
+ DCL_UINT8 *u4ADC_ch_number;
+ DCL_UINT8 u4Adc_max_ch_number;
+ PFN_DCLSADC_COMPLETE_MULTI_CALLBACK complete_multi_cb;
+}DCL_MULTI_CHANNEL_PARA_T;
+
+#define ADC_CTRLS \
+ ADC_CTRL_CREATE_OBJECT_T rADCCreateObj; \
+ ADC_CTRL_MODIFY_PARAM_T rADCModifyParam; \
+ ADC_CTRL_IMM_MEASURE_T rADCImmMeasure; \
+ ADC_CTRL_SYNC_MEASURE_T rADCSyncMeasure; \
+ ADC_CTRL_TDMA_SYNC_SETUP_T rADCTDMASyncSetup; \
+ ADC_CTRL_POWER_T rADCPower; \
+ ADC_CTRL_TIMER_ALIGN_T rADCTimerAlign; \
+ ADC_CTRL_REGISTER_MEASURE_CB_T rADCRegisterMeasureCB; \
+ ADC_CTRL_REGISTER_COMPLETE_CB_T rADCRegisterCompleteCB; \
+ ADC_CTRL_GET_PHYSICAL_CHANNEL_T rADCGetPhyChannel; \
+ DCL_CTRL_SCHE_ID_GET_HANDLE_T rADCScheIdGetHandle; \
+ ADC_CTRL_TRANSFORM_INTO_VOLT_T rADCTransformVolt; \
+ ADC_CTRL_TRANSFORM_INTO_TEMP_T rADCTransformTemp; \
+ ADC_CTRL_TRANSFORM_INTO_CURR_T rADCTransformCurr; \
+ ADC_CTRL_GET_DATA_2_META_T rADCGetData2Meta; \
+ ADC_CTRL_GET_DATA_T rADCGetData; \
+ ADC_CTRL_GET_META_DATA_T rADCGetMetaData; \
+ ADC_CTRL_GET_SCHEDULER_PARAMETER_T rGetSchedulerPara; \
+ ADC_CTRL_GET_MAX_PHYSICAL_CH_T rADCGetMaxPhyCh; \
+ ADC_CTRL_SET_CALIBRATION_DATA_T rSetCalibrationData; \
+ ADC_CTRL_READ_CALIBRATION_DATA_T rReadCalibrationData; \
+ ADC_CTRL_GET_IMM_DATA_ON_BOOTING_T rGetImmDataOnBooting; \
+ ADC_CTRL_GET_TEMP_T rGetTempData; \
+ DCL_MULTI_CHANNEL_PARA_T rMultiChannelPara;
+#endif // #ifndef __DCL_ADC_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_ADC_H_PROTOTYPE__
+#define __DCL_ADC_H_PROTOTYPE__
+
+/*************************************************************************
+* FUNCTION
+* DclSADC_Initialize
+*
+* DESCRIPTION
+* This function is to initialize SW ADC module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclSADC_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclSADC_Open
+*
+* DESCRIPTION
+* This function is to open the SW ADC module and return a handle
+*
+* PARAMETERS
+* dev: only valid for DCL_ADC
+* flags: no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Open failed
+* Other value: A valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclSADC_Open(DCL_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* DclSADC_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the ADC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclSADC_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclSADC_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the ADC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclSADC_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclSADC_Configure
+*
+* DESCRIPTION
+* This function is not supported for the ADC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclSADC_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+/*************************************************************************
+* FUNCTION
+* DclSADC_RegisterCallback
+*
+* DESCRIPTION
+* This function is not supported for the ADC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclSADC_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+/*************************************************************************
+* FUNCTION
+* DclSADC_Control
+*
+* DESCRIPTION
+* This function is to send command to control the SW ADC module.
+*
+* PARAMETERS
+* handle: A valid handle return by DclSADC_Open()
+* cmd: A control command for ADC module
+* 1. ADC_CMD_CREATE_OBJECT: to create measurement object
+* 2. ADC_CMD_MODIFY_PARAM: to change measurement parameters
+* 3. ADC_CMD_START_MEASURE: to start measurement item
+* 4. ADC_CMD_STOP_MEASURE: to stop measurement item
+* data: The data of the control command
+* 1. ADC_CMD_CREATE_OBJECT: pointer to a ADC_CTRL_CREATE_OBJECT_T structure
+* 2. ADC_CMD_MODIFY_PARAM: pointer to a ADC_CTRL_MODIFY_PARAM_T structure
+* 3. ADC_CMD_START_MEASURE: a null pointer
+* 4. ADC_CMD_STOP_MEASURE: a null pointer
+*
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+*
+*************************************************************************/
+extern DCL_STATUS DclSADC_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclSADC_Close
+*
+* DESCRIPTION
+* This function is to close the SW ADC module.
+*
+* PARAMETERS
+* handle: the returned handle value of DclSADC_Open
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclSADC_Close(DCL_HANDLE handle);
+
+/*************************************************************************
+* FUNCTION
+* DclHADC_Initialize
+*
+* DESCRIPTION
+* This function is to initialize Hardware ADC module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclHADC_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclHADC_Open
+*
+* DESCRIPTION
+* This function is to open the Hardware ADC module and return a handle
+*
+* PARAMETERS
+* dev: only valid for Hardware DCL_ADC
+* flags: no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Open failed
+* Other value: A valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclHADC_Open(DCL_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* DclHADC_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the ADC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclHADC_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclHADC_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the ADC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclHADC_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclHADC_Configure
+*
+* DESCRIPTION
+* This function is not supported for the ADC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclHADC_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+/*************************************************************************
+* FUNCTION
+* DclHADC_RegisterCallback
+*
+* DESCRIPTION
+* This function is not supported for the ADC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclHADC_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+/*************************************************************************
+* FUNCTION
+* DclHADC_Control
+*
+* DESCRIPTION
+* This function is to send command to control the Hardware ADC module.
+*
+* PARAMETERS
+* handle: A valid handle return by DclHADC_Open()
+* cmd: A control command for ADC module
+* 1. ADC_CMD_IMM_MEASURE: to perform a immediate mode measurement (Register control only, not include power setting)
+* 2. ADC_CMD_SYNC_MEASURE: to perform a sync mode measurement (Register control only, not include power setting)
+* 3. ADC_CMD_TDMA_SYNC_SETUP: to setup TDMA sync mode parameters
+* 4. ADC_CMD_POWER: to turn on/off ADC module power
+* data: The data of the control command
+* 1. ADC_CMD_IMM_MEASURE: pointer to a ADC_CTRL_IMM_MEASURE_T structure
+* 2. ADC_CMD_SYNC_MEASURE: pointer to a ADC_CTRL_SYNC_MEASURE_T structure
+* 3. ADC_CMD_TDMA_SYNC_SETUP: pointer to a ADC_CTRL_TDMA_SYNC_SETUP_T structure
+* 4. ADC_CMD_POWER: pointer to a ADC_CTRL_POWER_T structure
+*
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+*
+*************************************************************************/
+extern DCL_STATUS DclHADC_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclHADC_Close
+*
+* DESCRIPTION
+* This function is to close the Hardware ADC module.
+*
+* PARAMETERS
+* handle: the returned handle value of HDclADC_Open
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclHADC_Close(DCL_HANDLE handle);
+
+#endif // #ifndef __DCL_ADC_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
diff --git a/mcu/interface/driver/peripheral/dcl_aux.h b/mcu/interface/driver/peripheral/dcl_aux.h
new file mode 100644
index 0000000..e69de29
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_aux.h
diff --git a/mcu/interface/driver/peripheral/dcl_bmt.h b/mcu/interface/driver/peripheral/dcl_bmt.h
new file mode 100644
index 0000000..7f68611
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_bmt.h
@@ -0,0 +1,461 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2010
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_bmt.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for BMT.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_BMT_H_STRUCT__
+#define __DCL_BMT_H_STRUCT__
+
+/*******************************************************************************
+ * DCL_OPTIONS for BMT
+ *******************************************************************************/
+#define BMT_OPTIONS
+
+/*******************************************************************************
+ * DCL_CONFIGURE_T for BMT
+ *******************************************************************************/
+#define BMT_CONFIGS
+
+/*******************************************************************************
+ * DCL_EVENT for BMT
+ *******************************************************************************/
+#define BMT_EVENTS
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for BMT
+ *******************************************************************************/
+#ifdef __BUILD_DOM__
+/* The BMT Command Values in DCL_CTRL_CMD_T Enum of dcl.h */
+typedef enum {
+ BMT_CMD_CALLSTATE, /* To Set BMT Call State */
+ BMT_CMD_CHARGE, /* To Enable/Disable Charge */
+ BMT_CMD_GET_CUSTOMIZED_PARA, /* To Get Customized Parameters */
+ BMT_CMD_SET_EXT_CHARGER, /* To Set External Charger */
+ BMT_CMD_INITIALIZE, /* To Initialize BMT Module */
+ BMT_CMD_IS_BAT_ON, /* To Check If Battery Exist or Not */
+ BMT_CMD_SENDMES2UEM, /* To Send Message to UEM via BMT */
+ BMT_CMD_SET_CHR_STATUS, /* To Set Charger Status */
+ BMT_CMD_VBATINHISR, /* To Save The Battery Voltage in HISR */
+ BMT_CMD_WDT_INIT, /
+} DCL_CTRL_CMD_T;
+#else /* __BUILD_DOM__ */
+#define BMT_CMDS \
+ BMT_CMD_CALLSTATE, \
+ BMT_CMD_CHARGE, \
+ BMT_CMD_GET_CUSTOMIZED_PARA, \
+ BMT_CMD_SET_EXT_CHARGER, \
+ BMT_CMD_INITIALIZE, \
+ BMT_CMD_IS_BAT_ON, \
+ BMT_CMD_SENDMES2UEM, \
+ BMT_CMD_SET_CHR_STATUS, \
+ BMT_CMD_VBATINHISR, \
+ BMT_CMD_WDT_INIT,
+#endif /* __BUILD_DOM__ */
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+
+/* For BMT_CMD_CALLSTATE command. */
+typedef struct
+{
+ DCL_UINT8 call_state; /* Input : Phone State */
+}BMT_CTRL_CALLSTATE_T;
+
+/* For BMT_CMD_CHARGE command. */
+typedef struct
+{
+ DCL_BOOLEAN bEnable; /* Input : Enable/Disable Charge */
+}BMT_CTRL_CHARGE_T;
+
+/* Enum for Get Commands of Charge Parameter. */
+typedef enum
+{
+ DCL_GET_BATTERY_TYPE, /* Get Bettery Type */
+ DCL_GET_CHECK_BATTERY, /* Get Check Battery Configuration */
+ DCL_GET_CHECK_CHARGER_VOLTAGE, /* Get Check Charger Voltage Configuration */
+ DCL_GET_CHECK_BATT_TEMP, /* Get Check Battery Temperature Configuration */
+ DCL_GET_MAX_VBAT_LI /* Get Max Voltage of Li Battery */
+}DCL_GET_CUSTOM_CHR_PARA;
+
+/* For BMT_CMD_GET_CUSTOMIZED_PARA command. */
+typedef struct
+{
+ DCL_UINT32 u4ChargingParameter; /* Output : Result of Charge Parameter */
+ DCL_GET_CUSTOM_CHR_PARA eGetParaCmd; /* Input : Get Command of Charge Parameter */
+}BMT_CTRL_GET_CUSTOMIZED_PARA_T;
+
+/* Enum for Commands of External Charger. */
+typedef enum
+{
+ DCL_BMT_EXT_CHR_DRV_INIT = 0, /* Called at Driver Init Phase */
+ DCL_BMT_EXT_CHR_ENABLE_INTR, /* Called at PMIC Adpt Layer Init Phase */
+ DCL_BMT_EXT_CHR_CHARGE_ENABLE, /* Control Charge Enable/Disable */
+ DCL_BMT_EXT_CHR_SET_CHARGE_CURRENT, /* Set Charge Current */
+ DCL_BMT_EXT_CHR_GET_CHR_FAC_MEASURE_SUPPORT, /* Whether the External Charger Can Measure the Passed-in Charging Factor */
+ DCL_BMT_EXT_CHR_GET_CHR_FAC_CHECK_SUPPORT, /* Whether the External Charger Can Check the Passed-in Charging Factor */
+ DCL_BMT_EXT_CHR_CHECK_CHR_STATUS, /* Charger Device Can Calculate the Charger Status Through the Passed-in Information */
+ DCL_BMT_EXT_CHR_GET_CHR_STATUS, /* Return calculated charger status */
+ DCL_BMT_EXT_CHR_GET_VBAT, /* Get VBAT */
+ DCL_BMT_EXT_CHR_GET_ISENSE, /* Get ISENSE */
+ DCL_BMT_EXT_CHR_GET_VCHARGER, /* Get VCHARGER */
+ DCL_BMT_EXT_CHR_GET_BAT_TEMP, /* Get Battery Temperature */
+ DCL_BMT_EXT_CHR_GET_CHARGE_FULL, /* Return If Charge Full */
+ DCL_BMT_EXT_CHR_GET_CHARGE_UNDER_EXTREMETMP, /* Return If It's Under Extreme Temperature */
+ DCL_BMT_EXT_CHR_GET_CHARGE_EXTREMETMP_FULL, /* Return If Charge Full When Under Extreme Temperature */
+ DCL_BMT_EXT_CHR_GET_CHARGE_EXTREMETMP_RECHARGE, /* Return If Charge Should Recharge When Under Extreme Temperature */
+ DCL_BMT_EXT_CHR_GET_CHARGE_HOLD, /* Return If It's Need to Hold Charging */
+ DCL_BMT_EXT_CHR_GET_CHR_BATT_STATE_TRANSIT_SUPPORT, /* Whether the External Charger Can Handle the Specific Charging Battery State */
+ DCL_BMT_EXT_CHR_CHR_BATT_STATE_TRANSIT, /* Perform Charging Battery State Transit */
+ DCL_BMT_EXT_CHR_GET_CURR_CHR_BATT_STATE, /* Get Current Charging Battery State */
+ DCL_BMT_EXT_CHR_GET_SPECIFIC_CHR_CURRENT, /* Get Custom Charge Current According to Specific Charger */
+ DCL_BMT_EXT_CHR_GET_VBAT_SPECIFIC_FULL_VOLTAGE_STATE /* Whether the VBAT is Higher Than Specific Full Check Vaule or Not */
+}DCL_BMT_EXT_CHR_CMD;
+
+/* For BMT_CMD_SET_EXT_CHARGER command. */
+typedef struct
+{
+ DCL_BMT_EXT_CHR_CMD eExtChargerCtrl; /* Input : Command of External Charger */
+}BMT_CTRL_SET_EXT_CHARGER_T;
+
+/* For BMT_CMD_IS_BAT_ON command. */
+typedef struct
+{
+ DCL_BOOLEAN fgBatIsOn; /* Output : Battery Exist or Not */
+}BMT_CTRL_IS_BAT_ON_T;
+
+/* Enum for BMT to UEM Messages. */
+typedef enum
+{
+ DCL_BMT_CHARGER_IN = 0, /* Charger In */
+ DCL_BMT_CHARGER_OUT, /* Charger Out */
+ DCL_BMT_OVERVOLPROTECT, /* Battery Over Voltage Protect */
+ DCL_BMT_OVERBATTEMP, /* Battery Over Temperature */
+ DCL_BMT_LOWBATTEMP, /* Battery Low Temperature */
+ DCL_BMT_OVERCHARGECURRENT, /* Over Charger Current */
+ DCL_BMT_CHARGE_COMPLETE, /* Charge Complete */
+ DCL_BMT_INVALID_BAT, /* Invalid Battery */
+ DCL_BMT_INVALID_CHARGER, /* Invalid Charger */
+ DCL_BMT_CHARGE_TIMEOUT, /* Charge Time Out */
+ DCL_BMT_LOWCHARGECURRENT, /* Low Charger Current */
+ DCL_BMT_CHARGE_BAD_CONTACT, /* Charger Bat Contact */
+ DCL_BMT_BATTERY_BAD_CONTACT, /* Battery Bad Contact */
+ DCL_BMT_USB_CHARGER_IN, /* USB Charger In */
+ DCL_BMT_USB_CHARGER_OUT, /* USB Charger Out */
+ DCL_BMT_USB_NO_CHARGING_IN, /* USB No Charger In */
+ DCL_BMT_USB_NO_CHARGING_OUT, /* USB No Charger Out */
+ DCL_BMT_BATT_IN, /* Battery In */
+ DCL_BMT_BATT_OUT /* Battery Out */
+}DCL_BMT_CHR_MSG;
+
+/* For BMT_CMD_SENDMES2UEM command. */
+typedef struct
+{
+ DCL_BMT_CHR_MSG ChargerMsg; /* Input : BMT to UEM Message */
+}BMT_CTRL_SENDMES2UEM_T;
+
+/* Enum for Charger Status. */
+typedef enum {
+ DCL_BMT_CHR_IN = 0, /* Charger In */
+ DCL_BMT_CHR_OUT, /* Charger Out */
+ DCL_BMT_CHR_UNINIT = 0xff /* Charger Uninitialized */
+}DCL_BMT_CHR_STAT;
+
+/* For BMT_CMD_SET_CHR_STATUS command. */
+typedef struct
+{
+ DCL_BMT_CHR_STAT ChargerStat; /* Input : Charger State */
+}BMT_CTRL_SET_CHR_STATUS_T;
+
+/* For BMT_CMD_VBATINHISR command. */
+// BMT_CMD_VBATINHISR does NOT need parameters
+
+#ifdef __BUILD_DOM__
+/* The BMT Command Parameter Data Structure for Each Command in DCL_CTRL_DATA_T Enum of dcl.h */
+typedef struct
+{
+ BMT_CTRL_CALLSTATE_T rCallState; /* Data Structure for BMT_CMD_CALLSTATE */
+ BMT_CTRL_CHARGE_T rChargeControl; /* Data Structure for BMT_CMD_CHARGE */
+ BMT_CTRL_GET_CUSTOMIZED_PARA_T rGetCustomizedPara; /* Data Structure for BMT_CMD_GET_CUSTOMIZED_PARA */
+ BMT_CTRL_SET_EXT_CHARGER_T rSetExtChr; /* Data Structure for BMT_CMD_SET_EXT_CHARGER */
+ BMT_CTRL_IS_BAT_ON_T rIsBatOn; /* Data Structure for BMT_CMD_IS_BAT_ON */
+ BMT_CTRL_SENDMES2UEM_T rSendMes2Uem; /* Data Structure for BMT_CMD_SENDMES2UEM */
+ BMT_CTRL_SET_CHR_STATUS_T rSetChrStatus; /* Data Structure for BMT_CMD_SET_CHR_STATUS */
+}DCL_CTRL_DATA_T;
+#else /* __BUILD_DOM__ */
+#define BMT_CTRLS \
+ BMT_CTRL_CALLSTATE_T rCallState; \
+ BMT_CTRL_CHARGE_T rChargeControl; \
+ BMT_CTRL_GET_CUSTOMIZED_PARA_T rGetCustomizedPara; \
+ BMT_CTRL_SET_EXT_CHARGER_T rSetExtChr; \
+ BMT_CTRL_IS_BAT_ON_T rIsBatOn; \
+ BMT_CTRL_SENDMES2UEM_T rSendMes2Uem; \
+ BMT_CTRL_SET_CHR_STATUS_T rSetChrStatus;
+#endif /* __BUILD_DOM__ */
+
+#endif // #ifndef __DCL_BMT_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_BMT_H_PROTOTYPE__
+#define __DCL_BMT_H_PROTOTYPE__
+
+/*************************************************************************
+* FUNCTION
+* DclBMT_Initialize
+*
+* DESCRIPTION
+* This function is to initialize BMT module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* Return the status of DclBMT_Initialize
+*
+* RETURN VALUES
+* STATUS_OK: Initialize Finished
+*
+*************************************************************************/
+extern DCL_STATUS DclBMT_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclBMT_Open
+*
+* DESCRIPTION
+* This function is to open the BMT module and return a handle
+*
+* PARAMETERS
+* dev: [IN] Only valid for DCL_BMT
+* flags: [IN] No sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* Return DCL_HANDLE of BMT
+*
+* RETURN VALUES
+* DCL_HANDLE_INVALID : Open failed
+* Other value : A valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclBMT_Open(DCL_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* DclBMT_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the BMT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclBMT_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclBMT_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the BMT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclBMT_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclBMT_Configure
+*
+* DESCRIPTION
+* This function is not supported for the BMT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclBMT_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+/*************************************************************************
+* FUNCTION
+* DclBMT_RegisterCallback
+*
+* DESCRIPTION
+* This function is not supported for the BMT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclBMT_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+/*************************************************************************
+* FUNCTION
+* DclBMT_Control
+*
+* DESCRIPTION
+* This function is to send command to control the BMT module.
+*
+* PARAMETERS
+* handle: [IN] The handle value returned from DclBMT_Open
+* cmd: [IN] A control command for BMT module
+* 1. BMT_CMD_CALLSTATE: to nodify talk/idle state to BMT task
+* 2. BMT_CMD_CHARGE: to enable/disble charge
+* 3. BMT_CMD_GET_CUSTOMIZED_PARA: to get customized charge parameters
+* 4. BMT_CMD_SET_EXT_CHARGER: to control the external charger
+* 5. BMT_CMD_INITIALIZE: to initialize BMT Module
+* 6. BMT_CMD_IS_BAT_ON: to check is battery exist or not
+* 7. BMT_CMD_SENDMES2UEM: to send message from BMT to UEM
+* 8. BMT_CMD_SET_CHR_STATUS: to set charger status
+* 9. BMT_CMD_VBATINHISR: to save the Battery voltage in HISR
+*
+* data: [IN] The data of the control command
+* 1. BMT_CMD_CALLSTATE: pointer to a BMT_CTRL_CALLSTATE_T structure
+* 2. BMT_CMD_CHARGE: pointer to a BMT_CTRL_CHARGE_T structure
+* 3. BMT_CMD_GET_CUSTOMIZED_PARA: pointer to a BMT_CTRL_GET_CUSTOMIZED_PARA_T structure
+* 4. BMT_CMD_SET_EXT_CHARGER: pointer to a BMT_CTRL_SET_EXT_CHARGER_T structure
+* 5. BMT_CMD_INITIALIZE: A null pointer
+* 6. BMT_CMD_IS_BAT_ON: pointer to a BMT_CTRL_IS_BAT_ON_T structure
+* 7. BMT_CMD_SENDMES2UEM: pointer to a BMT_CTRL_SENDMES2UEM_T structure
+* 8. BMT_CMD_SET_CHR_STATUS: pointer to a BMT_CTRL_SET_CHR_STATUS_T structure
+* 9. BMT_CMD_VBATINHISR: A null pointer
+*
+* RETURNS
+* Return the status of DclBMT_Control
+*
+* RETURN VALUES
+* STATUS_OK: Command is executed successfully.
+* STATUS_FAIL: Command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+*
+*************************************************************************/
+extern DCL_STATUS DclBMT_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclBMT_Close
+*
+* DESCRIPTION
+* This function is to close the BMT module.
+*
+* PARAMETERS
+* handle: [IN] The returned handle value of DclBMT_Open
+*
+* RETURNS
+* Return the status of DclBMT_Close
+*
+* RETURN VALUES
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclBMT_Close(DCL_HANDLE handle);
+
+
+#endif // #ifndef __DCL_BMT_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
+
diff --git a/mcu/interface/driver/peripheral/dcl_chr_det.h b/mcu/interface/driver/peripheral/dcl_chr_det.h
new file mode 100644
index 0000000..3d5e66b
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_chr_det.h
@@ -0,0 +1,413 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+ /*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_chr_det.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module defines functions of charger detection
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+#ifdef DCL_DEFINITION_STRUCT
+
+#ifndef __DCL_CHR_DET_H_STRUCT__
+#define __DCL_CHR_DET_H_STRUCT__
+
+
+/*******************************************************************************
+ * DCL_OPTIONS for PMU
+ *******************************************************************************/
+#define CHR_DET_OPTIONS
+
+ /*******************************************************************************
+ * DCL_CONFIGURE_T for PMU
+ *******************************************************************************/
+
+#define CHR_DET_CONFIGS
+
+/*******************************************************************************
+ * DCL_EVENT for PMU
+ *******************************************************************************/
+#define CHR_DET_EVENTS
+
+/* Enum of Charger type */
+typedef enum
+{
+ PW_AC_CHR=0, /* AC CHARGER */
+ PW_USB_CHR, /* USB CHARGER */
+ PW_AC_NON_STD_CHR, /* NON-STANDARD AC CHARGER */
+ PW_USB_CHARGING_HOST_CHR, /* USB CHARGING HOST */
+ PW_NO_CHR // Indicate NO charger
+}CHR_DET_TYPE_ENUM;
+
+/* For CHR_DET_CMD_QUERY_CHR_TYPE command. */
+typedef struct
+{
+ CHR_DET_TYPE_ENUM Chr_det_type; /* Output : Value of Charger type */
+}CHR_DET_CTRL_QUERY_IS_CHR_IN_BY_PW;
+
+/* For RTC_CMD_CONFIG_AL_TC command. */
+typedef struct
+{
+ CHR_DET_TYPE_ENUM Chr_det_type; /* Output : Value of Charger type */
+}CHR_DET_CTRL_QUERY_CHR_TYPE;
+
+typedef struct
+{
+ void (*usb_det_hisr)(void);
+}CHR_DET_CTRL_REGISTER_USB_HISR;
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+#ifdef __BUILD_DOM__
+/* The CHR_DET Command Parameter Data Structure for Each Command in DCL_CTRL_DATA_T Enum of dcl.h */
+typedef struct
+{
+ CHR_DET_CTRL_QUERY_IS_CHR_IN_BY_PW rChrDetQueryIsChrInByPW; /* Data Structure for CHR_DET_CMD_QUERY_IS_CHR_IN_BY_PW */
+ CHR_DET_CTRL_QUERY_CHR_TYPE rChrDetQueryChrType; /* Data Structure for CHR_DET_CMD_QUERY_CHR_TYPE */
+ CHR_DET_CTRL_REGISTER_USB_HISR rChrDetUSBHISR; /* Data Structure for CHR_DET_CTRL_REGISTER_USB_HISR */
+} DCL_CTRL_CHR_DET_DATA;
+#else /* __BUILD_DOM__ */
+#define CHR_DET_CTRLS \
+ CHR_DET_CTRL_QUERY_IS_CHR_IN_BY_PW rChrDetQueryIsChrInByPW; \
+ CHR_DET_CTRL_QUERY_CHR_TYPE rChrDetQueryChrType; \
+ CHR_DET_CTRL_REGISTER_USB_HISR rChrDetUSBHISR;
+#endif /* __BUILD_DOM__ */
+
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for PMU
+ *******************************************************************************/
+#ifdef __BUILD_DOM__
+/* The CHR DET Command Values in DCL_CTRL_CMD_T Enum of dcl.h */
+typedef enum
+{
+ CHR_DET_CMD_QUERY_IS_CHR_IN_BY_PW,
+ CHR_DET_CMD_QUERY_CHR_TYPE,
+ CHR_DET_CMD_REGISTER_CHR_USB,
+ CHR_DET_CMD_UNMASK_EINT,
+ CHR_DET_CMD_REGISTER_CHR_USB_EINT,
+ CHR_DET_CMD_REGISTER_USB_HISR,
+} DCL_CTRL_CHR_DET_CMD;
+#else /* __BUILD_DOM__ */
+#define CHR_DET_CMDS \
+ CHR_DET_CMD_QUERY_IS_CHR_IN_BY_PW=0, \
+ CHR_DET_CMD_QUERY_CHR_TYPE, \
+ CHR_DET_CMD_REGISTER_CHR_USB, \
+ CHR_DET_CMD_UNMASK_EINT, \
+ CHR_DET_CMD_REGISTER_CHR_USB_EINT,\
+ CHR_DET_CMD_REGISTER_USB_HISR,
+#endif /* __BUILD_DOM__ */
+
+
+// CHR_USB_EINT control owner list
+// Only the tasks listed can control CHR_USB_EINT Unmask
+typedef enum
+{
+ CHR_DET_EINT_OWNER_USB = 0x01, // Bit00
+ CHR_DET_EINT_OWNER_BMT = 0x02, // Bit01
+ USB_DET_EINT_OWNER_FORCE_UNMASK = 0x80 // Bit7 // It means we should skip bit match and directly unmask EINT
+}CHR_DET_EINT_OWNER;
+
+
+typedef struct
+{
+ CHR_DET_TYPE_ENUM (*pw_is_charger_usb_det)(void);
+ void (*pw_is_charger_usb_det_eint)(void);
+ void (*usb_det_hisr)(void);
+}CHR_USB_DET_MGR_T;
+
+
+
+#endif // #ifndef __DCL_PMU_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_CHR_DET_H_PROTOTYPE__
+#define __DCL_CHR_DET_H_PROTOTYPE__
+
+
+
+
+/*************************************************************************
+* FUNCTION
+* Dcl_Chr_Det_Initialize
+*
+* DESCRIPTION
+* This function is to initialize Chr_Det module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS Dcl_Chr_Det_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* Dcl_Chr_Det_Open
+*
+* DESCRIPTION
+* This function is to open the Chr_Det module and return a handle
+*
+* PARAMETERS
+* dev: only valid for DCL_CHR_USB_DET
+* flags: no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Open failed.
+* other value: a valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE Dcl_Chr_Det_Open(DCL_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* Dcl_Chr_Det_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the Chr_Det module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS Dcl_Chr_Det_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* Dcl_Chr_Det_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the Chr_Det module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS Dcl_Chr_Det_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* Dcl_Chr_Det_Configure
+*
+* DESCRIPTION
+* This function is to close the Chr_Det module.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS Dcl_Chr_Det_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+/*************************************************************************
+* FUNCTION
+* Dcl_Chr_Det_RegisterCallback
+*
+* DESCRIPTION
+* This function is not supported for the Chr_Det module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS Dcl_Chr_Det_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+/*************************************************************************
+* FUNCTION
+* Dcl_Chr_Det_Control
+*
+* DESCRIPTION
+* This function is to send command to control the Chr_Det module.
+* All command
+*
+* CALLS
+* It is called to send command to control the Chr_Det module.
+*
+* PARAMETERS
+* handle: [IN] The handle value returned from Dcl_Chr_Det_Open()
+* cmd: [IN] A control command for Chr_Det module
+* 1. PW_CMD_POWERON: call RTC module to latch power and init time if necessary
+* 2. PW_CMD_POWEROFF: call RTC module to unlatch power
+* 3. PW_CMD_SET_POWERON_REASON: set power on reason
+* 4. PW_CMD_GET_POWERON_REASON: get power on reason
+* 5. PW_CMD_SET_SWITCH_TO_IDLE: set flag which force phone to enter idle mode
+* 6. PW_CMD_CLEAR_SWITCH_TO_IDLE: clear flag which force phone to enter idle mode
+* 7. PW_CMD_POWER_INIT: check power on factors to decide power on reason and save in RTC register
+* 8. PW_CMD_UPDATE_FLAGS: update power on reason to rtc register
+* 9. PW_CMD_NFB_POWERON: call RTC module to latch power and init time if necessary (only for NAND FLASH BOOTING)
+* 10. PW_CMD_IS_USB_BOOT: query is power on reason USB plug in
+*
+* data: The data of the control command
+* 1. PW_CMD_POWERON: A null pointer
+* 2. PW_CMD_POWEROFF: A null pointer
+* 3. PW_CMD_SET_POWERON_REASON: pointer to a PW_CTRL_SET_POWERON_REASON structure
+* 4. PW_CMD_GET_POWERON_REASON: pointer to a PW_CTRL_GET_POWERON_REASON structure
+* 5. PW_CMD_SET_SWITCH_TO_IDLE: A null pointer
+* 6. PW_CMD_CLEAR_SWITCH_TO_IDLE: A null pointer
+* 7. PW_CMD_POWER_INIT: A null pointer
+* 8. PW_CMD_UPDATE_FLAGS: A null pointer
+* 9. PW_CMD_NFB_POWERON: A null pointer
+* 10. PW_CMD_IS_USB_BOOT: pointer to a PW_CTRL_IS_USB_BOOT
+*
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+* STATUS_UNSUPPORTED: It's a unsupported command.
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS Dcl_Chr_Det_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* Dcl_Chr_Det_Close
+*
+* DESCRIPTION
+* This function is to close the Chr_Det module.
+*
+* PARAMETERS
+* handle: the returned handle value of Dcl_Chr_Det_Open
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS Dcl_Chr_Det_Close(DCL_HANDLE handle);
+
+
+#endif // #ifndef __DCL_CHR_DET_H_PROTOTYPE__
+#endif //#ifdef DCL_DEFINITION_PROTOTYPE
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/mcu/interface/driver/peripheral/dcl_f32k_clk.h b/mcu/interface/driver/peripheral/dcl_f32k_clk.h
new file mode 100644
index 0000000..0254248
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_f32k_clk.h
@@ -0,0 +1,251 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_f32k_clk.h
+ *
+ * Project:
+ * --------
+ * Maui_sw
+ *
+ * Description:
+ * ------------
+ * This file defines the DCL common definitions for f32k_clk dcl interface.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_F32K_CLK_H_STRUCT__
+#define __DCL_F32K_CLK_H_STRUCT__
+
+#include "dcl.h"
+
+/*******************************************************************************
+ * DCL_OPTIONS for F32K_CLK
+ *******************************************************************************/
+#define F32K_CLK_OPTIONS
+
+ /*******************************************************************************
+ * DCL_CONFIGURE_T for F32K_CLK
+ *******************************************************************************/
+#define F32K_CLK_CONFIGS
+
+/*******************************************************************************
+ * DCL_EVENT for F32K_CLK
+ *******************************************************************************/
+#define F32K_CLK_EVENTS
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+
+typedef struct
+{
+ DCL_BOOLEAN f32k_is_xosc32;
+}F32K_CLK_CTRL_F32K_IS_XOSC32_T;
+
+typedef struct
+{
+ DCL_UINT16 eosc32_cali_val;
+}F32K_CLK_CTRL_EOSC32_CALI_VAL_T;
+
+#ifdef __BUILD_DOM__
+/* The F32K_CLK Command Parameter Data Structure for Each Command in DCL_CTRL_DATA_T Enum of dcl.h */
+typedef struct
+{
+ F32K_CLK_CTRL_F32K_IS_XOSC32_T rF32kIsXOSC32; /* Data structure for F32K_CLK_CTRL_F32K_IS_XOSC32 */
+ F32K_CLK_CTRL_EOSC32_CALI_VAL_T rEosc32CaliVal;
+}DCL_CTRL_F32K_CLK_DATA_T;
+#else /* __BUILD_DOM__ */
+#define F32K_CLK_CTRLS \
+ F32K_CLK_CTRL_F32K_IS_XOSC32_T rF32kIsXOSC32; \
+ F32K_CLK_CTRL_EOSC32_CALI_VAL_T rEosc32CaliVal;
+#endif /* __BUILD_DOM__ */
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for F32K_CLK
+ *******************************************************************************/
+#ifdef __BUILD_DOM__
+/* The F32K_CLK Command Values in DCL_CTRL_CMD_T Enum of dcl.h */
+typedef enum {
+ F32K_CLK_CMD_QUERY_IS_XOSC32K, /* To query F32K is XOSC32K or not */
+ F32K_CLK_CMD_EOSC32_TRIMMING, /* To trimming EOSC32 and get ideal cali value */
+ F32K_CLK_CMD_HW_INIT, /* To init 32K HW setting */
+} DCL_CTRL_F32K_CLK_CMD_T;
+#else /* __BUILD_DOM__ */
+#define F32K_CLK_CMDS \
+ F32K_CLK_CMD_QUERY_IS_XOSC32K, \
+ F32K_CLK_CMD_EOSC32_TRIMMING, \
+ F32K_CLK_CMD_HW_INIT,
+#endif /* __BUILD_DOM__ */
+
+
+#endif // #ifndef __DCL_F32K_CLK_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_F32K_CLK_H_PROTOTYPE__
+#define __DCL_F32K_CLK_H_PROTOTYPE__
+/*************************************************************************
+* FUNCTION
+* DclF32K_Initialize
+*
+* DESCRIPTION
+* This function is to initialize F32K_CLK module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* Return the status of DclF32K_Initialize
+*
+* RETURN VALUES
+* STATUS_OK: Initialize Finished
+*
+*************************************************************************/
+extern DCL_STATUS DclF32K_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclF32K_Open
+*
+* DESCRIPTION
+* This function is to open the F32K_CLK module and return a handle
+*
+* PARAMETERS
+* dev: [IN] Only valid for DCL_F32K_CLK
+* flags: [IN] No sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* Return DCL_HANDLE of F32K_CLK
+*
+* RETURN VALUES
+* DCL_HANDLE_INVALID : Open failed
+* Other value : A valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclF32K_Open(DCL_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* DclF32K_Control
+*
+* DESCRIPTION
+* This function is to send command to control the F32K_CLK module.
+*
+* PARAMETERS
+* handle: [IN] The handle value returned from DclF32K_Open
+* cmd: [IN] A control command for RTC module
+* 1. F32K_CLK_CMD_QUERY_IS_XOSC32K: To query clock source F32K is XOSC32K or not
+*
+* data: The data of the control command
+* 1. F32K_CLK_CMD_QUERY_IS_XOSC32K: pointer to a F32K_CLK_CTRL_F32K_IS_XOSC32_T structure
+*
+* RETURNS
+* Return the status of DclF32K_Control
+*
+* RETURN VALUES
+* STATUS_OK: Command is executed successfully.
+* STATUS_FAIL: Command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+*
+*************************************************************************/
+extern DCL_STATUS DclF32K_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclF32K_Close
+*
+* DESCRIPTION
+* This function is to close the F32K_CLK module.
+*
+* PARAMETERS
+* handle: [IN] The returned handle value of DclF32K_Open
+*
+* RETURNS
+* Return the status of DclF32K_Close
+*
+* RETURN VALUES
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclF32K_Close(DCL_HANDLE handle);
+
+#endif // #ifndef __DCL_F32K_CLK_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
+
diff --git a/mcu/interface/driver/peripheral/dcl_gpio.h b/mcu/interface/driver/peripheral/dcl_gpio.h
new file mode 100644
index 0000000..99f30d7
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_gpio.h
@@ -0,0 +1,831 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_gpio.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for GPIO.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_GPIO_H_STRUCT__
+#define __DCL_GPIO_H_STRUCT__
+//#include "gpio_sw_.h"
+#include "drv_features_gpio.h"
+
+#define GPIO_DIR_INPUT 0
+#define GPIO_DIR_OUTPUT 1
+#define GPIO_DIR_BOTH 2
+
+#define GPIO_MAGIC_NUM 0x80
+#define GPO_MAGIC_NUM 0x70
+
+
+#define GPIO_INPUT 0 /* IO in input */
+#define GPIO_ALL_INPUT 0x0000
+#define GPIO_OUTPUT 1 /* IO in output */
+#define GPIO_ALL_OUTPUT 0xffff
+
+#define GPIO_MAGIC_NUM_INTERNAL 0x80
+#define GPO_MAGIC_NUM_INTERNAL 0x70
+
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(DRV_GPIO_REG_AS_6223) || defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6253E) || defined(DRV_GPIO_REG_AS_6253E_1)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #if defined(DRV_GPIO_REG_AS_6253T) || defined(DRV_GPIO_REG_AS_6253E) || defined(DRV_GPIO_REG_AS_6253E_1)
+/* under construction !*/
+/* under construction !*/
+ #if defined(DRV_GPIO_REG_AS_6253E_1)
+/* under construction !*/
+/* under construction !*/
+ #endif /*DRV_GPIO_REG_AS_6253E*/
+ #endif /*DRV_GPIO_REG_AS_6253T*/
+#elif defined(DRV_GPIO_REG_AS_6238) || defined(DRV_GPIO_REG_AS_6235)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#if defined(DRV_GPIO_REG_AS_6235)
+/* under construction !*/
+/* under construction !*/
+#endif
+#elif defined(DRV_GPIO_REG_AS_6268A) || defined(DRV_GPIO_REG_AS_6268) || defined(DRV_GPIO_REG_AS_6270A)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+ #if !defined(DRV_GPIO_REG_AS_6270A)
+/* under construction !*/
+/* under construction !*/
+ #endif//!defined(DRV_GPIO_REG_AS_6270A)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#elif defined(DRV_GPIO_REG_AS_6236)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#elif defined(DRV_GPIO_REG_AS_6255)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#elif defined(DRV_GPIO_REG_AS_6276)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#elif defined(DRV_GPIO_REG_AS_6251)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+typedef enum {
+ mode_default = 0,
+ mode_f32k_ck = 0x82,
+ mode_max_num
+ } gpio_clk_mode;
+//remove this to see if there are build error .this should be delete. 12-22.
+#if 0
+/* under construction !*/
+/* under construction !*/
+#if defined(DRV_GPIO_REG_AS_6255)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#elif defined(DRV_GPIO_REG_AS_6276)
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif //defined(DRV_GPIO_REG_AS_6255)
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+
+typedef enum {
+ div_max_num=16
+} gpio_clk_div;
+typedef struct
+{
+ kal_uint8 pin_num; /*1,activated ,0:de-activated*/
+ kal_uint8 dir; // GPIO_DIR_OUTPUT or GPIO_DIR_INPUT or GPIO_DIR_BOTH
+} GPIOCheckStruct;
+
+/*******************************************************************************
+ * DCL_OPTIONS for GPIO
+ *******************************************************************************/
+#define GPIO_OPTIONS
+
+/*******************************************************************************
+ * DCL_CONFIGURE_T
+ *******************************************************************************/
+
+/*******************************************************************************
+ * DCL_EVENT for GPIO
+ *******************************************************************************/
+#define GPIO_EVENTS
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for GPIO
+ *******************************************************************************/
+#ifdef __BUILD_DOM__
+/*The GPIO Command values in DCL_CTRL_CMD_T Enum of dcl.h*/
+/*DCL_CTRL_DATA_T Define the Control data structure for each module's command*/
+typedef enum
+{
+ GPIO_CMD_READ, /*read data from GPIO Pin*/
+ GPIO_CMD_WRITE_LOW, /*write low to GPIO pin*/
+ GPIO_CMD_WRITE_HIGH, /*write high to GPIO Pin*/
+ GPIO_CMD_SET_MODE_0, /*set GPIO mode as mode 0*/
+ GPIO_CMD_SET_MODE_1, /*set GPIO mode as mode 1*/
+ GPIO_CMD_SET_MODE_2, /*set GPIO mode as mode 2*/
+ GPIO_CMD_SET_MODE_3, /*set GPIO mode as mode 3*/
+ GPIO_CMD_SET_MODE_4, /*set GPIO mode as mode 4 ,only for chip support 4-bit mode*/
+ GPIO_CMD_SET_MODE_5, /*set GPIO mode as mode 5*,only for chip support 4-bit mode*/
+ GPIO_CMD_SET_MODE_6, /*set GPIO mode as mode 6*,only for chip support 4-bit mode*/
+ GPIO_CMD_SET_MODE_7, /*set GPIO mode as mode 7*,only for chip support 4-bit mode*/
+ GPIO_CMD_SET_MODE_8, /*set GPIO mode as mode 8*,only for chip support 4-bit mode*/
+ GPIO_CMD_SET_DIR_OUT, /*set GPIO direction as output*/
+ GPIO_CMD_SET_DIR_IN, /*set GPIO direction as input*/
+ GPIO_CMD_RETURN_MODE, /*get current GPIO mode*/
+ GPIO_CMD_RETURN_DIR, /*get current GPIO direction*/
+ GPIO_CMD_RETURN_OUT, /*get current GPIO output level*/
+ GPIO_CMD_ENABLE_PULL, /*enable GPIO pull-up/pull-down seting */
+ GPIO_CMD_DISABLE_PULL, /*disable GPIO pull-up/pull-down seting*/
+ GPIO_CMD_SET_PULL_HIGH, /*set GPIO as pull-up*/
+ GPIO_CMD_SET_PULL_LOW, /*set GPIO as pull-down*/
+ GPIO_CMD_SET_DINV, /*enable or disable GPIO data inversion*/
+ GPIO_CMD_SET_DEBUG, /*configure the GPIO sets to auxiliary function mode or to debug mode*/
+ GPIO_CMD_SET_CLK_OUT, /*select the clock output source of GPIO*/
+ GPIO_CMD_SET_CLK_DIV,
+ GPIO_CMD_SET_OWNERSHIP_TO_MD, /* to set ownership of a GPIO port to Modem side.*/
+ GPIO_CMD_SET_OWNERSHIP_TO_AP, /* to set ownership of a GPIO port to AP side.*/
+ GPIO_CMD_SET_DRIVE, /* to set the drive of a GPIO port.*/
+ GPIO_CMD_RETURN_DRIVE, /* to return the drive of the GPIO port.*/
+ GPIO_CMD_RETURN_OWNERSHIP, /* to return the ownership of the GPIO port. */
+ GPO_CMD_RETURN_MODE, /*get current GPO mode*/
+ GPO_CMD_RETURN_OUT, /*get current GPO output level*/
+ GPO_CMD_WRITE_HIGH, /*write high to GPO Pin*/
+ GPO_CMD_WRITE_LOW, /*write low to GPO Pin*/
+ GPO_CMD_MODE_SET_0, /*set GPIO mode as mode 0*/
+ GPO_CMD_MODE_SET_1, /*set GPIO mode as mode 1*/
+ GPO_CMD_MODE_SET_2, /*set GPIO mode as mode 2*/
+ GPO_CMD_MODE_SET_3, /*set GPIO mode as mode 3*/
+ GPIO_CMD_SET_DIR_OUT_NO_IRQ_MASK, /*set GPIO direction as output without mask IRQ portect*/
+ GPIO_CMD_SET_DIR_IN_NO_IRQ_MASK, /*set GPIO direction as input without mask IRQ portect*/
+ GPIO_CMD_WRITE_HIGH_NO_IRQ_MASK, /*write high to GPIO Pin without mask IRQ protect*/
+ GPIO_CMD_WRITE_LOW_NO_IRQ_MASK, /*write low to GPIO Pin without mask IRQ protect*/
+ GPIO_CMD_READ_NO_IRQ_MASK, /*read data from GPIO Pin without IRQ mask*/
+ GPIO_CMD_WRITE_FOR_SPI, /*this function is to write data to one GPIO port, that for faster access without debug checking.*/
+ GPIO_CMD_GET_AP_PIN,
+}DCL_CTRL_CMD_T;
+#else
+#define GPIO_CMDS \
+ GPIO_CMD_READ, \
+ GPIO_CMD_WRITE_LOW, \
+ GPIO_CMD_WRITE_HIGH, \
+ GPIO_CMD_SET_MODE_0, \
+ GPIO_CMD_SET_MODE_1, \
+ GPIO_CMD_SET_MODE_2, \
+ GPIO_CMD_SET_MODE_3, \
+ GPIO_CMD_SET_MODE_4, \
+ GPIO_CMD_SET_MODE_5, \
+ GPIO_CMD_SET_MODE_6, \
+ GPIO_CMD_SET_MODE_7, \
+ GPIO_CMD_SET_MODE_8, \
+ GPIO_CMD_SET_DIR_OUT,\
+ GPIO_CMD_SET_DIR_IN, \
+ GPIO_CMD_RETURN_MODE, \
+ GPIO_CMD_RETURN_DIR, \
+ GPIO_CMD_RETURN_OUT, \
+ GPIO_CMD_ENABLE_PULL, \
+ GPIO_CMD_DISABLE_PULL,\
+ GPIO_CMD_SET_PULL_HIGH, \
+ GPIO_CMD_SET_PULL_LOW, \
+ GPIO_CMD_SET_DINV, \
+ GPIO_CMD_SET_DEBUG, \
+ GPIO_CMD_SET_CLK_OUT, \
+ GPIO_CMD_SET_CLK_DIV, \
+ GPIO_CMD_SET_OWNERSHIP_TO_MD, \
+ GPIO_CMD_SET_OWNERSHIP_TO_AP, \
+ GPIO_CMD_SET_DRIVE, \
+ GPIO_CMD_RETURN_DRIVE, \
+ GPIO_CMD_RETURN_OWNERSHIP, \
+ GPO_CMD_RETURN_MODE, \
+ GPO_CMD_RETURN_OUT, \
+ GPO_CMD_WRITE_HIGH, \
+ GPO_CMD_WRITE_LOW, \
+ GPO_CMD_MODE_SET_0, \
+ GPO_CMD_MODE_SET_1, \
+ GPO_CMD_MODE_SET_2, \
+ GPO_CMD_MODE_SET_3,\
+ GPIO_CMD_SET_DIR_OUT_NO_IRQ_MASK, \
+ GPIO_CMD_SET_DIR_IN_NO_IRQ_MASK, \
+ GPIO_CMD_WRITE_HIGH_NO_IRQ_MASK, \
+ GPIO_CMD_WRITE_LOW_NO_IRQ_MASK, \
+ GPIO_CMD_READ_NO_IRQ_MASK, \
+ GPIO_CMD_WRITE_FOR_SPI,\
+ GPIO_CMD_GET_AP_PIN,
+#endif /*__BUILD_DOM__*/
+#define GPIO_PULL_ENABLE 1
+#define GPIO_PULL_DISABLE 0
+#define GPIO_PULL_HIGH 1
+#define GPIO_PULL_LOW 0
+
+/* FOR GPIO_CMD_READ control command. */
+typedef struct
+{
+#define GPIO_IO_HIGH 1
+#define GPIO_IO_LOW 0
+ DCL_UINT8 u1IOData; // GPIO_IO_HIGH or GPIO_IO_LOW
+} GPIO_CTRL_READ_T;
+
+/* FOR GPIO_CMD_RETURN_MODE control command. */
+typedef struct
+{
+#define GPIO_MODE_0 0
+#define GPIO_MODE_1 1
+#define GPIO_MODE_2 2
+#define GPIO_MODE_3 3
+#define GPIO_MODE_4 4
+#define GPIO_MODE_5 5
+#define GPIO_MODE_6 6
+#define GPIO_MODE_7 7
+#define GPIO_MODE_8 8
+ DCL_UINT8 u1RetMode;//Output: to return GPIO_MODE0, GPIO_MODE1, GPIO_MODE2, or GPIO_MODE3
+} GPIO_CTRL_RETURN_MODE_T;
+
+/* FOR GPO_CMD_RETURN_MODE control command. */
+typedef struct
+{
+#define GPO_MODE_0 0
+#define GPO_MODE_1 1
+#define GPO_MODE_2 2
+#define GPO_MODE_3 3
+ DCL_UINT8 u1RetMode;//Output: to return GPO_MODE0, GPO_MODE1, GPO_MODE2, or GPO_MODE3
+} GPO_CTRL_RETURN_MODE_T;
+
+/* FOR GPIO_CMD_RETURN_DIR control command. */
+typedef struct
+{
+#define GPIO_DIR_IN 0
+#define GPIO_DIR_OUT 1
+ DCL_UINT8 u1RetDirData;//Output: to return GPIO_DIR_INPUT, or GPIO_DIR_OUTPUT
+} GPIO_CTRL_RETURN_DIR_T;
+
+/* FOR GPIO_CMD_RETURN_OUT control command. */
+typedef struct
+{
+ DCL_UINT8 u1RetOutData;//Output: to return GPIO_IO_HIGH or GPIO_IO_LOW
+} GPIO_CTRL_RETURN_OUT_T;
+
+/* FOR GPIO_CMD_RETURN_AP control command. */
+typedef struct
+{
+ DCL_UINT8 u1RetApData;//
+} GPIO_CTRL_RETURN_AP_T;
+
+/* FOR GPO_CMD_RETURN_OUT control command. */
+typedef struct
+{
+#define GPO_IO_HIGH 1
+#define GPO_IO_LOW 0
+ DCL_UINT8 u1RetOutData;//Output: to return GPO_IO_HIGH or GPO_IO_LOW
+} GPO_CTRL_RETURN_OUT_T;
+
+/* FOR GPIO_CMD_SET_DINV control command. */
+typedef struct
+{
+ DCL_BOOL fgSetDinv; //get more detail in spec.
+} GPIO_CTRL_SET_DINV_T;
+
+/* FOR GPIO_CMD_SET_DEBUG control command. */
+typedef struct
+{
+ DCL_BOOL fgSetDebug;
+} GPIO_CTRL_SET_DEBUG_T;
+
+/* FOR GPIO_CMD_SET_CLK_OUT control command. */
+typedef struct
+{
+ DCL_UINT16 u2ClkNum; //clock number in spec.
+ gpio_clk_mode u2Mode;
+ // DCL_UINT16 u2Mode; //the CLKOUT value in spec.(by chip)
+} GPIO_CTRL_SET_CLK_OUT_T;
+
+
+/* FOR GPIO_CMD_SET_CLK_DIV control command. */
+typedef struct
+{
+ DCL_UINT16 u2ClkNum; //clock number in spec.
+ gpio_clk_div u2Div;
+ //DCL_UINT16 u2Div; //the CLKOUT value in spec.(by chip)
+}GPIO_CTRL_SET_CLK_DIV_T;
+
+/* FOR GPIO_CTRL_WRITE_FOR_SPI_T control command. */
+typedef struct
+{
+ DCL_UINT8 data;
+ DCL_UINT16 no;
+ DCL_UINT16 remainder_shift;
+} GPIO_CTRL_WRITE_FOR_SPI_T;
+
+/* FOR GPIO_CMD_SET_DRIVE and GPIO_CMD_RETURN_DRIVE control command. */
+typedef struct
+{
+ #define GPIO_DRIVE_MODE_0 0 // 4mA
+ #define GPIO_DRIVE_MODE_1 1 // 8mA
+ #define GPIO_DRIVE_MODE_2 2 // 12mA
+ #define GPIO_DRIVE_MODE_3 3 // 16mA
+ DCL_UINT8 u1DriveMode; //GPIO drive mode value in spec
+}GPIO_CTRL_RETURN_DRIVE_T,GPIO_CTRL_SET_DRIVE_T;
+
+
+/* FOR GPIO_CMD_RETURN_OWNERSHIP control command. */
+typedef struct
+{
+ #define GPIO_MD_OWNERSHIP 0
+ #define GPIO_AP_OWNERSHIP 1
+ DCL_UINT8 u1OwnerShip; //GPIO ownership value in spec
+}GPIO_CTRL_RETURN_OWNERSHIP_T;
+
+
+#ifdef __BUILD_DOM__
+/*The GPIO command prarmeter data structure for each command. that's enum in in DCL_CTRL_DATA_T*/
+typedef struct
+{
+ GPIO_CTRL_READ_T rRead; /*data structure for GPIO_CMD_READ control command */
+ GPIO_CTRL_RETURN_MODE_T rReturnMode; /*data structure for GPIO_CMD_RETURN_MODE control command*/
+ GPIO_CTRL_RETURN_DIR_T rReturnDir; /*data structure for GPIO_CMD_RETURN_DIR control command */
+ GPIO_CTRL_RETURN_OUT_T rReturnOut; /*data structure for GPIO_CMD_RETURN_OUT control command */
+ GPIO_CTRL_RETURN_AP_T rReturnAp;
+ GPIO_CTRL_SET_DINV_T rSetDinv; /*data structure for GPIO_CMD_SET_DINV control command */
+ GPIO_CTRL_SET_DEBUG_T rSetDebug; /*data structure for GPIO_CMD_SET_DEBUG control command */
+ GPIO_CTRL_SET_CLK_OUT_T rSetClkOut; /*data structure for GPIO_CMD_SET_CLK_OUT control command */
+ GPIO_CTRL_SET_CLK_DIV_T rSetClkDiv;
+ GPIO_CTRL_WRITE_FOR_SPI_T rWriteSpi; /*data structure for GPIO_CTRL_WRITE_FOR_SPI control command */
+ GPIO_CTRL_SET_DRIVE_T rSetDrive; /*data structure for GPIO_CMD_SET_DRIVE control command */
+ GPIO_CTRL_RETURN_DRIVE_T rReturnDrive; /*data structure for GPIO_CMD_RETURN_DRIVE control command */
+ GPIO_CTRL_RETURN_OWNERSHIP_T rReturnOwnership; /*data structure for GPIO_CMD_RETURN_OWNERSHIP control command */
+ GPO_CTRL_RETURN_MODE_T oReturnMode; /*data structure for GPO_CMD_RETURN_OUT control command */
+ GPO_CTRL_RETURN_OUT_T oReturnOut; /*data structure for GPO_CMD_RETURN_MODE control command */
+}DCL_CTRL_DATA_T;
+#else
+#define GPIO_CTRLS \
+ GPIO_CTRL_READ_T rRead; \
+ GPIO_CTRL_RETURN_MODE_T rReturnMode; \
+ GPIO_CTRL_RETURN_DIR_T rReturnDir; \
+ GPIO_CTRL_RETURN_OUT_T rReturnOut; \
+ GPIO_CTRL_RETURN_AP_T rReturnAp; \
+ GPIO_CTRL_SET_DINV_T rSetDinv; \
+ GPIO_CTRL_SET_DEBUG_T rSetDebug; \
+ GPIO_CTRL_SET_CLK_OUT_T rSetClkOut; \
+ GPIO_CTRL_SET_CLK_DIV_T rSetClkDiv; \
+ GPIO_CTRL_WRITE_FOR_SPI_T rWriteSpi; \
+ GPIO_CTRL_SET_DRIVE_T rSetDrive; \
+ GPIO_CTRL_RETURN_DRIVE_T rReturnDrive; \
+ GPIO_CTRL_RETURN_OWNERSHIP_T rReturnOwnership; \
+ GPO_CTRL_RETURN_MODE_T oReturnMode; \
+ GPO_CTRL_RETURN_OUT_T oReturnOut;
+#endif //__BUILD_DOM__
+#endif // #ifndef __DCL_GPIO_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+#if defined(DCL_DEFINITION_PROTOTYPE)
+#ifndef __DCL_GPIO_H_PROTOTYPE__
+#define __DCL_GPIO_H_PROTOTYPE__
+
+// MoDIS parser skip start
+
+/*************************************************************************
+* FUNCTION
+* DclGPIO_Initialize
+*
+* DESCRIPTION
+* This function is to initialize GPIO module. Note that all the GPIO pin
+* will be set to a predefined state.
+*
+* PARAMETERS
+* none
+*
+* RETURN VALUES
+* none
+*
+*************************************************************************/
+extern DCL_STATUS DclGPIO_Initialize(void);
+
+/*************************************************************************
+* FUNCTION
+* DclGPIO_Open
+* DESCRIPTION
+* This function is to open the GPIO module and get a handle. Note that multiple opens are allowed.
+*
+* PARAMETERS
+* eDev: - only valid for DCL_GPIO,DCL_GPO,DCL_GPIO_CLK.
+* flags: - no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURN VALUES
+* DCL_HANDLE_INVALID: - Open failed.
+* other value: - a valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclGPIO_Open(DCL_DEV dev, DCL_FLAGS flags);
+
+/*************************************************************************
+* FUNCTION
+* DclGPIO_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the GPIO module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURN VALUES
+* STATUS_UNSUPPORTED:
+*
+*************************************************************************/
+extern DCL_STATUS DclGPIO_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+
+/*************************************************************************
+* FUNCTION
+* DclGPIO_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the GPIO module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURN VALUES
+* STATUS_UNSUPPORTED:
+*
+*************************************************************************/
+extern DCL_STATUS DclGPIO_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+
+/*************************************************************************
+* FUNCTION
+* DclGPIO_Configure
+*
+* DESCRIPTION
+* This function is not supported for the GPIO module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURN VALUES
+* STATUS_UNSUPPORTED:
+*
+*************************************************************************/
+extern DCL_STATUS DclGPIO_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+
+/*************************************************************************
+* FUNCTION
+* DclGPIO_RegisterCallback
+*
+* DESCRIPTION
+* This function is not supported for the GPIO module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURN VALUES
+* STATUS_UNSUPPORTED:
+*
+*************************************************************************/
+extern DCL_STATUS DclGPIO_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+
+/*************************************************************************
+* FUNCTION
+* DclGPIO_Control
+*
+* DESCRIPTION
+* This function is to send command to control the GPIO module.
+*
+* PARAMETERS
+* handle: - a valid handle return by DclGPIO_Open()
+* cmd: - a control command for GPIO module
+* 1. GPIO_CMD_READ: to read the input value from the GPIO port contain in handle.
+* 2. GPIO_CMD_WRITE_LOW: to write low to the output of GPIO port contain in handle.
+* 3. GPIO_CMD_WRITE_HIGH: to write high to the output of GPIO port contain in handle.
+* 4. GPIO_CMD_SET_MODE_0: to set the mode of the GPIO port contain in handle as mode 0.
+* 5. GPIO_CMD_SET_MODE_1: to set the mode of the GPIO port contain in handle as mode 1.
+* 6. GPIO_CMD_SET_MODE_2: to set the mode of the GPIO port contain in handle as mode 2.
+* 7. GPIO_CMD_SET_MODE_3: to set the mode of the GPIO port contain in handle as mode 3.
+* 8. GPIO_CMD_SET_DIR_OUT: to set the direction of the GPIO port as output.
+* 9. GPIO_CMD_SET_DIR_IN: to set the direction of the GPIO port as input.
+* 10. GPIO_CMD_RETURN_MODE: to get the mode of the GPIO port
+* 11. GPIO_CMD_RETURN_DIR: to get the direction of the GPIO port
+* 12. GPIO_CMD_RETURN_OUT: to return the output value of the GPIO port
+* 13. GPIO_CMD_ENABLE_PULL: to enable the pull resister for a GPIO port
+* 14. GPIO_CMD_DISABLE_PULL: to disenable the pull resister for a GPIO port
+* 15. GPIO_CMD_SET_PULL_HIGH: to select the pull up for a GPIO port
+* 16. GPIO_CMD_SET_PULL_LOW: to select the pull down for a GPIO port
+* 17. GPIO_CMD_SET_DINV: to set the inversion of a GPIO port
+* 18. GPIO_CMD_SET_DEBUG: to enable or disable debug mode
+* 19. GPIO_CMD_SET_CLK_OUT: to set the clock frequency for a clock output
+* 20. GPIO_CMD_SET_OWNERSHIP_TO_MD: to set ownership of a GPIO port to Modem side.
+* 21. GPIO_CMD_SET_OWNERSHIP_TO_AP: to set ownership of a GPIO port to AP side.
+* 22. GPIO_CMD_SET_DRIVE: to set the drive of a GPIO port.
+* 23. GPIO_CMD_RETURN_DRIVE: to return the drive of the GPIO port.
+* 24. GPIO_CMD_RETURN_OWNERSHIP: to return the ownership of the GPIO port.
+* 25. GPO_CMD_RETURN_MODE: to get the mode of the GPO port
+* 26. GPO_CMD_RETURN_OUT: to return the output value of the GPO port
+* 27. GPO_CMD_WRITE_HIGH: to write high to the output of GPO port contain in handle.
+* 28. GPO_CMD_WRITE_LOW: to write low to the output of GPO port contain in handle.
+* 29. GPO_CMD_MODE_SET_0: to set the mode of the GPIO port contain in handle as mode 0.
+* 30. GPO_CMD_MODE_SET_1: to set the mode of the GPI1 port contain in handle as mode 1.
+* 31. GPO_CMD_MODE_SET_2: to set the mode of the GPI2 port contain in handle as mode 2.
+* 32. GPO_CMD_MODE_SET_3: to set the mode of the GPI3 port contain in handle as mode 3.
+
+* 33. GPIO_CMD_SET_DIR_OUT_NO_IRQ_MASK: to set the direction of the GPIO port as output without IRQ protect.
+* 34. GPIO_CMD_SET_DIR_IN_NO_IRQ_MASK: to set the direction of the GPIO port as input without IRQ protect
+* 35. GPIO_CMD_WRITE_HIGH_NO_IRQ_MASK: to write high to the output of GPIO port contain in handle without IRQ protect.
+* 36. GPIO_CMD_WRITE_LOW_NO_IRQ_MASK: to write low to the output of GPIO port contain in handle without IRQ protect.
+* 37. GPIO_CMD_READ_NO_IRQ_MASK: to read the input value from the GPIO port contain in handle without IRQ protect..
+
+* 38. GPIO_CMD_WRITE_FOR_SPI_T:
+* data: - data for GPIO control command.
+* 1. GPIO_CMD_READ: pointer to a GPIO_CTRLS structure
+* 2. GPIO_CMD_WRITE_LOW: NULL.
+* 3. GPIO_CMD_WRITE_HIGH: NULL.
+* 4. GPIO_CMD_SET_MODE_0: NULL.
+* 5. GPIO_CMD_SET_MODE_1: NULL.
+* 6. GPIO_CMD_SET_MODE_2: NULL.
+* 7. GPIO_CMD_SET_MODE_3: NULL.
+* 8. GPIO_CMD_SET_DIR_OUT: NULL.
+* 9. GPIO_CMD_SET_DIR_IN: NULL.
+* 10. GPIO_CMD_RETURN_MODE: pointer to a GPIO_CTRL_RETURN_MODE_T structure
+* 11. GPIO_CMD_RETURN_DIR: pointer to a GPIO_CTRL_SET_DIR_T structure
+* 12. GPIO_CMD_RETURN_OUT: pointer to a GPIO_CTRL_RETURN_OUT_T structure
+* 13. GPIO_CMD_ENABLE_PULL: NULL.
+* 14. GPIO_CMD_DISABLE_PULL: NULL.
+* 15. GPIO_CMD_SET_PULL_HIGH: NULL.
+* 16. GPIO_CMD_SET_PULL_LOW: NULL.
+* 17. GPIO_CMD_SET_DINV: pointer to a GPIO_CTRL_SET_DINV_T structure
+* 18. GPIO_CMD_SET_DEBUG: pointer to a GPIO_CTRL_SET_DEBUG_T structure
+* 19. GPIO_CMD_SET_CLK_OUT: pointer to a GPIO_CTRL_SET_CLK_OUT_T structure
+* 20. GPIO_CMD_SET_OWNERSHIP_TO_MD: NULL.
+* 21. GPIO_CMD_SET_OWNERSHIP_TO_AP: NULL.
+* 22. GPIO_CMD_SET_DRIVE: pointer to a GPIO_CTRL_SET_DRIVE_T structure
+* 23. GPIO_CMD_RETURN_DRIVE: pointer to a GPIO_CTRL_RETURN_DRIVE_T structure
+* 24. GPIO_CMD_RETURN_OWNERSHIP: pointer to a GPIO_CTRL_RETURN_OWNERSHIP_T structure
+*
+* 25. GPO_CMD_RETURN_MODE: pointer to a GPO_CTRL_RETURN_MODE_T structure
+* 26. GPO_CMD_RETURN_OUT: pointer to a GPO_CTRL_RETURN_OUT_T structure
+* 27. GPO_CMD_WRITE_HIGH: NULL.
+* 28. GPO_CMD_WRITE_LOW: NULL.
+* 29. GPO_CMD_MODE_SET_0: NULL..
+* 30. GPO_CMD_MODE_SET_1: NULL..
+* 31. GPO_CMD_MODE_SET_2: NULL.
+* 32. GPO_CMD_MODE_SET_3: NULL.
+
+* 33. GPIO_CMD_SET_DIR_OUT_NO_IRQ_MASK: NULL.
+* 34. GPIO_CMD_SET_DIR_IN_NO_IRQ_MASK: NULL.
+* 35. GPIO_CMD_WRITE_HIGH_NO_IRQ_MASK: NULL.
+* 36. GPIO_CMD_WRITE_LOW_NO_IRQ_MASK: NULL.
+* 37. GPIO_CMD_READ_NO_IRQ_MASK: pointer to a GPIO_CTRLS structure
+
+* 38. GPIO_CMD_WRITE_FOR_SPI_T: pointer to GPIO_CTRL_WRITE_FOR_SPI_T
+* RETURN VALUES
+* STATUS_OK: - command is executed successfully.
+* STATUS_FAIL: - command is failed.
+* STATUS_INVALID_CMD: - The command is invalid.
+* STATUS_INVALID_DCL_HANDLE: - The handle is invalid.
+* STATUS_INVALID_CTRL_DATA: - The ctrl data is not valid.
+*************************************************************************/
+extern DCL_STATUS DclGPIO_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+
+/*************************************************************************
+* FUNCTION
+* DclGPIO_Close
+*
+* DESCRIPTION
+* This function is not supported for the GPIO module now.
+*
+* PARAMETERS
+* handle: the handle that return by DclGPIO_Open.
+*
+* RETURN VALUES:
+* STATUS_UNSUPPORTED:
+*
+*************************************************************************/
+extern DCL_STATUS DclGPIO_Close(DCL_HANDLE handle);
+
+// MoDIS parser skip end
+
+#endif // #ifndef __DCL_GPIO_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
+
+
diff --git a/mcu/interface/driver/peripheral/dcl_gpt.h b/mcu/interface/driver/peripheral/dcl_gpt.h
new file mode 100644
index 0000000..2747c4b
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_gpt.h
@@ -0,0 +1,596 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_gpt.h
+ *
+ * Project:
+ * --------
+ * TATAKA
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for GPT.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_GPT_H_STRUCT__
+#define __DCL_GPT_H_STRUCT__
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+
+// GPT Interrupt Interval. [write to hardware register.]
+// put this macro in here, becasue it will be used in alerter.c
+#define gptimer_interval 10
+/*******************************************************************************
+ * DCL_OPTIONS for GPT
+ *******************************************************************************/
+#define GPT_OPTIONS
+
+/*******************************************************************************
+ * DCL_CONFIGURE_T for GPT
+ *******************************************************************************/
+
+
+/*******************************************************************************
+ * DCL_EVENT
+ *******************************************************************************/
+#define GPT_EVENTS \
+ EVENT_HGPT_TIMEOUT = 0x1,
+
+/*******************************************************************************
+ * DCL_CTRL_CMD
+ *******************************************************************************/
+ #ifdef __BUILD_DOM__
+/*
+* The GPIO Command values in DCL_CTRL_CMD_T Enum of dcl.h
+* DCL_CTRL_DATA_T Define the Control data structure for each module's command
+*/
+typedef enum
+{
+ SGPT_CMD_START, //GPT Start command. <DCL_GPT_CB>
+ SGPT_CMD_STOP, //GPT Stop command. <DCL_GPT_CB>
+ SGPT_CMD_GET_REMAINING_TICK, //LITE GPT Used Command
+ SGPT_CMD_BUSYWAIT, //GPT Busywait command, that's only support to DCL_GPT_BusyWait.
+ SGPT_CMD_RUNNING_TICK, // C2K to Get running tick number
+ SGPT_CMD_MODIFY_CNT, //C2K to modify auto repeat GPT duration
+
+ SGPT2_CMD_START, //for gpt2 start command.
+ SGPT2_CMD_STOP,
+ SGPT2_CMD_SET_COUNTVALUE,
+ SGPT2_CMD_REGISTERCALLBACK,
+ SGPT2_CMD_SET_CLK,
+
+ FGPT_CMD_START, //Free run GPT start command <DCL_GPT_FreeRUN3 & DCL_GPT_FreeRUN4>
+ FGPT_CMD_STOP, //Free run GPT Stop command <DCL_GPT_FreeRUN3 & DCL_GPT_FreeRUN4>
+ FGPT_CMD_RETURN_COUNT, //Free run GPT return current count value. <DCL_GPT_FreeRUN3 & DCL_GPT_FreeRUN4>
+}DCL_CTRL_CMD_T;
+#else
+#define GPT_CMDS \
+ SGPT_CMD_START, \
+ SGPT_CMD_STOP, \
+ SGPT_CMD_GET_REMAINING_TICK, \
+ SGPT_CMD_BUSYWAIT, \
+ SGPT_CMD_RUNNING_TICK, \
+ SGPT_CMD_MODIFY_CNT, \
+ SGPT2_CMD_START, \
+ SGPT2_CMD_STOP, \
+ SGPT2_CMD_SET_COUNTVALUE, \
+ SGPT2_CMD_REGISTERCALLBACK, \
+ SGPT2_CMD_SET_CLK, \
+ FGPT_CMD_START, \
+ FGPT_CMD_STOP, \
+ FGPT_CMD_RETURN_COUNT,
+#endif
+
+/* For SGPT_CMD_START command. */
+typedef struct
+{
+ DCL_UINT16 u2Tick;//The time Ticks(a tick is 10ms) that register callback function delay to wake up.
+ DCL_UINT32 u4Tick;
+ void (*pfCallback)(void *); //register callback function
+ void *vPara; //parameter of register callback function
+} SGPT_CTRL_START_T;
+
+/* For FGPT_CMD_RETURN_COUNT command. */
+typedef DCL_UINT16 FGPT_CTRL_RETURN_COUNT_T;
+/*For SGPT_CMD_BUSYWAIT command*/
+typedef DCL_UINT16 GPT_BUSYWAIT_COUNT;
+
+
+//added by dongming for gpt2
+typedef struct
+{
+ DCL_UINT16 u2CountValue;
+ DCL_BOOL fgAutoReload;
+} SGPT2_CTRL_RESET_DATA_T;
+
+typedef struct
+{
+ DCL_UINT32 u4Clock; // for gpt2 SGPT2_CTRL_CLK_T enum
+} SGPT2_CTRL_CLK_T;
+
+
+typedef DCL_UINT32 DCL_EVENT_NEW;
+
+typedef void (*SGPT2_CALLBACK_FUNC)(DCL_EVENT_NEW event);
+
+typedef struct{
+ SGPT2_CALLBACK_FUNC gpt2CallBack;
+}SGPT2_CALLBACK_FUNC_T;
+
+
+#ifdef __BUILD_DOM__
+/*The GPIO command prarmeter data structure for each command. that's enum in in DCL_CTRL_DATA_T*/
+typedef enum
+ {
+ SGPT_CTRL_START_T rSGPTStart, /* For SGPT_CMD_START command. */
+ FGPT_CTRL_RETURN_COUNT_T u2RetCount, /* For FGPT_CMD_RETURN_COUNT command. */
+ GPT_BUSYWAIT_COUNT uBusyWaitcount, /*For SGPT_CMD_BUSYWAIT command*/
+ SGPT2_CTRL_RESET_DATA_T rHGPTReset, /*add for gpt2 reset command */
+ SGPT2_CALLBACK_FUNC_T gpt2_callback,/*add for gpt2 registercallback command */
+ SGPT2_CTRL_CLK_T gpt2_clk,
+ }DCL_CTRL_DATA_T;
+#else
+#define GPT_CTRLS \
+ SGPT_CTRL_START_T rSGPTStart; \
+ FGPT_CTRL_RETURN_COUNT_T u2RetCount; \
+ GPT_BUSYWAIT_COUNT uBusyWaitcount;\
+ SGPT2_CTRL_RESET_DATA_T rHGPTReset;\
+ SGPT2_CALLBACK_FUNC_T gpt2_callback;\
+ SGPT2_CTRL_CLK_T gpt2_clk;
+#endif // __BUILD_DOM__
+
+#endif // #ifndef __DCL_GPT_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+#ifndef DCL_GPT_H_
+#define DCL_GPT_H_
+#define MAX_GPT_ITEMS 32
+#define DSP_USER_NUM 4
+#define EMPTY_GPT_CB_HANDLER 0x7F
+
+#if defined(__FPGA__)
+/* ALTERA JADE Version */
+//#define LITEGPT_CLOCK 31250//31250
+//#define LITEGPT_US_TO_TICK(us) ((us)/32)
+/* HAPS JADE Version */
+#define LITEGPT_CLOCK 31920//31920
+#define LITEGPT_US_TO_TICK(us) ((us)/125)
+
+#else
+
+#define LITEGPT_CLOCK 32768
+#define LITEGPT_US_TO_TICK(us) (((us)*2)/61)
+#endif
+
+//static kal_bool fgGPT1Init = KAL_FALSE;
+
+typedef struct
+{
+ void (*gpt1_func)(void);
+ void (*gpt2_func)(void);
+}gpt_func;
+
+typedef struct
+{
+ kal_uint32 tick;
+ void (*gptimer_func)(void *parameter);
+ void *parameter;
+}gptimer_item;
+
+typedef struct
+{
+ kal_bool execute;
+ kal_uint32 tick;
+ void (*gptimer_func)(void *parameter);
+ void *parameter;
+}gptimer_multiple;
+
+typedef struct
+{
+ kal_uint32 status; /*1,activated ,0:de-activated*/
+ kal_bool GPTSTOP;
+ kal_uint32 Hgpt_handle;
+ kal_uint16 GPT_TICK;
+ kal_uint8 MAX_GPTIMER_ITEMS; // Indicate the current registered GPT users
+ kal_uint8 GPTUsed[32]; /* 0: Not registered by user, 1: Registerd by used*/
+ /* Reset to 0 when user release GPT handle*/
+ gptimer_item GPTItems[32]; /*support at most 32 gptimer*/
+ gpt_func GPT_FUNC;
+ kal_hisrid hisr;
+} GPTStruct;
+#endif
+#if defined(DCL_DEFINITION_PROTOTYPE)
+#ifndef __DCL_GPT_H_PROTOTYPE__
+#define __DCL_GPT_H_PROTOTYPE__
+
+
+/*************************************************************************
+* FUNCTION
+* DclSGPT_Initialize
+*
+* DESCRIPTION
+* This function is to initialize SW GPT module.
+*
+* PARAMETERS
+* DCL_STATUS_OK
+*
+* RETURNS
+* none
+*
+*************************************************************************/
+extern DCL_STATUS DclSGPT_Initialize(void);
+
+/*************************************************************************
+* FUNCTION
+* DclSGPT_Open
+*
+* DESCRIPTION
+* This function is to open the SW GPT module and get a handle.
+* Note that for DCL_GPT_CB, multiple opens are allowed.For DCL_GPT_BusyWait, Multiple opens are not support.
+*
+* PARAMETERS
+* eDev: only valid for DCL_GPT_CB DCL_GPT_BusyWait
+* flags: no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURN VALUES
+* DCL_HANDLE_INVALID: Open failed.
+* other value: Open success, return a a valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclSGPT_Open(DCL_DEV dev, DCL_FLAGS flags);
+
+/*************************************************************************
+* FUNCTION
+* DclSGPT_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the SW GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURN VALUES
+* STATUS_UNSUPPORTED:
+*
+*************************************************************************/
+extern DCL_STATUS DclSGPT_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+
+/*************************************************************************
+* FUNCTION
+* DclSGPT_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the SW GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURN VALUES
+* STATUS_UNSUPPORTED:
+*
+*************************************************************************/
+extern DCL_STATUS DclSGPT_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+
+/*************************************************************************
+* FUNCTION
+* DclSGPT_Configure
+*
+* DESCRIPTION
+* This function is not supported for the SW GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURN VALUES
+* STATUS_UNSUPPORTED:
+*
+*************************************************************************/
+extern DCL_STATUS DclSGPT_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+
+/*************************************************************************
+* FUNCTION
+* DclSGPT_RegisterCallback
+*
+* DESCRIPTION
+* This function is not supported for the SW GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURN VALUES
+* STATUS_UNSUPPORTED:
+*
+*************************************************************************/
+extern DCL_STATUS DclSGPT_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+
+/*************************************************************************
+* FUNCTION
+* DclSGPT_Control
+*
+* DESCRIPTION
+* This function is to send command to control the SW GPT module.
+*
+* Now, we support two kind of GPT function.
+* For DCL_GPT_CB timer, you can register a callback function with some tick waiting to run.(a tick is 10ms)
+* when timeout ,the callback function will be run in DRV_HISR.
+*
+* For DCL_GPT_BusyWait, You can call DclSGPT_Control with SGPT_CMD_BUSYWAIT command, the programm will be loop in this
+* function until timeout. (a busywait tick is 1ms).
+*
+* PARAMETERS
+* handle: a valid handle return by DclSGPT_Open()
+* cmd: a control command for GPT module
+* 1. SGPT_CMD_START - to start a GPT timer
+* 2. SGPT_CMD_STOP- to stop a GPT timer
+* 3. SGPT_CMD_BUSYWAIT - to start GPT Busywait function.
+* data: data structure for control command.
+* 1. SGPT_CMD_START- pointer to a SGPT_CTRL_START_T structure
+* 2. SGPT_CMD_STOP- a NULL pointer
+* 3. SGPT_CMD_BUSYWAIT - a pointer to GPT_BUSYWAIT_COUNT;
+*
+* RETURN VALUES
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* DCL_HANDLE_INVALID: It's a invaild handle.
+* STATUS_INVALID_CMD: It's a invalid command.
+*
+*************************************************************************/
+extern DCL_STATUS DclSGPT_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+
+/*************************************************************************
+* FUNCTION
+* DclSGPT_Close
+*
+* DESCRIPTION
+* This function is to close the SW GPT module.
+*
+* PARAMETERS
+* handle: hanlde previous got from DclSGPT_Open()
+*
+* RETURN VALUES
+* DCL_STATUS_OK: successfully close the SW GPT module.
+* DCL_STATUS_fail: fails to close the SW GPT module.
+* STATUS_INVALID_HANDLE: invalid handle.
+*************************************************************************/
+extern DCL_STATUS DclSGPT_Close(DCL_HANDLE *handle);
+
+/*************************************************************************
+* FUNCTION
+* DclFGPT_Initialize
+*
+* DESCRIPTION
+* This function is to initialize the free run GPT module.
+*
+* PARAMETERS
+* None
+*
+* RETURN VALUES
+* DCL_STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclFGPT_Initialize(void);
+
+/*************************************************************************
+* FUNCTION
+* DclFGPT_Open
+*
+* DESCRIPTION
+* This function is to open a free run GPT module if it exists. Note
+* that it supports multiple opens and no need to close it.
+*
+* PARAMETERS
+* eDev: only valid for <DCL_GPT_FreeRUN3 & DCL_GPT_FreeRUN4>
+* flags: no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURN VALUES
+* DCL_HANDLE_INVALID: Open failed. It means no free run GPT exists or
+* open a wrong device.
+* other value: a valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclFGPT_Open(DCL_DEV dev, DCL_FLAGS flags);
+
+/*************************************************************************
+* FUNCTION
+* DclFGPT_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the free run GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclFGPT_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+
+/*************************************************************************
+* FUNCTION
+* DclFGPT_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the free run GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclFGPT_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+
+/*************************************************************************
+* FUNCTION
+* DclFGPT_Configure
+*
+* DESCRIPTION
+* This function is not supported for the free run GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclFGPT_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+
+/*************************************************************************
+* FUNCTION
+* DclFGPT_RegisterCallback
+*
+* DESCRIPTION
+* This function is not supported for the free run GPT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclFGPT_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+
+/*************************************************************************
+* FUNCTION
+* DclFGPT_Control
+*
+* DESCRIPTION
+* This function is to send command to control the free run GPT module.
+*
+* PARAMETERS
+* handle: a valid handle return by DclFGPT_Open()
+* cmd: a control command for free ryb GPT module
+* 1. FGPT_CMD_START - to start free run gpt timer
+* 2. FGPT_CMD_STOP - to stop free run gpt timer
+* 3. FGPT_CMD_RETURN_COUNT - to get the timer count
+* data:
+* 1. FGPT_CMD_RETURN_COUNT- pointer to a FGPT_CTRL_RETURN_COUNT_T type
+* 2. FGPT_CMD_START - pointer to null
+* 3. FGPT_CMD_STOP -pointer to null
+*
+* RETURN VALUES
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed. No free run GPT is supported.
+* STATUS_INVALID_CMD: The command is invalid.
+* STATUS_INVALID_HANDLE: The handle is invalid.
+*
+*************************************************************************/
+extern DCL_STATUS DclFGPT_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+
+/*************************************************************************
+* FUNCTION
+* DclFGPT_Close
+*
+* DESCRIPTION
+* This function is to close the SW GPT module.
+*
+* PARAMETERS
+* handle: hanlde previous got from DclSGPT_Open()
+*
+* RETURN VALUES
+* DCL_STATUS_OK: successfully close the SW GPT module.
+* DCL_STATUS_fail: fails to close the SW GPT module.
+* STATUS_INVALID_HANDLE: invalid handle.
+*
+*************************************************************************/
+extern DCL_STATUS DclFGPT_Close(DCL_HANDLE handle);
+
+#endif // #ifndef __DCL_GPT_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
+
+
diff --git a/mcu/interface/driver/peripheral/dcl_i2c.h b/mcu/interface/driver/peripheral/dcl_i2c.h
new file mode 100644
index 0000000..1363a50
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_i2c.h
@@ -0,0 +1,510 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_i2c.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for I2C.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_I2C_H_STRUCT__
+#define __DCL_I2C_H_STRUCT__
+
+/*******************************************************************************
+ * DCL_OPTIONS for I2C, not in use now.
+ *******************************************************************************/
+#define I2C_OPTIONS
+
+#include "dcl_i2c_owner.h"
+
+ /* I2C Transaction Mode*/
+typedef enum
+{
+ DCL_I2C_TRANSACTION_FAST_MODE, /* Fast Mode: < 400kbps */
+ DCL_I2C_TRANSACTION_HIGH_SPEED_MODE /* Hign Speed Mode: > 400kbps */
+}DCL_I2C_TRANSACTION_MODE;
+
+/* Transaction Type, for batch transaction use*/
+typedef enum
+{
+ DCL_I2C_TRANSACTION_WRITE, /* Single write */
+ DCL_I2C_TRANSACTION_READ, /* Single read */
+ DCL_I2C_TRANSACTION_CONT_WRITE, /* Continue write */
+ DCL_I2C_TRANSACTION_CONT_READ, /* Continue read */
+ DCL_I2C_TRANSACTION_WRITE_AND_READ /* Write and read. Note: This command can not be used, when using DMA to transfer but driver can only support DCL_I2C_DMA_SINGLE_CHANNEL. */
+}DCL_I2C_TRANSACTION_TYPE;
+
+/* Transaction result, for batch transaction query */
+typedef enum
+{
+ DCL_I2C_BATCH_TRANSACTION_SUCCESS, /* The prior batch transaction is successfully transmitted */
+ DCL_I2C_BATCH_TRANSACTION_FAIL, /* Something wrong was happened during the prior batch transaction */
+ DCL_I2C_BATCH_TRANSACTION_IS_BUSY /* I2C bus is occupied now */
+}DCL_I2C_BATCH_TRANSACTION_RESULT;
+
+/* DMA property that driver support, for user query */
+typedef enum
+{
+ DCL_I2C_DMA_NOT_SUPPORT, /* Driver do not support DMA */
+ DCL_I2C_DMA_DUAL_CHANNEL, /* Driver support dual channel DMA mode */
+ DCL_I2C_DMA_SINGLE_CHANNEL /* Driver support single channel DMA mode, not support WRITE_AND_READ when DMA is enabled */
+}DCL_I2C_DMA_PROPERTY;
+
+/* DCL I2C configure structure */
+typedef struct
+{
+ DCL_I2C_OWNER eOwner; /* The owner of I2C, defined in DCL_I2C_OWNER */
+ DCL_BOOL fgGetHandleWait; /* KAL_TRUE: wait until I2C is idle; KAL_FALSE: do not wait */
+ DCL_UINT8 u1SlaveAddress; /* Slave address */
+ DCL_UINT8 u1DelayLen; /* Wait delay between consecutive transfers (the unit is half pulse width) */
+ DCL_I2C_TRANSACTION_MODE eTransactionMode; /* Fast mode or high speed mode */
+ DCL_UINT32 u4FastModeSpeed; /* The transfer speed under fast mode. But even under high speed mode, you should alse configure this parameter */
+ DCL_UINT32 u4HSModeSpeed; /* The transfer speed under high speed mode */
+ DCL_BOOL fgEnableDMA; /* KAL_TRUE: use DMA to transfer data; KAL_FALSE: do not use DMA. Note: Make sure driver support DMA mode before you use it. */
+} I2C_CONFIG_T;
+
+/* DCL_CONFIGURE_T for I2C. */
+#define I2C_CONFIGS \
+ I2C_CONFIG_T rI2CCofig;
+
+/* DCL_EVENT for I2C, not in use now. */
+#define I2C_EVENTS
+
+#ifdef __BUILD_DOM__
+/* DCL_CTRL_CMD for I2C */
+typedef enum
+{
+ I2C_CMD_GET_TRANSACTION_MODE, /* Get transaction mode */
+ I2C_CMD_SET_TRANSACTION_SPEED, /* Set transaction speed */
+ I2C_CMD_SINGLE_WRITE, /* Single write of blocking mode */
+ I2C_CMD_SINGLE_READ, /* Single read of blocking mode */
+ I2C_CMD_CONT_WRITE, /* Continue write of blocking mode */
+ I2C_CMD_CONT_READ, /* Continue read of blocking mode */
+ I2C_CMD_WRITE_AND_READ, /* Write and read of blocking mode */
+ I2C_CMD_BATCH_TRANSACTION, /* Batch transaction which support non-blocking mode */
+ I2C_CMD_GET_BATCH_TRANSACTION_RESULT, /* Query the prior batch transaction result */
+ I2C_CMD_GET_DMA_PROPERTY, /* Get the DMA property which driver support */
+ I2C_CMD_ENABLE_DMA, /* Use DMA to transfer data. Note: Before you do this, please make sure that driver support DMA mode */
+ I2C_CMD_SET_SLAVE_ADDRESS /* Set the slave address of sensor */
+}DCL_CTRL_CMD_T;
+#else
+#define I2C_CMDS \
+ I2C_CMD_GET_TRANSACTION_MODE, \
+ I2C_CMD_SET_TRANSACTION_SPEED, \
+ I2C_CMD_SINGLE_WRITE, \
+ I2C_CMD_SINGLE_READ, \
+ I2C_CMD_CONT_WRITE, \
+ I2C_CMD_CONT_READ, \
+ I2C_CMD_WRITE_AND_READ, \
+ I2C_CMD_BATCH_TRANSACTION, \
+ I2C_CMD_GET_BATCH_TRANSACTION_RESULT, \
+ I2C_CMD_GET_DMA_PROPERTY, \
+ I2C_CMD_ENABLE_DMA, \
+ I2C_CMD_SET_SLAVE_ADDRESS,
+#endif /* __BUILD_DOM__ */
+
+/* For I2C_CMD_GET_TRANSACTION_MODE command. */
+typedef struct
+{
+ DCL_I2C_TRANSACTION_MODE eTransactionMode; /* Transaction mode */
+}I2C_CTRL_GET_TRANSACTION_MODE_T;
+/* For I2C_CMD_SET_TRANSACTION_SPEED command. */
+typedef struct
+{
+ DCL_I2C_TRANSACTION_MODE eTransactionMode; /* Transaction mode */
+ DCL_UINT32 u4FastModeSpeed; /* Fast mode speed */
+ DCL_UINT32 u4HSModeSpeed; /* High speed mode speed */
+}I2C_CTRL_SET_TRANSACTION_SPEED_T;
+/* For I2C_CMD_SINGLE_WRITE, I2C_CMD_SINGLE_READ command. */
+typedef struct
+{
+ DCL_UINT8 *pu1Data; /* Pointer to the buffer of data */
+ DCL_UINT32 u4DataLen; /* Data length */
+}I2C_CTRL_SINGLE_WRITE_T, I2C_CTRL_SINGLE_READ_T;
+/* For I2C_CMD_CONT_WRITE, I2C_CMD_CONT_READ command. */
+typedef struct
+{
+ DCL_UINT8 *pu1Data; /* Pointer to the buffer of data */
+ DCL_UINT32 u4DataLen; /* Data length of each transfer */
+ DCL_UINT32 u4TransferNum; /* Transfer number */
+}I2C_CTRL_CONT_WRITE_T, I2C_CTRL_CONT_READ_T;
+/* For I2C_CMD_WRITE_AND_READ command. */
+typedef struct
+{
+ DCL_UINT8 *pu1InData; /* Pointer to the read data */
+ DCL_UINT32 u4InDataLen; /* Read data length */
+ DCL_UINT8 *pu1OutData; /* Pointer to the write data */
+ DCL_UINT32 u4OutDataLen; /* Write data length */
+}I2C_CTRL_WRITE_AND_READE_T;
+/* For I2C_CTRL_BATCH_DATA_T structure. */
+typedef union
+{
+ I2C_CTRL_SINGLE_WRITE_T rSingleWrite; /* Single write */
+ I2C_CTRL_SINGLE_READ_T rSingleRead; /* Single read */
+ I2C_CTRL_CONT_WRITE_T rContWrite; /* Continue write */
+ I2C_CTRL_CONT_READ_T rContRead; /* Continue read */
+ I2C_CTRL_WRITE_AND_READE_T rWriteAndRead; /* Write and read. Note: this command can not be used, when using DMA to transfer but driver can only support DCL_I2C_DMA_SINGLE_CHANNEL. */
+}I2C_CTRL_TRANSACTION_DATA_T;
+/* For I2C_CTRL_BATCH_TRANSACTION_T structure. */
+typedef struct
+{
+ DCL_I2C_TRANSACTION_TYPE eTransactionType; /* Transaction type */
+ I2C_CTRL_TRANSACTION_DATA_T rTansactionData; /* Batch transaction data of corresponding transaction type */
+}I2C_CTRL_BATCH_DATA_T;
+/* For I2C_CMD_BATCH_TRANSACTION command. */
+typedef struct
+{
+ DCL_UINT32 u4BatchNum; /* Number of batches of this batch transaction */
+ I2C_CTRL_BATCH_DATA_T *prBatchData; /* Pointer to the buffer where stored the batches data*/
+}I2C_CTRL_BATCH_TRANSACTION_T;
+/* For I2C_CMD_GET_BATCH_TRANSACTION_RESULT command. */
+typedef struct
+{
+ DCL_I2C_BATCH_TRANSACTION_RESULT eBatchTransactionResult; /* Batch transaction result */
+ DCL_UINT32 u4BatchNum; /* The number of Batches have been transferred successfully */
+}I2C_CTRL_GET_BATCH_TRANSACTION_RESULT_T;
+/* For I2C_CMD_GET_DMA_PROPERTY command. */
+typedef struct
+{
+ DCL_I2C_DMA_PROPERTY eDMAProperty; /* DMA property */
+}I2C_CTRL_GET_DMA_PROPERTY_T;
+/* For I2C_CMD_ENABLE_DMA command. */
+typedef struct
+{
+ DCL_BOOL fgEnableDMA; /* KAL_TRUE: use DMA to transfer data; KAL_FALSE: do not use DMA. Note: Make sure driver support DMA mode before you use it. */
+}I2C_CTRL_ENABLE_DMA_T;
+/* For I2C_CMD_SET_SLAVE_ADDRESS command. */
+typedef struct
+{
+ DCL_UINT8 u1SlaveAddress; /* Slave address */
+}I2C_CTRL_SET_SLAVE_ADDRESS_T;
+
+#ifdef __BUILD_DOM__
+/* DCL_CTRL_DATA_T for I2C: Define the Control data structure for each command */
+typedef union
+{
+ I2C_CTRL_GET_TRANSACTION_MODE_T rGetTransactionMode; /* Get transaction mode */
+ I2C_CTRL_SET_TRANSACTION_SPEED_T rSetTransactionSpeed; /* Set transaction speed */
+ I2C_CTRL_SINGLE_WRITE_T rSingleWrite; /* Single write of blocking mode */
+ I2C_CTRL_SINGLE_READ_T rSingleRead; /* Single read of blocking mode */
+ I2C_CTRL_CONT_WRITE_T rContWrite; /* Continue write of blocking mode */
+ I2C_CTRL_CONT_READ_T rContRead; /* Continue read of blocking mode */
+ I2C_CTRL_WRITE_AND_READE_T rWriteAndRead; /* Write and read of blocking mode */
+ I2C_CTRL_BATCH_TRANSACTION_T rBatchTransaction; /* Batch transaction which support non-blocking mode */
+ I2C_CTRL_GET_BATCH_TRANSACTION_RESULT_T rGetBatchTransactionResult; /* Query the prior batch transaction result */
+ I2C_CTRL_GET_DMA_PROPERTY_T rGetDMAProperty; /* Get the DMA property which driver support */
+ I2C_CTRL_ENABLE_DMA_T rEnableDMA; /* Use DMA to transfer data. Note: Before you do this, please make sure that driver support DMA mode */
+ I2C_CTRL_SET_SLAVE_ADDRESS_T rSetSlaveAddress; /* Set slave address of sensor */
+}DCL_CTRL_DATA_T;
+#else
+#define I2C_CTRLS \
+ I2C_CTRL_GET_TRANSACTION_MODE_T rGetTransactionMode; \
+ I2C_CTRL_SET_TRANSACTION_SPEED_T rSetTransactionSpeed; \
+ I2C_CTRL_SINGLE_WRITE_T rSingleWrite; \
+ I2C_CTRL_SINGLE_READ_T rSingleRead; \
+ I2C_CTRL_CONT_WRITE_T rContWrite; \
+ I2C_CTRL_CONT_READ_T rContRead; \
+ I2C_CTRL_WRITE_AND_READE_T rWriteAndRead; \
+ I2C_CTRL_BATCH_TRANSACTION_T rBatchTransaction; \
+ I2C_CTRL_GET_BATCH_TRANSACTION_RESULT_T rGetBatchTransactionResult; \
+ I2C_CTRL_GET_DMA_PROPERTY_T rGetDMAProperty; \
+ I2C_CTRL_ENABLE_DMA_T rEnableDMA; \
+ I2C_CTRL_SET_SLAVE_ADDRESS_T rSetSlaveAddress;
+#endif /* __BUILD_DOM__ */
+
+#endif // #ifndef __DCL_I2C_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_I2C_H_PROTOTYPE__
+#define __DCL_I2C_H_PROTOTYPE__
+
+/*************************************************************************
+* FUNCTION
+* DclSI2C_Initialize
+*
+* DESCRIPTION
+* This function is to initialize S/W I2C module, should be called only once when driver init.
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclSI2C_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclSI2C_Open
+*
+* DESCRIPTION
+* This function is to open the I2C module and return a handle
+*
+* PARAMETERS
+* dev: I2C device ID. Only valid for DCL_I2C.
+* flags: User of I2C. Should be one of the enum DCL_I2C_OWNER.
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Incorrect device ID.
+* DCL_HANDLE_OCCUPIED: This user has opened a handle, which is in use.
+* Other value: A valid handle
+*
+* EXAMPLE
+* <code>
+* DCL_HANDLE i2c_handle = NULL;
+* if (NULL == i2c_handle)
+* {
+* i2c_handle = DclSI2C_Open(DCL_I2C, DCL_I2C_OWNER_CAMERA);
+* }
+* </code>
+*
+*************************************************************************/
+extern DCL_HANDLE DclSI2C_Open(DCL_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* DclSI2C_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the I2C module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclSI2C_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclSI2C_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the I2C module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclSI2C_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclSI2C_Configure
+*
+* DESCRIPTION
+* This function is to configure the I2C module.
+*
+* PARAMETERS
+* handle: the returned handle value of DclSI2C_Open
+* configure: a structure which include the I2C configuration.
+*
+* RETURNS
+* STATUS_OK: Successfully configure I2C module.
+* STATUS_INVALID_DCL_HANDLE: It's a invalid handle.
+* STATUS_NOT_OPENED: The module has not been opened.
+* STATUS_INVALID_CONFIGURATION: The configuration is invalid.
+* STATUS_DEVICE_NOT_SUPPORT_DMA: User wants to use DMA transfer, but driver do not support.
+*
+* EXAMPLE
+* <code>
+* I2C_CONFIG_T cfg;
+* cfg.eOwner = DCL_I2C_OWNER_CAMERA;
+* cfg.fgGetHandleWait = KAL_TRUE;
+* cfg.u1SlaveAddress = SLAVE_ADDRESS_ID;
+* cfg.u1DelayLen = 0;
+* cfg.eTransactionMode = DCL_I2C_TRANSACTION_FAST_MODE;
+* cfg.u4FastModeSpeed = 300;
+* cfg.u4HSModeSpeed = 0;
+* cfg.fgEnableDMA = KAL_FALSE;
+* if (STATUS_OK != DclSI2C_Configure(i2c_handle, (DCL_CONFIGURE_T *)&cfg))
+* {
+* ASSERT(0);
+* }
+* </code>
+*
+*************************************************************************/
+extern DCL_STATUS DclSI2C_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+/*************************************************************************
+* FUNCTION
+* DclSI2C_RegisterCallback
+*
+* DESCRIPTION
+* This function is to set callback function for the I2C module, which is not supported for the I2C module now.
+*
+* PARAMETERS
+* handle: the returned handle value of DclSI2C_Open
+* event: Supported events:
+* callback: the callback function for registered events
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclSI2C_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+/*************************************************************************
+* FUNCTION
+* DclSI2C_Control
+*
+* DESCRIPTION
+* This function is to send command to control the I2C module.
+*
+* PARAMETERS
+* handle: The handle value returned from DclSI2C_Open
+* cmd: A control command for I2C module
+* 1. I2C_CMD_GET_TRANSACTION_MODE: to get transaction mode
+* 2. I2C_CMD_SET_TRANSACTION_SPEED: to set transaction speed
+* 3. I2C_CMD_SINGLE_WRITE: to perform a single WRITE
+* 4. I2C_CMD_SINGLE_READ: to perform a single READ
+* 5. I2C_CMD_CONT_WRITE: to perform a continuous WRITE
+* 6. I2C_CMD_CONT_READ: to perform a continuous READ
+* 7. I2C_CMD_WRITE_AND_READ: to perform a specific sequence "WRITE then READ"
+* 8. I2C_CMD_BATCH_TRANSACTION: to perform a non-blocking batch transaction
+* 9. I2C_CMD_GET_BATCH_TRANSACTION_RESULT: to get batch transaction result
+* 10. I2C_CMD_GET_DMA_PROPERTY: to get DMA property
+* 11. I2C_CMD_ENABLE_DMA: to enable/disable DMA
+* data: The data of the control command
+* 1. I2C_CMD_GET_TRANSACTION_MODE: pointer to a I2C_CTRL_GET_TRANSACTION_MODE_T structure
+* 2. I2C_CMD_SET_TRANSACTION_SPEED: pointer to a I2C_CTRL_SET_TRANSACTION_SPEED_T structure
+* 3. I2C_CMD_SINGLE_WRITE: pointer to a I2C_CTRL_SINGLE_WRITE_T structure
+* 4. I2C_CMD_SINGLE_READ: pointer to a I2C_CTRL_SINGLE_READ_T structure
+* 5. I2C_CMD_CONT_WRITE: pointer to a I2C_CTRL_CONT_WRITE_T structure
+* 6. I2C_CMD_CONT_READ: pointer to a I2C_CTRL_CONT_READ_T structure
+* 7. I2C_CMD_WRITE_AND_READ: pointer to a I2C_CTRL_WRITE_AND_READE_T structure
+* 8. I2C_CMD_BATCH_TRANSACTION: pointer to a I2C_CTRL_BATCH_TRANSACTION_T structure
+* 9. I2C_CMD_GET_BATCH_TRANSACTION_RESULT: pointer to a I2C_CTRL_GET_BATCH_TRANSACTION_RESULT_T structure
+* 10. I2C_CMD_GET_DMA_PROPERTY: pointer to a I2C_CTRL_GET_DMA_PROPERTY_T structure
+* 11. I2C_CMD_ENABLE_DMA: pointer to a I2C_CTRL_ENABLE_DMA_T structure
+*
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+* STATUS_INVALID_DCL_HANDLE: It's a invalid handle.
+* STATUS_NOT_OPENED: The module has not been opened.
+* STATUS_DEVICE_IS_BUSY: I2C bus is occupied by others, but this user choose not to wait. Only valid for blocking transaction mode.
+* STATUS_ACKERR: ACK error occured. Only valid for blocking transaction mode.
+* STATUS_HS_NACKERR: Master code nack error occured. Only valid for blocking transaction mode.
+*
+* EXAMPLE
+* <code>
+* kal_uint8 out_buff[3];
+* out_buff[0] = REG_ADDR >> 8;
+* out_buff[1] = REG_ADDR;
+* out_buff[1] = WRT_DATA;
+* DCL_STATUS_T rt;
+* DCL_CTRL_CMD cmd = I2C_CMD_SINGLE_WRITE;
+* I2C_CTRL_SINGLE_WRITE_T write_data;
+* write_data.pu1Data = out_buff;
+* write_data.u4DataLen = 3;
+* rt = DclSI2C_Control(i2c_handle, cmd, (DCL_CTRL_DATA_T *)&write_data);
+* if (STATUS_OK != rt)
+* {
+* ASSERT(0);
+* }
+* </code>
+*
+*************************************************************************/
+extern DCL_STATUS DclSI2C_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclSI2C_Close
+*
+* DESCRIPTION
+* This function is to close the I2C module.
+*
+* PARAMETERS
+* handle: the returned handle value of DclSI2C_Open
+*
+* RETURNS
+* STATUS_OK
+*
+* EXAMPLE
+* <code>
+* if (i2c_handle)
+* {
+* DclSI2C_Close(i2c_handle);
+* i2c_handle = NULL;
+* }
+* </code>
+*
+*************************************************************************/
+extern DCL_STATUS DclSI2C_Close(DCL_HANDLE handle);
+
+
+#endif // #ifndef __DCL_I2C_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
+
+
+
diff --git a/mcu/interface/driver/peripheral/dcl_i2c_owner.h b/mcu/interface/driver/peripheral/dcl_i2c_owner.h
new file mode 100644
index 0000000..2ead8af
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_i2c_owner.h
@@ -0,0 +1,160 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * sccb_v2_custom.c
+ *
+ *
+ * Description:
+ * ------------
+ * SCCB/I2C V2 Driver
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
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+ * removed!
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+ *
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+ * removed!
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+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ *****************************************************************************/
+#ifndef __DCL_I2C_CUSTOM_OWNER_STRUCT__
+#define __DCL_I2C_CUSTOM_OWNER_STRUCT__
+
+//#if (defined(DRV_I2C_25_SERIES))
+//Note: DCL_I2C_OWNER is used in dcl_i2c.h.
+typedef enum
+{
+ DCL_I2C_OWNER_CAMERA=0,
+ DCL_I2C_OWNER_FM,
+ DCL_I2C_OWNER_TP,
+ DCL_I2C_OWNER_MS,
+ DCL_I2C_OWNER_AF,
+ DCL_I2C_OWNER_CAMERA_EEPROM,
+ DCL_I2C_OWNER_MUIC,
+ DCL_I2C_OWNER_MATV,
+ DCL_I2C_OWNER_PS,/*pressure sensor*/
+ DCL_I2C_OWNER_EP, /*EEPROM*/
+ DCL_I2C_OWNER_AMS, /*M-Sensor*/
+ DCL_I2C_OWNER_GS, /*G-Sensor*/
+ DCL_I2C_OWNER_MT6306, /*for MT6306*/
+ DCL_I2C_OWNER_AUDIO, /* for WM8904*/
+ DCL_I2C_NUM_OF_OWNER
+}DCL_I2C_OWNER;
+//#endif //defined(DRV_I2C_25_SERIES)
+
+#endif //__DCL_I2C_CUSTOM_OWNER_STRUCT__
diff --git a/mcu/interface/driver/peripheral/dcl_idc.h b/mcu/interface/driver/peripheral/dcl_idc.h
new file mode 100644
index 0000000..5ba9ad7
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_idc.h
@@ -0,0 +1,785 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2010
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_idc.h
+ *
+ * Project:
+ * --------
+ * MOLY_Software
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for IDC.
+ *
+ * Author:
+ * -------
+ *
+ * Ansel Liao
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
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+ *
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+ * removed!
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+ *
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+ * removed!
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+ * removed!
+ *
+ * removed!
+ * removed!
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+ * removed!
+ *
+ * removed!
+ * removed!
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+ * removed!
+ *
+ * removed!
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+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
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+ * removed!
+ *
+ * removed!
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+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_IDC_H_STRUCT__
+#define __DCL_IDC_H_STRUCT__
+
+#include "kal_general_types.h"
+
+#define MAX_NUM_BYTE 9
+#ifdef ATEST_DRV_ENABLE
+#define MAX_NUM_EVENT 16
+#else /*ATEST_DRV_ENABLE*/
+#define MAX_NUM_EVENT 1
+#endif
+
+
+#if defined(__MD93__)
+ typedef void (*IDC_DRV_TO_EL1_CALLBACK)(kal_bool data);
+#elif defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+ typedef void (*IDC_DRV_TO_EL1_CALLBACK)(void *data);
+#endif
+
+
+/*******************************************************************************
+ * DCL_OPTIONS for IDC
+ *******************************************************************************/
+#define IDC_OPTIONS
+
+
+/*******************************************************************************
+ * DCL_CONFIGURE_T for IDC
+ *******************************************************************************/
+#define IDC_CONFIGS
+
+
+/*******************************************************************************
+ * DCL_EVENT for IDC
+ *******************************************************************************/
+#define IDC_EVENTS
+
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for IDC
+ *******************************************************************************/
+/* The IDC Command Values in DCL_CTRL_CMD_T Enum of dcl.h */
+#ifdef __BUILD_DOM__
+typedef enum {
+ IDC_CMD_SET_DCB_CONFIG,
+ IDC_CMD_GET_DCB_CONFIG,
+ IDC_CMD_SET_BAUDRATE,
+ IDC_CMD_GET_MAX_BAUDRATE,
+ IDC_CMD_SET_FIFO_TRIGGER,
+ IDC_CMD_SET_PM_CONFIG,
+ IDC_CMD_GET_PM_CONFIG,
+ IDC_CMD_SEND_EVENT,
+ IDC_CMD_SCHEDULE_EVENT,
+ IDC_CMD_SCHEDULE_GPS_BLANK_EVENT,
+ IDC_CMD_SCHEDULE_GPS_L1_L5_BLANK_EVENT,
+ IDC_CMD_SCHEDULE_UPDATE,
+ IDC_CMD_PURGE,
+ IDC_CMD_CHECK_EVENT_SEND_OUT,
+ IDC_CMD_SET_PIN_CONFIG,
+ IDC_CMD_GET_PIN_CONFIG,
+ IDC_CMD_REGISTER_PM_CALLBACK,
+ IDC_CMD_UNREGISTER_PM_CALLBACK,
+ IDC_CMD_SET_NEW_PM_CONFIG,
+ IDC_CMD_GET_NEW_PM_CONFIG,
+ IDC_CMD_STOP_EVENT,
+ IDC_CMD_GET_SCHEDULE_STATUS,
+ IDC_CMD_GET_SCHEDULE_STATUS_2,
+ IDC_CMD_FORCE_ON_RF,
+ IDC_CMD_REMAPPING_CONFIG,
+ IDC_CMD_AUTO_TX_CONFIG,
+ IDC_CMD_AUTO_TX_EN,
+ IDC_CMD_SCHEDULE_UPDATE_N_RETRUN_RFTX,
+ IDC_CMD_SCHEDULE_EVENT_LTE_NR,
+ IDC_CMD_ENABLE_RAT,
+ IDC_CMD_DISABLE_RAT,
+ IDC_CMD_SLEEP_NOTIFY,
+ IDC_CMD_WAKE_NOTIFY,
+ IDC_CMD_SET_ILM,
+ IDC_CMD_GPS_B13_B14,
+} DCL_CTRL_CMD_T;
+#else // __BUILD_DOM__
+#define IDC_CMDS \
+ IDC_CMD_SET_DCB_CONFIG, \
+ IDC_CMD_GET_DCB_CONFIG, \
+ IDC_CMD_SET_BAUDRATE, \
+ IDC_CMD_GET_MAX_BAUDRATE, \
+ IDC_CMD_SET_FIFO_TRIGGER, \
+ IDC_CMD_SET_PM_CONFIG, \
+ IDC_CMD_GET_PM_CONFIG, \
+ IDC_CMD_SEND_EVENT, \
+ IDC_CMD_SCHEDULE_EVENT, \
+ IDC_CMD_SCHEDULE_GPS_BLANK_EVENT, \
+ IDC_CMD_SCHEDULE_GPS_L1_L5_BLANK_EVENT, \
+ IDC_CMD_SCHEDULE_UPDATE, \
+ IDC_CMD_PURGE, \
+ IDC_CMD_CHECK_EVENT_SEND_OUT, \
+ IDC_CMD_SET_PIN_CONFIG, \
+ IDC_CMD_GET_PIN_CONFIG, \
+ IDC_CMD_REGISTER_PM_CALLBACK, \
+ IDC_CMD_UNREGISTER_PM_CALLBACK, \
+ IDC_CMD_SET_NEW_PM_CONFIG, \
+ IDC_CMD_GET_NEW_PM_CONFIG, \
+ IDC_CMD_STOP_EVENT, \
+ IDC_CMD_GET_SCHEDULE_STATUS, \
+ IDC_CMD_GET_SCHEDULE_STATUS_2, \
+ IDC_CMD_FORCE_ON_RF, \
+ IDC_CMD_REMAPPING_CONFIG, \
+ IDC_CMD_AUTO_TX_CONFIG, \
+ IDC_CMD_AUTO_TX_EN, \
+ IDC_CMD_SCHEDULE_UPDATE_N_RETRUN_RFTX, \
+ IDC_CMD_SCHEDULE_EVENT_LTE_NR, \
+ IDC_CMD_ENABLE_RAT, \
+ IDC_CMD_DISABLE_RAT, \
+ IDC_CMD_SLEEP_NOTIFY, \
+ IDC_CMD_WAKE_NOTIFY, \
+ IDC_CMD_SET_ILM, \
+ IDC_CMD_GPS_B13_B14,
+#endif // __BUILD_DOM__
+
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+// For DclIDC_Initialize
+typedef enum
+{
+ IDC_INIT,
+ IDC_REINIT,
+ IDC_UART_ACTIVATE,
+} IDC_INIT_TYPE_T;
+
+// For IDC_CMD_SET_DCB_CONFIG command
+// For IDC_CMD_GET_DCB_CONFIG command
+typedef struct
+{
+ kal_uint32 u4Baud; // baudrate
+ kal_uint8 u1DataBits; // UART_BITS_PER_CHAR_T
+ kal_uint8 u1StopBits; // UART_STOP_BITS_T
+ kal_uint8 u1Parity; // UART_PARTIY_T
+} IDC_CTRL_DCB_CONFIG_T;
+
+// For IDC_CMD_SET_BAUDRATE command
+// For IDC_CMD_GET_MAX_BAUDRATE command
+typedef struct
+{
+ kal_uint32 baudrate; // baudrate
+} IDC_CTRL_BAUDRATE_T;
+
+// For IDC_CMD_SET_FIFO_TRIGGER command
+typedef struct
+{
+ kal_uint8 rx_threshold; // threshold of RX FIFO
+} IDC_CTRL_SET_FIFO_TRIGGER_T;
+
+// For IDC_CMD_SET_PM_CONFIG command
+// For IDC_CMD_GET_PM_CONFIG command
+typedef struct
+{
+ kal_uint8 pm_idx; // Pattern match index
+ kal_uint8 priority; // Priority
+ kal_uint8 priority_bit_en;// Priority bit enable
+ kal_uint8 pattern; // Pattern
+ kal_uint8 pattern_bit_en; // Pattern bit enable
+} IDC_CTRL_PM_CONFIG_T;
+
+// For IDC_CMD_SET_NEW_PM_CONFIG command
+// For IDC_CMD_GET_NEW_PM_CONFIG command
+typedef struct
+{
+ kal_uint8 pattern0; // Pattern 0
+ kal_uint8 pattern1; // Pattern 1
+} IDC_CTRL_NEW_PM_CONFIG_T;
+
+// For IDC_REGISTER_PM_CALLBACK command
+// For IDC_UNREGISTER_PM_CALLBACK command
+typedef struct
+{
+ kal_uint8 pm_idx; // Pattern match index , 0~3 : old PM, 4: new PM
+ IDC_DRV_TO_EL1_CALLBACK func_ptr; // Callback function
+#if defined(__MD93__)
+ kal_bool private_data;// Private data
+#elif defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+ void *private_data;// old PM -> kal_bool, new PM -> kal_uint16
+#endif
+} IDC_CTRL_PM_CALLBACK_T;
+
+
+// For IDC_CMD_SCHEDULE_EVENT command
+typedef struct
+{
+#if defined(__MD93__)
+ kal_uint8 data[2];
+#elif defined(__MD95__) || defined(__MD97__) || defined(__MD97P__)
+ kal_uint8 num; // number of byte in the event
+ kal_uint8 data[MAX_NUM_BYTE]; // 2~9 byte data per event
+#endif
+ kal_uint32 offset; // 97: 1000 = 1 ms, can be set up to 10000 (= 10 ms) *** 95: 61440 = 1 ms, can be set up to 614400 (= 10 ms)
+} IDC_EVENT_T;
+
+typedef struct
+{
+ kal_uint8 cmd_type;
+ kal_uint8 cmd_sub_type;
+ kal_uint32 cmd_phytime;
+ kal_uint8 event_type;
+} IDC_CTRL_DROP_CMD_T;
+
+typedef struct
+{
+ IDC_EVENT_T schedule_event; // event columns
+ kal_bool sleep_mode; // Use KAL_TRUE to lock resource
+ kal_bool gps_mode; // Use KAL_TRUE to notify gps to blank
+ IDC_CTRL_DROP_CMD_T *drop_cmd; // drop_cmd structure for DRV_IDC fill in if drop behavior occurs
+} IDC_CTRL_SCHEDULE_EVENT_T;
+
+typedef struct
+{
+ kal_uint8 rat_status; // rat_lte = 0, rat_nr = 1
+ kal_uint8 raw_data; // L1: bit[0], L5:bit[1], if value = 0x0 : gps_off, value = 0x1 : gps_on
+ kal_uint32 frc_time; //1000 = 1 ms, can be set up to 10000 (= 10 ms)
+} IDC_CTRL_GPS_L1_L5_BLANK_EVENT_T;
+
+typedef struct
+{
+ kal_uint8 rat_status; // rat_lte = 0, rat_nr = 1
+ kal_bool gps_mode; // Using KAL_TRUE to ON GPS blank,KAL_FALSE to OFF GPS blank
+ kal_uint32 frc_time; //1000 = 1 ms, can be set up to 10000 (= 10 ms)
+} IDC_CTRL_GPS_SINGLE_BLANK_EVENT_T;
+
+
+// For IDC_CMD_SCHEDULE_UPDATE command
+typedef struct
+{
+ kal_uint32 phy_time_set; // According to sub frame boundary, range = 0 ~ 61440*n (n: last sub frame boundary, 61440 = 1ms)
+} IDC_CTRL_SCHEDULE_UPDATE_T;
+
+// For IDC_CMD_STOP_EVENT command
+typedef struct
+{
+ kal_uint32 bitmap; // events need to be stopped
+} IDC_CTRL_STOP_EVENT_T;
+
+// For IDC_CMD_PURGE
+typedef struct
+{
+ UART_buffer dir;
+} IDC_CTRL_PURGE_T;
+
+// For IDC_CMD_GET_SCHEDULE_STATUS
+typedef struct
+{
+ kal_uint32 schedule_status; // (bitmap)
+} IDC_CTRL_GET_SCHEDULE_STATUS_T;
+
+// For IDC_CMD_CHECK_EVENT_SEND_OUT
+typedef struct
+{
+ kal_bool send_out; // all events are sent out
+} IDC_CTRL_CHECK_EVENT_SEND_OUT_T;
+
+// For IDC_CMD_SET_PIN_CONFIG
+typedef enum
+{
+ IDC_INTERNAL_PIN,
+ IDC_EXTERNAL_PIN,
+} IDC_PIN_MODE_T;
+
+typedef struct
+{
+ IDC_PIN_MODE_T pin_mode;
+} IDC_CTRL_PIN_CONFIG_T;
+
+typedef struct
+{
+ kal_uint8 rf_path; // 0: rf path 0, 1: rf path 1
+} IDC_CTRL_RF_PATH_T;
+
+typedef struct
+{
+ kal_uint8 remapping_table; // remapping table config
+ kal_uint8 remapping_table_en; // remapping table enable
+} IDC_CTRL_REMAPPING_CONFIG_T;
+
+typedef struct
+{
+ kal_uint8 tx_susp_quota; // it count down when receive REVOKE IDC_CMD, usually set 30ms, 1ms per unit
+ kal_uint8 reset_quota; // it count down when start auto tx system, usually set 200ms, 1ms per unit
+} IDC_AUTO_TX_CONFIG_T;
+
+typedef struct
+{
+ kal_bool auto_tx_en; // KAL_TRUE : auto tx on, KAL_FALSE : auto tx off
+} IDC_AUTO_TX_EN_T;
+
+// For IDC_CMD_SCHEDULE_UPDATE_N_RETRUN_RFTX command
+typedef struct
+{
+ kal_uint8 rat_status; // rat_lte = 0, rat_nr = 1
+
+} IDC_RAT_T;
+typedef struct
+{
+ kal_bool ilm_mode; // 0 : ILM_DISABLE, 1 : ILM_ENABLE
+
+} IDC_ILM_T;
+typedef struct
+{
+ kal_uint8 rat_status; // rat_lte = 0, rat_nr = 1
+ kal_uint16 raw_data; // rat_lte: bit[0:1], rat_nr:bit[2]
+} IDC_GPS_B13_B14_T;
+
+typedef struct
+{
+ kal_uint32 frc_time_set; // According to sub frame boundary, range = 0 ~ 1000*n (n: last sub frame boundary, 1000 = 1ms)
+ kal_uint8 rf_path_status; // returns RF status to MD_IDC
+
+} IDC_CTRL_SCHEDULE_UPDATE_N_RETRUN_RFTX_T;
+
+typedef struct
+{
+ IDC_EVENT_T schedule_event; // event columns
+ kal_bool sleep_mode; // Use KAL_TRUE to lock resource
+ kal_uint8 event_type; // LTE/NR/Common
+ IDC_CTRL_DROP_CMD_T *drop_cmd; // drop_cmd structure for DRV_IDC fill in if drop behavior occurs
+} IDC_CTRL_SCHEDULE_EVENT_LTE_NR_T;
+
+/* The IDC Command Parameter Data Structure for Each Command in DCL_CTRL_DATA_T Enum of dcl.h */
+#ifdef __BUILD_DOM__
+typedef union
+{
+ IDC_CTRL_DCB_CONFIG_T r_idc_ctrl_dcb_config; // Data Structure for IDC_CMD_SET_DCB_CONFIG, IDC_CMD_GET_DCB_CONFIG
+ IDC_CTRL_BAUDRATE_T r_idc_ctrl_baudrate; // Data Structure for IDC_CMD_SET_BAUDRATE, IDC_CMD_GET_MAX_BAUDRATE
+ IDC_CTRL_SET_FIFO_TRIGGER_T r_idc_ctrl_set_fifo_trigger; // Data Structure for IDC_CMD_SET_FIFO_TRIGGER
+ IDC_CTRL_PM_CONFIG_T r_idc_ctrl_pm_config; // Data Structure for IDC_CMD_SET_PM_CONFIG, IDC_CMD_GET_PM_CONFIG
+ IDC_CTRL_NEW_PM_CONFIG_T r_idc_ctrl_new_pm_config; // Data Structure for IDC_CMD_SET_NEW_PM_CONFIG, IDC_CMD_GET_NEW_PM_CONFIG
+ IDC_CTRL_SCHEDULE_EVENT_T r_idc_ctrl_schedule_event; // Data Structure for IDC_CMD_SCHEDULE_EVENT
+ IDC_CTRL_GPS_SINGLE_BLANK_EVENT_T r_idc_ctrl_gps_single_blank_event; // Data Structure for IDC_CMD_GPS_SINGLE_BLANK_EVENT
+ IDC_CTRL_GPS_L1_L5_BLANK_EVENT_T r_idc_ctrl_gps_l1_l5_blank_event; // Data Structure for IDC_CMD_GPS_L1_L5_BLANK_EVENT
+ IDC_CTRL_SCHEDULE_UPDATE_T r_idc_ctrl_schedule_start; // Data Structure for IDC_CMD_SCHEDULE_EVENT
+ IDC_CTRL_STOP_EVENT_T r_idc_ctrl_stop_event; // Data Structure for IDC_CMD_STOP_EVENT
+ IDC_CTRL_PURGE_T r_idc_ctrl_purge; // Data Structure for IDC_CMD_PURGE
+ IDC_CTRL_GET_SCHEDULE_STATUS_T r_idc_ctrl_get_schedule_status; // Data Structure for IDC_CMD_GET_SCHEDULE_STATUS
+ IDC_CTRL_CHECK_EVENT_SEND_OUT_T r_idc_ctrl_check_event_send_out; // Data Structure for IDC_CMD_CHECK_EVENT_SEND_OUT
+ IDC_CTRL_PIN_CONFIG_T r_idc_ctrl_pin_config; // Data Structure for IDC_CTRL_PIN_CONFIG_T
+ IDC_CTRL_PM_CALLBACK_T r_idc_ctrl_pm_callback;
+ IDC_CTRL_RF_PATH_T r_idc_ctrl_rf_path;
+ IDC_CTRL_REMAPPING_CONFIG_T r_idc_ctrl_remapping_config;
+ IDC_AUTO_TX_CONFIG_T r_idc_ctrl_auto_tx_config;
+ IDC_AUTO_TX_EN_T r_idc_ctrl_auto_tx_en;
+ IDC_CTRL_SCHEDULE_UPDATE_N_RETRUN_RFTX_T r_idc_ctrl_schedule_update_n_return_rftx;
+ IDC_CTRL_SCHEDULE_EVENT_LTE_NR_T r_idc_ctrl_schedule_event_lte_nr;
+ IDC_RAT_T r_idc_ctrl_rat_status;
+ IDC_ILM_T r_idc_ctrl_ilm_mode;
+ IDC_GPS_B13_B14_T r_idc_ctrl_gps_b13_b14_mode;
+} DCL_CTRL_DATA_T;
+#else /* __BUILD_DOM__ */
+#define IDC_CTRLS \
+ IDC_CTRL_DCB_CONFIG_T r_idc_ctrl_dcb_config; \
+ IDC_CTRL_BAUDRATE_T r_idc_ctrl_baudrate; \
+ IDC_CTRL_SET_FIFO_TRIGGER_T r_idc_ctrl_set_fifo_trigger; \
+ IDC_CTRL_PM_CONFIG_T r_idc_ctrl_pm_config; \
+ IDC_CTRL_SCHEDULE_EVENT_T r_idc_ctrl_schedule_event; \
+ IDC_CTRL_GPS_SINGLE_BLANK_EVENT_T r_idc_ctrl_gps_single_blank_event; \
+ IDC_CTRL_GPS_L1_L5_BLANK_EVENT_T r_idc_ctrl_gps_l1_l5_blank_event; \
+ IDC_CTRL_SCHEDULE_UPDATE_T r_idc_ctrl_schedule_start; \
+ IDC_CTRL_STOP_EVENT_T r_idc_ctrl_stop_event; \
+ IDC_CTRL_PURGE_T r_idc_ctrl_purge; \
+ IDC_CTRL_GET_SCHEDULE_STATUS_T r_idc_ctrl_get_schedule_status; \
+ IDC_CTRL_CHECK_EVENT_SEND_OUT_T r_idc_ctrl_check_event_send_out; \
+ IDC_CTRL_PIN_CONFIG_T r_idc_ctrl_pin_config; \
+ IDC_CTRL_PM_CALLBACK_T r_idc_ctrl_pm_callback; \
+ IDC_CTRL_NEW_PM_CONFIG_T r_idc_ctrl_new_pm_config; \
+ IDC_CTRL_RF_PATH_T r_idc_ctrl_rf_path; \
+ IDC_CTRL_REMAPPING_CONFIG_T r_idc_ctrl_remapping_config; \
+ IDC_AUTO_TX_CONFIG_T r_idc_ctrl_auto_tx_config; \
+ IDC_AUTO_TX_EN_T r_idc_ctrl_auto_tx_en; \
+ IDC_CTRL_SCHEDULE_UPDATE_N_RETRUN_RFTX_T r_idc_ctrl_schedule_update_n_return_rftx; \
+ IDC_CTRL_SCHEDULE_EVENT_LTE_NR_T r_idc_ctrl_schedule_event_lte_nr; \
+ IDC_RAT_T r_idc_ctrl_rat_status; \
+ IDC_ILM_T r_idc_ctrl_ilm_mode; \
+ IDC_GPS_B13_B14_T r_idc_ctrl_gps_b13_b14_mode;
+#endif /* __BUILD_DOM__ */
+
+// Support list of IDC driver
+typedef struct
+{
+ kal_bool idc;
+ kal_bool gpio;
+ kal_bool uart;
+} IDC_SUPPORT_T;
+
+#endif // #ifndef __DCL_IDC_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_IDC_H_PROTOTYPE__
+#define __DCL_IDC_H_PROTOTYPE__
+
+/*************************************************************************
+* FUNCTION
+* DclIDC_GetSupport
+*
+* DESCRIPTION
+* This function is to get the support list of IDC driver.
+*
+* PARAMETERS
+* support: [IN] IDC_SUPPORT_T *support
+* 1. idc: Indicate whether or not idc driver is supported
+* 2. gpio: Indicate whether or not GPIO Co-Exist will be used after idc_init
+* 3. uart: Indicate whether or not UART will be used after idc_init
+*
+* RETURNS
+* Return the support list
+*
+* RETURN VALUES
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclIDC_GetSupport(IDC_SUPPORT_T *support);
+
+/*************************************************************************
+* FUNCTION
+* DclIDC_Initialize
+*
+* DESCRIPTION
+* This function is to initialize IDC module
+*
+* RETURNS
+* Return the status of DclIDC_Initialize
+*
+* RETURN VALUES
+* STATUS_OK: Initialize Finished
+*
+*************************************************************************/
+extern DCL_STATUS DclIDC_Initialize(IDC_INIT_TYPE_T type);
+
+
+/*************************************************************************
+* FUNCTION
+* DclIDC_Open
+*
+* DESCRIPTION
+* This function is to open the IDC module and return a handle
+*
+* PARAMETERS
+* dev: [IN] Only valid for DCL_IDC
+* flags: [IN] No sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* Return DCL_HANDLE of IDC
+*
+* RETURN VALUES
+* DCL_HANDLE_INVALID : Open failed
+* Other value : A valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclIDC_Open(DCL_DEV dev, DCL_FLAGS flags);
+
+
+/*************************************************************************
+* FUNCTION
+* DclIDC_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the IDC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclIDC_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+
+
+/*************************************************************************
+* FUNCTION
+* DclIDC_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the IDC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclIDC_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+
+
+/*************************************************************************
+* FUNCTION
+* DclIDC_Configure
+*
+* DESCRIPTION
+* This function is not supported for the IDC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclIDC_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+
+
+/*************************************************************************
+* FUNCTION
+* DclIDC_RegisterCallback
+*
+* DESCRIPTION
+* This function is not supported for the IDC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclIDC_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+
+
+/*************************************************************************
+* FUNCTION
+* DclIDC_Control
+*
+* DESCRIPTION
+* This function is to send command to control the IDC module.
+*
+* PARAMETERS
+* handle: [IN] The handle value returned from DclIDC_Open
+* cmd: [IN] A control command for IDC module
+* 1. IDC_CMD_SET_DCB_CONFIG: to config DCB (baudrate, data bits, stop bits, and parity bits)
+* 2. IDC_CMD_GET_DCB_CONFIG: to get DCB config from driver
+* 3. IDC_CMD_SET_BAUDRATE: to set baud rate
+* 4. IDC_CMD_GET_MAX_BAUDRATE: to get max baudrate
+* 5. IDC_CMD_SET_FIFO_TRIGGER: to set threshold of idc rx fifo
+* 6. IDC_CMD_SET_PM_CONFIG: to set pattern matching confg (start/finish priority/pattern, pariority/pattern bit enable)
+* 7. IDC_CMD_GET_PM_CONFIG: to get pattern matching
+* 8. IDC_CMD_SCHEDULE_EVENT: to schedule events
+* 9. IDC_CMD_SCHEDULE_UPDATE: to run schedule
+* 10. IDC_CMD_STOP_EVENT: to stop specific event from specific schedule
+* 11. IDC_CMD_PURGE: to clean IDC RX FIFO
+* 12. IDC_CMD_GET_SCHEDULE_STATUS: to get status of schedule (bitmap, busy:1, idle:0)
+* 13. IDC_CMD_CHECK_EVENT_SEND_OUT: to check all events are sent out from IDC or not
+* 14. IDC_CMD_SET_PIN_CONFIG: to set pinmux beteen internal and external pins (K2 Only)
+* 15. IDC_CMD_GET_PIN_CONFIG: to get pinumx config (K2 Only)
+*
+* data: [IN] The data of the control command
+* 1. IDC_CTRL_DCB_CONFIG_T: pointer to an IDC_CTRL_DCB_CONFIG_T structure
+* 2. IDC_CTRL_BAUDRATE_T: pointer to an IDC_CTRL_BAUDRATE_T structure
+* 3. IDC_CTRL_SET_FIFO_TRIGGER_T: pointer to an IDC_CTRL_SET_FIFO_TRIGGER_T structure
+* 4. IDC_CTRL_PM_CONFIG_T: pointer to an IDC_CTRL_PM_CONFIG_T structure
+* 5. IDC_CTRL_SCHEDULE_EVENT_T: pointer to an IDC_CTRL_SCHEDULE_EVENT_T structure
+* 6. IDC_CTRL_SCHEDULE_UPDATE_T: pointer to an IDC_CTRL_SCHEDULE_UPDATE_T structure
+* 7. IDC_CTRL_STOP_EVENT_T: pointer to an IDC_CTRL_STOP_EVENT_T structure
+* 8. IDC_CTRL_PURGE_T: pointer to an IDC_CTRL_PURGE structure
+* 9. IDC_CTRL_GET_SCHEDULE_STATUS_T: pointer to an IDC_CTRL_GET_SCHEDULE_STATUS_T structure
+* 10. IDC_CTRL_CHECK_EVENT_SEND_OUT_T: pointer to an IDC_CTRL_CHECK_EVENT_SEND_OUT_T structure
+* 11. IDC_CTRL_PIN_CONFIG_T: pointer to an IDC_CTRL_PIN_CONFIG_T structure
+*
+* RETURNS
+* Return the status of DclIDC_Control
+*
+* RETURN VALUES
+* STATUS_OK: Command is executed successfully.
+* STATUS_FAIL: Command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+*
+*************************************************************************/
+extern DCL_STATUS DclIDC_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+
+/*************************************************************************
+* FUNCTION
+* DclIDC_conn_txrx_count
+*
+* DESCRIPTION
+* This function is to start/end counting BT_80211_RX and BT_80211_TX
+*
+* PARAMETERS
+* is_start: [IN] KAL_TRUE: Start counting
+* KAL_FALSE: End counting
+*
+* RETURNS
+* Return the status of DclIDC_conn_txrx_count
+*
+* RETURN VALUES
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclIDC_conn_txrx_count(kal_bool is_start);
+
+/*************************************************************************
+* FUNCTION
+* DclIDC_Close
+*
+* DESCRIPTION
+* This function is to close the IDC module.
+*
+* PARAMETERS
+* handle: [IN] The returned handle value of DclIDC_Open
+*
+* RETURNS
+* Return the status of DclIDC_Close
+*
+* RETURN VALUES
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclIDC_Close(DCL_HANDLE handle);
+
+// MoDIS parser skip end
+
+#endif // #ifndef __DCL_IDC_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
diff --git a/mcu/interface/driver/peripheral/dcl_irda.h b/mcu/interface/driver/peripheral/dcl_irda.h
new file mode 100644
index 0000000..8e845e9
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_irda.h
@@ -0,0 +1,261 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_irda.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for IrDA.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_IRDA_H_STRUCT__
+#define __DCL_IRDA_H_STRUCT__
+/*******************************************************************************
+ * DCL_OPTIONS for IRDA
+ *******************************************************************************/
+#define IRDA_OPTIONS
+
+/*******************************************************************************
+ * DCL_CONFIGURE_T
+ *******************************************************************************/
+typedef struct
+{
+ DCL_BOOL fgModulation1p63;
+ DCL_BOOL fgBOFType0xff;
+ DCL_UINT8 uMirDoubleStaNum;
+#define DCL_MIR_DOUBLE_STA_DEFAULT 0x7f
+#define DCL_MIR_DOUBLE_STA_MAX 0x7f
+} IRDA_CONFIG_T;
+
+#define IRDA_CONFIGS \
+ IRDA_CONFIG_T rIRDACofig;
+
+
+/*******************************************************************************
+ * DCL_EVENT for IRDA
+ *******************************************************************************/
+#define IRDA_EVENTS
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for IRDA
+ *******************************************************************************/
+#define IRDA_CMDS
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+#define IRDA_CTRLS
+
+#endif // #ifndef __DCL_IRDA_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+#if defined(DCL_DEFINITION_PROTOTYPE)
+#ifndef __DCL_IRDA_H_PROTOTYPE__
+#define __DCL_IRDA_H_PROTOTYPE__
+// MoDIS parser skip start
+/*************************************************************************
+* FUNCTION
+* DclIRDA_Initialize
+*
+* DESCRIPTION
+* This function is to initialize IRDA module.
+*
+* PARAMETERS
+* DCL_STATUS_OK
+* STATUS_UNSUPPORTED - IrDA is not supported or enabled.
+*
+* RETURNS
+* none
+*
+*************************************************************************/
+extern DCL_STATUS DclIRDA_Initialize(void);
+
+/*************************************************************************
+* FUNCTION
+* DclIRDA_Open
+*
+* DESCRIPTION
+* This function is to open the IRDA module and get a handle. Note that
+* multiple opens are not allowed.
+*
+* PARAMETERS
+* eDev - only valid for DCL_IRDA
+* flags - no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* DCL_HANDLE_INVALID - Open failed.
+* STATUS_UNSUPPORTED - IrDA is not supported or enabled.
+* other value - a valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclIRDA_Open(DCL_DEV eDev, DCL_FLAGS flags);
+
+/*************************************************************************
+* FUNCTION
+* DclIRDA_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the IRDA module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclIRDA_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+
+/*************************************************************************
+* FUNCTION
+* DclIRDA_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the IRDA module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclIRDA_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+
+/*************************************************************************
+* FUNCTION
+* DclIRDA_Configure
+*
+* DESCRIPTION
+* This function is to configure for the IRDA module.
+*
+* PARAMETERS
+* handle - a valid handle return by DclIRDA_Open()
+* configure - a ponter to IRDAT_CONFIG_T structure which is a member of union
+* DCL_CONFIGURE_T.
+*
+* RETURNS
+* STATUS_OK - successfully set the configuratuib.
+* STATUS_INVALID_HANDLE - It's a invalid handle.
+* STATUS_UNSUPPORTED - IrDA is not supported or enabled.
+*
+*************************************************************************/
+extern DCL_STATUS DclIRDA_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+
+/*************************************************************************
+* FUNCTION
+* DclIRDA_RegisterCallback
+*
+* DESCRIPTION
+* This function is not supported for the IRDA module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclIRDA_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+
+/*************************************************************************
+* FUNCTION
+* DclIRDA_Control
+*
+* DESCRIPTION
+* This function is not supported for the IRDA module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclIRDA_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+
+/*************************************************************************
+* FUNCTION
+* DclIRDA_Close
+*
+* DESCRIPTION
+* This function is to close the IRDA module.
+*
+* PARAMETERS
+* handle - hanlde previous got from DclIRDA_Open()
+*
+* RETURNS
+* DCL_STATUS_OK - successfully close the IRDA module.
+* STATUS_NOT_OPENED - IrDA hasn't been opened yet.
+* STATUS_INVALID_HANDLE - It's a invalid handle.
+* STATUS_UNSUPPORTED - IrDA is not supported or enabled.
+*
+*************************************************************************/
+extern DCL_STATUS DclIRDA_Close(DCL_HANDLE handle);
+
+// MoDIS parser skip end
+
+#endif // #ifndef __DCL_IRDA_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
+
+
diff --git a/mcu/interface/driver/peripheral/dcl_msdc.h b/mcu/interface/driver/peripheral/dcl_msdc.h
new file mode 100644
index 0000000..e3fb488
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_msdc.h
@@ -0,0 +1,690 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_msdc.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file defines common part of msdc related modules.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_MSDC_H_FRONT__
+#define __DCL_MSDC_H_FRONT__
+
+//RHR ADD
+#include "kal_general_types.h"
+//RHR REMOVE
+/*
+//MSBB remove #include "kal_non_specific_general_types.h"
+*/
+//RHR
+
+#define DCL_MSDC_HW_MSDC1 1
+#define DCL_MSDC_HW_MSDC2 2
+
+/*********************************************************************************************************
+*followings we defines the structure used by DCL user, this is prevent DCL user from include invividual moudles' header file.
+**********************************************************************************************************/
+typedef DCL_UINT32 DCL_SDC_CMD_STATUS;//this is to replace SDC_CMD_STATUS
+
+
+/*this is to replace cmd53_op_enum*/
+typedef enum{
+ DCL_SDIO_FIX, //multi byte r/w at fixed address
+ DCL_SDIO_INC //multi byte r/w at incrementing address
+}DCL_SDIO_cmd53_op_enum;
+
+/*this is to replace SDIO_function_id_enum*/
+typedef enum{
+ DCL_SDIO_FUCN_0=0,
+ DCL_SDIO_FUCN_1,
+ DCL_SDIO_MAX_FUCN_ID,
+ DCL_SDIO_FUCN_MEM=0x1000
+}DCL_SDIO_function_id_enum;
+
+/*this is to replace SD_BITWIDTH*/
+typedef enum{
+ DCL_BIT_1W = 0x0000,
+ DCL_BIT_4W = 0x0002
+}DCL_SD_BITWIDTH;
+
+typedef void ( *MSDC_CALLBACK) (void);
+#define DCL_SECTOR_SIZE 512
+
+/*******************************************************************************
+ * driver function tables exposed to DCL, in SD layer, SDIO layer, and MSDC layer
+ *******************************************************************************/
+/*here are type definition for functions*/
+typedef DCL_SDC_CMD_STATUS (*DCL_SINGLE_BLK_RD) (DCL_UINT32 data_adrs, DCL_UINT32 *rxbuffer);
+typedef DCL_SDC_CMD_STATUS (*DCL_MUL_BLK_RD) (DCL_UINT32 data_adrs, DCL_UINT32 *rxbuffer, DCL_UINT32 num);
+typedef DCL_SDC_CMD_STATUS (*DCL_SINGLE_BLK_WR) (DCL_UINT32 address, DCL_UINT32 *txbuffer);
+typedef DCL_SDC_CMD_STATUS (*DCL_MUL_BLK_WR) (DCL_UINT32 address, DCL_UINT32 *txbuffer, DCL_UINT32 num);
+typedef DCL_SDC_CMD_STATUS (*DCL_SD_INITITALIZE) (void);
+typedef DCL_SDC_CMD_STATUS (*DCL_SET_PRE_ERASE_CNT) (DCL_UINT32 num);
+typedef DCL_SDC_CMD_STATUS (*DCL_SD_SET_CALLBACK)(MSDC_CALLBACK callback1, MSDC_CALLBACK callback2, MSDC_CALLBACK callback3,MSDC_CALLBACK callback4,MSDC_CALLBACK callback5,MSDC_CALLBACK callback6);
+typedef DCL_SDC_CMD_STATUS (*DCL_SET_READ_TEST_FLAG)(kal_uint32 readTestFlag);
+typedef DCL_SDC_CMD_STATUS(*DCL_SD_READ_TEST)(void);
+typedef DCL_SDC_CMD_STATUS(*DCL_SD_SET_UPLL_CLOCK_TEST)(void);
+typedef DCL_SDC_CMD_STATUS(*DCL_SD_ERASE_BLK)(DCL_UINT32 startSector, DCL_UINT32 sectorNum);
+typedef DCL_SDC_CMD_STATUS (*DCL_GPD_MUL_BLK_RD) (DCL_UINT32 data_addrs,DCL_UINT32 num, void *data_buf);
+typedef DCL_SDC_CMD_STATUS (*DCL_GPD_MUL_BLK_WR) (DCL_UINT32 data_addrs,DCL_UINT32 num, void *data_buf);
+
+
+typedef struct
+{
+ DCL_SINGLE_BLK_RD singleBlkRd;
+ DCL_MUL_BLK_RD mulBlkRd;
+ DCL_SINGLE_BLK_WR singleBlkWr;
+ DCL_MUL_BLK_WR mulBlkWr;
+ DCL_SD_INITITALIZE sdInititalize;
+ DCL_SET_PRE_ERASE_CNT setPreEraseCnt;
+ DCL_SD_SET_CALLBACK sdSetCallBack;
+ DCL_SET_READ_TEST_FLAG sdSetReadTestFlag;
+ DCL_SD_READ_TEST sdSetReadTest;
+ DCL_SD_SET_UPLL_CLOCK_TEST sdSetUpllClock;
+ DCL_SD_ERASE_BLK eraseBlk;
+ DCL_GPD_MUL_BLK_RD GpdMulBlkRd;
+ DCL_GPD_MUL_BLK_WR GpdMulBlkWr;
+}SDDriver_t;
+
+
+typedef DCL_BOOL (*DCL_SDIO_REG_WR) (DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT32 data, DCL_SDIO_cmd53_op_enum op);
+typedef DCL_BOOL (*DCL_SDIO_REG_WR_ISR) (DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT32 data, DCL_SDIO_cmd53_op_enum op);
+typedef DCL_BOOL (*DCL_SDIO_DATA_WR) (DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT8 *data, DCL_SDIO_cmd53_op_enum op, DCL_UINT32 count, DCL_BOOL block);
+typedef DCL_BOOL (*DCL_SDIO_REG_RD) (DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT32 *data, DCL_SDIO_cmd53_op_enum op);
+typedef DCL_BOOL (*DCL_SDIO_DATA_RD) (DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT8 *data, DCL_SDIO_cmd53_op_enum op, DCL_UINT32 count, DCL_BOOL block);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CHECK_INTR) (DCL_SDIO_function_id_enum function, DCL_BOOL *pending);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_ENABLE_INTR) (DCL_SDIO_function_id_enum function, DCL_BOOL enable);
+typedef DCL_UINT32 (*DCL_SDIO_INIT) (void);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_ABORT) (DCL_SDIO_function_id_enum function);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_SW_RST) (void);
+typedef DCL_UINT32 (*DCL_SDIO_QRY_BLOCK_SIZE) (DCL_SDIO_function_id_enum function);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_SET_BLOCK_SIZE) (DCL_SDIO_function_id_enum function, DCL_UINT32 size);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_GET_BLOCK_SIZE) (DCL_SDIO_function_id_enum function, DCL_UINT32 *size);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_ENABLE_IO) (DCL_SDIO_function_id_enum function, DCL_BOOL enable);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_SET_BUS_WIDTH) (DCL_SD_BITWIDTH bus);
+typedef void (*DCL_SDIO_GET_CCCR) (DCL_UINT8 *buf, DCL_UINT32 bufLen);
+typedef void (*DCL_SDIO_GET_FBR) (DCL_UINT8 *buf, DCL_UINT32 bufLen);
+
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CMD52_READ)(DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT8 *rdata, DCL_UINT8 *r5resp);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CMD52_WRITE)(DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT8 wdata, DCL_UINT8 *r5resp);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CMD52_WRITE_READ)(DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT8 wdata, DCL_UINT8 *rdata, DCL_UINT8 *r5resp);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CMD53_READ)(DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT32 data, DCL_SDIO_cmd53_op_enum op, DCL_UINT32 count, DCL_BOOL block, DCL_UINT8 *r5resp);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CMD53_WRITE)(DCL_SDIO_function_id_enum function, DCL_UINT32 addr, DCL_UINT32 data, DCL_SDIO_cmd53_op_enum op, DCL_UINT32 count, DCL_BOOL block, DCL_UINT8 *r5resp);
+typedef void (*DCL_SDIO_int_registration)(DCL_SDIO_function_id_enum function, void (func)(void));
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_MCUDMA_READ)(DCL_UINT32 *rdata);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_MCUDMA_WRITE)(DCL_UINT32 wdata);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CLKPADRED_READ)(DCL_UINT32 *rdata);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_CLKPADRED_WRITE)(DCL_UINT32 wdata);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_FORCEMCU_READ)(DCL_UINT32 *rdata);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_FORCEMCU_WRITE)(DCL_UINT32 wdata);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_GETCLK)(DCL_UINT32 *rdata);
+typedef DCL_SDC_CMD_STATUS (*DCL_SDIO_SETCLK)(DCL_UINT32 wdata);
+
+//guilin
+
+typedef struct
+{
+ DCL_SDIO_REG_WR regWr;
+ DCL_SDIO_REG_WR_ISR regWrInIsr;
+ DCL_SDIO_DATA_WR dataWr;
+ DCL_SDIO_REG_RD regRd;
+ DCL_SDIO_DATA_RD dataRd;
+ DCL_SDIO_CHECK_INTR checkIntr;
+ DCL_SDIO_ENABLE_INTR enableIntr;
+ DCL_SDIO_INIT sdioInititalize;
+ DCL_SDIO_ABORT abort;
+ DCL_SDIO_SW_RST swRst;
+ DCL_SDIO_QRY_BLOCK_SIZE qryBlkSize;
+ DCL_SDIO_SET_BLOCK_SIZE setBlkSize;
+ DCL_SDIO_GET_BLOCK_SIZE getBlkSize;
+ DCL_SDIO_ENABLE_IO enableIO;
+ DCL_SDIO_SET_BUS_WIDTH setBusWidth;
+ DCL_SDIO_GET_CCCR getCCCR;
+ DCL_SDIO_GET_FBR getFBR;
+
+ DCL_SDIO_CMD52_READ cmd52_read;
+ DCL_SDIO_CMD52_WRITE cmd52_write;
+ DCL_SDIO_CMD52_WRITE_READ cmd52_write_read;
+ DCL_SDIO_CMD53_READ cmd53_read;
+ DCL_SDIO_CMD53_WRITE cmd53_write;
+ DCL_SDIO_int_registration hisr_callback;
+ DCL_SDIO_MCUDMA_READ mcudma_read;
+ DCL_SDIO_MCUDMA_WRITE mcudma_write;
+ DCL_SDIO_CLKPADRED_READ clkpadred_read;
+ DCL_SDIO_CLKPADRED_WRITE clkpadred_write;
+ DCL_SDIO_FORCEMCU_READ forcemcu_read;
+ DCL_SDIO_FORCEMCU_WRITE forcemcu_write;
+ DCL_SDIO_GETCLK getclk;
+ DCL_SDIO_SETCLK setclk;
+
+}SDIODriver_t;
+//guilin
+typedef void (* DCL_MSDC_PDN)(DCL_BOOLEAN pwDown);
+
+typedef struct
+{
+ //void (*modulePDN) (DCL_BOOLEAN pwDown);
+ DCL_MSDC_PDN modulePDN;
+}MSDCDriver_t;
+
+
+/*******************************************************************************
+ * DCL_FLAGS_T for SD
+ *******************************************************************************/
+#define DCL_SD_FLAGS_DEVICE_CARD1 0x1
+#define DCL_SD_FLAGS_DEVICE_CARD2 0x2
+#define DCL_SD_FLAGS_DEVICE_SIMPLUS 0x4
+#define DCL_SDIO_FLAGS_SDIO1 0x100
+#define DCL_SDIO_FLAGS_SDIO2 0x200
+#define DCL_SDIO_FLAGS_ALL 0x300
+#define DCL_SD_FLAGS_USAGE_GET_INFORMATION 0x10000
+#define DCL_SD_FLAGS_USAGE_CMD 0x20000
+
+#define DCL_SD_FLAGS_DEVICE_ALL (DCL_SD_FLAGS_DEVICE_CARD1|DCL_SD_FLAGS_DEVICE_CARD2|DCL_SD_FLAGS_DEVICE_SIMPLUS)
+#define DCL_SD_FLAGS_USAGE_ALL (DCL_SD_FLAGS_USAGE_GET_INFORMATION|DCL_SD_FLAGS_USAGE_CMD)
+/*******************************************************************************
+ * DCL_CTRL_CMD for SD
+ *******************************************************************************/
+#define SD_CMDS \
+ SD_CTRL_CMD_BASE, \
+ SD_CTRL_CMD_READ = SD_CTRL_CMD_BASE, \
+ SD_CTRL_CMD_WRITE, \
+ SD_CTRL_CMD_READ_ODD_SIZE, \
+ SD_CTRL_CMD_WRITE_ODD_SIZE, \
+ SD_CTRL_CMD_INIT, \
+ SD_CTRL_CMD_IS_INITED, \
+ SD_CTRL_CMD_ANALOG_SWITCH, \
+ SD_CTRL_CMD_FAST_FORMAT_START, \
+ SD_CTRL_CMD_FAST_FORMAT_STOP, \
+ SD_CTRL_CMD_IS_FAST_FORMAT_RUNNING, \
+ SD_CTRL_CMD_GET_CAPACITY, \
+ SD_CTRL_CMD_IS_EXISTENCE, \
+ SD_CTRL_CMD_POLL_EXISTENCE, \
+ SD_CTRL_CMD_SET_CLEAR_EXISTENCE, \
+ SD_CTRL_CMD_WRITE_PROTECTION, \
+ SD_CTRL_CMD_QUERY_EVER_PLUGOUT, \
+ SD_CTRL_CMD_RESET_EVER_PLUGOUT, \
+ SD_CTRL_CMD_FORCE_SINGLE_LINE, \
+ SD_CTRL_CMD_GO_IDLE, \
+ SD_CTRL_CMD_CACHEABLE_BUFFER, \
+ SD_CTRL_CMD_ADD_CALLBACK, \
+ SD_CTRL_CMD_SET_FLAG, \
+ SD_CTRL_CMD_READ_TEST, \
+ SD_CTRL_CMD_SET_CLOCK_TEST, \
+ SD_CTRL_CMD_FLUSH, \
+ SD_CTRL_CMD_GET_AND_CLEAR_MEDIA_CHANGED, \
+ SD_CTRL_CMD_GPD_READ,\
+ SD_CTRL_CMD_GPD_WRITE,\
+ SD_CTRL_CMD_GET_BD_STRUCT_NUM,\
+ SD_CTRL_CMD_DUMMY_END,
+
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+/* FOR SD_CTRL_CMD_READ control command. */
+typedef struct
+{
+ DCL_UINT32 u4Sector; //this specify the starting sector to read
+ DCL_UINT32 u4Sectors; //this specify the number of sectors to read
+ void *bufferAddr; //we will move read data from card to this address
+} SD_CTRL_READ_T;
+
+/* FOR SD_CTRL_CMD_WRITE control command. */
+typedef struct
+{
+ DCL_UINT32 u4Sector; //this specify the starting sector to write
+ DCL_UINT32 u4Sectors; //this specify the number of sectors to write
+ void *bufferAddr; //we will move move data from this address to card
+} SD_CTRL_WRITE_T;
+
+/* FOR SD_CTRL_CMD_GPD_READ control command. */
+typedef struct
+{
+ DCL_UINT32 u4Sector; //this specify the starting sector to read
+ DCL_UINT32 u4Sectors; //this specify the number of sectors to read
+ void *bufferHead; //we will move read data from card to this address
+ void *bufferTail;
+} SD_CTRL_GPD_READ_T;
+
+/* FOR SD_CTRL_CMD_GPD_WRITE control command. */
+typedef struct
+{
+ DCL_UINT32 u4Sector; //this specify the starting sector to write
+ DCL_UINT32 u4Sectors; //this specify the number of sectors to write
+ void *bufferHead; //we will move move data from this address to card
+ void *bufferTail;
+} SD_CTRL_GPD_WRITE_T;
+typedef struct
+{
+ DCL_UINT32 max_bd_num;//specify the max bd struct num for link list dma transfer
+} SD_CTRL_MAX_BD_STRUCT_NUM_T;
+
+/* FOR SD_CTRL_CMD_READ_ODD_SIZE control command. */
+typedef struct
+{
+ DCL_UINT32 u4Sector; //this specify the starting sector to read
+ DCL_UINT32 u4Size; //this specify the number of bytes to read
+ void *bufferAddr; //we will move read data from card to this address
+} SD_CTRL_READ_ODD_T;
+
+/* FOR SD_CTRL_CMD_WRITE_ODD_SIZE control command. */
+typedef struct
+{
+ DCL_UINT32 u4Sector; //this specify the starting sector to write
+ DCL_UINT32 u4Size; //this specify the number of bytes to write
+ void *bufferAddr; //we will move move data from this address to card
+} SD_CTRL_WRITE_ODD_T;
+
+/* FOR SD_CTRL_CMD_ANALOG_SWITCH control command. */
+typedef struct
+{
+ DCL_UINT32 u4TargetInterface;
+} SD_CTRL_ANALOG_SWITCH_T;
+
+/* FOR SD_CTRL_CMD_GET_CAPACITY control command. */
+typedef struct
+{
+ DCL_BOOL gHighCapacityCard;
+ DCL_UINT64 pu8Capacity;
+} SD_CTRL_GET_CAPACITY_T;
+
+/* FOR SD_CTRL_CMD_READY control command. */
+typedef struct
+{
+ DCL_BOOL fgInited;
+} SD_CTRL_INITED_T;
+
+/* FOR SD_CTRL_CMD_IS_EXISTENCE and SD_CTRL_CMD_POLL_EXISTENCE control command. */
+typedef struct
+{
+ DCL_BOOL fgPresent;
+} SD_CTRL_EXISTENCE_T;
+
+/* FOR SD_CTRL_CMD_WRITE_PROTECTION control command. */
+typedef struct
+{
+ DCL_BOOL fgReadOnly;
+} SD_CTRL_WRITE_PROTECTION_T;
+
+/* FOR SD_CTRL_CMD_QUERY_EVER_PLUGOUT control command. */
+typedef struct
+{
+ DCL_BOOL fgEverPLugOut;
+} SD_CTRL_QUERY_EVER_PLUGOUT_T;
+
+/* FOR SD_CTRL_CMD_FORCE_SINGLE_LINE control command. */
+typedef struct
+{
+ DCL_BOOL fgIsItTrue;
+} SD_CTRL_FORCE_SINGLE_LINE_T;
+
+/* FOR SD_CTRL_CMD_CACHEABLE_BUFFER control command. */
+typedef struct
+{
+ DCL_BOOL fgIsCACHEABLE;
+} SD_CTRL_CACHEABLE_BUFFER_T;
+
+typedef struct
+{
+ MSDC_CALLBACK callback1;
+ MSDC_CALLBACK callback2;
+ MSDC_CALLBACK callback3;
+ MSDC_CALLBACK callback4;
+ MSDC_CALLBACK callback5;
+ MSDC_CALLBACK callback6;
+}SD_CTRL_CALLBACK_T;
+
+typedef struct
+{
+ DCL_UINT32 readTestFlag;
+}SD_CTRL_SET_READ_TEST_FLAG_T;
+
+typedef struct
+{
+ DCL_UINT32 startSector;
+ DCL_UINT32 sectorNum;
+}SD_CTRL_FLUSH_T;
+
+typedef struct
+{
+ DCL_BOOL enable;
+}SD_CTRL_FAST_FORMAT_T;
+
+typedef struct
+{
+ DCL_BOOL changed;
+}SD_CTRL_MEDIA_CHANGED_T;
+
+#define SD_CTRLS \
+ SD_CTRL_READ_T rSDRead; \
+ SD_CTRL_WRITE_T rSDWrite; \
+ SD_CTRL_READ_ODD_T rSDReadOdd;\
+ SD_CTRL_WRITE_ODD_T rSDWriteOdd; \
+ SD_CTRL_ANALOG_SWITCH_T rSDSwitch; \
+ SD_CTRL_GET_CAPACITY_T rSDGetCapacity; \
+ SD_CTRL_INITED_T rSDInited; \
+ SD_CTRL_EXISTENCE_T rSDExistence; \
+ SD_CTRL_EXISTENCE_T rSDPollExistence; \
+ SD_CTRL_WRITE_PROTECTION_T rSDWriteProrect; \
+ SD_CTRL_QUERY_EVER_PLUGOUT_T rSDQueryEverPugOut; \
+ SD_CTRL_FORCE_SINGLE_LINE_T rSDForceSingleLine; \
+ SD_CTRL_CACHEABLE_BUFFER_T rSDCacheableBuf; \
+ SD_CTRL_CALLBACK_T rSDCallBackFunc; \
+ SD_CTRL_SET_READ_TEST_FLAG_T rSDSetReadTestFlag; \
+ SD_CTRL_FLUSH_T rSDFlush; \
+ SD_CTRL_FAST_FORMAT_T rSDFastFormat; \
+ SD_CTRL_MEDIA_CHANGED_T rSDMediaChanged; \
+ SD_CTRL_GPD_READ_T rSDReadGPD;\
+ SD_CTRL_GPD_WRITE_T rSDWriteGPD;\
+ SD_CTRL_MAX_BD_STRUCT_NUM_T rSDMaxBD;
+
+
+/***********************************************************************************
+* following is the part of SDIO
+************************************************************************************/
+
+/*******************************************************************************
+ * DCL_FLAGS_T for SDIO
+ *******************************************************************************/
+#define DCL_SDIO_FLAGS_DEVICE_CARD1 0x1
+#define DCL_SDIO_FLAGS_DEVICE_CARD2 0x2
+#define DCL_SDIO_FLAGS_USAGE_GET_INFORMATION 0x10
+#define DCL_SDIO_FLAGS_USAGE_CMD 0x20
+
+#define DCL_SDIO_FLAGS_DEVICE_ALL (DCL_SDIO_FLAGS_DEVICE_CARD1|DCL_SDIO_FLAGS_DEVICE_CARD2)
+#define DCL_SDIO_FLAGS_USAGE_ALL (DCL_SDIO_FLAGS_USAGE_GET_INFORMATION|DCL_SDIO_FLAGS_USAGE_CMD)
+
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for SDIO
+ *******************************************************************************/
+#define SDIO_CMDS \
+ SDIO_CTRL_CMD_REG_WR, \
+ SDIO_CTRL_CMD_REG_WR_ISR, \
+ SDIO_CTRL_CMD_DATA_WR, \
+ SDIO_CTRL_CMD_REG_RD, \
+ SDIO_CTRL_CMD_DATA_RD, \
+ SDIO_CTRL_CMD_CHECK_INTR, \
+ SDIO_CTRL_CMD_ENABLE_INTR, \
+ SDIO_CTRL_CMD_INIT, \
+ SDIO_CTRL_CMD_ABORT, \
+ SDIO_CTRL_CMD_SW_RST, \
+ SDIO_CTRL_CMD_QUERY_BLK_SIZE, \
+ SDIO_CTRL_CMD_SET_BLK_SIZE, \
+ SDIO_CTRL_CMD_GET_BLK_SIZE, \
+ SDIO_CTRL_CMD_ENABLE_IO, \
+ SDIO_CTRL_CMD_SET_BUS_WIDTH, \
+ SDIO_CTRL_CMD_GET_CCCR, \
+ SDIO_CTRL_CMD_GET_FBR, \
+ SDIO_CTRL_CMD_CMD52_READ, \
+ SDIO_CTRL_CMD_CMD52_WRITE, \
+ SDIO_CTRL_CMD_CMD52_WRITE_READ, \
+ SDIO_CTRL_CMD_CMD53_READ, \
+ SDIO_CTRL_CMD_CMD53_WRITE, \
+ SDIO_CTRL_CMD_MCUDMA_READ, \
+ SDIO_CTRL_CMD_MCUDMA_WRITE, \
+ SDIO_CTRL_CMD_CLKPADRED_READ, \
+ SDIO_CTRL_CMD_CLKPADRED_WRITE, \
+ SDIO_CTRL_CMD_FORCEMCU_READ, \
+ SDIO_CTRL_CMD_FORCEMCU_WRITE, \
+ SDIO_CTRL_CMD_GETCLK, \
+ SDIO_CTRL_CMD_SETCLK,
+//guilin
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+
+/* For SDIO_CTRL_CMD_REG_WR, SDIO_CTRL_CMD_REG_WR_ISR, SDIO_CTRL_CMD_REG_RD control command.*/
+typedef struct
+{
+ DCL_SDIO_function_id_enum function;
+ DCL_UINT32 addr; // card's address to access
+ DCL_UINT32 data; // the data want to read from/write from card
+ DCL_SDIO_cmd53_op_enum op; // operation mode
+} SDIO_CTRL_REG_RW_T;
+
+/* For SDIO_CTRL_CMD_DATA_WR, SDIO_CTRL_CMD_DATA_RD, control command.*/
+typedef struct{
+ DCL_SDIO_function_id_enum function; // function
+ DCL_BOOL block; // block mode or not
+ DCL_SDIO_cmd53_op_enum op; // operation mode
+ DCL_UINT16 count; // byte or block count
+ DCL_UINT32 addr; // address
+ DCL_UINT32 buffer; // address of buffer for data transfer
+}SDIO_CTRL_DAT_RW_T;
+
+/* For SDIO_CTRL_CMD_SET_BLK_SIZE, SDIO_CTRL_CMD_GET_BLK_SIZE , control command.*/
+typedef struct{
+ DCL_SDIO_function_id_enum function;
+ DCL_UINT32 size;
+}SDIO_CTRL_SET_BLK_SIZE_T;
+
+/* For SDIO_CTRL_CMD_CHECK_INTR, control command.*/
+typedef struct{
+ DCL_SDIO_function_id_enum function;
+ DCL_BOOL *pending;
+}SDIO_CTRL_CHECK_INTR_T;
+
+/* For SDIO_CTRL_CMD_ENABLE_INTR, control command.*/
+typedef struct{
+ DCL_SDIO_function_id_enum function;
+ DCL_BOOL enable;
+}SDIO_CTRL_ENABLE_T;
+
+/* For SDIO_CTRL_CMD_GET_CCCR and SDIO_CTRL_CMD_GET_FBR, control command.*/
+typedef struct{
+ DCL_UINT8 *buffer;
+ DCL_UINT32 bufferLength;
+}SDIO_CTRL_GET_INFO_T;
+
+typedef struct{
+// rw_dir_enum rw; // directon (input)0=read,1=write
+ kal_uint8 rw; // directon (input)0=read,1=write
+ kal_uint8 func; // function (input)
+ kal_uint8 rdata; // write data or read back data (Input , output)
+ kal_uint8 wdata; // write data or read back data (Input , output)
+ kal_bool raw; // read after write
+ kal_bool stop; // stop data transfer
+ kal_uint32 addr; // address (input)
+ kal_uint8 r5_resp; // R5
+}SDIO_CTRL_CMD52_T;
+
+typedef struct{
+// rw_dir_enum rw; // directon (input)0=read,1=write
+ kal_uint8 rw; // directon (input)0=read,1=write
+ kal_uint8 func; // function (input)
+ kal_uint8 r5_resp; // R5
+// cmd53_op_enum op; // operation mode,0=FIX,1=INC
+ kal_uint8 op; // operation mode,0=FIX,1=INC
+ kal_bool block; // block mode or not
+ kal_uint16 count; // byte or block count
+ kal_uint32 addr; // address
+ kal_uint32 buffer; // address of buffer for data transfer
+}SDIO_CTRL_CMD53_T;
+
+typedef struct{
+ kal_uint32 data;
+}SDIO_CTRL_CMD_REG_T;
+
+#define SDIO_CTRLS \
+ SDIO_CTRL_REG_RW_T rSDIORegRw; \
+ SDIO_CTRL_DAT_RW_T rSDIODatRw; \
+ DCL_SDIO_function_id_enum rSDIOFunction; \
+ SDIO_CTRL_SET_BLK_SIZE_T rSDIOSetBlkSize; \
+ SDIO_CTRL_CHECK_INTR_T rSDIOCheckIntr; \
+ SDIO_CTRL_ENABLE_T rSDIOEnable; \
+ DCL_SD_BITWIDTH rSDIOBusWidth; \
+ SDIO_CTRL_GET_INFO_T rSDIOGetInfo; \
+ SDIO_CTRL_CMD52_T rSDIOCMD52; \
+ SDIO_CTRL_CMD53_T rSDIOCMD53; \
+ SDIO_CTRL_CMD_REG_T rSDIOCMDREG;
+//guilin
+#endif /*__DCL_MSDC_H_FRONT__*/
+#endif /*DCL_DEFINITION_STRUCT*/
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+//#ifndef __DCL_MSDC_H_FRONT__
+//#define __DCL_MSDC_H_FRONT__
+
+/*******************************************************************************
+ * Declare function prototype.
+ *******************************************************************************/
+/* DCL for SD/MMC*/
+/* DCL for SDIO */
+extern DCL_STATUS DclSD_Initialize(void);
+extern DCL_HANDLE DclSD_Open(DCL_DEV dev, DCL_FLAGS flags);
+extern DCL_STATUS DclSD_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+extern DCL_STATUS DclSD_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+extern DCL_STATUS DclSD_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+extern DCL_STATUS DclSD_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+extern DCL_STATUS DclSD_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+extern DCL_STATUS DclSD_Close(DCL_HANDLE handle);
+//#endif /*__DCL_MSDC_H_FRONT__*/
+#endif /*DCL_DEFINITION_PROTOTYPE*/
+
+
diff --git a/mcu/interface/driver/peripheral/dcl_mtad.h b/mcu/interface/driver/peripheral/dcl_mtad.h
new file mode 100644
index 0000000..a1784de
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_mtad.h
@@ -0,0 +1,378 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_MTAD_STRUCT__
+#define __DCL_MTAD_STRUCT__
+
+//#include "dcl.h"
+
+#if 0
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+/* under construction !*/
+#endif
+
+
+#define FAKE_MTU_SIZE (2048)
+
+//UART_CMD_OPEN
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+}MTAD_CTRL_OPEN_T;
+
+//UART_CMD_CLOSE
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+}MTAD_CTRL_CLOSE_T;
+
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+} MTAD_CTRL_CLR_BUFFER_T;
+
+//UART_CMD_PUT_ISR_BYTES
+typedef struct
+{
+ DCL_UINT16 u2Length;
+ DCL_UINT32 u4OwenrId;
+ DCL_UINT16 u2RetSize;
+ DCL_UINT8* puBuffaddr;
+}MTAD_CTRL_PUT_BYTES_T;
+
+typedef struct
+{
+ DCL_UINT32 u4OwnerId;
+ void *putIor;
+}MTAD_CTRL_PUT_BYTES_IOR_T;
+
+
+//TTY_CMD_GET_CHUNK_SIZE
+typedef struct
+{
+ DCL_UINT32 chunkSize;
+} MTAD_CTRL_GET_CHUNK_SIZE_T;
+
+//TTY_CMD_NEED_TX_DONE_CB
+typedef struct
+{
+ DCL_UINT32 u4OwnerId;
+ DCL_BOOL needTxDoneCb;
+} MTAD_CTRL_NEED_TX_DONE_CB_T;
+
+//TTY_CMD_GET_MTU_SIZE
+typedef struct
+{
+ DCL_UINT32 ulmtu_sz;
+ DCL_UINT32 dlmtu_sz;
+} MTAD_CTRL_GET_MTU_SIZE_T;
+
+/*!
+ * @brief TTY driver state
+ */
+typedef enum _tty_drv_mtad_state {
+ /*!
+ * @brief driver detached state
+ */
+ DRV_MTAD_ST_DETACHED = 0,
+ /*!
+ * @brief driver attached state
+ */
+ DRV_MTAD_ST_ATTACHED
+} tty_drv_mtad_state_e;
+
+//TTY_CMD_GET_DRV_STATE
+typedef struct
+{
+ DCL_UINT32 u4OwnerId;
+ tty_drv_mtad_state_e drv_state;
+} MTAD_CTRL_GET_DRV_STATE_T;
+
+
+//TTY_CMD_ASSIGN_RX_IOR
+typedef struct
+{
+ DCL_UINT32 u4OwnerId;
+ void *ior;
+} MTAD_CTRL_ASSIGN_RX_IOR_T;
+
+
+
+
+#define MTAD_CTRLS \
+ MTAD_CTRL_OPEN_T rMTADCtrlOPEN;\
+ MTAD_CTRL_CLOSE_T rMTADCtrlCLOSE;\
+ MTAD_CTRL_CLR_BUFFER_T rMTADCtrlCLRBUFFER;\
+ MTAD_CTRL_PUT_BYTES_T rMTADCtrlPUTBYTES;\
+ MTAD_CTRL_GET_MTU_SIZE_T rMTADCtrlGETMTUSIZE;\
+ MTAD_CTRL_GET_CHUNK_SIZE_T rMTADCtrlGETCHUNKSIZE;\
+ MTAD_CTRL_ASSIGN_RX_IOR_T rMTADCtrlAssignRxIor;\
+ MTAD_CTRL_NEED_TX_DONE_CB_T rMTADCtrlNeedTxDoneCb;\
+ MTAD_CTRL_GET_DRV_STATE_T rMTADCtrlGetDrvState;\
+ MTAD_CTRL_PUT_BYTES_IOR_T rMTADCtrlPUTBYTESIOR;\
+
+
+
+typedef enum
+{
+ DCL_MTAD_TYPE = 0x00,
+
+}MTAD_SIO_TYPE_T;
+
+
+#endif // DCL_DEFINITION_STRUCT
+#endif // __DCL_MTAD_STRUCT__
+
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+
+typedef DCL_STATUS(*mtad_handler_cb)(DCL_DEV dev, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+
+typedef struct
+{
+ MTAD_SIO_TYPE_T DevType;
+ mtad_handler_cb mtadHandlerCb;
+}MTAD_HANDLER_T;
+
+
+/*!
+* @function DclSerialPort_Open
+* @brief This function is to open the UART module and get a handle.
+* @param dev Port number. it can take DCL_UART_DEV as reference
+* @param flags module_type | FLAGS_UART_USE_VFIFO
+* module_type: KAL module type enum value
+* FLAGS_UART_USE_VFIFO: flags that specifies to use Virtual FIFO or not for UART device. Note that it's only valide for eDev with DCL_UART1, DCL_UART2, DCL_UART3(if exists)
+* [Note] Currently TTY doesn't handle flags!! This parameter is kept for backward compatible.
+* @result STATUS_FAIL Open failed.
+* @result STATUS_ALREADY_OPENED This device has already been opened.
+* @result STATUS_INVALID_DEVICE The device is not valid.
+* @result STATUS_SET_VFIFO_FAIL Fail to use Vitual FIFO for the UART port.
+* @result other value a valid handle
+*
+*/
+extern DCL_HANDLE DclSerialPort_Open(DCL_DEV dev, DCL_FLAGS flags);
+
+ /*!
+ * @function DclSerialPort_Control
+ * @brief This function is support UART module commands. It is called to send command to control the UART module.
+ * @param handle a valid handle return by DclSerialPort_Open()
+ * @param cmd dcl uart commands
+ * @param data pointer to the corresponding data structure of command
+ * @result STATUS_OK command is executed successfully.
+ * @result STATUS_INVALID_CMD It's a invalid command.
+ * @result STATUS_INVALID_HANDLE It's a invalid handle.
+ */
+ extern DCL_STATUS DclSerialPort_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+
+
+/* ----------------------------------- Export to upper layer --------------------------------------- */
+
+/*!
+* @function [New TTY API] DclSerialPort_UpModuleInit
+* @brief This function is to initialize/start designated COM Port for upper module.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param module_id upper module id
+* @param flag TTY COM Port attribute. Currently they are TTY_FLAG_NEW_TX or TTY_FLAG_NEW_RX.
+* Upper module can initialize flag with new Tx/Rx flow (gpd based) or conventional Tx/Rx (buffer/length based) flow.
+* ex. New Tx and Conventional Rx - DclSerialPort_UpModuleReinit(handle, module_id, TTY_FLAG_NEW_TX);
+* @result STATUS_OK Init COM Port device successfully.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_ALREADY_OPENED The COM Port has been initialized by other module.
+* @result STATUS_DEVICE_NOT_EXIST The corresponding device driver of COM Port has not been initialized.
+*/
+extern DCL_STATUS DclSerialPort_UpModuleInit(DCL_HANDLE handle, module_type module_id, int flag);
+
+/*!
+* @function [New TTY API] DclSerialPort_UpModuleDeinit
+* @brief This function is to de-init/de-register COM Port.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @result STATUS_OK Deinit COM Port device successfully.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_NOT_OPENED The COM Port has not been initialized.
+* @result STATUS_DEVICE_NOT_EXIST The corresponding device driver of COM Port has not been initialized.
+*/
+extern DCL_STATUS DclSerialPort_UpModuleDeinit(DCL_HANDLE handle);
+
+
+
+/*!
+* @function [New TTY API] DclSerialPort_UpModuleRegisterCb
+* @brief This function is for upper layer module to register callback function.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param rx_cb rx callback function, driver send receiving data to upper layer through this rx callback function
+* @param tx_done_cb tx done callback function, this callback function will be called when data has been sent
+* @param drv_state_change_cb driver state change callback function, it notify the upper layer module when driver state is changed, ex. USB disconnect
+* @result STATUS_OK Register callback function successfully.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_NOT_OPENED The COM Port has not been initialized.
+* @result STATUS_DEVICE_NOT_EXIST The corresponding device driver of COM Port has not been initialized.
+* @result STATUS_FAIL Failed for other reasons.
+*/
+extern DCL_STATUS DclSerialPort_UpModuleRegisterCb(DCL_HANDLE handle, tty_rx_cb rx_cb, tty_txdone_cb tx_done_cb, tty_drv_state_change_cb drv_state_change_cb);
+
+
+/*!
+* @function [New TTY API] DclSerialPort_UpModuleTransmit
+* @brief This function is to transmit data to COM Port in ior format.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param ior pointer to tx io request which is sent to COM Port driver
+* @result STATUS_OK Transmit ior successfully.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_FAIL Failed for other reasons.
+*/
+extern DCL_STATUS DclSerialPort_UpModuleTransmit(DCL_HANDLE handle, tty_io_request_t *ior);
+
+
+/*!
+* @function [New TTY API] DclSerialPort_UpModuleTransmitLight
+* @brief This function is to transmit data to COM Port in ior format and light-weight.
+* Before user use this Tx function, it must calculate tx checksum and flush GPD in advance.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param ior pointer to tx io request which is sent to COM Port driver
+* @result STATUS_OK Transmit ior successfully.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_FAIL Failed for other reasons.
+*/
+extern DCL_STATUS DclSerialPort_UpModuleTransmitLight(DCL_HANDLE handle, tty_io_request_t *ior);
+
+/*!
+* @function [New TTY API] DclSerialPort_UpModuleAssignRxIor
+* @brief This function is to assign empty Rx ior to driver for data receiving.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param rx_ior pointer to rx io request for data receiving
+* @result STATUS_OK Assign Rx ior successfully.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_FAIL Failed for other reasons.
+*/
+extern DCL_STATUS DclSerialPort_UpModuleAssignRxIor(DCL_HANDLE handle, tty_io_request_t *rx_ior);
+
+
+/* ------------------------------------ Export to driver ------------------------------------------- */
+/*!
+* @function DclSerialPort_DrvRegisterCb
+* @brief This function is to register callback funtion for the UART module or COM Port class driver.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param seriport_handler the structure contains callback function and device type.
+ TTY would send commands (SIO/UART/USB/TTY/...) to driver through this callback function when the corresponding event happens.
+* @result STATUS_OK successful.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_ALREADY_OPENED This device has already been opened.
+* @result STATUS_INVALID_ARGUMENT The parameter is invalid, ex. uart_handler_cb is NULL.
+*/
+extern DCL_STATUS DclSerialPort_DrvRegisterCb(DCL_HANDLE handle, Seriport_HANDLER_T* seriport_handler);
+
+/*!
+* @function DclSerialPort_DrvDeRegisterCb
+* @brief This function is to De-register callback funtion for the UART module or COM Port class driver.
+* @param handle a valid handle return by DclSerialPort_Open()
+*
+* @result STATUS_OK successful.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_INVALID_OPERATION This device has already been de-registered or driver state is attached.
+*/
+extern DCL_STATUS DclSerialPort_DrvDeRegisterCb(DCL_HANDLE handle);
+
+/*!
+* @function [New TTY API] DclSerialPort_DrvAttach
+* @brief This function is for driver to inform TTY that the device is attached/connected.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @result STATUS_OK successful.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_DEVICE_NOT_EXIST The corresponding device driver of COM Port has not been initialized.
+*/
+extern DCL_STATUS DclSerialPort_DrvAttach(DCL_HANDLE handle);
+
+/*!
+* @function [New TTY API] DclSerialPort_DrvDetach
+* @brief This function is for driver to inform TTY that the device is detached/disconnected.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @result STATUS_OK successful.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_DEVICE_NOT_EXIST The corresponding device driver of COM Port has not been initialized.
+*/
+extern DCL_STATUS DclSerialPort_DrvDetach(DCL_HANDLE handle);
+
+/*!
+* @function [New TTY API] DclSerialPort_DrvRx
+* @brief This function is for driver to send back the received data to TTY/upper layer.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param source_id driver module id
+* @param rx_ior received data with ior format
+* @result STATUS_OK successfully register the callback function.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_NOT_OPENED The COM Port is not opened by upper layer.
+*/
+extern DCL_STATUS DclSerialPort_DrvRx(DCL_HANDLE handle, module_type source_id, void *rx_ior);
+
+/*!
+* @function [New TTY API] DclSerialPort_DrvTxDone
+* @brief This function is for driver to send back the transmitted (tx done) data to TTY/upper layer.
+* This function is called if "need tx done callback" is configured YES.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param source_id driver module id
+* @param tx_ior transmitted data with ior format
+* @result STATUS_OK successful.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_NOT_OPENED The COM Port is not opened by upper layer.
+*/
+extern DCL_STATUS DclSerialPort_DrvTxDone(DCL_HANDLE handle, module_type source_id, void *tx_ior);
+
+#endif // DCL_DEFINITION_PROTOTYPE
+
+
diff --git a/mcu/interface/driver/peripheral/dcl_pfc.h b/mcu/interface/driver/peripheral/dcl_pfc.h
new file mode 100644
index 0000000..d6dd0dd
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_pfc.h
@@ -0,0 +1,394 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2010
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pfc.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for PFC.
+ *
+ * Author:
+ * -------
+ *
+ * Ansel Liao
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_PFC_H_STRUCT__
+#define __DCL_PFC_H_STRUCT__
+
+/*******************************************************************************
+ * DCL_OPTIONS for PFC
+ *******************************************************************************/
+#define PFC_OPTIONS
+
+/*******************************************************************************
+ * DCL_CONFIGURE_T for PFC
+ *******************************************************************************/
+#define PFC_CONFIGS
+
+/*******************************************************************************
+ * DCL_EVENT for PFC
+ *******************************************************************************/
+#define PFC_EVENTS
+
+/*******************************************************************************
+ * PPP_PFC_CHANNEL enum for PFC
+ *******************************************************************************/
+typedef enum {
+ PPP_PFC_CHANNEL_0 = 0,
+ PPP_PFC_CHANNEL_1,
+ PPP_PFC_CHANNEL_2,
+} PPP_PFC_CHANNEL;
+
+/*******************************************************************************
+ * PPP_PFC_CHANNEL enum for PFC
+ *******************************************************************************/
+typedef enum {
+ PFC_ENCODE = 0,
+ PFC_DECODE,
+} PFC_OPERATION_SEL_T;
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for PFC
+ *******************************************************************************/
+/* The PFC Command Values in DCL_CTRL_CMD_T Enum of dcl.h */
+#ifdef __BUILD_DOM__
+typedef enum {
+ PFC_CMD_RESET, /* To Reset PFC */
+ PFC_CMD_SET_CONFIG, /* to set config */
+ PFC_CMD_ENCODE, /* To Encode PPP Framer */
+ PFC_CMD_DECODE, /* To Decode PPP Framer */
+ PFC_CMD_DEQUEUE, /* to de-Q encode/decode gpd list */
+ PFC_CMD_RELOAD_RX /* to reload GPD list */
+} DCL_CTRL_CMD_T;
+#else /* __BUILD_DOM__ */
+#define PFC_CMDS \
+ PFC_CMD_RESET, \
+ PFC_CMD_SET_CONFIG, \
+ PFC_CMD_ENCODE, \
+ PFC_CMD_DECODE, \
+ PFC_CMD_DEQUEUE, \
+ PFC_CMD_RELOAD_RX,
+#endif /* __BUILD_DOM__ */
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+
+/* For PFC_CMD_RESET command. */
+typedef struct
+{
+ DCL_UINT32 en_de; /* input: encode or decode */
+ DCL_UINT32 channel; /* input: channel id */
+} PFC_CTRL_RESET_T;
+
+/* For PFC_CMD_SET_CONFIG command. */
+typedef struct
+{
+ DCL_UINT32 en_de; /* input: encode or decode */
+ DCL_UINT32 channel; /* input: channel id */
+ DCL_BOOL f32; /* input: fcs mode */
+ DCL_BOOL acfc; /* input: address and control field compression */
+ DCL_BOOL pfc; /* input: protocol field compression */
+ DCL_UINT16 max_pkt_sz; /* input: max packet size */
+ DCL_UINT16 ptc; /* input: pfc protocol */
+ DCL_UINT32 pfc_accm[7]; /* input: accm 0 ~ 6 */
+} PFC_CTRL_SET_CONFIG_T;
+
+/* For PFC_CMD_ENCODE command. */
+typedef struct
+{
+ DCL_UINT32 channel; /* input: channel id */
+ void *head; /* input: head of TGPD list */
+ void *tail; /* input: tail of TGPD list */
+} PFC_CTRL_ENCODE_T;
+
+/* For PFC_CMD_DECODE command. */
+typedef struct
+{
+ DCL_UINT32 channel; /* input: channel id */
+ void *head; /* input: head of TGPD list */
+ void *tail; /* input: tail of TGPD list */
+} PFC_CTRL_DECODE_T;
+
+/* For PFC_CMD_DEQUEUE command. */
+typedef struct
+{
+ DCL_UINT32 en_de; /* input: encode or decode */
+ DCL_UINT32 channel; /* input: channel id */
+ void **head; /* output: head of RGPD list */
+ void **tail; /* output: tail of RGPD list */
+ DCL_UINT32 *queue_len; /* output: length of queue */
+} PFC_CTRL_DEQUEUE_T;
+
+/* For PFC_CMD_RELOAD_RX command. */
+typedef struct
+{
+ DCL_UINT32 en_de; /* input: encode or decode */
+ DCL_UINT32 channel; /* input: channel id */
+ void *head; /* input: head of RGPD list */
+ void *tail; /* input: tail of RGPD list */
+ DCL_UINT32 queue_len; /* input: length of RGPD list */
+} PFC_CTRL_RELOAD_RX_T;
+
+/* The PFC Command Parameter Data Structure for Each Command in DCL_CTRL_DATA_T Enum of dcl.h */
+#ifdef __BUILD_DOM__
+typedef union
+{
+ PFC_CTRL_RESET_T r_pfc_ctrl_reset; /* Data Structure for PFC_CMD_RESET */
+ PFC_CTRL_SET_CONFIG_T r_pfc_ctrl_set_config; /* Data Structure for PFC_CMD_SET_CONFIG */
+ PFC_CTRL_ENCODE_T r_pfc_ctrl_encode; /* Data Structure for PFC_CMD_ENCODE */
+ PFC_CTRL_DECODE_T r_pfc_ctrl_decode; /* Data Structure for PFC_CMD_DECODE */
+ PFC_CTRL_DEQUEUE_T r_pfc_ctrl_dequeue; /* Data Structure for PFC_CMD_DEQUEUE */
+ PFC_CTRL_RELOAD_RX_T r_pfc_ctrl_reload_rx; /* Data Structure for PFC_CMD_RELOAD_RX */
+} DCL_CTRL_DATA_T;
+#else /* __BUILD_DOM__ */
+#define PFC_CTRLS \
+ PFC_CTRL_RESET_T r_pfc_ctrl_reset; \
+ PFC_CTRL_SET_CONFIG_T r_pfc_ctrl_set_config; \
+ PFC_CTRL_ENCODE_T r_pfc_ctrl_encode; \
+ PFC_CTRL_DECODE_T r_pfc_ctrl_decode; \
+ PFC_CTRL_DEQUEUE_T r_pfc_ctrl_dequeue; \
+ PFC_CTRL_RELOAD_RX_T r_pfc_ctrl_reload_rx;
+#endif /* __BUILD_DOM__ */
+
+#endif // #ifndef __DCL_PFC_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_PFC_H_PROTOTYPE__
+#define __DCL_PFC_H_PROTOTYPE__
+
+
+/*************************************************************************
+* FUNCTION
+* DclPFC_Initialize
+*
+* DESCRIPTION
+* This function is to initialize PFC module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* Return the status of DclPFC_Initialize
+*
+* RETURN VALUES
+* STATUS_OK: Initialize Finished
+*
+*************************************************************************/
+extern DCL_STATUS DclPFC_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclPFC_Open
+*
+* DESCRIPTION
+* This function is to open the PFC module and return a handle
+*
+* PARAMETERS
+* dev: [IN] Only valid for DCL_PFC
+* flags: [IN] No sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* Return DCL_HANDLE of PFC
+*
+* RETURN VALUES
+* DCL_HANDLE_INVALID : Open failed
+* Other value : A valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclPFC_Open(DCL_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* DclPFC_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the PFC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclPFC_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclPFC_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the PFC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclPFC_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclPFC_Configure
+*
+* DESCRIPTION
+* This function is not supported for the PFC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclPFC_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+/*************************************************************************
+* FUNCTION
+* DclPFC_RegisterCallback
+*
+* DESCRIPTION
+* This function is to set callback function for the PFC module.
+*
+* PARAMETERS
+* handle: the returned handle value of DclPFC_Open
+* event: Supported events:
+* callback: the callback function for registered events
+*
+* RETURNS
+* STATUS_OK: Successfully register the callback function.
+* STATUS_INVALID_DCL_HANDLE: It's a invalid handle.
+* STATUS_NOT_OPENED: The module has not been opened.
+* STATUS_INVALID_EVENT: The event parameter is invalid.
+*
+*************************************************************************/
+extern DCL_STATUS DclPFC_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+/*************************************************************************
+* FUNCTION
+* DclPFC_Control
+*
+* DESCRIPTION
+* This function is to send command to control the PFC module.
+*
+* PARAMETERS
+* handle: [IN] The handle value returned from DclPFC_Open
+* cmd: [IN] A control command for PFC module
+* 1. PFC_CMD_RESET: to reset PFC Module
+* 2. PFC_CMD_ENCODE: to Encode
+* 3. PFC_CMD_DECODE: to Decode
+*
+* data: [IN] The data of the control command
+* 1. PFC_CMD_RESET: pointer to a PFC_CTRL_RESET_T structure
+* 2. PFC_CMD_ENCODE: pointer to a PFC_CTRL_ENCODE_T structure
+* 3. PFC_CMD_DECODE: pointer to a PFC_CTRL_DECODE_T structure
+*
+* RETURNS
+* Return the status of DclPFC_Control
+*
+* RETURN VALUES
+* STATUS_OK: Command is executed successfully.
+* STATUS_FAIL: Command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+*
+*************************************************************************/
+extern DCL_STATUS DclPFC_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclPFC_Close
+*
+* DESCRIPTION
+* This function is to close the PFC module.
+*
+* PARAMETERS
+* handle: [IN] The returned handle value of DclPFC_Open
+*
+* RETURNS
+* Return the status of DclPFC_Close
+*
+* RETURN VALUES
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclPFC_Close(DCL_HANDLE handle);
+
+// MoDIS parser skip end
+
+#endif // #ifndef __DCL_PFC_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
diff --git a/mcu/interface/driver/peripheral/dcl_pmu.h b/mcu/interface/driver/peripheral/dcl_pmu.h
new file mode 100644
index 0000000..cecef22
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_pmu.h
@@ -0,0 +1,3700 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pmu.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for PMU.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_PMU_H_STRUCT__
+#define __DCL_PMU_H_STRUCT__
+
+
+/*******************************************************************************
+ * DCL_OPTIONS for PMU
+ *******************************************************************************/
+#define PMU_OPTIONS
+
+ /*******************************************************************************
+ * DCL_CONFIGURE_T for PMU
+ *******************************************************************************/
+
+#define PMU_CONFIGS
+
+/*******************************************************************************
+ * DCL_EVENT for PMU
+ *******************************************************************************/
+#define PMU_EVENTS
+
+/* Enum of LDO/BUCK List */
+typedef enum
+{
+ VA12,
+ VRTC,
+ VMIC,
+ VAUDN,
+ VAUDP,
+ VRF28,
+ VRF=VRF28,
+ VRF28_1=VRF28,
+ VRF28_2,
+ VTCXO,
+ VTCXO_1=VTCXO,
+ VTCXO_2,
+ VA25,
+ VCAMA,
+ VCAMD,
+ VCAM_IO,
+ VCAM_AF,
+ VIO28,
+ VUSB,
+ VBT,
+ VSIM,
+ VSIM1 = VSIM,
+ VSIM2,
+ VIBR,
+ VMC,
+ VMC1,
+ VMCH,
+ VCAMA2,
+ VCAMD2,
+ VFM,
+ VM12,
+ VM12_1,
+ VM12_2,
+ VM12_INT,
+ VCORE,
+ VCORE2,
+ VIO18,
+ VPA_SW,
+ VPROC,
+ VRF18,
+ VRF12,
+ VRF18_1,
+ VRF18_2,
+ VRF1,
+ VRF2,
+ VA28,
+ VM,
+ VSF,
+ VWIFI2V8,
+ VWIFI3V3,
+ V3GTX,
+ V3GRX,
+ VGP,
+ VGP2,
+ VSDIO,
+ VDIG,
+ VBUS,
+ VA1,
+ VA2,
+ VMIPI,
+ VBACKUP,
+ VMODEM,
+ VSRAM_MD,
+ VMD1,
+ VTCXO24,
+ VTCXO28,
+ VXO22,
+ VFE28,
+ VS1,
+ VS2,
+ VPA2,
+ VSRAM_OTHERS,
+ VRF18_VOCAL,
+ VRF12_VOCAL,
+ VRF18_VOTRIM,
+ VRF12_VOTRIM,
+ VPA_OC_SDN_STATUS,
+ VPA_OC_SDN_EN,
+ VSRAM_GPU,
+ VGPU,
+ VGPU11,
+ VGPU12,
+ VPROC1,
+ VPROC2,
+ VPU,
+ VSRAM_PROC1,
+ VSRAM_PROC2,
+ PMU_LDO_BUCK_MAX,
+ VIO18_VOCAL,
+ VIO18_VOTRIM,
+}PMU_LDO_BUCK_LIST_ENUM;
+
+/* Enum of VPA List */
+typedef enum
+{
+ VPA,
+ VPA1=VPA,
+ PMU_VPA_MAX
+}PMU_VPA_LIST_ENUM;
+
+/* Enum of VRF18 List */
+typedef enum
+{
+ PMIC_VRF18,
+ PMIC_VRF18_1 = PMIC_VRF18,
+ PMIC_VRF18_2,
+ PMIC_VRF18_MAX
+}PMIC_VRF18_LIST_ENUM;
+
+/* Enum of VSIM List */
+typedef enum
+{
+ PMIC_VSIM,
+ PMIC_VSIM1 = PMIC_VSIM,
+ PMIC_VSIM2,
+ PMIC_VSIM_MAX
+}PMIC_VSIM_LIST_ENUM;
+
+/* Enum of KPLED List */
+typedef enum
+{
+ KPLED,
+ PMU_KPLED_MAX
+}PMU_KPLED_LIST_ENUM;
+
+/* Enum of CHR List */
+typedef enum
+{
+ CHR,
+ PMU_CHR_MAX
+}PMU_CHR_LIST_ENUM;
+
+/* Enum of STARTUP List */
+typedef enum
+{
+ STRUP,
+ PMU_STRUP_MAX
+}PMU_STRUP_LIST_ENUM;
+
+/* Enum of ISINK List */
+typedef enum
+{
+ ISINK0,
+ ISINK1,
+ ISINK2,
+ ISINK3,
+ ISINK4,
+ ISINK5,
+ PMU_ISINK_MAX
+}PMU_ISINK_LIST_ENUM;
+
+/* Enum of BOOST List */
+typedef enum
+{
+ BOOST,
+ BOOST1=BOOST,
+ BOOST2,
+ PMU_BOOST_MAX
+}PMU_BOOST_LIST_ENUM;
+
+/* Enum of SPK List */
+typedef enum
+{
+ SPK,
+ PMU_SPK_MAX
+}PMU_SPK_LIST_ENUM;
+
+/* Enum of LPOSC List */
+typedef enum
+{
+ LPOSC,
+ PMU_LPOSC_MAX
+}PMU_LPOSC_LIST_ENUM;
+
+/* Enum of Voltage List */
+typedef enum
+{
+ PMU_VOLT_00_000000_V = 0,
+ PMU_VOLT_00_100000_V = 100000,
+ PMU_VOLT_00_200000_V = 200000,
+ PMU_VOLT_00_300000_V = 300000,
+ PMU_VOLT_00_400000_V = 400000,
+ PMU_VOLT_00_450000_V = 450000,
+ PMU_VOLT_00_500000_V = 500000,
+ PMU_VOLT_00_525000_V = 525000,
+ PMU_VOLT_00_550000_V = 550000,
+ PMU_VOLT_00_568000_V = 568000,
+ PMU_VOLT_00_600000_V = 600000,
+ PMU_VOLT_00_650000_V = 650000,
+ PMU_VOLT_00_700000_V = 700000,
+ PMU_VOLT_00_725000_V = 725000,
+ PMU_VOLT_00_750000_V = 750000,
+ PMU_VOLT_00_775000_V = 775000,
+ PMU_VOLT_00_800000_V = 800000,
+ PMU_VOLT_00_825000_V = 825000,
+ PMU_VOLT_00_850000_V = 850000,
+ PMU_VOLT_00_875000_V = 875000,
+ PMU_VOLT_00_900000_V = 900000,
+ PMU_VOLT_00_925000_V = 925000,
+ PMU_VOLT_00_950000_V = 950000,
+ PMU_VOLT_00_975000_V = 975000,
+ PMU_VOLT_01_000000_V = 1000000,
+ PMU_VOLT_01_025000_V = 1025000,
+ PMU_VOLT_01_050000_V = 1050000,
+ PMU_VOLT_01_060000_V = 1060000,
+ PMU_VOLT_01_075000_V = 1075000,
+ PMU_VOLT_01_100000_V = 1100000,
+ PMU_VOLT_01_125000_V = 1125000,
+ PMU_VOLT_01_150000_V = 1150000,
+ PMU_VOLT_01_175000_V = 1175000,
+ PMU_VOLT_01_200000_V = 1200000,
+ PMU_VOLT_01_225000_V = 1225000,
+ PMU_VOLT_01_250000_V = 1250000,
+ PMU_VOLT_01_275000_V = 1275000,
+ PMU_VOLT_01_300000_V = 1300000,
+ PMU_VOLT_01_325000_V = 1325000,
+ PMU_VOLT_01_350000_V = 1350000,
+ PMU_VOLT_01_375000_V = 1375000,
+ PMU_VOLT_01_400000_V = 1400000,
+ PMU_VOLT_01_425000_V = 1425000,
+ PMU_VOLT_01_450000_V = 1450000,
+ PMU_VOLT_01_475000_V = 1475000,
+ PMU_VOLT_01_500000_V = 1500000,
+ PMU_VOLT_01_520000_V = 1520000,
+ PMU_VOLT_01_525000_V = 1525000,
+ PMU_VOLT_01_540000_V = 1540000,
+ PMU_VOLT_01_550000_V = 1550000,
+ PMU_VOLT_01_560000_V = 1560000,
+ PMU_VOLT_01_575000_V = 1575000,
+ PMU_VOLT_01_580000_V = 1580000,
+ PMU_VOLT_01_600000_V = 1600000,
+ PMU_VOLT_01_620000_V = 1620000,
+ PMU_VOLT_01_625000_V = 1625000,
+ PMU_VOLT_01_640000_V = 1640000,
+ PMU_VOLT_01_650000_V = 1650000,
+ PMU_VOLT_01_660000_V = 1660000,
+ PMU_VOLT_01_675000_V = 1675000,
+ PMU_VOLT_01_680000_V = 1680000,
+ PMU_VOLT_01_700000_V = 1700000,
+ PMU_VOLT_01_720000_V = 1720000,
+ PMU_VOLT_01_725000_V = 1725000,
+ PMU_VOLT_01_740000_V = 1740000,
+ PMU_VOLT_01_750000_V = 1750000,
+ PMU_VOLT_01_760000_V = 1760000,
+ PMU_VOLT_01_775000_V = 1775000,
+ PMU_VOLT_01_780000_V = 1780000,
+ PMU_VOLT_01_800000_V = 1800000,
+ PMU_VOLT_01_820000_V = 1820000,
+ PMU_VOLT_01_825000_V = 1825000,
+ PMU_VOLT_01_840000_V = 1840000,
+ PMU_VOLT_01_850000_V = 1850000,
+ PMU_VOLT_01_860000_V = 1860000,
+ PMU_VOLT_01_875000_V = 1875000,
+ PMU_VOLT_01_880000_V = 1880000,
+ PMU_VOLT_01_900000_V = 1900000,
+ PMU_VOLT_01_920000_V = 1920000,
+ PMU_VOLT_01_925000_V = 1925000,
+ PMU_VOLT_01_940000_V = 1940000,
+ PMU_VOLT_01_950000_V = 1950000,
+ PMU_VOLT_01_960000_V = 1960000,
+ PMU_VOLT_01_975000_V = 1975000,
+ PMU_VOLT_01_980000_V = 1980000,
+ PMU_VOLT_02_000000_V = 2000000,
+ PMU_VOLT_02_020000_V = 2020000,
+ PMU_VOLT_02_025000_V = 2025000,
+ PMU_VOLT_02_040000_V = 2040000,
+ PMU_VOLT_02_050000_V = 2050000,
+ PMU_VOLT_02_060000_V = 2060000,
+ PMU_VOLT_02_075000_V = 2075000,
+ PMU_VOLT_02_080000_V = 2080000,
+ PMU_VOLT_02_100000_V = 2100000,
+ PMU_VOLT_02_120000_V = 2120000,
+ PMU_VOLT_02_125000_V = 2125000,
+ PMU_VOLT_02_140000_V = 2140000,
+ PMU_VOLT_02_150000_V = 2150000,
+ PMU_VOLT_02_175000_V = 2175000,
+ PMU_VOLT_02_200000_V = 2200000,
+ PMU_VOLT_02_225000_V = 2225000,
+ PMU_VOLT_02_250000_V = 2250000,
+ PMU_VOLT_02_275000_V = 2275000,
+ PMU_VOLT_02_300000_V = 2300000,
+ PMU_VOLT_02_375000_V = 2375000,
+ PMU_VOLT_02_350000_V = 2350000,
+ PMU_VOLT_02_425000_V = 2425000,
+ PMU_VOLT_02_400000_V = 2400000,
+ PMU_VOLT_02_450000_V = 2450000,
+ PMU_VOLT_02_500000_V = 2500000,
+ PMU_VOLT_02_550000_V = 2550000,
+ PMU_VOLT_02_575000_V = 2575000,
+ PMU_VOLT_02_600000_V = 2600000,
+ PMU_VOLT_02_650000_V = 2650000,
+ PMU_VOLT_02_700000_V = 2700000,
+ PMU_VOLT_02_725000_V = 2725000,
+ PMU_VOLT_02_750000_V = 2750000,
+ PMU_VOLT_02_760000_V = 2760000,
+ PMU_VOLT_02_800000_V = 2800000,
+ PMU_VOLT_02_850000_V = 2850000,
+ PMU_VOLT_02_875000_V = 2875000,
+ PMU_VOLT_02_900000_V = 2900000,
+ PMU_VOLT_02_950000_V = 2950000,
+ PMU_VOLT_03_000000_V = 3000000,
+ PMU_VOLT_03_025000_V = 3025000,
+ PMU_VOLT_03_050000_V = 3050000,
+ PMU_VOLT_03_100000_V = 3100000,
+ PMU_VOLT_03_150000_V = 3150000,
+ PMU_VOLT_03_175000_V = 3175000,
+ PMU_VOLT_03_200000_V = 3200000,
+ PMU_VOLT_03_250000_V = 3250000,
+ PMU_VOLT_03_275000_V = 3275000,
+ PMU_VOLT_03_300000_V = 3300000,
+ PMU_VOLT_03_325000_V = 3325000,
+ PMU_VOLT_03_350000_V = 3350000,
+ PMU_VOLT_03_400000_V = 3400000,
+ PMU_VOLT_03_450000_V = 3450000,
+ PMU_VOLT_03_500000_V = 3500000,
+ PMU_VOLT_03_550000_V = 3550000,
+ PMU_VOLT_03_600000_V = 3600000,
+ PMU_VOLT_03_650000_V = 3650000,
+ PMU_VOLT_03_800000_V = 3800000,
+ PMU_VOLT_03_950000_V = 3950000,
+ PMU_VOLT_04_000000_V = 4000000,
+ PMU_VOLT_04_012500_V = 4012500,
+ PMU_VOLT_04_025000_V = 4025000,
+ PMU_VOLT_04_037500_V = 4037500,
+ PMU_VOLT_04_050000_V = 4050000,
+ PMU_VOLT_04_062500_V = 4062500,
+ PMU_VOLT_04_067500_V = 4067500,
+ PMU_VOLT_04_075000_V = 4075000,
+ PMU_VOLT_04_087500_V = 4087500,
+ PMU_VOLT_04_100000_V = 4100000,
+ PMU_VOLT_04_112500_V = 4112500,
+ PMU_VOLT_04_115000_V = 4115000,
+ PMU_VOLT_04_116000_V = 4116000,
+ PMU_VOLT_04_125000_V = 4125000,
+ PMU_VOLT_04_137500_V = 4137500,
+ PMU_VOLT_04_150000_V = 4150000,
+ PMU_VOLT_04_162500_V = 4162500,
+ PMU_VOLT_04_175000_V = 4175000,
+ PMU_VOLT_04_187500_V = 4187500,
+ PMU_VOLT_04_200000_V = 4200000,
+ PMU_VOLT_04_212500_V = 4212500,
+ PMU_VOLT_04_225000_V = 4225000,
+ PMU_VOLT_04_237500_V = 4237500,
+ PMU_VOLT_04_250000_V = 4250000,
+ PMU_VOLT_04_262500_V = 4262500,
+ PMU_VOLT_04_275000_V = 4275000,
+ PMU_VOLT_04_287500_V = 4287500,
+ PMU_VOLT_04_300000_V = 4300000,
+ PMU_VOLT_04_325000_V = 4325000,
+ PMU_VOLT_04_350000_V = 4350000,
+ PMU_VOLT_04_375000_V = 4375000,
+ PMU_VOLT_04_400000_V = 4400000,
+ PMU_VOLT_04_411500_V = 4411500,
+ PMU_VOLT_04_450000_V = 4450000,
+ PMU_VOLT_04_500000_V = 4500000,
+ PMU_VOLT_04_550000_V = 4550000,
+ PMU_VOLT_04_600000_V = 4600000,
+ PMU_VOLT_04_700000_V = 4700000,
+ PMU_VOLT_04_800000_V = 4800000,
+ PMU_VOLT_04_850000_V = 4850000,
+ PMU_VOLT_04_950000_V = 4950000,
+ PMU_VOLT_05_000000_V = 5000000,
+ PMU_VOLT_05_150000_V = 5150000,
+ PMU_VOLT_05_250000_V = 5250000,
+ PMU_VOLT_05_300000_V = 5300000,
+ PMU_VOLT_05_450000_V = 5450000,
+ PMU_VOLT_06_000000_V = 6000000,
+ PMU_VOLT_06_500000_V = 6500000,
+ PMU_VOLT_06_750000_V = 6750000,
+ PMU_VOLT_07_000000_V = 7000000,
+ PMU_VOLT_07_250000_V = 7250000,
+ PMU_VOLT_07_500000_V = 7500000,
+ PMU_VOLT_08_000000_V = 8000000,
+ PMU_VOLT_08_500000_V = 8500000,
+ PMU_VOLT_09_500000_V = 9500000,
+ PMU_VOLT_10_000000_V = 10000000,
+ PMU_VOLT_10_500000_V = 10500000,
+ PMU_VOLT_MAX,
+ PMU_VOLT_INVALID
+
+}PMU_VOLTAGE_ENUM;
+
+typedef enum
+{
+ PMU_VOLT_CAL_MINUS_00_140000_V = -140000,
+ PMU_VOLT_CAL_MINUS_00_120000_V = -120000,
+ PMU_VOLT_CAL_MINUS_00_100000_V = -100000,
+ PMU_VOLT_CAL_MINUS_00_080000_V = -80000,
+ PMU_VOLT_CAL_MINUS_00_060000_V = -60000,
+ PMU_VOLT_CAL_MINUS_00_040000_V = -40000,
+ PMU_VOLT_CAL_MINUS_00_020000_V = -20000,
+ PMU_VOLT_CAL_00_000000_V = 0,
+ PMU_VOLT_CAL_00_020000_V = 20000,
+ PMU_VOLT_CAL_00_040000_V = 40000,
+ PMU_VOLT_CAL_00_060000_V = 60000,
+ PMU_VOLT_CAL_00_080000_V = 80000,
+ PMU_VOLT_CAL_00_100000_V = 100000,
+ PMU_VOLT_CAL_00_120000_V = 120000,
+ PMU_VOLT_CAL_00_140000_V = 140000,
+ PMU_VOLT_CAL_00_160000_V = 160000,
+ PMU_VOLT_CAL_MAX,
+ PMU_VOLT_CAL_INVALID
+} PMU_VOLTAGE_CALIBRATION_ENUM;
+
+/* Enum of SPK db List */
+typedef enum
+{
+ PMIC_SPK_VOL_00_00_dB = 0,
+ PMIC_SPK_VOL_00_50_dB = 50,
+ PMIC_SPK_VOL_01_00_dB = 100,
+ PMIC_SPK_VOL_01_50_dB = 150,
+ PMIC_SPK_VOL_02_00_dB = 200,
+ PMIC_SPK_VOL_02_50_dB = 250,
+ PMIC_SPK_VOL_03_00_dB = 300,
+ PMIC_SPK_VOL_03_50_dB = 350,
+ PMIC_SPK_VOL_04_00_dB = 400,
+ PMIC_SPK_VOL_04_50_dB = 450,
+ PMIC_SPK_VOL_05_00_dB = 500,
+ PMIC_SPK_VOL_05_50_dB = 550,
+ PMIC_SPK_VOL_06_00_dB = 600,
+ PMIC_SPK_VOL_06_50_dB = 650,
+ PMIC_SPK_VOL_07_00_dB = 700,
+ PMIC_SPK_VOL_07_50_dB = 750,
+ PMIC_SPK_VOL_08_00_dB = 800,
+ PMIC_SPK_VOL_08_50_dB = 850,
+ PMIC_SPK_VOL_09_00_dB = 900,
+ PMIC_SPK_VOL_09_50_dB = 950,
+ PMIC_SPK_VOL_10_00_dB = 1000,
+ PMIC_SPK_VOL_10_50_dB = 1050,
+ PMIC_SPK_VOL_11_00_dB = 1100,
+ PMIC_SPK_VOL_11_50_dB = 1150,
+ PMIC_SPK_VOL_12_00_dB = 1200,
+ PMIC_SPK_VOL_12_50_dB = 1250,
+ PMIC_SPK_VOL_13_00_dB = 1300,
+ PMIC_SPK_VOL_13_50_dB = 1350,
+ PMIC_SPK_VOL_14_00_dB = 1400,
+ PMIC_SPK_VOL_14_50_dB = 1450,
+ PMIC_SPK_VOL_15_00_dB = 1500,
+ PMIC_SPK_VOL_15_50_dB = 1550,
+ PMIC_SPK_VOL_16_00_dB = 1600,
+ PMIC_SPK_VOL_16_50_dB = 1650,
+ PMIC_SPK_VOL_17_00_dB = 1700,
+ PMIC_SPK_VOL_17_50_dB = 1750,
+ PMIC_SPK_VOL_18_00_dB = 1800,
+ PMIC_SPK_VOL_18_50_dB = 1850,
+ PMIC_SPK_VOL_19_00_dB = 1900,
+ PMIC_SPK_VOL_19_50_dB = 1950,
+ PMIC_SPK_VOL_20_00_dB = 2000,
+ PMIC_SPK_VOL_20_50_dB = 2050,
+ PMIC_SPK_VOL_21_00_dB = 2100,
+ PMIC_SPK_VOL_21_50_dB = 2150,
+ PMIC_SPK_VOL_22_00_dB = 2200,
+ PMIC_SPK_VOL_22_50_dB = 2250,
+ PMIC_SPK_VOL_23_00_dB = 2300,
+ PMIC_SPK_VOL_23_50_dB = 2350,
+ PMIC_SPK_VOL_24_00_dB = 2400,
+ PMIC_SPK_VOL_24_50_dB = 2450,
+ PMIC_SPK_VOL_MAX = 9900,
+
+ PMU_SPK_VOL_00_00_dB = 0,
+ PMU_SPK_VOL_00_50_dB = 50,
+ PMU_SPK_VOL_01_00_dB = 100,
+ PMU_SPK_VOL_01_50_dB = 150,
+ PMU_SPK_VOL_02_00_dB = 200,
+ PMU_SPK_VOL_02_50_dB = 250,
+ PMU_SPK_VOL_03_00_dB = 300,
+ PMU_SPK_VOL_03_50_dB = 350,
+ PMU_SPK_VOL_04_00_dB = 400,
+ PMU_SPK_VOL_04_50_dB = 450,
+ PMU_SPK_VOL_05_00_dB = 500,
+ PMU_SPK_VOL_05_50_dB = 550,
+ PMU_SPK_VOL_06_00_dB = 600,
+ PMU_SPK_VOL_06_50_dB = 650,
+ PMU_SPK_VOL_07_00_dB = 700,
+ PMU_SPK_VOL_07_50_dB = 750,
+ PMU_SPK_VOL_08_00_dB = 800,
+ PMU_SPK_VOL_08_50_dB = 850,
+ PMU_SPK_VOL_09_00_dB = 900,
+ PMU_SPK_VOL_09_50_dB = 950,
+ PMU_SPK_VOL_10_00_dB = 1000,
+ PMU_SPK_VOL_10_50_dB = 1050,
+ PMU_SPK_VOL_11_00_dB = 1100,
+ PMU_SPK_VOL_11_50_dB = 1150,
+ PMU_SPK_VOL_12_00_dB = 1200,
+ PMU_SPK_VOL_12_50_dB = 1250,
+ PMU_SPK_VOL_13_00_dB = 1300,
+ PMU_SPK_VOL_13_50_dB = 1350,
+ PMU_SPK_VOL_14_00_dB = 1400,
+ PMU_SPK_VOL_14_50_dB = 1450,
+ PMU_SPK_VOL_15_00_dB = 1500,
+ PMU_SPK_VOL_15_50_dB = 1550,
+ PMU_SPK_VOL_16_00_dB = 1600,
+ PMU_SPK_VOL_16_50_dB = 1650,
+ PMU_SPK_VOL_17_00_dB = 1700,
+ PMU_SPK_VOL_17_50_dB = 1750,
+ PMU_SPK_VOL_18_00_dB = 1800,
+ PMU_SPK_VOL_18_50_dB = 1850,
+ PMU_SPK_VOL_19_00_dB = 1900,
+ PMU_SPK_VOL_19_50_dB = 1950,
+ PMU_SPK_VOL_20_00_dB = 2000,
+ PMU_SPK_VOL_20_50_dB = 2050,
+ PMU_SPK_VOL_21_00_dB = 2100,
+ PMU_SPK_VOL_21_50_dB = 2150,
+ PMU_SPK_VOL_22_00_dB = 2200,
+ PMU_SPK_VOL_22_50_dB = 2250,
+ PMU_SPK_VOL_23_00_dB = 2300,
+ PMU_SPK_VOL_23_50_dB = 2350,
+ PMU_SPK_VOL_24_00_dB = 2400,
+ PMU_SPK_VOL_24_50_dB = 2450,
+ PMU_SPK_VOL_MAX = 9900
+}PMU_SPK_VOL_ENUM;
+
+/* Enum of charger current List */
+typedef enum
+{
+ PMU_CHARGE_CURRENT_0_00_MA = 0,
+ PMU_CHARGE_CURRENT_50_00_MA = 5000,
+ PMU_CHARGE_CURRENT_62_50_MA = 6250,
+ PMU_CHARGE_CURRENT_70_00_MA = 7000,
+ PMU_CHARGE_CURRENT_75_00_MA = 7500,
+ PMU_CHARGE_CURRENT_87_50_MA = 8750,
+ PMU_CHARGE_CURRENT_100_00_MA = 10000,
+ PMU_CHARGE_CURRENT_150_00_MA = 15000,
+ PMU_CHARGE_CURRENT_200_00_MA = 20000,
+ PMU_CHARGE_CURRENT_225_00_MA = 22500,
+ PMU_CHARGE_CURRENT_250_00_MA = 25000,
+ PMU_CHARGE_CURRENT_300_00_MA = 30000,
+ PMU_CHARGE_CURRENT_350_00_MA = 35000,
+ PMU_CHARGE_CURRENT_400_00_MA = 40000,
+ PMU_CHARGE_CURRENT_425_00_MA = 42500,
+ PMU_CHARGE_CURRENT_450_00_MA = 45000,
+ PMU_CHARGE_CURRENT_500_00_MA = 50000,
+ PMU_CHARGE_CURRENT_550_00_MA = 55000,
+ PMU_CHARGE_CURRENT_600_00_MA = 60000,
+ PMU_CHARGE_CURRENT_650_00_MA = 65000,
+ PMU_CHARGE_CURRENT_700_00_MA = 70000,
+ PMU_CHARGE_CURRENT_750_00_MA = 75000,
+ PMU_CHARGE_CURRENT_800_00_MA = 80000,
+ PMU_CHARGE_CURRENT_850_00_MA = 85000,
+ PMU_CHARGE_CURRENT_900_00_MA = 90000,
+ PMU_CHARGE_CURRENT_950_00_MA = 95000,
+ PMU_CHARGE_CURRENT_1000_00_MA = 100000,
+ PMU_CHARGE_CURRENT_1200_00_MA = 120000,
+ PMU_CHARGE_CURRENT_1500_00_MA = 150000,
+ PMU_CHARGE_CURRENT_1800_00_MA = 180000,
+ PMU_CHARGE_CURRENT_2000_00_MA = 200000,
+ PMU_CHARGE_CURRENT_MAX
+}PMU_CHR_CURRENT_ENUM;
+
+
+/* Enum of VPA output select List */
+typedef enum
+{
+ PMU_VPA0,
+ PMU_VPA1,
+ PMU_VPA2,
+ PMU_VPA3,
+ PMU_VPA4,
+ PMU_VPA5,
+ PMU_VPA6,
+ PMU_VPA7
+}PMU_VPA_ENUM;
+
+/* Enum of on select List */
+typedef enum
+{
+ ENABLE_WITH_SRCLKEN = 0,
+ ENABLE_LDO_BUCK_EN_REGISTER = 1
+}PMU_ON_SEL_ENUM;
+
+/* Enum of on select(PMIC) List */
+typedef enum
+{
+ SW_CONTROL = 0,
+ SRCLKEN_CONTROL = 1
+}PMIC_ON_SEL_ENUM;
+
+/* Enum of on control(PMIC) List */
+typedef enum
+{
+ SW_CONTROL_BY_REG = 0,
+ HW_CONTROL = 1
+}PMIC_ON_CTRL_ENUM;
+
+#if defined(MT6320)
+/* Enum of srclken select List */
+typedef enum
+{
+ SRCVOLTEN = 0,
+ SRCLKEN_PERI,
+ SRCLKEN_MD2,
+ SRCVOLTEN_OR_SRCLKEN_PERI,
+ SRCVOLTEN_OR_SRCLKEN_MD2,
+ SRCLKEN_PERI_OR_SRCLKEN_MD2,
+ SRCVOLTEN_OR_SRCLKEN_PERI_OR_SRCLKEN_MD2
+}PMU_SRCLKEN_SEL_ENUM;
+
+#elif defined(MT6325) || defined(MT6328)
+/* Enum of srclken select List */
+typedef enum
+{
+ SRCLKEN_IN0 = 0,
+ SRCLKEN_IN1,
+ SRCLKEN_IN0_OR_SRCLKEN_IN1,
+ SRCLKEN_IN0_AND_SRCLKEN_IN1
+}PMU_SRCLKEN_SEL_ENUM;
+
+#elif defined(MT6351)
+typedef enum
+{
+ SRCLKEN_IN0 = 0,
+ SRCLKEN_IN1,
+ SRCLKEN_IN0_OR_SRCLKEN_IN1,
+ SRCLKEN_IN0_AND_SRCLKEN_IN1,
+ SRCLKEN_IN2,
+ SRCLKEN_IN0_OR_SRCLKEN_IN2,
+ SRCLKEN_IN1_OR_SRCLKEN_IN2,
+ SRCLKEN_IN0_OR_SRCLKEN_IN1_OR_SRCLKEN_IN2
+}PMU_SRCLKEN_SEL_ENUM;
+#else
+/* Enum of srclken select List */
+typedef enum
+{
+ SRCLKEN_IN1_AND_SRCLKEN_IN2 = 0,
+ SRCLKEN_IN1,
+ SRCLKEN_IN2,
+ SRCLKEN_IN1_OR_SRCLKEN_IN2
+}PMU_SRCLKEN_SEL_ENUM;
+#endif
+
+#if defined(MT6328)
+/* Enum of srclken select List */
+typedef enum
+{
+ SRCLKEN_IN0_SEL = 0,
+ SRCLKEN_IN1_SEL,
+ SRCLKEN_IN0_OR_SRCLKEN_IN1_SEL,
+ SRCLKEN_IN0_AND_SRCLKEN_IN1_SEL
+}PMIC_SIGNAL_SEL_ENUM;
+#elif defined(MT6351)
+/* Enum of srclken select List */
+typedef enum
+{
+ SRCLKEN_IN0_SEL = 0,
+ SRCLKEN_IN1_SEL,
+ SRCLKEN_IN0_OR_SRCLKEN_IN1_SEL,
+ SRCLKEN_IN0_AND_SRCLKEN_IN1_SEL,
+ SRCLKEN_IN2_SEL,
+ SRCLKEN_IN0_OR_SRCLKEN_IN2_SEL,
+ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL,
+ SRCLKEN_IN0_OR_SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL
+}PMIC_SIGNAL_SEL_ENUM;
+#else
+/* Enum of srclken select List */
+typedef enum
+{
+ SRCLKEN_IN1_SEL = 0,
+ SRCLKEN_IN2_SEL,
+ SRCLKEN_IN1_OR_SRCLKEN_IN2_SEL,
+ SRCLKEN_IN1_AND_SRCLKEN_IN2_SEL
+}PMIC_SIGNAL_SEL_ENUM;
+#endif
+
+/* Enum of remote sense List */
+typedef enum
+{
+ DEFAULT_LOCAL_SENSE= 0,
+ REMOTE_SENSE = 1
+}PMU_RS_ENUM;
+
+/* Enum of control mode List */
+typedef enum
+{
+ KPLED_PWM_MODE = 0,
+ KPLED_REGISTER_CTRL_MODE = 1
+}PMU_CTRL_KPLED_MODE_ENUM;
+
+/* Enum of control mode List */
+typedef enum
+{
+ LDO_EN_SEL_BY_CONTROLLER = 0, // The LDO is connected to specific controller and can be controlled directly by the controller
+ LDO_EN_SEL_BY_LDO_CON,
+ LDO_EN_SEL_MAX = 0xFF
+}PMU_CTRL_LDO_CTRL_MODE_ENUM;
+
+/* Enum of control LDO/Buck mode List */
+typedef enum
+{
+ BUCK_MODE = 0,
+ LDO_MODE
+}PMU_CTRL_BUCK_LDO_CTRL_MODE_ENUM;
+
+/* Enum of control LDO/Buck MODESET list */
+typedef enum
+{
+ AUTO_MODE = 0,
+ FORCE_PWM_MODE
+}PMU_CTRL_BUCK_LDO_CTRL_MODESET_ENUM;
+
+typedef enum
+{
+ COT_AUTO_MODE = 0,
+ FORCE_COT_MODE
+}PMU_CTRL_BUCK_LDO_CTRL_COT_ENUM;
+
+/* Enum of STB SIO mode List */
+typedef enum
+{
+ HW_ENABLE = 0,
+ SW_ENABLE
+}PMU_CTRL_STB_SIO_CTRL_MODE_ENUM;
+
+/* Enum of kpled sel List */
+typedef enum
+{
+ KPLED_SEL_1_SWITCH = 0,
+ KPLED_SEL_2_SWITCH = 1,
+ KPLED_SEL_3_SWITCH = 2,
+ KPLED_SEL_4_SWITCH = 3,
+ KPLED_SEL_5_SWITCH = 4,
+ KPLED_SEL_6_SWITCH = 5,
+ KPLED_SEL_7_SWITCH = 6,
+ KPLED_SEL_8_SWITCH = 7
+}PMU_CTRL_KPLED_SEL_ENUM;
+
+/* Enum of control mode List */
+typedef enum
+{
+ FLASHLED_PWM_MODE = 0,
+ FLASHLED_REGISTER_CTRL_MODE = 1
+}PMU_CTRL_FLASHLED_MODE_ENUM;
+
+/* Enum of kpled sel List */
+typedef enum
+{
+ FLASHLED_SEL_1_SWITCH = 0,
+ FLASHLED_SEL_2_SWITCH = 1,
+ FLASHLED_SEL_3_SWITCH = 2,
+ FLASHLED_SEL_4_SWITCH = 3,
+ FLASHLED_SEL_5_SWITCH = 4,
+ FLASHLED_SEL_6_SWITCH = 5,
+ FLASHLED_SEL_7_SWITCH = 6,
+ FLASHLED_SEL_8_SWITCH = 7
+}PMU_CTRL_FLASHLED_SEL_ENUM;
+
+/* Enum of wdt interval List */
+typedef enum
+{
+ PMU_CHR_WDT_TD_4SEC = 40,
+ PMU_CHR_WDT_TD_8SEC = 80,
+ PMU_CHR_WDT_TD_16SEC = 160,
+ PMU_CHR_WDT_TD_32SEC = 320,
+ PMU_CHR_WDT_TD_128SEC = 1280,
+ PMU_CHR_WDT_TD_256SEC = 2560,
+ PMU_CHR_WDT_TD_512SEC = 5120,
+ PMU_CHR_WDT_TD_1024SEC = 10240,
+ PMU_CHR_WDT_TD_3000SEC = 30000
+}PMU_CHR_WDT_TD_ENUM;
+
+/* Enum of control mode List */
+typedef enum
+{
+ ISINK_PWM_MODE = 0,
+ ISINK_REGISTER_CTRL_MODE = 1
+}PMU_CTRL_ISINK_MODE_ENUM;
+
+/* Enum of ISINK current List */
+typedef enum
+{
+ ISINK_STEP_04_MA = 4,
+ ISINK_STEP_05_MA = 5,
+ ISINK_STEP_08_MA = 8,
+ ISINK_STEP_10_MA = 10,
+ ISINK_STEP_12_MA = 12,
+ ISINK_STEP_15_MA = 15,
+ ISINK_STEP_16_MA = 16,
+ ISINK_STEP_20_MA = 20,
+ ISINK_STEP_24_MA = 24
+}PMU_CTRL_ISINK_STEP_ENUM;
+
+/* Enum of spk mode List */
+typedef enum{
+ SPK_CLASS_D_MODE = 0,
+ SPK_CLASS_AB_MODE
+}PMU_CTRL_SPK_MODE_ENUM;
+
+/* Enum of spk slew List */
+typedef enum{
+ SPK_SLEW_RATE_2_OVER_4 = 0,
+ SPK_SLEW_RATE_1_OVER_4,
+ SPK_SLEW_RATE_4_OVER_4,
+ SPK_SLEW_RATE_3_OVER_4
+}PMU_CTRL_SPK_SLEW_RATE_ENUM;
+
+/* Enum of spk class D offset calibration pathList */
+typedef enum{
+ SPK_N = 0,
+ SPK_P,
+}PMU_CTRL_SPK_CALI_PATH_ENUM;
+
+/* Enum of control steps List */
+typedef enum{
+ PMU_CTRL_STEP1,
+ PMU_CTRL_STEP2,
+ PMU_CTRL_STEP3,
+ PMU_CTRL_STEP4
+}PMU_CTRL_STEP_ENUM;
+
+/* Enum of PMIC List */
+typedef enum
+{
+ PMIC_MT_6320 = 0x6320,
+ PMIC_MT_6323 = 0x6323,
+ PMIC_MT_6325 = 0x6325,
+ PMIC_MT_6328 = 0x6328,
+ PMIC_MT_6329 = 0x6329,
+ PMIC_MT_6331 = 0x6331,
+ PMIC_MT_6332 = 0x6332,
+ PMIC_MT_6339 = 0x6339,
+ PMIC_CHIP_MAX
+}PMIC_CHIP_LIST_ENUM;
+
+typedef enum
+{
+ PMIC_ECO_E1 = 0,
+ PMIC_ECO_E2,
+ PMIC_ECO_E3,
+ PMIC_ECO_E4,
+ PMIC_ECO_E5,
+ PMIC_ECO_E6,
+ PMIC_ECO_E7,
+ PMIC_ECO_E8,
+ PMIC_ECO_E9,
+ PMIC_ECO_E10,
+}PMU_CTRL_PMIC_ECO_VERSION_ENUM;
+
+typedef enum
+{
+ SW_OP_EN_SHIFT = 0,
+ HW0_OP_EN_SHIFT,
+ HW1_OP_EN_SHIFT,
+ HW2_OP_EN_SHIFT,
+}PMU_LDO_BUCK_OP_EN_SHIFT_ENUM;
+
+typedef enum
+{
+ HW0_OP_CFG_SHIFT = 1,
+ HW1_OP_CFG_SHIFT = 2,
+ HW2_OP_CFG_SHIFT = 3,
+ GO_ON_OP_SHIFT = 8,
+ GO_LP_OP_SHIFT = 9,
+
+}PMU_LDO_BUCK_OP_CFG_SHIFT_ENUM;
+
+typedef enum
+{
+ ON_OFF_MODE = 0,
+ LP_NOLP_MODE,
+}PMU_LDO_BUCK_HW_OP_CFG_MODE_ENUM;
+
+typedef enum
+{
+ MULTI_USER_MODE = 0,
+ LOW_POWER_MODE,
+}PMU_LDO_BUCK_OP_MODE_ENUM;
+
+typedef enum
+{
+ Prefer_ON = 0,
+ Prefer_OFF,
+}PMU_LDO_BUCK_GO_ON_OP_MODE_ENUM;
+
+typedef enum
+{
+ Prefer_LP = 0,
+ Prefer_NO_LP,
+}PMU_LDO_BUCK_GO_LP_OP_MODE_ENUM;
+
+typedef enum
+{
+ PMIC_SRCLKEN_IN0 = 0,
+ PMIC_SRCLKEN_IN1 = 1,
+ PMIC_SRCLKEN_IN2 = 2,
+ PMIC_SRCLKEN_IN3 = 3,
+}PMIC_TOP_SRCLKEN_IN_LIST_ENUM;
+
+typedef enum
+{
+ PMIC_SLEEP_MODE = 0,
+ PMIC_NORMAL_MODE,
+}PMIC_SRCLKEN_IN_EN_ENUM;
+
+typedef enum
+{
+ SW_MODE = 0,
+ HW_MODE,
+}PMIC_SRCLKEN_IN_MODE_ENUM;
+
+
+/* For LDO_BUCK_SET_EN command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_SET_EN;
+
+/* For LDO_BUCK_GET_EN_STATUS command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_GET_EN_STATUS;
+
+/* For LDO_BUCK_GET_QI_MODE command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL mode;
+}PMU_CTRL_LDO_BUCK_GET_QI_MODE;
+
+/* For LDO_BUCK_SET_EN_FORCE command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_SET_EN_FORCE;
+
+/* For LDO_BUCK_SET_THER_SHDN_EN command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_SET_THER_SHDN_EN;
+
+/* For LDO_BUCK_SET_VOLTAGE command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_VOLTAGE_ENUM voltage;
+}PMU_CTRL_LDO_BUCK_SET_VOLTAGE;
+
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 code;
+}PMU_CTRL_LDO_BUCK_GET_VOLTAGE;
+
+/* For LDO_BUCK_GET_VOSEL_CTRL command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMIC_ON_CTRL_ENUM mode;
+}PMU_CTRL_LDO_BUCK_GET_VOSEL_CTRL;
+
+/* For LDO_BUCK_GET_VOSEL command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 code;
+}PMU_CTRL_LDO_BUCK_GET_VOSEL;
+
+/* For LDO_BUCK_GET_VOSEL_ON command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 code;
+}PMU_CTRL_LDO_BUCK_GET_VOSEL_ON;
+
+/* For LDO_BUCK_GET_VOSEL_SLEEP command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 code;
+}PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP;
+
+/* For LDO_BUCK_SET_VOSEL_CTRL command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMIC_ON_CTRL_ENUM mode;
+}PMU_CTRL_LDO_BUCK_SET_VOSEL_CTRL;
+
+/* For LDO_BUCK_SET_VOSEL command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 code;
+}PMU_CTRL_LDO_BUCK_SET_VOSEL;
+
+/* For LDO_BUCK_SET_VOSEL_ON command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 code;
+}PMU_CTRL_LDO_BUCK_SET_VOSEL_ON;
+
+/* For LDO_BUCK_SET_VOSEL_SLEEP command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 code;
+}PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP;
+
+/* For LDO_VTCXO24_SWITCH_SET_EN command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_SET_VTCXO24_SWITCH_EN;
+
+/* For BUCK_SET_FPWM command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_SET_FPWM;
+
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_GET_FPWM;
+
+/* For LDO_BUCK_SET_SLEEP_VOLTAGE command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_VOLTAGE_ENUM sleepVoltage;
+}PMU_CTRL_LDO_BUCK_SET_SLEEP_VOLTAGE;
+
+/* For LDO_BUCK_SET_VOLTAGE_EN command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_VOLTAGE_ENUM voltage;
+}PMU_CTRL_LDO_BUCK_SET_VOLTAGE_EN;
+
+/* For LDO_BUCK_SET_RS command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_RS_ENUM rs;
+}PMU_CTRL_LDO_BUCK_SET_RS;
+
+/* For LDO_BUCK_SET_BURST_THRESHOLD command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 thresholdIdx;
+}PMU_CTRL_LDO_BUCK_SET_BURST_THRESHOLD;
+
+/* For LDO_BUCK_SET_CURRENT_LIMIT command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 currentLimitIdx;
+}PMU_CTRL_LDO_BUCK_SET_CURRENT_LIMIT;
+
+/* For LDO_BUCK_SET_BIAS_CURRENT_CALIBRATION_CODE command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 biasCurrentCalibrationCode;
+}PMU_CTRL_LDO_BUCK_SET_BIAS_CURRENT_CALIBRATION_CODE;
+
+/* For LDO_BUCK_SET_VOLTAGE_CALIBRATION_CODE command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 voltageCalibrationCode;
+}PMU_CTRL_LDO_BUCK_SET_VOLTAGE_CALIBRATION_CODE;
+
+/* For LDO_BUCK_SET_STB_TD command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 delayTimeIdx;
+}PMU_CTRL_LDO_BUCK_SET_STB_TD;
+
+/* For LDO_BUCK_SET_OC_TD command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 deglitchTimeIdx;
+}PMU_CTRL_LDO_BUCK_SET_OC_TD;
+
+/* For LDO_BUCK_SET_OCFB_EN command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_SET_OCFB_EN;
+
+/* For LDO_BUCK_SET_OC_AUTO_OFF command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_SET_OC_AUTO_OFF;
+
+/* For LDO_BUCK_SET_ON_SEL command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_ON_SEL_ENUM onSel;
+}PMU_CTRL_LDO_BUCK_SET_ON_SEL;
+
+/* For LDO_BUCK_SET_SRCLKEN_SEL command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_SRCLKEN_SEL_ENUM SrclkenSel;
+}PMU_CTRL_LDO_BUCK_SET_SRCLKEN_SEL;
+
+/* For LDO_BUCK_SET_SRCLK_EN_SEL command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMIC_SIGNAL_SEL_ENUM sel;
+}PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL;
+
+/* For LDO_BUCK_SET_STB_EN command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_SET_STB_EN;
+
+/* For LDO_BUCK_SET_NDIS_EN command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_SET_NDIS_EN;
+
+/* For LDO_BUCK_SET_VSIM_GPLDO_EN command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_SET_VSIM_GPLDO_EN;
+
+/* For _LDO_BUCK_SET_VSIM2_GPLDO_EN command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_SET_VSIM2_GPLDO_EN;
+
+/* For LDO_BUCK_SET_SIM2_GPIO_EN command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_SET_SIM2_GPIO_EN;
+
+/* For LDO_BUCK_SET_CCI_SRCLKEN command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_SET_CCI_SRCLKEN;
+
+/* For LDO_BUCK_GET_OC_STATUS command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL status;
+}PMU_CTRL_LDO_BUCK_GET_OC_STATUS;
+
+/* For LDO_BUCK_GET_QI_OC_STATUS command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL status;
+}PMU_CTRL_LDO_BUCK_GET_QI_OC_STATUS;
+
+/* For LDO_BUCK_SET_OC_INT_EN. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL oc_int_en;
+}PMU_CTRL_LDO_BUCK_SET_OC_INT_EN;
+
+/* For LDO_BUCK_CLEAR_OC_FLAG. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+}PMU_CTRL_LDO_BUCK_CLEAR_OC_FLAG;
+
+/* For LDO_BUCK_GET_OC_FLAG. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL oc_flag;
+}PMU_CTRL_LDO_BUCK_GET_OC_FLAG;
+
+/* For LDO_BUCK_GET_VOLTAGE_LIST. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ const DCL_UINT32 *pVals;
+ DCL_UINT8 size;
+}PMU_CTRL_LDO_BUCK_GET_VOLTAGE_LIST;
+
+/* For LDO_BUCK_SET_LP_MODE_SET command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET;
+
+/* For LDO_BUCK_SET_LP_SEL command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMIC_ON_SEL_ENUM onSel;
+}PMU_CTRL_LDO_BUCK_SET_LP_SEL;
+
+/* For LDO_BUCK_GET_LP_MODE. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL enable;
+}PMU_CTRL_LDO_BUCK_GET_LP_MODE;
+
+/* For LDO_BUCK_SET_ON_CTRL command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMIC_ON_CTRL_ENUM mode;
+}PMU_CTRL_LDO_BUCK_SET_ON_CTRL;
+
+/* For LDO_BUCK_SET_MODESET command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_CTRL_BUCK_LDO_CTRL_MODESET_ENUM mode;
+}PMU_CTRL_LDO_BUCK_SET_MODESET;
+
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_CTRL_BUCK_LDO_CTRL_COT_ENUM mode;
+}PMU_CTRL_LDO_BUCK_SET_COT;
+
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_CTRL_BUCK_LDO_CTRL_COT_ENUM mode;
+}PMU_CTRL_LDO_BUCK_GET_COT;
+
+/* For LDO_BUCK_SET_EN_CTRL command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMIC_ON_CTRL_ENUM mode;
+}PMU_CTRL_LDO_BUCK_SET_EN_CTRL;
+
+/* For LDO_BUCK_SET_EN_SEL command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMIC_SIGNAL_SEL_ENUM sel;
+}PMU_CTRL_LDO_BUCK_SET_EN_SEL;
+
+/* For LDO_BUCK_SET_SRCLK_MODE_SEL command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMIC_SIGNAL_SEL_ENUM sel;
+}PMU_CTRL_LDO_BUCK_SET_SRCLK_MODE_SEL;
+
+/* For LDO_BUCK_SET_OP_EN command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL sw_op_en;
+ DCL_BOOL hw0_op_en;
+ DCL_BOOL hw1_op_en;
+ DCL_BOOL hw2_op_en;
+}PMU_CTRL_LDO_BUCK_SET_OP_EN;
+
+/* For LDO_BUCK_CLR_OP_EN command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_BOOL sw_op_en;
+ DCL_BOOL hw0_op_en;
+ DCL_BOOL hw1_op_en;
+ DCL_BOOL hw2_op_en;
+}PMU_CTRL_LDO_BUCK_CLR_OP_EN;
+
+/* For LDO_BUCK_SET_HW_OP_CFG command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_LDO_BUCK_HW_OP_CFG_MODE_ENUM hw0_op_cfg;
+ PMU_LDO_BUCK_HW_OP_CFG_MODE_ENUM hw1_op_cfg;
+ PMU_LDO_BUCK_HW_OP_CFG_MODE_ENUM hw2_op_cfg;
+}PMU_CTRL_LDO_BUCK_SET_HW_OP_CFG;
+
+/* For LDO_BUCK_CLR_HW_OP_CFG command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_LDO_BUCK_HW_OP_CFG_MODE_ENUM hw0_op_cfg;
+ PMU_LDO_BUCK_HW_OP_CFG_MODE_ENUM hw1_op_cfg;
+ PMU_LDO_BUCK_HW_OP_CFG_MODE_ENUM hw2_op_cfg;
+}PMU_CTRL_LDO_BUCK_CLR_HW_OP_CFG;
+
+/* For LDO_BUCK_SET_HW_OP_MODE command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_LDO_BUCK_OP_MODE_ENUM hw0_op_mode;
+ PMU_LDO_BUCK_OP_MODE_ENUM hw1_op_mode;
+ PMU_LDO_BUCK_OP_MODE_ENUM hw2_op_mode;
+}PMU_CTRL_LDO_BUCK_SET_BUCK_HW_OP_MODE;
+
+/* For LDO_BUCK_CLR_HW_OP_MODE command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_LDO_BUCK_OP_MODE_ENUM hw0_op_mode;
+ PMU_LDO_BUCK_OP_MODE_ENUM hw1_op_mode;
+ PMU_LDO_BUCK_OP_MODE_ENUM hw2_op_mode;
+}PMU_CTRL_LDO_BUCK_CLR_BUCK_HW_OP_MODE;
+
+/* For LDO_BUCK_SET_HW_OP_MODE command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_LDO_BUCK_OP_MODE_ENUM hw0_op_mode;
+ PMU_LDO_BUCK_OP_MODE_ENUM hw1_op_mode;
+ PMU_LDO_BUCK_OP_MODE_ENUM hw2_op_mode;
+}PMU_CTRL_LDO_BUCK_SET_HW_OP_MODE;
+
+/* For LDO_BUCK_CLR_HW_OP_MODE command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_LDO_BUCK_OP_MODE_ENUM hw0_op_mode;
+ PMU_LDO_BUCK_OP_MODE_ENUM hw1_op_mode;
+ PMU_LDO_BUCK_OP_MODE_ENUM hw2_op_mode;
+}PMU_CTRL_LDO_BUCK_CLR_HW_OP_MODE;
+
+/* For LDO_BUCK_SET_GO_ON_OP command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_LDO_BUCK_GO_ON_OP_MODE_ENUM mode;
+}PMU_CTRL_LDO_BUCK_SET_GO_ON_OP;
+
+/* For LDO_BUCK_SET_GO_LP_OP command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_LDO_BUCK_GO_LP_OP_MODE_ENUM mode;
+}PMU_CTRL_LDO_BUCK_SET_GO_LP_OP;
+
+/* For LDO_SET_CAL command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ PMU_VOLTAGE_CALIBRATION_ENUM voltage;
+}PMU_CTRL_LDO_SET_CAL;
+
+
+/* For VPA_SET_VOSEL_MAP_EN command. */
+typedef struct
+{
+ PMU_VPA_LIST_ENUM vpa;
+ DCL_BOOL enable;
+}PMU_CTRL_VPA_SET_VOSEL_MAP_EN;
+
+/* For VPA_SET_EN command. */
+typedef struct
+{
+ PMU_VPA_LIST_ENUM vpa;
+ DCL_BOOL enable;
+}PMU_CTRL_VPA_SET_EN;
+
+/* For VPA_SET_VOLTAGE command. */
+typedef struct
+{
+ PMU_VOLTAGE_ENUM voltage;
+ PMU_VPA_ENUM vpaIdx;
+ PMU_VPA_LIST_ENUM vpa;
+}PMU_CTRL_VPA_SET_VOLTAGE;
+
+/* For VPA_CTRL_SEL command. */
+typedef struct
+{
+ DCL_BOOL byPASEL;
+}PMU_CTRL_VPA_CTRL_SEL;
+
+/* For VPA_GET_VOLTAGE_LIST command. */
+typedef struct
+{
+ const DCL_UINT32 *pVoltageList;
+ DCL_UINT32 number;
+}PMU_CTRL_VPA_GET_VOLTAGE_LIST;
+
+/* For VPA_SET_BAT_LOW command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_VPA_SET_BAT_LOW;
+
+/* For VPA_SET_FPWM command. */
+typedef struct
+{
+ PMU_VPA_LIST_ENUM vpa;
+ DCL_BOOL enable;
+}PMU_CTRL_VPA_SET_FPWM;
+
+/* For VPA_SET_VOLTAGE_SELECTION_TABLE command. */
+typedef struct
+{
+ PMU_VPA_ENUM table_entry;
+ PMU_VOLTAGE_ENUM voltage;
+}PMU_CTRL_VPA_SET_VOLTAGE_SELECTION_TABLE;
+
+
+/* For VPA_SET_MAP_SEL command. */
+typedef struct
+{
+ PMU_VPA_ENUM table_entry;
+}PMU_CTRL_VPA_SET_MAP_SEL;
+
+/* For VIBR_SET_DIMMING_ON_DUTY command. */
+typedef struct
+{
+ DCL_UINT16 duty;
+}PMU_CTRL_VIBR_SET_DIMMING_ON_DUTY;
+
+/* For VRF18_SET_FPWM command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_VRF18_SET_FPWM;
+
+/* For VRF18_SET_MODESET command. */
+typedef struct
+{
+ PMIC_VRF18_LIST_ENUM vrf18Idx;
+ DCL_BOOL enable;
+}PMU_CTRL_VRF18_SET_MODESET;
+
+/* For VRF18_SET_BUCK_LDO_MODE command. */
+typedef struct
+{
+ PMIC_VRF18_LIST_ENUM vrf18Idx;
+ PMU_CTRL_BUCK_LDO_CTRL_MODE_ENUM mode;
+}PMU_CTRL_VRF18_SET_BUCK_LDO_MODE;
+
+/* For VRF1_SET_MODESET_CKPDN_SET command. */
+typedef struct
+{
+ DCL_UINT16 regval;
+}PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET;
+
+/* For VRF1_SET_MODESET_CKPDN_CLR command. */
+typedef struct
+{
+ DCL_UINT16 regval;
+}PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR;
+
+/* For VRF1_GET_MODESET_CKPDN command. */
+typedef struct
+{
+ DCL_UINT16 regval;
+}PMU_CTRL_VRF1_GET_MODESET_CKPDN;
+
+/* For SIMLS_SET_SRST_CONF command. */
+typedef struct
+{
+ PMIC_VSIM_LIST_ENUM vsimIdx;
+ DCL_UINT32 regval;
+}PMU_CTRL_SIMLS_SET_SRST_CONF;
+
+/* For SIMLS_SET_SCLK_CONF command. */
+typedef struct
+{
+ PMIC_VSIM_LIST_ENUM vsimIdx;
+ DCL_UINT32 regval;
+}PMU_CTRL_SIMLS_SET_SCLK_CONF;
+
+/* For SIMLS_SET_TDSEL command. */
+typedef struct
+{
+ DCL_UINT32 regval;
+}PMU_CTRL_SIMLS_SET_TDSEL;
+
+/* For SIMAP_SET_TDSEL command. */
+typedef struct
+{
+ DCL_UINT32 regval;
+}PMU_CTRL_SIMAP_SET_TDSEL;
+
+/* For SIMLS_SET_RDSEL command. */
+typedef struct
+{
+ DCL_UINT32 regval;
+}PMU_CTRL_SIMLS_SET_RDSEL;
+
+/* For SIMAP_SET_RDSEL command. */
+typedef struct
+{
+ DCL_UINT32 regval;
+}PMU_CTRL_SIMAP_SET_RDSEL;
+
+/* For OCTL_SET_SIM_AP_SRST command. */
+typedef struct
+{
+ PMIC_VSIM_LIST_ENUM vsimIdx;
+ DCL_UINT32 regval;
+}PMU_CTRL_OCTL_SET_SIM_AP_SRST;
+
+/* For OCTL_SET_SIM_AP_SCLK command. */
+typedef struct
+{
+ PMIC_VSIM_LIST_ENUM vsimIdx;
+ DCL_UINT32 regval;
+}PMU_CTRL_OCTL_SET_SIM_AP_SCLK;
+
+/* For OCTL_SET_SIMLS_SRST command. */
+typedef struct
+{
+ PMIC_VSIM_LIST_ENUM vsimIdx;
+ DCL_UINT32 regval;
+}PMU_CTRL_OCTL_SET_SIMLS_SRST;
+
+/* For OCTL_SET_SIMLS_SCLK command. */
+typedef struct
+{
+ PMIC_VSIM_LIST_ENUM vsimIdx;
+ DCL_UINT32 regval;
+}PMU_CTRL_OCTL_SET_SIMLS_SCLK;
+
+/* For SIM_SET_STB_SIO_MODE command. */
+typedef struct
+{
+ PMIC_VSIM_LIST_ENUM vsimIdx;
+ PMU_CTRL_STB_SIO_CTRL_MODE_ENUM mode;
+}PMU_CTRL_SIM_SET_STB_SIO_MODE;
+
+/* For SIMRST_SET_GPIO_SET command. */
+typedef struct
+{
+ PMIC_VSIM_LIST_ENUM vsimIdx;
+}PMU_CTRL_SIMRST_SET_GPIO_SET;
+
+/* For SIMRST_SET_GPIO_CLR command. */
+typedef struct
+{
+ PMIC_VSIM_LIST_ENUM vsimIdx;
+}PMU_CTRL_SIMRST_SET_GPIO_CLR;
+
+/* For SPK_SET_EN command. */
+typedef struct
+{
+ PMU_SPK_LIST_ENUM spk;
+ DCL_BOOL enable;
+ PMU_CTRL_STEP_ENUM step;
+}PMU_CTRL_SPK_SET_EN;
+
+/* For SPK_SET_MODE command. */
+typedef struct
+{
+ PMU_SPK_LIST_ENUM spk;
+ PMU_CTRL_SPK_MODE_ENUM mode;
+}PMU_CTRL_SPK_SET_MODE;
+
+/* For SPK_GET_MODE command. */
+typedef struct
+{
+ PMU_SPK_LIST_ENUM spk;
+ DCL_UINT16 mode;
+}PMU_CTRL_SPK_GET_MODE;
+
+/* For SPK_SET_SLEW_RATE command. */
+typedef struct
+{
+ PMU_SPK_LIST_ENUM spk;
+ PMU_CTRL_SPK_MODE_ENUM mode;
+}PMU_CTRL_SPK_SET_SLEW_RATE;
+
+/* For SPK_SET_OC_AUTO_OFF command. */
+typedef struct
+{
+ PMU_SPK_LIST_ENUM spk;
+ DCL_BOOL enable;
+}PMU_CTRL_SPK_SET_OC_AUTO_OFF;
+
+/* For SPK_SET_VOL_VALUE command. */
+typedef struct
+{
+ PMU_SPK_LIST_ENUM spk;
+ DCL_UINT16 volValue;
+}PMU_CTRL_SPK_SET_VOL_VALUE;
+
+/* For SPK_GET_VOL_VALUE command. */
+typedef struct
+{
+ PMU_SPK_LIST_ENUM spk;
+ DCL_UINT16 volValue;
+}PMU_CTRL_SPK_GET_VOL_VALUE;
+
+/* For SPK_GET_VOL command. */
+typedef struct
+{
+ PMU_SPK_LIST_ENUM spk;
+ PMU_SPK_VOL_ENUM dbm;
+}PMU_CTRL_SPK_GET_VOL;
+
+/* For SPK_SET_VOL command. */
+typedef struct
+{
+ PMU_SPK_LIST_ENUM spk;
+ PMU_SPK_VOL_ENUM dbm;
+}PMU_CTRL_SPK_SET_VOL;
+
+/* For SPK_SET_CALIBR_EN command. */
+typedef struct
+{
+ PMU_SPK_LIST_ENUM spk;
+ DCL_BOOL enable;
+}PMU_CTRL_SPK_SET_CALIBR_EN;
+
+/* For SPK_SET_CALIBR_SEL command. */
+typedef struct
+{
+ PMU_SPK_LIST_ENUM spk;
+ PMU_CTRL_SPK_CALI_PATH_ENUM path;
+}PMU_CTRL_SPK_SET_CALIBR_SEL;
+
+/* For BL_SET_INIT command. */
+typedef enum
+{
+ BL_VBOOST_VOLTAGE_CONTROLLER_MODE=0,
+ BL_VBOOST_CURRENT_CONVERTER_MODE=1,
+ BL_ISINK_MODE=2,
+ BL_MODE_1=0,
+ BL_MODE_2=1,
+ BL_MODE_3=2,
+ BL_MODE0=0,
+ BL_MODE1=1,
+ BL_MODE2=2,
+ BL_MODE3=3,
+ BL_MODE_NUM
+}PMU_CTRL_BL_MODE_ENUM;
+
+/* For BL_SET_INIT command. */
+typedef struct
+{
+ PMU_CTRL_BL_MODE_ENUM blMode;
+}PMU_CTRL_BL_SET_INIT;
+
+/* For BL_SET_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_BL_SET_EN;
+
+/* For BL_GET_SUPPORT_LEVEL command */
+typedef struct
+{
+ DCL_UINT32 blSupportLevel;
+}PMU_CTRL_BL_GET_SUPPORT_LEVEL;
+
+/* For BL_GET_USE_PWM_MODE command */
+typedef struct
+{
+ DCL_UINT32 blUsePwmQuery;
+}PMU_CTRL_BL_GET_USE_PWM_QUERY;
+
+/* For FLASHLED_SET_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_FLASHLED_SET_EN;
+
+/* For FLASHLED_SET_MODE command. */
+typedef struct
+{
+ PMU_CTRL_FLASHLED_MODE_ENUM mode;
+}PMU_CTRL_FLASHLED_SET_MODE;
+
+/* For FLASHLED_SET_SEL command. */
+typedef struct
+{
+ PMU_CTRL_FLASHLED_SEL_ENUM sel;
+}PMU_CTRL_FLASHLED_SET_SEL;
+
+/* For KPLED_SET_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_KPLED_SET_EN;
+
+/* For KPLED_SET_MODE command. */
+typedef struct
+{
+ PMU_CTRL_KPLED_MODE_ENUM mode;
+}PMU_CTRL_KPLED_SET_MODE;
+
+/* For KPLED_SET_SEL command. */
+typedef struct
+{
+ PMU_CTRL_KPLED_SEL_ENUM sel;
+}PMU_CTRL_KPLED_SET_SEL;
+
+/* For KPLED_SET_FREQUENCY_DIVISION command. */
+typedef struct
+{
+ DCL_UINT16 div;
+}PMU_CTRL_KPLED_SET_FREQUENCY_DIVISION;
+
+/* For KPLED_SET_DIMMING_ON_DUTY command. */
+typedef struct
+{
+ DCL_UINT16 duty;
+}PMU_CTRL_KPLED_SET_DIMMING_ON_DUTY;
+
+/* For CHR_SET_ADC_MEASURE_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_SET_ADC_MEASURE_EN;
+
+/* For CHR_SET_CSDAC_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_SET_CSDAC_EN;
+
+/* For CHR_SET_CHR_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_SET_CHR_EN;
+
+/* For CHR_SET_CHR_FORCE_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_SET_CHR_FORCE_EN;
+
+/* For CHR_GET_CHR_CURRENT command. */
+typedef struct
+{
+ PMU_CHR_CURRENT_ENUM current;
+}PMU_CTRL_CHR_GET_CHR_CURRENT;
+
+/* For CHR_GET_CHR_CURRENT_LIST command. */
+typedef struct
+{
+ const DCL_UINT32 *pCurrentList;
+ DCL_UINT32 number;
+}PMU_CTRL_CHR_GET_CHR_CURRENT_LIST;
+
+/* For CHR_SET_CHR_CURRENT command. */
+typedef struct
+{
+ PMU_CHR_CURRENT_ENUM current;
+}PMU_CTRL_CHR_SET_CHR_CURRENT;
+
+/* For CHR_GET_CHR_DET_STATUS command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_GET_CHR_DET_STATUS;
+
+/* For CHR_GET_CV_DETECTION_STATUS command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_GET_CV_DETECTION_STATUS;
+
+/* For CHR_SET_CV_DETECTION_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_SET_CV_DETECTION_EN;
+
+/* For CHR_SET_CV_DETECTION_VOLTAGE command. */
+typedef struct
+{
+ PMU_VOLTAGE_ENUM voltage;
+}PMU_CTRL_CHR_SET_CV_DETECTION_VOLTAGE;
+
+/* For CHR_GET_IS_BATTERY_ON command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_GET_IS_BATTERY_ON;
+
+/* For CHR_GET_IS_CHR_VALID command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_GET_IS_CHR_VALID;
+
+/* For CHR_SET_WDT_INT_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_SET_WDT_INT_EN;
+
+/* For CHR_SET_WDT_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_SET_WDT_EN;
+
+/* For CHR_SET_WDT_TIMER command. */
+typedef struct
+{
+ PMU_CHR_WDT_TD_ENUM secs;
+}PMU_CTRL_CHR_SET_WDT_TIMER;
+
+/* For CHR_SET_HV_DETECTION_VOLTAGE command. */
+typedef struct
+{
+ PMU_VOLTAGE_ENUM voltage;
+}PMU_CTRL_CHR_SET_HV_DETECTION_VOLTAGE;
+
+/* For CHR_GET_HV_DETECTION_VOLTAGE_LIST command. */
+typedef struct
+{
+ const DCL_UINT32 *pVoltageList;
+ DCL_UINT32 number;
+}PMU_CTRL_CHR_GET_HV_DETECTION_VOLTAGE_LIST;
+
+/* For CHR_SET_VBAT_OV_DETECTION_VOLTAGE command. */
+typedef struct
+{
+ PMU_VOLTAGE_ENUM voltage;
+}PMU_CTRL_CHR_SET_VBAT_OV_DETECTION_VOLTAGE;
+
+/* For CHR_SET_BAT_HT_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_SET_BAT_HT_EN;
+
+/* For CHR_SET_OTG_BVALID_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_SET_OTG_BVALID_EN;
+
+/* For CHR_SET_BC11_PULLUP_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_SET_BC11_PULLUP_EN;
+
+/* For CHR_SET_CV_MODE command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_SET_CV_MODE;
+
+/* For CHR_SET_CSDAC_MODE command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_SET_CSDAC_MODE;
+
+/* For CHR_SET_TRACKING_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_SET_TRACKING_EN;
+
+/* For CHR_SET_HWCV_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_SET_HWCV_EN;
+
+/* For CHR_SET_ULC_DET_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_CHR_SET_ULC_DET_EN;
+
+/* For CHR_SET_LOW_ICH_DB command. */
+typedef struct
+{
+ DCL_UINT16 debounceTime;
+}PMU_CTRL_CHR_SET_LOW_ICH_DB;
+
+/* For CHR_SET_VBAT_CV_CALIBRATION command. */
+typedef struct
+{
+ DCL_INT32 vbat;
+}PMU_CTRL_CHR_SET_VBAT_CV_CALIBRATION;
+
+/* For CHR_GET_CC_DET command. */
+typedef struct
+{
+ DCL_BOOL vbat_cc_det;
+}PMU_CTRL_CHR_GET_CC_DET;
+
+/* For BOOST_SET_EN command. */
+typedef struct
+{
+ PMU_BOOST_LIST_ENUM boost;
+ DCL_BOOL enable;
+}PMU_CTRL_BOOST_SET_EN;
+
+/* For BOOST_SET_CURRENT_LIMIT command. */
+typedef struct
+{
+ PMU_BOOST_LIST_ENUM boost;
+ DCL_BOOL currentLimit;
+}PMU_CTRL_BOOST_SET_CURRENT_LIMIT;
+
+/* For BOOST_SET_CLK_CAL command. */
+typedef struct
+{
+ PMU_BOOST_LIST_ENUM boost;
+ DCL_BOOL clkCal;
+}PMU_CTRL_BOOST_SET_CLK_CAL;
+
+/* For BOOST_SET_SYNC_EN command. */
+typedef struct
+{
+ PMU_BOOST_LIST_ENUM boost;
+ DCL_BOOL enable;
+}PMU_CTRL_BOOST_SET_SYNC_EN;
+
+/* For BOOST_SET_VOLTAGE command. */
+typedef struct
+{
+ PMU_BOOST_LIST_ENUM boost;
+ PMU_VOLTAGE_ENUM voltage;
+}PMU_CTRL_BOOST_SET_VOLTAGE;
+
+/* For BOOST_SET_LEVEL command. */
+typedef struct
+{
+ PMU_BOOST_LIST_ENUM boost;
+ DCL_UINT16 level;
+}PMU_CTRL_BOOST_SET_LEVEL;
+
+/* For ISINK_SET_EN command. */
+typedef struct
+{
+ PMU_ISINK_LIST_ENUM isink;
+ DCL_BOOL enable;
+}PMU_CTRL_ISINK_SET_EN;
+
+/* For ISINK_SET_MODE command. */
+typedef struct
+{
+ PMU_ISINK_LIST_ENUM isink;
+ PMU_CTRL_ISINK_MODE_ENUM mode;
+}PMU_CTRL_ISINK_SET_MODE;
+
+/* For ISINK_SET_STEP command. */
+typedef struct
+{
+ PMU_ISINK_LIST_ENUM isink;
+ PMU_CTRL_ISINK_STEP_ENUM step;
+}PMU_CTRL_ISINK_SET_STEP;
+
+/* For ISINK_SET_STEP command. */
+typedef struct
+{
+ PMU_ISINK_LIST_ENUM isink;
+ DCL_BOOL forceOff;
+}PMU_CTRL_ISINK_SET_FORCE_OFF;
+
+/* For ISINK_SET_DIMMING_ON_DUTY command. */
+typedef struct
+{
+ PMU_ISINK_LIST_ENUM isink;
+ DCL_UINT16 duty;
+}PMU_CTRL_ISINK_SET_DIMMING_ON_DUTY;
+
+/* For ISINK_SET_FREQUENCY_DIVISION command. */
+typedef struct
+{
+ PMU_ISINK_LIST_ENUM isink;
+ DCL_UINT16 div;
+}PMU_CTRL_ISINK_SET_FREQUENCY_DIVISION;
+
+/* For ADC_SET_RQST command. */
+typedef struct
+{
+ DCL_BOOL enable;
+
+}PMU_CTRL_ADC_SET_RQST;
+
+/* For ADC_CLR_RQST command. */
+typedef struct
+{
+ DCL_BOOL enable;
+
+}PMU_CTRL_ADC_CLR_RQST;
+
+/* For ADC_GET_RDY_MD command. */
+typedef struct
+{
+ DCL_BOOL status;
+}PMU_CTRL_ADC_GET_RDY_MD;
+
+/* For ADC_GET_OUT_MD command. */
+typedef struct
+{
+ DCL_UINT32 data;
+}PMU_CTRL_ADC_GET_OUT_MD;
+
+/* For TOP_SET_SRCLKEN_IN_EN command. */
+typedef struct
+{
+ PMIC_TOP_SRCLKEN_IN_LIST_ENUM mod;
+ PMIC_SRCLKEN_IN_EN_ENUM mode;
+}PMU_CTRL_TOP_SET_SRCLKEN_IN_EN;
+
+/* For TOP_SET_SRCLKEN_IN_MODE command. */
+typedef struct
+{
+ PMIC_TOP_SRCLKEN_IN_LIST_ENUM mod;
+ PMIC_SRCLKEN_IN_MODE_ENUM mode;
+}PMU_CTRL_TOP_SET_SRCLKEN_IN_MODE;
+
+/* For DCXO_SET_REGISTER_VALUE command. */
+typedef struct
+{
+ DCL_UINT32 offset;
+ DCL_UINT16 value;
+}PMU_CTRL_DCXO_SET_REGISTER_VALUE;
+
+/* For DCXO_GET_REGISTER_VALUE command. */
+typedef struct
+{
+ DCL_UINT32 offset;
+ DCL_UINT16 value;
+}PMU_CTRL_DCXO_GET_REGISTER_VALUE;
+
+/* For MISC_BLED_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_MISC_SET_BLED_EN;
+
+/* For MISC_RLED_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_MISC_SET_RLED_EN;
+
+/* For MISC_GLED_EN command. */
+typedef struct
+{
+ DCL_BOOL enable;
+}PMU_CTRL_MISC_SET_GLED_EN;
+
+/* For MISC_GET_CID command. */
+typedef struct
+{
+ DCL_UINT32 cid_value;
+}PMU_CTRL_MISC_GET_CID;
+
+/* For MISC_GET_ECO_VERSION command. */
+typedef struct
+{
+ DCL_UINT32 eco_version;
+}PMU_CTRL_MISC_GET_ECO_VERSION;
+
+/* For MISC_GET_HW_VERSION command. */
+typedef struct
+{
+ PMIC_CHIP_LIST_ENUM chip_name;
+ DCL_UINT32 version;
+}PMU_CTRL_MISC_GET_HW_VERSION;
+
+/* For MISC_SET_REGISTER_VALUE command. */
+typedef struct
+{
+ DCL_UINT32 offset;
+ DCL_UINT16 value;
+}PMU_CTRL_MISC_SET_REGISTER_VALUE;
+
+/* For MISC_GET_REGISTER_VALUE command. */
+typedef struct
+{
+ DCL_UINT32 offset;
+ DCL_UINT16 value;
+}PMU_CTRL_MISC_GET_REGISTER_VALUE;
+
+/* internal use for buck and ldo. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+}PMU_CTRL_LDO_BUCK_CTRL;
+
+/* For LDO_BUCK_SET_VOCAL command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 value;
+}PMU_CTRL_LDO_BUCK_SET_VOCAL;
+
+/* For LDO_BUCK_GET_VOCAL command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 value;
+}PMU_CTRL_LDO_BUCK_GET_VOCAL;
+
+/* For LDO_BUCK_SET_VOTRIM command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 value;
+}PMU_CTRL_LDO_BUCK_SET_VOTRIM;
+
+/* For LDO_BUCK_GET_VOTRIM command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 value;
+}PMU_CTRL_LDO_BUCK_GET_VOTRIM;
+
+/* For LDO_BUCK_SET_VPA_OC_SDN_STATUS command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 value;
+}PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_STATUS;
+
+/* For LDO_BUCK_GET_VPA_OC_SDN_STATUS command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 value;
+}PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_STATUS;
+
+/* For LDO_BUCK_SET_VPA_OC_SDN_EN command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 value;
+}PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_EN;
+
+/* For LDO_BUCK_GET_VPA_OC_SDN_EN command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 value;
+}PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_EN;
+
+/* For LDO_BUCK_SET_OP_MODE command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 value;
+}PMU_CTRL_LDO_BUCK_SET_OP_MODE;
+
+/* For LDO_BUCK_SET_VOTER_VOLTAGE command. */
+typedef struct
+{
+ PMU_LDO_BUCK_LIST_ENUM mod;
+ DCL_UINT16 value;
+}PMU_CTRL_LDO_BUCK_SET_VOTER_VOLTAGE;
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+#ifdef __BUILD_DOM__
+/* The PMU Command Parameter Data Structure for Each Command in DCL_CTRL_DATA_T Enum of dcl.h */
+typedef struct
+{
+ PMU_CTRL_LDO_BUCK_CTRL rPMULdoBuckCtrl; /* Data Structure for Internal Use*/
+ PMU_CTRL_LDO_BUCK_SET_EN rPMULdoBuckSetEn; /* Data Structure for LDO_BUCK_SET_EN */
+ PMU_CTRL_LDO_BUCK_GET_EN_STATUS rPMULdoBuckGetEnStatus; /* Data Structure for LDO_BUCK_GET_EN_STATUS */
+ PMU_CTRL_LDO_BUCK_GET_QI_MODE rPMULdoBuckGetQiMode; /* Data Structure for LDO_BUCK_GET_QI_MODE */
+ PMU_CTRL_LDO_BUCK_SET_EN_FORCE rPMULdoBuckSetEnForce; /* Data Structure for LDO_BUCK_SET_EN_FORCE */
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE rPMULdoBuckSetVoltage; /* Data Structure for LDO_BUCK_SET_VOLTAGE */
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE_EN rPMULdoBuckSetVoltageEn; /* Data Structure for LDO_BUCK_SET_VOLTAGE_EN */
+ PMU_CTRL_LDO_BUCK_SET_SLEEP_VOLTAGE rPMULdoBuckSetSleepVoltage; /* Data Structure for LDO_BUCK_SET_SLEEP_VOLTAGE */
+ PMU_CTRL_LDO_BUCK_SET_BURST_THRESHOLD rPMULdoBuckSetBurstThreshold; /* Data Structure for LDO_BUCK_SET_BURST_THRESHOLD */
+ PMU_CTRL_LDO_BUCK_SET_CURRENT_LIMIT rPMULdoBuckSetCurrentLimit; /* Data Structure for LDO_BUCK_SET_CURRENT_LIMIT */
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE_CALIBRATION_CODE rPMULdoBuckSetVoltageCalibrationCode; /* Data Structure for LDO_BUCK_SET_VOLTAGE_CALIBRATION_CODE */
+ PMU_CTRL_LDO_BUCK_SET_BIAS_CURRENT_CALIBRATION_CODE rPMULdoBuckSetBiasCurrentCalibrationCode; /* Data Structure for LDO_BUCK_SET_BIAS_CURRENT_CALIBRATION_CODE */
+ PMU_CTRL_LDO_BUCK_SET_STB_EN rPMULdoBuckSetStbEn; /* Data Structure for LDO_BUCK_SET_STB_EN */
+ PMU_CTRL_LDO_BUCK_SET_OC_AUTO_OFF rPMULdoBuckSetOcAutoOff; /* Data Structure for LDO_BUCK_SET_OC_AUTO_OFF */
+ PMU_CTRL_LDO_BUCK_SET_RS rPMULdoBuckSetRs; /* Data Structure for LDO_BUCK_SET_RS */
+ PMU_CTRL_LDO_BUCK_SET_ON_SEL rPMULdoBuckSetOnSel; /* Data Structure for LDO_BUCK_SET_ON_SEL */
+ PMU_CTRL_LDO_BUCK_SET_SRCLKEN_SEL rPMULdoBuckSetSrclkenSel; /* Data Structure for LDO_BUCK_SET_SRCLKEN_SEL */
+ PMU_CTRL_LDO_BUCK_SET_STB_TD rPMULdoBuckSetStbTd; /* Data Structure for LDO_BUCK_SET_STB_TD */
+ PMU_CTRL_LDO_BUCK_SET_NDIS_EN rPMULdoBuckSetNdisEn; /* Data Structure for LDO_BUCK_SET_NDIS_EN */
+ PMU_CTRL_LDO_BUCK_SET_OC_TD rPMULdoBuckSetOcTd; /* Data Structure for LDO_BUCK_SET_OC_TD */
+ PMU_CTRL_LDO_BUCK_SET_OCFB_EN rPMULdoBuckSetOcfbEn; /* Data Structure for LDO_BUCK_SET_OCFB_EN */
+ PMU_CTRL_LDO_BUCK_SET_VSIM_GPLDO_EN rPMULdoBuckSetVsimGpldoEn; /* Data Structure for LDO_BUCK_SET_VSIM_GPLDO_EN */
+ PMU_CTRL_LDO_BUCK_SET_VSIM2_GPLDO_EN rPMULdoBuckSetVsim2GpldoEn; /* Data Structure for LDO_BUCK_SET_VSIM2_GPLDO_EN */
+ PMU_CTRL_LDO_BUCK_SET_SIM2_GPIO_EN rPMULdoBuckSetSim2GpioEn; /* Data Structure for LDO_BUCK_SET_SIM2_GPIO_EN */
+ PMU_CTRL_LDO_BUCK_SET_CCI_SRCLKEN rPMULdoBuckSetCciSrclken; /* Data Structure for LDO_BUCK_SET_CCI_SRCLKEN */
+ PMU_CTRL_LDO_BUCK_GET_OC_STATUS rPMULdoBuckGetOcStatus; /* Data Structure for LDO_BUCK_GET_OC_STATUS */
+ PMU_CTRL_LDO_BUCK_GET_QI_OC_STATUS rPMULdoBuckGetQiOcStatus; /* Data Structure for LDO_BUCK_GET_QI_OC_STATUS */
+ PMU_CTRL_LDO_BUCK_SET_OC_INT_EN rPMULdoBuckSetOcIntEn; /* Data Structure for LDO_BUCK_SET_OC_INT_EN */
+ PMU_CTRL_LDO_BUCK_CLEAR_OC_FLAG rPMULdoBuckClearOcFlag; /* Data Structure for LDO_BUCK_CLEAR_OC_FLAG */
+ PMU_CTRL_LDO_BUCK_GET_OC_FLAG rPMULdoBuckGetOcFlag; /* Data Structure for LDO_BUCK_GET_OC_FLAG */
+ PMU_CTRL_LDO_BUCK_GET_VOLTAGE_LIST rPMULdoBuckGetVoltageList; /* Data Structure for LDO_BUCK_GET_VOLTAGE_LIST */
+ PMU_CTRL_LDO_BUCK_SET_THER_SHDN_EN rPMULdoBuckSetTherShdnEn; /* Data Structure for LDO_BUCK_SET_THER_SHDN_EN */
+ PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET rPMULdoBuckSetLpModeSet; /* Data Structure for LDO_BUCK_SET_LP_MODE_SET */
+ PMU_CTRL_LDO_BUCK_SET_LP_SEL rPMULdoBuckSetLpSel; /* Data Structure for LDO_BUCK_SET_LP_SEL */
+ PMU_CTRL_LDO_BUCK_GET_LP_MODE rPMULdoBuckGetLpMode; /* Data Structure for LDO_BUCK_GET_LP_MODE */
+ PMU_CTRL_LDO_BUCK_SET_ON_CTRL rPMULdoBuckSetOnCtrl; /* Data Structure for LDO_BUCK_SET_ON_CTRL */
+ PMU_CTRL_LDO_BUCK_SET_MODESET rPMULdoBuckSetModeset; /* Data Structure for LDO_BUCK_SET_MODESET */
+ PMU_CTRL_LDO_BUCK_SET_COT rPMULdoBuckSetCotset; /* Data Structure for LDO_BUCK_SET_COT */
+ PMU_CTRL_LDO_BUCK_GET_COT rPMULdoBuckGetCot; /* Data Structure for LDO_BUCK_SET_COT */
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL rPMULdoBuckSetEnCtrl; /* Data Structure for LDO_BUCK_SET_EN_CTRL */
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL rPMULdoBuckSetEnSel; /* Data Structure for LDO_BUCK_SET_EN_SEL */
+ PMU_CTRL_LDO_BUCK_SET_SRCLK_MODE_SEL rPMULdoBuckSetSrclkModeSel; /* Data Structure for LDO_BUCK_SET_SRCLK_MODE_SEL */
+ PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL rPMULdoBuckSetSrclkEnSel; /* Data Structure for LDO_BUCK_SET_SRCLK_EN_SEL */
+ PMU_CTRL_LDO_SET_CAL rPMULdoSetCal; /* Data Structure for LDO_SET_CAL */
+ PMU_CTRL_LDO_BUCK_GET_VOLTAGE rPMULdoBuckGetVolt; /* Data structure for PMU_CTRL_LDO_BUCK_GET_VOLTAGE */
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_CTRL rPMULdoBuckGetVoselCtrl; /* Data structure for PMU_CTRL_LDO_BUCK_GET_VOSEL_CTRL */
+ PMU_CTRL_LDO_BUCK_GET_VOSEL rPMULdoBuckGetVosel; /* Data structure for PMU_CTRL_LDO_BUCK_GET_VOSEL */
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_ON rPMULdoBuckGetVoselOn; /* Data structure for PMU_CTRL_LDO_BUCK_GET_VOSEL_ON */
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP rPMULdoBuckGetVoselSleep; /* Data structure for PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP */
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_CTRL rPMULdoBuckSetVoselCtrl; /* Data structure for PMU_CTRL_LDO_BUCK_SET_VOSEL_CTRL */
+ PMU_CTRL_LDO_BUCK_SET_VOSEL rPMULdoBuckSetVosel; /* Data structure for PMU_CTRL_LDO_BUCK_SET_VOSEL */
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_ON rPMULdoBuckSetVoselOn; /* Data structure for PMU_CTRL_LDO_BUCK_SET_VOSEL_ON */
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP rPMULdoBuckSetVoselSleep; /* Data structure for PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP */
+ PMU_CTRL_LDO_SET_VTCXO24_SWITCH_EN rPMULdoBuckSetVtcxoSwith; /* Data structure for PMU_CTRL_LDO_VTCXO24_SWITCH_SET_EN */
+ PMU_CTRL_LDO_BUCK_SET_FPWM rPMULdoBuckSetFpwm; /* Data structure for BUCK SET FPWM */
+ PMU_CTRL_LDO_BUCK_GET_FPWM rPMULdoBuckGetFpwm; /* Data structure for BUCK GET FPWM */
+ PMU_CTRL_VPA_SET_VOSEL_MAP_EN rPMUVpaSetVoselMapEn; /* Data Structure for VPA_SET_VOSEL_MAP_EN */
+ PMU_CTRL_VPA_SET_EN rPMUVpaSetEn; /* Data Structure for VPA_SET_EN */
+ PMU_CTRL_VPA_SET_VOLTAGE rPMUVpaSetVoltage; /* Data Structure for VPA_SET_VOLTAGE */
+ PMU_CTRL_VPA_CTRL_SEL rPMUVpaCtrlSel; /* Data Structure for VPA_CTRL_SEL */
+ PMU_CTRL_VPA_GET_VOLTAGE_LIST rPMUVpaGetVoltageList; /* Data Structure for VPA_GET_VOLTAGE_LIST */
+ PMU_CTRL_VPA_SET_BAT_LOW rPMUVpaSetBatLow; /* Data Structure for VPA_SET_BAT_LOW */
+ PMU_CTRL_VPA_SET_FPWM rPMUVpaSetFpwm; /* Data Structure for VPA_SET_FPWM */
+ PMU_CTRL_VPA_SET_VOLTAGE_SELECTION_TABLE rPMUVpaSetVoltageSelectionTable; /* Data Structure for VPA_SET_VOLTAGE_SELECTION_TABLE */
+ PMU_CTRL_VPA_SET_MAP_SEL rPMUVpaSetMapSel; /* Data Structure for VPA_SET_MAP_SEL */
+ PMU_CTRL_VIBR_SET_DIMMING_ON_DUTY rPMUVibrSetDimmingOnDuty; /* Data Structure for VIBR_SET_DIMMING_ON_DUTY */
+ PMU_CTRL_VRF18_SET_FPWM rPMUVrf18SetFpwm; /* Data Structure for VRF18_SET_FPWM */
+ PMU_CTRL_VRF18_SET_MODESET rPMUVrf18SetModeset; /* Data Structure for VRF18_SET_FPWM */
+ PMU_CTRL_VRF18_SET_BUCK_LDO_MODE rPMUVrf18SetBuckLdoMode; /* Data Structure for VRF18_SET_BUCK_LDO_MODE */
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET rPMUVrf1SetModesetCkpdnSet; /* Data Structure for VRF1_SET_MODESET_CKPDN_SET */
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR rPMUVrf1SetModesetCkpdnClr; /* Data Structure for VRF1_SET_MODESET_CKPDN_CLR */
+ PMU_CTRL_VRF1_GET_MODESET_CKPDN rPMUVrf1GetModesetCkpdn; /* Data Structure for VRF1_GET_MODESET_CKPDN */
+ PMU_CTRL_SIMLS_SET_SRST_CONF rPMUSimlsSetSrstConf; /* Data Structure for SIMLS_SET_SRST_CONF */
+ PMU_CTRL_SIMLS_SET_SCLK_CONF rPMUSimlsSetSclkConf; /* Data Structure for SIMLS_SET_SCLK_CONF */
+ PMU_CTRL_SIMLS_SET_TDSEL rPMUSimlsSetTdsel; /* Data Structure for SIMLS_SET_TDSEL */
+ PMU_CTRL_SIMAP_SET_TDSEL rPMUSimapSetTdsel; /* Data Structure for SIMAP_SET_TDSEL */
+ PMU_CTRL_SIMLS_SET_RDSEL rPMUSimlsSetRdsel; /* Data Structure for SIMLS_SET_RDSEL */
+ PMU_CTRL_SIMAP_SET_RDSEL rPMUSimapSetRdsel; /* Data Structure for SIMAP_SET_RDSEL */
+ PMU_CTRL_SIM_SET_STB_SIO_MODE rPMUSimSetStbSioMode; /* Data Structure for SIM_SET_STB_SIO_MODE */
+ PMU_CTRL_SIMRST_SET_GPIO_SET rPMUSimrstSetGpioSet; /* Data Structure for SIMRST_SET_GPIO_SET */
+ PMU_CTRL_SIMRST_SET_GPIO_CLR rPMUSimrstSetGpioClr; /* Data Structure for SIMRST_SET_GPIO_CLR */
+ PMU_CTRL_OCTL_SET_SIM_AP_SRST rPMUOctlSetSimApSrst; /* Data Structure for OCTL_SET_SIM_AP_SRST */
+ PMU_CTRL_OCTL_SET_SIM_AP_SCLK rPMUOctlSetSimApSclk; /* Data Structure for OCTL_SET_SIM_AP_SCLK */
+ PMU_CTRL_OCTL_SET_SIMLS_SRST rPMUOctlSetSimlsSrst; /* Data Structure for OCTL_SET_SIMLS_SRST */
+ PMU_CTRL_OCTL_SET_SIMLS_SCLK rPMUOctlSetSimlsSclk; /* Data Structure for OCTL_SET_SIMLS_SCLK */
+ PMU_CTRL_SPK_SET_EN rPMUSpkSetEn; /* Data Structure for SPK_SET_EN */
+ PMU_CTRL_SPK_SET_MODE rPMUSpkSetMode; /* Data Structure for SPK_SET_MODE */
+ PMU_CTRL_SPK_GET_MODE rPMUSpkGetMode; /* Data Structure for SPK_GET_MODE */
+ PMU_CTRL_SPK_SET_OC_AUTO_OFF rPMUSpkSetOcAutoOff; /* Data Structure for SPK_SET_OC_AUTO_OFF */
+ PMU_CTRL_SPK_SET_VOL_VALUE rPMUSpkSetVolValue; /* Data Structure for SPK_SET_VOL_VALUE */
+ PMU_CTRL_SPK_GET_VOL_VALUE rPMUSpkGetVolValue; /* Data Structure for SPK_GET_VOL_VALUE */
+ PMU_CTRL_SPK_SET_VOL rPMUSpkSetVol; /* Data Structure for SPK_SET_VOL */
+ PMU_CTRL_SPK_GET_VOL rPMUSpkGetVol; /* Data Structure for SPK_GET_VOL */
+ PMU_CTRL_SPK_SET_SLEW_RATE rPMUSpkSetSlewRate; /* Data Structure for SPK_SET_SLEW_RATE */
+ PMU_CTRL_SPK_SET_CALIBR_EN rPMUSpkSetCalibrEn; /* Data Structure for SPK_SET_CALIBR_EN */
+ PMU_CTRL_SPK_SET_CALIBR_SEL rPMUSpkSetCalibrSel; /* Data Structure for SPK_SET_CALIBR_SEL */
+ PMU_CTRL_FLASHLED_SET_EN rPMUFlashledSetEn; /* Data Structure for FLASHLED_SET_EN */
+ PMU_CTRL_FLASHLED_SET_MODE rPMUFlashledSetMode; /* Data Structure for FLASHLED_SET_MODE */
+ PMU_CTRL_FLASHLED_SET_SEL rPMUFlashledSetSel; /* Data Structure for FLASHLED_SET_SEL */
+ PMU_CTRL_KPLED_SET_EN rPMUKpledSetEn; /* Data Structure for KPLED_SET_EN */
+ PMU_CTRL_KPLED_SET_MODE rPMUKpledSetMode; /* Data Structure for KPLED_SET_MODE */
+ PMU_CTRL_KPLED_SET_SEL rPMUKpledSetSel; /* Data Structure for KPLED_SET_SEL */
+ PMU_CTRL_KPLED_SET_FREQUENCY_DIVISION rPMUKpledSetFrequencyDivision; /* Data Structure for KPLED_SET_FREQUENCY_DIVISION */
+ PMU_CTRL_KPLED_SET_DIMMING_ON_DUTY rPMUKpledSetDimmingOnDuty; /* Data Structure for KPLED_SET_DIMMING_ON_DUTY */
+ PMU_CTRL_CHR_SET_ADC_MEASURE_EN rPMUChrSetAdcMeasureEn; /* Data Structure for CHR_SET_ADC_MEASURE_EN */
+ PMU_CTRL_CHR_SET_WDT_TIMER rPMUChrSetWdtTimer; /* Data Structure for CHR_SET_WDT_TIMER */
+ PMU_CTRL_CHR_SET_WDT_INT_EN rPMUChrSetWdtIntEn; /* Data Structure for CHR_SET_WDT_INT_EN */
+ PMU_CTRL_CHR_SET_WDT_EN rPMUChrSetWdtEn; /* Data Structure for CHR_SET_WDT_EN */
+ PMU_CTRL_CHR_SET_CHR_EN rPMUChrSetChrEn; /* Data Structure for CHR_SET_CHR_EN */
+ PMU_CTRL_CHR_SET_CHR_FORCE_EN rPMUChrSetChrForceEn; /* Data Structure for CHR_SET_CHR_FORCE_EN */
+ PMU_CTRL_CHR_GET_CHR_DET_STATUS rPMUChrGetChrDetStatus; /* Data Structure for CHR_GET_CHR_DET_STATUS */
+ PMU_CTRL_CHR_GET_CHR_CURRENT rPMUChrGetChrCurrent; /* Data Structure for CHR_GET_CHR_CURRENT */
+ PMU_CTRL_CHR_GET_CHR_CURRENT_LIST rPMUChrGetChrCurrentList; /* Data Structure for CHR_GET_CHR_CURRENT_LIST */
+ PMU_CTRL_CHR_SET_CHR_CURRENT rPMUChrSetChrCurrent; /* Data Structure for CHR_SET_CHR_CURRENT */
+ PMU_CTRL_CHR_GET_CV_DETECTION_STATUS rPMUChrGetCvDetectionStatus; /* Data Structure for CHR_GET_CV_DETECTION_STATUS */
+ PMU_CTRL_CHR_SET_CV_DETECTION_EN rPMUChrSetCvDetectionEn; /* Data Structure for CHR_SET_CV_DETECTION_EN */
+ PMU_CTRL_CHR_SET_CV_DETECTION_VOLTAGE rPMUChrSetCvDetectionVoltage; /* Data Structure for CHR_SET_CV_DETECTION_VOLTAGE */
+ PMU_CTRL_CHR_SET_CSDAC_EN rPMUChrSetCsdacEn; /* Data Structure for CHR_SET_CSDAC_EN */
+ PMU_CTRL_CHR_GET_IS_BATTERY_ON rPMUChrGetIsBatteryOn; /* Data Structure for CHR_GET_IS_BATTERY_ON */
+ PMU_CTRL_CHR_GET_IS_CHR_VALID rPMUChrGetIsChrValid; /* Data Structure for CHR_GET_IS_CHR_VALID */
+ PMU_CTRL_CHR_SET_HV_DETECTION_VOLTAGE rPMUChrSetHvDetectionVoltage; /* Data Structure for CHR_SET_HV_DETECTION_VOLTAGE */
+ PMU_CTRL_CHR_GET_HV_DETECTION_VOLTAGE_LIST rPMUChrGetHvDetectionVoltageList; /* Data Structure for CHR_GET_HV_DETECTION_VOLTAGE_LIST */
+ PMU_CTRL_CHR_SET_VBAT_OV_DETECTION_VOLTAGE rPMUChrSetVbatOvDetectionVoltage; /* Data Structure for CHR_SET_VBAT_OV_DETECTION_VOLTAGE */
+ PMU_CTRL_CHR_SET_BAT_HT_EN rPMUChrSetBatHtEn; /* Data Structure for CHR_SET_BAT_HT_EN */
+ PMU_CTRL_CHR_SET_OTG_BVALID_EN rPMUChrSetOtgBvalidEn; /* Data Structure for CHR_SET_OTG_BVALID_EN */
+ PMU_CTRL_CHR_SET_CV_MODE rPMUChrSetCvMode; /* Data Structure for CHR_SET_CV_MODE */
+ PMU_CTRL_CHR_SET_CSDAC_MODE rPMUChrSetCsdacMode; /* Data Structure for CHR_SET_CSDAC_MODE */
+ PMU_CTRL_CHR_SET_TRACKING_EN rPMUChrSetTrackingEn; /* Data Structure for CHR_SET_TRACKING_EN */
+ PMU_CTRL_CHR_SET_HWCV_EN rPMUChrSetHwcvEn; /* Data Structure for CHR_SET_HWCV_EN */
+ PMU_CTRL_CHR_SET_ULC_DET_EN rPMUChrSetUlcDetEn; /* Data Structure for CHR_SET_ULC_DET_EN */
+ PMU_CTRL_CHR_SET_BC11_PULLUP_EN rPMUChrSetBc11PullupEn; /* Data Structure for CHR_SET_BC11_PULLUP_EN */
+ PMU_CTRL_CHR_SET_LOW_ICH_DB rPMUChrSetLowIchDb; /* Data Structure for CHR_SET_LOW_ICH_DB */
+ PMU_CTRL_CHR_SET_VBAT_CV_CALIBRATION rPMUChrSetVbatCvCalibration; /* Data Structure for CHR_SET_VBAT_CV_CALIBRATION */
+ PMU_CTRL_CHR_GET_CC_DET rPMUChrGetCcDet; /* Data Structure for CHR_GET_CC_DET */
+ PMU_CTRL_BL_SET_EN rPMUBlSetEn; /* Data Structure for BL_SET_EN */
+ PMU_CTRL_BL_SET_INIT rPMUBlSetInit; /* Data Structure for BL_SET_INIT */
+ PMU_CTRL_BL_GET_SUPPORT_LEVEL rPMUBlGetSupportLevel; /* Data Structure for BL_GET_SUPPPORT_LEVEL */
+ PMU_CTRL_BL_GET_USE_PWM_QUERY rPMUBlGetUsePwmQuery; /* Data Structure for BL_GET_USE_PWM_QUERY */
+ PMU_CTRL_BOOST_SET_EN rPMUBoostSetEn; /* Data Structure for BOOST_SET_EN */
+ PMU_CTRL_BOOST_SET_CURRENT_LIMIT rPMUBoostSetCurrentLimit; /* Data Structure for BOOST_SET_CURRENT_LIMIT */
+ PMU_CTRL_BOOST_SET_CLK_CAL rPMUBoostSetClkCal; /* Data Structure for BOOST_SET_CLK_CAL */
+ PMU_CTRL_BOOST_SET_SYNC_EN rPMUBoostSetSyncEn; /* Data Structure for BOOST_SET_SYNC_EN */
+ PMU_CTRL_BOOST_SET_VOLTAGE rPMUBoostSetVoltage; /* Data Structure for BOOST_SET_VOLTAGE */
+ PMU_CTRL_BOOST_SET_LEVEL rPMUBoostSetLevel; /* Data Structure for BOOST_SET_LEVEL */
+ PMU_CTRL_ISINK_SET_EN rPMUIsinkSetEn; /* Data Structure for ISINK_SET_EN */
+ PMU_CTRL_ISINK_SET_MODE rPMUIsinkSetMode; /* Data Structure for ISINK_SET_MODE */
+ PMU_CTRL_ISINK_SET_STEP rPMUIsinkSetStep; /* Data Structure for ISINK_SET_STEP */
+ PMU_CTRL_ISINK_SET_FORCE_OFF rPMUIsinkSetForceOff; /* Data Structure for ISINK_SET_FORCE_OFF */
+ PMU_CTRL_ISINK_SET_DIMMING_ON_DUTY rPMUIsinkSetDimmingOnDuty; /* Data Structure for ISINK_SET_DIMMING_ON_DUTY */
+ PMU_CTRL_ISINK_SET_FREQUENCY_DIVISION rPMUIsinkSetFrequencyDivision; /* Data Structure for ISINK_SET_FREQUENCY_DIVISION */
+ PMU_CTRL_ADC_SET_RQST rPMUAdcSetRqst; /* Data Structure for ADC_SET_RQST */
+ PMU_CTRL_ADC_CLR_RQST rPMUAdcClrRqst; /* Data Structure for ADC_CLR_RQST */
+ PMU_CTRL_ADC_GET_RDY_MD rPMUAdcGetRdyMd; /* Data Structure for ADC_GET_RDY_MD */
+ PMU_CTRL_ADC_GET_OUT_MD rPMUAdcGetOutMd; /* Data Structure for ADC_GET_OUT_MD */
+ PMU_CTRL_MISC_SET_RLED_EN rPMUMiscSetRledEn; /* Data Structure for MISC_SET_RLED_EN */
+ PMU_CTRL_MISC_SET_GLED_EN rPMUMiscSetGledEn; /* Data Structure for MISC_SET_GLED_EN */
+ PMU_CTRL_MISC_SET_BLED_EN rPMUMiscSetBledEn; /* Data Structure for MISC_SET_BLED_EN */
+ PMU_CTRL_MISC_GET_CID rPMUMiscGetCid; /* Data Structure for MISC_GET_CID */
+ PMU_CTRL_MISC_GET_ECO_VERSION rPMUMiscGetEcoVersion; /* Data Structure for MISC_GET_ECO_VERSION */
+ PMU_CTRL_MISC_GET_HW_VERSION rPMUMiscGetHwVersion; /* Data Structure for MISC_GET_HW_VERISON */
+ PMU_CTRL_MISC_SET_REGISTER_VALUE rPMUMiscSetRegisterValue; /* Data Structure for MISC_SET_REGISTER_VALUE */
+ PMU_CTRL_MISC_GET_REGISTER_VALUE rPMUMiscGetRegisterValue; /* Data Structure for MISC_GET_REGISTER_VALUE */
+ PMU_CTRL_LDO_BUCK_SET_OP_EN rPMULdoBuckSetOpEn;
+ PMU_CTRL_LDO_BUCK_CLR_OP_EN rPMULdoBuckClrOpEn;
+ PMU_CTRL_LDO_BUCK_SET_HW_OP_CFG rPMULdoBuckSetHwOp;
+ PMU_CTRL_LDO_BUCK_CLR_HW_OP_CFG rPMULdoBuckClrHwOp;
+ PMU_CTRL_LDO_BUCK_SET_GO_ON_OP rPMULdoBuckSetGoOnOp;
+ PMU_CTRL_LDO_BUCK_SET_GO_LP_OP rPMULdoBuckSetGoLpOp;
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_EN rPMUTopSetSrclkenInEn;
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_MODE rPMUTopSetSrclkenInMode;
+ PMU_CTRL_DCXO_SET_REGISTER_VALUE rPMUDcxoSetRegisterValue;
+ PMU_CTRL_DCXO_GET_REGISTER_VALUE rPMUDcxoGetRegisterValue;
+ PMU_CTRL_LDO_BUCK_SET_VOCAL rPMULdoBuckSetVocal;
+ PMU_CTRL_LDO_BUCK_GET_VOCAL rPMULdoBuckGetVocal;
+ PMU_CTRL_LDO_BUCK_SET_VOTRIM rPMULdoBuckSetVotrim;
+ PMU_CTRL_LDO_BUCK_GET_VOTRIM rPMULdoBuckGetVotrim;
+ PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_STATUS rPMULdoBuckSetVpaOcSdnStatus;
+ PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_STATUS rPMULdoBuckGetVpaOcSdnStatus;
+ PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_EN rPMULdoBuckSetVpaOcSdnEn;
+ PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_EN rPMULdoBuckGetVpaOcSdnEn;
+ PMU_CTRL_LDO_BUCK_SET_OP_MODE rPMULdoBuckSetOpMode;
+ PMU_CTRL_LDO_BUCK_SET_VOTER_VOLTAGE rPMULdoBuckSetVoterVoltage;
+ PMU_CTRL_LDO_BUCK_SET_BUCK_HW_OP_MODE rPMULdoBuckSetBuckHwOpMode;
+ PMU_CTRL_LDO_BUCK_CLR_BUCK_HW_OP_MODE rPMULdoBuckClrBuckHwOpMode;
+ PMU_CTRL_LDO_BUCK_SET_HW_OP_MODE rPMULdoBuckSetHwOpMode;
+ PMU_CTRL_LDO_BUCK_CLR_HW_OP_MODE rPMULdoBuckClrHwOpMode;
+
+}PMU_CTRL_DATA;
+#else /* __BUILD_DOM__ */
+#define PMU_CTRLS \
+ PMU_CTRL_LDO_BUCK_CTRL rPMULdoBuckCtrl; \
+ PMU_CTRL_LDO_BUCK_SET_EN rPMULdoBuckSetEn; \
+ PMU_CTRL_LDO_BUCK_GET_EN_STATUS rPMULdoBuckGetEnStatus; \
+ PMU_CTRL_LDO_BUCK_GET_QI_MODE rPMULdoBuckGetQiMode; \
+ PMU_CTRL_LDO_BUCK_SET_EN_FORCE rPMULdoBuckSetEnForce; \
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE rPMULdoBuckSetVoltage; \
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE_EN rPMULdoBuckSetVoltageEn; \
+ PMU_CTRL_LDO_BUCK_SET_SLEEP_VOLTAGE rPMULdoBuckSetSleepVoltage; \
+ PMU_CTRL_LDO_BUCK_SET_BURST_THRESHOLD rPMULdoBuckSetBurstThreshold; \
+ PMU_CTRL_LDO_BUCK_SET_CURRENT_LIMIT rPMULdoBuckSetCurrentLimit; \
+ PMU_CTRL_LDO_BUCK_SET_VOLTAGE_CALIBRATION_CODE rPMULdoBuckSetVoltageCalibrationCode; \
+ PMU_CTRL_LDO_BUCK_SET_BIAS_CURRENT_CALIBRATION_CODE rPMULdoBuckSetBiasCurrentCalibrationCode; \
+ PMU_CTRL_LDO_BUCK_SET_STB_EN rPMULdoBuckSetStbEn; \
+ PMU_CTRL_LDO_BUCK_SET_OC_AUTO_OFF rPMULdoBuckSetOcAutoOff; \
+ PMU_CTRL_LDO_BUCK_SET_RS rPMULdoBuckSetRs; \
+ PMU_CTRL_LDO_BUCK_SET_ON_SEL rPMULdoBuckSetOnSel; \
+ PMU_CTRL_LDO_BUCK_SET_SRCLKEN_SEL rPMULdoBuckSetSrclkenSel; \
+ PMU_CTRL_LDO_BUCK_SET_STB_TD rPMULdoBuckSetStbTd; \
+ PMU_CTRL_LDO_BUCK_SET_NDIS_EN rPMULdoBuckSetNdisEn; \
+ PMU_CTRL_LDO_BUCK_SET_OC_TD rPMULdoBuckSetOcTd; \
+ PMU_CTRL_LDO_BUCK_SET_OCFB_EN rPMULdoBuckSetOcfbEn; \
+ PMU_CTRL_LDO_BUCK_SET_VSIM_GPLDO_EN rPMULdoBuckSetVsimGpldoEn; \
+ PMU_CTRL_LDO_BUCK_SET_VSIM2_GPLDO_EN rPMULdoBuckSetVsim2GpldoEn; \
+ PMU_CTRL_LDO_BUCK_SET_SIM2_GPIO_EN rPMULdoBuckSetSim2GpioEn; \
+ PMU_CTRL_LDO_BUCK_SET_CCI_SRCLKEN rPMULdoBuckSetCciSrclken; \
+ PMU_CTRL_LDO_BUCK_GET_OC_STATUS rPMULdoBuckGetOcStatus; \
+ PMU_CTRL_LDO_BUCK_GET_QI_OC_STATUS rPMULdoBuckGetQiOcStatus; \
+ PMU_CTRL_LDO_BUCK_SET_OC_INT_EN rPMULdoBuckSetOcIntEn; \
+ PMU_CTRL_LDO_BUCK_CLEAR_OC_FLAG rPMULdoBuckClearOcFlag; \
+ PMU_CTRL_LDO_BUCK_GET_OC_FLAG rPMULdoBuckGetOcFlag; \
+ PMU_CTRL_LDO_BUCK_GET_VOLTAGE_LIST rPMULdoBuckGetVoltageList; \
+ PMU_CTRL_LDO_BUCK_SET_THER_SHDN_EN rPMULdoBuckSetTherShdnEn; \
+ PMU_CTRL_LDO_BUCK_SET_LP_MODE_SET rPMULdoBuckSetLpModeSet; \
+ PMU_CTRL_LDO_BUCK_GET_LP_MODE rPMULdoBuckGetLpMode; \
+ PMU_CTRL_LDO_BUCK_SET_LP_SEL rPMULdoBuckSetLpSel; \
+ PMU_CTRL_LDO_BUCK_SET_ON_CTRL rPMULdoBuckSetOnCtrl; \
+ PMU_CTRL_LDO_BUCK_SET_MODESET rPMULdoBuckSetModeset; \
+ PMU_CTRL_LDO_BUCK_SET_COT rPMULdoBuckSetCotset; \
+ PMU_CTRL_LDO_BUCK_GET_COT rPMULdoBuckGetCot; \
+ PMU_CTRL_LDO_BUCK_SET_EN_CTRL rPMULdoBuckSetEnCtrl; \
+ PMU_CTRL_LDO_BUCK_SET_EN_SEL rPMULdoBuckSetEnSel; \
+ PMU_CTRL_LDO_BUCK_SET_SRCLK_MODE_SEL rPMULdoBuckSetSrclkModeSel; \
+ PMU_CTRL_LDO_BUCK_SET_SRCLK_EN_SEL rPMULdoBuckSetSrclkEnSel; \
+ PMU_CTRL_LDO_SET_CAL rPMULdoSetCal; \
+ PMU_CTRL_LDO_BUCK_GET_VOLTAGE rPMULdoBuckGetVolt; \
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_CTRL rPMULdoBuckGetVoselCtrl; \
+ PMU_CTRL_LDO_BUCK_GET_VOSEL rPMULdoBuckGetVosel; \
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_ON rPMULdoBuckGetVoselOn; \
+ PMU_CTRL_LDO_BUCK_GET_VOSEL_SLEEP rPMULdoBuckGetVoselSleep; \
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_CTRL rPMULdoBuckSetVoselCtrl; \
+ PMU_CTRL_LDO_BUCK_SET_VOSEL rPMULdoBuckSetVosel; \
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_ON rPMULdoBuckSetVoselOn; \
+ PMU_CTRL_LDO_BUCK_SET_VOSEL_SLEEP rPMULdoBuckSetVoselSleep; \
+ PMU_CTRL_LDO_SET_VTCXO24_SWITCH_EN rPMULdoBuckSetVtcxoSwith; \
+ PMU_CTRL_LDO_BUCK_SET_FPWM rPMULdoBuckSetFpwm; \
+ PMU_CTRL_LDO_BUCK_GET_FPWM rPMULdoBuckGetFpwm; \
+ PMU_CTRL_VPA_SET_VOSEL_MAP_EN rPMUVpaSetVoselMapEn; \
+ PMU_CTRL_VPA_SET_EN rPMUVpaSetEn; \
+ PMU_CTRL_VPA_SET_VOLTAGE rPMUVpaSetVoltage; \
+ PMU_CTRL_VPA_CTRL_SEL rPMUVpaCtrlSel; \
+ PMU_CTRL_VPA_GET_VOLTAGE_LIST rPMUVpaGetVoltageList; \
+ PMU_CTRL_VPA_SET_BAT_LOW rPMUVpaSetBatLow; \
+ PMU_CTRL_VPA_SET_FPWM rPMUVpaSetFpwm; \
+ PMU_CTRL_VPA_SET_VOLTAGE_SELECTION_TABLE rPMUVpaSetVoltageSelectionTable; \
+ PMU_CTRL_VPA_SET_MAP_SEL rPMUVpaSetMapSel; \
+ PMU_CTRL_VIBR_SET_DIMMING_ON_DUTY rPMUVibrSetDimmingOnDuty; \
+ PMU_CTRL_VRF18_SET_FPWM rPMUVrf18SetFpwm; \
+ PMU_CTRL_VRF18_SET_MODESET rPMUVrf18SetModeset; \
+ PMU_CTRL_VRF18_SET_BUCK_LDO_MODE rPMUVrf18SetBuckLdoMode; \
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_SET rPMUVrf1SetModesetCkpdnSet; \
+ PMU_CTRL_VRF1_SET_MODESET_CKPDN_CLR rPMUVrf1SetModesetCkpdnClr; \
+ PMU_CTRL_VRF1_GET_MODESET_CKPDN rPMUVrf1GetModesetCkpdn; \
+ PMU_CTRL_SIMLS_SET_SRST_CONF rPMUSimlsSetSrstConf; \
+ PMU_CTRL_SIMLS_SET_SCLK_CONF rPMUSimlsSetSclkConf; \
+ PMU_CTRL_SIMLS_SET_TDSEL rPMUSimlsSetTdsel; \
+ PMU_CTRL_SIMAP_SET_TDSEL rPMUSimapSetTdsel; \
+ PMU_CTRL_SIMLS_SET_RDSEL rPMUSimlsSetRdsel; \
+ PMU_CTRL_SIMAP_SET_RDSEL rPMUSimapSetRdsel; \
+ PMU_CTRL_SIM_SET_STB_SIO_MODE rPMUSimSetStbSioMode; \
+ PMU_CTRL_SIMRST_SET_GPIO_SET rPMUSimrstSetGpioSet; \
+ PMU_CTRL_SIMRST_SET_GPIO_CLR rPMUSimrstSetGpioClr; \
+ PMU_CTRL_OCTL_SET_SIM_AP_SRST rPMUOctlSetSimApSrst; \
+ PMU_CTRL_OCTL_SET_SIM_AP_SCLK rPMUOctlSetSimApSclk; \
+ PMU_CTRL_OCTL_SET_SIMLS_SRST rPMUOctlSetSimlsSrst; \
+ PMU_CTRL_OCTL_SET_SIMLS_SCLK rPMUOctlSetSimlsSclk; \
+ PMU_CTRL_SPK_SET_EN rPMUSpkSetEn; \
+ PMU_CTRL_SPK_SET_MODE rPMUSpkSetMode; \
+ PMU_CTRL_SPK_GET_MODE rPMUSpkGetMode; \
+ PMU_CTRL_SPK_SET_OC_AUTO_OFF rPMUSpkSetOcAutoOff; \
+ PMU_CTRL_SPK_SET_VOL_VALUE rPMUSpkSetVolValue; \
+ PMU_CTRL_SPK_GET_VOL_VALUE rPMUSpkGetVolValue; \
+ PMU_CTRL_SPK_SET_VOL rPMUSpkSetVol; \
+ PMU_CTRL_SPK_GET_VOL rPMUSpkGetVol; \
+ PMU_CTRL_SPK_SET_SLEW_RATE rPMUSpkSetSlewRate; \
+ PMU_CTRL_SPK_SET_CALIBR_EN rPMUSpkSetCalibrEn; \
+ PMU_CTRL_SPK_SET_CALIBR_SEL rPMUSpkSetCalibrSel; \
+ PMU_CTRL_FLASHLED_SET_EN rPMUFlashledSetEn; \
+ PMU_CTRL_FLASHLED_SET_MODE rPMUFlashledSetMode; \
+ PMU_CTRL_FLASHLED_SET_SEL rPMUFlashledSetSel; \
+ PMU_CTRL_KPLED_SET_EN rPMUKpledSetEn; \
+ PMU_CTRL_KPLED_SET_MODE rPMUKpledSetMode; \
+ PMU_CTRL_KPLED_SET_SEL rPMUKpledSetSel; \
+ PMU_CTRL_KPLED_SET_FREQUENCY_DIVISION rPMUKpledSetFrequencyDivision; \
+ PMU_CTRL_KPLED_SET_DIMMING_ON_DUTY rPMUKpledSetDimmingOnDuty; \
+ PMU_CTRL_CHR_SET_ADC_MEASURE_EN rPMUChrSetAdcMeasureEn; \
+ PMU_CTRL_CHR_SET_WDT_TIMER rPMUChrSetWdtTimer; \
+ PMU_CTRL_CHR_SET_WDT_INT_EN rPMUChrSetWdtIntEn; \
+ PMU_CTRL_CHR_SET_WDT_EN rPMUChrSetWdtEn; \
+ PMU_CTRL_CHR_SET_CHR_EN rPMUChrSetChrEn; \
+ PMU_CTRL_CHR_SET_CHR_FORCE_EN rPMUChrSetChrForceEn; \
+ PMU_CTRL_CHR_GET_CHR_DET_STATUS rPMUChrGetChrDetStatus; \
+ PMU_CTRL_CHR_GET_CHR_CURRENT rPMUChrGetChrCurrent; \
+ PMU_CTRL_CHR_GET_CHR_CURRENT_LIST rPMUChrGetChrCurrentList; \
+ PMU_CTRL_CHR_SET_CHR_CURRENT rPMUChrSetChrCurrent; \
+ PMU_CTRL_CHR_GET_CV_DETECTION_STATUS rPMUChrGetCvDetectionStatus; \
+ PMU_CTRL_CHR_SET_CV_DETECTION_EN rPMUChrSetCvDetectionEn; \
+ PMU_CTRL_CHR_SET_CV_DETECTION_VOLTAGE rPMUChrSetCvDetectionVoltage; \
+ PMU_CTRL_CHR_SET_CSDAC_EN rPMUChrSetCsdacEn; \
+ PMU_CTRL_CHR_GET_IS_BATTERY_ON rPMUChrGetIsBatteryOn; \
+ PMU_CTRL_CHR_GET_IS_CHR_VALID rPMUChrGetIsChrValid; \
+ PMU_CTRL_CHR_SET_HV_DETECTION_VOLTAGE rPMUChrSetHvDetectionVoltage; \
+ PMU_CTRL_CHR_GET_HV_DETECTION_VOLTAGE_LIST rPMUChrGetHvDetectionVoltageList; \
+ PMU_CTRL_CHR_SET_VBAT_OV_DETECTION_VOLTAGE rPMUChrSetVbatOvDetectionVoltage; \
+ PMU_CTRL_CHR_SET_BAT_HT_EN rPMUChrSetBatHtEn; \
+ PMU_CTRL_CHR_SET_OTG_BVALID_EN rPMUChrSetOtgBvalidEn; \
+ PMU_CTRL_CHR_SET_CV_MODE rPMUChrSetCvMode; \
+ PMU_CTRL_CHR_SET_CSDAC_MODE rPMUChrSetCsdacMode; \
+ PMU_CTRL_CHR_SET_TRACKING_EN rPMUChrSetTrackingEn; \
+ PMU_CTRL_CHR_SET_HWCV_EN rPMUChrSetHwcvEn; \
+ PMU_CTRL_CHR_SET_ULC_DET_EN rPMUChrSetUlcDetEn; \
+ PMU_CTRL_CHR_SET_BC11_PULLUP_EN rPMUChrSetBc11PullupEn; \
+ PMU_CTRL_CHR_SET_LOW_ICH_DB rPMUChrSetLowIchDb; \
+ PMU_CTRL_CHR_SET_VBAT_CV_CALIBRATION rPMUChrSetVbatCvCalibration; \
+ PMU_CTRL_CHR_GET_CC_DET rPMUChrGetCcDet; \
+ PMU_CTRL_BL_SET_EN rPMUBlSetEn; \
+ PMU_CTRL_BL_SET_INIT rPMUBlSetInit; \
+ PMU_CTRL_BL_GET_SUPPORT_LEVEL rPMUBlGetSupportLevel; \
+ PMU_CTRL_BL_GET_USE_PWM_QUERY rPMUBlGetUsePwmQuery; \
+ PMU_CTRL_BOOST_SET_EN rPMUBoostSetEn; \
+ PMU_CTRL_BOOST_SET_CURRENT_LIMIT rPMUBoostSetCurrentLimit; \
+ PMU_CTRL_BOOST_SET_CLK_CAL rPMUBoostSetClkCal; \
+ PMU_CTRL_BOOST_SET_SYNC_EN rPMUBoostSetSyncEn; \
+ PMU_CTRL_BOOST_SET_VOLTAGE rPMUBoostSetVoltage; \
+ PMU_CTRL_BOOST_SET_LEVEL rPMUBoostSetLevel; \
+ PMU_CTRL_ISINK_SET_EN rPMUIsinkSetEn; \
+ PMU_CTRL_ISINK_SET_MODE rPMUIsinkSetMode; \
+ PMU_CTRL_ISINK_SET_STEP rPMUIsinkSetStep; \
+ PMU_CTRL_ISINK_SET_FORCE_OFF rPMUIsinkSetForceOff; \
+ PMU_CTRL_ISINK_SET_DIMMING_ON_DUTY rPMUIsinkSetDimmingOnDuty; \
+ PMU_CTRL_ISINK_SET_FREQUENCY_DIVISION rPMUIsinkSetFrequencyDivision; \
+ PMU_CTRL_ADC_SET_RQST rPMUAdcSetRqst; \
+ PMU_CTRL_ADC_CLR_RQST rPMUAdcClrRqst; \
+ PMU_CTRL_ADC_GET_RDY_MD rPMUAdcGetRdyMd; \
+ PMU_CTRL_ADC_GET_OUT_MD rPMUAdcGetOutMd; \
+ PMU_CTRL_MISC_SET_RLED_EN rPMUMiscSetRledEn; \
+ PMU_CTRL_MISC_SET_GLED_EN rPMUMiscSetGledEn; \
+ PMU_CTRL_MISC_SET_BLED_EN rPMUMiscSetBledEn; \
+ PMU_CTRL_MISC_GET_CID rPMUMiscGetCid; \
+ PMU_CTRL_MISC_GET_ECO_VERSION rPMUMiscGetEcoVersion; \
+ PMU_CTRL_MISC_GET_HW_VERSION rPMUMiscGetHwVersion; \
+ PMU_CTRL_MISC_SET_REGISTER_VALUE rPMUMiscSetRegisterValue; \
+ PMU_CTRL_MISC_GET_REGISTER_VALUE rPMUMiscGetRegisterValue; \
+ PMU_CTRL_LDO_BUCK_SET_OP_EN rPMULdoBuckSetOpEn; \
+ PMU_CTRL_LDO_BUCK_CLR_OP_EN rPMULdoBuckClrOpEn; \
+ PMU_CTRL_LDO_BUCK_SET_HW_OP_CFG rPMULdoBuckSetHwOp; \
+ PMU_CTRL_LDO_BUCK_CLR_HW_OP_CFG rPMULdoBuckClrHwOp; \
+ PMU_CTRL_LDO_BUCK_SET_GO_ON_OP rPMULdoBuckSetGoOnOp; \
+ PMU_CTRL_LDO_BUCK_SET_GO_LP_OP rPMULdoBuckSetGoLpOp; \
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_EN rPMUTopSetSrclkenInEn; \
+ PMU_CTRL_TOP_SET_SRCLKEN_IN_MODE rPMUTopSetSrclkenInMode; \
+ PMU_CTRL_DCXO_SET_REGISTER_VALUE rPMUDcxoSetRegisterValue; \
+ PMU_CTRL_DCXO_GET_REGISTER_VALUE rPMUDcxoGetRegisterValue; \
+ PMU_CTRL_LDO_BUCK_SET_VOCAL rPMULdoBuckSetVocal; \
+ PMU_CTRL_LDO_BUCK_GET_VOCAL rPMULdoBuckGetVocal; \
+ PMU_CTRL_LDO_BUCK_SET_VOTRIM rPMULdoBuckSetVotrim; \
+ PMU_CTRL_LDO_BUCK_GET_VOTRIM rPMULdoBuckGetVotrim; \
+ PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_STATUS rPMULdoBuckSetVpaOcSdnStatus; \
+ PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_STATUS rPMULdoBuckGetVpaOcSdnStatus; \
+ PMU_CTRL_LDO_BUCK_SET_VPA_OC_SDN_EN rPMULdoBuckSetVpaOcSdnEn; \
+ PMU_CTRL_LDO_BUCK_GET_VPA_OC_SDN_EN rPMULdoBuckGetVpaOcSdnEn; \
+ PMU_CTRL_LDO_BUCK_SET_OP_MODE rPMULdoBuckSetOpMode; \
+ PMU_CTRL_LDO_BUCK_SET_VOTER_VOLTAGE rPMULdoBuckSetVoterVoltage; \
+ PMU_CTRL_LDO_BUCK_SET_BUCK_HW_OP_MODE rPMULdoBuckSetBuckHwOpMode; \
+ PMU_CTRL_LDO_BUCK_CLR_BUCK_HW_OP_MODE rPMULdoBuckClrBuckHwOpMode; \
+ PMU_CTRL_LDO_BUCK_SET_HW_OP_MODE rPMULdoBuckSetHwOpMode; \
+ PMU_CTRL_LDO_BUCK_CLR_HW_OP_MODE rPMULdoBuckClrHwOpMode;
+
+#endif /* __BUILD_DOM__ */
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for PMU
+ *******************************************************************************/
+ #ifdef __BUILD_DOM__
+/* The PMU Command Values in DCL_CTRL_CMD_T Enum of dcl.h */
+typedef enum {
+ LDO_BUCK_SET_CMDS_START = 0, /* For internal use */
+ LDO_BUCK_CTRL, /* For internal use */
+ LDO_BUCK_SET_EN, /* enable ldo/buck */
+ LDO_BUCK_GET_EN_STATUS, /* Get LDO/BUCK Enable Status */
+ LDO_BUCK_GET_QI_MODE, /* Get LDO/BUCK QI Mode */
+ LDO_BUCK_SET_EN_FORCE, /* set ldo/buck force enable */
+ LDO_BUCK_SET_VOLTAGE, /* set ldo/buck voltage */
+ LDO_BUCK_SET_VOLTAGE_EN, /* set ldo/buck voltage and enable */
+ LDO_BUCK_SET_SLEEP_VOLTAGE, /* set ldo/buck sleep voltage */
+ LDO_BUCK_SET_BURST_THRESHOLD = 500, /* set ldo/buck burst threshold */
+ LDO_BUCK_SET_CURRENT_LIMIT, /* set ldo/buck current limit */
+ LDO_BUCK_SET_VOLTAGE_CALIBRATION_CODE, /* set ldo/buck voltage calibration code */
+ LDO_BUCK_SET_BIAS_CURRENT_CALIBRATION_CODE, /* set ldo/buck bias current calibration code */
+ LDO_BUCK_SET_STB_EN, /* enable ldo/buck soft start */
+ LDO_BUCK_SET_OC_AUTO_OFF, /* enable to power-off automatically if oc_flag been asserted */
+ LDO_BUCK_SET_RS, /* set ldo/buck local/remote sense */
+ LDO_BUCK_SET_ON_SEL, /* enable control selection, hardware/software */
+ LDO_BUCK_SET_SRCLKEN_SEL, /* h/w srclk enable selection */
+ LDO_BUCK_SET_STB_TD, /* set ldo/buck deglitch delay time for soft start */
+ LDO_BUCK_SET_NDIS_EN, /* enable ldo/buck NMOS discharge */
+ LDO_BUCK_SET_OC_TD, /* set ldo/buck deglitch time constant for over-current status from PMU to generate oc_flag */
+ LDO_BUCK_SET_OCFB_EN, /* enable ldo/buck over-current fold-back */
+ LDO_BUCK_SET_VSIM_GPLDO_EN, /* select VSIM LDO enable & voltage controlled by SIM controller or register */
+ LDO_BUCK_SET_VSIM2_GPLDO_EN, /* select VSIM2 LDO enable & voltage controlled by SIM2 controller or register */
+ LDO_BUCK_SET_SIM2_GPIO_EN, /* set SIM2 GPIO enable */
+ LDO_BUCK_SET_CCI_SRCLKEN, /* enable SRCLKENA to PMIC force enable control signal */
+ LDO_BUCK_GET_OC_STATUS, /* Get LDO/BUCK Over Current Status */
+ LDO_BUCK_GET_QI_OC_STATUS, /* Get LDO/BUCK QI Over Current Status */
+ LDO_BUCK_SET_OC_INT_EN, /* enable oc interrupt of a ldo or buck */
+ LDO_BUCK_CLEAR_OC_FLAG, /* clear oc flag of ldo or buck */
+ LDO_BUCK_GET_OC_FLAG, /* get oc flag of ldo or buck */
+ LDO_BUCK_GET_VOLTAGE_LIST, /* get voltage list of ldo or buck */
+ LDO_BUCK_SET_THER_SHDN_EN, /* Set Low Power Mode */
+ LDO_BUCK_SET_LP_MODE_SET, /* Set Low Power Mode */
+ LDO_BUCK_GET_LP_MODE, /* get lp mode of ldo or buck */
+ LDO_BUCK_SET_LP_SEL, /* Set Low Power Mode Selection */
+ LDO_BUCK_SET_ON_CTRL, /* Set On Control Mode */
+ LDO_BUCK_SET_MODESET, /* Switch between force PWM mode and AUTO Mode */
+ LDO_BUCK_SET_COT, /* Switch between force COT mode and AUTO Mode */
+ LDO_BUCK_GET_COT, /* Switch between force COT mode and AUTO Mode */
+ LDO_BUCK_SET_EN_CTRL, /* Enable Control */
+ LDO_BUCK_SET_EN_SEL, /* Enable Selection */
+ LDO_BUCK_SET_SRCLK_MODE_SEL, /* HW low power mode srclk selection */
+ LDO_BUCK_SET_SRCLK_EN_SEL, /* Enable Selection */
+ LDO_SET_CAL, /* ldo output voltage calibration */
+ LDO_BUCK_GET_VOLTAGE, /* get voltage of ldo or buck */
+ LDO_BUCK_GET_VOSEL_CTRL, /* get vosel ctrl by sw or hw */
+ LDO_BUCK_GET_VOSEL, /* get vosel */
+ LDO_BUCK_GET_VOSEL_ON, /* get vosel on */
+ LDO_BUCK_GET_VOSEL_SLEEP, /* get vosel sleep */
+ LDO_BUCK_SET_VOSEL_CTRL, /* set vosel ctrl by sw or hw */
+ LDO_BUCK_SET_VOSEL, /* set vosel */
+ LDO_BUCK_SET_VOSEL_ON, /* set vosel on */
+ LDO_BUCK_SET_VOSEL_SLEEP, /* set vosel sleep */
+ LDO_BUCK_SET_VTCXO24_SWITCH, /* set vtcxo24 switch */
+ LDO_BUCK_SET_FPWM, /* For internal use */
+ LDO_BUCK_GET_FPWM, /* For internal use */
+ LDO_BUCK_SET_CMDS_END, /* For internal use */
+ VIBR_SET_DIMMING_ON_DUTY = 900, /* modify vibrator dimming duty */
+ VPA_SET_VOLTAGE = 1000, /* set VPA0-7 voltage */
+ VPA_SET_VOSEL_MAP_EN, /* enables voltage mapping to select VPA_VOSEL from vpa vosel table depending on vpa_table_sel */
+ VPA_SET_EN, /* enable VPA */
+ VPA_CTRL_SEL, /* Control the VPA Sourse */
+ VPA_GET_VOLTAGE_LIST, /* get VPA supported voltage list */
+ VPA_SET_BAT_LOW, /* BAT_LOW to indicate VPA by-pass mode (6326) */
+ VPA_SET_FPWM, /* set VPA FPWM */
+ VPA_SET_VOLTAGE_SELECTION_TABLE, /* voltage selection when vpa_vosel_map_en=1 */
+ VPA_SET_MAP_SEL, /* Selects one entry in vpa vosel table to use for VPA_VOSEL */
+ VRF18_SET_MODESET, /* set VRF18 Force PWM Mode */
+ VRF18_SET_FPWM, /* set VRF18 FPWM */
+ VRF18_2_SET_FPWM, /* set VRF18_2 FPWM */
+ VRF18_SET_BUCK_LDO_MODE, /* set VRF18 Buck/LDO Mode */
+ VRF1_SET_MODESET_CKPDN_SET, /* VRF1 MODESET Clock SET */
+ VRF1_SET_MODESET_CKPDN_CLR, /* VRF1 MODESET Clock CLR */
+ VRF1_GET_MODESET_CKPDN, /* Enable Selection */
+ SIMLS_SET_SRST_CONF, /* Set SIMLS_SRST */
+ SIMLS_SET_SCLK_CONF, /* Set SIMLS_SCLK */
+ SIMLS_SET_TDSEL, /* Set SIMLS_TDSEL */
+ SIMAP_SET_TDSEL, /* Set SIMAP_RDSEL */
+ SIMLS_SET_RDSEL, /* Set SIMLS_TDSEL */
+ SIMAP_SET_RDSEL, /* Set SIMAP_RDSEL */
+ SIM_SET_STB_SIO_MODE, /* Set SIM STB SIO Mode */
+ SIMRST_SET_GPIO_SET, /* Set SIMRST GPIO */
+ SIMRST_SET_GPIO_CLR, /* Clear SIMRST GPIO */
+ OCTL_SET_SIM_AP_SRST, /* Set OCTL_SIM_AP_SRST */
+ OCTL_SET_SIM_AP_SCLK, /* Set OCTL_SIM_AP_SCLK */
+ OCTL_SET_SIMLS_SRST, /* Set OCTL_SIMLS_SRST */
+ OCTL_SET_SIMLS_SCLK, /* Set OCTL_SIMLS_SCLK */
+ SPK_SET_EN = 2000, /* enable spk */
+ SPK_SET_MODE, /* set spk mode */
+ SPK_GET_MODE, /* get spk mode */
+ SPK_SET_OC_AUTO_OFF, /* enable spk over-current auto off */
+ SPK_SET_VOL_VALUE, /* set spk volume (register value) */
+ SPK_GET_VOL_VALUE, /* get spk volume (register value) */
+ SPK_SET_VOL, /* set spk volume (dbm) */
+ SPK_GET_VOL, /* get spk volume (dbm) */
+ SPK_SET_SLEW_RATE, /* set spk slew rate */
+ SPK_SET_CALIBR_EN, /* set spk Class D offset calibration enable */
+ SPK_SET_CALIBR_SEL, /* set spk Class D offset calibration path */
+ KPLED_SET_EN = 3000, /* enable kpled */
+ KPLED_SET_MODE, /* set kpled mode (pwm/register) */
+ KPLED_SET_SEL, /* kpled Turn On Resistor Select */
+ KPLED_SET_FREQUENCY_DIVISION, /* set kpled frequency division */
+ KPLED_SET_DIMMING_ON_DUTY, /* set kpled dimming duty */
+ FLASHLED_SET_EN = 4000, /* enable flashled */
+ FLASHLED_SET_MODE, /* set flashled mode (pwm/regsiter) */
+ FLASHLED_SET_SEL, /* kpled Turn On Resistor Select */
+ BL_SET_INIT = 5000, /* backlight init mode */
+ BL_SET_EN, /* enable backlight */
+ BL_GET_SUPPORT_LEVEL, /* get backlight support level */
+ BL_GET_USE_PWM_QUERY, /* get backlight use pwm query */
+ BOOST_SET_EN = 6000, /* enable boost */
+ BOOST_SET_CURRENT_LIMIT, /* set boost current limit */
+ BOOST_SET_CLK_CAL, /* set boost clock cal */
+ BOOST_SET_SYNC_EN, /* enable boost sync */
+ BOOST_SET_VOLTAGE, /* set boost voltage */
+ BOOST_SET_LEVEL, /* set boost level */
+ ISINK_SET_EN = 7000, /* enable isink */
+ ISINK_SET_MODE, /* set isink mode */
+ ISINK_SET_STEP, /* set isink step */
+ ISINK_SET_FORCE_OFF, /* set isink force off */
+ ISINK_SET_CHANNEL, /* set isink channel */
+ ISINK_SET_DIMMING_ON_DUTY, /* set kpled dimming duty */
+ ISINK_SET_FREQUENCY_DIVISION, /* set kpled frequency division */
+ CHR_SET_ADC_MEASURE_EN = 8000, /* enable adc measure */
+ CHR_SET_WDT_CLEAR, /* clear charger wdt */
+ CHR_SET_WDT_TIMER, /* set charger wdt timer */
+ CHR_SET_WDT_INT_EN, /* enable charger wdt interrupt */
+ CHR_SET_WDT_EN, /* enable charger wdt */
+ CHR_SET_CHR_EN, /* enable charger */
+ CHR_SET_CHR_FORCE_EN, /* force enable charger */
+ CHR_GET_CHR_DET_STATUS, /* get charger detection status */
+ CHR_GET_CHR_CURRENT, /* get charger current */
+ CHR_GET_CHR_CURRENT_LIST, /* get charger current list */
+ CHR_SET_CHR_CURRENT, /* set charger current */
+ CHR_GET_CV_DETECTION_STATUS, /* get CV detection status */
+ CHR_SET_CV_DETECTION_EN, /* enable CV detection */
+ CHR_SET_CV_DETECTION_VOLTAGE, /* set CV voltage */
+ CHR_SET_CV_DETECTION_VOLTAGE_CALIBRATION, /* set CV voltage calibration */
+ CHR_SET_CSDAC_EN, /* enable csdac */
+ CHR_GET_IS_BATTERY_ON, /* check is battery on */
+ CHR_GET_IS_CHR_VALID, /* check is charger valid */
+ CHR_SET_HV_DETECTION_VOLTAGE, /* set HV detection voltage */
+ CHR_GET_HV_DETECTION_VOLTAGE_LIST, /* get HV detection voltage list */
+ CHR_SET_VBAT_OV_DETECTION_VOLTAGE, /* set battery OV detection voltage */
+ CHR_SET_BAT_HT_EN, /* enable battery high tempture detection */
+ CHR_SET_OTG_BVALID_EN, /* enable OTG BVALID */
+ CHR_SET_CV_MODE, /* enable CV detect@ charging enable */
+ CHR_SET_CSDAC_MODE, /* enable s/w control */
+ CHR_SET_TRACKING_EN, /* enable HTH/LTH for current tracking */
+ CHR_SET_HWCV_EN, /* enable H/W CV */
+ CHR_SET_ULC_DET_EN, /* enable plug out HW detection */
+ CHR_SET_LOW_ICH_DB, /* set plug out HW detection de-bounce time */
+ CHR_SET_CHARGE_WITHOUT_BATTERY, /* enable charger without battery */
+ CHR_SET_BC11_PULLUP_EN, /* turn on/off BC11 pull up*/
+ CHR_SET_VBAT_CV_CALIBRATION, /* do VBAT CV Calibration trimming */
+ CHR_GET_CC_DET, /* get VBAT CC detection result */
+ ADC_SET_RQST, /* AUXADC MD Set request */
+ ADC_CLR_RQST, /* AUXADC MD Clr request */
+ ADC_GET_RDY_MD, /* AUXADC MD Data Ready */
+ ADC_GET_OUT_MD, /* AUXADC channel output data for MD */
+ MISC_SET_RLED_EN = 9000, /* enable Red led */
+ MISC_SET_GLED_EN, /* enable green led */
+ MISC_SET_BLED_EN, /* enable blue led */
+ MISC_GET_CID, /* get pmu/pmic cid */
+ MISC_GET_ECO_VERSION, /* get pmu/pmic eco version */
+ MISC_GET_HW_VERSION, /* get pmu/pmic HW version */
+ MISC_SET_REGISTER_VALUE, /* set pmu/pmic register value */
+ MISC_GET_REGISTER_VALUE, /* get pmu/pmic register value */
+ LDO_BUCK_SET_OP_EN,
+ LDO_BUCK_CLR_OP_EN,
+ LDO_BUCK_SET_HW_OP_CFG,
+ LDO_BUCK_CLR_HW_OP_CFG,
+ LDO_BUCK_SET_GO_ON_OP,
+ LDO_BUCK_SET_GO_LP_OP,
+ TOP_SET_SRCLKEN_IN_EN,
+ TOP_SET_SRCLKEN_IN_MODE,
+ DCXO_SET_REGISTER_VALUE,
+ DCXO_GET_REGISTER_VALUE,
+ PMU_MOD_CMD_MAX,
+ LDO_BUCK_SET_VOCAL,
+ LDO_BUCK_GET_VOCAL,
+ LDO_BUCK_SET_VOTRIM,
+ LDO_BUCK_GET_VOTRIM,
+ LDO_BUCK_SET_VPA_OC_SDN_STATUS,
+ LDO_BUCK_GET_VPA_OC_SDN_STATUS,
+ LDO_BUCK_SET_VPA_OC_SDN_EN,
+ LDO_BUCK_GET_VPA_OC_SDN_EN,
+ LDO_BUCK_SET_OP_MODE,
+ LDO_BUCK_SET_VOTER_VOLTAGE,
+ LDO_BUCK_SET_BUCK_HW_OP_MODE,
+ LDO_BUCK_CLR_BUCK_HW_OP_MODE,
+ LDO_BUCK_SET_HW_OP_MODE,
+ LDO_BUCK_CLR_HW_OP_MODE
+} PMU_CTRL_CMD;
+#else /* __BUILD_DOM__ */
+#define PMU_CMDS \
+ LDO_BUCK_SET_CMDS_START = 0, \
+ LDO_BUCK_CTRL, \
+ LDO_BUCK_SET_EN, \
+ LDO_BUCK_GET_EN_STATUS, \
+ LDO_BUCK_GET_QI_MODE, \
+ LDO_BUCK_SET_EN_FORCE, \
+ LDO_BUCK_SET_VOLTAGE, \
+ LDO_BUCK_SET_VOLTAGE_EN, \
+ LDO_BUCK_SET_SLEEP_VOLTAGE, \
+ LDO_BUCK_SET_BURST_THRESHOLD = 500, \
+ LDO_BUCK_SET_CURRENT_LIMIT, \
+ LDO_BUCK_SET_VOLTAGE_CALIBRATION_CODE, \
+ LDO_BUCK_SET_BIAS_CURRENT_CALIBRATION_CODE, \
+ LDO_BUCK_SET_STB_EN, \
+ LDO_BUCK_SET_OC_AUTO_OFF, \
+ LDO_BUCK_SET_RS, \
+ LDO_BUCK_SET_ON_SEL, \
+ LDO_BUCK_SET_SRCLKEN_SEL, \
+ LDO_BUCK_SET_STB_TD, \
+ LDO_BUCK_SET_NDIS_EN, \
+ LDO_BUCK_SET_OC_TD, \
+ LDO_BUCK_SET_OCFB_EN, \
+ LDO_BUCK_SET_VSIM_GPLDO_EN, \
+ LDO_BUCK_SET_VSIM2_GPLDO_EN, \
+ LDO_BUCK_SET_SIM2_GPIO_EN, \
+ LDO_BUCK_SET_CCI_SRCLKEN, \
+ LDO_BUCK_GET_OC_STATUS, \
+ LDO_BUCK_GET_QI_OC_STATUS, \
+ LDO_BUCK_SET_OC_INT_EN, \
+ LDO_BUCK_CLEAR_OC_FLAG, \
+ LDO_BUCK_GET_OC_FLAG, \
+ LDO_BUCK_GET_VOLTAGE_LIST, \
+ LDO_BUCK_SET_THER_SHDN_EN, \
+ LDO_BUCK_SET_LP_MODE_SET, \
+ LDO_BUCK_GET_LP_MODE, \
+ LDO_BUCK_SET_LP_SEL, \
+ LDO_BUCK_SET_ON_CTRL, \
+ LDO_BUCK_SET_MODESET, \
+ LDO_BUCK_SET_COT, \
+ LDO_BUCK_GET_COT, \
+ LDO_BUCK_SET_EN_CTRL, \
+ LDO_BUCK_SET_SRCLK_MODE_SEL, \
+ LDO_BUCK_SET_SRCLK_EN_SEL, \
+ LDO_BUCK_SET_EN_SEL, \
+ LDO_SET_CAL, \
+ LDO_BUCK_GET_VOLTAGE, \
+ LDO_BUCK_GET_VOSEL_CTRL, \
+ LDO_BUCK_GET_VOSEL, \
+ LDO_BUCK_GET_VOSEL_ON, \
+ LDO_BUCK_GET_VOSEL_SLEEP, \
+ LDO_BUCK_SET_VOSEL_CTRL, \
+ LDO_BUCK_SET_VOSEL, \
+ LDO_BUCK_SET_VOSEL_ON, \
+ LDO_BUCK_SET_VOSEL_SLEEP, \
+ LDO_BUCK_SET_VTCXO24_SWITCH, \
+ LDO_BUCK_SET_FPWM, \
+ LDO_BUCK_GET_FPWM, \
+ LDO_BUCK_SET_CMDS_END, \
+ VIBR_SET_DIMMING_ON_DUTY = 900, \
+ VPA_SET_VOLTAGE = 1000, \
+ VPA_SET_VOSEL_MAP_EN, \
+ VPA_SET_EN, \
+ VPA_CTRL_SEL, \
+ VPA_GET_VOLTAGE_LIST, \
+ VPA_SET_BAT_LOW, \
+ VPA_SET_FPWM, \
+ VPA_SET_VOLTAGE_SELECTION_TABLE, \
+ VPA_SET_MAP_SEL, \
+ VRF18_SET_FPWM, \
+ VRF18_SET_MODESET, \
+ VRF18_2_SET_FPWM, \
+ VRF18_SET_BUCK_LDO_MODE, \
+ VRF1_SET_MODESET_CKPDN_SET, \
+ VRF1_SET_MODESET_CKPDN_CLR, \
+ VRF1_GET_MODESET_CKPDN, \
+ SIMLS_SET_SRST_CONF, \
+ SIMLS_SET_SCLK_CONF, \
+ SIMLS_SET_TDSEL, \
+ SIMAP_SET_TDSEL, \
+ SIMLS_SET_RDSEL, \
+ SIMAP_SET_RDSEL, \
+ SIM_SET_STB_SIO_MODE, \
+ SIMRST_SET_GPIO_SET, \
+ SIMRST_SET_GPIO_CLR, \
+ OCTL_SET_SIM_AP_SRST, \
+ OCTL_SET_SIM_AP_SCLK, \
+ OCTL_SET_SIMLS_SRST, \
+ OCTL_SET_SIMLS_SCLK, \
+ SPK_SET_EN = 2000, \
+ SPK_SET_MODE, \
+ SPK_GET_MODE, \
+ SPK_SET_OC_AUTO_OFF, \
+ SPK_SET_VOL_VALUE, \
+ SPK_GET_VOL_VALUE, \
+ SPK_SET_VOL, \
+ SPK_GET_VOL, \
+ SPK_SET_SLEW_RATE, \
+ SPK_SET_CALIBR_EN, \
+ SPK_SET_CALIBR_SEL, \
+ KPLED_SET_EN = 3000, \
+ KPLED_SET_MODE, \
+ KPLED_SET_SEL, \
+ KPLED_SET_FREQUENCY_DIVISION, \
+ KPLED_SET_DIMMING_ON_DUTY, \
+ FLASHLED_SET_EN = 4000, \
+ FLASHLED_SET_MODE, \
+ FLASHLED_SET_SEL, \
+ BL_SET_INIT = 5000, \
+ BL_SET_EN, \
+ BL_GET_SUPPORT_LEVEL, \
+ BL_GET_USE_PWM_QUERY, \
+ BOOST_SET_EN = 6000, \
+ BOOST_SET_CURRENT_LIMIT, \
+ BOOST_SET_CLK_CAL, \
+ BOOST_SET_SYNC_EN, \
+ BOOST_SET_VOLTAGE, \
+ BOOST_SET_LEVEL, \
+ ISINK_SET_EN = 7000, \
+ ISINK_SET_MODE, \
+ ISINK_SET_STEP, \
+ ISINK_SET_FORCE_OFF, \
+ ISINK_SET_CHANNEL, \
+ ISINK_SET_DIMMING_ON_DUTY, \
+ ISINK_SET_FREQUENCY_DIVISION, \
+ CHR_SET_ADC_MEASURE_EN = 8000, \
+ CHR_SET_WDT_CLEAR, \
+ CHR_SET_WDT_TIMER, \
+ CHR_SET_WDT_INT_EN, \
+ CHR_SET_WDT_EN, \
+ CHR_SET_CHR_EN, \
+ CHR_SET_CHR_FORCE_EN, \
+ CHR_GET_CHR_DET_STATUS, \
+ CHR_GET_CHR_CURRENT, \
+ CHR_GET_CHR_CURRENT_LIST, \
+ CHR_SET_CHR_CURRENT, \
+ CHR_GET_CV_DETECTION_STATUS, \
+ CHR_SET_CV_DETECTION_EN, \
+ CHR_SET_CV_DETECTION_VOLTAGE, \
+ CHR_SET_CV_DETECTION_VOLTAGE_CALIBRATION, \
+ CHR_SET_CSDAC_EN, \
+ CHR_GET_IS_BATTERY_ON, \
+ CHR_GET_IS_CHR_VALID, \
+ CHR_SET_HV_DETECTION_VOLTAGE, \
+ CHR_GET_HV_DETECTION_VOLTAGE_LIST, \
+ CHR_SET_VBAT_OV_DETECTION_VOLTAGE, \
+ CHR_SET_BAT_HT_EN, \
+ CHR_SET_OTG_BVALID_EN, \
+ CHR_SET_CV_MODE, \
+ CHR_SET_CSDAC_MODE, \
+ CHR_SET_TRACKING_EN, \
+ CHR_SET_HWCV_EN, \
+ CHR_SET_ULC_DET_EN, \
+ CHR_SET_LOW_ICH_DB, \
+ CHR_SET_CHARGE_WITHOUT_BATTERY, \
+ CHR_SET_BC11_PULLUP_EN, \
+ CHR_SET_VBAT_CV_CALIBRATION, \
+ CHR_GET_CC_DET, \
+ ADC_SET_RQST, \
+ ADC_CLR_RQST, \
+ ADC_GET_RDY_MD, \
+ ADC_GET_OUT_MD, \
+ MISC_SET_RLED_EN = 9000, \
+ MISC_SET_GLED_EN, \
+ MISC_SET_BLED_EN, \
+ MISC_GET_CID, \
+ MISC_GET_ECO_VERSION, \
+ MISC_GET_HW_VERSION, \
+ MISC_SET_REGISTER_VALUE, \
+ MISC_GET_REGISTER_VALUE, \
+ LDO_BUCK_SET_OP_EN, \
+ LDO_BUCK_CLR_OP_EN, \
+ LDO_BUCK_SET_HW_OP_CFG,\
+ LDO_BUCK_CLR_HW_OP_CFG,\
+ LDO_BUCK_SET_GO_ON_OP,\
+ LDO_BUCK_SET_GO_LP_OP,\
+ TOP_SET_SRCLKEN_IN_EN, \
+ TOP_SET_SRCLKEN_IN_MODE , \
+ DCXO_SET_REGISTER_VALUE, \
+ DCXO_GET_REGISTER_VALUE, \
+ LDO_BUCK_SET_VOCAL, \
+ LDO_BUCK_GET_VOCAL, \
+ LDO_BUCK_SET_VOTRIM, \
+ LDO_BUCK_GET_VOTRIM, \
+ LDO_BUCK_SET_VPA_OC_SDN_STATUS, \
+ LDO_BUCK_GET_VPA_OC_SDN_STATUS, \
+ LDO_BUCK_SET_VPA_OC_SDN_EN, \
+ LDO_BUCK_GET_VPA_OC_SDN_EN, \
+ LDO_BUCK_SET_OP_MODE, \
+ LDO_BUCK_SET_VOTER_VOLTAGE, \
+ LDO_BUCK_SET_BUCK_HW_OP_MODE,\
+ LDO_BUCK_CLR_BUCK_HW_OP_MODE, \
+ LDO_BUCK_SET_HW_OP_MODE, \
+ LDO_BUCK_CLR_HW_OP_MODE, \
+ PMU_MOD_CMD_MAX,
+#endif /* __BUILD_DOM__ */
+
+/*******************************************************************************
+ * DCL_FLAGS for PMU
+ *******************************************************************************/
+ #ifdef __BUILD_DOM__
+/* The PMU Command Values in DCL_CTRL_CMD_T Enum of dcl.h */
+typedef enum {
+ PWRAP_FLAGS_START = 100,
+ PWRAP_FLAGS_ACCESS_WACS0 = PWRAP_FLAGS_START,
+ PWRAP_FLAGS_ACCESS_WACS1,
+ PMU_MOD_CMD_MAX,
+} PMU_FLAGS;
+#else /* __BUILD_DOM__ */
+#define PMU_FLAGS \
+ PWRAP_FLAGS_START = 100, \
+ PWRAP_FLAGS_ACCESS_WACS0 = PWRAP_FLAGS_START,\
+ PWRAP_FLAGS_ACCESS_WACS1, \
+ PMU_FLAGS_MAX,
+#endif /* __BUILD_DOM__ */
+
+#endif // #ifndef __DCL_PMU_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_PMU_H_PROTOTYPE__
+#define __DCL_PMU_H_PROTOTYPE__
+
+typedef DCL_STATUS (*PMU_CONTROL_HANDLER)(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+
+/*************************************************************************
+* FUNCTION
+* DclPMU_Initialize
+*
+* DESCRIPTION
+* This function is to initialize PMU module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclPMU_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclPMU_Open
+*
+* DESCRIPTION
+* This function is to open the PMU module and return a handle
+*
+* PARAMETERS
+* dev: only valid for DCL_PMU
+* flags: no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Open failed.
+* other value: a valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclPMU_Open(DCL_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* DclPMU_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the PMU module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclPMU_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclPMU_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the PMU module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclPMU_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclPMU_Configure
+*
+* DESCRIPTION
+* This function is not supported for the PMU module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclPMU_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+/*************************************************************************
+* FUNCTION
+* DclPMU_RegisterCallback
+*
+* DESCRIPTION
+* This function is not supported for the PMU module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclPMU_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+/*************************************************************************
+* FUNCTION
+* DclPMU_Control
+*
+* DESCRIPTION
+* This function is to send command to control the PMU module.
+*
+* PARAMETERS
+* handle: The handle value returned from DclPMU_Open
+* cmd: a control command for PMU module
+* LDO_BUCK_SET_CMDS_START: For internal use
+* LDO_BUCK_CTRL: For internal use
+* LDO_BUCK_SET_EN: enable ldo/buck
+* LDO_BUCK_GET_EN_STATUS: Get LDO/BUCK Enable Status
+* LDO_BUCK_GET_QI_MODE: Get LDO/BUCK QI MODE
+* LDO_BUCK_SET_EN_FORCE: set ldo/buck force enable
+* LDO_BUCK_SET_VOLTAGE: set ldo/buck voltage
+* LDO_BUCK_SET_VOLTAGE_EN: set ldo/buck voltage and enable
+* LDO_BUCK_SET_SLEEP_VOLTAGE: set ldo/buck sleep voltage
+* LDO_BUCK_SET_BURST_THRESHOLD: set ldo/buck burst threshold
+* LDO_BUCK_SET_CURRENT_LIMIT: set ldo/buck current limit
+* LDO_BUCK_SET_VOLTAGE_CALIBRATION_CODE: set ldo/buck voltage calibration code
+* LDO_BUCK_SET_BIAS_CURRENT_CALIBRATION_CODE: set ldo/buck bias current calibration code
+* LDO_BUCK_SET_STB_EN: enable ldo/buck soft start
+* LDO_BUCK_SET_OC_AUTO_OFF: enable to power-off automatically if oc_flag been asserted
+* LDO_BUCK_SET_RS: set ldo/buck local/remote sense
+* LDO_BUCK_SET_ON_SEL: enable control selection, hardware/software
+* LDO_BUCK_SET_STB_TD: set ldo/buck deglitch delay time for soft start
+* LDO_BUCK_SET_NDIS_EN: enable ldo/buck NMOS discharge
+* LDO_BUCK_SET_OC_TD: set ldo/buck deglitch time constant for over-current status from PMU to generate oc_flag
+* LDO_BUCK_SET_OCFB_EN: enable ldo/buck over-current fold-back
+* LDO_BUCK_SET_VSIM_GPLDO_EN: select VSIM LDO enable & voltage controlled by SIM controller or register
+* LDO_BUCK_SET_VSIM2_GPLDO_EN: select VSIM2 LDO enable & voltage controlled by SIM2 controller or register
+* LDO_BUCK_SET_SIM2_GPIO_EN: set SIM2 GPIO enable
+* LDO_BUCK_SET_CCI_SRCLKEN: enable SRCLKENA to PMIC force enable control signal
+* LDO_BUCK_GET_OC_STATUS: Get LDO/BUCK Over Current Status
+* LDO_BUCK_GET_QI_OC_STATUS: Get LDO/BUCK QI Over Current Status
+* LDO_BUCK_SET_THER_SHDN_EN: Set Low Power Mode
+* LDO_BUCK_SET_LP_MODE_SET: Set Low Power Mode
+* LDO_BUCK_SET_LP_SEL: Set Low Power Mode Selection
+* LDO_BUCK_SET_ON_CTRL: On Control Mode
+* LDO_BUCK_SET_MODESET: Switch between force PWM mode and AUTO Mode
+* LDO_BUCK_SET_EN_CTRL: Enable Control
+* LDO_BUCK_SET_EN_SEL: Enable Selection
+* LDO_BUCK_SET_SRCLK_MODE_SEL: HW low power mode srclk selection
+* LDO_BUCK_SET_SRCLK_EN_SEL: SRCLK_EN Selection
+* LDO_BUCK_SET_CMDS_END: For internal use
+* VIBR_SET_DIMMING_ON_DUTY: modify vibrator dimming duty
+* VPA_SET_VOLTAGE: set VPA0-7 voltage
+* VPA_SET_VOSEL_MAP_EN: enables voltage mapping to select VPA_VOSEL from vpa vosel table depending on vpa_table_sel
+* VPA_SET_EN: enable VPA
+* VPA_GET_VOLTAGE_LIST: get VPA supported voltage list
+* VPA_SET_BAT_LOW: BAT_LOW to indicate VPA by-pass mode (6326)
+* VPA_SET_VOLTAGE_SELECTION_TABLE: voltage selection when vpa_vosel_map_en=1
+* VPA_SET_MAP_SEL: Selects one entry in vpa vosel table to use for VPA_VOSEL
+* VRF1_SET_MODESET_CKPDN_SET: Enable VRF1 MODESET Clock
+* VRF1_SET_MODESET_CKPDN_CLR: Disable VRF1 MODESET Clock
+* VRF1_GET_MODESET_CKPDN: Readback VRF1 MODESET Clock
+* SIMLS_SET_SRST_CONF: Set SIMLS_SRST
+* SIMLS_SET_SCLK_CONF: Set SIMLS_SCLK
+* SIMLS_SET_TDSEL: Set SIMLS_TDSEL
+* SIMAP_SET_TDSEL: Set SIMAP_TDSEL
+* SIMLS_SET_RDSEL: Set SIMLS_RDSEL
+* SIMAP_SET_RDSEL: Set SIMAP_RDSEL
+* SIM_SET_STB_SIO_MODE: Set SIM STB SIO Mode
+* SIMRST_SET_GPIO_SET: Set SIMRST GPIO
+* SIMRST_SET_GPIO_CLR: Clear SIMRST GPIO
+* OCTL_SET_SIM_AP_SCLK: Set SIM_AP_SRST
+* OCTL_SET_SIM_AP_SCLK: Set SIM_AP_SCLK
+* OCTL_SET_SIMLS_SCLK: Set SIMLS_SRST
+* OCTL_SET_SIMLS_SCLK: Set SIMLS_SCLK
+* LDO_SET_CAL: ldo output voltage calibration
+* SPK_SET_EN: enable spk
+* SPK_SET_MODE: set spk mode
+* SPK_GET_MODE: get spk mode
+* SPK_SET_OC_AUTO_OFF: enable spk over-current auto off
+* SPK_SET_VOL_VALUE: set spk volume (register value)
+* SPK_GET_VOL_VALUE: get spk volume (register value)
+* SPK_SET_VOL: set spk volume (dbm)
+* SPK_GET_VOL: get spk volume (dbm)
+* SPK_SET_SLEW_RATE: set spk slew rate
+* SPK_SET_CALIBR_EN: set spk Class D offset calibration enable
+* SPK_SET_CALIBR_SEL: set spk Class D offset calibration path
+* KPLED_SET_EN: enable kpled
+* KPLED_SET_MODE: set kpled mode (pwm/register)
+* KPLED_SET_SEL: kpled Turn On Resistor Select
+* KPLED_SET_FREQUENCY_DIVISION: set kpled frequency division
+* KPLED_SET_DIMMING_ON_DUTY: set kpled dimming duty
+* FLASHLED_SET_EN: enable flashled
+* FLASHLED_SET_MODE: set flashled mode (pwm/regsiter)
+* FLASHLED_SET_SEL: kpled Turn On Resistor Select
+* BL_SET_INIT: backlight init mode
+* BL_SET_EN: enable backlight
+* BOOST_SET_EN: enable boost
+* BOOST_SET_CURRENT_LIMIT: set boost current limit
+* BOOST_SET_CLK_CAL: set boost clock cal
+* BOOST_SET_SYNC_EN: enable boost sync
+* BOOST_SET_VOLTAGE: set boost voltage
+* BOOST_SET_LEVEL: set boost level
+* ISINK_SET_EN: enable isink
+* ISINK_SET_MODE: set isink mode
+* ISINK_SET_STEP: set isink step
+* ISINK_SET_FORCE_OFF: set isink force off
+* ISINK_SET_CHANNEL: set isink channel
+* ISINK_SET_DIMMING_ON_DUTY: set kpled dimming duty
+* ISINK_SET_FREQUENCY_DIVISION: set kpled frequency division
+* CHR_SET_ADC_MEASURE_EN: enable adc measure
+* CHR_SET_WDT_CLEAR: clear charger wdt
+* CHR_SET_WDT_TIMER: set charger wdt timer
+* CHR_SET_WDT_INT_EN: enable charger wdt interrupt
+* CHR_SET_WDT_EN: enable charger wdt
+* CHR_SET_CHR_EN: enable charger
+* CHR_SET_CHR_FORCE_EN: force enable charger
+* CHR_GET_CHR_DET_STATUS: get charger detection status
+* CHR_GET_CHR_CURRENT: get charger current
+* CHR_GET_CHR_CURRENT_LIST: get charger current list
+* CHR_SET_CHR_CURRENT: set charger current
+* CHR_GET_CV_DETECTION_STATUS: get CV detection status
+* CHR_SET_CV_DETECTION_EN: enable CV detection
+* CHR_SET_CV_DETECTION_VOLTAGE: set CV voltage
+* CHR_SET_CV_DETECTION_VOLTAGE_CALIBRATION: set CV voltage calibration
+* CHR_SET_CSDAC_EN: enable csdac
+* CHR_GET_IS_BATTERY_ON: check is battery on
+* CHR_GET_IS_CHR_VALID: check is charger valid
+* CHR_SET_HV_DETECTION_VOLTAGE: set HV detection voltage
+* CHR_SET_VBAT_OV_DETECTION_VOLTAGE: set battery OV detection voltage
+* CHR_SET_BAT_HT_EN: enable battery high tempture detection
+* CHR_SET_OTG_BVALID_EN: enable OTG BVALID
+* CHR_SET_CV_MODE: enable CV detect@ charging enable
+* CHR_SET_CSDAC_MODE: enable s/w control
+* CHR_SET_TRACKING_EN: enable HTH/LTH for current tracking
+* CHR_SET_HWCV_EN: enable H/W CV
+* CHR_SET_ULC_DET_EN: enable plug out HW detection
+* CHR_SET_LOW_ICH_DB: set plug out HW detection de-bounce time
+* CHR_GET_CC_DET: get VBAT CC detection result
+* ADC_SET_RQST: AUXADC MD SET request
+* ADC_CLR_RQST: AUXADC MD CLR request
+* ADC_GET_RDY_MD: AUXADC MD Data Ready
+* ADC_GET_OUT_MD: AUXADC channel output data for MD
+* MISC_SET_RLED_EN: enable Red led
+* MISC_SET_GLED_EN: enable green led
+* MISC_SET_BLED_EN: enable blue led
+* MISC_SET_REGISTER_VALUE: set pmu/pmic register value
+* MISC_GET_REGISTER_VALUE: get pmu/pmic register value
+* data: The data of the control command
+* cmd: xxxx : pointer to a PMU_CTRL_xxxx structure
+* ex: LDO_BUCK_SET_EN: pointer to a PMU_CTRL_LDO_BUCK_SET_EN structure
+*
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+* STATUS_UNSUPPORTED: It's a unsupported command.
+*
+*************************************************************************/
+extern DCL_STATUS DclPMU_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclPMU_Close
+*
+* DESCRIPTION
+* This function is to close the PMU module.
+*
+* PARAMETERS
+* handle: the returned handle value of DclPMU_Open
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclPMU_Close(DCL_HANDLE handle);
+
+#define DCL_PMIC_MODULE_CONTROL
+kal_atomic_uint32 DclPMU_GetHrtFlag(void);
+
+#if defined(DCL_PMIC_MODULE_CONTROL)
+extern DCL_FLAGS DclPMU_GetCurrentHandlerFlag(DCL_HANDLE handle);
+#endif
+
+#endif // #ifndef __DCL_PMU_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
diff --git a/mcu/interface/driver/peripheral/dcl_pw.h b/mcu/interface/driver/peripheral/dcl_pw.h
new file mode 100644
index 0000000..8aae50c
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_pw.h
@@ -0,0 +1,425 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for phone on/off control and power on reason
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_PW_H_STRUCT__
+#define __DCL_PW_H_STRUCT__
+
+
+/*******************************************************************************
+ * DCL_OPTIONS for PMU
+ *******************************************************************************/
+#define PW_OPTIONS
+
+ /*******************************************************************************
+ * DCL_CONFIGURE_T for PMU
+ *******************************************************************************/
+
+#define PW_CONFIGS
+
+/*******************************************************************************
+ * DCL_EVENT for PMU
+ *******************************************************************************/
+#define PW_EVENTS
+
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+
+typedef enum{
+ PWRKEYPWRON = 0, /* power on reason is powerkey */
+ CHRPWRON = 1, /* power on reason is charger in */
+ RTCPWRON = 2, /* power on reason is rtc alarm */
+ CHRPWROFF = 3, /* reserved */
+ WDTRESET = 4, /* reserved */
+ ABNRESET = 5, /* power on reason is abnormal reboot */
+ USBPWRON = 6, /* power on reason is usb cable in */
+ USBPWRON_WDT = 7, /* power on reason is usb cable in and abnormal reboot*/
+ PRECHRPWRON = 8, /* power on reason is precharger power on*/
+ UNKNOWN_PWRON = 0xF9 /* power on reason is unknown*/
+}PW_CTRL_POWER_ON_REASON;
+
+typedef enum{
+ PWR_FACTOR_POWER_KEY = 0,
+ PWR_FACTOR_CHARGER_IN,
+ PWR_FACTOR_USB_IN,
+ PWR_FACTOR_RTC_EXPIRE,
+ PWR_FACTOR_WDT_RESET,
+ PWR_FACTOR_NORMAL_RESET_FLG,
+ PWR_FACTOR_CHRPWRON_FLG,
+ PWR_FACTOR_USBMS_PWRON_FLG,
+ PWR_FACTOR_RTCPWRON_FLG,
+ PWR_FACTOR_PRECHRPWRON_FLG,
+ PWR_FACTOR_SWITCH2IDLE_FLG,
+ PWR_FACTOR_SWITCH2CHR_FLG,
+ PWR_FACTOR_SWITCH2USB_FLG,
+ PWR_FACTOR_MAX
+}pwr_factor_enum;
+
+typedef enum{
+ PWR_FACTOR_BL_POWER_KEY = 0x1,
+ PWR_FACTOR_BL_CABLE_IN = 0x2,
+ PWR_FACTOR_BL_RTC_EXPIRE = 0x4,
+ PWR_FACTOR_BL_NORMAL_RESET_FLG = 0x8,
+ PWR_FACTOR_BL_CHRPWRON_FLG = 0x10,
+ PWR_FACTOR_BL_USBMS_PWRON_FLG = 0x20,
+ PWR_FACTOR_BL_RTCPWRON_FLG = 0x40,
+ PWR_FACTOR_BL_FACTORY_FLG = 0x80,
+ PWR_FACTOR_BL_MAX
+}pw_factor_bl_enum;
+
+typedef struct
+{
+ DCL_BOOL val; /* Output : TRUE: indicate usb plug in; FALSE: indicate not usb plug in */
+} PW_CTRL_IS_USB_BOOT;
+
+typedef struct
+{
+ PW_CTRL_POWER_ON_REASON powerOnReason; /* Input : power on reason */
+} PW_CTRL_SET_POWERON_REASON;
+
+typedef struct
+{
+ PW_CTRL_POWER_ON_REASON powerOnReason; /* Output : power on reason */
+} PW_CTRL_GET_POWERON_REASON;
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+#ifdef __BUILD_DOM__
+/* The PW Command Parameter Data Structure for Each Command in DCL_CTRL_DATA_T Enum of dcl.h */
+typedef struct
+{
+ PW_CTRL_SET_POWERON_REASON rPWSetPowerOnReason; /* Data Structure for PW_CMD_SET_POWERON_REASON */
+ PW_CTRL_GET_POWERON_REASON rPWGetPowerOnReason; /* Data Structure for PW_CMD_GET_POWERON_REASON */
+ PW_CTRL_IS_USB_BOOT rPWIsUsbBoot; /* Data Structure for PW_CMD_IS_USB_BOOT */
+}DCL_CTRL_PW_DATA;
+#else /* __BUILD_DOM__ */
+#define PW_CTRLS \
+ PW_CTRL_SET_POWERON_REASON rPWSetPowerOnReason; \
+ PW_CTRL_GET_POWERON_REASON rPWGetPowerOnReason; \
+ PW_CTRL_IS_USB_BOOT rPWIsUsbBoot;
+#endif /* __BUILD_DOM__ */
+
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for PMU
+ *******************************************************************************/
+#ifdef __BUILD_DOM__
+/* The PW Command Values in DCL_CTRL_CMD_T Enum of dcl.h */
+typedef enum {
+ PW_CMD_POWERON, /* call RTC module to latch power and init time if necessary */
+ PW_CMD_POWEROFF, /* call RTC module to unlatch power */
+ PW_CMD_SET_POWERON_REASON, /* set power on reason */
+ PW_CMD_GET_POWERON_REASON, /* get power on reason */
+ PW_CMD_SET_SWITCH_TO_IDLE, /* set flag which force phone to enter idle mode */
+ PW_CMD_CLEAR_SWITCH_TO_IDLE, /* clear flag which force phone to enter idle mode */
+ PW_CMD_POWER_INIT, /* For check power on factors to decide power on reason and save in RTC register */
+ PW_CMD_UPDATE_FLAGS, /* update power on reason to rtc register */
+ PW_CMD_NFB_POWERON, /* call RTC module to latch power and init time if necessary (only for NAND FLASH BOOTING) */
+ PW_CMD_IS_USB_BOOT, /* query is power on reason USB plug in */
+} DCL_CTRL_PW_CMD;
+#else /* __BUILD_DOM__ */
+#define PW_CMDS \
+ PW_CMD_POWERON, \
+ PW_CMD_POWEROFF, \
+ PW_CMD_SET_POWERON_REASON, \
+ PW_CMD_GET_POWERON_REASON, \
+ PW_CMD_SET_SWITCH_TO_IDLE, \
+ PW_CMD_CLEAR_SWITCH_TO_IDLE, \
+ PW_CMD_POWER_INIT, \
+ PW_CMD_UPDATE_FLAGS, \
+ PW_CMD_NFB_POWERON, \
+ PW_CMD_IS_USB_BOOT,
+#endif /* __BUILD_DOM__ */
+
+#ifndef __DRV_DEBUG_PWIC_REG_READ_WRITE__
+#define PW_DRV_ClearBits16(addr, data) DRV_ClearBits(addr,data)
+#define PW_DRV_SetBits16(addr, data) DRV_SetBits(addr,data)
+#define PW_DRV_WriteReg16(addr, data) DRV_WriteReg(addr, data)
+#define PW_DRV_WriteReg32(addr, data) DRV_WriteReg32(addr, data)
+#define PW_DRV_ReadReg16(addr) DRV_Reg(addr)
+#define PW_DRV_ReadReg32(addr) DRV_Reg32(addr)
+#else // #ifndef __DRV_DEBUG_PWIC_REG_READ_WRITE__
+#define PW_DRV_ClearBits16(addr,data) DRV_DBG_ClearBits(addr,data)
+#define PW_DRV_SetBits16(addr) DRV_DBG_SetBits(addr)
+#define PW_DRV_WriteReg16(addr, data) DRV_DBG_WriteReg(addr, data)
+#define PW_DRV_WriteReg32(addr, data) DRV_DBG_WriteReg32(addr, data)
+#define PW_DRV_ReadReg16(addr) DRV_DBG_Reg(addr)
+#define PW_DRV_ReadReg32(addr) DRV_DBG_Reg32(addr)
+#endif // #ifndef __DRV_DEBUG_PWIC_REG_READ_WRITE__
+
+
+#endif // #ifndef __DCL_PMU_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_PW_H_PROTOTYPE__
+#define __DCL_PW_H_PROTOTYPE__
+
+
+
+/*************************************************************************
+* FUNCTION
+* DclPW_Initialize
+*
+* DESCRIPTION
+* This function is to initialize PW module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclPW_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclPW_Open
+*
+* DESCRIPTION
+* This function is to open the PW module and return a handle
+*
+* PARAMETERS
+* dev: only valid for DCL_PW
+* flags: no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Open failed.
+* other value: a valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclPW_Open(DCL_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* DclPW_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the PW module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclPW_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclPW_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the PW module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclPW_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclPW_Configure
+*
+* DESCRIPTION
+* This function is not supported for the PW module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclPW_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+/*************************************************************************
+* FUNCTION
+* DclPW_RegisterCallback
+*
+* DESCRIPTION
+* This function is not supported for the PW module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclPW_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+/*************************************************************************
+* FUNCTION
+* DclPW_Control
+*
+* DESCRIPTION
+* This function is to send command to control the PW module.
+* All command
+*
+* CALLS
+* It is called to send command to control the PW module.
+*
+* PARAMETERS
+* handle: [IN] The handle value returned from DclPW_Open()
+* cmd: [IN] A control command for PW module
+* 1. PW_CMD_POWERON: call RTC module to latch power and init time if necessary
+* 2. PW_CMD_POWEROFF: call RTC module to unlatch power
+* 3. PW_CMD_SET_POWERON_REASON: set power on reason
+* 4. PW_CMD_GET_POWERON_REASON: get power on reason
+* 5. PW_CMD_SET_SWITCH_TO_IDLE: set flag which force phone to enter idle mode
+* 6. PW_CMD_CLEAR_SWITCH_TO_IDLE: clear flag which force phone to enter idle mode
+* 7. PW_CMD_POWER_INIT: check power on factors to decide power on reason and save in RTC register
+* 8. PW_CMD_UPDATE_FLAGS: update power on reason to rtc register
+* 9. PW_CMD_NFB_POWERON: call RTC module to latch power and init time if necessary (only for NAND FLASH BOOTING)
+* 10. PW_CMD_IS_USB_BOOT: query is power on reason USB plug in
+*
+* data: The data of the control command
+* 1. PW_CMD_POWERON: A null pointer
+* 2. PW_CMD_POWEROFF: A null pointer
+* 3. PW_CMD_SET_POWERON_REASON: pointer to a PW_CTRL_SET_POWERON_REASON structure
+* 4. PW_CMD_GET_POWERON_REASON: pointer to a PW_CTRL_GET_POWERON_REASON structure
+* 5. PW_CMD_SET_SWITCH_TO_IDLE: A null pointer
+* 6. PW_CMD_CLEAR_SWITCH_TO_IDLE: A null pointer
+* 7. PW_CMD_POWER_INIT: A null pointer
+* 8. PW_CMD_UPDATE_FLAGS: A null pointer
+* 9. PW_CMD_NFB_POWERON: A null pointer
+* 10. PW_CMD_IS_USB_BOOT: pointer to a PW_CTRL_IS_USB_BOOT
+*
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+* STATUS_UNSUPPORTED: It's a unsupported command.
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclPW_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclPW_Close
+*
+* DESCRIPTION
+* This function is to close the PW module.
+*
+* PARAMETERS
+* handle: the returned handle value of DclPW_Open
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclPW_Close(DCL_HANDLE handle);
+
+
+#endif // #ifndef __DCL_PW_H_PROTOTYPE__
+
+#endif //#ifdef DCL_DEFINITION_PROTOTYPE
+
+
+
diff --git a/mcu/interface/driver/peripheral/dcl_pwm.h b/mcu/interface/driver/peripheral/dcl_pwm.h
new file mode 100644
index 0000000..0566df9
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_pwm.h
@@ -0,0 +1,603 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_PWM.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for PWM.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_PWM_H_STRUCT__
+#define __DCL_PWM_H_STRUCT__
+//#include "kal_non_specific_general_types.h" //it is empty ,we don't delete it in order to avoid vilating HAL rule 1
+
+#include "kal_general_types.h"
+#define PWM_OUTPUT_LOW 0
+#define PWM_OUTPUT_HIGH 1
+//******************************************
+#define PWM_MAX_FREQ 50000
+#define PWM_MAX_DUTY 100
+#define PWM_MIN_FREQ 50
+#define PWM_MIN_DUTY 1
+//******************************************
+typedef struct
+{
+ DCL_UINT8 pitch; /*note vlaue*/
+ DCL_UINT8 volume; /*note volume*/
+ DCL_UINT16 on_duration; /* in ms */
+ DCL_UINT16 off_duration; /* in ms */
+}BuzNoteStruct;
+
+typedef struct
+{
+ DCL_UINT8 volume;
+ DCL_UINT8 stop;
+ DCL_UINT32 handle; /*GPT handle*/
+ BuzNoteStruct NotesData;
+ kal_bool (*GetNotesCallbac)(BuzNoteStruct *Buz);
+ void (*EndofAlterPlay)(void);
+}ALterNoteStruct;
+
+/* PWM wrok mode enumerate*/
+typedef enum
+{
+ PWM_FIFO_MODE=0,
+ PWM_MEMO_MODE,
+ PWM_OLD_MODE,
+ PWM_RANDOM_MODE,
+ PWM_MODE_COUNT
+}pwm_mode_e;
+
+/*PWM FIFO mode data structure.[more detail in spec]*/
+typedef struct
+{
+ kal_uint32 data0;
+ kal_uint32 data1;
+ kal_uint16 repeat_count; /* 0 means endless repeat */
+ kal_uint8 stop_bitpos; /* 0~63*/
+ kal_uint16 high_dur; /* must>0. When set to N, the duration is N+1 clocks. */
+ kal_uint16 low_dur; /* must>0. When set to N, the duration is N+1 clocks. */
+ kal_uint16 guard_dur; /* must>0. When set to N, the duration is N+1 clocks. */
+ kal_uint8 idle_output; /* PWM_OUTPUT_LOW or PWM_OUTPUT_HIGH */
+ kal_uint8 guard_output; /* PWM_OUTPUT_LOW or PWM_OUTPUT_HIGH */
+ void (*pwm_callback)(kal_uint32 pwm_num);
+}pwm_fifo_para_s;
+
+/*PWM memory mode data structure.[more detail in spec] */
+typedef struct
+{
+ kal_uint32 *buf_addr;
+ kal_uint16 buf_size;
+ kal_uint16 repeat_count; /* 0 means endless repeat */
+ kal_uint8 stop_bitpos; /* 0~31 in the last 32bits*/
+ kal_uint16 high_dur; /* must>0. When set to N, the duration is N+1 clocks. */
+ kal_uint16 low_dur; /* must>0. When set to N, the duration is N+1 clocks. */
+ kal_uint16 guard_dur; /* must>0. When set to N, the duration is N+1 clocks. */
+ kal_uint8 idle_output; /* PWM_OUTPUT_LOW or PWM_OUTPUT_HIGH */
+ kal_uint8 guard_output; /* PWM_OUTPUT_LOW or PWM_OUTPUT_HIGH */
+ void (*pwm_callback)(kal_uint32 pwm_num);
+}pwm_memo_para_s;
+
+/*PWM old mode data structure.[more detail in spec]*/
+typedef struct
+{
+ kal_uint16 data_width;
+ kal_uint16 threshold;
+ kal_uint16 repeat_count; /* 0 means endless repeat */
+ kal_uint16 guard_dur; /* must>0. When set to N, the duration is N+1 clocks. */
+ kal_uint8 idle_output; /* PWM_OUTPUT_LOW or PWM_OUTPUT_HIGH */
+ kal_uint8 guard_output; /* PWM_OUTPUT_LOW or PWM_OUTPUT_HIGH */
+ void (*pwm_callback)(kal_uint32 pwm_num);
+}pwm_old_para_s;
+
+/*PWM random mode data structure.[more detail in spec]*/
+typedef struct
+{
+ kal_uint32 *buf0_addr;
+ kal_uint32 *buf1_addr;
+ kal_uint16 buf0_size; /* must>0 */
+ kal_uint16 buf1_size; /* must>0 */
+ kal_uint16 high_dur; /* must>0. When set to N, the duration is N+1 clocks. */
+ kal_uint16 low_dur; /* must>0. When set to N, the duration is N+1 clocks. */
+ kal_uint8 idle_output; /* PWM_OUTPUT_LOW or PWM_OUTPUT_HIGH */
+ void (*pwm_invalid_cb)(kal_uint32 pwm_num, kal_uint8 buf_num);
+ void (*pwm_underflow_cb)(kal_uint32 pwm_num);
+}pwm_random_para_s;
+
+typedef struct
+{
+ DCL_UINT32 clksrc; //the Clock source of the PWM module.
+ DCL_UINT32 clkdiv; //The Clock Divisor value.
+}PWM_CONFIG_T;
+
+#define PWM_CONFIGS \
+ PWM_CONFIG_T rPWMConfig;
+
+#ifdef __BUILD_DOM__
+/*
+* The ALERTER Command values in DCL_CTRL_CMD_T Enum of dcl.h
+* DCL_CTRL_DATA_T Define the Control data structure for each module's command
+*/
+typedef enum
+{
+ PWM_CMD_SEQ_OPEN, //This command is to open the PWM channel under the Sequential mode.
+ PWM_CMD_SEQ_START, //This command is to enable PWM output under the Sequential mode.
+ PWM_CMD_SEQ_STOP, //This command is to stop PWM output under the Sequential mode.
+ PWM_CMD_SEQ_CLOSE, //This command is to Close the PWM channel under the Sequential mode.
+ PWM_CONFIG_FREQ_STEPS, //The command is to set the output frequency and the steps.it is used by the Camera AF lens driver.
+ PWM_CMD_SET_DUTY, //The function is to set the output duty value, it should not larger than the Steps in the above function.it is used by the Camera AF lens driver.
+ PWM_CMD_OPEN, //This command is to Open PWM channel.This command should be called before any other configuration function.
+ PWM_CMD_CLOSE, //The function is to close the PWM channel.it should be called after stop the PWM channel.
+ PWM_CMD_START, //This command is to Start the PWM channel output.It is called after all the configuration finished
+ PWM_CMD_STOP, //This command is to stop the PWM channel output.
+ PWM_CMD_CONFIG, //This command is to configure the PWM channel working mode and setting the accoring mode parameter.
+ PWM_CMD_CONFIG_OLD, //This command is to configure the PWM1 output frequency and duty cycle.the function is to generate the simpliest periodical output signal.
+ PWM_CMD_SET_BUF_VALID, //Set buffer status to be valid and update the buffer data.the function is called when receiving the finish interrupt under the random mode.it is responsible to call the function to update the buffer of the user.
+ PWM_CMD_SET_DELAY, //This command is to set the delay time during the adjacent channels under the Sequential mode.
+ //PWM_CMD_TEST_SEL, should remove.
+ PWM_CMD_GET_CURRENT_LEVEL, //This command is to get current PWM1 output level.
+ PWM_CMD_GET_CURRENT_DUTY, //This command is to get current PWM1 output duty cycle.
+ PWM_CMD_GET_CURRENT_FREQ, //This command is to get current PWM1 output duty cycle.
+ ALERTER_CMD_CONFIGURE, //configure ALerter freq and duty.
+ ALERTER_CMD_START, //Start ALERTER module.
+ ALERTER_CMD_STOP, //Stop ALERTER module.
+ ALERTER_CMD_PWROPEN,
+ ALERTER_CMD_OUTPUT,
+ ALERTER_CMD_PLAYNOTES,
+ ALERTER_CMD_STOPNOTES,
+ ALERTER_CMD_SETBUZVOLUME,
+ ALERTER_CMD_GETLEVEL,
+}DCL_CTRL_CMD_T;
+#else
+#define PWM_CMDS \
+ PWM_CMD_SEQ_OPEN, \
+ PWM_CMD_SEQ_START, \
+ PWM_CMD_SEQ_STOP, \
+ PWM_CMD_SEQ_CLOSE, \
+ PWM_CONFIG_FREQ_STEPS, \
+ PWM_CMD_START, \
+ PWM_CMD_STOP, \
+ PWM_CMD_GET_CURRENT_LEVEL, \
+ PWM_CMD_GET_CURRENT_DUTY, \
+ PWM_CMD_GET_CURRENT_FREQ, \
+ PWM_CMD_CONFIG, \
+ PWM_CMD_CONFIG_OLD, \
+ PWM_CMD_SET_BUF_VALID, \
+ PWM_CMD_SET_DELAY, \
+ PWM_CMD_SET_DUTY, \
+ PWM_CMD_TEST_SEL, \
+ PWM_CMD_OPEN, \
+ PWM_CMD_CLOSE,
+
+#define ALERTER_CMDS \
+ ALERTER_CMD_CONFIGURE, \
+ ALERTER_CMD_START, \
+ ALERTER_CMD_STOP, \
+ ALERTER_CMD_PWROPEN, \
+ ALERTER_CMD_OUTPUT, \
+ ALERTER_CMD_PLAYNOTES, \
+ ALERTER_CMD_STOPNOTES, \
+ ALERTER_CMD_SETBUZVOLUME, \
+ ALERTER_CMD_GETLEVEL,
+
+#endif
+
+/* For PWM_CMD_SEQ_START command parameter. */
+typedef struct
+{
+ DCL_UINT8 uEnCount; //the PWM Channel Group of the Sequential mode
+}PWM_CTRL_SS_T;
+
+/* For PWM_CMD_CLK_INIT command parameter. */
+typedef struct
+{
+ DCL_UINT32 u4ClkSel; //the Clock source of the PWM module.
+ DCL_UINT32 u4ClkDiv; // The Clock Divisor value.
+}PWM_CTRL_CI_T;
+
+/* For PWM_CMD_SET_BUF_VALID command parameter. */
+typedef struct
+{
+ DCL_UINT32 *pu4BufAddr; //the buffer address of the update data.
+ DCL_UINT16 u2BufSize; //the buffer size.
+ DCL_BOOL fgIsBuf0; //the flag indicates whether buffer 0 is to be update
+}PWM_CTRL_SBV_T;
+
+/* For PWM_CMD_SET_DELAY command parameter. */
+typedef struct
+{
+ DCL_UINT32 u4ClkSel; // the clock unit of the delay_cnt
+ DCL_UINT16 u2DelayCnt; //the delay clock count of the two channels.
+}PWM_CTRL_SD_T;
+
+/* For PWM_CMD_TEST_SEL command parameter. */
+typedef struct
+{
+ DCL_BOOLEAN bTestSel;
+}PWM_CTRL_TS_T;
+
+/* For PWM_CMD_CONFIG command parameter. */
+typedef struct
+{
+ DCL_UINT32 mode; //Set the work mode of the PWM channel.
+ void *para; // The mode parameter.
+}PWM_CTRL_CONFIG_T;
+
+/* For PWM_CMD_CONFIG_OLD command parameter. */
+typedef struct
+{
+ kal_uint32 freq; // the PWM channel output frequency.
+ kal_uint8 duty; // the duty cycle of the high level under the periodical output.
+}PWM_CMD_CONFIG_OLD_T;
+
+/*For
+* PWM_CMD_GET_CURRENT_LEVEL,
+* PWM_CMD_GET_CURRENT_DUTY,
+* PWM_CMD_GET_CURRENT_FREQ,
+* command parameter
+*/
+typedef struct
+{
+ DCL_UINT8 pwm_level;//return value of the command , the current level value
+ DCL_UINT8 pwm_duty; //return value of the command ,the current setting duty cycle value
+ DCL_UINT32 pwm_freq;//return value of the command ,the current setting frequency value
+}PWM_DATA_T;
+
+/*For PWM_CMD_SET_DUTY command parameter.*/
+typedef struct
+{
+ DCL_UINT16 duty; //the output duty value (0~steps).
+}PWM_DUTY_T;
+
+/*For PWM_CONFIG_FREQ_STEPS command parameter.*/
+typedef struct
+{
+ kal_uint32 freq; //the output frequency.
+ kal_uint16 steps; //the lens driver steps.
+}PWM_CONFIG_FREQ_STEPS_T;
+
+//#if !defined(DRV_ALERTER_NOT_EXIST)
+typedef struct
+{
+ DCL_UINT32 freq;
+ DCL_UINT8 duty;
+}ALERTER_CONFIGURE_T;
+
+typedef struct
+{
+ DCL_BOOL poweron;
+}ALERTER_PWROPEN_T;
+
+typedef struct
+{
+ kal_bool (*GetNotecallbac)(BuzNoteStruct *Buz);
+ void (*endofAlter)(void);
+}ALERTER_PLAYNOTE_T;
+
+typedef struct
+{
+ DCL_UINT8 volumn;
+}ALERTER_SETVOLUMN_T;
+
+typedef struct
+{
+ DCL_UINT8 mode;
+ DCL_UINT8 clock;
+}ALERTER_CONFIG_T;
+
+typedef struct
+{
+ kal_uint8 output;
+}ALERTER_OUTPUT_T;
+
+typedef struct
+{
+ kal_uint8 level;
+}ALERTER_LEVEL_T;
+
+#define ALERTER_CTRLS \
+ ALERTER_CONFIGURE_T ralertConfigure; \
+ ALERTER_PWROPEN_T ralertPwrOpen; \
+ ALERTER_PLAYNOTE_T ralertPlayNote; \
+ ALERTER_SETVOLUMN_T ralertSetVolumn; \
+ ALERTER_CONFIG_T ralertConfig; \
+ ALERTER_OUTPUT_T ralertOutput; \
+ ALERTER_LEVEL_T ralertlevel;
+
+
+#define PWM_CTRLS \
+ PWM_CTRL_SS_T rPWMCtrlSS; \
+ PWM_CTRL_CI_T rPWMCtrlCI; \
+ PWM_CTRL_SBV_T rPWMCtrlSBV; \
+ PWM_CTRL_SD_T rPWMCtrlSD; \
+ PWM_CTRL_TS_T rPWMCtrlTS; \
+ PWM_DUTY_T rPWMCtrlDuty; \
+ PWM_DATA_T rPWMSaveData; \
+ PWM_CTRL_CONFIG_T rPWMConfig; \
+ PWM_CONFIG_FREQ_STEPS_T rPWMFreqConfig; \
+ PWM_CMD_CONFIG_OLD_T rPWMConfigOld;
+
+#endif // #ifndef __DCL_PWM_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_PWM_H_PROTOTYPE__
+#define __DCL_PWM_H_PROTOTYPE__
+
+/*************************************************************************
+* FUNCTION
+* DclPWM_Close
+*
+* DESCRIPTION
+* This function is to close the software layer of PWM module.
+*
+* CALLS
+* It is called to close PWM(1~6) module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* DCL_STATUS_OK
+* STATUS_INVALID_ARGUMENT: invalid arguments
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclPWM_Close(DCL_HANDLE handle);
+/*************************************************************************
+* FUNCTION
+* DclPWM_Configure
+*
+* DESCRIPTION
+* This function is to configure the PWM module. Include clock sources and div vaules.
+*
+* CALLS
+* It is called to configure of the PWM module.
+*
+* PARAMETERS
+* handle: - a valid handle return by DclPWM_Configure()
+*
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclPWM_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+/*************************************************************************
+* FUNCTION
+* DclPWM_Control
+*
+* DESCRIPTION
+* This function is to send command to control the PWM module.
+* All command
+*
+* CALLS
+* It is called to send command to control the PWM module.
+*
+* PARAMETERS
+* handle: - a valid handle return by DclPWM_Open()
+* cmd: - a control command for PWM module
+* 1. PWM_CMD_START: to start a PWM timer
+* 2. PWM_CMD_STOP: to stop a PWM timer
+* 3. PWM_CMD_CONFIG: to config a pwm timer.
+* 4. PWM_CMD_CONFIG_OLD
+* 5. PWM_CMD_GET_CURRENT_LEVEL:
+* 6. PWM_CMD_GET_CURRENT_DUTY:
+* 7. PWM_CMD_GET_CURRENT_FREQ:
+* 8. PWM_CMD_OPEN
+* 9. PWM_CMD_CLOSE
+* 10. PWM_CMD_SEQ_OPEN:
+* 11. PWM_CMD_SEQ_START:
+* 12. PWM_CMD_SEQ_STOP:
+* 13. PWM_CMD_SEQ_CLOSE
+* 14. PWM_CMD_SET_BUF_VALID
+* 15. PWM_CMD_SET_DELAY
+* 16. PWM_CMD_TEST_SEL
+* data - for 1. PWM_CMD_START: poiter to a PWM_CTRL_START_T structure
+* 2. PWM_CMD_STOP: a NULL pointer
+* #if !defined(DRV_ALERTER_NOT_EXIST)
+ #define ALERTER_CMDS
+ ALERTER_CMD_CONFIGURE, \
+ ALERTER_CMD_START, \
+ ALERTER_CMD_STOP, \
+ ALERTER_CMD_PWROPEN, \
+ ALERTER_CMD_OUTPUT, \
+ ALERTER_CMD_PLAYNOTES, \
+ ALERTER_CMD_STOPNOTES, \
+ ALERTER_CMD_SETBUZVOLUME,
+ #endif
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclPWM_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclPWM_Initialize
+*
+* DESCRIPTION
+* This function is to initialize PWM module, It's should be called during drv_init stage.
+*
+* For PWM, this function do nothing.
+*
+* For RWG, this function create some global variable and LISR, HISR.
+*
+* CALLS
+* It is called to initialize PWM module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* DCL_STATUS_OK
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclPWM_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclPWM_Open
+*
+* DESCRIPTION
+* This function is to open the software layer PWM module and return a software handle.
+* This function don't open the PWM hardware power or generate out wave.
+* This is only for software layer to avoid multi open by different module.
+*
+* If you want to power on or start PWM hardware , you should send a command by use of DclPWM_Control.
+* CALLS
+* It is called to open PWM module
+*
+* PARAMETERS
+* dev - valid for DCL_PWM1 ~ DCL_PWM6
+* flags - module name that call this fuction.
+*
+* RETURNS
+* DCL_HANDLE_OCCUPIED: - Open failed.
+* STATUS_INVALID_ARGUMENT: - invalid arguments
+* other value: - a valid handle
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_HANDLE DclPWM_Open(DCL_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* DclPWM_RegisterCallback
+*
+* DESCRIPTION
+* This function is not supported for the PWM module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclPWM_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+
+#endif // #ifndef __DCL_PWM_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
+
+
diff --git a/mcu/interface/driver/peripheral/dcl_pxs.h b/mcu/interface/driver/peripheral/dcl_pxs.h
new file mode 100644
index 0000000..15a340a
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_pxs.h
@@ -0,0 +1,393 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_pxs.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for proximity sensor.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_PXS_H_STRUCT__
+#define __DCL_PXS_H_STRUCT__
+
+/*******************************************************************************
+ * DCL_OPTIONS for PXS
+ *******************************************************************************/
+#define PXS_OPTIONS
+
+/*******************************************************************************
+ * DCL_CONFIGURE_T for PXS
+ *******************************************************************************/
+typedef void (*PFN_DCL_PXS_NOTIFY_CALLBACK)(DCL_BOOL fgObjectDetected);
+
+typedef enum
+{
+ PXS_COMPARE_WINDOW, // Comparing window of PXS thresold algorithm
+ PXS_HILO_THRESHOLD, // HIGH/LOW thresold methodology
+ PXS_ADV_ALGO_MAX
+} PXS_ADV_ALGO_ENUM;
+
+typedef struct
+{
+ DCL_BOOL fgNotify;
+ PFN_DCL_PXS_NOTIFY_CALLBACK NotifyCallback;
+} PXS_CONFIG_T, PXS_CTRL_CONFIG_T;
+
+#define PXS_CONFIGS \
+ PXS_CONFIG_T rPXSConfig;
+
+/*******************************************************************************
+ * DCL_EVENT for PXS
+ *******************************************************************************/
+#define PXS_EVENTS
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for PXS
+ *******************************************************************************/
+#define PXS_CMDS \
+ PXS_CMD_ENABLE, \
+ PXS_CMD_GET_RAW_DATA, \
+ PXS_CMD_EM_READ, \
+ PXS_CMD_EM_WRITE, \
+ PXS_CMD_GET_ADV_ALGO_WINDOWING, \
+ PXS_CMD_GET_ADV_ALGO_THRESHOLD, \
+ PXS_CMD_MODIFY_CONFIG, \
+ PXS_CMD_GET_SENSITIVITY_LEVEL_NUM, \
+ PXS_CMD_SET_SENSITIVITY_LEVEL, \
+ PXS_CMD_GET_DETECT_STATUS, \
+ PXS_CMD_SET_DEBOUNCE, \
+
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+
+
+typedef enum
+{
+ PXS_HW_CMD_POWER_ENABLE,
+ PXS_HW_CMD_GET_SENSITIVITY_LEVEL_NUM,
+ PXS_HW_CMD_GET_SENSITIVITY_TABLE,
+}PXS_HW_CMD_ENUM;
+
+/* For PXS_CMD_ENABLE command. */
+typedef struct
+{
+ DCL_BOOL fgEnable;
+}PXS_CTRL_ENABLE_T;
+
+/* For PXS_CMD_GET_RAW_DATA command. */
+typedef struct
+{
+ DCL_UINT16 u2Data;
+}PXS_CTRL_RAW_DATA_T;
+
+/* For PXS_CMD_EM_ADV_ALGO_WINDOWING command. */
+//typedef struct
+//{
+// DCL_UINT16 u2Count;
+//}PXS_CTRL_EM_WINDOWING_T;
+
+/* For PXS_CMD_EM_ADV_ALGO_THRESHOLD command. */
+//typedef struct
+//{
+// DCL_UINT16 u2HiThreshold;
+// DCL_UINT16 u2LoThreshold;
+//}PXS_CTRL_EM_THRESHOLD_T;
+
+/* For PXS_CMD_EM_READ, PXS_CMD_EM_WRITE command. */
+typedef struct
+{
+ DCL_UINT32 u4P1;
+ DCL_UINT32 u4P2;
+ DCL_UINT32 u4P3;
+ DCL_UINT32 u4P4;
+ DCL_UINT32 u4P5;
+ DCL_UINT32 u4P6;
+ DCL_UINT32 u4P7;
+ DCL_UINT32 u4P8;
+ DCL_UINT32 u4PollingPeriod; // EM polling period, unit by ms
+}PXS_CTRL_EM_PARAM_T;
+
+/* For PXS_CMD_GET_ADV_ALGO_WINDOWING command. */
+typedef struct
+{
+ DCL_UINT16 u2Count;
+}PXS_CTRL_GET_ADV_ALGO_WINDOWING_T;
+
+/* For PXS_CMD_GET_ADV_ALGO_THRESHOLD command. */
+typedef struct
+{
+ DCL_UINT16 u2HiThreshold;
+ DCL_UINT16 u2LoThreshold;
+}PXS_CTRL_GET_ADV_ALGO_THRESHOLD_T;
+
+/* For PXS_CMD_GET_SENSITIVITY_LEVEL_NUM command. */
+typedef struct
+{
+ DCL_UINT16 u2LevelNum;
+}PXS_CTRL_GET_SENSITIVITY_LEVEL_NUM_T;
+
+/* For PXS_CMD_SET_SENSITIVITY_LEVEL command. */
+typedef struct
+{
+ DCL_UINT16 u2Level;
+}PXS_CTRL_SET_SENSITIVITY_LEVEL_T;
+
+/* For PXS_CMD_GET_DETECT_STATUS command. */
+typedef struct
+{
+ DCL_BOOL fgDetected;
+}PXS_CTRL_GET_DETECT_STATUS_T;
+
+
+/* For PXS_CMD_SET_DEBOUNCE command. */
+typedef struct
+{
+ DCL_UINT32 u4TopAreaDebounce; //ms
+ DCL_UINT32 u4LargerAreaDebounce; //ms
+}PXS_CTRL_SET_DEBOUNCE_T;
+
+#define PXS_CTRLS \
+ PXS_CTRL_ENABLE_T rPXSEnable; \
+ PXS_CTRL_RAW_DATA_T rPXSRawData; \
+ PXS_CTRL_EM_PARAM_T rPXSEMParam; \
+ PXS_CTRL_GET_ADV_ALGO_WINDOWING_T rPXSAdvAlgoWindowing; \
+ PXS_CTRL_GET_ADV_ALGO_THRESHOLD_T rPXSAdvAlgoThreshold; \
+ PXS_CTRL_CONFIG_T rPXSConfig; \
+ PXS_CTRL_GET_SENSITIVITY_LEVEL_NUM_T rPXSSensitivityLevelNum; \
+ PXS_CTRL_SET_SENSITIVITY_LEVEL_T rPXSSensitivityLevel; \
+ PXS_CTRL_GET_DETECT_STATUS_T rPXSDetectStatus; \
+ PXS_CTRL_SET_DEBOUNCE_T rPXSSetDebounce;
+
+
+
+#endif // #ifndef __DCL_PXS_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_PXS_H_PROTOTYPE__
+#define __DCL_PXS_H_PROTOTYPE__
+
+/*************************************************************************
+* FUNCTION
+* DclPXS_Initialize
+*
+* DESCRIPTION
+* This function is to initialize PXS module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclPXS_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclPXS_Open
+*
+* DESCRIPTION
+* This function is to open the PXS module and return a handle
+*
+* PARAMETERS
+* dev: only valid for DCL_PXS
+* flags: no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Open failed
+* Other value: A valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclPXS_Open(DCL_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* DclPXS_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the PXS module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclPXS_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclPXS_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the PXS module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclPXS_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclPXS_Configure
+*
+* DESCRIPTION
+* This function is to configure the PXS module.
+*
+* PARAMETERS
+* handle: the returned handle value of DclPXS_Open
+* configure: a structure which include the PXS configuration.
+*
+* RETURNS
+* STATUS_OK: Successfully configure PXS module.
+* STATUS_INVALID_HANDLE: It's a invalid handle.
+* STATUS_NOT_OPENED: The module has not been opened.
+* STATUS_INVALID_CONFIGURATION: The configuration is invalid.
+*
+*************************************************************************/
+extern DCL_STATUS DclPXS_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+/*************************************************************************
+* FUNCTION
+* DclPXS_RegisterCallback
+*
+* DESCRIPTION
+* This function is to set callback function for the PXS module.
+*
+* PARAMETERS
+* handle: the returned handle value of DclPXS_Open
+* event: Supported events:
+* callback: the callback function for registered events
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclPXS_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+/*************************************************************************
+* FUNCTION
+* DclPXS_Control
+*
+* DESCRIPTION
+* This function is to send command to control the PXS module.
+*
+* PARAMETERS
+* handle: The handle value returned from DclPXS_Open
+* cmd: A control command for PXS module
+* 1. PXS_CMD_ENABLE: to enable/disable PXS function
+* 2. PXS_CMD_GET_RAW_DATA: to get PXS sampled raw data
+* 3. PXS_CMD_EM_READ: to read EM parameters
+* 4. PXS_CMD_EM_WRITE: to write EM parameters
+* 5. PXS_CMD_GET_DETECT_STATUS: to get PXS detected status
+* data: The data of the control command
+* 1. PXS_CMD_ENABLE: pointer to a PXS_CTRL_ENABLE_T structure
+* 2. PXS_CMD_GET_RAW_DATA: pointer to a PXS_CTRL_RAW_DATA_T structure
+* 3. PXS_CMD_EM_READ: pointer to a PXS_CTRL_EM_PARAM_T structure
+* 4. PXS_CMD_EM_WRITE: pointer to a PXS_CTRL_EM_PARAM_T structure
+* 5. PXS_CMD_GET_DETECT_STATUS: pointer to a PXS_CTRL_GET_DETECT_STATUS_T structure
+*
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+* STATUS_UNSUPPORTED: The command is NOT supported
+*
+*************************************************************************/
+extern DCL_STATUS DclPXS_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclPXS_Close
+*
+* DESCRIPTION
+* This function is to close the PXS module.
+*
+* PARAMETERS
+* handle: the returned handle value of DclPXS_Open
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclPXS_Close(DCL_HANDLE handle);
+
+
+
+// Low level PXS driver (DclHPXS_XXX interfaces)
+extern DCL_STATUS DclHPXS_Initialize(void);
+extern DCL_HANDLE DclHPXS_Open(DCL_DEV dev, DCL_FLAGS flags);
+extern DCL_STATUS DclHPXS_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+extern DCL_STATUS DclHPXS_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+extern DCL_STATUS DclHPXS_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+extern DCL_STATUS DclHPXS_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+extern DCL_STATUS DclHPXS_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+extern DCL_STATUS DclHPXS_Close(DCL_HANDLE handle);
+
+
+
+
+
+#endif // #ifndef __DCL_PXS_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
+
+
diff --git a/mcu/interface/driver/peripheral/dcl_rtc.h b/mcu/interface/driver/peripheral/dcl_rtc.h
new file mode 100644
index 0000000..8a04d52
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_rtc.h
@@ -0,0 +1,893 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_rtc.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for RTC.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_RTC_H_STRUCT__
+#define __DCL_RTC_H_STRUCT__
+
+/*******************************************************************************
+ * DCL_OPTIONS for RTC
+ *******************************************************************************/
+#define RTC_OPTIONS
+
+ /*******************************************************************************
+ * DCL_CONFIGURE_T for RTC
+ *******************************************************************************/
+#define RTC_CONFIGS
+
+/*******************************************************************************
+ * DCL_EVENT for RTC
+ *******************************************************************************/
+#define RTC_EVENTS \
+ EVENT_RTC_ALARM = 0x00000001,\
+ EVENT_RTC_TC = 0x00000002,
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for RTC
+ *******************************************************************************/
+#ifdef __BUILD_DOM__
+/* The RTC Command Values in DCL_CTRL_CMD_T Enum of dcl.h */
+typedef enum {
+ RTC_CMD_BOOTLOADER_POWERON, /* For RTC Bootloader Power On */
+ RTC_CMD_CLEAR_PDN_BITS, /* To Clear RTC PDN Bits */
+ RTC_CMD_CONFIG_AL_TC, /* To Configure the RTC Interrupt */
+ RTC_CMD_DELAY, /* To Delay */
+ RTC_CMD_FT_POWEROFF, /* For Flash Tool Power Off */
+ RTC_CMD_GET_ALARM_TIME, /* To Get Alarm Time */
+ RTC_CMD_GET_TIME, /* To Get Time*/
+ RTC_CMD_GPIO_GET_INPUT, /* To Get GPIO Input */
+ RTC_CMD_GPIO_SET_EXPORT_32K, /* To Set Export 32K for GPIO */
+ RTC_CMD_GPIO_SET_EXPORT_COREDETB, /* To Set Export COREDETB for GPIO */
+ RTC_CMD_GPIO_SET_INPUT_MODE, /* To Set GPIO Input Mode */
+ RTC_CMD_GPIO_SET_OUTPUT_MODE, /* To Set GPIO Output Mode */
+ RTC_CMD_HW_INIT, /* To Initialize RTC HW */
+ RTC_CMD_INIT, /* To Initialize RTC SW */
+ RTC_CMD_INIT_TC_AL_INTR, /* To Initialize RTC SW (RTC_TCintr,RTC_ALintr) */
+ RTC_CMD_IS_CONFIG_VALID, /* To Check If RTC Configure Valid or Not */
+ RTC_CMD_IS_FIRST_ON, /* To Check If RTC Is First On or Not */
+ RTC_CMD_IS_MS_FIRSTPOWERON, /* To Check If RTC Is First On or Not (for MMI Only) */
+ RTC_CMD_IS_TIME_VALID, /* To Check If RTC Time Is Valid or Not */
+ RTC_CMD_PWIC_CHECK_POWERON, /* To Check RTC Power On (for PWIC Only) */
+ RTC_CMD_PWIC_FIRST_POWERON_INIT_RTCTIME, /* To Initialize RTC Time When First Power On (for PWIC Only) */
+ RTC_CMD_PWIC_MASK_AL, /* To Diable All Alarm Mask (for PWIC Only) */
+ RTC_CMD_PWIC_POWEROFF_RTC_INIT, /* To Do RTC Initalize When Power Off (for PWIC Only) */
+ RTC_CMD_PWIC_POWERON_RTC_INIT, /* To Do RTC Initalize When Power On (for PWIC Only) */
+ RTC_CMD_READ_PDN_BITS, /* To Read RTC PDN Bits */
+ RTC_CMD_READ_SPAR, /* To Read SPAR Register */
+ RTC_CMD_READ_XOSC_REG, /* To Read RTC XOSC Register */
+ RTC_CMD_RELOAD, /* To Do RTC Reload */
+ RTC_CMD_SET_ALARM_TIME, /* To Set Alarm Time */
+ RTC_CMD_SET_FIRST_POWERON, /* To Set First Power On */
+ RTC_CMD_SET_PDN_BITS, /* To Set RTC PDN Bits */
+ RTC_CMD_SET_PWR_KEY, /* To Set Power Key */
+ RTC_CMD_SET_TIME, /* To Set Time */
+ RTC_CMD_SETBBPU, /* To Set BBPU */
+ RTC_CMD_SETXOSC, /* To Set XOSC */
+ RTC_CMD_START_CALI, /* To Start Calibration */
+ RTC_CMD_WAIT_DEBOUNCE, /* To Wait De-bounce */
+ RTC_CMD_WRITE_PDN_BITS, /* To Write RTC PDN Bits */
+ RTC_CMD_WRITE_SPAR, /* To Write SPAR Register */
+ RTC_CMD_WRITE_TRIGGER, /* To Set Write Trigger */
+ RTC_CMD_WRITE_TRIGGER_WAIT, /* To Set Write Trigger And Wait */
+ RTC_CMD_WRITE_XOSC_REG, /* To Write RTC XOSC Register */
+ RTC_CMD_PROT_UNLOCK, /* To Unlock RTC PROT */
+ RTC_CMD_REGISTER_MODULE_TO_SEND_RTCTIME, /* To register ilm infomation by other modules to request RTC time */
+ RTC_CMD_WRITE_OSC32CON_REG, /* To Write RTC OSC32CON Register */
+} DCL_CTRL_CMD_T;
+#else /* __BUILD_DOM__ */
+#define RTC_CMDS \
+ RTC_CMD_BOOTLOADER_POWERON, \
+ RTC_CMD_CLEAR_PDN_BITS, \
+ RTC_CMD_CONFIG_AL_TC, \
+ RTC_CMD_DELAY, \
+ RTC_CMD_FT_POWEROFF, \
+ RTC_CMD_GET_ALARM_TIME, \
+ RTC_CMD_GET_TIME, \
+ RTC_CMD_GPIO_GET_INPUT, \
+ RTC_CMD_GPIO_SET_EXPORT_32K, \
+ RTC_CMD_GPIO_SET_EXPORT_COREDETB, \
+ RTC_CMD_GPIO_SET_INPUT_MODE, \
+ RTC_CMD_GPIO_SET_OUTPUT_MODE, \
+ RTC_CMD_HW_INIT, \
+ RTC_CMD_INIT, \
+ RTC_CMD_INIT_TC_AL_INTR, \
+ RTC_CMD_IS_CONFIG_VALID,\
+ RTC_CMD_IS_FIRST_ON, \
+ RTC_CMD_IS_MS_FIRSTPOWERON, \
+ RTC_CMD_IS_TIME_VALID, \
+ RTC_CMD_PWIC_CHECK_POWERON, \
+ RTC_CMD_PWIC_FIRST_POWERON_INIT_RTCTIME, \
+ RTC_CMD_PWIC_MASK_AL, \
+ RTC_CMD_PWIC_POWEROFF_RTC_INIT, \
+ RTC_CMD_PWIC_POWERON_RTC_INIT, \
+ RTC_CMD_READ_PDN_BITS, \
+ RTC_CMD_READ_SPAR, \
+ RTC_CMD_READ_XOSC_REG, \
+ RTC_CMD_RELOAD, \
+ RTC_CMD_SET_ALARM_TIME, \
+ RTC_CMD_SET_FIRST_POWERON, \
+ RTC_CMD_SET_PDN_BITS, \
+ RTC_CMD_SET_PWR_KEY, \
+ RTC_CMD_SET_TIME, \
+ RTC_CMD_SETBBPU, \
+ RTC_CMD_SETXOSC, \
+ RTC_CMD_START_CALI, \
+ RTC_CMD_WAIT_DEBOUNCE, \
+ RTC_CMD_WRITE_PDN_BITS, \
+ RTC_CMD_WRITE_SPAR, \
+ RTC_CMD_WRITE_TRIGGER, \
+ RTC_CMD_WRITE_TRIGGER_WAIT, \
+ RTC_CMD_WRITE_XOSC_REG, \
+ RTC_CMD_PROT_UNLOCK, \
+ RTC_CMD_REGISTER_MODULE_TO_SEND_RTCTIME, \
+ RTC_CMD_WRITE_OSC32CON_REG,
+#endif /* __BUILD_DOM__ */
+
+/*******************************************************************************
+ * Define the Data and Time Interrupt Control Bit
+ *******************************************************************************/
+
+/* Y:Year, M:Month, W:DOW, D:DOM, H:Hour, M:Min, S:SEC */
+
+/* Alarm Enable None */
+#define AL_EN_None 0
+/* Alarm Enable Check Sec */
+#define AL_EN_ChkS 1
+/* Alarm Enable Check Min & Sec */
+#define AL_EN_ChkMS 2
+/* Alarm Enable Check Hour, Min & Sec */
+#define AL_EN_ChkHMS 3
+/* Alarm Enable Check DOM, Hour, Min & Sec */
+#define AL_EN_ChkDHMS 4
+/* Alarm Enable Check DOW, Hour, Min & Sec */
+#define AL_EN_ChkWHMS 5
+/* Alarm Enable Check Month, DOM, Hour, Min & Sec */
+#define AL_EN_ChkMDHMS 6
+/* Alarm Enable Check Year, Month, DOM, Hour, Min & Sec */
+#define AL_EN_ChkYMDHMS 7
+/* Alarm Enable No Change */
+#define AL_EN_NoChange 8
+
+/* Time Counter Enable None */
+#define TC_EN_None 0
+/* Time Counter Enable Check Sec */
+#define TC_EN_ChkS 1
+/* Time Counter Enable Check Min & Sec */
+#define TC_EN_ChkM 2
+/* Time Counter Enable Check Hour, Min & Sec */
+#define TC_EN_ChkH 3
+/* Time Counter Enable Check DOM, Hour, Min & Sec */
+#define TC_EN_ChkD 4
+/* Time Counter Enable Check DOW, Hour, Min & Sec */
+#define TC_EN_ChkW 5
+/* Time Counter Enable Check Month, DOM, Hour, Min & Sec */
+#define TC_EN_ChkMon 6
+/* Time Counter Enable Check Year, Month, DOM, Hour, Min & Sec */
+#define TC_EN_ChkY 7
+/* Time Counter Enable No Change */
+#define TC_EN_NoChange 8
+
+/*******************************************************************************
+ * RTC PDN Bits Definitions
+ *******************************************************************************/
+
+/* PDN 1 Bit[7], META Reset RTC */
+#define DRV_COMM_REG1_META_RESET_RTC 0x0080
+/* PDN 2 Bit[7], Normal Reset */
+#define DRV_COMM_REG2_NORMAL_RESET 0x0080
+/* PDN 2 Bit[6], Charge Power On */
+#define DRV_COMM_REG2_CHRPWRON 0x0040
+/* PDN 2 Bit[5], USB Mass Storage Power On */
+#define DRV_COMM_REG2_USBMS_PWRON 0x0020
+/* PDN 2 Bit[4], RTC Power On */
+#define DRV_COMM_REG2_RTCPWRON 0x0010
+/* PDN 2 Bit[3], USB Mass Storage Power Off */
+#define DRV_COMM_REG2_USBMS_PWROFF 0x0008
+/* PDN 2 Bit[2], RTC NVRAM Valid */
+#define DRV_COMM_REG2_RTC_NVRAM 0x0004
+/* PDN 2 Bit[1], Swich To IDLE Power On */
+#define DRV_COMM_REG2_SWITCH2IDLE_PWRON 0x0002
+/* PDN 2 Bit[0], BTMT Watchdog Reset Power On */
+#define DRV_COMM_REG2_BTMT_WDTRET_PWRON 0x0001
+
+/* Reserved for bootrom security, support it after 6227 */
+#if defined(DRV_RTC_COMM_REG1_SECURITY)
+/* Bootrom Security 1 */
+#define DRV_COMM_REG1_BOOTROM_SECURITY1 0x0001
+/* Bootrom Security 2 */
+#define DRV_COMM_REG1_BOOTROM_SECURITY2 0x0010
+/* Bootrom Security 3 */
+#define DRV_COMM_REG1_BOOTROM_SECURITY3 0x0020
+/* Bootrom Security 4 */
+#define DRV_COMM_REG1_BOOTROM_SECURITY4 0x0040
+#endif
+
+/* RTC PDN1, use RTC INFO1 as DRV_COMM_REG1 */
+#define DRV_COMM_REG1 (RTC_base+0x0058)
+/* RTC PDN1, use RTC INFO2 as DRV_COMM_REG2 */
+#define DRV_COMM_REG2 (RTC_base+0x005c)
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+
+/* RTC Data Stucture for Save Information Only (Cannot be used for function's parameter) */
+typedef struct
+{
+ DCL_UINT8 rtc_sec; /* Seconds after the minute - [0,59] */
+ DCL_UINT8 rtc_min; /* Minutes after the hour - [0,59] */
+ DCL_UINT8 rtc_hour; /* Hours after the midnight - [0,23] */
+ DCL_UINT8 rtc_day; /* Day of the month - [1,31] */
+ DCL_UINT8 rtc_mon; /* Months - [1,12] */
+ DCL_UINT8 rtc_wday; /* Days in a week - [1,7] */
+ DCL_UINT8 rtc_year; /* Years - [0,127] */
+}DCL_RTC_DATA_T;
+
+/* For RTC_CMD_BOOTLOADER_POWERON command. */
+typedef struct
+{
+ DCL_BOOLEAN fgBootloaderPowerOn; /* Output : TRUE: Indicate Device Is First On; FALSE: Device Is Not First On */
+}RTC_CTRL_BOOTLOADER_POWERON_T;
+
+/* Enum of PDN Registers */
+typedef enum
+{
+ DCL_RTC_PDN1 = 0, /* PDN1 */
+ DCL_RTC_PDN2, /* PDN2 */
+ DCL_RTC_MAX_INDEX /* Maximum PDN Register */
+}DCL_RTC_PDN_INDEX_T;
+
+/* For RTC_CMD_CLEAR_PDN_BITS, RTC_CMD_READ_PDN_BITS, RTC_CMD_SET_PDN_BITS, RTC_CMD_WRITE_PDN_BITS commands. */
+typedef struct
+{
+ DCL_RTC_PDN_INDEX_T PDNIndex; /* Input : Number of PDN Register */
+ DCL_UINT16 fgConfigBit; /* Input : PDN Bit for Configuration */
+ DCL_UINT16 PDNValue; /* Output : Value of PDN Register */
+}RTC_CTRL_CONFIG_PDN_BIT_T;
+
+/* For RTC_CMD_CONFIG_AL_TC command. */
+typedef struct
+{
+ DCL_UINT8 u1ALEn; /* Input : Alarm Enable */
+ DCL_UINT8 u1TCEn; /* Input : Time Counter Enable */
+}RTC_CTRL_CONFIG_AL_TC_T;
+
+/* For RTC_CMD_DELAY command. */
+// RTC_CMD_DELAY does NOT need parameters
+
+/* For RTC_CMD_FT_POWEROFF command. */
+typedef struct
+{
+ DCL_BOOLEAN fgMetaReset; /* Output : If DRV_COMM_REG1_META_RESET_RTC set or not*/
+}RTC_CTRL_FT_POWEROFF_T;
+
+/* For RTC_CMD_GET_ALARM_TIME command. */
+typedef struct
+{
+ DCL_UINT8 u1Sec; /* Output : Seconds after the minute - [0,59] */
+ DCL_UINT8 u1Min; /* Output : Minutes after the hour - [0,59] */
+ DCL_UINT8 u1Hour; /* Output : Hours after the midnight - [0,23] */
+ DCL_UINT8 u1Day; /* Output : Day of the month - [1,31] */
+ DCL_UINT8 u1Mon; /* Output : Months - [1,12] */
+ DCL_UINT8 u1WDay; /* Output : Days in a week - [1,7] */
+ DCL_UINT8 u1Year; /* Output : Years - [0,127] */
+ DCL_BOOLEAN ALEnBit; /* Output : The status of AL enable bit of RTC_IRQ_EN */
+}RTC_CTRL_GET_ALARM_TIME_T;
+
+/* For RTC_CMD_GET_TIME command. */
+typedef struct
+{
+ DCL_UINT8 u1Sec; /* Output : Seconds after the minute - [0,59] */
+ DCL_UINT8 u1Min; /* Output : Minutes after the hour - [0,59] */
+ DCL_UINT8 u1Hour; /* Output : Hours after the midnight - [0,23] */
+ DCL_UINT8 u1Day; /* Output : Day of the month - [1,31] */
+ DCL_UINT8 u1Mon; /* Output : Months - [1,12] */
+ DCL_UINT8 u1WDay; /* Output : Days in a week - [1,7] */
+ DCL_UINT8 u1Year; /* Output : Years - [0,127] */
+}RTC_CTRL_GET_TIME_T;
+
+/* For RTC GPIO Pulling Type */
+typedef enum {
+ DCL_RTC_GPIO_NO_PULL = 0, /* No Pull */
+ DCL_RTC_GPIO_PULL_DOWN, /* Pull Down */
+ DCL_RTC_GPIO_PULL_UP /* Pull Up */
+}DCL_RTC_GPIO_PULL_TYPE_T;
+
+/* For RTC GPIO Driving Strength */
+typedef enum {
+ DCL_RTC_GPIO_DS_4mA = 0, /* 4mA */
+ DCL_RTC_GPIO_DS_8mA, /* 8mA */
+ DCL_RTC_GPIO_DS_12mA, /* 12mA */
+ DCL_RTC_GPIO_DS_16mA /* 16mA */
+}DCL_RTC_GPIO_DRIVING_STRENGTH_T;
+
+/* For RTC_CMD_GPIO_CONFIG_MODE command. */
+typedef struct
+{
+ DCL_RTC_GPIO_PULL_TYPE_T rPullType; /* Input : Pull Type */
+ DCL_RTC_GPIO_DRIVING_STRENGTH_T rPullStrength; /* Input : Drving Strength */
+ DCL_BOOLEAN InputValue; /* Output : Value of GPIO Input */
+ DCL_BOOLEAN OutputValue; /* Input : Value of GPIO Output */
+ DCL_BOOLEAN is_SmithTrigger; /* Input : Is Smith Triggter Or Not */
+ DCL_BOOLEAN is_SlewRateControl; /* Input : Is Slew Rate Control Or Not */
+}RTC_CTRL_GPIO_TIME_T;
+
+/* For RTC_CMD_HW_INIT command. */
+// RTC_CMD_HW_INIT does NOT need parameters
+
+/* For RTC_CMD_INIT command. */
+typedef struct
+{
+ void (*RTC_TCCallback)(void); /* Input : Callback Function for Timer Count */
+ void (*RTC_ALCallback)(void); /* Input : Callback Function for Alarm */
+}RTC_CTRL_INIT_T;
+
+/* For RTC_CMD_INIT_TC_AL_INTR command. */
+// RTC_CMD_INIT_TC_AL_INTR does NOT need parameters
+
+/* For RTC_CMD_IS_CONFIG_VALID command. */
+typedef struct
+{
+ DCL_BOOLEAN fgIsValid; /* Output : RTC Config Is Valid Or Not */
+}RTC_CTRL_IS_CONFIG_VALID_T;
+
+/* For RTC_CMD_IS_FIRST_ON command. */
+typedef struct
+{
+ DCL_BOOLEAN fgFirstOn; /* Output : TRUE: Indicate Device Is First On; FALSE: Device Is Not First On */
+}RTC_CTRL_IS_FIRST_ON_T;
+
+/* For RTC_CMD_IS_MS_FIRSTPOWERON command. */
+typedef struct
+{
+ DCL_BOOLEAN fgMSFirstPowerOn; /* Output : TRUE: Indicate Device Is First On; FALSE: Device Is Not First On */
+}RTC_CTRL_IS_MS_FIRSTPOWERON_T;
+
+/* For RTC_CMD_IS_TIME_VALID command. */
+typedef struct
+{
+ DCL_UINT8 u1Sec; /* Input : Seconds after the minute - [0,59] */
+ DCL_UINT8 u1Min; /* Input : Minutes after the hour - [0,59] */
+ DCL_UINT8 u1Hour; /* Input : Hours after the midnight - [0,23] */
+ DCL_UINT8 u1Day; /* Input : Day of the month - [1,31] */
+ DCL_UINT8 u1Mon; /* Input : Months - [1,12] */
+ DCL_UINT8 u1WDay; /* Input : Days in a week - [1,7] */
+ DCL_UINT8 u1Year; /* Input : Years - [0,127] */
+ DCL_BOOLEAN isTimeValid; /* Output: If time is valid */
+}RTC_CTRL_IS_TIME_VALID_T;
+
+/* For RTC_CMD_PWIC_CHECK_POWERON command. */
+typedef struct
+{
+ DCL_BOOLEAN fgIsPowerOn; /* Output : If Power On Or Not */
+}RTC_CTRL_PWIC_CHECK_POWERON_T;
+
+/* For RTC_CMD_PWIC_FIRST_POWERON_INIT_RTCTIME command. */
+typedef struct
+{
+ DCL_UINT8 u1Sec; /* Input : Seconds after the minute - [0,59] */
+ DCL_UINT8 u1Min; /* Input : Minutes after the hour - [0,59] */
+ DCL_UINT8 u1Hour; /* Input : Hours after the midnight - [0,23] */
+ DCL_UINT8 u1Day; /* Input : Day of the month - [1,31] */
+ DCL_UINT8 u1Mon; /* Input : Months - [1,12] */
+ DCL_UINT8 u1WDay; /* Input : Days in a week - [1,7] */
+ DCL_UINT8 u1Year; /* Input : Years - [0,127] */
+}RTC_CTRL_PWIC_FIRST_POWERON_INIT_RTCTIME_T;
+
+/* For RTC_CMD_PWIC_MASK_AL command. */
+// RTC_CMD_PWIC_MASK_AL does NOT need parameters
+
+/* For RTC_CMD_PWIC_POWEROFF_RTC_INIT command. */
+// RTC_CMD_PWIC_POWEROFF_RTC_INIT does NOT need parameters
+
+/* For RTC_CMD_PWIC_POWERON_RTC_INIT command. */
+// RTC_CMD_PWIC_POWERON_RTC_INIT does NOT need parameters
+
+/* Enum of SPAR Registers */
+typedef enum
+{
+ DCL_RTC_SPAR0 = 0, /* SPAR0 */
+ DCL_RTC_SPAR1, /* SPAR1 */
+ DCL_RTC_SPAR_MAX_INDEX /* Maximum SPAR Register */
+}DCL_RTC_SPAR_INDEX_T;
+
+/* For RTC_CMD_READ_SPAR, RTC_CMD_WRITE_SPAR commands. */
+typedef struct
+{
+ DCL_RTC_SPAR_INDEX_T SPARIndex; /* Input : Number of SPAR Register */
+ DCL_UINT16 WriteValue; /* Input : Value of SPAR for Configuration */
+ DCL_UINT16 ReadValue; /* Output : Value of SPAR Register */
+}RTC_CTRL_CONFIG_SPAR_T;
+
+/* For RTC_CMD_READ_XOSC_REG command. */
+typedef struct
+{
+ DCL_UINT8 XOSCValue; /* Output : The Result of XOSCCALI */
+}RTC_CTRL_READ_XOSC_REG_T;
+
+/* For RTC_CMD_RELOAD command. */
+// RTC_CMD_RELOAD does NOT need parameters
+
+/* For RTC_CMD_SET_ALARM_TIME command. */
+typedef struct
+{
+ DCL_UINT8 u1Sec; /* Input : Seconds after the minute - [0,59] */
+ DCL_UINT8 u1Min; /* Input : Minutes after the hour - [0,59] */
+ DCL_UINT8 u1Hour; /* Input : Hours after the midnight - [0,23] */
+ DCL_UINT8 u1Day; /* Input : Day of the month - [1,31] */
+ DCL_UINT8 u1Mon; /* Input : Months - [1,12] */
+ DCL_UINT8 u1WDay; /* Input : Days in a week - [1,7] */
+ DCL_UINT8 u1Year; /* Input : Years - [0,127] */
+}RTC_CTRL_SET_ALARM_TIME_T;
+
+/* For RTC_CMD_SET_FIRST_POWERON command. */
+typedef struct
+{
+ DCL_BOOLEAN fgPowerOn; /* Input : Set First Power On */
+}RTC_CTRL_SET_FIRST_POWERON_T;
+
+/* For RTC_CMD_SET_PWR_KEY command. */
+// RTC_CMD_SET_PWR_KEY does NOT need parameters
+
+/* For RTC_CMD_SET_TIME command. */
+typedef struct
+{
+ DCL_UINT8 u1Sec; /* Input : Seconds after the minute - [0,59] */
+ DCL_UINT8 u1Min; /* Input : Minutes after the hour - [0,59] */
+ DCL_UINT8 u1Hour; /* Input : Hours after the midnight - [0,23] */
+ DCL_UINT8 u1Day; /* Input : Day of the month - [1,31] */
+ DCL_UINT8 u1Mon; /* Input : Months - [1,12] */
+ DCL_UINT8 u1WDay; /* Input : Days in a week - [1,7] */
+ DCL_UINT8 u1Year; /* Input : Years - [0,127] */
+}RTC_CTRL_SET_TIME_T;
+
+/* For RTC_CMD_SETBBPU command. */
+typedef struct
+{
+ DCL_UINT16 BBPUReg; /* Input : Set BBPU Register */
+}RTC_CTRL_SETBBPU_T;
+
+/* For RTC_CMD_SETXOSC command. */
+// RTC_CMD_SETXOSC does NOT need parameters
+
+/* For RTC_CMD_START_CALI command. */
+// RTC_CMD_START_CALI does NOT need parameters
+
+/* For RTC_CMD_WAIT_DEBOUNCE command. */
+// RTC_CMD_WAIT_DEBOUNCE does NOT need parameters
+
+/* For RTC_CMD_WRITE_TRIGGER command. */
+// RTC_CMD_WRITE_TRIGGER does NOT need parameters
+
+/* For RTC_CMD_WRITE_TRIGGER_WAIT command. */
+// RTC_CMD_WRITE_TRIGGER_WAIT does NOT need parameters
+
+/* For RTC_CMD_WRITE_XOSC_REG command. */
+typedef struct
+{
+ DCL_UINT8 XOSC_Reg; /* Input : Set XOSCCALI Register */
+}RTC_CTRL_WRITE_XOSC_REG_T;
+
+typedef struct
+{
+ DCL_UINT32 dest_mod_id;
+ DCL_UINT32 sap_id;
+ DCL_UINT32 msg_id;
+ DCL_BOOLEAN fgRegisterILM;
+}RTC_CTRL_REGISTER_MODULE_ILM_INFO_T;
+
+/* For RTC_CMD_WRITE_XOSC_REG command. */
+typedef struct
+{
+ DCL_UINT16 OSC32CON_Reg; /* Input : Set XOSCCALI Register */
+}RTC_CTRL_WRITE_OSC32CON_REG_T;
+
+#ifdef __BUILD_DOM__
+/* The RTC Command Parameter Data Structure for Each Command in DCL_CTRL_DATA_T Enum of dcl.h */
+typedef struct
+{
+ RTC_CTRL_BOOTLOADER_POWERON_T rBootloaderPowerOn; /* Data Structure for RTC_CMD_BOOTLOADER_POWERON */
+ RTC_CTRL_CONFIG_AL_TC_T rConfigALTC; /* Data Structure for RTC_CMD_CONFIG_AL_TC */
+ RTC_CTRL_CONFIG_PDN_BIT_T rConfigPDNBit; /* Data Structure for RTC_CMD_CLEAR_PDN_BITS, RTC_CMD_READ_PDN_BITS, RTC_CMD_SET_PDN_BITS, and RTC_CMD_WRITE_PDN_BITS */
+ RTC_CTRL_FT_POWEROFF_T rFTPowerOff; /* Data Structure for RTC_CMD_FT_POWEROFF */
+ RTC_CTRL_GET_ALARM_TIME_T rGetAlarmTime; /* Data Structure for RTC_CMD_GET_ALARM_TIME */
+ RTC_CTRL_GET_TIME_T rGetTime; /* Data Structure for RTC_CMD_GET_TIME */
+ RTC_CTRL_GPIO_TIME_T rGPIO; /* Data Structure for RTC_CMD_GPIO_GET_INPUT, RTC_CMD_GPIO_SET_INPUT_MODE, and RTC_CMD_GPIO_SET_OUTPUT_MODE */
+ RTC_CTRL_INIT_T rInit; /* Data Structure for RTC_CMD_INIT */
+ RTC_CTRL_IS_CONFIG_VALID_T rIsConfigValid; /* Data Structure for RTC_CMD_IS_CONFIG_VALID */
+ RTC_CTRL_IS_FIRST_ON_T rIsFirstOn; /* Data Structure for RTC_CMD_IS_FIRST_ON */
+ RTC_CTRL_IS_MS_FIRSTPOWERON_T rIsMSFirstPowerOn; /* Data Structure for RTC_CMD_IS_MS_FIRSTPOWERON */
+ RTC_CTRL_IS_TIME_VALID_T rIsTimeValid; /* Data Structure for RTC_CMD_IS_TIME_VALID */
+ RTC_CTRL_PWIC_CHECK_POWERON_T rPwicCheckPowerOn; /* Data Structure for RTC_CMD_PWIC_CHECK_POWERON */
+ RTC_CTRL_PWIC_FIRST_POWERON_INIT_RTCTIME_T rPwicFirstPowerOnInitRTCTime; /* Data Structure for RTC_CMD_PWIC_FIRST_POWERON_INIT_RTCTIME */
+ RTC_CTRL_CONFIG_SPAR_T rConfigSPARReg; /* Data Structure for RTC_CMD_READ_SPAR, and RTC_CMD_WRITE_SPAR */
+ RTC_CTRL_READ_XOSC_REG_T rReadXOSCReg; /* Data Structure for RTC_CMD_READ_XOSC_REG */
+ RTC_CTRL_SET_ALARM_TIME_T rSetAlarmTime; /* Data Structure for RTC_CMD_SET_ALARM_TIME */
+ RTC_CTRL_SET_FIRST_POWERON_T rSetFirstPowerOn; /* Data Structure for RTC_CMD_SET_FIRST_POWERON */
+ RTC_CTRL_SET_TIME_T rSetTime; /* Data Structure for RTC_CMD_SET_TIME */
+ RTC_CTRL_SETBBPU_T rSetBBPU; /* Data Structure for RTC_CMD_SETBBPU */
+ RTC_CTRL_WRITE_XOSC_REG_T rWriteXOSCRef; /* Data Structure for RTC_CMD_WRITE_XOSC_REG */
+ RTC_CTRL_REGISTER_MODULE_ILM_INFO_T rRegisterModILMInfo; /* Data Structure for ilm to send to other modules */
+ RTC_CTRL_WRITE_OSC32CON_REG_T rWriteOSC32CONReg; /* Data Structure for RTC_CMD_REGISTER_MODULE_TO_SEND_RTCTIME */
+}DCL_CTRL_DATA_T;
+#else /* __BUILD_DOM__ */
+
+#define RTC_CTRLS \
+ RTC_CTRL_BOOTLOADER_POWERON_T rBootloaderPowerOn; \
+ RTC_CTRL_CONFIG_AL_TC_T rConfigALTC; \
+ RTC_CTRL_CONFIG_PDN_BIT_T rConfigPDNBit; \
+ RTC_CTRL_FT_POWEROFF_T rFTPowerOff; \
+ RTC_CTRL_GET_ALARM_TIME_T rGetAlarmTime; \
+ RTC_CTRL_GET_TIME_T rGetTime; \
+ RTC_CTRL_GPIO_TIME_T rGPIO; \
+ RTC_CTRL_INIT_T rInit; \
+ RTC_CTRL_IS_CONFIG_VALID_T rIsConfigValid; \
+ RTC_CTRL_IS_FIRST_ON_T rIsFirstOn; \
+ RTC_CTRL_IS_MS_FIRSTPOWERON_T rIsMSFirstPowerOn; \
+ RTC_CTRL_IS_TIME_VALID_T rIsTimeValid; \
+ RTC_CTRL_PWIC_CHECK_POWERON_T rPwicCheckPowerOn; \
+ RTC_CTRL_PWIC_FIRST_POWERON_INIT_RTCTIME_T rPwicFirstPowerOnInitRTCTime; \
+ RTC_CTRL_CONFIG_SPAR_T rConfigSPARReg; \
+ RTC_CTRL_READ_XOSC_REG_T rReadXOSCReg; \
+ RTC_CTRL_SET_ALARM_TIME_T rSetAlarmTime; \
+ RTC_CTRL_SET_FIRST_POWERON_T rSetFirstPowerOn; \
+ RTC_CTRL_SET_TIME_T rSetTime; \
+ RTC_CTRL_SETBBPU_T rSetBBPU; \
+ RTC_CTRL_WRITE_XOSC_REG_T rWriteXOSCRef; \
+ RTC_CTRL_REGISTER_MODULE_ILM_INFO_T rRegisterModILMInfo; \
+ RTC_CTRL_WRITE_OSC32CON_REG_T rWriteOSC32CONReg;
+
+#endif /* __BUILD_DOM__ */
+
+#endif // #ifndef __DCL_RTC_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_RTC_H_PROTOTYPE__
+#define __DCL_RTC_H_PROTOTYPE__
+
+/*************************************************************************
+* FUNCTION
+* DclRTC_Initialize
+*
+* DESCRIPTION
+* This function is to initialize RTC module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* Return the status of DclRTC_Initialize
+*
+* RETURN VALUES
+* STATUS_OK: Initialize Finished
+*
+*************************************************************************/
+extern DCL_STATUS DclRTC_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclRTC_Open
+*
+* DESCRIPTION
+* This function is to open the RTC module and return a handle
+*
+* PARAMETERS
+* dev: [IN] Only valid for DCL_RTC
+* flags: [IN] No sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* Return DCL_HANDLE of RTC
+*
+* RETURN VALUES
+* DCL_HANDLE_INVALID : Open failed
+* Other value : A valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclRTC_Open(DCL_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* DclRTC_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the RTC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclRTC_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclRTC_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the RTC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclRTC_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclRTC_Configure
+*
+* DESCRIPTION
+* This function is not supported for the RTC module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclRTC_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+/*************************************************************************
+* FUNCTION
+* DclRTC_RegisterCallback
+*
+* DESCRIPTION
+* This function is to set callback function for the RTC module.
+*
+* PARAMETERS
+* handle: [IN] The returned handle value of DclRTC_Open
+* event: [IN] Supported events:
+* 1.EVENT_RTC_ALARM: RTC alarm interrupt
+* 2.EVENT_RTC_TC: RTC tick interrupt
+* callback: [IN] the callback function for registered events
+*
+* RETURNS
+* Return the status of DclRTC_RegisterCallback
+*
+* RETURN VALUES
+* STATUS_OK: Successfully register the callback function.
+* STATUS_INVALID_DCL_HANDLE: It's a invalid handle.
+* STATUS_NOT_OPENED: The module has not been opened.
+* STATUS_INVALID_EVENT: The event parameter is invalid.
+*
+*************************************************************************/
+extern DCL_STATUS DclRTC_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+/*************************************************************************
+* FUNCTION
+* DclRTC_Control
+*
+* DESCRIPTION
+* This function is to send command to control the RTC module.
+*
+* PARAMETERS
+* handle: [IN] The handle value returned from DclRTC_Open
+* cmd: [IN] A control command for RTC module
+* 1. RTC_CMD_BOOTLOADER_POWERON: to check RTC Power On in bootloader
+* 2. RTC_CMD_CLEAR_PDN_BITS: to clear RTC PDN bits
+* 3. RTC_CMD_CONFIG_AL_TC: to set alarm mask and tick mask
+* 4. RTC_CMD_DELAY: to Delay 2000 counts
+* 5. RTC_CMD_FT_POWEROFF: to Power Off for FlashTool
+* 6. RTC_CMD_GET_ALARM_TIME: to get alarm time
+* 7. RTC_CMD_GET_TIME: to get time
+* 8. RTC_CMD_GPIO_GET_INPUT: to get RTC_GPIO_GPI register value
+* 9. RTC_CMD_GPIO_SET_EXPORT_32K: to export 32.768KHz clock on RTC_GPIO
+* 10. RTC_CMD_GPIO_SET_EXPORT_COREDETB: to export COREDETB on RTC_GPIO
+* 11. RTC_CMD_GPIO_SET_INPUT_MODE: to set RTC_GPIO input mode
+* 12. RTC_CMD_GPIO_SET_OUTPUT_MODE: to set RTC_GPIO output mode
+* 13. RTC_CMD_HW_INIT: to initialize RTC hardware
+* 14. RTC_CMD_INIT: to initialize RTC software
+* 15. RTC_CMD_INIT_TC_AL_INTR: to initialize RTC TC & AL INTR
+* 16. RTC_CMD_IS_CONFIG_VALID: to check if RTC time and Alarm are valid
+* 17. RTC_CMD_IS_FIRST_ON: to check if device is first on
+* 18. RTC_CMD_IS_MS_FIRSTPOWERON: to check whether RTC is first power on(for MMI)
+* 19. RTC_CMD_IS_TIME_VALID: to check if time are valid
+* 20. RTC_CMD_PWIC_CHECK_POWERON: to check if power on (for PWIC)
+* 21. RTC_CMD_PWIC_FIRST_POWERON_INIT_RTCTIME: to init RTC time at first power on (for PWIC)
+* 22. RTC_CMD_PWIC_MASK_AL: to control RTC Alarm mask (for PWIC)
+* 23. RTC_CMD_PWIC_POWEROFF_RTC_INIT: to init RTC at power off (for PWIC)
+* 24. RTC_CMD_PWIC_POWERON_RTC_INIT: to init RTC at power on (for PWIC)
+* 25. RTC_CMD_READ_PDN_BITS: to read RTC PDN bits
+* 26. RTC_CMD_READ_SPAR: to read RTC SPAR Register
+* 27. RTC_CMD_READ_XOSC_REG: to read RTC XOSCCALI register
+* 28. RTC_CMD_RELOAD: to load RTC whole register info from RTC module
+* 29. RTC_CMD_SET_ALARM_TIME: to set alarm time
+* 30. RTC_CMD_SET_FIRST_POWERON: to set first power on
+* 31. RTC_CMD_SET_PDN_BITS: to set RTC PDN bits
+* 32. RTC_CMD_SET_PWR_KEY: to set PWR KEY
+* 33. RTC_CMD_SET_TIME: to set time
+* 34. RTC_CMD_SETBBPU: to set RTC_BBPU
+* 35. RTC_CMD_SETXOSC: to set RTC XOSCCALI register
+* 36. RTC_CMD_START_CALI: to start calibration process
+* 37. RTC_CMD_WAIT_DEBOUNCE: to wait until debounce bit becomes 0
+* 38. RTC_CMD_WRITE_PDN_BITS: to write RTC PDN bits
+* 39. RTC_CMD_WRITE_SPAR: to write RTC SPAR Register
+* 40. RTC_CMD_WRITE_TRIGGER: to set write trigger
+* 41. RTC_CMD_WRITE_TRIGGER_WAIT: to set write trigger and wait until BUSY bit becomes 0
+* 42. RTC_CMD_WRITE_XOSC_REG: to write RTC XOSCCALI register
+*
+* data: The data of the control command
+* 1. RTC_CMD_BOOTLOADER_POWERON: pointer to a RTC_CTRL_BOOTLOADER_POWERON_T structure
+* 2. RTC_CMD_CLEAR_PDN_BITS: pointer to a RTC_CTRL_CONFIG_PDN_BIT_T structure
+* 3. RTC_CMD_CONFIG_AL_TC: pointer to a RTC_CTRL_CONFIG_AL_TC_T structure
+* 4. RTC_CMD_DELAY: A null pointer
+* 5. RTC_CMD_FT_POWEROFF: A null pointer
+* 6. RTC_CMD_GET_ALARM_TIME: pointer to a RTC_CTRL_GET_ALARM_TIME_T structure
+* 7. RTC_CMD_GET_TIME: pointer to a RTC_CTRL_GET_TIME_T structure
+* 8. RTC_CMD_GPIO_GET_INPUT: pointer to a RTC_CTRL_GPIO_TIME_T structure
+* 9. RTC_CMD_GPIO_SET_EXPORT_32K: pointer to a RTC_CTRL_GPIO_TIME_T structure
+* 10. RTC_CMD_GPIO_SET_EXPORT_COREDETB: pointer to a RTC_CTRL_GPIO_TIME_T structure
+* 11. RTC_CMD_GPIO_SET_INPUT_MODE: pointer to a RTC_CTRL_GPIO_TIME_T structure
+* 12. RTC_CMD_GPIO_SET_OUTPUT_MODE: pointer to a RTC_CTRL_GPIO_TIME_T structure
+* 13. RTC_CMD_HW_INIT: A null pointer
+* 14. RTC_CMD_INIT: pointer to a RTC_CTRL_INIT_T structure
+* 15. RTC_CMD_INIT_TC_AL_INTR: A null pointer
+* 16. RTC_CMD_IS_CONFIG_VALID: pointer to a RTC_CTRL_IS_CONFIG_VALID_T structure
+* 17. RTC_CMD_IS_FIRST_ON: pointer to a RTC_CTRL_IS_FIRST_ON_T structure
+* 18. RTC_CMD_IS_MS_FIRSTPOWERON: pointer to a RTC_CTRL_IS_MS_FIRSTPOWERON_T structure
+* 19. RTC_CMD_IS_TIME_VALID: pointer to a RTC_CTRL_IS_TIME_VALID_T structure
+* 20. RTC_CMD_PWIC_CHECK_POWERON: pointer to a RTC_CTRL_PWIC_CHECK_POWERON_T structure
+* 21. RTC_CMD_PWIC_FIRST_POWERON_INIT_RTCTIME: pointer to a RTC_CTRL_PWIC_FIRST_POWERON_INIT_RTCTIME_T structure
+* 22. RTC_CMD_PWIC_MASK_AL: A null pointer
+* 23. RTC_CMD_PWIC_POWEROFF_RTC_INIT: A null pointer
+* 24. RTC_CMD_PWIC_POWERON_RTC_INIT: A null pointer
+* 25. RTC_CMD_READ_PDN_BITS: pointer to a RTC_CTRL_CONFIG_PDN_BIT_T structure
+* 26. RTC_CMD_READ_SPAR: pointer to a RTC_CTRL_CONFIG_SPAR_T structure
+* 27. RTC_CMD_READ_XOSC_REG: pointer to a RTC_CTRL_READ_XOSC_REG_T structure
+* 28. RTC_CMD_RELOAD: A null pointer
+* 29. RTC_CMD_SET_ALARM_TIME: pointer to a RTC_CTRL_SET_ALARM_TIME_T structure
+* 30. RTC_CMD_SET_FIRST_POWERON: pointer to a RTC_CTRL_SET_FIRST_POWERON_T structure
+* 31. RTC_CMD_SET_PDN_BITS: pointer to a RTC_CTRL_CONFIG_PDN_BIT_T structure
+* 32. RTC_CMD_SET_PWR_KEY: A null pointer
+* 33. RTC_CMD_SET_TIME: pointer to a RTC_CTRL_SET_TIME_T structure
+* 34. RTC_CMD_SETBBPU: pointer to a RTC_CTRL_SETBBPU_T structure
+* 35. RTC_CMD_SETXOSC: A null pointer
+* 36. RTC_CMD_START_CALI: A null pointer
+* 37. RTC_CMD_WAIT_DEBOUNCE: A null pointer
+* 38. RTC_CMD_WRITE_PDN_BITS: pointer to a RTC_CTRL_CONFIG_PDN_BIT_T structure
+* 39. RTC_CMD_WRITE_SPAR: pointer to a RTC_CTRL_CONFIG_SPAR_T structure
+* 40. RTC_CMD_WRITE_TRIGGER: A null pointer
+* 41. RTC_CMD_WRITE_TRIGGER_WAIT: A null pointer
+* 42. RTC_CMD_WRITE_XOSC_REG: pointer to a RTC_CTRL_WRITE_XOSC_REG_T structure
+*
+* RETURNS
+* Return the status of DclRTC_Control
+*
+* RETURN VALUES
+* STATUS_OK: Command is executed successfully.
+* STATUS_FAIL: Command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+*
+*************************************************************************/
+extern DCL_STATUS DclRTC_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclRTC_Close
+*
+* DESCRIPTION
+* This function is to close the RTC module.
+*
+* PARAMETERS
+* handle: [IN] The returned handle value of DclRTC_Open
+*
+* RETURNS
+* Return the status of DclRTC_Close
+*
+* RETURN VALUES
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclRTC_Close(DCL_HANDLE handle);
+
+
+#endif // #ifndef __DCL_RTC_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
+
diff --git a/mcu/interface/driver/peripheral/dcl_sim.h b/mcu/interface/driver/peripheral/dcl_sim.h
new file mode 100644
index 0000000..6577557
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_sim.h
@@ -0,0 +1,544 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_sim.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file defines structures and functions for SIM DCL interface.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifdef DCL_DEFINITION_STRUCT
+
+#ifndef __DCL_SIM_H_STRUCT__
+#define __DCL_SIM_H_STRUCT__
+
+/*RHR*/
+//#include "kal_non_specific_general_types.h"
+#include "dcl.h"
+/*RHR*/
+
+#define DCL_SIM_MAX_INTERFACE 5
+
+/*********************************************************************************************************
+*followings we defines the structure used by DCL user, this is prevent DCL user from include invividual moudles' header file.
+**********************************************************************************************************/
+typedef DCL_UINT16 DCL_SIM_STATUS_WORD;
+
+typedef enum
+{
+ DCL_ME_UNKNOW =0,
+ DCL_ME_18V_30V,
+ DCL_ME_30V_ONLY,
+ DCL_ME_18V_ONLY
+} DCL_SIM_ENV;
+
+typedef enum{
+ DCL_USIM_NO_ERROR = 0,
+
+ /*expected status*/
+ DCL_USIM_WAITING_EVENT = 1, /* initial wait event status */
+ DCL_USIM_BLOCK_REC = 2, /* successfully received a complete block */
+ DCL_USIM_POWER_OFF = 3, /* successfully powered off */
+ DCL_USIM_ATR_REC = 4, /* successfully reveived all ATR */
+ DCL_USIM_S_BLOCK_REC = 5, /* successfully reveived S RESP */
+
+ DCL_SIM_INIPTSERR = 6,
+ DCL_SIM_CMDTOUT = 9,
+ DCL_SIM_NULLTIMEOUT = 11,
+ DCL_SIM_PTS_RX_INVALID = 18,
+ DCL_SIM_CMDRECERR = 8,
+ DCL_SIM_OVERRUN = 19,
+
+ /* error status */
+ DCL_USIM_NO_INSERT = -1,
+ DCL_USIM_VOLT_NOT_SUPPORT = -2,
+ DCL_USIM_NO_ATR = -3,
+ DCL_USIM_TS_INVALID = -4,
+ DCL_USIM_ATR_ERR = -5,
+ DCL_USIM_INVALID_ATR = -6,
+ DCL_USIM_PTS_FAIL = -7,
+ DCL_USIM_RX_INVALID = -8, /* EDC error or parity error */
+ DCL_USIM_BWT_TIMEOUT = -9,
+ DCL_USIM_DATA_ABORT = -10,
+ DCL_USIM_DEACTIVATED = -11,
+ DCL_USIM_S_BLOCK_FAIL = -12,
+ DCL_USIM_INVALID_WRST = -13,
+ DCL_USIM_GPT_TIMEOUT = -14,
+ DCL_USIM_PTS_TIMEOUT = -15,
+ DCL_USIM_PTS_RX_INVALID = -16
+}DCL_SIM_STATUS;
+
+/*All possible volatege support values. This enum to duplicate the same definition as internal SIM driver definition, so that protocol does not need to include driver internal header files*/
+typedef enum{
+ DCL_UNKNOWN_POWER_CLASS = 0,
+ DCL_CLASS_A_50V = 1, /*this card support 5V only, from ATR*/
+ DCL_CLASS_B_30V = 2, /*this card support 3V only, from ATR*/
+ DCL_CLASS_AB = 3, /*this card support 5V and 3V, from ATR*/
+ DCL_CLASS_C_18V = 4, /*this card support 1.8V only, from ATR*/
+ DCL_ClASS_BC = 6, /*this card support 3V and 1.8V, from ATR*/
+ DCL_CLASS_ABC = 7 /*this card support 5V, 3V, and 1.8V, from ATR*/
+}DCL_SIM_POWER;
+
+typedef DCL_UINT32 DCL_SIM_HW_CB;
+
+/*The application protocol support information. This enum to duplicate the same definition as internal SIM driver definition, so that protocol does not need to include driver internal header files*/
+typedef enum
+{
+ DCL_SIM_PROTOCOL, /*support SIM protocol, or to be more precisely, this should be a ICC card*/
+ DCL_USIM_PROTOCOL /*support USIM protocol, or to be more precisely, this should be a UICC card*/
+}DCL_SIM_APP_PROTOCOL;
+
+
+
+/*defines the possible choice of physical protocol. This enum to duplicate the same definition as internal SIM driver definition, so that protocol does not need to include driver internal header files*/
+typedef enum
+{
+ DCL_T0_PROTOCOL, /*prefer to use the T0 protocol*/
+ DCL_T1_PROTOCOL, /*prefer to use the T1 protocol*/
+ DCL_UNKNOWN_PROTOCOL /*no preferred physical protocol*/
+}DCL_SIM_PHY_PROTOCOL;
+
+/*defines the all of the clock stop related information. This enum to duplicate the same definition as internal SIM driver definition, so that protocol does not need to include driver internal header files*/
+typedef enum{
+ DCL_CLOCK_STOP_NOT_SUPPORT = 0x0, /*not support clock stop*/
+ DCL_CLOCK_STOP_LOW = 0x40, /*support clock stop in low level*/
+ DCL_CLOCK_STOP_HIGH = 0x80, /*support clock stop in high level*/
+ DCL_CLOCK_STOP_ANY = 0xc0, /*support clock stop in any voltage level*/
+ DCL_CLOCK_STOP_MSK = 0xc0, /*define the clock stop mask, used to parse the information received from cards*/
+ DCL_CLOCK_STOP_UNKONW = 0x0f /*the default value*/
+}DCL_SIM_CLK_STOP;
+
+/*defines the possible card speed values. This enum is to duplicate the same definition as internal SIM driver definition, so that protocol does not need to include driver internal header files*/
+typedef enum{
+ DCL_SPEED_372, /*for speed372*/
+ DCL_SPEED_64, /*for speed64*/
+ DCL_SPEED_32, /*for speed32*/
+ DCL_SPEED_16 /*for speed16*/
+}DCL_SIM_CARD_SPEED;
+
+/*the structure to define the values exchanged when doing get card information*/
+typedef struct{
+ DCL_SIM_POWER power; /*the voltage we choose*/
+ DCL_SIM_CARD_SPEED speed; /*the speed we choose*/
+ DCL_SIM_CLK_STOP clock_stop; /*clock stop information in ATR*/
+ DCL_SIM_APP_PROTOCOL app_proto; /*whether it is a ICC card or UICC card*/
+ DCL_SIM_PHY_PROTOCOL phy_proto; /*the physical protocol we used*/
+ kal_bool T0_support; /* if T0 is supported*/
+ kal_bool T1_support; /* if T1 is supported*/
+ kal_uint8 hist_index; /* index to the historical char of ATR*/
+ kal_uint8 *ATR; /*the pointer to store the ATR received*/
+ kal_bool TAiExist; /*if the first TA for T=15 is existed*/
+ kal_uint8 ATR_length; /* length to the ATR_data*/
+ kal_bool isSW6263; /* query if status word 0x62xx 0x63xx happen*/
+ kal_uint8 TB15; // query if support ic usb
+ kal_bool hasPowerClass;
+ kal_uint8 PowerClass;
+ kal_bool SupportExtendedLength;
+ kal_uint8 sim_tray_status;
+ kal_uint8 sim_result;
+}DCL_SIM_INFO;
+
+/*******************************************************************************
+ * driver function tables exposed to DCL
+ *******************************************************************************/
+/*here are type definition for functions*/
+/*dcl add new api : 2. define function type*/
+
+/*the prototype definition for RST function pointer*/
+typedef DCL_SIM_STATUS (* DCL_SIM_RST)(DCL_SIM_POWER ExpectVolt, DCL_SIM_POWER *ResultVolt, kal_bool warm, DCL_SIM_HW_CB handle);
+/*the prototype definition for CMD function pointer*/
+typedef DCL_SIM_STATUS_WORD (* DCL_SIM_CMD)(kal_uint8 *txData,kal_uint32 *txSize,kal_uint8 *rxData, kal_uint32 *rxSize, DCL_SIM_HW_CB handle,kal_uint8 *bypass6263);
+/*the prototype definition for power off function pointer*/
+typedef void (* DCL_SIM_PWOFF)(DCL_SIM_HW_CB handle);
+/*the prototype definition for get card info function pointer*/
+typedef void (* DCL_SIM_GET_CARD_INFO)(DCL_SIM_INFO *info, DCL_SIM_HW_CB handle);
+/*the prototype definition for get card info function pointer*/
+typedef void (* DCL_SIM_GET_CARD_ERROR_TYPES_INFO)(DCL_SIM_INFO *info, DCL_SIM_HW_CB handle);
+/*the prototype definition for set maximum speed function pointer*/
+typedef void (* DCL_SIM_SET_MAX_SPEED)(DCL_SIM_CARD_SPEED speed, DCL_SIM_HW_CB handle);
+/*the prototype definition for set prefer physical protocol function pointer*/
+typedef void (* DCL_SIM_SET_PREFER_PROTOCOL)(DCL_SIM_PHY_PROTOCOL T, DCL_SIM_HW_CB handle);
+/*the prototype definition for set clock stop mode function pointer*/
+typedef kal_bool (* DCL_SIM_SET_CLK_STOP_MODE)(DCL_SIM_CLK_STOP mode, DCL_SIM_HW_CB handle);
+/*the prototype definition for TOUT test function pointer*/
+typedef void (* DCL_SIM_TOUT_TEST)(kal_uint32 toutValue, DCL_SIM_HW_CB handle);
+/*the prototype definition for assign logical number function pointer*/
+typedef kal_uint32 (* DCL_SIM_ASSIGN_LOGICAL)(kal_uint32 logicalNumber);
+/*the prototype definition for get card speed function pointer*/
+typedef DCL_SIM_CARD_SPEED (*DCL_SIM_GAT_CARD_SPEED)(DCL_SIM_HW_CB handle);
+/*the prototype definition for query 9000 function pointer*/
+typedef DCL_BOOL (*DCL_SIM_QUERY_GET_9000_WHEN_SELECT)(DCL_SIM_HW_CB handle);
+/*the prototype definition for set owner task pointer*/
+typedef void (* DCL_SIM_SET_OWNER_TASK)(DCL_SIM_HW_CB handle);
+/* For sim hot plug callback function */
+/*the prototype definition for SIM hot plug out call back function*/
+typedef void (*DCL_SIM_PLUG_OUT_CALLBACK)(kal_uint32 simIf);
+/*the prototype definition for SIM hot plug in call back function*/
+typedef void (*DCL_SIM_PLUG_IN_CALLBACK)(kal_uint32 simIf);
+/*the prototype definition for get card detect status pointer*/
+typedef void (* DCL_SIM_GET_CARD_DETECT_STATUS)(DCL_SIM_INFO *info, DCL_SIM_HW_CB handle);
+
+/*dcl add new api : 3. add to funtion table type*/
+
+/*the declaration of SIM driver table, expeorted from SIM driver to DCL SIM interface. This table implies we accept any SIM driver function tables with the same format.*/
+typedef struct
+{
+ DCL_SIM_RST rst; /*The RST function to detect card's existence*/
+ DCL_SIM_CMD cmd; /*The CMD function to send the APDU command to the card*/
+ DCL_SIM_PWOFF pwOff; /*The power off function to deactivate the card*/
+ DCL_SIM_GET_CARD_INFO getCardInfo; /*To report the card information, known by SIM driver, to the protocol layer*/
+ DCL_SIM_GET_CARD_ERROR_TYPES_INFO getCardErrorTypesInfo; /*To report the card error tpyes information, known by SIM driver, to the protocol layer*/
+ DCL_SIM_SET_MAX_SPEED setSpeed; /*To set the maximum allowed speed to driver*/
+ DCL_SIM_SET_PREFER_PROTOCOL setPreferT; /*To set the preferred physical layer protocol to driver*/
+ DCL_SIM_SET_CLK_STOP_MODE setClockStopMode; /*To set the CLK stop information, known by protocol, to driver*/
+ DCL_SIM_TOUT_TEST toutTest; /*To ask the driver to start TOUT test*/
+ DCL_SIM_ASSIGN_LOGICAL assignLogical; /*To Assign the logical number to specific card*/
+ DCL_SIM_GAT_CARD_SPEED getCardSpeed; /*to get the card speed information*/
+ DCL_SIM_QUERY_GET_9000_WHEN_SELECT query9000WhenSelect; /*To query whether a status word 0x9000 happened after SELECT command*/
+ DCL_SIM_SET_OWNER_TASK setOwnerTask; /*to update current owner task */
+ DCL_SIM_GET_CARD_DETECT_STATUS getCardDetectStatus; /*to get card detect pin status */
+}DCL_SIMDriver_t;
+
+/* defines the possible application value*/
+typedef enum
+{
+ SIM_CONFIG_AP_TYPE_PHONE1, /*the card will be used for phone application SIM card 1*/
+ SIM_CONFIG_AP_TYPE_PHONE2, /*the card will be used for phone application SIM card 2*/
+ SIM_CONFIG_AP_TYPE_CMMB_SMD, /*the card will be used for CMMB SMD card*/
+ SIM_CONFIG_AP_TYPE_PHONE3, /*the card will be used for phone application SIM card 3*/
+ SIM_CONFIG_AP_TYPE_PHONE4 /*the card will be used for phone application SIM card 4*/
+} DCL_SIM_CONFIG_AP_TYPE;
+
+/* defines the SIM configure structure */
+typedef struct
+{
+ DCL_SIM_CONFIG_AP_TYPE apType; /* define the application type protocol want to use*/
+ DCL_SIM_PLUG_IN_CALLBACK hotPlugInCb; /* specify the hot plug in callback function pointer*/
+ DCL_SIM_PLUG_OUT_CALLBACK hotPlugOutCb; /* specify the hot plug out callback function pointer*/
+} SIM_CONFIG_T;
+
+#define SIM_CONFIGS \
+ SIM_CONFIG_T rSimConfig;
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for SIM
+ *******************************************************************************/
+ /*dcl add new api : 4. add to DCL_CTRL_CMD enum*/
+
+#ifdef __BUILD_DOM__
+/*The SIM Command values in DCL_CTRL_CMD_T Enum of dcl.h*/
+typedef enum
+{
+ SIM_CTRL_CMD_RST, /*try to reset the card and tell its existence*/
+ SIM_CTRL_CMD_CMD, /*send APDU command to ICC/UICC*/
+ SIM_CTRL_CMD_PWOFF, /*to power off the card*/
+ SIM_CTRL_CMD_GET_CARD_INFO, /*to get the card information stored in driver layer*/
+ SIM_CTRL_CMD_GET_CARD_ERROR_TYPES_INFO, /*to get the card error types information stored in driver layer*/
+ SIM_CTRL_CMD_SET_SPEED, /*set the maximum allowed speed*/
+ SIM_CTRL_CMD_SET_PREFER_PROTOCOL, /*to set the preferred physical protocl*/
+ SIM_CTRL_CMD_SET_CLK_STOP_MODE, /*to set the clock stop related setting*/
+ SIM_CTRL_CMD_TOUT_TEST, /*to start TOUT test, used by MEUT SIM test task*/
+ SIM_CTRL_CMD_GET_SPEED, /*to get the card speed information*/
+ SIM_CTRL_CMD_QUERY_9000_ON_SELECT, /*to querry whether 0x9000 after SELECT command happens*/
+ SIM_CTRL_CMD_SET_OWNER_TASK, /*to update sim driver owner task*/
+ SIM_CTRL_CMD_GET_CARD_DETECT_STATUS, /*to get sim card detect pin status*/
+ SIM_CTRL_CMD_SET_SLT_RLT, /*to set SLT result*/
+}DCL_CTRL_CMD_T;
+#else
+#define SIM_CMDS \
+ SIM_CTRL_CMD_BASE, \
+ SIM_CTRL_CMD_RST = 0, \
+ SIM_CTRL_CMD_CMD, \
+ SIM_CTRL_CMD_PWOFF, \
+ SIM_CTRL_CMD_GET_CARD_INFO, \
+ SIM_CTRL_CMD_GET_CARD_ERROR_TYPES_INFO, \
+ SIM_CTRL_CMD_SET_SPEED, \
+ SIM_CTRL_CMD_SET_PREFER_PROTOCOL, \
+ SIM_CTRL_CMD_SET_CLK_STOP_MODE, \
+ SIM_CTRL_CMD_TOUT_TEST, \
+ SIM_CTRL_CMD_GET_SPEED, \
+ SIM_CTRL_CMD_QUERY_9000_ON_SELECT, \
+ SIM_CTRL_CMD_SET_OWNER_TASK, \
+ SIM_CTRL_CMD_GET_CARD_DETECT_STATUS, \
+ SIM_CTRL_CMD_SET_SLT_RLT, \
+ SIM_CTRL_CMD_MAX_VALUE, \
+ SIM_CTRL_CMD_DUMMY_END = SIM_CTRL_CMD_BASE + SIM_CTRL_CMD_MAX_VALUE,
+#endif /*__BUILD_DOM__*/
+
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+
+/* FOR SIM_CTRL_CMD_RST control command. */
+typedef struct
+{
+ DCL_SIM_POWER ExpectVolt; /*the expected voltage from caller*/
+ DCL_SIM_POWER *ResultVolt; /*the pointer to report the eventual reset voltage from driver*/
+ kal_bool warm; /*to indicate whether this is cold reset or warm reset*/
+ DCL_SIM_STATUS rstResult; /*the result*/
+} SIM_CTRL_RST_T;
+
+/* FOR SIM_CTRL_CMD_CMD control command. */
+typedef struct
+{
+ kal_uint8 *txData; /*the pointer to the tx data buffer*/
+ kal_uint32 *txSize; /*the pointer to the tx buffer size*/
+ kal_uint8 *rxData; /*the pointer to the tx data buffer*/
+ kal_uint32 *rxSize; /*the pointer to the rx buffer size, driver will then feedback actual receive size here*/
+ kal_uint16 *statusWord; /*the pointer to contains the status word from card*/
+ kal_uint8 *bypass6263; /*the flag to control whether return 6263 direcltly*/
+} SIM_CTRL_CMD_T;
+
+/*dcl add new api : 4. new ctrl data type*/
+
+/* FOR SIM_CTRL_CMD_GET_CARD_INFO control command. */
+typedef struct
+{
+ DCL_SIM_INFO *info; /*the pointer to DCL_SIM_INFO structure, SIM driver will filled the values of the structure*/
+} SIM_CTRL_GET_CARD_INFO_T;
+typedef struct
+{
+ DCL_SIM_INFO *info; /*the pointer to DCL_SIM_INFO structure, SIM driver will filled the values of the structure*/
+} SIM_CTRL_GET_CARD_DETECT_STATUS_T;
+
+/* FOR SIM_CTRL_CMD_GET_CARD_ERROR_TYPES_INFO control command. */
+typedef struct
+{
+ DCL_SIM_INFO *info; /*the pointer to DCL_SIM_INFO structure, SIM driver will filled the values of the structure*/
+} SIM_CTRL_GET_CARD_ERROR_TYPES_INFO_T;
+
+/* FOR SIM_CTRL_CMD_SET_SPEED control command. */
+typedef struct
+{
+ DCL_SIM_CARD_SPEED speed; /*the DCL_SIM_CARD_SPEED structure, the structure is to tell the driver the maximum allowed speed value*/
+} SIM_CTRL_SET_MAX_SPEED_T;
+
+/* FOR SIM_CTRL_CMD_SET_PREFER_PROTOCOL control command. */
+typedef struct
+{
+ DCL_SIM_PHY_PROTOCOL T; /*the DCL_SIM_PHY_PROTOCOL structure, the structure is to tell the driver the preferred physical protocol*/
+} SIM_CTRL_SET_PREFER_PROTOCOL_T;
+
+/* FOR SIM_CTRL_CMD_SET_CLK_STOP_MODE control command. */
+typedef struct
+{
+ DCL_SIM_CLK_STOP mode; /*the DCL_SIM_CLK_STOP structure, the structure is to tell the driver clock stop related information*/
+} SIM_CTRL_SET_CLK_STOP_MODE_T;
+
+/* FOR SIM_CTRL_CMD_TOUT_TEST control command. */
+typedef struct
+{
+ DCL_UINT32 toutValue; /*the tout value that we want to apply to TOUT test*/
+} SIM_CTRL_TOUT_TEST_T;
+
+/* FOR SIM_CTRL_CMD_GET_SPEED control command. */
+typedef struct
+{
+ DCL_SIM_CARD_SPEED *speed; //return the card's speed to SIM task
+} SIM_CTRL_GET_SPEED_T;
+
+/* FOR SIM_CTRL_CMD_QUERY_9000_ON_SELECT control command. */
+typedef struct
+{
+ DCL_BOOL *got9000; //return the information whether we encounter 9000 in select command
+} SIM_CTRL_QUERY_9000_T;
+
+/* FOR SIM_SLT_SET_RLT control command. */
+typedef struct
+{
+ DCL_BOOL rlt; /*the SLT checking result set from protocol*/
+} SIM_CTRL_SET_SLT_RLT_T;
+
+/*dcl add new api : 5. add to DCL_CTRL_DATA enum*/
+
+#ifdef __BUILD_DOM__
+/*data structure union for all of SIM control commands*/
+typedef union
+{
+ SIM_CTRL_RST_T rSIMRst; /*data structure for SIM_CTRL_CMD_RST control command*/
+ SIM_CTRL_CMD_T rSIMCmd; /*data structure for SIM_CTRL_CMD_CMD control command*/
+ SIM_CTRL_GET_CARD_INFO_T rSIMGetCardInfo; /*data structure for SIM_CTRL_CMD_GET_CARD_INFO control command*/
+ SIM_CTRL_GET_CARD_ERROR_TYPES_INFO_T rSIMGetCardErrorTypesInfo; /*data structure for SIM_CTRL_CMD_GET_CARD_ERROR_TYPES_INFO control command*/
+ SIM_CTRL_GET_CARD_DETECT_STATUS_T rSIMGetCardDetectStatus; /*data structure for SIM_CTRL_GET_CARD_DETECT_STATUS control command*/
+ SIM_CTRL_SET_MAX_SPEED_T rSIMSetMaxSpeed; /*data structure for SIM_CTRL_CMD_SET_SPEED control command*/
+ SIM_CTRL_SET_PREFER_PROTOCOL_T rSIMSetPreferProtocol; /*data structure for SIM_CTRL_CMD_SET_PREFER_PROTOCOL control command*/
+ SIM_CTRL_SET_CLK_STOP_MODE_T rSIMSetClkStopMode; /*data structure for SIM_CTRL_CMD_SET_CLK_STOP_MODE control command*/
+ SIM_CTRL_TOUT_TEST_T rSIMToutTest; /*data structure for SIM_CTRL_CMD_TOUT_TEST control command*/
+ SIM_CTRL_GET_SPEED_T rSIMGetSpeed; /*data structure for SIM_CTRL_CMD_GET_SPEED control command*/
+ SIM_CTRL_QUERY_9000_T rSIMQuery9000; /*data structure for SIM_CTRL_CMD_QUERY_9000_ON_SELECT control command*/
+ SIM_CTRL_SET_SLT_RLT_T rSIMSetSltRlt; /*data structure for SIM_CTRL_CMD_SET_SLT_RLT control command*/
+}DCL_CTRL_DATA_T;
+#else
+#define SIM_CTRLS \
+ SIM_CTRL_RST_T rSIMRst; \
+ SIM_CTRL_CMD_T rSIMCmd; \
+ SIM_CTRL_GET_CARD_INFO_T rSIMGetCardInfo;\
+ SIM_CTRL_GET_CARD_ERROR_TYPES_INFO_T rSIMGetCardErrorTypesInfo;\
+ SIM_CTRL_GET_CARD_DETECT_STATUS_T rSIMGetCardDetectStatus; \
+ SIM_CTRL_SET_MAX_SPEED_T rSIMSetMaxSpeed; \
+ SIM_CTRL_SET_PREFER_PROTOCOL_T rSIMSetPreferProtocol; \
+ SIM_CTRL_SET_CLK_STOP_MODE_T rSIMSetClkStopMode; \
+ SIM_CTRL_TOUT_TEST_T rSIMToutTest; \
+ SIM_CTRL_GET_SPEED_T rSIMGetSpeed; \
+ SIM_CTRL_QUERY_9000_T rSIMQuery9000; \
+ SIM_CTRL_SET_SLT_RLT_T rSIMSetSltRlt;
+#endif /*__BUILD_DOM__*/
+
+#endif /*__DCL_SIM_H_STRUCT__*/
+
+#endif /*DCL_DEFINITION_STRUCT*/
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_SIM_H_PROTOTYPE__
+#define __DCL_SIM_H_PROTOTYPE__
+
+/*************************************************************************
+* FUNCTION
+* DclSIM_Open
+* DESCRIPTION
+* This function is to open the SIM module and get a handle.
+*
+* PARAMETERS
+* dev: - only valid for DCL_SIM.
+* flags: - no sepcial flags is needed.
+*
+* RETURN VALUES
+* DCL_HANDLE_INVALID: - dev is an invalid value.
+* DCL_HANDLE_NONE: - no handler left, open failed.
+* other value: - a valid handle
+*
+*************************************************************************/
+DCL_HANDLE DclSIM_Open(DCL_DEV dev, DCL_FLAGS flags);
+
+/*************************************************************************
+* FUNCTION
+* DclSIM_Configure
+*
+* DESCRIPTION
+* This function is to configure the application usage of given handler.
+*
+* PARAMETERS
+* handle: - the handle to be configured, the value cannot be zero
+* configure: - to configure the application usage of this card, possible value can be found in DCL_SIM_CONFIG_AP_TYPE
+*
+* RETURN VALUES
+* STATUS_INVALID_DCL_HANDLE: - the handle is illegal
+* STATUS_OK: - the configuration is done successfully
+* STATUS_INVALID_CONFIGURATION: - the value of configure is not the one in DCL_SIM_CONFIG_AP_TYPE
+*
+*************************************************************************/
+DCL_STATUS DclSIM_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+
+/*************************************************************************
+* FUNCTION
+* DclSIM_Control
+*
+* DESCRIPTION
+* This function is the control command of SIM driver, this provides most of the SIM driver services to protocol.
+*
+* PARAMETERS
+* handle: - a valid handle return by DclSIM_Open()
+* cmd: - a control command to SIM driver, possible values are as following
+* 1. SIM_CTRL_CMD_RST: try to reset the card and tell its existence
+* 2. SIM_CTRL_CMD_CMD: send APDU command to ICC/UICC
+* 3. SIM_CTRL_CMD_PWOFF: to power off the card
+* 4. SIM_CTRL_CMD_GET_CARD_INFO: to get the card information stored in driver layer
+* 5. SIM_CTRL_CMD_SET_SPEED: set the maximum allowed speed
+* 6. SIM_CTRL_CMD_SET_PREFER_PROTOCOL: to set the preferred physical protocl
+* 7. SIM_CTRL_CMD_SET_CLK_STOP_MODE: to set the clock stop related setting
+* 8. SIM_CTRL_CMD_TOUT_TEST: to start TOUT test, used by MEUT SIM test task
+* 9. SIM_CTRL_CMD_GET_SPEED: to get the card speed information
+* 10. SIM_CTRL_CMD_QUERY_9000_ON_SELECT: to querry whether 0x9000 after SELECT command happens
+* data: - control data for SIM control command, possible values are as following
+* 1. SIM_CTRL_CMD_RST: pointer to a SIM_CTRL_RST_T structure
+* 1. SIM_CTRL_CMD_CMD: pointer to a SIM_CTRL_CMD_T structure
+* 2. SIM_CTRL_CMD_PWOFF: NULL
+* 3. SIM_CTRL_CMD_GET_CARD_INFO: pointer to a SIM_CTRL_GET_CARD_INFO_T structure
+* 4. SIM_CTRL_CMD_SET_SPEED: pointer to a SIM_CTRL_SET_MAX_SPEED_T structure
+* 5. SIM_CTRL_CMD_SET_PREFER_PROTOCOL: pointer to a SIM_CTRL_SET_PREFER_PROTOCOL_T structure
+* 6. SIM_CTRL_CMD_SET_CLK_STOP_MODE: pointer to a SIM_CTRL_SET_CLK_STOP_MODE_T structure
+* 7. SIM_CTRL_CMD_TOUT_TEST: pointer to a SIM_CTRL_TOUT_TEST_T structure
+* 8. SIM_CTRL_CMD_GET_SPEED: pointer to a SIM_CTRL_GET_SPEED_T structure
+* 9. SIM_CTRL_CMD_QUERY_9000_ON_SELECT: pointer to a SIM_CTRL_QUERY_9000_T structure
+* RETURN VALUES
+* STATUS_OK: - command is executed successfully.
+* STATUS_INVALID_CMD: - The command is invalid.
+*************************************************************************/
+DCL_STATUS DclSIM_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+
+/*************************************************************************
+* FUNCTION
+* DclSIM_Close
+*
+* DESCRIPTION
+* This function to close the further functionality of specified SIM handle.
+*
+* PARAMETERS
+* handle: the handle that return by DclSIM_Open.
+*
+* RETURN VALUES:
+* STATUS_OK: - the handle is closed successfully
+* STATUS_INVALID_DCL_HANDLE: - the handle is invalid
+* STATUS_UNSUPPORTED:
+*
+*************************************************************************/
+DCL_STATUS DclSIM_Close(DCL_HANDLE handle);
+DCL_STATUS DclSIM_Initialize(void);
+#endif /*__DCL_SIM_H_PROTOTYPE__*/
+#endif //DCL_DEFINITION_PROTOTYPE
+
diff --git a/mcu/interface/driver/peripheral/dcl_sim_gpio.h b/mcu/interface/driver/peripheral/dcl_sim_gpio.h
new file mode 100644
index 0000000..9819d17
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_sim_gpio.h
@@ -0,0 +1,177 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_sim_gpio.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file defines structures and functions for SIM GPIO DCL interface.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifdef DCL_DEFINITION_STRUCT
+
+#ifndef __DCL_SIM_GPIO_H_STRUCT__
+#define __DCL_SIM_GPIO_H_STRUCT__
+
+/*RHR*/
+//#include "kal_non_specific_general_types.h"
+#include "dcl.h"
+/*RHR*/
+
+typedef enum{
+ MT6306_SIM_GPIO1 = 0,
+ MT6306_SIM_GPIO2,
+ MT6306_SIM_GPIO3,
+ MT6306_SIM_GPIO4,
+ MT6306_SIM_GPIO5,
+ MT6306_SIM_GPIO6,
+ MT6306_SIM_GPIO7,
+ MT6306_SIM_GPIO8,
+ MT6306_SIM_GPIO9,
+ MT6306_SIM_GPIO10,
+ MT6306_SIM_GPIO11,
+ MT6306_SIM_GPIO12,
+ MT6306_SIM_GPI13,
+ MT6306_SIM_GPI14,
+ MT6306_SIM_GPI15,
+ MT6306_SIM_GPI16,
+ MT6306_SIM_GPI17,
+ MT6306_SIM_GPI18,
+}DCL_SIMGPIO_PIN_DEF;
+
+#define SIMGPIO_PULL_HIGH 1
+#define SIMGPIO_PULL_LOW 0
+#define SIMGPIO_DIR_IN 0
+#define SIMGPIO_DIR_OUT 1
+#define SIMGPIO_VOLT_18V 0
+#define SIMGPIO_VOLT_28V 1
+#define SIMGPIO_VOLT_30V 2
+
+
+/*******************************************************************************
+ * DCL_OPTIONS for SIMGPIO
+ *******************************************************************************/
+#define SIMGPIO_OPTIONS
+
+/*******************************************************************************
+ * DCL_CONFIGURE_T
+ *******************************************************************************/
+
+/*******************************************************************************
+ * DCL_EVENT for GPIO
+ *******************************************************************************/
+#define SIMGPIO_EVENTS
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for GPIO
+ *******************************************************************************/
+#define SIMGPIO_CMDS \
+ SIMGPIO_CMD_READ, \
+ SIMGPIO_CMD_WRITE, \
+ SIMGPIO_CMD_SET_DIR, \
+ SIMGPIO_CMD_TRUN_ON_VCC, \
+ SIMGPI_CMD_READ,
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+/* FOR GPIO_CMD_READ control command. */
+typedef struct
+{
+ DCL_UINT8 u1IOData; // GPIO_IO_HIGH or GPIO_IO_LOW
+} SIMGPIO_CTRL_READ_T;
+
+/* FOR SIMGPIO_CMD_WRITE control command. */
+typedef struct
+{
+ DCL_UINT8 u1IOData;// GPIO_IO_HIGH or GPIO_IO_LOW
+} SIMGPIO_CTRL_WRITE_T;
+
+/* FOR SIMGPIO_CMD_SET_DIR control command. */
+typedef struct
+{
+ DCL_UINT16 u2Dir;
+} SIMGPIO_CTRL_SET_DIR_T;
+
+/* FOR SIMGPIO_CMD_TRUN_ON_VCC control command. */
+typedef struct
+{
+ kal_bool on;
+ kal_uint8 volt;
+} SIMGPIO_CTRL_TRUN_ON_POWER;
+
+#define SIMGPIO_CTRLS \
+ SIMGPIO_CTRL_READ_T rSGRead; \
+ SIMGPIO_CTRL_WRITE_T rSGWrite; \
+ SIMGPIO_CTRL_SET_DIR_T rSGSetDir; \
+ SIMGPIO_CTRL_TRUN_ON_POWER rSGTurnOnPower; \
+ SIMGPIO_CTRL_READ_T rSGIRead;
+
+#endif /*__DCL_SIM_GPIO_H_STRUCT__*/
+
+#endif /*DCL_DEFINITION_STRUCT*/
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_SIM_GPIO_H_PROTOTYPE__
+#define __DCL_SIM_GPIO_H_PROTOTYPE__
+DCL_STATUS DclSIMGPIO_Initialize(void);
+DCL_HANDLE DclSIMGPIO_Open(DCL_DEV dev, DCL_FLAGS flags);
+DCL_STATUS DclSIMGPIO_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+DCL_STATUS DclSIMGPIO_Close(DCL_HANDLE handle);
+#endif /*__DCL_SIM_GPIO_H_PROTOTYPE__*/
+#endif //DCL_DEFINITION_PROTOTYPE
+
+
diff --git a/mcu/interface/driver/peripheral/dcl_spmi.h b/mcu/interface/driver/peripheral/dcl_spmi.h
new file mode 100644
index 0000000..1aa4eea
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_spmi.h
@@ -0,0 +1,335 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2019
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_spmi.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file defines structures and functions for SPMI DCL interface.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifdef DCL_DEFINITION_STRUCT
+
+#ifndef __DCL_SPMI_H_STRUCT__
+#define __DCL_SPMI_H_STRUCT__
+
+/*******************************************************************************
+ * DCL_OPTIONS for SPMI
+ *******************************************************************************/
+#define SPMI_OPTIONS
+
+/*******************************************************************************
+ * DCL_CONFIGURE_T
+ *******************************************************************************/
+#define SPMI_CONFIGS
+
+/*******************************************************************************
+ * DCL_EVENT for SPMI
+ *******************************************************************************/
+#define SPMI_EVENTS
+
+typedef enum
+{
+ DCL_BUCK_CPU,
+ DCL_BUCK_GPU,
+ DCL_BUCK_MD,
+ DCL_BUCK_RF,
+ DCL_MAIN_PMIC,
+ DCL_BUCK_VPU,
+ DCL_SUB_PMIC,
+ DCL_SLV_TYPE_MAX
+}SPMI_SLV_TYPE_ENUM;
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+/* For SPMI_CTRL_EXT_REGISTER_READL command. */
+typedef struct
+{
+ DCL_UINT16 type;
+ DCL_UINT16 addr;
+ DCL_UINT16 value;
+ DCL_UINT16 len;
+}SPMI_CTRL_EXT_REGISTER_READL;
+
+/* For SPMI_CTRL_EXT_REGISTER_WRITEL command. */
+typedef struct
+{
+ DCL_UINT16 type;
+ DCL_UINT16 addr;
+ DCL_UINT16 value;
+ DCL_UINT16 len;
+}SPMI_CTRL_EXT_REGISTER_WRITEL;
+
+/* For SPMI_CTRL_EXT_REGISTER_READL_FIELD command. */
+typedef struct
+{
+ DCL_UINT16 type;
+ DCL_UINT16 addr;
+ DCL_UINT16 value;
+ DCL_UINT16 len;
+ DCL_UINT16 mask;
+ DCL_UINT16 shift;
+}SPMI_CTRL_EXT_REGISTER_READL_FIELD;
+
+/* For SPMI_CTRL_EXT_REGISTER_WRITEL_FIELD command. */
+typedef struct
+{
+ DCL_UINT16 type;
+ DCL_UINT16 addr;
+ DCL_UINT16 value;
+ DCL_UINT16 len;
+ DCL_UINT16 mask;
+ DCL_UINT16 shift;
+}SPMI_CTRL_EXT_REGISTER_WRITEL_FIELD;
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+#ifdef __BUILD_DOM__
+/* The SPMI Command Parameter Data Structure for Each Command in DCL_CTRL_DATA_T Enum of dcl.h */
+typedef struct
+{
+ SPMI_CTRL_EXT_REGISTER_READL rSPMIExtRegisterReadL;
+ SPMI_CTRL_EXT_REGISTER_WRITEL rSPMIExtRegisterWriteL;
+ SPMI_CTRL_EXT_REGISTER_READL_FIELD rSPMIExtRegisterReadLField;
+ SPMI_CTRL_EXT_REGISTER_WRITEL_FIELD rSPMIExtRegisterWriteLField;
+}SPMI_CTRL_DATA;
+#else /* __BUILD_DOM__ */
+#define SPMI_CTRLS \
+ SPMI_CTRL_EXT_REGISTER_READL rSPMIExtRegisterReadL; \
+ SPMI_CTRL_EXT_REGISTER_WRITEL rSPMIExtRegisterWriteL; \
+ SPMI_CTRL_EXT_REGISTER_READL_FIELD rSPMIExtRegisterReadLField; \
+ SPMI_CTRL_EXT_REGISTER_WRITEL_FIELD rSPMIExtRegisterWriteLField;
+#endif /* __BUILD_DOM__ */
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for SPMI
+ *******************************************************************************/
+ #ifdef __BUILD_DOM__
+typedef enum {
+ EXT_REGISTER_READL = 0,
+ EXT_REGISTER_WRITEL,
+ EXT_REGISTER_READL_FIELD,
+ EXT_REGISTER_WRITEL_FIELD,
+ REGISTER_READ,
+ REGISTER_WRITE,
+ EXT_REGISTER_READ,
+ EXT_REGISTER_WRITE,
+ SPMI_MOD_CMD_MAX
+} SPMI_CTRL_CMD;
+#else /* __BUILD_DOM__ */
+#define SPMI_CMDS \
+ EXT_REGISTER_READL = 0, \
+ EXT_REGISTER_WRITEL, \
+ EXT_REGISTER_READL_FIELD, \
+ EXT_REGISTER_WRITEL_FIELD, \
+ REGISTER_READ, \
+ REGISTER_WRITE, \
+ EXT_REGISTER_READ, \
+ EXT_REGISTER_WRITE, \
+ SPMI_MOD_CMD_MAX,
+#endif /* __BUILD_DOM__ */
+
+#endif /*__DCL_SPMI_H_STRUCT__*/
+
+#endif /*DCL_DEFINITION_STRUCT*/
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_SPMI_H_PROTOTYPE__
+#define __DCL_SPMI_H_PROTOTYPE__
+
+typedef DCL_STATUS (*SPMI_CONTROL_HANDLER)(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclSPMI_Initialize
+*
+* DESCRIPTION
+* This function is to initialize SPMI module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclSPMI_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclSPMI_Open
+*
+* DESCRIPTION
+* This function is to open the SPMI module and return a handle
+*
+* PARAMETERS
+* dev: only valid for DCL_SPMI
+* flags: no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* DCL_HANDLE_INVALID: Open failed.
+* other value: a valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclSPMI_Open(DCL_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* DclSPMI_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the SPMI module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclSPMI_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclSPMI_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the SPMI module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclSPMI_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclSPMI_Configure
+*
+* DESCRIPTION
+* This function is not supported for the SPMI module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclSPMI_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+/*************************************************************************
+* FUNCTION
+* DclSPMI_RegisterCallback
+*
+* DESCRIPTION
+* This function is not supported for the SPMI module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURNS
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclSPMI_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+/*************************************************************************
+* FUNCTION
+* DclSPMI_Control
+*
+* DESCRIPTION
+* This function is to send command to control the SPMI module.
+*
+* PARAMETERS
+* handle: The handle value returned from DclSPMI_Open
+* cmd: a control command for SPMI module
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+* STATUS_UNSUPPORTED: It's a unsupported command.
+*
+*************************************************************************/
+extern DCL_STATUS DclSPMI_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclSPMI_Close
+*
+* DESCRIPTION
+* This function is to close the spmi module.
+*
+* PARAMETERS
+* handle: the returned handle value of DclSPMI_Close
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclSPMI_Close(DCL_HANDLE handle);
+#endif /*__DCL_SPMI_H_PROTOTYPE__*/
+#endif //DCL_DEFINITION_PROTOTYPE
+
+
diff --git a/mcu/interface/driver/peripheral/dcl_sts.h b/mcu/interface/driver/peripheral/dcl_sts.h
new file mode 100644
index 0000000..5b6f0a8
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_sts.h
@@ -0,0 +1,665 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_ts.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for TS.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_TS_H_STRUCT__
+#define __DCL_TS_H_STRUCT__
+
+
+/*******************************************************************************
+ * DCL_OPTIONS for TS
+ *******************************************************************************/
+#define TS_OPTIONS
+
+// Earlier defined in dcl_ts.c. Moved here so that application files can use this define
+
+/*******************************************************************************
+ * DCL_CONFIGURE_T
+ *******************************************************************************/
+
+#define TS_CONFIGS \
+ //TS_CONFIG_T rTSConfig;
+
+/*******************************************************************************
+ * DCL_EVENT for TS
+ *******************************************************************************/
+#define TS_EVENTS \
+ DCL_EVENT_STS_PUSH_BUFF = 1, \
+ DCL_EVENT_STS_UP, \
+ DCL_EVNET_STS_DOWN, \
+ DCL_EVENT_STS_MAX,
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for TS
+ *******************************************************************************/
+#define TS_CMDS \
+ STS_CMD_GET_EVENT, \
+ STS_CMD_PEEK_EVENT, \
+ STS_CMD_ENABLE, \
+ STS_CMD_FLUSH, \
+ STS_CMD_START_CALI, \
+ STS_CMD_STOP_CALI, \
+ STS_CMD_READ_CALI, \
+ STS_CMD_SET_CALI, \
+ STS_CMD_RESET, \
+ STS_CMD_RESET_HANDWRITING, \
+ STS_CMD_CONF_SAMPLE_PERIOD, \
+ STS_CMD_CONF_MOVE_OFFSET, \
+ STS_CMD_CONF_HANDWRITING, \
+ STS_CMD_POWER_ON, \
+ STS_CMD_CONF_TIMEOUT_PERIOD, \
+ STS_CMD_CTRL_CUSTOM_PARAM,\
+ STS_CMD_CTRL_CUSTOM_PARAM_RANGE,\
+ STS_CMD_CTRL_MICRONMETER_TO_COORD,\
+ STS_CMD_CTRL_COORD_TO_MICRONMETER,\
+ STS_CMD_QUERY_TP_TYPE,\
+ STS_CMD_SET_DEVICE,\
+ STS_CMD_COMMAND,
+
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+/* For TS_CMD command. */
+
+
+//STS_CMD_QUERY_TP_TYPE
+typedef enum
+{
+ RTP_Type = 0,
+ CTP_Type
+
+}DCL_TP_TYPE_Enum;
+
+typedef struct
+{
+ DCL_TP_TYPE_Enum TouchPanelType;
+}DCL_TP_TYPE_T;
+
+
+//STS_CMD_CTRL_CUSTOM_PARAM
+typedef enum
+{
+ TP_PARAM_GET = 0,
+ TP_PARAM_SET,
+ TP_PARAM_RESET
+}TP_CTRL_PARAM_TYPE;
+
+typedef struct {
+ kal_uint32 ts_debounce_time;
+ kal_uint32 touch_panel_cali_check_offset;
+ kal_uint32 min_pen_move_offset;
+ kal_uint32 hand_writing_max_offset;
+ kal_uint32 nonhand_writing_max_offset;
+ kal_uint32 max_stroke_move_offset;
+ kal_uint32 multiple_point_selection;
+ kal_uint32 touch_pressure_threshold_high;
+ kal_uint32 touch_pressure_threshold_low;
+ kal_uint32 pressure_check_boundary;
+ kal_uint32 pressure_shifting_boundary;
+ kal_uint32 border_pass_criterion;
+ kal_uint32 non_border_pass_criterion;
+ kal_uint32 border_range;
+ kal_uint32 jitter_circuit_interval;
+ kal_uint32 Dump_Screen;
+ kal_uint32 reserve_parameter1; //use for AUX_SPL_NUM
+ kal_uint32 reserve_parameter2;
+ kal_uint32 reserve_parameter3;
+ kal_uint32 height; // get only
+ kal_uint32 width; // get only
+} TouchPanel_EM_custom_data_struct;
+
+typedef struct
+{
+ TP_CTRL_PARAM_TYPE type;
+ TouchPanel_EM_custom_data_struct* pEmData;
+}DCL_CTRL_CUSTOM_PARAM_T;
+
+
+
+typedef struct
+{
+ kal_int32 ts_debounce_time_min;
+ kal_int32 ts_debounce_time_max;
+kal_int32 touch_panel_cali_check_offset_min;
+kal_int32 touch_panel_cali_check_offset_max;
+kal_int32 min_pen_move_offset_min;
+kal_int32 min_pen_move_offset_max;
+kal_int32 hand_writing_max_offset_min;
+kal_int32 hand_writing_max_offset_max;
+kal_int32 nonhand_writing_max_offset_min;
+kal_int32 nonhand_writing_max_offset_max;
+kal_int32 max_stroke_move_offset_min;
+kal_int32 max_stroke_move_offset_max;
+kal_int32 multiple_point_selection_min;
+kal_int32 multiple_point_selection_max;
+kal_int32 touch_pressure_threshold_high_min;
+kal_int32 touch_pressure_threshold_high_max;
+kal_int32 pressure_check_boundary_min;
+kal_int32 pressure_check_boundary_max;
+kal_int32 pressure_shifting_boundary_min;
+kal_int32 pressure_shifting_boundary_max;
+kal_int32 border_pass_criterion_min;
+kal_int32 border_pass_criterion_max;
+kal_int32 nonborder_pass_criterion_min;
+kal_int32 nonborder_pass_criterion_max;
+kal_int32 border_range_min;
+kal_int32 border_range_max;
+kal_uint32 jitter_circuit_interval_min;
+kal_uint32 jitter_circuit_interval_max;
+kal_uint32 Dump_Screen_min;
+kal_uint32 Dump_Screen_max;
+kal_int32 reserve_parameter1_min;
+kal_int32 reserve_parameter1_max;
+kal_int32 reserve_parameter2_min;
+kal_int32 reserve_parameter2_max;
+kal_int32 reserve_parameter3_min;
+kal_int32 reserve_parameter3_max;
+}TP_PARAM_RANGE;
+
+//STS_CMD_CTRL_CUSTOM_PARAM_RANGE
+typedef struct
+{
+ TP_CTRL_PARAM_TYPE type;
+ TP_PARAM_RANGE* pEmDataRange;
+}DCL_CTRL_CUSTOM_PARAM_RANGE_T;
+
+// STS_CMD_CTRL_MICRONMETER_TO_PIXEL
+typedef struct
+{
+ kal_uint32 x_micronmeter;
+ kal_uint32 y_micronmeter;
+ kal_uint32 x_coord;
+ kal_uint32 y_coord;
+}DCL_CTRL_MICRONMETER_COORD_T;
+
+
+
+//STS_CMD_GET_EVENT
+
+typedef enum {
+ DCL_PEN_DOWN, /*0*/
+ DCL_PEN_UP, /*1*/
+ DCL_PEN_MOVE, /*2*/
+ DCL_PEN_LONGTAP, /*3*/
+ DCL_PEN_REPEAT, /*4*/
+ DCL_PEN_ABORT, /*5*/
+ DCL_TP_UNKNOWN_EVENT,/*6*/
+ DCL_STROKE_MOVE, /*7*/
+ DCL_STROKE_STATICAL, /*8*/
+ DCL_STROKE_HOLD, /*9*/
+ DCL_PEN_LONGTAP_HOLD, /*10*/
+ DCL_PEN_REPEAT_HOLD, /*11*/
+ DCL_STROKE_DOWN=0xc0, /*0*/ /*1*/
+ DCL_STROKE_LONGTAP=0x7e, /*8*/
+ DCL_STROKE_UP=0x7f/*127*/
+} DCL_TP_Event_enum;
+
+/*
+typedef struct
+{
+ DCL_INT16 i2xAdc;
+ DCL_INT16 i2yAdc;
+ DCL_TP_Event_enum rEvent;
+ DCL_UINT16 i2TimeStamp; // unit: system tick
+} STS_CTRL_GET_T;
+*/
+
+typedef struct
+{
+ // Touch_Panel_Event_enum
+ DCL_UINT16 u2Event;
+ /*coordinate point, not diff*/
+ DCL_UINT16 u2x;
+ DCL_UINT16 u2y;
+ DCL_UINT16 u2z; //resistance TP: presure, capacitive TP: area
+} DCL_TP_SINGLE_EVENT_T;
+
+typedef struct
+{
+ DCL_UINT16 uModel; // Single/Dual/Triple/Four/Five/All gesture
+ DCL_UINT16 uPadding; //currently use for check the structure format correctness, 0xAA
+ DCL_UINT32 u2Time_stamp;
+ DCL_TP_SINGLE_EVENT_T rPoints[5];
+} STS_CTRL_GET_T;
+
+//STS_CMD_ENABLE
+typedef struct
+{
+ DCL_BOOL fgEnable;
+} STS_CTRL_EN_T;
+
+typedef struct
+{
+ kal_uint8 ref_count;
+ kal_uint16 msg_len; /* LOCAL_PARA_HDR */
+ kal_bool result;
+}tp_cali_done_struct;
+
+//STS_CMD_START_CALI
+typedef struct
+{
+ DCL_INT16 i2x; /*x coordinate*/
+ DCL_INT16 i2y; /*y coordinate*/
+} TS_COORD_T;
+typedef struct
+{
+ TS_COORD_T *rpPoint;
+ DCL_UINT16 u2Num;
+} STS_CTRL_SC_T;
+
+//STS_CMD_READ_CALI
+typedef struct
+{
+ /*x*/
+ double x_slope;
+ double x_offset;
+ /*y*/
+ double y_slope;
+ double y_offset;
+} TS_CALI_T;
+typedef struct
+{
+ TS_CALI_T rCali;
+} STS_CTRL_RC_T;
+
+//STS_CMD_SET_CALI
+typedef struct
+{
+ TS_CALI_T rCali;
+} STS_CTRL_SETC_T;
+
+//STS_CMD_RESET
+typedef struct
+{
+ DCL_BOOL fgSkipUnreleaseEnable;
+} STS_CTRL_RESET_T;
+
+//STS_CMD_CONF_SAMPLE_PERIOD
+typedef struct
+{
+ DCL_UINT32 u4Low;
+ DCL_UINT32 u4High;
+} STS_CTRL_CSP_T;
+
+//STS_CMD_CONF_MOVE_OFFSET
+typedef struct
+{
+ DCL_UINT16 u2Pen_offset;
+ DCL_UINT16 u2Stroke_offset;
+ DCL_UINT16 u2Longtap_pen_offset;
+ DCL_UINT16 u2Longtap_stroke_offset;
+} STS_CTRL_CMO_T;
+
+//STS_CMD_CONF_HANDWRITING
+typedef struct
+{
+ TS_COORD_T rMin;
+ TS_COORD_T rMax;
+} TS_HandArea_T;
+typedef struct
+{
+ TS_HandArea_T *rArea;
+ DCL_UINT16 u2n;
+ TS_HandArea_T *rExtArea;
+} STS_CTRL_CHW_T;
+
+//STS_CMD_CONF_TIMEOUT_PERIOD
+typedef struct
+{
+ DCL_UINT32 u4Longtap;
+ DCL_UINT32 u4Repeat;
+ DCL_UINT32 u4Handwriting_longtap;
+} STS_CTRL_CTP_T;
+
+//STS_CMD_POWER_ON
+typedef struct
+{
+ DCL_BOOL fgPowerOn;
+} STS_CTRL_POWER_ON_T;
+
+//STS_CMD_SET_DEVICE
+typedef enum
+{
+ DCL_CTP_ACTIVE_MODE,
+ DCL_CTP_IDLE_MODE,
+ DCL_CTP_SLEEP_MODE,
+ DCL_CTP_GESTURE_DETECTION_MODE,
+ DCL_CTP_MULTIPLE_POINT_MODE,
+ DCL_CTP_FIRMWARE_UPDATE,
+ DCL_CTP_FM_ENABLE,
+ DCL_CTP_FM_DISABLE
+}DCL_CTP_DEVICE_MODE_enum;
+
+typedef struct
+{
+ DCL_CTP_DEVICE_MODE_enum mode;
+} STS_CTRL_SET_DEVICE_T;
+
+//STS_CMD_COMMAND
+typedef enum
+{
+ DCL_CTP_COMMAND_GET_VERSION,
+ DCL_CTP_COMMAND_GET_CONFIG,
+ DCL_CTP_COMMAND_LOAD_INT_CONFIG,
+ DCL_CTP_COMMAND_LOAD_EXT_CONFIG,
+ DCL_CTP_COMMAND_GET_DIFF_DATA,
+ DCL_CTP_COMMAND_GET_FW_BUFFER,
+ DCL_CTP_COMMAND_DO_FW_UPDATE
+}DCL_CTP_CTRL_COMMAND_enum;
+
+typedef struct
+{
+ DCL_UINT32 u4Command;
+ void *pVoid1;
+ void *pVoid2;
+} STS_CTRL_COMMAND_T;
+
+#define TS_CTRLS \
+ STS_CTRL_GET_T rTSCtrlGE; \
+ STS_CTRL_EN_T rTSCtrlEN; \
+ STS_CTRL_SC_T rTSCtrlSC; \
+ STS_CTRL_RC_T rTSCtrlRC; \
+ STS_CTRL_SETC_T rTSCtrlSETC; \
+ STS_CTRL_RESET_T rTSCtrlRESET; \
+ STS_CTRL_CSP_T rTSCtrlCSP; \
+ STS_CTRL_CMO_T rTSCtrlCMO; \
+ STS_CTRL_CHW_T rTSCtrlCHW; \
+ STS_CTRL_POWER_ON_T rTSCtrlPO; \
+ STS_CTRL_CTP_T rTSCtrlCTP; \
+ DCL_CTRL_CUSTOM_PARAM_T rTSCtrlCustomParam;\
+ DCL_CTRL_CUSTOM_PARAM_RANGE_T rTSCtrlCustomParamRang;\
+ DCL_CTRL_MICRONMETER_COORD_T rTSCtrlMicronMeter_Pixel;\
+ DCL_TP_TYPE_T rTSCtrlTouchPanelType;\
+ STS_CTRL_SET_DEVICE_T rTSCtrlSD;\
+ STS_CTRL_COMMAND_T rTSCtrlCmd;
+
+
+#endif // #ifndef __DCL_TS_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_TS_H_PROTOTYPE__
+#define __DCL_TS_H_PROTOTYPE__
+
+
+/*************************************************************************
+* FUNCTION
+* DclSTS_Configure
+*
+* DESCRIPTION
+* This function is to configure the SW TS module.
+*
+* CALLS
+* It is called to configure of the SW TS module.
+*
+* PARAMETERS
+* handle - a valid handle return by DclSTS_Open()
+* configure - a structure which include the TS configuration.
+*
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: not open yet.
+* STATUS_INVALID_ARGUMENT: not a valid handle.
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclSTS_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+/*************************************************************************
+* FUNCTION
+* DclSTS_Control
+*
+* DESCRIPTION
+* This function is to send command to control the SW TS module.
+*
+* CALLS
+* It is called to send command to control the SW TS module.
+*
+* PARAMETERS
+* handle - a valid handle return by DclSTS_Open()
+* cmd - a control command for TS module
+* 1. STS_CMD_ENABLE :enable/disable touch panel
+* 2. STS_CMD_FLUSH :to flush all data in ring buffer.
+* 3. STS_CMD_START_CALI :to do coordinate calibration.
+* 4. STS_CMD_STOP_CALI :to stop coordinate calibration.
+* 5. STS_CMD_READ_CALI :to read coordinate calibration.
+* 6. STS_CMD_SET_CALI :to set coordinate calibration.
+* 7. STS_CMD_RESET :to reset touch panel driver.
+* 8. STS_CMD_RESET_HANDWRITING :to reset handwriting area as normal.
+* 9. STS_CMD_CONF_SAMPLE_PERIOD :to configure sample period in handwriting and non-handwriting area.
+* 10. STS_CMD_CONF_MOVE_OFFSET :to configure pen move offset and stroke move offset.
+* 11. STS_CMD_CONF_HANDWRITING :to configure handwriting area.
+* 12. STS_CMD_CONF_TIMEOUT_PERIOD:to configure period of long tap and repeat event.
+* 13. STS_CMD_GET_EVENT :to read event from ring buffer
+* 13. STS_CMD_PEEK_EVENT :to peek event from ring buffer
+
+* data - a union of DCL_CTRL_DATA_T
+* rTSCtrlEN; //STS_CMD_ENABLE
+* rTSCtrlSC; //STS_CMD_START_CALI
+* rTSCtrlRC; //STS_CMD_READ_CALI
+* rTSCtrlSETC; //STS_CMD_SET_CALI
+* rTSCtrlRESET; //STS_CMD_RESET
+* rTSCtrlCSP; //STS_CMD_CONF_SAMPLE_PERIOD
+* rTSCtrlCMO; //STS_CMD_CONF_MOVE_OFFSET
+* rTSCtrlCHW; //STS_CMD_CONF_HANDWRITING
+* rTSCtrlCTP; //STS_CMD_CONF_TIMEOUT_PERIOD
+* rTSCtrlGE; //STS_CMD_GET_EVENT
+* rTSCtrlGE; //STS_CMD_PEEK_EVENT
+*
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+* STATUS_INVALID_ARGUMENT: not a valid handle.
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclSTS_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclSTS_Initialize
+*
+* DESCRIPTION
+* This function is to initialize SW TS module
+*
+* CALLS
+* It is called to initialize SW TS module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* DCL_STATUS_OK
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclSTS_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclSTS_Open
+*
+* DESCRIPTION
+* This function is to open the TS SW module and return a handle
+*
+* CALLS
+* It is called to open SW TS module
+*
+* PARAMETERS
+* dev - valid for DCL_TS
+* flags - no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURNS
+* DCL_HANDLE_INVALID - Open failed.
+* Other value - a valid handle
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_HANDLE DclSTS_Open(DCL_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* DclSTS_ReadData
+*
+* DESCRIPTION
+* This function unsupported.
+*
+* CALLS
+* It is unsupported.
+*
+* PARAMETERS
+* handle
+* buff
+* buf_len
+* options
+*
+* RETURNS
+* STATUS_UNSUPPORTED: command unsupported
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclSTS_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN *buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclSTS_RegisterCallback
+*
+* DESCRIPTION
+* This function is to register SW TS call back funciton.
+* Execute call back function when we push ts data into ts ring buffer.
+*
+* CALLS
+* It is called to register SW TS call back funciton.
+*
+* PARAMETERS
+* event - a valid event indicate register which event's call back funciton
+* 1. DCL_EVENT_STS_PUSH_BUFF
+*
+* callback - a call back funciton
+*
+* RETURNS
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclSTS_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+/*************************************************************************
+* FUNCTION
+* DclSTS_Close
+*
+* DESCRIPTION
+* This function is to close the SW TS module.
+*
+* CALLS
+* It is called to close SW TS module
+*
+* PARAMETERS
+* None
+*
+* RETURNS
+* DCL_STATUS_OK
+* STATUS_INVALID_ARGUMENT: invalid arguments
+*
+* GLOBALS AFFECTED
+* external_global
+*************************************************************************/
+extern DCL_STATUS DclSTS_Close(DCL_HANDLE handle);
+
+
+#endif // #ifndef __DCL_TS_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
diff --git a/mcu/interface/driver/peripheral/dcl_uart.h b/mcu/interface/driver/peripheral/dcl_uart.h
new file mode 100644
index 0000000..6ac8877
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_uart.h
@@ -0,0 +1,1670 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_uart.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for UART.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_UART_STRUCT__
+#define __DCL_UART_STRUCT__
+
+#if defined(__CMUX_SUPPORT__)
+#include "cmux_vp_num.h"
+#define VIRTUAL_PORT_NUM CMUX_VP_NUM
+#else // #if defined(__CMUX_SUPPORT__)
+#define VIRTUAL_PORT_NUM 0
+#endif // #if defined(__CMUX_SUPPORT__)
+
+/*!
+ * @brief it defines DCL UART Device port enumeration
+ */
+#define DCL_UART_DEV \
+ uart_port1=0x00, \
+ uart_port2, \
+ uart_port3, \
+ /*uart_port_irda,*/\
+ uart_port_usb,\
+ uart_port_usb2,\
+ uart_port_usb3,\
+ uart_port_usb4,\
+ uart_port_usb5,\
+ uart_port_usb6,\
+ uart_port_usb7,\
+ uart_port_usb8,\
+ uart_port_usb_sp_direct,\
+ /*uart_port_bluetooth,*/\
+ /*uart_port_swdbg,*/\
+ uart_port_dhl_sp_expt,\
+ uart_port_dhl_eap_expt = uart_port_dhl_sp_expt,\
+ uart_port_dhl_ctrl_sp_expt,\
+ uart_port_meta_eap_expt = uart_port_dhl_ctrl_sp_expt,\
+ uart_port_dhl_sp,\
+ uart_port_dhl_ccci = uart_port_dhl_sp,\
+ uart_port_ccci_start = uart_port_dhl_ccci,\
+ uart_port_dhl_ctrl_sp,\
+ uart_port_tst_ccci = uart_port_dhl_ctrl_sp,\
+ uart_port_at_ccci,\
+ uart_port_gps_ccci,\
+ uart_port_sim_ccci,\
+ uart_port_dhl2_ccci,\
+ uart_port_atcp_ccci,\
+ uart_port_c2k_ppp_ccci,\
+ uart_port_c2k_agps_ccci,\
+ uart_port_cellinfo_ccci,\
+ uart_port_imsm_ccci,\
+ uart_port_woa_ccci,\
+ uart_port_xui_ccci,\
+ uart_port_bip_ccci,\
+ uart_port_udc_ccci,\
+ uart_port_nlopt_ccci,\
+ uart_port_nlopp_ccci,\
+ uart_port_sar_ccci,\
+ uart_port_ciq_ccci,\
+ uart_port_ikeraw_ccci,\
+ uart_port_ril_ipc0_ccci,\
+ uart_port_ril_ipc1_ccci,\
+ uart_port_vt_ccci,\
+ uart_port_cc_state_ccci,\
+ uart_port_mipi_ccci,\
+ uart_port_mipc_ap0_ccci,\
+ uart_port_mipc_ap1_ccci,\
+ uart_port_mipc_ap2_ccci,\
+ uart_port_mipc_ap3_ccci,\
+ uart_port_mipc_ap4_ccci,\
+ uart_port_mipc_ap5_ccci,\
+ uart_port_mipc_ap6_ccci,\
+ uart_port_mipc_ap7_ccci,\
+ uart_port_mipc_ap8_ccci,\
+ uart_port_mipc_ap9_ccci,\
+ uart_port_mipc_eap0_ccci,\
+ uart_port_mbim_eap0_ccci,\
+ uart_port_log_eap_ccci, uart_port_dhl_eap = uart_port_log_eap_ccci,\
+ uart_port_meta_eap_ccci, uart_port_meta_eap = uart_port_meta_eap_ccci,\
+ uart_port_epdg_ccci,\
+ uart_port_epdg2_ccci,\
+ uart_port_epdg3_ccci,\
+ uart_port_epdg4_ccci,\
+ uart_port_mbim_eap_dss0_ccci,\
+ uart_port_mbim_eap_dss1_ccci,\
+ uart_port_mbim_eap_dss2_ccci,\
+ uart_port_mbim_eap_dss3_ccci,\
+ uart_port_mbim_eap_dss4_ccci,\
+ uart_port_mbim_eap_dss5_ccci,\
+ uart_port_mbim_eap_dss6_ccci,\
+ uart_port_mbim_eap_dss7_ccci,\
+ uart_port_mipc_ap10_ccci,\
+ uart_port_mipc_ap11_ccci,\
+ uart_port_mipc_ap12_ccci,\
+ uart_port_mipc_ap13_ccci,\
+ uart_port_mipc_ap14_ccci,\
+ uart_port_ccci_end = uart_port_mipc_ap14_ccci,\
+ start_of_virtual_port,\
+ end_of_virtual_port = (VIRTUAL_PORT_NUM + start_of_virtual_port),\
+ /*uart_port_dcc,*/\
+ /*uart_port_lga1,*/\
+ /*uart_port_lga2,*/\
+ /*uart_port_lmu,*/\
+ /*uart_port_sp_usb,*/\
+ /*uart_port_sp_usb_dsp,*/\
+ uart_port_mini_log,\
+ uart_port_dual_talk,\
+ uart_port_modis,/*only for modis*/\
+ uart_port_mtad,\
+ uart_max_port,\
+ uart_port_null = 99,
+
+
+/*******************************************************************************
+ * DCL_CTRL_CMD for UART
+ *******************************************************************************/
+/*!
+ * @brief it defines DCL UART commands, including SIO/UART/USB/TTY commands
+ * Since TTY architecture has been modified and enhanced, there are some summaries for UART commands:
+ * - Data related SIO commands, such as
+ * SIO_CMD_PUT_BYTES
+ * SIO_CMD_PUT_ISR_BYTES,
+ * SIO_CMD_PUT_UART_BYTE
+ * SIO_CMD_PUT_UART_BYTES
+ * SIO_CMD_GET_TX_AVAIL
+ * SIO_CMD_GET_ISR_TX_AVAIL
+ * -> only support for conventional Tx Path.
+ * SIO_CMD_GET_BYTES
+ * SIO_CMD_GET_UART_BYTE
+ * SIO_CMD_GET_RX_AVAIL
+ * -> only support for conventional Rx Path.
+ * SIO_CMD_SEND_ISR_DATA
+ * SIO_CMD_SEND_DATA
+ * -> not support for all path.
+ * are not supported for new upper layer modules which use NEW TTY architecture.
+ * - TTY commands are added for new TTY architecture.
+ * among these commands, TTY_CMD_PUT_BYTES_IOR is to put bytes with ior format.
+ * But the upper layer modules don't need to take care TTY_CMD_PUT_BYTES_IOR commands. They only use DclSerialPort_UpModuleTransmit API to put data.
+ * - Driver must implement the following commands:
+ * SIO_CMD_INIT
+ * SIO_CMD_OPEN
+ * SIO_CMD_CLOSE
+ * SIO_CMD_PURGE
+ * SIO_CMD_SET_OWNER
+ * SIO_CMD_CLR_RX_BUF
+ * SIO_CMD_CLR_TX_BUF
+ * SIO_CMD_GET_OWNER_ID
+ * TTY_CMD_PUT_BYTES_IOR
+ * TTY_CMD_GET_CHUNK_SIZE
+ * TTY_CMD_ASSIGN_RX_IOR
+ * TTY_CMD_NEED_TX_DONE_CB
+ * , other commands
+ * - UART commands UART_CMD_BOOT_PUTBYTES & UART_CMD_BMT_PUT_BYTES still use buffer/length instead of ior as parameter.
+ *
+ * Notes of some commands:
+ * - SIO_CMD_CLR_TX_BUF : it would block and sleep before the command returns in conventional Tx mode.
+ * - SIO_CMD_CLR_RX_BUF : it would block and sleep before the command returns in conventional Rx mode.
+ * - SIO_CMD_SET_OWNER : it would block and sleep before the command returns in conventional Tx or Rx mode.
+ * - SIO_CMD_CLOSE : it would block and sleep before the command returns in conventional Tx or Rx mode.
+ * - SIO_CMD_PUT_ISR_BYTES : This command doesn't guarantee that all data can be sent successfully in conventional Tx mode since it won't send ReadyToWrite ilm.
+ */
+#define UART_CMDS \
+ SIO_CMD_INIT = 0x00,\
+ SIO_CMD_OPEN,\
+ SIO_CMD_CLOSE,\
+ SIO_CMD_GET_BYTES,\
+ SIO_CMD_PUT_BYTES,\
+ SIO_CMD_GET_RX_AVAIL,\
+ SIO_CMD_GET_TX_AVAIL,\
+ SIO_CMD_PUT_ISR_BYTES,\
+ SIO_CMD_GET_ISR_TX_AVAIL,\
+ SIO_CMD_PURGE,\
+ SIO_CMD_SET_OWNER,\
+ SIO_CMD_SET_FLOW_CTRL,\
+ SIO_CMD_CONFIG_ESCAPE,\
+ SIO_CMD_SET_DCB_CONFIG,\
+ SIO_CMD_CTRL_DCD,\
+ SIO_CMD_CTRL_BREAK, \
+ SIO_CMD_CLR_RX_BUF,\
+ SIO_CMD_CLR_TX_BUF, \
+ SIO_CMD_SET_BAUDRATE, \
+ SIO_CMD_SEND_ISR_DATA, \
+ SIO_CMD_SEND_DATA, \
+ SIO_CMD_GET_OWNER_ID, \
+ SIO_CMD_SET_AUTOBAUD_DIV, \
+ SIO_CMD_REG_TX_CB,\
+ SIO_CMD_REG_RX_CB,\
+ SIO_CMD_GET_UART_BYTE,\
+ SIO_CMD_PUT_UART_BYTE,\
+ SIO_CMD_PUT_UART_BYTES,\
+ SIO_CMD_READ_DCB_CONFIG,\
+ SIO_CMD_CTRL_RI,\
+ SIO_CMD_GET_ESCAPE_INFO,\
+ SIO_CMD_CTRL_DTR,\
+ SIO_CMD_READ_HW_STATUS,\
+ SIO_CMD_GET_UART_BYTE_WITH_TIMEOUT,\
+ UART_CMD_UART_START = 0x100,\
+ UART_CMD_SET_FIFO_TRIGGER,\
+ UART_CMD_POWER_ON,\
+ UART_CMD_CHECK_TX_BUF_EMPTY,\
+ UART_CMD_CHECK_TX_SEND_OUT,\
+ UART_CMD_GET_TX_BUF_SIZE,\
+ UART_CMD_SLEEP_TX_ENABLE,\
+ UART_CMD_CTRL_SLEEP_MODE,\
+ UART_CMD_SWITCH_PORT,\
+ UART_CMD_BOOTUP_INIT,\
+ UART_CMD_BOOT_PUTBYTES,\
+ UART_CMD_LOOPBACK,\
+ UART_CMD_ASSERT_WAIT_SEND_OUT,\
+ UART_CMD_CTRL_USE_VFIFO,\
+ UART_CMD_GET_FLOW_CONTROL,\
+ UART_CMD_REG_DEF_CB,\
+ UART_CMD_BMT_PUT_BYTES,\
+ UART_CMD_RECHANDLER_VFIFO,\
+ UART_CMD_TRXHANDLER_VFIFO,\
+ UART_CMD_RECTIMEOUTHANDLE,\
+ UART_CMD_CTRL_TX_DMA,\
+ UART_CMD_GET_MAX_BAUDRATE,\
+ UART_CMD_UART_END,\
+ USB_CMD_UART_START = 0x200,\
+ USB_CMD_IS_CDCACM,\
+ USB_CMD_HIGH_SPEED_IF_ENABLE, \
+ USB_CMD_REG_TX_CB, \
+ USB_CMD_TX_DATA_STATUS, \
+ USB_CMD_SEND_DATA, \
+ USB_CMD_GET_DATA, \
+ USB_CMD_SEND_ISR_DATA, \
+ USB_CMD_CTRL_SEND_DATA, \
+ USB_CMD_CTRL_GET_DATA, \
+ USB_CMD_HALT, \
+ USB_CMD_FT_PORT, \
+ USB_CMD_ACM_RING_BUFF_THRESHOLD_EN, \
+ USB_CMD_USB2UART_TX_DMA_CBK, \
+ USB_CMD_BOOT_PUTBYTES, \
+ USB_CMD_IS_CDCACM_ACTIVE,\
+ USB_CMD_UART_END, \
+ TTY_CMD_UART_START = 0x300,\
+ TTY_CMD_GET_CHUNK_SIZE,\
+ TTY_CMD_ASSIGN_RX_IOR,\
+ TTY_CMD_NEED_TX_DONE_CB,\
+ TTY_CMD_GET_DRV_STATE,\
+ TTY_CMD_PUT_BYTES_IOR,\
+ TTY_CMD_PUT_BYTES_IOR_LIGHT,\
+ TTY_CMD_GET_MTU_SIZE,\
+ TTY_CMD_SET_INDICATION,\
+ TTY_CMD_UART_END,\
+ TTY_CMD_EXCEPTION_START = 0x400,\
+ TTY_CMD_EXCEPTION_RESET,\
+ TTY_CMD_EXCEPTION_HIF_INIT,\
+ TTY_CMD_EXCEPTION_CLEAR_CHANNEL,\
+ TTY_CMD_EXCEPTION_TX_GPD,\
+ TTY_CMD_EXCEPTION_TX_DONE_INFO,\
+ TTY_CMD_EXCEPTION_HIF_STATE,\
+ TTY_CMD_EXCEPTION_ASSIGN_RX_GPD,\
+ TTY_CMD_EXCEPTION_GET_RX_GPD,\
+ TTY_CMD_EXCEPTION_HIF_POLL,\
+ TTY_CMD_EXCEPTION_HIF_RESET_LINK,\
+ TTY_CMD_EXCEPTION_FLUSH_TX,\
+ TTY_CMD_EXCEPTION_FLUSH_RX,\
+ TTY_CMD_EXCEPTION_END,
+
+//
+typedef enum
+{
+ DCL_UART_TYPE = 0x00,
+ DCL_UART_USB_TYPE,
+ DCL_UART_BLUETOOTH_TYPE,
+ DCL_UART_CMUX_TYPE,
+ DCL_UART_SPPA_TYPE,
+ DCL_UART_CCCI_TYPE,
+ DCL_UART_CCIF_TYPE,
+ DCL_UART_DCC_TYPE,
+ DCL_UART_LOGACC_TYPE,
+ DCL_UART_LMU_TYPE,
+ DCL_UART_SP_USB_TYPE,
+ DCL_UART_MINI_LOG_TYPE,
+ DCL_UART_MTAD_TYPE,
+ DCL_UART_DEV_TYPE_MAX
+}SIO_TYPE_T;
+
+typedef DCL_UINT32 UART_BAUDRATE_T;
+typedef UART_BAUDRATE_T UART_baudrate;
+typedef DCL_UINT16 UART_PORT;
+
+#define UART_BAUD_AUTO 0
+#define UART_BAUD_75 75
+#define UART_BAUD_150 150
+#define UART_BAUD_300 300
+#define UART_BAUD_600 600
+#define UART_BAUD_1200 1200
+#define UART_BAUD_2400 2400
+#define UART_BAUD_4800 4800
+#define UART_BAUD_7200 7200
+#define UART_BAUD_9600 9600
+#define UART_BAUD_14400 14400
+#define UART_BAUD_19200 19200
+#define UART_BAUD_28800 28800
+#define UART_BAUD_33900 33900
+#define UART_BAUD_38400 38400
+#define UART_BAUD_57600 57600
+#define UART_BAUD_115200 115200
+#define UART_BAUD_230400 230400
+#define UART_BAUD_460800 460800
+#define UART_BAUD_921600 921600
+#define UART_BAUD_1500000 1500000
+
+#define UART_TO_ELT_BAUD 1500000
+
+typedef enum {
+ LEN_5=5,
+ LEN_6,
+ LEN_7,
+ LEN_8
+} UART_BITS_PER_CHAR_T;
+
+typedef enum {
+ SB_1=1,
+ SB_2,
+ SB_1_5
+} UART_STOP_BITS_T;
+
+typedef enum {
+ PA_NONE=0,
+ PA_ODD,
+ PA_EVEN,
+ PA_SPACE
+} UART_PARITY_T;
+
+/*
+#if defined(FC_NONE)
+#undef FC_NONE
+#endif
+*/
+
+typedef enum {
+ FC_NONE=1,
+ FC_HW,
+ FC_SW
+} UART_FLOW_CTRL_MODE_T;
+
+typedef enum {
+ DCL_NONE_VFIFO,
+ DCL_RX_VFIFO,
+ DCL_TX_VFIFO,
+ DCL_TXRX_VFIFO
+} UART_VFIFO_T;
+
+typedef enum {
+ uart_sleep_on_tx_allow = 0,
+ uart_sleep_on_tx_forbid
+} UART_SLEEP_ON_TX;
+
+
+
+typedef struct
+{
+ UART_BAUDRATE_T u4Baud;
+ DCL_UINT8 u1DataBits; //UART_BITS_PER_CHAR_T
+ DCL_UINT8 u1StopBits; //UART_STOP_BITS_T
+ DCL_UINT8 u1Parity; //UART_PARITY_T
+ DCL_UINT8 u1FlowControl; //UART_FLOW_CTRL_MODE_T
+ DCL_UCHAR ucXonChar;
+ DCL_UCHAR ucXoffChar;
+ DCL_BOOLEAN fgDSRCheck;
+} UART_CONFIG_T;
+
+typedef enum
+{
+ DCL_IO_Low=0,
+ DCL_IO_High
+} IO_LEVEL_T;
+
+
+typedef enum {
+ DCL_RX_BUF,
+ DCL_TX_BUF
+} UART_BUFFER_T;
+
+typedef enum {
+ DCL_UART_SLEEP_ON_TX_ALLOW = 0,
+ DCL_UART_SLEEP_ON_TX_FORBID,
+} UART_SLEEP_ON_TX_T;
+
+typedef enum {
+ DCL_UART_BY_VFIFO,
+ DCL_UART_BY_DMA,
+ DCL_UART_BY_MCU,
+ DCL_UART_BY_UNKNOWN
+} UART_WORK_MODE;
+
+
+/*!
+ * @brief tty_io_request_t is a typedef of struct _tty_io_request
+ */
+typedef struct _tty_io_request_t tty_io_request_t;
+
+/*!
+ * @brief struct _tty_io_request_t describe io request used to communicate
+ * between ap module & tty
+ */
+struct _tty_io_request_t{
+ /*!
+ * @brief next io request
+ */
+ tty_io_request_t *next_request;
+ /*!
+ * @brief pointer to current gpd of this io request
+ */
+ void *first_gpd;
+ /*!
+ * @brief pointer to last gpd of this io request
+ */
+ void *last_gpd;
+};
+
+//UART_CMD_INIT
+typedef struct
+{
+ DCL_UINT32 u4Flag;
+}UART_CTRL_INIT_T;
+
+//UART_CMD_OPEN
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+}UART_CTRL_OPEN_T;
+
+//UART_CMD_CLOSE
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+}UART_CTRL_CLOSE_T;
+
+//UART_CMD_GET_BYTES
+typedef struct
+{
+ DCL_UINT16 u2Length;
+ DCL_UINT32 u4OwenrId;
+ DCL_UINT16 u2RetSize;
+ DCL_UINT8* puBuffaddr;
+ DCL_UINT8* pustatus;
+
+}UART_CTRL_GET_BYTES_T;
+
+//UART_CMD_PUT_BTYES
+//UART_CMD_PUT_ISR_BYTES
+typedef struct
+{
+ DCL_UINT16 u2Length;
+ DCL_UINT32 u4OwenrId;
+ DCL_UINT16 u2RetSize;
+ DCL_UINT8* puBuffaddr;
+}UART_CTRL_PUT_BYTES_T;
+
+typedef struct
+{
+ DCL_UINT32 u4OwnerId;
+ void *putIor;
+}UART_CTRL_PUT_BYTES_IOR_T;
+
+//UART_CMD_GET_RX_AVAIL
+typedef struct
+{
+ DCL_UINT16 u2RetSize;
+}UART_CTRL_RX_AVAIL_T;
+
+//UART_CMD_GET_TX_AVAIL
+//UART_CMD_GET_ISR_TX_AVAIL
+typedef struct
+{
+ DCL_UINT16 u2RetSize;
+}UART_CTRL_TX_AVAIL_T;
+
+//UART_CMD_PURGE
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+ UART_BUFFER_T dir;
+}UART_CTRL_PURGE_T;
+
+//UART_CMD_SET_OWNER
+//UART_CMD_GET_OWNER_ID
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+}UART_CTRL_OWNER_T;
+
+//UART_CMD_SET_FLOW_CTRL
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+ DCL_BOOL bXON;
+}UART_CTRL_FLOW_CTRL_T;
+
+//UART_CMD_CONFIG_ESCAPE
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+ DCL_UINT8 uEscChar;
+ DCL_UINT16 u2ESCGuardtime;
+} UART_CTRL_CONFIG_ESP_T;
+
+//UART_CMD_SET_DCB_COFIG
+//UART_CMD_READ_DCB_CONFIG
+
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+ UART_CONFIG_T rUARTConfig;
+} UART_CTRL_DCB_T;
+
+//UART_CMD_CTRL_DCD
+
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+ IO_LEVEL_T rIOLevelDCD;
+} UART_CTRL_DCD_T;
+
+//UART_CMD_GET_FLOW_CONTROL
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+ UART_FLOW_CTRL_MODE_T FlowCtrlMode;
+}UART_CTRL_GET_FC_T;
+
+//TTY_CMD_GET_CHUNK_SIZE
+typedef struct
+{
+ DCL_UINT32 chunkSize;
+} UART_CTRL_GET_CHUNK_SIZE_T;
+
+//TTY_CMD_NEED_TX_DONE_CB
+typedef struct
+{
+ DCL_UINT32 u4OwnerId;
+ DCL_BOOL needTxDoneCb;
+} UART_CTRL_NEED_TX_DONE_CB_T;
+
+//TTY_CMD_GET_MTU_SIZE
+typedef struct
+{
+ DCL_UINT32 ulmtu_sz;
+ DCL_UINT32 dlmtu_sz;
+} UART_CTRL_GET_MTU_SIZE_T;
+
+//TTY_CMD_SET_INDICATION
+typedef struct
+{
+ DCL_BOOL need_indication;
+} UART_CTRL_SET_INDICATION_T;
+
+/*!
+ * @brief TTY driver state
+ */
+typedef enum _tty_drv_state {
+ /*!
+ * @brief driver detached state
+ */
+ DRV_ST_DETACHED = 0,
+ /*!
+ * @brief driver attached state
+ */
+ DRV_ST_ATTACHED
+} tty_drv_state_e;
+
+//TTY_CMD_GET_DRV_STATE
+typedef struct
+{
+ DCL_UINT32 u4OwnerId;
+ tty_drv_state_e drv_state;
+} UART_CTRL_GET_DRV_STATE_T;
+
+//TTY_CMD_ASSIGN_RX_IOR
+typedef struct
+{
+ DCL_UINT32 u4OwnerId;
+ void *ior;
+} UART_CTRL_ASSIGN_RX_IOR_T;
+
+//UART_CMD_CTRL_BREAK
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+ IO_LEVEL_T rIOLevelBRK;
+} UART_CTRL_BREAK_T;
+
+//UART_CMD_CLR_RX_BUF
+//UART_CMD_CLR_TX_BUF
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+} UART_CTRL_CLR_BUFFER_T;
+
+//UART_CMD_SET_BAUDRATE
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+ UART_BAUDRATE_T baudrate;
+} UART_CTRL_BAUDRATE_T;
+
+//UART_CMD_SEND_ISR_DATA
+//UART_CMD_SEND_DATA
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+ DCL_UINT8* puBuffaddr;
+ DCL_UINT16 u2Length;
+ DCL_UINT8 umode;
+ DCL_UINT8 uescape_char;
+ DCL_UINT16 u2RetSize;
+}UART_CTRL_SEND_DATA_T;
+
+//UART_CMD_SET_AUTOBAUD_DIV
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+} UART_CTRL_AUTO_BAUDDIV_T;
+
+typedef void (*DCL_UART_TX_FUNC)(DCL_UINT32 u4Port);
+typedef void (*DCL_UART_RX_FUNC)(DCL_UINT32 u4Port) ;
+
+
+//UART_CMD_REG_TX_CB
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+ DCL_UART_TX_FUNC func;
+} UART_CTRL_REG_TX_CB_T;
+
+
+//UART_CMD_REG_RX_CB
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+
+ DCL_UART_RX_FUNC func;
+} UART_CTRL_REG_RX_CB_T;
+
+typedef enum
+{
+ UART_TX = 0,
+ UART_RX,
+ DSP_TX,
+ DSP_RX
+}UART_IO_DIR;
+
+//UART_CMD_REG_DEF_CB
+typedef struct
+{
+ UART_IO_DIR dir;
+}UART_CTRL_REG_DEF_CB_T;
+
+//UART_CMD_GET_UART_BYTE
+typedef struct
+{
+ DCL_UINT8 uByte;
+}UART_CTRL_GET_UART_BYTE_T;
+
+//SIO_CMD_GET_UART_BYTE_WITH_TIMEOUT
+typedef struct
+{
+ DCL_UINT8 u1retByte;
+ DCL_UINT8 uByte;
+ DCL_UINT32 u4timeout_value;
+}UART_CTRL_GET_UART_BYTE_WITH_TIMEOUT_T;
+
+//UART_CMD_PUT_UART_BYTE
+typedef struct
+{
+ DCL_UINT8 uData;
+}UART_CTRL_PUT_UART_BYTE_T;
+
+//UART_CMD_PUT_UART_BYTES
+typedef struct
+{
+ DCL_UINT8* puBuffaddr;
+ DCL_UINT16 u2Length;
+
+}UART_CTRL_PUT_UART_BYTES_T;
+
+//UART_CMD_CTRL_RI
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+ IO_LEVEL_T rIOLevelSRI;
+
+}UART_CTRL_RI_T;
+
+//UART_CMD_CTRL_DTR
+typedef struct
+{
+ DCL_UINT32 u4OwenrId;
+ IO_LEVEL_T rIOLevelDTR;
+}UART_CTRL_DTR_T;
+
+//UART_CMD_READ_HW_STATUS
+typedef struct
+{
+ IO_LEVEL_T rIOLevelDSR;
+ IO_LEVEL_T rIOLevelCTS;
+}UART_CTRL_RHS_T;
+
+//UART_CMD_SET_FIFO_TRIGGER
+typedef struct
+{
+ DCL_UINT16 tx_level;
+ DCL_UINT16 rx_level;
+}UART_CTRL_SFT_T;
+
+//UART_CMD_POWER_ON
+typedef struct
+{
+ DCL_BOOL bFlag_Poweron;
+}UART_CTRL_POWERON_T;
+
+//UART_CMD_CHECK_TX_BUF_EMPTY
+typedef struct
+{
+ DCL_BOOL bFlag;
+}UART_CTRL_CHECK_TBE_T;
+
+// UART_CMD_CHECK_TX_SEND_OUT
+typedef struct
+{
+ DCL_BOOL bFlag;
+}UART_CTRL_CHECK_TSO_T;
+
+//UART_CMD_GET_TX_BUF_SIZE
+typedef struct
+{
+ DCL_UINT32* ptotal_size;
+ DCL_UINT32* preturn_size;
+}UART_CTRL_GET_TBS_T;
+
+
+//UART_CMD_SLEEP_TX_ENABLE
+typedef struct
+{
+ UART_SLEEP_ON_TX_T bFlag;
+}UART_CTRL_SLEEP_ON_TX_ENABLE_T;
+
+//UART_CMD_CTRL_SLEEP_MODE
+typedef struct
+{
+ DCL_BOOL bFlag;
+}UART_CTRL_SLEEP_ENABLE_T;
+
+
+//UART_CMD_BOOT_PUTBYTES
+typedef struct
+{
+ DCL_UINT8* puBuffaddr;
+ DCL_UINT16 u2Length;
+}UART_CTRL_BOOT_PUTBYTES_T;
+
+
+//UART_CMD_CTRL_USE_VFIFO
+typedef struct
+{
+ DCL_BOOL bUseVFifo;
+}UART_CTRL_USE_VFIFO_T;
+
+//UART_CMD_GET_MAX_BAUDRATE
+typedef struct
+{
+ kal_uint32 max_baudrate;
+}UART_CTRL_GET_MAXBAUDRATE_T;
+
+//TTY_CMD_EXCEPTION_TX_GPD
+typedef struct
+{
+ void *first_gpd;
+ void *last_gpd;
+}TTY_CTRL_EXCP_TX_GPD_T;
+
+//TTY_CMD_EXCEPTION_TX_DONE_INFO
+typedef struct
+{
+ void *first_gpd;
+ void *last_gpd;
+ DCL_UINT32 num;
+}TTY_CTRL_EXCP_TX_DONE_INFO_T;
+
+//TTY_CMD_EXCEPTION_HIF_STATE
+typedef enum _tty_excp_hif_state {
+ HIF_STATE_NORMAL = 0,
+ HIF_STATE_TXERROR
+} tty_excp_hif_state;
+typedef struct
+{
+ tty_excp_hif_state hif_state;
+}TTY_CTRL_EXCP_HIF_STATE_T;
+
+//TTY_CMD_EXCEPTION_ASSIGN_RX_GPD
+typedef struct
+{
+ void *first_gpd;
+ void *last_gpd;
+}TTY_CTRL_EXCP_ASSIGN_RX_GPD_T;
+
+//TTY_CMD_EXCEPTION_GET_RX_GPD
+typedef struct
+{
+ void *first_gpd;
+ void *last_gpd;
+ DCL_UINT32 num;
+}TTY_CTRL_EXCP_GET_RX_GPD_T;
+
+//TTY_CMD_EXCEPTION_FLUSH_TX
+typedef struct
+{
+ void *first_gpd;
+ void *last_gpd;
+ DCL_UINT32 num;
+}TTY_CTRL_EXCP_FLUSH_TX_T;
+
+//TTY_CMD_EXCEPTION_FLUSH_RX
+typedef struct
+{
+ void *first_gpd;
+ void *last_gpd;
+ DCL_UINT32 num;
+}TTY_CTRL_EXCP_FLUSH_RX_T;
+
+//TTY_CMD_EXCEPTION_HIF_POLL
+typedef struct
+{
+ DCL_BOOL reset_event;
+}TTY_CTRL_EXCP_HIF_POLL_T;
+
+typedef enum {
+ NONE_VFIFO,
+ RX_VFIFO,
+ TX_VFIFO,
+ TXRX_VFIFO
+} UART_TxRx_VFIFO_support;
+
+typedef enum {
+ RX_BUF,
+ TX_BUF
+} UART_buffer;
+
+typedef enum {
+ Compensate_None = 0,
+ Compensate_Wait,
+ Compensate_AT,
+ Compensate_at
+}UART_Compensate_enum;
+
+
+typedef enum {
+ len_5=5,
+ len_6,
+ len_7,
+ len_8
+} UART_bitsPerCharacter;
+
+typedef enum {
+ sb_1=1,
+ sb_2,
+ sb_1_5
+} UART_stopBits;
+
+typedef enum {
+ pa_none=0,
+ pa_odd,
+ pa_even,
+ pa_mark, //k2 md2 6589, add for solving driver/peripheral uart module build error
+ pa_space
+} UART_parity;
+
+typedef enum {
+ fc_none=1,
+ fc_hw,
+ fc_sw
+} UART_flowCtrlMode;
+
+typedef struct
+{
+ UART_baudrate baud;
+ UART_bitsPerCharacter dataBits;
+ UART_stopBits stopBits;
+ UART_parity parity;
+ UART_flowCtrlMode flowControl;
+ kal_uint8 xonChar;
+ kal_uint8 xoffChar;
+ kal_bool DSRCheck;
+} UARTDCBStruct;
+
+typedef struct
+{
+ kal_uint8 EscChar;
+ kal_uint16 GuardTime;
+} UART_ESCDetectStruct;
+
+typedef struct
+{
+ kal_uint8 *rx_buffer; /* data buffer */
+ kal_uint8 *tx_buffer; /* data buffer */
+ kal_uint8 *txISR_buffer; /* data buffer */
+} UART_RingBufferStruct;
+
+
+ typedef enum {
+ uart_null_buffer=0,
+ uart_isr_buffer,
+ uart_normal_buffer
+ } UART_RingBuffer_Type;
+
+ typedef struct
+ {
+ UART_RingBuffer_Type type;
+ kal_uint16 index;
+ } UART_RingBuffer_SaveIndex;
+
+
+typedef struct
+{
+ kal_uint16 tst_port_ps;
+ kal_uint16 ps_port;
+ UART_baudrate tst_baudrate_ps;
+ UART_baudrate ps_baudrate;
+ kal_bool High_Speed_SIM_Enabled;
+ kal_uint8 swdbg;
+ kal_uint8 uart_power_setting; /* For DCM, Start [Set UART POWER], CTI */
+ kal_uint8 cti_uart_port;
+ UART_baudrate cti_baudrate;
+ kal_uint8 tst_port_l1;
+ UART_baudrate tst_baudrate_l1;
+ kal_uint8 tst_output_mode;
+ kal_uint8 usb_logging_mode;
+ kal_uint16 tst_port_dsp;
+ UART_baudrate tst_baud_rate_dsp;
+ kal_uint8 usb_cdrom_config;
+ kal_uint16 speech_port;
+ kal_uint16 ndis_port;
+ kal_uint16 epdg_cmd_port;
+ kal_uint16 epdg_urc_port;
+ kal_uint16 epdg_cmd_port_2;
+ kal_uint16 epdg_urc_port_2;
+} port_setting_struct;
+
+/*start of local parameter struct */
+
+typedef struct
+{
+ LOCAL_PARA_HDR /* LOCAL_PARA_HDR */
+ DCL_UINT16 port;
+}uart_ready_to_read_ind_struct;
+
+typedef struct
+{
+ LOCAL_PARA_HDR /* LOCAL_PARA_HDR */
+ DCL_UINT16 port;
+}uart_ready_to_write_ind_struct;
+
+ typedef struct
+{
+ LOCAL_PARA_HDR /* LOCAL_PARA_HDR */
+ DCL_UINT16 port;
+}uart_dsr_change_ind_struct;
+
+ typedef struct
+{
+ LOCAL_PARA_HDR /* LOCAL_PARA_HDR */
+ DCL_UINT16 port;
+}uart_escape_detected_ind_struct;
+
+ typedef struct
+{
+ LOCAL_PARA_HDR /* LOCAL_PARA_HDR */
+ DCL_UINT16 port;
+}uart_plugin_ind_struct;
+
+ typedef struct
+{
+ LOCAL_PARA_HDR /* LOCAL_PARA_HDR */
+ DCL_UINT16 port;
+}uart_plugout_ind_struct;
+
+
+#define UART_CTRLS \
+ UART_CTRL_INIT_T rUARTCtrlInit;\
+ UART_CTRL_OPEN_T rUARTCtrlOPEN; \
+ UART_CTRL_CLOSE_T rUARTCtrlCLOSE; \
+ UART_CTRL_GET_BYTES_T rUARTCtrlGETBYTES; \
+ UART_CTRL_PUT_BYTES_T rUARTCtrlPUTBYTES; \
+ UART_CTRL_RX_AVAIL_T rUARTCtrlRXAVAIL; \
+ UART_CTRL_TX_AVAIL_T rUARTCtrlTXAVAIL; \
+ UART_CTRL_PURGE_T rUARTCtrlPURGE; \
+ UART_CTRL_OWNER_T rUARTCtrlOWNER; \
+ UART_CTRL_FLOW_CTRL_T rUARTCtrlFLOWCTRL; \
+ UART_CTRL_CONFIG_ESP_T rUARTCtrlCONFIGESP; \
+ UART_CTRL_DCB_T rUARTCtrlDCB; \
+ UART_CTRL_DCD_T rUARTCtrlDCD;\
+ UART_CTRL_BREAK_T rUARTCtrlBREAK;\
+ UART_CTRL_CLR_BUFFER_T rUARTCtrlCLRBUFFER;\
+ UART_CTRL_BAUDRATE_T rUARTCtrlBAUDRATE;\
+ UART_CTRL_SEND_DATA_T rUARTCtrlSENDDATA;\
+ UART_CTRL_AUTO_BAUDDIV_T rUARTCtrlAUTOBAUDDIV;\
+ UART_CTRL_REG_TX_CB_T rUARTCtrlREGTXCB;\
+ UART_CTRL_REG_RX_CB_T rUARTCtrlREGRXCB;\
+ UART_CTRL_GET_UART_BYTE_T rUARTCtrlGETUARTBYTE;\
+ UART_CTRL_GET_UART_BYTE_WITH_TIMEOUT_T rUARTCtrlGETUARTBYTEWithTimeOut;\
+ UART_CTRL_PUT_UART_BYTE_T rUARTCtrlPUTUARTBYTE;\
+ UART_CTRL_PUT_UART_BYTES_T rUARTCtrlPUTUARTBYTES;\
+ UART_CTRL_RI_T rUARTCtrlRI;\
+ UART_CTRL_DTR_T rUARTCtrlDTR;\
+ UART_CTRL_RHS_T rUARTCtrlRHS;\
+ UART_CTRL_SFT_T rUARTCtrlSFT;\
+ UART_CTRL_POWERON_T rUARTCtrlPoweron;\
+ UART_CTRL_CHECK_TBE_T rUARTCtrlCheckBUFEMP;\
+ UART_CTRL_CHECK_TSO_T rUARTCtrlCheckTXSendOut;\
+ UART_CTRL_GET_TBS_T rUARTCtrlGetTxBufSize;\
+ UART_CTRL_SLEEP_ON_TX_ENABLE_T rUARTCtrlSleepOnTxEnable;\
+ UART_CTRL_SLEEP_ENABLE_T rUARTCtrlSleepEnable;\
+ UART_CTRL_BOOT_PUTBYTES_T rUARTCtrlBootPutBytes;\
+ UART_CTRL_USE_VFIFO_T rUARTCtrlUseVFifo;\
+ UART_CTRL_REG_DEF_CB_T rUARTCtrlRegDefCB;\
+ UART_CTRL_GET_MAXBAUDRATE_T rUARTCtrlGetMaxBaudrate;\
+ UART_CTRL_GET_FC_T rUARTCtrlGetFC;\
+ UART_CTRL_NEED_TX_DONE_CB_T rUARTCtrlNeedTxDoneCb; /*new*/\
+ UART_CTRL_GET_DRV_STATE_T rUARTCtrlGetDrvState; /*new*/\
+ UART_CTRL_ASSIGN_RX_IOR_T rUARTCtrlAssignRxIor; /*new*/ \
+ UART_CTRL_PUT_BYTES_IOR_T rUARTCtrlPUTBYTESIOR; /*new*/ \
+ UART_CTRL_GET_CHUNK_SIZE_T rUARTCtrlGETCHUNKSIZE; /*new*/\
+ UART_CTRL_GET_MTU_SIZE_T rUARTCtrlGETMTUSIZE; /*new*/\
+ UART_CTRL_SET_INDICATION_T rUARTCtrlSETINDICATION; /*new*/\
+ TTY_CTRL_EXCP_TX_GPD_T rTTYCtrlExcpTxGPD; /*new*/\
+ TTY_CTRL_EXCP_TX_DONE_INFO_T rTTYCtrlExcpTxDoneInfo; /*new*/\
+ TTY_CTRL_EXCP_HIF_STATE_T rTTYCtrlExcpHifState; /*new*/\
+ TTY_CTRL_EXCP_ASSIGN_RX_GPD_T rTTYCtrlExcpAssignRxGPD; /*new*/\
+ TTY_CTRL_EXCP_GET_RX_GPD_T rTTYCtrlExcpGetRxGPD; /*new*/\
+ TTY_CTRL_EXCP_FLUSH_TX_T rTTYCtrlExcpFlushTx; /*new*/\
+ TTY_CTRL_EXCP_FLUSH_RX_T rTTYCtrlExcpFlushRx; /*new*/\
+ TTY_CTRL_EXCP_HIF_POLL_T rTTYCtrlExcpHifPoll; /*new*/
+
+#endif
+#endif
+
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_UART_H_PROTOTYPE__
+#define __DCL_UART_H_PROTOTYPE__
+
+typedef DCL_STATUS(*SeriPort_HANLDER_CB)(DCL_DEV dev, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+typedef struct
+{
+ SIO_TYPE_T DevType;
+ SeriPort_HANLDER_CB SeriportHandlerCb;
+}Seriport_HANDLER_T;
+
+/*!
+ * @brief TTY flag
+ */
+typedef enum _tty_flag {
+ /*!
+ * @brief use new TTY Tx path
+ */
+ TTY_FLAG_NEW_TX = (1 << 0),
+ /*!
+ * @brief use new TTY Rx path
+ */
+ TTY_FLAG_NEW_RX = (1 << 1),
+} tty_flag_e;
+
+typedef DCL_STATUS(*tty_txdone_cb)(DCL_HANDLE handle, module_type source_id, tty_io_request_t *tx_ior);
+typedef DCL_STATUS(*tty_rx_cb)(DCL_HANDLE handle, module_type source_id, tty_io_request_t *rx_ior);
+typedef DCL_STATUS(*tty_drv_state_change_cb)(DCL_HANDLE handle, tty_drv_state_e state);
+
+
+
+/*!
+* @function DclSerialPort_Open
+* @brief This function is to open the UART module and get a handle.
+* @param dev Port number. it can take DCL_UART_DEV as reference
+* @param flags module_type | FLAGS_UART_USE_VFIFO
+* module_type: KAL module type enum value
+* FLAGS_UART_USE_VFIFO: flags that specifies to use Virtual FIFO or not for UART device. Note that it's only valide for eDev with DCL_UART1, DCL_UART2, DCL_UART3(if exists)
+* [Note] Currently TTY doesn't handle flags!! This parameter is kept for backward compatible.
+* @result STATUS_FAIL Open failed.
+* @result STATUS_ALREADY_OPENED This device has already been opened.
+* @result STATUS_INVALID_DEVICE The device is not valid.
+* @result STATUS_SET_VFIFO_FAIL Fail to use Vitual FIFO for the UART port.
+* @result other value a valid handle
+*
+*/
+extern DCL_HANDLE DclSerialPort_Open(DCL_DEV dev, DCL_FLAGS flags);
+
+/*!
+* @function DclSerialPort_Configure
+* @brief This function is to configure for the UART module. [Note] Currenlty this function is not used.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param configure a ponter to UART_CONFIG_T structure which is a member of union DCL_CONFIGURE_T
+* @result STATUS_OK successfully configure.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_NOT_OPENED The module has not been opened.
+* @result STATUS_INVALID_CONFIGURATION the configuration is not valid.
+*/
+extern DCL_STATUS DclSerialPort_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+
+/*!
+* @function DclSerialPort_Control
+* @brief This function is support UART module commands. It is called to send command to control the UART module.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param cmd dcl uart commands
+* @param data pointer to the corresponding data structure of command
+* @result STATUS_OK command is executed successfully.
+* @result STATUS_INVALID_CMD It's a invalid command.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+*/
+extern DCL_STATUS DclSerialPort_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+
+/*!
+* @function DclSerialPort_Close
+* @brief This function is to close the UART module.
+* @param handle hanlde previous got from DclSerialPort_Open()
+* @result STATUS_OK Successfully close the UART module.
+* @result STATUS_INVALID_HANDLE It's invalid handle.
+* @result STATUS_NOT_OPENED The UART module hasn't been opened yet.
+*/
+extern DCL_STATUS DclSerialPort_Close(DCL_HANDLE handle);
+
+/* ---------------------------------------- General --------------------------------------------- */
+/*!
+* @function DclSerialPort_Initialize
+* @brief This function is to initialize TTY module..
+* @param none
+* @result STATUS_OK successfully initialize TTY module.
+* @result STATUS_FAIL initialized failed..
+*/
+extern DCL_STATUS DclSerialPort_Initialize(void);
+
+/* ----------------------------------- Export to upper layer --------------------------------------- */
+/*!
+* @function [New TTY API] DclSerialPort_UpModuleInit
+* @brief This function is to initialize/start designated COM Port for upper module.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param module_id upper module id
+* @param flag TTY COM Port attribute. Currently they are TTY_FLAG_NEW_TX or TTY_FLAG_NEW_RX.
+* Upper module can initialize flag with new Tx/Rx flow (gpd based) or conventional Tx/Rx (buffer/length based) flow.
+* ex. New Tx and Conventional Rx - DclSerialPort_UpModuleReinit(handle, module_id, TTY_FLAG_NEW_TX);
+* @result STATUS_OK Init COM Port device successfully.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_ALREADY_OPENED The COM Port has been initialized by other module.
+* @result STATUS_DEVICE_NOT_EXIST The corresponding device driver of COM Port has not been initialized.
+*/
+extern DCL_STATUS DclSerialPort_UpModuleInit(DCL_HANDLE handle, module_type module_id, int flag);
+
+/*!
+* @function [New TTY API] DclSerialPort_UpModuleReinit
+* @brief This function is to re-init TTY COM Port setting. This function is called when owner is changed.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param module_id upper module id
+* @param flag TTY COM Port attribute. Currently they are TTY_FLAG_NEW_TX or TTY_FLAG_NEW_RX.
+* Upper module can re-init flag with new Tx/Rx flow (gpd based) or conventional Tx/Rx (buffer/length based) flow.
+* ex. Reinit to New Tx and Conventional Rx - DclSerialPort_UpModuleReinit(handle, module_id, TTY_FLAG_NEW_TX);
+* @result STATUS_OK Re-Init COM Port device successfully.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_NOT_OPENED The COM Port has not been initialized.
+* @result STATUS_DEVICE_NOT_EXIST The corresponding device driver of COM Port has not been initialized.
+*/
+extern DCL_STATUS DclSerialPort_UpModuleReinit(DCL_HANDLE handle, module_type module_id, int flag);
+
+/*!
+* @function [New TTY API] DclSerialPort_UpModuleDeinit
+* @brief This function is to de-init/de-register COM Port.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @result STATUS_OK Deinit COM Port device successfully.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_NOT_OPENED The COM Port has not been initialized.
+* @result STATUS_DEVICE_NOT_EXIST The corresponding device driver of COM Port has not been initialized.
+*/
+extern DCL_STATUS DclSerialPort_UpModuleDeinit(DCL_HANDLE handle);
+
+/*!
+* @function [New TTY API] DclSerialPort_UpModuleRegisterCb
+* @brief This function is for upper layer module to register callback function.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param rx_cb rx callback function, driver send receiving data to upper layer through this rx callback function
+* @param tx_done_cb tx done callback function, this callback function will be called when data has been sent
+* @param drv_state_change_cb driver state change callback function, it notify the upper layer module when driver state is changed, ex. USB disconnect
+* @result STATUS_OK Register callback function successfully.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_NOT_OPENED The COM Port has not been initialized.
+* @result STATUS_DEVICE_NOT_EXIST The corresponding device driver of COM Port has not been initialized.
+* @result STATUS_FAIL Failed for other reasons.
+*/
+extern DCL_STATUS DclSerialPort_UpModuleRegisterCb(DCL_HANDLE handle, tty_rx_cb rx_cb, tty_txdone_cb tx_done_cb, tty_drv_state_change_cb drv_state_change_cb);
+
+/*!
+* @function [New TTY API] DclSerialPort_UpModuleTransmit
+* @brief This function is to transmit data to COM Port in ior format.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param ior pointer to tx io request which is sent to COM Port driver
+* @result STATUS_OK Transmit ior successfully.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_FAIL Failed for other reasons.
+*/
+extern DCL_STATUS DclSerialPort_UpModuleTransmit(DCL_HANDLE handle, tty_io_request_t *ior);
+
+/*!
+* @function [New TTY API] DclSerialPort_UpModuleTransmitLight
+* @brief This function is to transmit data to COM Port in ior format and light-weight.
+* Before user use this Tx function, it must calculate tx checksum and flush GPD in advance.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param ior pointer to tx io request which is sent to COM Port driver
+* @result STATUS_OK Transmit ior successfully.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_FAIL Failed for other reasons.
+*/
+extern DCL_STATUS DclSerialPort_UpModuleTransmitLight(DCL_HANDLE handle, tty_io_request_t *ior);
+
+/*!
+* @function [New TTY API] DclSerialPort_UpModuleAssignRxIor
+* @brief This function is to assign empty Rx ior to driver for data receiving.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param rx_ior pointer to rx io request for data receiving
+* @result STATUS_OK Assign Rx ior successfully.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_FAIL Failed for other reasons.
+*/
+extern DCL_STATUS DclSerialPort_UpModuleAssignRxIor(DCL_HANDLE handle, tty_io_request_t *rx_ior);
+
+/* ------------------------------------ Export to driver ------------------------------------------- */
+/*!
+* @function DclSerialPort_DrvRegisterCb
+* @brief This function is to register callback funtion for the UART module or COM Port class driver.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param seriport_handler the structure contains callback function and device type.
+ TTY would send commands (SIO/UART/USB/TTY/...) to driver through this callback function when the corresponding event happens.
+* @result STATUS_OK successful.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_ALREADY_OPENED This device has already been opened.
+* @result STATUS_INVALID_ARGUMENT The parameter is invalid, ex. uart_handler_cb is NULL.
+*/
+extern DCL_STATUS DclSerialPort_DrvRegisterCb(DCL_HANDLE handle, Seriport_HANDLER_T* seriport_handler);
+
+/*!
+* @function DclSerialPort_DrvDeRegisterCb
+* @brief This function is to De-register callback funtion for the UART module or COM Port class driver.
+* @param handle a valid handle return by DclSerialPort_Open()
+*
+* @result STATUS_OK successful.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_INVALID_OPERATION This device has already been de-registered or driver state is attached.
+*/
+extern DCL_STATUS DclSerialPort_DrvDeRegisterCb(DCL_HANDLE handle);
+
+/*!
+* @function [New TTY API] DclSerialPort_DrvAttach
+* @brief This function is for driver to inform TTY that the device is attached/connected.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @result STATUS_OK successful.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_DEVICE_NOT_EXIST The corresponding device driver of COM Port has not been initialized.
+*/
+extern DCL_STATUS DclSerialPort_DrvAttach(DCL_HANDLE handle);
+
+/*!
+* @function [New TTY API] DclSerialPort_DrvDetach
+* @brief This function is for driver to inform TTY that the device is detached/disconnected.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @result STATUS_OK successful.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_DEVICE_NOT_EXIST The corresponding device driver of COM Port has not been initialized.
+*/
+extern DCL_STATUS DclSerialPort_DrvDetach(DCL_HANDLE handle);
+
+/*!
+* @function [New TTY API] DclSerialPort_DrvRx
+* @brief This function is for driver to send back the received data to TTY/upper layer.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param source_id driver module id
+* @param rx_ior received data with ior format
+* @result STATUS_OK successfully register the callback function.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_NOT_OPENED The COM Port is not opened by upper layer.
+*/
+extern DCL_STATUS DclSerialPort_DrvRx(DCL_HANDLE handle, module_type source_id, void *rx_ior);
+
+/*!
+* @function [New TTY API] DclSerialPort_DrvTxDone
+* @brief This function is for driver to send back the transmitted (tx done) data to TTY/upper layer.
+* This function is called if "need tx done callback" is configured YES.
+* @param handle a valid handle return by DclSerialPort_Open()
+* @param source_id driver module id
+* @param tx_ior transmitted data with ior format
+* @result STATUS_OK successful.
+* @result STATUS_INVALID_HANDLE It's a invalid handle.
+* @result STATUS_NOT_OPENED The COM Port is not opened by upper layer.
+*/
+extern DCL_STATUS DclSerialPort_DrvTxDone(DCL_HANDLE handle, module_type source_id, void *tx_ior);
+
+
+#endif // #ifndef __DCL_UART_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
+
diff --git a/mcu/interface/driver/peripheral/dcl_wdt.h b/mcu/interface/driver/peripheral/dcl_wdt.h
new file mode 100644
index 0000000..aa86503
--- /dev/null
+++ b/mcu/interface/driver/peripheral/dcl_wdt.h
@@ -0,0 +1,390 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2001
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * dcl_wdt.h
+ *
+ * Project:
+ * --------
+ * Maui
+ *
+ * Description:
+ * ------------
+ * Header file of DCL (Driver Common Layer) for WDT.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifdef DCL_DEFINITION_STRUCT
+#ifndef __DCL_WDT_H_STRUCT__
+#define __DCL_WDT_H_STRUCT__
+
+
+#define DCL_WDT_RSTINTERVAL_VALUE 0xffa
+
+/*******************************************************************************
+ * DCL_OPTIONS for WDT
+ *******************************************************************************/
+#define WDT_OPTIONS
+
+ /*******************************************************************************
+ * DCL_CONFIGURE_T for WDT
+ *******************************************************************************/
+
+#define WDT_CONFIGS
+
+/*******************************************************************************
+ * DCL_EVENT for WDT
+ *******************************************************************************/
+#ifdef __BUILD_DOM__
+/*The WDT EVENT is part of DCL_EVENT_T Enum of dcl.h*/
+/*WDT_EVENTS_T Define the event type that wdt support to register a callback function*/
+typedef enum
+{
+ EVENT_WDT_TIMEOUT = 0x00000001
+}DCL_EVENT_T;
+#else
+#define WDT_EVENTS \
+ EVENT_WDT_TIMEOUT = 0x00000001,
+#endif
+/*******************************************************************************
+ * DCL_CTRL_CMD for WDT
+ *******************************************************************************/
+#ifdef __BUILD_DOM__
+/*The WDT Command values is part of DCL_CTRL_CMD_T Enum of dcl.h*/
+/*DCL_CTRL_DATA_T Define the Control data structure for each module's command*/
+typedef enum
+{
+ WDT_CMD_ENABLE , /*to enable/disable WDT*/
+ WDT_CMD_SET_EXT_POL, /*to set ploarity of external pin when WDT expired */
+ WDT_CMD_SET_EXT_RESET, /*to generate an external watchdog reset signal when WDT expired*/
+ WDT_CMD_SET_VALUE, /*to set WDT count value*/
+ WDT_CMD_RESTART, /*to restart counter*/
+ WDT_CMD_DRV_RESET, /*to reset device*/
+ WDT_CMD_ABN_RESET, /*to reset device with abnormal flag set to indicate it is a abnormal reset*/
+ WDT_CMD_IRQ, /*to generate interrupt instead of resetting device*/
+ WDT_CMD_IRQ_AUX,
+ WDT_CMD_GET_RSTINTERVAL,
+ WDT_CMD_GET_RSTINTERVAL_AUX,
+ WDT_CMD_ENABLE_DEBUG,
+ WDT_CMD_CLR_CHECK,
+ WDT_CMD_SET_CHECK,
+ WDT_CMD_CLR_KICK,
+ WDT_CMD_SET_KICK,
+}DCL_CTRL_CMD_T;
+#else
+#define WDT_CMDS \
+ WDT_CMD_ENABLE , \
+ WDT_CMD_SET_EXT_POL, \
+ WDT_CMD_SET_EXT_RESET, \
+ WDT_CMD_SET_VALUE, \
+ WDT_CMD_RESTART, \
+ WDT_CMD_DRV_RESET, \
+ WDT_CMD_ABN_RESET, \
+ WDT_CMD_IRQ, \
+ WDT_CMD_IRQ_AUX, \
+ WDT_CMD_GET_RSTINTERVAL, \
+ WDT_CMD_GET_RSTINTERVAL_AUX, \
+ WDT_CMD_ENABLE_DEBUG, \
+ WDT_CMD_CLR_CHECK, \
+ WDT_CMD_SET_CHECK, \
+ WDT_CMD_CLR_KICK, \
+ WDT_CMD_SET_KICK,
+#endif
+/*******************************************************************************
+ * DCL_CTRL_DATA_T: Define the Control data structure for each module's command
+ *******************************************************************************/
+ typedef struct
+ {
+ DCL_UINT32 rstInterval;
+ }WDT_CTRL_GET_RSTINTERVAL_T;
+
+/* For WDT_CMD_ENABLE command. */
+typedef struct
+{
+ DCL_BOOL fgEnable; // TRUE: Enable WDT, FALSE: Disable WDT
+} WDT_CTRL_ENABLE_T;
+/* For WDT_CMD_SET_EXT_POL command. */
+typedef struct
+{
+ DCL_BOOL fgIOHigh; // TRUE: IO high, FALSE: IO low
+} WDT_CTRL_SET_EXT_POL_T;
+/* For WDT_CMD_SET_EXT_RESET command. */
+typedef struct
+{
+ DCL_BOOL fgEnable; // TRUE: Generate reset signal, FALSE: Do NOT generate reset signal
+} WDT_CTRL_SET_EXT_RESET_T;
+/* For WDT_CMD_SET_VALUE command. */
+typedef struct
+{
+ DCL_UINT16 u2Value; // Set WDT count down value, the unit is 15.6ms
+} WDT_CTRL_SET_VALUE_T;
+/* For WDT_CMD_RESTART command. */
+// WDT_CMD_RESTART does NOT need parameters
+/* For WDT_CMD_DRV_RESET command. */
+// WDT_CMD_DRV_RESET does NOT need parameters
+/* For WDT_CMD_ABN_RESET command. */
+// WDT_CMD_ABN_RESET does NOT need parameters
+/* For WDT_CMD_IRQ command. */
+typedef struct
+{
+ DCL_BOOL fgEnable; // TRUE: Enable interrupt instread of generating reset, FALSE: Do NOT enable interrupt
+} WDT_CTRL_IRQ_T;
+/*For WDT_CMD_ENABLE_DEBUG command*/
+typedef struct
+{
+ DCL_BOOL fgEnable; //enable or disable debug
+}WDT_CTRL_DEBUG_T;
+
+#ifdef __BUILD_DOM__
+/*The GPIO command prarmeter data structure for each command. that's enum in in DCL_CTRL_DATA_T*/
+typedef struct
+{
+ WDT_CTRL_ENABLE_T rWDTEnable; /*data structure for WDT_CMD_ENABLE control command */
+ WDT_CTRL_SET_EXT_POL_T rWDTSetExtPol; /*data structure for WDT_CMD_SET_EXT_POL control command */
+ WDT_CTRL_SET_EXT_RESET_T rWDTSetExtReset; /*data structure for WDT_CMD_SET_EXT_RESET control command */
+ WDT_CTRL_SET_VALUE_T rWDTSetValue; /*data structure for WDT_CMD_SET_VALUE control command */
+ WDT_CTRL_IRQ_T rWDTIRQ; /*data structure for WDT_CMD_IRQ control command */
+ WDT_CTRL_DEBUG_T rWDTDebug; /*data structure for WDT_CMD_ENABLE_DEBUG control command */
+}DCL_CTRL_DATA_T;
+#else
+#define WDT_CTRLS \
+ WDT_CTRL_ENABLE_T rWDTEnable; \
+ WDT_CTRL_SET_EXT_POL_T rWDTSetExtPol; \
+ WDT_CTRL_SET_EXT_RESET_T rWDTSetExtReset; \
+ WDT_CTRL_SET_VALUE_T rWDTSetValue; \
+ WDT_CTRL_IRQ_T rWDTIRQ; \
+ WDT_CTRL_DEBUG_T rWDTDebug; \
+ WDT_CTRL_GET_RSTINTERVAL_T rRstValue;
+#endif
+
+#endif // #ifndef __DCL_I2C_H_STRUCT__
+#endif // #ifdef DCL_DEFINITION_STRUCT
+
+
+#ifdef DCL_DEFINITION_PROTOTYPE
+#ifndef __DCL_WDT_H_PROTOTYPE__
+#define __DCL_WDT_H_PROTOTYPE__
+
+/*************************************************************************
+* FUNCTION
+* DclWDT_Initialize
+*
+* DESCRIPTION
+* This function is to initialize WDT module
+*
+* PARAMETERS
+* None
+*
+* RETURN VALUES
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclWDT_Initialize(void);
+/*************************************************************************
+* FUNCTION
+* DclWDT_Open
+*
+* DESCRIPTION
+* This function is to open the WDT module and return a handle
+*
+* PARAMETERS
+* dev: only valid for DCL_WDT
+* flags: no sepcial flags is needed. Please use FLAGS_NONE
+*
+* RETURN VALUES
+* DCL_HANDLE_INVALID: Open failed.
+* other value: a valid handle
+*
+*************************************************************************/
+extern DCL_HANDLE DclWDT_Open(DCL_DEV dev, DCL_FLAGS flags);
+/*************************************************************************
+* FUNCTION
+* DclWDT_ReadData
+*
+* DESCRIPTION
+* This function is not supported for the WDT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURN VALUES
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclWDT_ReadData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclWDT_WriteData
+*
+* DESCRIPTION
+* This function is not supported for the WDT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURN VALUES
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclWDT_WriteData(DCL_HANDLE handle, DCL_BUFF *buff, DCL_BUFF_LEN buf_len, DCL_OPTIONS options);
+/*************************************************************************
+* FUNCTION
+* DclWDT_Configure
+*
+* DESCRIPTION
+* This function is not supported for the WDT module now.
+*
+* PARAMETERS
+* N/A
+*
+* RETURN VALUES
+* STATUS_UNSUPPORTED
+*
+*************************************************************************/
+extern DCL_STATUS DclWDT_Configure(DCL_HANDLE handle, DCL_CONFIGURE_T *configure);
+/*************************************************************************
+* FUNCTION
+* DclWDT_RegisterCallback
+*
+* DESCRIPTION
+* This function is to set callback function for the WDT module.
+*
+* PARAMETERS
+* handle: the returned handle value of DclWDT_Open
+* event: Supported events:
+* EVENT_WDT_TIMEOUT: Watch dog time out interrupt
+* callback: the callback function for registered events
+*
+* RETURN VALUES
+* STATUS_OK: Successfully register the callback function.
+* STATUS_INVALID_DCL_HANDLE: It's a invalid handle.
+* STATUS_NOT_OPENED: The module has not been opened.
+* STATUS_INVALID_EVENT: The event parameter is invalid.
+*
+*************************************************************************/
+extern DCL_STATUS DclWDT_RegisterCallback(DCL_HANDLE handle, DCL_EVENT event, PFN_DCL_CALLBACK callback);
+/*************************************************************************
+* FUNCTION
+* DclWDT_Control
+*
+* DESCRIPTION
+* This function is to send command to control the WDT module.
+*
+* PARAMETERS
+* handle: The handle value returned from DclWDT_Open
+* cmd: a control command for WDT module
+* 1. WDT_CMD_ENABLE: to enable/disable WDT
+* 2. WDT_CMD_SET_EXT_POL: to set ploarity of external pin when WDT expired
+* 3. WDT_CMD_SET_EXT_RESET: to generate an external watchdog reset signal when WDT expired
+* 4. WDT_CMD_SET_VALUE: to set WDT count value
+* 5 WDT_CMD_RESTART: to restart counter
+* 6. WDT_CMD_DRV_RESET: to reset device
+* 7. WDT_CMD_ABN_RESET: to reset device with abnormal flag set to indicate it is a abnormal reset
+* 8. WDT_CMD_IRQ: to generate interrupt instead of reseting device
+* data: The data of the control command
+* 1. WDT_CMD_ENABLE: pointer to a WDT_CTRL_ENABLE_T structure
+* 2. WDT_CMD_SET_EXT_POL: pointer to a WDT_CTRL_SET_EXT_POL_T structure
+* 3. WDT_CMD_SET_EXT_RESET: pointer to a WDT_CTRL_SET_EXT_RESET_T structure
+* 4. WDT_CMD_SET_VALUE: pointer to a WDT_CTRL_SET_VALUE_T structure
+* 5 WDT_CMD_RESTART: A null pointer
+* 6. WDT_CMD_DRV_RESET: A null pointer
+* 7. WDT_CMD_ABN_RESET: A null pointer
+* 8. WDT_CMD_IRQ: pointer to a WDT_CTRL_IRQ_T structure
+*
+* RETURN VALUES
+* STATUS_OK: command is executed successfully.
+* STATUS_FAIL: command is failed.
+* STATUS_INVALID_CMD: It's a invalid command.
+*
+*************************************************************************/
+extern DCL_STATUS DclWDT_Control(DCL_HANDLE handle, DCL_CTRL_CMD cmd, DCL_CTRL_DATA_T *data);
+/*************************************************************************
+* FUNCTION
+* DclWDT_Close
+*
+* DESCRIPTION
+* This function is to close the WDT module.
+*
+* PARAMETERS
+* handle: the returned handle value of DclWDT_Open
+*
+* RETURNS
+* STATUS_OK
+*
+*************************************************************************/
+extern DCL_STATUS DclWDT_Close(DCL_HANDLE handle);
+
+
+#endif // #ifndef __DCL_WDT_H_PROTOTYPE__
+#endif // #ifdef DCL_DEFINITION_PROTOTYPE
+
+
+
+
+
+
diff --git a/mcu/interface/driver/peripheral/drv_comm.h b/mcu/interface/driver/peripheral/drv_comm.h
new file mode 100644
index 0000000..8e319b1
--- /dev/null
+++ b/mcu/interface/driver/peripheral/drv_comm.h
@@ -0,0 +1,1124 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * drv_comm.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for driver common interface.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by ClearCase. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * $Log$
+ *
+ * 07 17 2019 wei-de.chen
+ * [MOLY00422800] [Build Error][MERCURY] Add Mercury related definition
+ * Add definition of MERCURY and MT6297P to solve build error on MERCURY.DEV
+ *
+ * 05 02 2019 wei-de.chen
+ * [MOLY00396869] [MODIS HW Copro] Work on making Modis to run with ESL HW models and Uplane with ESL
+ * Merge code of ESL_MASE_GEN97 according to MUK/WCS/CTD/MTA4 Ireneusz Zie's request
+ *
+ * 06 20 2018 steven-yx.hu
+ * [MOLY00333775][UMOLYE] 95 xL1Sim build warning fix.
+ *
+ * 03 14 2018 wei-de.chen
+ * [MOLY00309244] [6297] Add MT6297 related definition
+ * Add MT6297 related definition
+ *
+ * 02 22 2018 wei-de.chen
+ * [MOLY00309244] [6297] Add MT6297 related definition
+ *
+ * Add MT6297 related definition
+ *
+ * 02 22 2018 wei-de.chen
+ * [MOLY00309244] [6297] Add MT6297 related definition
+ * Add MT6297 related definition
+ *
+ * 12 15 2017 wei-de.chen
+ * [MOLY00296581] [Gen95] add MT3967 related definition
+ * Add MT3967 related definition
+ *
+ * 12 15 2017 wei-de.chen
+ * [MOLY00296581] [Gen95] add MT3967 related definition
+ * Add MT3967 related definition
+ *
+ * 10 30 2017 wei-de.chen
+ * [MOLY00286038] [MT6765] Add definition of MT6765
+ * Add MT6765 (Cervino) Definition
+ *
+ * 08 24 2017 wei-de.chen
+ * [MOLY00273493] [UMOLYA] Add definition of MT6771
+ * Add MT6771 (Sylvia) Definition
+ *
+ * 06 08 2017 wei-de.chen
+ * [MOLY00243802] [MT6739] Add definition of MT6739
+ * Add MT6739 related definition
+ *
+ * 05 26 2017 wei-de.chen
+ * [MOLY00253086] [Need Patch](LTE domain) UMOLYA build error for MT6295M_FPGA(L1S_L1DISABLE)
+ * Add MT6295M definition
+ *
+ * 04 20 2017 wei-de.chen
+ * [MOLY00243706] [MT6295M] Add MT6295M related definition
+ * Add MT6295 related definition
+ *
+ * 06 16 2016 wei-de.chen
+ * [MOLY00184725] UMOLYA ESL/MASE porting
+ * add __ESL_MASE__ definition due to ESL load
+ * Request by SSE_SS3 Chin-Chieh Hung
+ *
+ * 03 29 2016 wei-de.chen
+ * [MOLY00171664] [UMOLYA] Add definition of MT6763
+ * Add definition of MT6763
+ *
+ * 01 06 2016 wei-de.chen
+ * [MOLY00156132] [ELBRUS] Add ESL definition to DRV_WriteReg32_NPW_RB
+ * Add ESL definition to DRV_WriteReg32_NPW_RB for fake HW in ESL
+ *
+ * 12 09 2015 wei-de.chen
+ * [MOLY00151011] [6292] Modify NPW_write API to fit new CPU & bus architecture
+ * Modify NPW_write API of Elbrus to fit new CPU & bus architecture
+ *
+ * 11 30 2015 wei-de.chen
+ * [MOLY00151011] [6292] Modify NPW_write API to fit new CPU & bus architecture
+ * Modify NPW_write API of Elbrus to fit new CPU & bus architecture
+ *
+ * 09 22 2015 wei-de.chen
+ * [MOLY00137134] [UMOLY] Add driver feature files for Elbrus
+ * Temp add ELBRUS definition for NPW related function for bring-up (still need optimize in future)
+ *
+ * 06 23 2015 wei-de.chen
+ * [MOLY00122918] [MT6755][BRINGUP_FIRSTCALL][SS]
+ * Add MT6755 & MT6797 definition on drv_comm.h
+ *
+ * 02 06 2015 wei-de.chen
+ * [MOLY00094939] MASE UMOLY check in
+ * Merge 3G MASE change to UMOLY trunk due to JL Hsiao's request
+ *
+ * 10 01 2014 wei-de.chen
+ * [MOLY00080141] Change macro of DRV_WriteReg32_NPW_RB of TK6291
+ * Change macro of DRV_WriteReg32_NPW_RB by TK6291 due to memory map of TK6291
+ * u1rwduu`whqnvpghlqg|r`l(a`+fm`k
+ *
+ * 12 11 2013 chin-chieh.hung
+ * [MOLY00045704] Init MT6595 common driver
+ * update NPW Driver API for MT6595
+ *
+ * 12 10 2012 po.hu
+ * [MOLY00007257] [Modis] Modis????JMinGW?@?compier?H??linux build
+ * .
+ *
+ * 11 30 2012 ansel.liao
+ * [MOLY00006575] Add UART/HDMA Driver
+ * add dbg_flush and corresponding drvtest
+ *
+ * 11 02 2012 chin-chieh.hung
+ * [MOLY00005322] TATAKA merge to MOLY
+ * Integration change(non-devdrv/non-sys_drv driver part-2)
+ *
+ * 06 11 2012 jy.lan
+ * removed!
+ * .
+ *
+ * 05 24 2012 wcpuser_integrator
+ * removed!
+ * Qinghua Yu check in global enum (MSG & SAP) at modem_dev.
+ *
+ * 05 24 2012 wcpuser_integrator
+ * removed!
+ * Qinghua Yu check in global enum (MSG & SAP) at modem_dev.
+ *
+ * 05 24 2012 wcpuser_integrator
+ * removed!
+ * Qinghua Yu check in global enum (MSG & SAP) at modem_dev.
+ *
+ * 03 15 2012 argus.lin
+ * removed!
+ * fix build error
+ *
+ * 03 15 2012 argus.lin
+ * removed!
+ * fix build error
+ *
+ * 11 11 2011 jy.lan
+ * removed!
+ * .
+ *
+ * 02 16 2011 guoxin.hong
+ * removed!
+ * .
+ *
+ * 12 23 2010 anderson.tsai
+ * removed!
+ * .
+ *
+ * 12 16 2010 simon.shih
+ * removed!
+ * .
+ *
+ * 11 25 2010 simon.shih
+ * removed!
+ * .
+ *
+ * 10 18 2010 simon.shih
+ * removed!
+ * .
+ *
+ * 09 24 2010 simon.shih
+ * removed!
+ * .
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
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+ *
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+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ * add NFI bus mutex
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
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+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * removed!
+ * removed!
+ *
+ *
+ * Rev 1.24 Jul 11 2005 17:41:48 mtk00288
+ * add DEVICE_ID
+ * Resolution for 11921: [LPWR][Add feature]Add LPWR module
+ *
+ * Rev 1.23 20 Jun 2005 20:00:32 mtk00502
+ * add MT6226/MT6227 compile option
+ * Resolution for 11617: [DRV][New Feature]Add MT6226/M6227 compile option
+ *
+ * Rev 1.22 May 17 2005 00:29:10 BM_Trunk
+ * Karlos:
+ * add copyright and disclaimer statement
+ *
+ * Rev 1.21 Mar 19 2005 14:49:34 mtk00502
+ * add 6228 compile option
+ * Resolution for 10304: [Drirver][New Fearture]Support MT6228
+ *
+ * Rev 1.20 Jan 18 2005 00:34:22 BM
+ * append new line in W05.04
+ *
+ * Rev 1.19 Dec 10 2004 12:12:18 mtk00479
+ * Add parentheses for the parameters of macro ()
+ * Resolution for 9089: [Drv][Optimization]Add parentheses for the parameters of macro
+ *
+ * Rev 1.18 Oct 12 2004 11:34:12 mtk00479
+ * Add compile option of MT6217
+ * Resolution for 8195: [Drv][NewFeature]Add compile option of MT6217
+ *
+ * Rev 1.17 May 13 2004 22:15:40 mtk00479
+ * Add for USB charging
+ * Resolution for 5419: [Drv][AddFeature]Add USB charging function
+ *
+ * Rev 1.16 Mar 25 2004 15:01:16 mtk00288
+ * Add driver timing debug functions.
+ * Resolution for 4496: [DRV][Add Feature]add driver timing debug functions
+ *
+ * Rev 1.15 Mar 12 2004 14:00:30 mtk00502
+ * define a macro to send msg
+ * Resolution for 4231: [BMT][New Feature]add a function to translate voltage to temperature
+ *
+ * Rev 1.14 Feb 27 2004 20:14:52 mtk00502
+ * add 6219 compilt option
+ * Resolution for 4005: [Driver][New Feature]add 6219 compile option
+ *
+ * Rev 1.13 Feb 19 2004 19:51:30 mtk00502
+ * to solve assert during RTC power on
+ * Resolution for 3956: [Driver][New feature]solve assert during RTC power on
+ *
+ * Rev 1.12 Feb 05 2004 18:57:28 mtk00288
+ * add DRV_COMM_REG2_USBMS_PWRON definition
+ * Resolution for 3839: [MMI USB DRV L4 UEM TST BMT] [New Feature] USB device integration
+ *
+ * Rev 1.11 Dec 25 2003 10:03:36 mtk00479
+ * Remove compile option of MT6205B for DRV_COMM_REG2_NORMAL_RESET and DRV_COMM_REG2_CHRPWRON.
+ * Resolution for 3588: [Drv][BugFix]Remove compile option of MT6205B for DRV_COMM_REG2_NORMAL_RESET and DRV_COMM_REG2_CHRPWRON.
+ *
+ * Rev 1.10 Oct 31 2003 15:27:24 mtk00502
+ * add 6218B compile option
+ * Resolution for 3233: [Driver][New Feature] Add 6218B compile option
+ *
+ * Rev 1.8 Oct 02 2003 21:01:26 mtk00288
+ * add the power on cause bit in DRV_COMM_REG2 register
+ * Resolution for 3045: [DRV][Bugfix]Adjust the priority of power on cause
+ *
+ * Rev 1.7 Jun 18 2003 22:37:28 mtk00288
+ * Driver customize
+ * Resolution for 2052: [DRV][Customize]Driver customize for different requirements
+ *
+ * Rev 1.6 Jun 12 2003 16:10:22 mtk00288
+ * add MT6218 definitions
+ * Resolution for 1952: [Drivers][add Feature]MT6218 Peripherals driver
+ *
+ * Rev 1.5 Apr 16 2003 21:43:24 mtk00288
+ * add "()" in DRV_Reg&DRV_WriteReg macro
+ * Resolution for 1547: [Drivers][Add Feature]Add MT6205B drivers
+ *
+ * Rev 1.4 Feb 27 2003 16:41:48 mtk00288
+ * add a macro(DRV_BuildPrimitive) to send primitive for driver.
+ * Resolution for 1098: Add Accessory(AUX) Task to MAUI project
+ *
+ * Rev 1.3 Feb 21 2003 15:40:02 mtk00288
+ * extern dbg_print function, when DRV_DEBUG define
+ * Resolution for 1011: Create ADC scheduler
+ *
+ * Rev 1.2 Jan 23 2003 22:03:40 mtk00288
+ * remove unnecessary comments.
+ * Resolution for 491: BMT task and PMIC driver
+ *
+ * Rev 1.1 Dec 16 2002 11:38:28 mtk00288
+ * add kal_uint16 into DRV_WriteReg macro
+ * Resolution for 9: Read/Write Register access
+ *
+ * Rev 1.0 Nov 30 2002 19:49:58 admin
+ * Initial revision.
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by ClearCase. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+
+#ifndef __DRV_COMM_H__
+#define __DRV_COMM_H__
+
+#ifndef __CATEGORY_MODEM__
+#include "drv_features.h"
+#endif
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "md_drv_sap.h"
+#ifndef __CATEGORY_MODEM__
+#include "reg_base.h"
+#endif
+
+#include "kal_trace.h"
+#include "sync_data.h"
+
+#if defined(DRV_MISC_LOW_COST_PROJ)
+ #define __LOW_COST_PROJECT__
+#endif
+
+
+
+typedef enum {
+ io_low=0,
+ io_high
+} IO_level;
+
+
+
+typedef enum {
+ DEV_DMA=0,
+ DEV_USB,
+ DEV_GCU,
+ DEV_CHE,
+ DEV_PPP,
+ DEV_GPT,
+ DEV_KP,
+ DEV_GPIO,
+ DEV_UART1,
+ DEV_UART2,
+ DEV_UART3,
+ DEV_SIM,
+ DEV_PWM,
+ DEV_PWM2,
+ DEV_ALTER,
+ DEV_LCD,
+ DEV_MSDC,
+ DEV_TRC,
+ DEV_NFI,
+ DEV_B2SPI,
+ DEV_IRDA,
+ DEV_ADC,
+ DEV_RTC,
+ DEV_DIV,
+ DEV_FCS,
+ DEV_RZLB,
+ DEV_CRZ,
+ DEV_TV_OUT,
+ DEV_IPP,
+ DEV_PNG,
+ DEV_GIF,
+ DEV_GCMQ,
+ DEV_G2D,
+ DEV_MP4,
+ DEV_JPEG,
+ DEV_PRZ,
+ DEV_RESZ,
+ DEV_ISP,
+ DEV_DCT,
+ DEV_IMGDMA,
+ DEV_DRZ,
+ DEV_MSDC2,
+ DEV_SIM2,
+ DEV_ROTDMA,
+ DEV_CAM104M,
+ DEV_LCD104M,
+ DEV_MAX_ID,
+ DEV_NULL_ID = 0xfe
+} DEVICE_ID_ENUM;
+
+
+
+typedef void (* VOID_FUNC)(void);
+
+//#define __DRV_COMM_REG_DBG__
+#ifdef __DRV_COMM_REG_DBG__
+
+#define MAX_DRV_COMM_REG_DBG_INFO_SIZE 2048 /*must be 2^n*/
+
+typedef struct{
+ kal_uint8 write_flag;
+ kal_uint16 line_number;
+ kal_uint32 reg_addr;
+ kal_uint32 reg_value;
+ kal_uint32 time_log;
+}DRV_COMM_REG_DBG_DATA;
+
+typedef struct{
+ DRV_COMM_REG_DBG_DATA dbg_data[MAX_DRV_COMM_REG_DBG_INFO_SIZE];
+ kal_uint16 dbg_data_idx;
+}DRV_REG_DBG_STRUCT;
+
+#define DRV_DBG_WriteReg(addr,data) drv_reg_dbg_trace_write16(__LINE__, addr, data)
+
+#define DRV_DBG_Reg(addr) drv_reg_dbg_trace_read16(__LINE__, addr)
+
+#define DRV_DBG_WriteReg32(addr,data) drv_reg_dbg_trace_write32(__LINE__, addr, data)
+
+#define DRV_DBG_Reg32(addr) drv_reg_dbg_trace_read32(__LINE__, addr)
+
+#define DRV_DBG_WriteReg8(addr,data) drv_reg_dbg_trace_write8(__LINE__, addr, data)
+
+#define DRV_DBG_Reg8(addr) drv_reg_dbg_trace_read8(__LINE__, addr)
+
+#define DRV_DBG_ClearBits(addr,data) {\
+ kal_uint16 temp;\
+ temp = DRV_DBG_Reg(addr);\
+ temp &=~(data);\
+ DRV_DBG_WriteReg(addr,temp);\
+}
+
+#define DRV_DBG_SetBits(addr,data) {\
+ kal_uint16 temp;\
+ temp = DRV_DBG_Reg(addr);\
+ temp |= (data);\
+ DRV_DBG_WriteReg(addr,temp);\
+}
+
+#define DRV_DBG_SetData(addr, bitmask, value) {\
+ kal_uint16 temp;\
+ temp = (~(bitmask)) & DRV_DBG_Reg(addr);\
+ temp |= ((value) & (bitmask));\
+ DRV_DBG_WriteReg(addr,temp);\
+}
+
+#define DRV_DBG_ClearBits32(addr,data) {\
+ kal_uint32 temp;\
+ temp = DRV_DBG_Reg32(addr);\
+ temp &=~(data);\
+ DRV_DBG_WriteReg32(addr,temp);\
+}
+
+#define DRV_DBG_SetBits32(addr,data) {\
+ kal_uint32 temp;\
+ temp = DRV_DBG_Reg32(addr);\
+ temp |= (data);\
+ DRV_DBG_WriteReg32(addr,temp);\
+}
+
+#define DRV_DBG_SetData32(addr, bitmask, value) {\
+ kal_uint32 temp;\
+ temp = (~(bitmask)) & DRV_DBG_Reg32(addr);\
+ temp |= ((value) & (bitmask));\
+ DRV_DBG_WriteReg32(addr,temp);\
+}
+
+#define DRV_DBG_ClearBits8(addr,data) {\
+ kal_uint8 temp;\
+ temp = DRV_DBG_Reg8(addr);\
+ temp &=~(data);\
+ DRV_DBG_WriteReg8(addr,temp);\
+}
+
+#define DRV_DBG_SetBits8(addr,data) {\
+ kal_uint8 temp;\
+ temp = DRV_DBG_Reg8(addr);\
+ temp |= (data);\
+ DRV_DBG_WriteReg8(addr,temp);\
+}
+
+#define DRV_DBG_SetData8(addr, bitmask, value) {\
+ kal_uint8 temp;\
+ temp = (~(bitmask)) & DRV_DBG_Reg8(addr);\
+ temp |= ((value) & (bitmask));\
+ DRV_DBG_WriteReg8(addr,temp);\
+}
+
+extern void drv_reg_dbg_trace_write16(kal_uint16 line, kal_uint32 addr, kal_uint32 data);
+extern void drv_reg_dbg_trace_write32(kal_uint16 line, kal_uint32 addr, kal_uint32 data);
+extern void drv_reg_dbg_trace_write8(kal_uint16 line, kal_uint32 addr, kal_uint32 data);
+extern kal_uint16 drv_reg_dbg_trace_read16(kal_uint16 line, kal_uint32 addr);
+extern kal_uint32 drv_reg_dbg_trace_read32(kal_uint16 line, kal_uint32 addr);
+extern kal_uint32 drv_reg_dbg_trace_read8(kal_uint16 line, kal_uint32 addr);
+
+#endif //__DRV_COMM_REG_DBG__
+
+#if defined(__ESL_MASE_GEN97__) && !defined(__MTK_TARGET__)
+void write_register(unsigned regOfst, unsigned value);
+unsigned read_register (unsigned regOfst);
+#define DRV_WriteReg(addr,data) write_register(addr, data)
+#define DRV_WriteReg32(addr,data) write_register(addr, data)
+#define DRV_Reg32(addr) read_register(addr)
+#else /* __ESL_MASE_GEN97__ && !__MTK_TARGET__ */
+#define DRV_WriteReg(addr,data) ((*(volatile kal_uint16 *)(addr)) = (kal_uint16)(data))
+#define DRV_Reg(addr) (*(volatile kal_uint16 *)(addr))
+#define DRV_WriteReg32(addr,data) ((*(volatile kal_uint32 *)(addr)) = (kal_uint32)(data))
+#define DRV_Reg32(addr) (*(volatile kal_uint32 *)(addr))
+#define DRV_WriteReg8(addr,data) ((*(volatile kal_uint8 *)(addr)) = (kal_uint8)(data))
+#define DRV_Reg8(addr) (*(volatile kal_uint8 *)(addr))
+#endif /* else __ESL_MASE_GEN97__ && !__MTK_TARGET__ */
+
+#define DRV_SetReg8(addr, data) (DRV_WriteReg8(addr, DRV_Reg8(addr)|(data)))
+#define DRV_ClrReg8(addr, data) (DRV_WriteReg8(addr, DRV_Reg8(addr)&~(data)))
+#define DRV_SetReg(addr, data) (DRV_WriteReg(addr, DRV_Reg(addr)|(data)))
+#define DRV_ClrReg(addr, data) (DRV_WriteReg(addr, DRV_Reg(addr)&~(data)))
+#define DRV_SetReg32(addr, data) (DRV_WriteReg32(addr, DRV_Reg32(addr)|(data)))
+#define DRV_ClrReg32(addr, data) (DRV_WriteReg32(addr, DRV_Reg32(addr)&~(data)))
+
+
+
+/* DRV_WriteReg32_NPW, DRV_WriteReg32_NPW_RB provide non-post-write operation
+ Abbreviation:
+ NPW: Non Post Write
+ RB : Read Back
+ Description:
+ 1. DRV_WriteReg32_NPW: In System with strongly order memory attribute
+ (write response from target hardware IP), we just write the data
+ into the strongly order region (write_addr | 0xF000_0000)
+ 2. DRV_WriteReg32_NPW: In System without strongly order memory attribute,
+ we write the data into the write_addr and read the write_addr
+ back to avoid the write data is buffered in bus fabric
+ 3. DRV_WriteReg32_NPW_RB: In some hardware IP design, reading the
+ write_addr has some side-effects, in order to avoid this situation,
+ DRV_WriteReg32_NPW_RB is provided and the read_addr of
+ DRV_WriteReg32_NPW_RB is assigned by the user.
+ User must confirm that all previous write operations are finished
+ before the data of read_addr ready.
+ For example, write_addr in IP-A, read_addr in IP-B can't make sure the
+ IP-A write operation is finished. write_addr/read_addr must be in the
+ same IP.
+ 4. DRV_WriteReg32_NPW_RB: For system with strongly order memory
+ attribute, DRV_WriteReg32_NPW_RB does NOT read the read_addr
+ (the same behavior with DRV_WriteReg32_NPW).
+ 5. Memory barrier operations (DMB/DSB in ARM Arch.) are not included in
+ DRV_WriteReg32_NPW_RB and DRV_WriteReg32_NPW.
+ 6. (For 6292 MIPS CPU arch) Due to MIPS has no strongly order memory
+ attribute, we use non-bufferable bank write + MO_sync to reach
+ this feature.
+ -- MO_sync is a series of r/w access special address
+ through MO port. It has same effect as memory barrier of
+ other MO port access, but NO effect to other MM port access.
+ So strictly it is not conflict to description #5.
+ */
+
+#if defined(__ESL_COSIM_LTE__)
+ #define DRV_WriteReg32_NPW_RB(write_addr, data, read_addr) \
+ do { \
+ DRV_WriteReg32(write_addr, data); \
+ DRV_Reg32(read_addr); \
+ } while(0);
+
+ #define DRV_WriteReg32_NPW(write_addr, data) \
+ DRV_WriteReg32_NPW_RB(write_addr, data, write_addr)
+ #define DRV_SetReg32_NPW(write_addr, data) \
+ DRV_WriteReg32_NPW(((kal_uint32)(write_addr)), DRV_Reg32(write_addr) | (data))
+ #define DRV_ClrReg32_NPW(write_addr, data) \
+ DRV_WriteReg32_NPW(((kal_uint32)(write_addr)), DRV_Reg32(write_addr) & (~(data)))
+
+#elif defined(__MD93__) || defined(__MD95__) || defined(MT6297) || defined(__MD97__) || defined(__MD97P__)
+
+ #if defined(__ESL_ENABLE__)||defined(__ESL_MASE__)
+ #define ELBRUS_UKNOWN_BANK_ACCESS(write_addr, data) do { \
+ DRV_WriteReg32((write_addr), (data)); \
+ MO_Sync(); \
+ } while(0);
+ #else
+ #define ELBRUS_UKNOWN_BANK_ACCESS(write_addr, data) do { \
+ ASSERT(0); \
+ } while(0);
+ #endif
+
+#if defined(__ESL_MASE_GEN97__) && !defined(__MTK_TARGET__)
+ #define DRV_WriteReg32_NPW_RB(write_addr, data, read_addr) DRV_WriteReg32(write_addr, read_addr)
+#else /* __ESL_MASE_GEN97__ && !__MTK_TARGET__ */
+ #define DRV_WriteReg32_NPW_RB(write_addr, data, read_addr) \
+ do{ \
+ /* For non-bufferable HW BANK */ \
+ if( (((kal_uint32)write_addr)>>28)==0xA || (((kal_uint32)write_addr)>>28)==0xC || (((kal_uint32)write_addr)>>28)==0xE ) \
+ { \
+ DRV_WriteReg32((write_addr), (data)); \
+ MO_Sync(); \
+ } \
+ /* For MDHW bufferable access, change to MDHW non-bufferable BANK */ \
+ else if( (((kal_uint32)write_addr)>>28)==0xB ) \
+ { \
+ DRV_WriteReg32(((((kal_uint32)write_addr) << 4) >> 4)|0xA0000000, (data)); \
+ MO_Sync(); \
+ } \
+ /* For APHW bufferable access, change to APHW non-bufferable BANK */ \
+ else if( ((((kal_uint32)write_addr)>>28)==0xD) ) \
+ { \
+ DRV_WriteReg32(((((kal_uint32)write_addr) << 4) >> 4)|0xC0000000, (data)); \
+ MO_Sync(); \
+ } \
+ else \
+ { \
+ ELBRUS_UKNOWN_BANK_ACCESS(write_addr, data); \
+ } \
+ }while(0);
+#endif /* else __ESL_MASE_GEN97__ && !__MTK_TARGET__ */
+
+ #define DRV_WriteReg32_NPW(write_addr, data) \
+ DRV_WriteReg32_NPW_RB(write_addr, data, write_addr)
+ #define DRV_SetReg32_NPW(write_addr, data) \
+ DRV_WriteReg32_NPW(((kal_uint32)(write_addr)), DRV_Reg32(write_addr) | (data))
+ #define DRV_ClrReg32_NPW(write_addr, data) \
+ DRV_WriteReg32_NPW(((kal_uint32)(write_addr)), DRV_Reg32(write_addr) & (~(data)))
+
+
+#elif defined(COMMON_PLATFORM_MAP)
+ #define DRV_WriteReg32_NPW_RB(write_addr, data, read_addr) \
+ do{ \
+ if((write_addr)>=0x88000000U && (write_addr)<=0x8FFFFFFFU) \
+ { \
+ DRV_WriteReg32((write_addr)&(~(0x08000000)), (data)); \
+ } \
+ else if( ((write_addr)>>28)==0xB ) \
+ { \
+ DRV_WriteReg32((write_addr)&(~(0x10000000)), (data)); \
+ } \
+ /* Strongly Order: 0x80000000~0x87FFFFFF/0xA0000000 */ \
+ else if( (((write_addr)>>28)==8) || (((write_addr)>>28)==0xA) ) \
+ { \
+ DRV_WriteReg32((write_addr), (data)); \
+ } \
+ else \
+ { \
+ ASSERT(0); \
+ } \
+ }while(0);
+
+ #define DRV_WriteReg32_NPW(write_addr, data) \
+ DRV_WriteReg32_NPW_RB(write_addr, data, write_addr)
+ #define DRV_SetReg32_NPW(write_addr, data) \
+ DRV_WriteReg32_NPW(((kal_uint32)(write_addr)), DRV_Reg32(write_addr) | (data))
+ #define DRV_ClrReg32_NPW(write_addr, data) \
+ DRV_WriteReg32_NPW(((kal_uint32)(write_addr)), DRV_Reg32(write_addr) & (~(data)))
+#else
+ /* TBC */
+ #error "NPW API: unsupported CHIP"
+#endif /* end of TK6280/MT6290/others */
+
+#define DRV_ClearBits(addr,data) {\
+ kal_uint16 temp;\
+ temp = DRV_Reg(addr);\
+ temp &=~(data);\
+ DRV_WriteReg(addr,temp);\
+}
+
+#define DRV_SetBits(addr,data) {\
+ kal_uint16 temp;\
+ temp = DRV_Reg(addr);\
+ temp |= (data);\
+ DRV_WriteReg(addr,temp);\
+}
+
+#define DRV_SetData(addr, bitmask, value) {\
+ kal_uint16 temp;\
+ temp = (~(bitmask)) & DRV_Reg(addr);\
+ temp |= ((value) & (bitmask));\
+ DRV_WriteReg(addr,temp);\
+}
+
+#define DRV_ClearBits32(addr,data) {\
+ kal_uint32 temp;\
+ temp = DRV_Reg32(addr);\
+ temp &=~(data);\
+ DRV_WriteReg32(addr,temp);\
+}
+
+#define DRV_SetBits32(addr,data) {\
+ kal_uint32 temp;\
+ temp = DRV_Reg32(addr);\
+ temp |= (data);\
+ DRV_WriteReg32(addr,temp);\
+}
+
+#define DRV_SetData32(addr, bitmask, value) {\
+ kal_uint32 temp;\
+ temp = (~(bitmask)) & DRV_Reg32(addr);\
+ temp |= ((value) & (bitmask));\
+ DRV_WriteReg32(addr,temp);\
+}
+
+#define DRV_ClearBits8(addr,data) {\
+ kal_uint8 temp;\
+ temp = DRV_Reg8(addr);\
+ temp &=~(data);\
+ DRV_WriteReg8(addr,temp);\
+}
+
+#define DRV_SetBits8(addr,data) {\
+ kal_uint8 temp;\
+ temp = DRV_Reg8(addr);\
+ temp |= (data);\
+ DRV_WriteReg8(addr,temp);\
+}
+
+#define DRV_SetData8(addr, bitmask, value) {\
+ kal_uint8 temp;\
+ temp = (~(bitmask)) & DRV_Reg8(addr);\
+ temp |= ((value) & (bitmask));\
+ DRV_WriteReg8(addr,temp);\
+}
+
+#define DRV_BuildPrimitive(_ilm,_srcid,_dstid,_msgid,_data) \
+{\
+ _ilm->src_mod_id = _srcid;\
+ _ilm->sap_id = DRIVER_PS_SAP;\
+ _ilm->dest_mod_id = _dstid;\
+ _ilm->msg_id = _msgid;\
+ _ilm->local_para_ptr = (local_para_struct *)_data;\
+ _ilm->peer_buff_ptr = NULL;\
+}
+
+#define DRV_SendPrimitive(_ilm,_srcid,_dstid,_msgid,_data, _sap_id) \
+{\
+ _ilm->src_mod_id = _srcid;\
+ _ilm->sap_id = _sap_id;\
+ _ilm->dest_mod_id = _dstid;\
+ _ilm->msg_id = _msgid;\
+ _ilm->local_para_ptr = (local_para_struct *)_data;\
+ _ilm->peer_buff_ptr = NULL;\
+}
+
+extern void Fast_Memcpy(void *srcaddr, void *dstaddr, kal_uint32 leng);
+extern void Fast_SherifWrite(void *srcaddr,void *dstaddr,kal_uint32 len);
+extern void Fast_SherifRead(void *srcaddr,void *dstaddr,kal_uint32 len);
+// MoDIS parser skip start
+extern kal_uint32 SaveAndSetIRQMask(void);
+extern void RestoreIRQMask(kal_uint32);
+extern boot_mode_type Drv_query_boot_mode(void);
+// MoDIS parser skip end
+extern kal_uint32 drv_get_current_time(void);
+extern kal_uint32 drv_get_duration_tick(kal_uint32 previous_time, kal_uint32 current_time);
+extern kal_uint32 drv_get_duration_ms(kal_uint32 previous_time);
+
+// MoDIS parser skip start
+/// NFI bus mutex
+void get_NFI_bus(void);
+void free_NFI_bus(void);
+
+#if defined(DRV_DEBUG) || defined(ATEST_DRV_ENABLE)
+extern void dbg_print(char *fmt,...);
+extern void dbg_printWithTime(char *fmt,...);
+extern void dbg_flush(void);
+#endif /*DRV_DEBUG*/
+// MoDIS parser skip end
+
+#ifdef DRV_MEMORY_TRACE_DEBUG
+
+ #define MAX_DRV_DBG_INFO_SIZE 2048
+ typedef enum {
+ NAND_READ_START,
+ NAND_READ_STOP,
+ DRV_DBG_MAX_ID
+ } DRV_DBG_ID;
+
+ typedef struct{
+ kal_uint16 tag;
+ kal_uint32 time;
+ kal_uint32 data1;
+ kal_uint32 data2;
+ }DRV_DBG_DATA;
+
+ typedef struct{
+ DRV_DBG_DATA dbg_data[MAX_DRV_DBG_INFO_SIZE];
+ kal_uint16 dbg_data_idx;
+ }DRV_DBG_STRUCT;
+
+extern void drv_dbg_trace(kal_uint16 index, kal_uint32 time, kal_uint32 data1, kal_uint32 data2);
+#endif /*DRV_MEMORY_TRACE_DEBUG*/
+
+#if defined(__MTK_TARGET__)
+#if defined(__RVCT__)
+/* This marco is to get the reture address of the caller function. */
+#define DRV_GET_RET_ADDR(retAddr) {\
+ retAddr = __return_address();\
+}
+
+/* This marco is to provide a for loop delay with the count as the parameter.
+ To add NOP is to prevent it from being optimized. */
+#define DRV_FOR_LOOP(_count) \
+{\
+ kal_uint32 loop;\
+ for (loop=0;loop<_count;loop++)\
+ {\
+ __nop();\
+ }\
+ }\
+}\
+
+#elif defined(__GNUC__)
+
+/* This marco is to get the reture address of the caller function. */
+/* GCC has function to support this */
+#define DRV_GET_RET_ADDR(retAddr) {\
+ retAddr = __builtin_return_address (0);\
+}
+
+/* This marco is to provide a for loop delay with the count as the parameter.
+ To add NOP is to prevent it from being optimized. */
+#define DRV_FOR_LOOP(_count) \
+{\
+ kal_uint32 loop;\
+ for (loop=0;loop<_count;loop++)\
+ {\
+ __nop();\
+ }\
+ }\
+}\
+
+#else /* __RVCT__ */
+
+/* This marco is to get the reture address of the caller function. */
+#define DRV_GET_RET_ADDR(retAddr) {\
+ __asm {\
+ MOV retAddr,lr\
+ }\
+}
+
+/* This marco is to provide a for loop delay with the count as the parameter.
+ To add NOP is to prevent it from being optimized. */
+#define DRV_FOR_LOOP(_count) \
+{\
+ kal_uint32 loop;\
+ for (loop=0;loop<_count;loop++)\
+ {\
+ __asm {\
+ NOP\
+ }\
+ }\
+}\
+
+#endif /* __RVCT__ */
+
+#else //#if defined(__MTK_TARGET__)
+
+#define DRV_GET_RET_ADDR(retAddr)
+
+#define DRV_FOR_LOOP(_count)
+
+#endif //#if defined(__MTK_TARGET__)
+/*************************************************************************
+ APIs for driver debugging
+*************************************************************************/
+// MoDIS parser skip start
+#if defined(__TST_MODULE__)|| defined(L1_SIM)
+#if defined(MTK_KAL_MNT) || defined(KAL_ON_OSCAR) || defined(MCD_DLL_EXPORT) || defined(L1_SIM)
+INLINE_MODIFIER INLINE void drv_trace0(trace_class_enum trc_class, kal_uint32 msg_index, const char *arg_type)
+{
+ (void)trc_class;
+ (void)msg_index;
+ (void)arg_type;
+ return;
+}
+INLINE_MODIFIER INLINE void drv_trace1(trace_class_enum trc_class, kal_uint32 msg_index, const char *arg_type, kal_uint32 data1)
+{
+ (void)trc_class;
+ (void)msg_index;
+ (void)arg_type;
+ (void)data1;
+ return;
+}
+INLINE_MODIFIER INLINE void drv_trace2(trace_class_enum trc_class, kal_uint32 msg_index, const char *arg_type, kal_uint32 data1, kal_uint32 data2)
+{
+ (void)trc_class;
+ (void)msg_index;
+ (void)arg_type;
+ (void)data1;
+ (void)data2;
+ return;
+}
+INLINE_MODIFIER INLINE void drv_trace4(trace_class_enum trc_class, kal_uint32 msg_index, const char *arg_type, kal_uint32 data1, kal_uint32 data2, kal_uint32 data3, kal_uint32 data4)
+{
+ (void)trc_class;
+ (void)msg_index;
+ (void)arg_type;
+ (void)data1;
+ (void)data2;
+ (void)data3;
+ (void)data4;
+ return;
+}
+INLINE_MODIFIER INLINE void drv_trace8(trace_class_enum trc_class, kal_uint32 msg_index, const char *arg_type, kal_uint32 data1, kal_uint32 data2, kal_uint32 data3, kal_uint32 data4,
+ kal_uint32 data5, kal_uint32 data6, kal_uint32 data7, kal_uint32 data8)
+{
+ (void)trc_class;
+ (void)msg_index;
+ (void)arg_type;
+ (void)data1;
+ (void)data2;
+ (void)data3;
+ (void)data4;
+ (void)data5;
+ (void)data6;
+ (void)data7;
+ (void)data8;
+ return;
+}
+#else /*#if defined(MTK_KAL_MNT) || defined(KAL_ON_OSCAR) || defined(MCD_DLL_EXPORT) || defined(L1_SIM)*/
+extern void drv_trace0(trace_class_enum trc_class, kal_uint32 msg_index, const char *arg_type);
+extern void drv_trace1(trace_class_enum trc_class, kal_uint32 msg_index, const char *arg_type, kal_uint32 data1);
+extern void drv_trace2(trace_class_enum trc_class, kal_uint32 msg_index, const char *arg_type, kal_uint32 data1, kal_uint32 data2);
+extern void drv_trace4(trace_class_enum trc_class, kal_uint32 msg_index, const char *arg_type, kal_uint32 data1, kal_uint32 data2, kal_uint32 data3, kal_uint32 data4);
+extern void drv_trace8(trace_class_enum trc_class, kal_uint32 msg_index, const char *arg_type, kal_uint32 data1, kal_uint32 data2, kal_uint32 data3, kal_uint32 data4,
+ kal_uint32 data5, kal_uint32 data6, kal_uint32 data7, kal_uint32 data8);
+#endif /*#if defined(MTK_KAL_MNT) || defined(KAL_ON_OSCAR) || defined(MCD_DLL_EXPORT) || defined(L1_SIM)*/
+#else // #if defined(__TST_MODULE__)|| defined(L1_SIM)
+/*#define drv_trace0(...)*/
+/*#define drv_trace1(...)*/
+/*#define drv_trace2(...)*/
+/*#define drv_trace4(...)*/
+/*#define drv_trace8(...)*/
+#endif // #if defined(__TST_MODULE__)|| defined(L1_SIM)
+
+extern kal_uint8 drv_dummy_return(void);
+// MoDIS parser skip end
+#endif /*__DRV_COMM_H__*/
diff --git a/mcu/interface/driver/peripheral/drv_hisr.h b/mcu/interface/driver/peripheral/drv_hisr.h
new file mode 100644
index 0000000..b4b2644
--- /dev/null
+++ b/mcu/interface/driver/peripheral/drv_hisr.h
@@ -0,0 +1,441 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*******************************************************************************
+ * Filename:
+ * ---------
+ * drv_hisr.h
+ *
+ * Project:
+ * --------
+ * ALL
+ *
+ * Description:
+ * ------------
+ * This file is intends for central driver HISR.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _DRV_HISR_H
+#define _DRV_HISR_H
+
+#include "drv_comm.h"
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+typedef enum {
+ DRV_CCIF_HISR_ID = 0,
+ DRV_MDIF_HISR_ID,
+ DRV_RT_MDIF_HISR_ID,
+ DRV_BTIF_HISR_ID,
+ DRV_PFC_HISR_ID,
+ DRV_PFC_DECODE_HISR_ID,
+ DRV_PFC_ENCODE_HISR_ID,
+ DRV_USIM_HSIR_ID,
+ DRV_USIM2_HSIR_ID,
+ DRV_FMIF_HISR_ID,
+ DRV_EINT_HISR_ID,
+ DRV_DEINT_HISR_ID,
+ DRV_WDT_HISR_ID,
+ DRV_USB_HISR_ID,
+ DRV_USBDMA_HISR_ID,
+ DRV_GDMA_HISR_ID,
+ DRV_PCMON_HISR_ID,
+ DRV_USB_LOGGING_3G_HISR_ID,
+ DRV_USB_LOGGING_DSP1_HISR_ID,
+ DRV_USB_LOGGING_DSP2_HISR_ID,
+ DRV_NFI_HISR_ID,
+ DRV_MSDC_HISR_ID,
+ DRV_MSDC2_HISR_ID,
+ DRV_SIM_HISR_ID,
+ DRV_SIM2_HISR_ID,
+ DRV_UART1_HISR_ID,
+ DRV_UART2_HISR_ID,
+ DRV_UART3_HISR_ID,
+ DRV_DMA_HISR_ID,
+ DRV_GPT1_HISR_ID,
+ DRV_GPT2_HISR_ID,
+ DRV_GPT3_HISR_ID,
+ DRV_GPT4_HISR_ID,
+ DRV_GPT5_HISR_ID,
+ DRV_GPT6_HISR_ID,
+ DRV_PWM_HISR_ID,
+ DRV_LCD_WFC_HISR_ID,
+ DRV_LCD_HISR_ID,
+ DRV_GOVL_HISR_ID,
+ DRV_HIF0_HISR_ID,
+ DRV_HIF1_HISR_ID,
+ DRV_BTIF_SLEEP_WAKEUP_OUT_HISR_ID,
+ DRV_ACCDET_HISR_ID,
+ DRV_KP_HISR_ID,
+ DRV_AUXADC_HISR_ID,
+ DRV_RTC_HISR_ID,
+ DRV_FPGA_DMA_HISR_ID,
+ DRV_IRDA_HISR_ID,
+ DRV_CHE_HISR_ID,
+ DRV_SPI_HISR_ID,
+ DRV_NIRQ_HISR_ID,
+ DRV_NFIQ_HISR_ID,
+ DRV_DMA2_HISR_ID,
+ DRV_GROT_HISR_ID,
+ DRV_LZMA_HISR_ID,
+ DRV_IDC_HISR_ID,
+ DRV_BUSMON_HISR_ID,
+ DRV_EBC_HISR_ID,
+ DRV_GDMA2_HISR_ID,
+ DRV_DEM_HISR_ID,
+ DRV_MTAD_HISR_ID,
+ MAX_DRV_HISR_DEVICE,
+ DRV_UNKNOWN_HISR_ID = 0xfe
+} DRV_HISR_ID;
+
+#if MAX_DRV_HISR_DEVICE > (32*2)
+#error DRV HISR ID out of range!!
+#endif
+
+
+typedef struct {
+ VOID_FUNC hisr_func;
+ kal_uint16 hisr_count;
+} DRV_HISR_STRUCT;
+
+#if !defined(__FUE__) && !defined(__UBL__)
+extern void drv_active_hisr(DRV_HISR_ID id);
+#else /* __FUE__ */
+#define drv_active_hisr(_id)
+#endif /* __FUE__ */
+
+
+//typedef void (* VOID_FUNCTION)(void);
+extern kal_hisrid drv_hisr;
+extern kal_uint32 drv_hisr_status1;
+extern kal_uint32 drv_hisr_status2;
+extern DRV_HISR_STRUCT DRV_HISR_TABLE[MAX_DRV_HISR_DEVICE];
+
+// MoDIS parser skip start
+extern void DRV_Register_HISR(DRV_HISR_ID hisr_id, VOID_FUNC hisr_func);
+extern void DRV_HISR(void);
+extern void DRV_ERROR_HISR(void);
+extern void drv_hisr_init(void);
+// MoDIS parser skip end
+#endif /*_DRV_HISR_H*/
+
diff --git a/mcu/interface/driver/peripheral/drvsignals.h b/mcu/interface/driver/peripheral/drvsignals.h
new file mode 100644
index 0000000..48ed8b1
--- /dev/null
+++ b/mcu/interface/driver/peripheral/drvsignals.h
@@ -0,0 +1,532 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * drvsignals.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for driver primitives.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _DRVSIGNALS_H
+#define _DRVSIGNALS_H
+
+#include "bmt.h"
+#include "usb_comm.h"
+#include "kal_public_api.h" //#include "stack_ltlcom.h" //MSBB change #include "app_ltlcom.h"
+#include "kal_general_types.h"
+#include "dcl.h"
+
+
+/*RTC driver*/
+#define RTC_TC_IND 0
+#define RTC_AL_IND 1
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint8 rtc_ind;
+} RTC_Primitive;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ DCL_RTC_DATA_T previous_rtc;
+ DCL_RTC_DATA_T new_rtc;
+} RTC_Time_Change_IND_Struct;
+
+/*Kbd driver*/
+#define Kbd_KeyPress 0
+#define Kbd_KeyRelease 1
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint8 kp_status;
+ kal_uint8 key;
+} Kbd_Primitive;
+
+/*Communicated with MMI, charging status*/
+typedef enum
+{
+ BMT_CHARGER_IN = 0,
+ BMT_CHARGER_OUT,
+ BMT_OVERVOLPROTECT,
+ BMT_OVERBATTEMP,
+ BMT_LOWBATTEMP,
+ BMT_OVERCHARGECURRENT,
+ BMT_CHARGE_COMPLETE,
+ BMT_INVALID_BAT,
+ BMT_INVALID_CHARGER,
+ BMT_CHARGE_TIMEOUT,
+ BMT_LOWCHARGECURRENT,
+ BMT_CHARGE_BAD_CONTACT,
+ BMT_BATTERY_BAD_CONTACT,
+ BMT_USB_CHARGER_IN,
+ BMT_USB_CHARGER_OUT,
+ BMT_USB_NO_CHARGING_IN,
+ BMT_USB_NO_CHARGING_OUT,
+ BMT_BATT_IN,
+ BMT_BATT_OUT
+}BMT_CHR_STAT;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ BMT_CHR_STAT status;
+} drvuem_pmic_ind_struct;
+
+/*ADC scheduler*/
+typedef struct {
+ LOCAL_PARA_HDR
+ double adc_value;
+ kal_int32 adc_handle;
+ kal_int32 volt;
+ kal_uint8 adc_sche_id;
+} bmt_adc_measure_done_conf_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_int32 adc_handle;
+ kal_uint8 adc_sche_id;
+} bmt_adc_add_item_req_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_int32 adc_handle;
+ kal_uint8 adc_sche_id;
+} bmt_adc_remove_item_req_struct;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_int32 adc_handle;
+ kal_uint32 period;
+ kal_uint8 evaluate_count;
+ kal_uint8 adc_sche_id;
+} bmt_adc_modify_parameters_req_struct;
+
+/*AUX task*/
+typedef enum
+{
+ AUX_ID_PLUGOUT=0,
+ AUX_ID_TVOUT,
+ AUX_ID_EARPHONE,
+ AUX_ID_KEY_PRESS,
+ AUX_ID_KEY_RELEASE,
+ AUX_ID_UART,
+ AUX_ID_CLAM_OPEN,
+ AUX_ID_CLAM_CLOSE,
+ AUX_ID_TVOUT_OUT,
+ AUX_ID_TVOUT_INIT1,
+ AUX_ID_DETECTION_DONE,
+ AUX_ID_PLUGIN,
+ AUX_ID_TRANSMITTER_HOLD_ON,
+ AUX_ID_TRANSMITTER_PUT_DOWN,
+ AUX_MAX_ID
+}AUX_ID;
+typedef struct {
+ LOCAL_PARA_HDR
+ AUX_ID aux_id;
+} aux_id_struct;
+
+/*Engineering mode*/
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_int32 vbat; /*Battery Voltage(micro-voltage)*/
+ kal_int32 bat_temp; /*Battery Temperature(¢J)*/
+ kal_int32 vaux; /*AUX Voltage(micro-voltage)*/
+ kal_int32 charge_current; /*Charge current(micro-A)*/
+ kal_int32 vcharger; /*Charger Voltage(micro-voltage)*/
+} adc_all_channel_struct;
+
+/*USB driver*/
+typedef struct {
+ LOCAL_PARA_HDR
+ void *pData; /* Pointer to data buffer */
+ kal_int32 nBuffLen; /* Length of data buffer */
+ kal_int32 nBytesRecv; /* Number of bytes received */
+} usb_ms_rec_done_conf_struct;
+
+/*L4->USB*/
+typedef struct {
+ LOCAL_PARA_HDR
+ USB_DEVICE_TYPE mode;
+ kal_uint32 *parameter;
+} drvuem_usbcfg_req_struct;
+
+/*USB->USB*/
+typedef struct {
+ LOCAL_PARA_HDR
+ USB_DEVICE_TYPE mode;
+ kal_uint32 *parameter;
+ kal_uint32 device_code;
+ kal_uint32 subclass_code;
+ kal_uint32 protocol_code;
+ kal_uint32 product_code;
+} drvusb_usbcfg_req_struct;
+
+/*USB->L4*/
+typedef struct {
+ LOCAL_PARA_HDR
+ USB_DEVICE_TYPE mode;
+ kal_uint32 reserved;
+ kal_bool result;
+} drvuem_usbcfg_cnf_struct;
+
+/*USB->L4*/
+typedef enum
+{
+ DETECT_ACTION_UNKNOWN=0,
+ DETECT_ACTION_PLUGIN,
+ DETECT_ACTION_PLUGOUT,
+ DETECT_ACTION_USB_SUSPEND,
+ DETECT_ACTION_MAX_ID
+}USB_DETECT_ACTION_ID;
+
+typedef struct {
+ LOCAL_PARA_HDR
+ USB_DETECT_ACTION_ID action; /*1: Plugin, 0:PlugOut*/
+}drvuem_usbdetect_ind_struct;
+
+// add for usb charging
+typedef enum{
+ BMT_USB_100,
+ BMT_USB_500
+}bmt_usb_ind_enum;
+
+typedef struct{
+ LOCAL_PARA_HDR
+ PMU_CHR_CURRENT_ENUM usb_ind;
+}bmt_usb_ind_struct;
+
+typedef struct{
+ LOCAL_PARA_HDR
+ PW_CTRL_POWER_ON_REASON power_on;
+ kal_uint32 poweron_time_left;
+}drvuem_power_on_ind_struct;
+
+
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint8 usb_ip_port;
+ kal_uint8 feature_index;
+// USB_HCD_STATUS result;
+ kal_uint8 result;
+ kal_uint32 param;
+}usb_host_usbattach_ind_struct;
+
+
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_bool confirm;
+}rndis_usb_config_cnf_struct;
+
+
+
+/* ----------------------------------MTP------------------------------------*/
+
+/*
+ * Macro
+ */
+#define MTP_PARAM_MAX 5
+#define MTP_EVENT_MAX 3
+
+/*
+ * Enum
+ */
+
+typedef enum {
+ USB_MTP_RESULT_OK = 0,
+ USB_MTP_RESULT_CONTINUE,
+ USB_MTP_RESULT_ABORTED,
+ USB_MTP_RESULT_DEVICE_BUSY,
+ USB_MTP_RESULT_NOT_ENABLE,
+ USB_MTP_RESULT_ALREADY_ENABLE,
+ USB_MTP_RESULT_UNKNOWN_ERROR
+}usb_mtp_result_enum;
+
+
+typedef enum {
+ USB_MTP_EVENT_NORMAL = 0,
+ USB_MTP_EVENT_ABORT
+}usb_mtp_event_enum;
+
+
+/*
+ * Struct
+ */
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_int32 result_code; /* < 0: FS error
+ >= 0: usb_mtp_result_enum */
+}usb_mtp_enable_rsp_struct, usb_mtp_disable_rsp_struct;
+
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint16 op_code; /* operation */
+ kal_uint32 op_params[MTP_PARAM_MAX]; /* operation */
+
+// kal_uint16 op_serial_no; /* start from 0 */
+
+ /* Data phase */
+ kal_uint32 data_total_size; /* size of total data, 0 means no Data phase */
+ kal_uint8 *data_pool_ptr; /* data pool */
+ kal_uint32 data_pool_size; /* size of data pool */
+ kal_uint32 data_size; /* size of real data, signle direction */
+}usb_mtp_operation_req_struct;
+
+
+typedef struct {
+ LOCAL_PARA_HDR
+
+ kal_int32 result_code; /* < 0: FS error
+ >= 0: usb_mtp_result_enum */
+ kal_uint16 rsp_code;
+ kal_uint32 rsp_params[MTP_PARAM_MAX];
+
+ kal_uint16 op_code;
+// kal_uint16 op_serial_no; /* start from 0 */
+
+ /* Data phase */
+ kal_uint32 data_total_size; /* size of total data, 0 means no Data phase */
+ kal_uint8 *data_pool_ptr; /* data pool */
+ kal_uint32 data_pool_size; /* size of data pool */
+ kal_uint32 data_size; /* size of real data */
+}usb_mtp_operation_rsp_struct;
+
+
+typedef struct {
+ LOCAL_PARA_HDR
+ kal_uint16 event; // see usb_mtp_event_enum
+ kal_uint16 event_code;
+ kal_uint32 params[MTP_EVENT_MAX];
+}usb_mtp_event_ind_struct;
+
+
+#endif
+
diff --git a/mcu/interface/driver/peripheral/gpio_sw.h b/mcu/interface/driver/peripheral/gpio_sw.h
new file mode 100644
index 0000000..ee8dfa2
--- /dev/null
+++ b/mcu/interface/driver/peripheral/gpio_sw.h
@@ -0,0 +1,374 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * gpio_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for GPIO driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _GPIO_SW_H
+#define _GPIO_SW_H
+
+#include "drv_features_gpio.h"
+#include "dcl.h"
+#include "drv_comm.h"
+#include "kal_general_types.h"
+
+
+#if !defined(DRV_GPIO_OFF)
+//#define __DRV_GPIO_REG_DBG__
+
+#define GPIO_6280_INVAILD_INDEX 200
+#define GPIO_6280_MIN_PIN_A 60
+#define GPIO_6280_MAX_PIN_A 67
+#define GPIO_6280_MIN_PIN_B 83
+#define GPIO_6280_MAX_PIN_B 90
+
+#if defined(DRV_GPIO_6280_SPECIAL_SET_REG)
+typedef struct MT6280_GPIO_PULL_EN_SELL_MAP_TABLE_TAG
+{
+
+ kal_uint16 pullen_sel_index;
+ kal_uint16 pullen_reg_num; // which register
+ kal_uint16 pullen_remainder; // which bit in register
+ kal_uint16 pullsel_remainder; // which bit in register
+}MT6280_GPIO_PULL_EN_SELL_MAP_Table_T;
+
+#endif
+
+#ifdef __DRV_GPIO_REG_DBG__
+
+#define DRV_GPIO_WriteReg(addr,data) DRV_DBG_WriteReg(addr,data)
+#define DRV_GPIO_Reg(addr) DRV_DBG_Reg(addr)
+#define DRV_GPIO_WriteReg32(addr,data) DRV_DBG_WriteReg32(addr,data)
+#define DRV_GPIO_Reg32(addr) DRV_DBG_Reg32(addr)
+#define DRV_GPIO_WriteReg8(addr,data) DRV_DBG_WriteReg8(addr,data)
+#define DRV_GPIO_Reg8(addr) DRV_DBG_Reg8(addr)
+
+
+#define DRV_GPIO_ClearBits(addr,data) DRV_DBG_ClearBits(addr,data)
+#define DRV_GPIO_SetBits(addr,data) DRV_DBG_SetBits(addr,data)
+#define DRV_GPIO_ClearBits32(addr,data) DRV_DBG_ClearBits32(addr,data)
+#define DRV_GPIO_SetBits32(addr,data) DRV_DBG_SetBits32(addr,data)
+#define DRV_GPIO_ClearBits8(addr,data) DRV_DBG_ClearBits8(addr,data)
+#define DRV_GPIO_SetBits8(addr,data) DRV_DBG_SetBits8(addr,data)
+
+#define DRV_GPIO_SetData(addr, bitmask, value) DRV_DBG_SetData(addr, bitmask, value)
+#define DRV_GPIO_SetData32(addr, bitmask, value) DRV_DBG_SetData32(addr, bitmask, value)
+#define DRV_GPIO_SetData8(addr, bitmask, value) DRV_DBG_SetData8(addr, bitmask, value)
+
+#else //__DRV_GPIO_REG_DBG__
+
+#define DRV_GPIO_WriteReg(addr,data) DRV_WriteReg(addr,data)
+#define DRV_GPIO_Reg(addr) DRV_Reg(addr)
+#define DRV_GPIO_WriteReg32(addr,data) DRV_WriteReg32(addr,data)
+#define DRV_GPIO_Reg32(addr) DRV_Reg32(addr)
+#define DRV_GPIO_WriteReg8(addr,data) DRV_WriteReg8(addr,data)
+#define DRV_GPIO_Reg8(addr) DRV_Reg8(addr)
+
+
+#define DRV_GPIO_ClearBits(addr,data) DRV_ClearBits(addr,data)
+#define DRV_GPIO_SetBits(addr,data) DRV_SetBits(addr,data)
+#define DRV_GPIO_ClearBits32(addr,data) DRV_ClearBits32(addr,data)
+#define DRV_GPIO_SetBits32(addr,data) DRV_DBGD_SetBits32(addr,data)
+#define DRV_GPIO_ClearBits8(addr,data) DRV_ClearBits8(addr,data)
+#define DRV_GPIO_SetBits8(addr,data) DRV_SetBits8(addr,data)
+
+#define DRV_GPIO_SetData(addr, bitmask, value) DRV_SetData(addr, bitmask, value)
+#define DRV_GPIO_SetData32(addr, bitmask, value) DRV_SetData32(addr, bitmask, value)
+#define DRV_GPIO_SetData8(addr, bitmask, value) DRV_SetData8(addr, bitmask, value)
+
+#endif //__DRV_GPIO_REG_DBG__
+
+#else //#if !defined(DRV_GPIO_OFF)
+
+#define DRV_GPIO_WriteReg(addr,data)
+#define DRV_GPIO_Reg(addr) drv_dummy_return()
+#define DRV_GPIO_WriteReg32(addr,data)
+#define DRV_GPIO_Reg32(addr) drv_dummy_return()
+#define DRV_GPIO_WriteReg8(addr,data)
+#define DRV_GPIO_Reg8(addr) drv_dummy_return()
+
+
+#define DRV_GPIO_ClearBits(addr,data)
+#define DRV_GPIO_SetBits(addr,data)
+#define DRV_GPIO_ClearBits32(addr,data)
+#define DRV_GPIO_SetBits32(addr,data)
+#define DRV_GPIO_ClearBits8(addr,data)
+#define DRV_GPIO_SetBits8(addr,data)
+
+#define DRV_GPIO_SetData(addr, bitmask, value)
+#define DRV_GPIO_SetData32(addr, bitmask, value)
+#define DRV_GPIO_SetData8(addr, bitmask, value)
+
+#endif //#if !defined(DRV_GPIO_OFF)
+
+extern kal_bool Is_6280_SPEC_GPIO( kal_uint16 pin);
+extern kal_uint16 get_6280_spec_index( kal_uint16 pin_num);
+extern void GPIO_MD_InitIO(char direction, char port);
+extern void GPIO_MD_ModeSetup(kal_uint16 pin, kal_uint16 conf_dada);
+extern DCL_UINT32 MD_get_gpio_pin_number(DCL_UINT32 flags);
+
+
+
+extern void GPIO_InitIO(char direction, char port);
+extern char GPIO_ReadIO(char port);
+extern kal_uint16 GPIO_ReadAll(void);
+extern void GPIO_WriteIO(char data, char port);
+extern void GPIO_WriteAll(kal_uint16 write_data);
+extern char GPIO_ReturnMode(char port);
+extern char GPO_ReturnMode(char port);
+extern char GPIO_ReturnDir(char port);
+extern char GPIO_ReturnDout(char port);
+extern char GPO_ReturnDout(char port);
+extern void GPO_WriteIO(char data,char port);
+extern void GPO_WriteAll(kal_uint16 write_data);
+extern void GPIO_ModeSetup(kal_uint16 pin, kal_uint16 conf_dada);
+extern void GPO_ModeSetup(kal_uint16 pin, kal_uint16 conf_dada);
+extern void initGPIO(void);
+//extern void GPIO_init_(void);
+extern void GPIO_ALLIO(void);
+extern void GPIO_PullenSetup(kal_uint16 pin, kal_bool enable);
+extern void GPIO_DinvSetup(kal_uint16 pin, kal_bool enable);
+extern void GPIO_SetDebugMode(kal_bool enable);
+extern void GPIO_SetClkOut(char clk_num, gpio_clk_mode mode);
+extern void GPIO_SetClkDiv(char clk_num, gpio_clk_div div);
+extern void GPIO_PullSelSetup(kal_uint16 pin, kal_bool pull_up);
+extern void GPIO_TMDir(kal_bool pad_oe);
+#ifdef __CUST_NEW__
+extern void GPIO_ModeSetup_FAST(kal_uint16 pin, kal_uint16 conf_dada);
+extern void GPIO_InitIO_FAST(char direction, char port);
+extern char GPIO_ReadIO_FAST(char port);
+extern void GPIO_WriteIO_FAST(char data, char port);
+#endif/* __CUST_NEW__ */
+extern void GPIO_Check_MultiPins(GPIOCheckStruct *check_ptr, kal_uint32 pin_cnt);
+extern void GPIO_WriteIO_Force(char data, char port);
+extern void GPIO_WriteIO_FAST2(char data, kal_uint16 no, kal_uint16 remainder_shift);
+#endif
+
diff --git a/mcu/interface/driver/peripheral/hif_hal.h b/mcu/interface/driver/peripheral/hif_hal.h
new file mode 100644
index 0000000..928ecfc
--- /dev/null
+++ b/mcu/interface/driver/peripheral/hif_hal.h
@@ -0,0 +1,393 @@
+#ifndef __HIF_HAL_H__
+/* !ignore me! */
+#define __HIF_HAL_H__
+
+#include "kal_general_types.h"
+#include "drv_features.h"
+
+#ifdef DRV_HIF_SUPPORT
+
+/* <GROUP CallBackFunctions>
+ FUNCTION
+ HIF_CALLBACK
+ DESCRIPTION
+ HIF callback function
+ HIF callback function is called when HIF interrupt has arrived. It indicates HIF has finished the last data transfer.
+ HIF callback function is called in the context of HISR.
+*/
+typedef void (*HIF_CALLBACK)(void);
+
+/* HIF Handle.
+ HIF handle can be retrieved from hif_open(). It is used for most HIF APIs.
+*/
+typedef kal_uint32 HIF_HANDLE;
+
+/* HIF transfer type.
+ Defines the transfer type of HIF interface.
+*/
+typedef enum
+{
+ /* HIF transfer with A0=1. Use CPU to move data. */
+ HIF_TYPE_A0H_CPU,
+ /* HIF transfer with A0=1. Use DMA to transfer data. */
+ HIF_TYPE_A0H_DMA,
+ /* HIF transfer with A0=0. Use CPU to move data. */
+ HIF_TYPE_A0L_CPU,
+ /* HIF transfer with A0=0. Use DMA to transfer data. */
+ HIF_TYPE_A0L_DMA,
+} HIF_TYPE;
+
+/* HIF result enum.
+*/
+typedef enum
+{
+ /* Indicates no error occurs in the last operation. */
+ HIF_RESULT_OK,
+ /* Indicates some errors have occured in the last operation. */
+ HIF_RESULT_ERROR,
+ /* Indicates the function is not supported on the current platform. */
+ HIF_RESULT_NOT_SUPPORTED,
+ /* Indicates the HIF handle is not valid. */
+ HIF_RESULT_INVALID_HANDLE,
+ /* Indicates the input argument is not valid. */
+ HIF_RESULT_INVALID_ARGUMENT,
+ /* Indicates that the HIF power was not turned on when making HIF transactions. */
+ HIF_RESULT_HIF_NOT_POWER_ON,
+ /* Indicates that the HIF power was not turned on when making HIF transactions. */
+ HIF_RESULT_DMA_IS_BUSY
+} HIF_RESULT;
+
+/*************************************************************************************************************************************
+ * HIF IOCTL code definition.
+ * For detail description and usage of HIF control codes, please refer to <xref target="HIF HAL IOCTL Code" text="HIF IOCTL Code" />.
+ *************************************************************************************************************************************/
+typedef enum
+{
+ /****************************************************************************************************************
+ * Get the current HIF configuration parameters.
+ * For detail description and usage of this control code, please refer to <xref target="HIF_IOCTL_GET_PARAM" />.
+ ****************************************************************************************************************/
+ HIF_IOCTL_GET_PARAM,
+ /****************************************************************************************************************
+ * Set ultra high control for HIF.
+ * For detail description and usage of this control code, please refer to <xref target="HIF_IOCTL_ULTRA_HIGH_CTRL" />.
+ ****************************************************************************************************************/
+ HIF_IOCTL_ULTRA_HIGH_CTRL,
+ /****************************************************************************************************************
+ * Query HIF timing support.
+ * For detail description and usage of this control code, please refer to <xref target="HIF_IOCTL_QUERY_TIMING_SUPPORT" />.
+ ****************************************************************************************************************/
+ HIF_IOCTL_QUERY_TIMING_SUPPORT,
+ /****************************************************************************************************************
+ * Query HIF capabilities.
+ * For detail description and usage of this control code, please refer to <xref target="HIF_IOCTL_QUERY_CAPABILITY" />.
+ ****************************************************************************************************************/
+ HIF_IOCTL_QUERY_CAPABILITY,
+ /****************************************************************************************************************
+ * Query HIF clock support.
+ * For detail description and usage of this control code, please refer to <xref target="HIF_IOCTL_QUERY_CLOCK_SUPPORT" />.
+ ****************************************************************************************************************/
+ HIF_IOCTL_QUERY_CLOCK_SUPPORT,
+ /****************************************************************************************************************
+ * Query HIF power state.
+ * For detail description and usage of this control code, please refer to <xref target="HIF_IOCTL_QUERY_POWER_STATE" />.
+ ****************************************************************************************************************/
+ HIF_IOCTL_QUERY_POWER_STATE,
+ /****************************************************************************************************************
+ * TD realtime support.
+ * For detail description and usage of this control code, please refer to <xref target="HIF_IOCTL_REALTIME_REQUEST" />.
+ ****************************************************************************************************************/
+ HIF_IOCTL_REALTIME_CALLBACK
+} HIF_IOCTL_CODE;
+
+/**********************************
+ * HIF configuration parameters.
+ *
+ * Remarks
+ * <img name="hif_write_timing" />
+ *
+ * <img name="hif_read_timing" />
+ **********************************/
+typedef struct
+{
+ /* Chip Select (LPCE#) to Write Strobe (LWR#) setup time. */
+ kal_uint32 hif_time_c2ws;
+ /* Chip Select (LPCE#) to Write Strobe (LWR#) hold time. */
+ kal_uint32 hif_time_c2wh;
+ /* Write wait state time. */
+ kal_uint32 hif_time_wst;
+ /* Chip Select (LPCE#) to Read Strobe (LRD#) setup time. */
+ kal_uint32 hif_time_c2rs;
+ /* Chip Select (LPCE#) to Read Strobe (LRD#) hold time. */
+ kal_uint32 hif_time_c2rh;
+ /* Read latency time. */
+ kal_uint32 hif_time_rlt;
+ /* Chip Select high width. */
+ kal_uint32 hif_time_chw;
+ /* HIF base clock. Unit in MHz. */
+ kal_uint32 hif_base_clk;
+ /* HIF bus width. */
+ kal_uint32 hif_bus_width;
+} HIF_CONFIG_T;
+
+/* This structure is used as the parameter of HIF_IOCTL_QUERY_TIMING_SUPPORT.
+*/
+typedef struct
+{
+ /* Indicates whether C2WS is supported. */
+ kal_bool c2ws_support;
+ /* Indicates whether C2WH is supported. */
+ kal_bool c2wh_support;
+ /* Indicates whether WST is supported. */
+ kal_bool wst_support;
+ /* Indicates whether C2RS is supported. */
+ kal_bool c2rs_support;
+ /* Indicates whether C2RH is supported. */
+ kal_bool c2rh_support;
+ /* Indicates whether CHW is supported. */
+ kal_bool chw_support;
+ /* Indicates whether RLT is supported. */
+ kal_bool rlt_support;
+} HIF_QUERY_TIMING_SUPPORT_T;
+
+/* This structure is used as the parameter of HIF_IOCTL_QUERY_CLOCK_SUPPORT.
+*/
+typedef struct
+{
+ /* This array contains the supported clock frequencies. Unit in MHz. Value 0 indicates invalid clock frequency.*/
+ kal_uint32 clock[4];
+} HIF_QUERY_CLOCK_SUPPORT_T;
+
+/* This structure is used as the parameter of HIF_IOCTL_QUERY_CAPABILITY.
+*/
+typedef struct
+{
+ /* Minimum value for HIF transfer length. */
+ kal_uint32 transfer_length_min;
+ /* Maximum value for HIF transfer length. */
+ kal_uint32 transfer_length_max;
+} HIF_CAPABILITY_T;
+
+/* This structure is used as the parameter of HIF_IOCTL_ULTRA_HIGH_CTRL.
+*/
+typedef struct
+{
+ /* Enable ultra high signal during HIF transaction. */
+ kal_bool ultra_high_en;
+} HIF_ULTRA_HIGH_CTRL_T;
+
+
+/* This structure is used as the parameter of HIF_IOCTL_QUERY_POWER_STATE.
+*/
+typedef struct
+{
+ /* HIF power state. */
+ kal_bool hif_power_on;
+} HIF_POWER_STATE_T;
+
+/* This structure is used as the parameter of HIF_IOCTL_REALTIME_CALLBACK.
+*/
+typedef struct
+{
+ /* Enable realtime request,Call HIF callback function(hif_hisr) at LISR level. */
+ kal_bool realtime_callback_en;
+} HIF_REALTIME_CALLBACK_T;
+
+/**************************************************************************************************************************************
+ * Function
+ * hif_init
+ * Description
+ * Initialize HIF hardware and structures.
+ * Returns
+ * None.
+ * Remarks
+ * <color Red>This function is called in system initialization. HIF user does not need to call this function.</color>
+ **************************************************************************************************************************************/
+void hif_init(void);
+
+/**************************************************************************************************************************************
+ * Function
+ * hif_open
+ * Description
+ * Open and get HIF handle.
+ * Parameters
+ * port : [IN] HIF port. Zero based port index.
+ * Returns
+ * Return a HIF handle.
+ * Example
+ * <code>
+ * HIF_HANDLE handle;
+ * handle = hif_open(0);
+ * </code>
+ **************************************************************************************************************************************/
+HIF_HANDLE hif_open(kal_uint32 port);
+
+/********************************************************
+ * Function
+ * hif_close
+ * Description
+ * Release a HIF handle.
+ * Parameters
+ * handle : [IN] HIF handle. Retrieved from hif_open().
+ * Returns
+ * Return a HIF result code.
+ * Example
+ * <code>
+ * HIF_HANDLE handle;
+ * handle = hif_open(0);
+ * // HIF operations.
+ * hif_close(handle);
+ * </code>
+ ********************************************************/
+HIF_RESULT hif_close(HIF_HANDLE handle);
+
+/***********************************************************************
+ * Function
+ * hif_config
+ * Description
+ * Configure HIF timing parameters.
+ * HIF parameters must be set before any HIF transmissions.
+ * Parameters
+ * handle : [IN] HIF handle. Retrieved from hif_open().
+ * pConfigParam : [IN] HIF parameters. Refer to HIF_CONFIG_T for details.
+ * Returns
+ * Return a HIF result code.
+ * Example
+ * <code>
+ * HIF_HANDLE handle;
+ * HIF_CONFIG_T hif_config_param;
+ * handle = hif_open(0);
+ * hif_config_param.hif_time_c2ws = 3;
+ * hif_config_param.hif_time_c2wh = 2;
+ * hif_config_param.hif_time_wst = 15;
+ * hif_config_param.hif_time_c2rs = 4;
+ * hif_config_param.hif_time_c2rh = 0;
+ * hif_config_param.hif_time_rlt = 0x1f;
+ * hif_config_param.hif_base_clk = 122;
+ * hif_config_param.hif_bus_width = 16;
+ * hif_config(handle, &hif_config_param);
+ * // ...
+ * hif_close(handle);
+ * </code>
+ ***********************************************************************/
+HIF_RESULT hif_config(HIF_HANDLE handle, HIF_CONFIG_T* pConfigParam);
+
+/*******************************************************************************
+ * Function
+ * hif_write
+ * Description
+ * Fire a HIF transmission for output.
+ * Parameters
+ * handle : [IN] HIF handle. Retrieved from hif_open().
+ * type : [IN] HIF transfer type. Refer to HIF_TYPE for details.
+ * addr : [IN] Data buffer address for output.
+ * size : [IN] Data length for HIF transfer. Unit in bytes.
+ * fCB : [IN] Specifies the callback function when the transmission completes.
+ * If fCB is specified, HIF driver uses interrupt mode. This API is asynchronous.
+ * If fCB is NULL, HIF drvier uses polling mode. This API becomes synchronous.
+ * Returns
+ * Return a HIF result code.
+ * Remarks
+ * If type is set to HIF_TYPE_A0H_CPU or HIF_TYPE_A0L_CPU, fCB is ignored. HIF driver works synchronous in CPU mode.
+ * Example
+ * <code>
+ * HIF_HANDLE handle;
+ * handle = hif_open(0);
+ * // ...
+ *
+ * // Synchronous call.
+ * hif_write(handle, HIF_TYPE_A0H_CPU, hif_test_buffer, 1024, NULL);
+ *
+ * // Asynchronous call.
+ * hif_write(handle, HIF_TYPE_A0H_DMA, hif_test_buffer, 1024, hif_test_cb);
+ * // Wait for a event which is set in callback function.
+ * // ...
+ * hif_close(handle);
+ * </code>
+ *******************************************************************************/
+HIF_RESULT hif_write(HIF_HANDLE handle, HIF_TYPE type, kal_uint32 addr, kal_uint32 size, HIF_CALLBACK fCB);
+
+/*******************************************************************************
+ * Function
+ * hif_read
+ * Description
+ * Fire a HIF transmission for input.
+ * Parameters
+ * handle : [IN] HIF handle. Retrieved from hif_open().
+ * type : [IN] HIF transfer type. Refer to HIF_TYPE for details.
+ * addr : [IN] Data buffer address for input.
+ * size : [IN] Data length for HIF transfer. Unit in bytes.
+ * fCB : [IN] Specifies the callback function when the transmission completes.
+ * If fCB is specified, HIF driver uses interrupt mode. This API is asynchronous.
+ * If fCB is NULL, HIF drvier uses polling mode. This API becomes synchronous.
+ * Returns
+ * Return a HIF result code.
+ * Remarks
+ * If type is set to HIF_TYPE_A0H_CPU or HIF_TYPE_A0L_CPU, fCB is ignored. HIF driver works synchronous in CPU mode.
+ * Example
+ * <code>
+ * HIF_HANDLE handle;
+ * handle = hif_open(0);
+ * // ...
+ *
+ * // Synchronous call.
+ * hif_read(handle, HIF_TYPE_A0H_CPU, hif_test_buffer, 1024, NULL);
+ *
+ * // Asynchronous call.
+ * hif_read(handle, HIF_TYPE_A0H_DMA, hif_test_buffer, 1024, hif_test_cb);
+ * // Wait for a event which is set in callback function.
+ * // ...
+ * hif_close(handle);
+ * </code>
+ *******************************************************************************/
+HIF_RESULT hif_read(HIF_HANDLE handle, HIF_TYPE type, kal_uint32 addr, kal_uint32 size, HIF_CALLBACK fCB);
+
+/*****************************************************************************
+ * Function
+ * hif_power_ctrl
+ * Description
+ * Enable or disable HIF hardware power.
+ * Parameters
+ * handle : [IN] HIF handle. Retrieved from hif_open().
+ * bPowerOn : [IN] Set KAL_TRUE to power on HIF hardware. Set KAL_FALSE to power off HIF hardware.
+ * Returns
+ * Return a HIF result code.
+ * Example
+ * <code>
+ * HIF_HANDLE handle;
+ * handle = hif_open(0);
+ * hif_power_ctrl(handle, KAL_TRUE);
+ * // HIF operations.
+ * hif_power_ctrl(handle, KAL_FALSE);
+ * hif_close(handle);
+ * </code>
+ *****************************************************************************/
+HIF_RESULT hif_power_ctrl(HIF_HANDLE handle, kal_bool bPowerOn);
+
+/*****************************************************************************
+ * Function
+ * hif_ioctl
+ * Description
+ * IO Control for HIF driver.
+ * A series of HIF control code is defined for extension usage. Refer to HIF_IOCTL_CODE.
+ * Parameters
+ * handle : [IN] HIF handle. Retrieved from hif_open().
+ * code : [IN] HIF control code. Refer to HIF_IOCTL_CODE.
+ * pParam : [IN/OUT] Parameter for HIF IO Control. The definition depends on the specified control code. Refer to HIF_IOCTL_CODE.
+ * Returns
+ * Return a HIF result code.
+ * The return value is HIF_RESULT_NOT_SUPPORTED if the current platform does not support the sepcific control code.
+ * Example
+ * <code>
+ * HIF_HANDLE handle;
+ * HIF_CONFIG_T config;
+ * handle = hif_open(0);
+ * hif_ioctl(handle, HIF_IOCTL_GET_PARAM, &config);
+ * hif_close(handle);
+ * </code>
+ *****************************************************************************/
+HIF_RESULT hif_ioctl(HIF_HANDLE handle, HIF_IOCTL_CODE code, void* pParam);
+
+#endif
+
+#endif
diff --git a/mcu/interface/driver/peripheral/irda_sw.h b/mcu/interface/driver/peripheral/irda_sw.h
new file mode 100644
index 0000000..2905c0d
--- /dev/null
+++ b/mcu/interface/driver/peripheral/irda_sw.h
@@ -0,0 +1,75 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * irda_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for irda driver and customization.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _IRDA_SW_H
+#define _IRDA_SW_H
+
+/*Customizae IRDA*/
+typedef struct {
+ void (*irda_switch_to_sir)(void);
+ void (*irda_switch_to_mir)(void);
+ void (*irda_switch_to_fir)(void);
+}irda_customize_function_struct;
+
+#endif
+
+
diff --git a/mcu/interface/driver/peripheral/kbd_table.h b/mcu/interface/driver/peripheral/kbd_table.h
new file mode 100644
index 0000000..9a85b61
--- /dev/null
+++ b/mcu/interface/driver/peripheral/kbd_table.h
@@ -0,0 +1,198 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * kbd_table.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is to define kaypad definition
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _KBD_TABLE_H
+#define _KBD_TABLE_H
+
+
+ #define DEVICE_KEY_0 0
+ #define DEVICE_KEY_1 1
+ #define DEVICE_KEY_2 2
+ #define DEVICE_KEY_3 3
+ #define DEVICE_KEY_4 4
+ #define DEVICE_KEY_5 5
+ #define DEVICE_KEY_6 6
+ #define DEVICE_KEY_7 7
+ #define DEVICE_KEY_8 8
+ #define DEVICE_KEY_9 9
+ #define DEVICE_KEY_STAR 10
+ #define DEVICE_KEY_HASH 11
+ #define DEVICE_KEY_VOL_UP 12
+ #define DEVICE_KEY_VOL_DOWN 13
+ #define DEVICE_KEY_UP 14
+ #define DEVICE_KEY_DOWN 15
+ #define DEVICE_KEY_LEFT 16
+ #define DEVICE_KEY_RIGHT 17
+ #define DEVICE_KEY_MENU 18/*WAP, IP*/
+ #define DEVICE_KEY_FUNCTION 19/*vol_c*//*Camera*/
+ #define DEVICE_KEY_SK_LEFT 20
+ #define DEVICE_KEY_SK_RIGHT 21
+ #define DEVICE_KEY_SEND 22
+ #define DEVICE_KEY_END 23
+ #define DEVICE_KEY_POWER 24
+ #define DEVICE_KEY_CLEAR 25/*soft_c*/
+ #define DEVICE_KEY_EXT_FUNC1 26/*for "go to xxx AP(ex, Calendar) shortcut"*/
+ #define DEVICE_KEY_EXT_FUNC2 27/*for "go to xxx AP(ex, Calendar) shortcut"*/
+ #define DEVICE_KEY_MP3_PLAY_STOP 28
+ #define DEVICE_KEY_MP3_FWD 29
+ #define DEVICE_KEY_MP3_BACK 30
+ #define DEVICE_KEY_EXT_A 31
+ #define DEVICE_KEY_EXT_B 32
+ #define DEVICE_KEY_A 33
+ #define DEVICE_KEY_B 34
+ #define DEVICE_KEY_C 35
+ #define DEVICE_KEY_D 36
+ #define DEVICE_KEY_E 37
+ #define DEVICE_KEY_F 38
+ #define DEVICE_KEY_G 39
+ #define DEVICE_KEY_H 40
+ #define DEVICE_KEY_I 41
+ #define DEVICE_KEY_J 42
+ #define DEVICE_KEY_K 43
+ #define DEVICE_KEY_L 44
+ #define DEVICE_KEY_M 45
+ #define DEVICE_KEY_N 46
+ #define DEVICE_KEY_O 47
+ #define DEVICE_KEY_P 48
+ #define DEVICE_KEY_Q 49
+ #define DEVICE_KEY_R 50
+ #define DEVICE_KEY_S 51
+ #define DEVICE_KEY_T 52
+ #define DEVICE_KEY_U 53
+ #define DEVICE_KEY_V 54
+ #define DEVICE_KEY_W 55
+ #define DEVICE_KEY_X 56
+ #define DEVICE_KEY_Y 57
+ #define DEVICE_KEY_Z 58
+ #define DEVICE_KEY_ENTER 59
+ #define DEVICE_KEY_SPACE 60
+ #define DEVICE_KEY_TAB 61
+ #define DEVICE_KEY_DEL 62
+ #define DEVICE_KEY_ALT 63
+ #define DEVICE_KEY_CTRL 64
+ #define DEVICE_KEY_WIN 65
+ #define DEVICE_KEY_SHIFT 66
+ #define DEVICE_KEY_QUESTION 67
+ #define DEVICE_KEY_PERIOD 68 /* . */
+ #define DEVICE_KEY_COMMA 69 /* , */
+ #define DEVICE_KEY_EXCLAMATION 70 /* ! */
+ #define DEVICE_KEY_APOSTROPHE 71 /* ' */
+ #define DEVICE_KEY_AT 72 /* @ */
+ #define DEVICE_KEY_SEND2 73
+
+ //below keys are define for qwerty
+ #define DEVICE_KEY_BACKQUOTE 74 /* ` */
+ #define DEVICE_KEY_DASH 75 /* - */
+ #define DEVICE_KEY_EQUAL 76 /* = */
+ #define DEVICE_KEY_BACKSPACE 77 /* <- */
+ #define DEVICE_KEY_OPEN_PARENS 78 /* ( */
+ #define DEVICE_KEY_CLOSE_PARENS 79 /* ) */
+ #define DEVICE_KEY_OPEN_SQUARE 80 /* [ */
+ #define DEVICE_KEY_CLOSE_SQUARE 81 /* ] */
+ #define DEVICE_KEY_OPEN_BRACE 82 /* { */
+ #define DEVICE_KEY_CLOSE_BRACE 83 /* } */
+ #define DEVICE_KEY_BACKSLASH 84 /* \ */
+ #define DEVICE_KEY_SEMICOLON 85 /* ; */
+ #define DEVICE_KEY_SLASH 86 /* / */
+ #define DEVICE_KEY_DOLLAR 87 /* $ */
+ #define DEVICE_KEY_PERCENT 88 /* % */
+ #define DEVICE_KEY_CARET 89 /* ^ */
+ #define DEVICE_KEY_AND 90 /* & */
+ #define DEVICE_KEY_QUOTE 91 /* " */
+ #define DEVICE_KEY_PLUS 92 /* + */
+ #define DEVICE_KEY_LESS_THAN 93 /* < */
+ #define DEVICE_KEY_GREAT_THAN 94 /* > */
+ #define DEVICE_KEY_UNDERSCORE 95 /* _ */
+ #define DEVICE_KEY_PIPE 96 /* | */
+ #define DEVICE_KEY_TILDE 97 /* ~ */
+ #define DEVICE_KEY_CAPS_LOCK 98
+ #define DEVICE_KEY_NUM_LOCK 99
+
+ #define DEVICE_KEY_FN 100
+ #define DEVICE_KEY_SYMBOL 101
+ #define DEVICE_KEY_EMAIL 102
+ #define DEVICE_KEY_MESSAGE 103
+ #define DEVICE_KEY_CAMERA 104
+ #define DEVICE_KEY_ESC 105
+ #define DEVICE_KEY_QWERTY_MENU 106
+ #define DEVICE_KEY_OK 107
+
+ #define DEVICE_KEY_F1 111
+ #define DEVICE_KEY_F2 112
+ #define DEVICE_KEY_F3 113
+ #define DEVICE_KEY_F4 114
+ #define DEVICE_KEY_F5 115
+ #define DEVICE_KEY_F6 116
+ #define DEVICE_KEY_F7 117
+ #define DEVICE_KEY_F8 118
+ #define DEVICE_KEY_F9 119
+ #define DEVICE_KEY_F10 120
+ #define DEVICE_KEY_F11 121
+ #define DEVICE_KEY_F12 122
+ #define DEVICE_KEY_BACK 123
+ #define DEVICE_KEY_HOME 124
+ #define MAX_DEVICE_KEYS 125
+
+
+ #define DEVICE_KEY_NONE 0xFE
+
+#endif
+
diff --git a/mcu/interface/driver/peripheral/keypad_hw.h b/mcu/interface/driver/peripheral/keypad_hw.h
new file mode 100644
index 0000000..c592225
--- /dev/null
+++ b/mcu/interface/driver/peripheral/keypad_hw.h
@@ -0,0 +1,264 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * keypad_hw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for keypad driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef KEYPAD_HW_H
+#define KEYPAD_HW_H
+#include "drv_features.h"
+#include "reg_base.h"
+#if defined(DRV_KBD_32KEYS_EQ_BELOW) || defined(FPGA)
+#ifndef DRV_KP_OFF
+ #define KP_STS (KP_base+0x00)
+ #define KP_LOW_KEY (KP_base+0x04)
+ #define KP_HI_KEY (KP_base+0x08)
+ #define KP_DEBOUNCE (KP_base+0x0C)
+ #define KP_SCAN (KP_base+0x10)
+#endif // DRV_KP_OFF
+
+ //kp_sts
+ #define KP_STS_KEYPRESS 0x0001
+ #define KP_STS_IDLE 0x0000
+ #define KP_STS_MASK 0x0001
+
+ //KP_LOW_KEY
+ #define KP_LOW_KEY_MASK 0xffff
+
+ //KP_HI_KEY
+ #define KP_HI_KEY_MASK 0x01ff
+
+ //KP_DEBOUNCE
+ #define KP_DEBOUNCE_TIME 0x0400
+
+ //KP_SCAN
+ #define KP_SCAN_4KHZ 0x0007
+#else /*DRV_KBD_32KEYS_EQ_BELOW,FPGA*/
+
+#ifndef DRV_KP_OFF
+ #define KP_STS (KP_base+0x00)
+ #define KP_LOW_KEY (KP_base+0x04)
+ #define KP_MID_KEY (KP_base+0x08)
+
+#if defined(DRV_KBD_32KEYS_ABOVE)
+ #define KP_HI_KEY (KP_base+0x0c)
+ #define KP_DEBOUNCE (KP_base+0x10)
+#elif defined(DRV_KBD_48KEYS_ABOVE)
+ #define KP_MID1_KEY (KP_base+0x0c)
+ #define KP_HI_KEY (KP_base+0x10)
+ #define KP_DEBOUNCE (KP_base+0x18)
+
+ #define KP_MID1_KEY_MASK 0xffff
+#elif defined(DRV_KBD_64KEYS_ABOVE)
+ #define KP_MID1_KEY (KP_base+0x0c)
+ #define KP_MID2_KEY (KP_base+0x10)
+ #define KP_HI_KEY (KP_base+0x14)
+ #define KP_DEBOUNCE (KP_base+0x18)
+
+ #define KP_MID1_KEY_MASK 0xffff
+ #define KP_MID2_KEY_MASK 0xffff
+#endif /*DRV_KBD_32KEYS_ABOVE*/
+#endif // DRV_KP_OFF
+
+ #define KP_STS_KEYPRESS 0x0001
+ #define KP_STS_IDLE 0x0000
+ #define KP_STS_MASK 0x0001
+
+ #define KP_LOW_KEY_MASK 0xffff
+ #define KP_MID_KEY_MASK 0xffff
+
+ #define KP_DEBOUNCE_TIME 0x0200
+#endif /*DRV_KBD_32KEYS_EQ_BELOW,FPGA*/
+
+#if defined(DRV_KBD_36_KEYS)
+ #define KP_HI_KEY_MASK 0x00ff
+#elif defined(DRV_KBD_42_KEYS)
+ #define KP_HI_KEY_MASK 0x07ff
+#elif defined(DRV_KBD_35_KEYS)
+ #define KP_HI_KEY_MASK 0x0007
+#elif defined(DRV_KBD_54_KEYS)
+ #define KP_HI_KEY_MASK 0x003F
+#elif defined(DRV_KBD_72_KEYS)
+ #define KP_HI_KEY_MASK 0x00ff
+#endif
+#endif /*KEYPAD_HW_H*/
+
+
diff --git a/mcu/interface/driver/peripheral/keypad_sw.h b/mcu/interface/driver/peripheral/keypad_sw.h
new file mode 100644
index 0000000..fd9ed2e
--- /dev/null
+++ b/mcu/interface/driver/peripheral/keypad_sw.h
@@ -0,0 +1,548 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * keypad_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for keypad driver and adaption.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef _KEYPAD_SW_H
+#define _KEYPAD_SW_H
+
+#include "intrCtrl.h"
+#include "drv_features_kbd.h"
+#include "drv_comm.h"
+#include "kal_general_types.h"
+#include "kal_public_defs.h"
+#include "kal_public_api.h"
+
+
+#if defined(DRV_KBD_25_KEYS) || defined(FPGA)
+ #define kbd_allkeys 25
+ #define KBD_ROW 5
+ #define KBD_COLUMN_MASK 0x1F //5 bits mask
+ #define KBD_COLUMN 5
+#elif defined(DRV_KBD_36_KEYS)
+ #define kbd_allkeys 36
+ #define KBD_ROW 6
+ #define KBD_COLUMN_MASK 0x3F //6 bits mask
+ #define KBD_COLUMN 6
+#elif defined(DRV_KBD_42_KEYS)
+ #define kbd_allkeys 42
+ #define KBD_ROW 6
+ #define KBD_COLUMN_MASK 0x3F //6 bits mask
+ #define KBD_COLUMN 7
+#elif defined(DRV_KBD_35_KEYS)
+ #define kbd_allkeys 35
+ #define KBD_ROW 5
+ #define KBD_COLUMN_MASK 0x1F //5 bits mask
+ #define KBD_COLUMN 7
+#elif defined(DRV_KBD_54_KEYS)
+ #define kbd_allkeys 54
+ #define KBD_ROW 6
+ #define KBD_COLUMN_MASK 0x3F //6 bits mask
+ #define KBD_COLUMN 9
+#elif defined(DRV_KBD_63_KEYS)
+ #define kbd_allkeys 63
+ #define KBD_ROW 7
+ #define KBD_COLUMN_MASK 0x3F //6 bits mask
+ #define KBD_COLUMN 9
+#elif defined(DRV_KBD_72_KEYS)
+ #define kbd_allkeys 72
+ #define KBD_ROW 8
+ #define KBD_COLUMN_MASK 0xFF //8 bits mask
+ #define KBD_COLUMN 9
+#elif defined(DRV_KBD_NOT_EXIST)
+ #define kbd_allkeys 1
+ #define KBD_ROW 1
+ #define KBD_COLUMN_MASK 0x1 //1 bits mask
+ #define KBD_COLUMN 1
+#endif /*DRV_KBD_25_KEYS,FPGA*/
+
+
+/*keypad*/
+typedef enum {
+ kbd_onekey_press=0,
+ kbd_onekey_release,
+#ifdef TWO_KEY_ENABLE
+ kbd_twokey_press,
+ kbd_twokey_release,
+#endif /*TWO_KEY_ENABLE*/
+ kbd_onekey_longpress,
+ kbd_onekey_repeated,
+ kbd_onekey_fullpress,
+ kbd_twokey_detection_enable,
+ kbd_threekey_detection_enable,
+ kbd_multikey_detection_disable
+} kbd_event;
+
+#define kbd_buffer_size 32
+
+
+typedef struct
+{
+ kbd_event Keyevent;
+#ifdef TWO_KEY_ENABLE
+ kal_uint8 Keydata[2];
+#else /*!TWO_KEY_ENABLE*/
+ kal_uint8 Keydata[1];
+#endif /*TWO_KEY_ENABLE*/
+#if defined(__TC01__)
+ kal_uint32 keytimestamp;
+#endif
+} kbd_data;
+
+
+typedef struct
+{
+ kbd_data kbd_data_buffer[kbd_buffer_size];
+ kal_uint8 kbd_data_buffer_rindex;
+ kal_uint8 kbd_data_buffer_windex;
+} kbd_buffer_struct;
+
+/*Customizae Keypad*/
+typedef struct {
+ /*keypad mapping*/
+#if defined(DRV_KBD_DRVTOOL_EXTEND_72_KEYS)
+ kal_uint8 keypad[72];//kbd_allkeys+KBD_COLUMN*2]; //reserve one GND row and GPO row.
+#else
+ kal_uint8 keypad[kbd_allkeys];
+#endif//#if defined(DRV_KBD_DRVTOOL_EXTEND_72_KEYS)
+#if defined(__EXTEND_QWERTY_KEYPAD__)
+ kal_uint16 kbd_extend_row_GPO; //extend row use which GPO
+#endif //#if defined(__EXTEND_QWERTY_KEYPAD__)
+ /*power on period*/
+ kal_uint32 Custom_Keypress_Period;
+ /*power key position*/
+ kal_uint8 powerkey_position;
+} keypad_struct;
+
+typedef struct {
+ const keypad_struct * (*keypad_Get_Data)(void);
+ #ifdef __KBD_2STEP_KEY_SUPPORT__
+ kal_bool (*keypad_is_fullpress)(kal_uint8 key);
+ kal_bool (*keypad_check_fullpress)(void);
+ #endif
+}keypad_customize_function_struct;
+
+/*keypad*/
+typedef enum {
+ low_key=0,
+#if defined(DRV_KBD_32KEYS_ABOVE)
+ medium_key,
+#elif defined(DRV_KBD_48KEYS_ABOVE)
+ medium_key,
+ medium_key1,
+#elif defined(DRV_KBD_64KEYS_ABOVE)
+ medium_key,
+ medium_key1,
+ medium_key2,
+#endif
+ high_key
+
+} kbd_type;
+
+
+
+/*
+extern void Kbd_Init(void);
+extern void keypad_customize_init(void);
+
+kal_bool kbd_key_det_mode_switch(kbd_key_det_mode mode);
+ kal_bool kbd_IsKeyButtonSupported(kal_uint8 key);
+
+extern kal_bool PowerKey_Pressed(void);
+extern kal_bool kbd_is_mutiple_key(kal_uint8 key);
+extern kal_bool kbd_IsKeyPressed(kal_uint8 key);
+
+extern kal_uint32 Kbd_GetKeyEventCount(void);
+extern kal_bool Kbd_GetKeyData(kbd_data *keydata);
+extern kal_bool Kbd_PeekBuffer(kbd_data *keydata, kal_bool specify_read,
+ kal_uint32 read_pointer,kal_uint32* current_read_pointer);
+extern kal_uint32 kbd_PutKeyData(kal_uint8 key);
+
+extern void Kbd_SetLongPressTime(kal_uint32 ticks);
+extern void Kbd_SetRepeatTime(kal_uint32 ticks);
+*/
+
+#endif
+
diff --git a/mcu/interface/driver/peripheral/lpwr.h b/mcu/interface/driver/peripheral/lpwr.h
new file mode 100644
index 0000000..5d67a71
--- /dev/null
+++ b/mcu/interface/driver/peripheral/lpwr.h
@@ -0,0 +1,213 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * lpwr.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for low power control
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef __LPWR_H__
+#define __LPWR_H__
+
+#include "kal_general_types.h"
+#include "drv_comm.h"
+#include "drvpdn.h"
+
+#define MAIN_MAX_MODULE 32
+#define SUB_MAX_MODULE 32
+
+typedef enum {
+ LPWR_DRV0_MODULE_GROUP=0,
+ LPWR_DRV1_MODULE_GROUP,
+ LPWR_MM_MODULE_GROUP,
+ LPWR_MAX_MODULE_GROUP,
+ LPWR_NULL_MODULE_GROUP = 0xfe
+} LPWR_MODULE_GROUP;
+
+typedef struct {
+ DEVICE_ID_ENUM module_id;
+ kal_uint8 lpwr_main_sm_handle;
+ kal_uint32 lpwr_sub_glb_hanlde; //central handle to maintain sub module
+ kal_uint32 lpwr_sub_sleepDisable;
+ void (*pdn_enable_ctrl_callback)(void *parameter);
+ void (*pdn_disable_ctrl_callback)(void *parameter);
+} LPWR_MAIN_STRUCT;
+
+typedef struct {
+ LPWR_MODULE_GROUP group_id;
+ kal_uint8 lpwr_group_sm_handle; //from l1 sm module
+ kal_uint8 lpwr_main_handle_cnt; //central handle to maintain main module
+ kal_uint32 lpwr_main_sleepDisable;
+ LPWR_MAIN_STRUCT main_info[MAIN_MAX_MODULE];
+} LPWR_INFO_STRUCT;
+
+typedef struct
+{
+ DEVICE_ID_ENUM id;
+ LPWR_MODULE_GROUP group;
+} LPWR_GROUP_MAP_STRUCT;
+
+typedef struct
+{
+ LPWR_MODULE_GROUP group_id;
+ kal_uint8 main_handle;
+ DEVICE_ID_ENUM module_id;
+} LPWR_STRUCT;
+
+#if defined (__OLD_PDN_ARCH__)
+#if defined(__NEW_DRVPDN_FUNCTION__)
+ #define DRVPDN_ENABLE2(addr,code,pdn_id) \
+ DRVPDN_Enable2(addr,code,pdn_id)
+ #define DRVPDN_DISABLE2(addr,code,pdn_id) \
+ DRVPDN_Disable2(addr,code,pdn_id)
+#else
+
+ #define DRVPDN_ENABLE2(addr,code,pdn_id) \
+ DRVPDN_Enable(addr,code,pdn_id)
+ #define DRVPDN_DISABLE2(addr,code,pdn_id) \
+ DRVPDN_Disable(addr,code,pdn_id)
+#endif
+#else //defined (__OLD_PDN_ARCH__)
+ #define DRVPDN_ENABLE2(pdn_id) \
+ DRVPDN_Enable2(pdn_id)
+ #define DRVPDN_DISABLE2(pdn_id) \
+ DRVPDN_Disable2(pdn_id)
+#endif //defined (__OLD_PDN_ARCH__)
+// MoDIS parser skip start
+/*Common module*/
+extern void lpwr_init(void);
+extern void lpwr_module_open(LPWR_STRUCT *lpwr_handle,
+ DEVICE_ID_ENUM module_id,
+ void (*pdn_enable_ctrl_callback)(void *parameter),
+ void (*pdn_disable_ctrl_callback)(void *parameter)
+ );
+/*Main module*/
+extern void lpwr_main_disable(LPWR_STRUCT *lpwr_handle,
+ void *parameter);
+extern void lpwr_main_enable(LPWR_STRUCT *lpwr_handle,
+ void *parameter);
+extern void lpwr_main_fast_disable(LPWR_STRUCT *lpwr_handle);
+extern void lpwr_main_fast_enable(LPWR_STRUCT *lpwr_handle);
+extern void lpwr_main_fast_disable2(LPWR_STRUCT *lpwr_handle,
+ void *parameter);
+extern void lpwr_main_fast_enable2(LPWR_STRUCT *lpwr_handle,
+ void *parameter);
+/*Sub module*/
+extern kal_uint8 lpwr_get_sub_handle(LPWR_STRUCT *lpwr_handle);
+extern void lpwr_free_sub_handle(LPWR_STRUCT *lpwr_handle, kal_uint8 sub_handle);
+extern void lpwr_sub_disable(LPWR_STRUCT *lpwr_handle,
+ kal_uint8 sub_handle,
+ void (*pdn_disable_ctrl_callback)(void *parameter),
+ void *parameter);
+extern void lpwr_sub_enable(LPWR_STRUCT *lpwr_handle,
+ kal_uint8 sub_handle,
+ void (*pdn_enable_ctrl_callback)(void *parameter),
+ void *parameter);
+#if defined (__OLD_PDN_ARCH__)
+#if defined(__NEW_DRVPDN_FUNCTION__)
+extern void DRVPDN_Enable2(kal_uint32 addr,kal_uint16 code,PDN_DEVICE handle);
+extern void DRVPDN_Disable2(kal_uint32 addr,kal_uint16 code,PDN_DEVICE hanlde);
+#endif
+#else
+ extern void DRVPDN_Enable2(PDN_DEVICE handle);
+ extern void DRVPDN_Disable2(PDN_DEVICE hanlde);
+#endif
+// MoDIS parser skip end
+#endif
+
diff --git a/mcu/interface/driver/peripheral/motion_sensor.h b/mcu/interface/driver/peripheral/motion_sensor.h
new file mode 100644
index 0000000..bcc8151
--- /dev/null
+++ b/mcu/interface/driver/peripheral/motion_sensor.h
@@ -0,0 +1,283 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * motion_sensor.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module is for motion sensor driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef _MOTIONSENSOR_H
+#define _MOTIONSENSOR_H
+
+#define SIN_INTERVAL_NUM 91
+#define SIN_0 0
+#define SIN_1 9
+#define SIN_2 18
+#define SIN_3 27
+#define SIN_4 36
+#define SIN_5 45
+#define SIN_6 53
+#define SIN_7 62
+#define SIN_8 71
+#define SIN_9 80
+#define SIN_10 89
+#define SIN_11 98
+#define SIN_12 106
+#define SIN_13 115
+#define SIN_14 124
+#define SIN_15 132
+#define SIN_16 141
+#define SIN_17 150
+#define SIN_18 158
+#define SIN_19 167
+#define SIN_20 175
+#define SIN_21 183
+#define SIN_22 192
+#define SIN_23 200
+#define SIN_24 208
+#define SIN_25 216
+#define SIN_26 224
+#define SIN_27 232
+#define SIN_28 240
+#define SIN_29 248
+#define SIN_30 256
+#define SIN_31 264
+#define SIN_32 271
+#define SIN_33 279
+#define SIN_34 286
+#define SIN_35 294
+#define SIN_36 301
+#define SIN_37 308
+#define SIN_38 315
+#define SIN_39 322
+#define SIN_40 329
+#define SIN_41 336
+#define SIN_42 342
+#define SIN_43 349
+#define SIN_44 356
+#define SIN_45 362
+#define SIN_46 368
+#define SIN_47 374
+#define SIN_48 380
+#define SIN_49 386
+#define SIN_50 392
+#define SIN_51 398
+#define SIN_52 403
+#define SIN_53 409
+#define SIN_54 414
+#define SIN_55 419
+#define SIN_56 424
+#define SIN_57 429
+#define SIN_58 434
+#define SIN_59 439
+#define SIN_60 443
+#define SIN_61 448
+#define SIN_62 452
+#define SIN_63 456
+#define SIN_64 460
+#define SIN_65 464
+#define SIN_66 468
+#define SIN_67 471
+#define SIN_68 475
+#define SIN_69 478
+#define SIN_70 481
+#define SIN_71 484
+#define SIN_72 487
+#define SIN_73 490
+#define SIN_74 492
+#define SIN_75 494
+#define SIN_76 497
+#define SIN_77 499
+#define SIN_78 501
+#define SIN_79 503
+#define SIN_80 504
+#define SIN_81 506
+#define SIN_82 507
+#define SIN_83 508
+#define SIN_84 509
+#define SIN_85 510
+#define SIN_86 511
+#define SIN_87 511
+#define SIN_88 512
+#define SIN_89 512
+#define SIN_90 512
+
+/* Must be a power of 2. */
+#define MOTION_SENSOR_BUFFER_SIZE 128
+
+typedef enum {
+ BUFF_EMPTY,
+ BUFF_DATA_EXIST,
+ BUFF_FULL
+} Motion_Sensor_BuffState_enum;
+
+typedef struct
+{
+ kal_int16 x_acc;
+ kal_int16 y_acc;
+ kal_int16 z_acc;
+}MotionSensorDataStruct;
+
+typedef struct
+{
+ kal_int16 x_gain;
+ kal_int16 y_gain;
+ kal_int16 z_gain;
+ kal_int16 x_offset;
+ kal_int16 y_offset;
+ kal_int16 z_offset;
+}MotionSensorCaliStruct;
+
+typedef void (*MS_DATA_FUNC)(void *parameter, Motion_Sensor_BuffState_enum state);
+typedef void (*MS_INT_CB_FUNC)(void);
+
+typedef struct
+{
+ MotionSensorCaliStruct cali;
+ MotionSensorDataStruct pre;
+ kal_uint8 sample_period;
+ kal_uint8 gpt_handle;
+ kal_timerid motionsensor_timerid;
+ kal_uint32 acc_offset;
+ kal_uint32 low_g_level;
+ kal_uint32 high_g_level;
+ kal_uint32 low_g_debounce;
+ kal_uint32 high_g_debounce;
+ MS_DATA_FUNC cb_func;
+ MS_INT_CB_FUNC low_g_cb;
+ MS_INT_CB_FUNC high_g_cb;
+ void *para;
+}MotionSensorStruct;
+
+typedef struct
+{
+ MotionSensorDataStruct motion_sensor_data[MOTION_SENSOR_BUFFER_SIZE];
+ kal_uint16 motion_sensor_rindex;
+ kal_uint16 motion_sensor_windex;
+}MotionSensorBufferStruct;
+
+/*customization part*/
+typedef struct {
+ /*ADC*/
+ kal_uint16 x_0g_adc;
+ kal_uint16 x_1g_adc;
+ kal_uint16 x_minus1g_adc;
+ kal_uint16 y_0g_adc;
+ kal_uint16 y_1g_adc;
+ kal_uint16 y_minus1g_adc;
+ kal_uint16 z_0g_adc;
+ kal_uint16 z_1g_adc;
+ kal_uint16 z_minus1g_adc;
+
+ kal_bool int_support;
+ kal_uint8 int_level;
+ kal_uint8 int_chan;
+} MotionSensor_custom_data_struct;
+
+typedef struct {
+ MotionSensor_custom_data_struct * (*ms_get_data)(void);
+ void (*ms_read_adc)(kal_uint16 *x, kal_uint16 *y, kal_uint16 *z);
+ void (*ms_custom_init)(void);
+ void (*ms_power_up)(void);
+ void (*ms_power_down)(void);
+ /*read interrupt*/
+ void (*ms_read_int_status)(kal_bool *low_g, kal_bool *high_g);
+ /*clear interrupt*/
+ void (*ms_clear_int_status)(void);
+ void (*ms_configure_low_g)(kal_uint32 debounce, kal_uint32 threshold);
+ void (*ms_configure_high_g)(kal_uint32 debounce, kal_uint32 threshold);
+}MotionSensor_customize_function_struct;
+
+/*For MMI */
+extern void motion_sensor_complete_cali(void);
+extern void motion_sensor_cancel_cali(void);
+extern void motion_sensor_start_cali(void);
+extern void motion_sensor_read_cali(MotionSensorCaliStruct *cali);
+extern void motion_sensor_set_cali(MotionSensorCaliStruct cali);
+extern kal_bool motion_sensor_power(kal_bool enable);
+extern void motion_sensor_conf_sample_period(kal_uint32 period);
+extern void motion_sensor_flush_buff(void);
+extern void motion_sensor_cb_registration(MS_DATA_FUNC cb_fun, void *para);
+extern void motion_sensor_sample(kal_bool enable);
+extern void motion_sensor_conf_filter(kal_uint32 acc_offset);
+extern kal_bool motion_sensor_get_data(MotionSensorDataStruct *ms_data);
+extern void motion_sensor_int_cb_registration(MS_INT_CB_FUNC low_g_cb_fun, MS_INT_CB_FUNC high_g_cb_fun);
+extern void motion_sensor_int_config(kal_uint32 low_g_level, kal_uint32 high_g_level,
+ kal_uint32 low_g_debounce, kal_uint32 high_g_debounce);
+extern void motion_sensor_int_enable(kal_bool enable);
+
+// MoDIS parser skip start
+// Private APIs
+/*For driver */
+extern void motion_sensor_eint_hisr(void);
+extern kal_bool motion_sensor_filter(MotionSensorDataStruct data);
+extern void motion_sensor_sample_cb(void *parameter);
+extern void motion_sensor_check_cali(kal_int16 x, kal_int16 y, kal_int16 z);
+extern void motion_sensor_init(void);
+extern void motion_sensor_get_acc(MotionSensorDataStruct *acc_data,
+ kal_uint16 x_adc, kal_uint16 y_adc, kal_uint16 z_adc);
+extern void motion_sensor_sample_cb(void *parameter);
+extern void motion_sensor_reset(void);
+#ifdef __MOTION_SENSOR_TILT_SUPPORT__
+extern void motion_sensor_get_tilt(kal_uint16 x, kal_uint16 y, kal_uint16 z);
+extern kal_uint16 motion_sensor_get_angle(kal_uint16 value);
+#endif
+
+// MoDIS parser skip end
+
+#endif
+
diff --git a/mcu/interface/driver/peripheral/motion_sensor_buff.h b/mcu/interface/driver/peripheral/motion_sensor_buff.h
new file mode 100644
index 0000000..5ab4d6d
--- /dev/null
+++ b/mcu/interface/driver/peripheral/motion_sensor_buff.h
@@ -0,0 +1,116 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * motion_sensor_buff.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This Module is for motion sensor driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef MOTION_SENSOR_BUFF_H
+#define MOTION_SENSOR_BUFF_H
+
+#define ms_get_buf_roomleft(_left) \
+{\
+ if ( motion_sensor_buff.motion_sensor_rindex <= motion_sensor_buff.motion_sensor_windex ) \
+ {\
+ _left = MOTION_SENSOR_BUFFER_SIZE - motion_sensor_buff.motion_sensor_windex + motion_sensor_buff.motion_sensor_rindex - 1;\
+ }\
+ else\
+ {\
+ _left = motion_sensor_buff.motion_sensor_rindex - motion_sensor_buff.motion_sensor_windex - 1;\
+ }\
+}
+#define ms_get_buf_avail(_left) \
+{\
+ if ( motion_sensor_buff.motion_sensor_windex >= motion_sensor_buff.motion_sensor_rindex ) \
+ {\
+ _left =motion_sensor_buff.motion_sensor_windex - motion_sensor_buff.motion_sensor_rindex;\
+ }\
+ else\
+ {\
+ _left = MOTION_SENSOR_BUFFER_SIZE - motion_sensor_buff.motion_sensor_rindex + motion_sensor_buff.motion_sensor_windex;\
+ }\
+}
+#define motion_push_data_to_buffer(_data) \
+{\
+ kal_uint16 room=0;\
+ ms_get_buf_roomleft(room);\
+ ASSERT(room!=0);\
+ motion_sensor_buff.motion_sensor_data[motion_sensor_buff.motion_sensor_windex]= _data;\
+ motion_sensor_buff.motion_sensor_windex++;\
+ motion_sensor_buff.motion_sensor_windex &= (MOTION_SENSOR_BUFFER_SIZE-1);\
+ if(room==1)\
+ motion_sensor_data.cb_func(motion_sensor_data.para, BUFF_FULL);\
+ else\
+ motion_sensor_data.cb_func(motion_sensor_data.para, BUFF_DATA_EXIST);\
+}
+#define motion_pop_data_from_buffer(_data) \
+{\
+ if(motion_sensor_buff.motion_sensor_rindex==motion_sensor_buff.motion_sensor_windex)\
+ ASSERT(0);\
+ (_data) = motion_sensor_buff.motion_sensor_data[motion_sensor_buff.motion_sensor_rindex];\
+ motion_sensor_buff.motion_sensor_rindex++;\
+ motion_sensor_buff.motion_sensor_rindex &= (MOTION_SENSOR_BUFFER_SIZE-1);\
+}
+
+
+#define motion_flush_data_buffer() \
+{\
+ motion_sensor_buff.motion_sensor_rindex=0;\
+ motion_sensor_buff.motion_sensor_windex=0;\
+}
+
+#endif
diff --git a/mcu/interface/driver/peripheral/pmic6318_sw.h b/mcu/interface/driver/peripheral/pmic6318_sw.h
new file mode 100644
index 0000000..1db56d9
--- /dev/null
+++ b/mcu/interface/driver/peripheral/pmic6318_sw.h
@@ -0,0 +1,20 @@
+/*****************************************************************************
+pmic6318_sw.h
+pmic6326_ccci_sw.h
+pmic6326_sw.h
+pmu6236_sw.h
+pmu6251_sw.h
+pmu6252_sw.h
+pmu6253_sw.h
+pmu6253el_sw.h
+pmu6255_sw.h
+pmu6276_sw.h
+pmu6573_sw.h
+pwic.h
+pmic_feature
+pmu_sw.h
+
+ are removed .
+ plz check \\glbfs14\WCP\sw_releases\Valid_Before_20110201\PMU for detail .
+
+*****************************************************************************/
diff --git a/mcu/interface/driver/peripheral/pmic_MT6236PMU_drv.h b/mcu/interface/driver/peripheral/pmic_MT6236PMU_drv.h
new file mode 100644
index 0000000..3b6f8d3
--- /dev/null
+++ b/mcu/interface/driver/peripheral/pmic_MT6236PMU_drv.h
@@ -0,0 +1,160 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * pmic_MT6236PMU_drv.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for PMU 6236
+ * The PMIC/PMU driver APIs exported for custom tool
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __PMIC_MT6236PMU_DRV_H__
+#define __PMIC_MT6236PMU_DRV_H__
+#include "kal_public_api.h"
+
+#if defined(PMIC_6236_REG_API)
+
+// VCORE
+extern void pmicMT6236PMU_VCORE_Enable(kal_bool enable);
+extern void pmicMT6236PMU_VCORE_Set_Volt(kal_uint32 volt);
+extern void pmicMT6236PMU_VCORE_Cal(kal_uint32 step);
+// VIO
+extern void pmicMT6236PMU_VIO_Enable(kal_bool enable);
+extern void pmicMT6236PMU_VIO_Set_Volt(kal_uint32 volt);
+extern void pmicMT6236PMU_VIO_Cal(kal_uint32 step);
+// VRF
+extern void pmicMT6236PMU_VRF_Enable(kal_bool enable);
+extern void pmicMT6236PMU_VRF_Set_Volt(kal_uint32 volt);
+extern void pmicMT6236PMU_VRF_Cal(kal_uint32 step);
+// VA
+extern void pmicMT6236PMU_VA_Enable(kal_bool enable);
+extern void pmicMT6236PMU_VA_Set_Volt(kal_uint32 volt);
+extern void pmicMT6236PMU_VA_Cal(kal_uint32 step);
+// VTCXO
+extern void pmicMT6236PMU_VTCXO_Enable(kal_bool enable);
+extern void pmicMT6236PMU_VTCXO_Set_Volt(kal_uint32 volt);
+extern void pmicMT6236PMU_VTCXO_Cal(kal_uint32 step);
+// VRTC
+extern void pmicMT6236PMU_VRTC_Enable(kal_bool enable);
+extern void pmicMT6236PMU_VRTC_Set_Volt(kal_uint32 volt);
+extern void pmicMT6236PMU_VRTC_Cal(kal_uint32 step);
+// VM
+extern void pmicMT6236PMU_VM_Enable(kal_bool enable);
+extern void pmicMT6236PMU_VM_Set_Volt(kal_uint32 volt);
+extern void pmicMT6236PMU_VM_Cal(kal_uint32 step);
+// VSIM
+extern void pmicMT6236PMU_VSIM_Enable(kal_bool enable);
+extern void pmicMT6236PMU_VSIM_Set_Volt(kal_uint32 volt);
+extern void pmicMT6236PMU_VSIM_Cal(kal_uint32 step);
+// VSIM2
+extern void pmicMT6236PMU_VSIM2_Enable(kal_bool enable);
+extern void pmicMT6236PMU_VSIM2_Set_Volt(kal_uint32 volt);
+extern void pmicMT6236PMU_VSIM2_Cal(kal_uint32 step);
+// VMC
+extern void pmicMT6236PMU_VMC_Enable(kal_bool enable);
+extern void pmicMT6236PMU_VMC_Set_Volt(kal_uint32 volt);
+extern void pmicMT6236PMU_VMC_Cal(kal_uint32 step);
+// VBT
+extern void pmicMT6236PMU_VBT_Enable(kal_bool enable);
+extern void pmicMT6236PMU_VBT_Set_Volt(kal_uint32 volt);
+extern void pmicMT6236PMU_VBT_Cal(kal_uint32 step);
+// VUSB
+extern void pmicMT6236PMU_VUSB_Enable(kal_bool enable);
+extern void pmicMT6236PMU_VUSB_Set_Volt(kal_uint32 volt);
+extern void pmicMT6236PMU_VUSB_Cal(kal_uint32 step);
+// VCAMD
+extern void pmicMT6236PMU_VCAMD_Enable(kal_bool enable);
+extern void pmicMT6236PMU_VCAMD_Set_Volt(kal_uint32 volt);
+extern void pmicMT6236PMU_VCAMD_Cal(kal_uint32 step);
+// VCAMA
+extern void pmicMT6236PMU_VCAMA_Enable(kal_bool enable);
+extern void pmicMT6236PMU_VCAMA_Set_Volt(kal_uint32 volt);
+extern void pmicMT6236PMU_VCAMA_Cal(kal_uint32 step);
+// VIBR
+extern void pmicMT6236PMU_VIBR_Enable(kal_bool enable);
+extern void pmicMT6236PMU_VIBR_Set_Volt(kal_uint32 volt);
+extern void pmicMT6236PMU_VIBR_Cal(kal_uint32 step);
+
+
+
+#endif // PMIC_6236_REG_API
+
+#endif // #ifndef __PMIC_MT6236PMU_DRV_H__
+
diff --git a/mcu/interface/driver/peripheral/pmic_MT6251PMUNONMP_drv.h b/mcu/interface/driver/peripheral/pmic_MT6251PMUNONMP_drv.h
new file mode 100644
index 0000000..c227ce9
--- /dev/null
+++ b/mcu/interface/driver/peripheral/pmic_MT6251PMUNONMP_drv.h
@@ -0,0 +1,85 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * pmic_MT6251PMUNONMP_drv.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for PMU 6251
+ * The PMIC/PMU driver APIs exported for custom tool
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+// This is only an adpt header file
+// To adapt the Non-MP version PMU header file
+
+#ifndef __PMIC_NONMP_DRV__INTERFACE__
+#define __PMIC_NONMP_DRV__INTERFACE__
+#endif // #ifndef __PMIC_NONMP_DRV__INTERFACE__
+
+#include "pmic_MT6251PMU_drv.h"
+
diff --git a/mcu/interface/driver/peripheral/pmic_MT6251PMU_drv.h b/mcu/interface/driver/peripheral/pmic_MT6251PMU_drv.h
new file mode 100644
index 0000000..440e3ab
--- /dev/null
+++ b/mcu/interface/driver/peripheral/pmic_MT6251PMU_drv.h
@@ -0,0 +1,153 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * pmic_MT6251PMU_drv.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for PMU 6251
+ * The PMIC/PMU driver APIs exported for custom tool
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __PMIC_MT6251PMU_DRV_H__
+#define __PMIC_MT6251PMU_DRV_H__
+#include "kal_public_api.h"
+
+#if defined(PMIC_6251_REG_API)
+
+// VRF
+extern void pmicMT6251PMU_VRF_Enable(kal_bool enable);
+extern void pmicMT6251PMU_VRF_Set_Volt(kal_uint32 volt);
+extern void pmicMT6251PMU_VRF_Cal(kal_uint32 step);
+extern void pmicMT6251PMUNONMP_VRF_Enable(kal_bool enable);
+extern void pmicMT6251PMUNONMP_VRF_Set_Volt(kal_uint32 volt);
+extern void pmicMT6251PMUNONMP_VRF_Cal(kal_uint32 step);
+
+// VTCXO
+extern void pmicMT6251PMU_VTCXO_Enable(kal_bool enable);
+extern void pmicMT6251PMU_VTCXO_Set_Volt(kal_uint32 volt);
+extern void pmicMT6251PMU_VTCXO_Cal(kal_uint32 step);
+extern void pmicMT6251PMUNONMP_VTCXO_Enable(kal_bool enable);
+extern void pmicMT6251PMUNONMP_VTCXO_Set_Volt(kal_uint32 volt);
+extern void pmicMT6251PMUNONMP_VTCXO_Cal(kal_uint32 step);
+
+// VSF
+extern void pmicMT6251PMU_VSF_Enable(kal_bool enable);
+extern void pmicMT6251PMU_VSF_Set_Volt(kal_uint32 volt);
+extern void pmicMT6251PMU_VSF_Cal(kal_uint32 step);
+extern void pmicMT6251PMUNONMP_VSF_Enable(kal_bool enable);
+extern void pmicMT6251PMUNONMP_VSF_Set_Volt(kal_uint32 volt);
+extern void pmicMT6251PMUNONMP_VSF_Cal(kal_uint32 step);
+
+// VSIM
+extern void pmicMT6251PMU_VSIM_Enable(kal_bool enable);
+extern void pmicMT6251PMU_VSIM_Set_Volt(kal_uint32 volt);
+extern void pmicMT6251PMU_VSIM_Cal(kal_uint32 step);
+extern void pmicMT6251PMUNONMP_VSIM_Enable(kal_bool enable);
+extern void pmicMT6251PMUNONMP_VSIM_Set_Volt(kal_uint32 volt);
+extern void pmicMT6251PMUNONMP_VSIM_Cal(kal_uint32 step);
+
+// VSIM2
+extern void pmicMT6251PMU_VSIM2_Enable(kal_bool enable);
+extern void pmicMT6251PMU_VSIM2_Set_Volt(kal_uint32 volt);
+extern void pmicMT6251PMU_VSIM2_Cal(kal_uint32 step);
+extern void pmicMT6251PMUNONMP_VSIM2_Enable(kal_bool enable);
+extern void pmicMT6251PMUNONMP_VSIM2_Set_Volt(kal_uint32 volt);
+extern void pmicMT6251PMUNONMP_VSIM2_Cal(kal_uint32 step);
+
+// VIBR
+extern void pmicMT6251PMU_VIBR_Enable(kal_bool enable);
+extern void pmicMT6251PMU_VIBR_Set_Volt(kal_uint32 volt);
+extern void pmicMT6251PMU_VIBR_Cal(kal_uint32 step);
+extern void pmicMT6251PMUNONMP_VIBR_Enable(kal_bool enable);
+extern void pmicMT6251PMUNONMP_VIBR_Set_Volt(kal_uint32 volt);
+extern void pmicMT6251PMUNONMP_VIBR_Cal(kal_uint32 step);
+
+// VFM
+extern void pmicMT6251PMU_VFM_Enable(kal_bool enable);
+extern void pmicMT6251PMU_VFM_Set_Volt(kal_uint32 volt);
+extern void pmicMT6251PMU_VFM_Cal(kal_uint32 step);
+extern void pmicMT6251PMUNONMP_VIBR_Enable(kal_bool enable);
+extern void pmicMT6251PMUNONMP_VIBR_Set_Volt(kal_uint32 volt);
+extern void pmicMT6251PMUNONMP_VIBR_Cal(kal_uint32 step);
+
+#endif // PMIC_6251_REG_API
+
+#endif // #ifndef __PMIC_MT6251PMU_DRV_H__
+
diff --git a/mcu/interface/driver/peripheral/pmic_MT6255PMUNONMP_drv.h b/mcu/interface/driver/peripheral/pmic_MT6255PMUNONMP_drv.h
new file mode 100644
index 0000000..0dc1ded
--- /dev/null
+++ b/mcu/interface/driver/peripheral/pmic_MT6255PMUNONMP_drv.h
@@ -0,0 +1,88 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * pmic_MT6255PMUNONMP_drv.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for PMU 6255
+ * The PMIC/PMU driver APIs exported for custom tool
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+
+// This is only an adpt header file
+// To adapt the Non-MP version PMU header file
+#ifndef __PMIC_NONMP_DRV__INTERFACE__
+#define __PMIC_NONMP_DRV__INTERFACE__
+#endif // #ifndef __PMIC_NONMP_DRV__INTERFACE__
+
+#include "pmic_MT6255PMU_drv.h"
+
diff --git a/mcu/interface/driver/peripheral/pmic_MT6255PMU_drv.h b/mcu/interface/driver/peripheral/pmic_MT6255PMU_drv.h
new file mode 100644
index 0000000..accecb3
--- /dev/null
+++ b/mcu/interface/driver/peripheral/pmic_MT6255PMU_drv.h
@@ -0,0 +1,152 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * pmic_MT6255PMU_drv.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for PMU 6255
+ * The PMIC/PMU driver APIs exported for custom tool
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __PMIC_MT6255PMU_DRV_H__
+#define __PMIC_MT6255PMU_DRV_H__
+#include "kal_public_api.h"
+
+#if defined(PMIC_6255_REG_API)
+
+// VRF
+extern void pmicMT6255PMU_VRF_Enable(kal_bool enable);
+extern void pmicMT6255PMU_VRF_Set_Volt(kal_uint32 volt);
+extern void pmicMT6255PMU_VRF_Cal(kal_uint32 step);
+
+// VTCXO
+extern void pmicMT6255PMU_VTCXO_Enable(kal_bool enable);
+extern void pmicMT6255PMU_VTCXO_Set_Volt(kal_uint32 volt);
+extern void pmicMT6255PMU_VTCXO_Cal(kal_uint32 step);
+
+// VCAMA
+extern void pmicMT6255PMU_VCAMA_Enable(kal_bool enable);
+extern void pmicMT6255PMU_VCAMA_Set_Volt(kal_uint32 volt);
+extern void pmicMT6255PMU_VCAMA_Cal(kal_uint32 step);
+
+// VCAMD
+extern void pmicMT6255PMU_VCAMD_Enable(kal_bool enable);
+extern void pmicMT6255PMU_VCAMD_Set_Volt(kal_uint32 volt);
+extern void pmicMT6255PMU_VCAMD_Cal(kal_uint32 step);
+
+// VUSB
+extern void pmicMT6255PMU_VUSB_Enable(kal_bool enable);
+extern void pmicMT6255PMU_VUSB_Set_Volt(kal_uint32 volt);
+extern void pmicMT6255PMU_VUSB_Cal(kal_uint32 step);
+
+// VBT
+extern void pmicMT6255PMU_VBT_Enable(kal_bool enable);
+extern void pmicMT6255PMU_VBT_Set_Volt(kal_uint32 volt);
+extern void pmicMT6255PMU_VBT_Cal(kal_uint32 step);
+
+// VSIM
+extern void pmicMT6255PMU_VSIM_Enable(kal_bool enable);
+extern void pmicMT6255PMU_VSIM_Set_Volt(kal_uint32 volt);
+extern void pmicMT6255PMU_VSIM_Cal(kal_uint32 step);
+
+// VSIM2
+extern void pmicMT6255PMU_VSIM2_Enable(kal_bool enable);
+extern void pmicMT6255PMU_VSIM2_Set_Volt(kal_uint32 volt);
+extern void pmicMT6255PMU_VSIM2_Cal(kal_uint32 step);
+
+// VIBR
+extern void pmicMT6255PMU_VIBR_Enable(kal_bool enable);
+extern void pmicMT6255PMU_VIBR_Set_Volt(kal_uint32 volt);
+extern void pmicMT6255PMU_VIBR_Cal(kal_uint32 step);
+
+// VMC
+extern void pmicMT6255PMU_VMC_Enable(kal_bool enable);
+extern void pmicMT6255PMU_VMC_Set_Volt(kal_uint32 volt);
+extern void pmicMT6255PMU_VMC_Cal(kal_uint32 step);
+
+// VFM
+extern void pmicMT6255PMU_VFM_Enable(kal_bool enable);
+extern void pmicMT6255PMU_VFM_Set_Volt(kal_uint32 volt);
+extern void pmicMT6255PMU_VFM_Cal(kal_uint32 step);
+
+#endif // PMIC_6255_REG_API
+
+#endif // #ifndef __PMIC_MT6255PMU_DRV_H__
+
diff --git a/mcu/interface/driver/peripheral/pmic_MT6276MPMUNONMP_drv.h b/mcu/interface/driver/peripheral/pmic_MT6276MPMUNONMP_drv.h
new file mode 100644
index 0000000..6473422
--- /dev/null
+++ b/mcu/interface/driver/peripheral/pmic_MT6276MPMUNONMP_drv.h
@@ -0,0 +1,91 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * pmic_MT6276PMUNONMP_drv.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for PMU 6276
+ * The PMIC/PMU driver APIs exported for custom tool
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+// This is only an adpt header file
+// To adapt the Non-MP version PMU header file
+#ifndef __PMIC_NONMP_DRV__INTERFACE__
+#define __PMIC_NONMP_DRV__INTERFACE__
+#endif // #ifndef __PMIC_NONMP_DRV__INTERFACE__
+
+#include "pmic_MT6276PMU_drv.h"
+
diff --git a/mcu/interface/driver/peripheral/pmic_MT6276PMUNONMP_drv.h b/mcu/interface/driver/peripheral/pmic_MT6276PMUNONMP_drv.h
new file mode 100644
index 0000000..af2a27d
--- /dev/null
+++ b/mcu/interface/driver/peripheral/pmic_MT6276PMUNONMP_drv.h
@@ -0,0 +1,87 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * pmic_MT6276PMUNONMP_drv.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for PMU 6276
+ * The PMIC/PMU driver APIs exported for custom tool
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+// This is only an adpt header file
+// To adapt the Non-MP version PMU header file
+#ifndef __PMIC_NONMP_DRV__INTERFACE__
+#define __PMIC_NONMP_DRV__INTERFACE__
+#endif // #ifndef __PMIC_NONMP_DRV__INTERFACE__
+
+#include "pmic_MT6276PMU_drv.h"
+
diff --git a/mcu/interface/driver/peripheral/pmic_MT6276PMU_drv.h b/mcu/interface/driver/peripheral/pmic_MT6276PMU_drv.h
new file mode 100644
index 0000000..213b24c
--- /dev/null
+++ b/mcu/interface/driver/peripheral/pmic_MT6276PMU_drv.h
@@ -0,0 +1,220 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * pmic_MT6276PMU_drv.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intended for PMU 6276
+ * The PMIC/PMU driver APIs exported for custom tool
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ * removed!
+ *
+ * removed!
+ * removed!
+ *
+ *
+ *
+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+
+#ifndef __PMIC_MT6276PMU_DRV_H__
+#define __PMIC_MT6276PMU_DRV_H__
+#include "kal_public_api.h"
+
+#if defined(PMIC_6276_REG_API)
+
+
+// VRF
+extern void pmicMT6276PMU_VRF_Enable(kal_bool enable);
+extern void pmicMT6276PMU_VRF_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMU_VRF_Cal(kal_uint32 step);
+extern void pmicMT6276PMUNONMP_VRF_Enable(kal_bool enable);
+extern void pmicMT6276PMUNONMP_VRF_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMUNONMP_VRF_Cal(kal_uint32 step);
+
+// VTCXO
+extern void pmicMT6276PMU_VTCXO_Enable(kal_bool enable);
+extern void pmicMT6276PMU_VTCXO_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMU_VTCXO_Cal(kal_uint32 step);
+extern void pmicMT6276PMUNONMP_VTCXO_Enable(kal_bool enable);
+extern void pmicMT6276PMUNONMP_VTCXO_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMUNONMP_VTCXO_Cal(kal_uint32 step);
+
+// VCAMA
+extern void pmicMT6276PMU_VCAMA_Enable(kal_bool enable);
+extern void pmicMT6276PMU_VCAMA_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMU_VCAMA_Cal(kal_uint32 step);
+extern void pmicMT6276PMUNONMP_VCAMA_Enable(kal_bool enable);
+extern void pmicMT6276PMUNONMP_VCAMA_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMUNONMP_VCAMA_Cal(kal_uint32 step);
+
+// VCAMD
+extern void pmicMT6276PMU_VCAMD_Enable(kal_bool enable);
+extern void pmicMT6276PMU_VCAMD_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMU_VCAMD_Cal(kal_uint32 step);
+extern void pmicMT6276PMUNONMP_VCAMD_Enable(kal_bool enable);
+extern void pmicMT6276PMUNONMP_VCAMD_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMUNONMP_VCAMD_Cal(kal_uint32 step);
+
+// VUSB
+extern void pmicMT6276PMU_VUSB_Enable(kal_bool enable);
+extern void pmicMT6276PMU_VUSB_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMU_VUSB_Cal(kal_uint32 step);
+extern void pmicMT6276PMUNONMP_VUSB_Enable(kal_bool enable);
+extern void pmicMT6276PMUNONMP_VUSB_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMUNONMP_VUSB_Cal(kal_uint32 step);
+
+// VBT
+extern void pmicMT6276PMU_VBT_Enable(kal_bool enable);
+extern void pmicMT6276PMU_VBT_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMU_VBT_Cal(kal_uint32 step);
+extern void pmicMT6276PMUNONMP_VBT_Enable(kal_bool enable);
+extern void pmicMT6276PMUNONMP_VBT_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMUNONMP_VBT_Cal(kal_uint32 step);
+
+// VSIM
+extern void pmicMT6276PMU_VSIM_Enable(kal_bool enable);
+extern void pmicMT6276PMU_VSIM_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMU_VSIM_Cal(kal_uint32 step);
+extern void pmicMT6276PMUNONMP_VSIM_Enable(kal_bool enable);
+extern void pmicMT6276PMUNONMP_VSIM_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMUNONMP_VSIM_Cal(kal_uint32 step);
+
+// VSIM2
+extern void pmicMT6276PMU_VSIM2_Enable(kal_bool enable);
+extern void pmicMT6276PMU_VSIM2_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMU_VSIM2_Cal(kal_uint32 step);
+extern void pmicMT6276PMUNONMP_VSIM2_Enable(kal_bool enable);
+extern void pmicMT6276PMUNONMP_VSIM2_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMUNONMP_VSIM2_Cal(kal_uint32 step);
+
+// VIBR
+extern void pmicMT6276PMU_VIBR_Enable(kal_bool enable);
+extern void pmicMT6276PMU_VIBR_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMU_VIBR_Cal(kal_uint32 step);
+extern void pmicMT6276PMUNONMP_VIBR_Enable(kal_bool enable);
+extern void pmicMT6276PMUNONMP_VIBR_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMUNONMP_VIBR_Cal(kal_uint32 step);
+
+// VMC
+extern void pmicMT6276PMU_VMC_Enable(kal_bool enable);
+extern void pmicMT6276PMU_VMC_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMU_VMC_Cal(kal_uint32 step);
+extern void pmicMT6276PMUNONMP_VMC_Enable(kal_bool enable);
+extern void pmicMT6276PMUNONMP_VMC_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMUNONMP_VMC_Cal(kal_uint32 step);
+
+// VCAMA2
+extern void pmicMT6276PMU_VCAMA2_Enable(kal_bool enable);
+extern void pmicMT6276PMU_VCAMA2_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMU_VCAMA2_Cal(kal_uint32 step);
+extern void pmicMT6276PMUNONMP_VCAMA2_Enable(kal_bool enable);
+extern void pmicMT6276PMUNONMP_VCAMA2_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMUNONMP_VCAMA2_Cal(kal_uint32 step);
+
+// VCAMD2
+extern void pmicMT6276PMU_VCAMD2_Enable(kal_bool enable);
+extern void pmicMT6276PMU_VCAMD2_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMU_VCAMD2_Cal(kal_uint32 step);
+extern void pmicMT6276PMUNONMP_VCAMD2_Enable(kal_bool enable);
+extern void pmicMT6276PMUNONMP_VCAMD2_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMUNONMP_VCAMD2_Cal(kal_uint32 step);
+
+// VFM
+extern void pmicMT6276PMU_VFM_Enable(kal_bool enable);
+extern void pmicMT6276PMU_VFM_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMU_VFM_Cal(kal_uint32 step);
+extern void pmicMT6276PMUNONMP_VFM_Enable(kal_bool enable);
+extern void pmicMT6276PMUNONMP_VFM_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMUNONMP_VFM_Cal(kal_uint32 step);
+
+// VM12
+extern void pmicMT6276PMU_VM12_Enable(kal_bool enable);
+extern void pmicMT6276PMU_VM12_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMU_VM12_Cal(kal_uint32 step);
+extern void pmicMT6276PMUNONMP_VM12_Enable(kal_bool enable);
+extern void pmicMT6276PMUNONMP_VM12_Set_Volt(kal_uint32 volt);
+extern void pmicMT6276PMUNONMP_VM12_Cal(kal_uint32 step);
+
+//// VRF_1V8
+//extern void pmicMT6276PMU_VRF_1V8_Enable(kal_bool enable);
+//extern void pmicMT6276PMU_VRF_1V8_Set_Volt(kal_uint32 volt);
+//extern void pmicMT6276PMU_VRF_1V8_Cal(kal_uint32 step);
+//extern void pmicMT6276PMUNONMP_VRF_1V8_Enable(kal_bool enable);
+//extern void pmicMT6276PMUNONMP_VRF_1V8_Set_Volt(kal_uint32 volt);
+//extern void pmicMT6276PMUNONMP_VRF_1V8_Cal(kal_uint32 step);
+
+
+#endif // PMIC_6276_REG_API
+
+#endif // #ifndef __PMIC_MT6276PMU_DRV_H__
+
diff --git a/mcu/interface/driver/peripheral/pmic_features.h b/mcu/interface/driver/peripheral/pmic_features.h
new file mode 100644
index 0000000..1db56d9
--- /dev/null
+++ b/mcu/interface/driver/peripheral/pmic_features.h
@@ -0,0 +1,20 @@
+/*****************************************************************************
+pmic6318_sw.h
+pmic6326_ccci_sw.h
+pmic6326_sw.h
+pmu6236_sw.h
+pmu6251_sw.h
+pmu6252_sw.h
+pmu6253_sw.h
+pmu6253el_sw.h
+pmu6255_sw.h
+pmu6276_sw.h
+pmu6573_sw.h
+pwic.h
+pmic_feature
+pmu_sw.h
+
+ are removed .
+ plz check \\glbfs14\WCP\sw_releases\Valid_Before_20110201\PMU for detail .
+
+*****************************************************************************/
diff --git a/mcu/interface/driver/peripheral/pmif.h b/mcu/interface/driver/peripheral/pmif.h
new file mode 100644
index 0000000..67abf78
--- /dev/null
+++ b/mcu/interface/driver/peripheral/pmif.h
@@ -0,0 +1,84 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+#ifndef __PMIF_H__
+#define __PMIF_H__
+
+#include "drv_comm.h"
+#include "kal_public_defs.h"
+
+#define PMIF_CMD_REG_0 0
+#define PMIF_CMD_REG 1
+#define PMIF_CMD_EXT_REG 2
+#define PMIF_CMD_EXT_REG_LONG 3
+
+struct pmif {
+ void *base;
+ int *regs;
+ int *dbgregs;
+ void *spmimst_base;
+ int *spmimst_regs;
+ int swinf_ch_start;
+ int swinf_no;
+ int write;
+ int mstid;
+ int pmifid;
+ int (*cmd)(struct pmif *arb, unsigned int opcode);
+ int (*read_cmd)(struct pmif *arb, unsigned char opc,
+ unsigned char sid, unsigned short addr,
+ unsigned char *buf, unsigned short len);
+ int (*write_cmd)(struct pmif *arb, unsigned char opc,
+ unsigned char sid, unsigned short addr,
+ const unsigned char *buf, unsigned short len);
+ void (*pmif_enable_clk_set)(int mstid);
+ void (*pmif_force_normal_mode)(int mstid);
+ void (*pmif_enable_swinf)(int mstid, unsigned int chan_no,
+ unsigned int swinf_no);
+ void (*pmif_enable_cmdIssue)(int mstid, kal_bool en);
+ void (*pmif_enable)(int mstid);
+ int (*is_pmif_init_done)(int mstid);
+};
+
+enum {
+ PMIF_SPMI,
+ PMIF_SPI
+};
+/* start external API */
+extern struct pmif *get_pmif_controller(int inf, int mstid);
+extern int is_pmif_spmi_init_done(int mstid);
+extern int pmif_spmi_init(int mstid);
+
+#endif /*__PMIF_H__*/
diff --git a/mcu/interface/driver/peripheral/pmu6253_sw.h b/mcu/interface/driver/peripheral/pmu6253_sw.h
new file mode 100644
index 0000000..1db56d9
--- /dev/null
+++ b/mcu/interface/driver/peripheral/pmu6253_sw.h
@@ -0,0 +1,20 @@
+/*****************************************************************************
+pmic6318_sw.h
+pmic6326_ccci_sw.h
+pmic6326_sw.h
+pmu6236_sw.h
+pmu6251_sw.h
+pmu6252_sw.h
+pmu6253_sw.h
+pmu6253el_sw.h
+pmu6255_sw.h
+pmu6276_sw.h
+pmu6573_sw.h
+pwic.h
+pmic_feature
+pmu_sw.h
+
+ are removed .
+ plz check \\glbfs14\WCP\sw_releases\Valid_Before_20110201\PMU for detail .
+
+*****************************************************************************/
diff --git a/mcu/interface/driver/peripheral/pmu6253el_sw.h b/mcu/interface/driver/peripheral/pmu6253el_sw.h
new file mode 100644
index 0000000..1db56d9
--- /dev/null
+++ b/mcu/interface/driver/peripheral/pmu6253el_sw.h
@@ -0,0 +1,20 @@
+/*****************************************************************************
+pmic6318_sw.h
+pmic6326_ccci_sw.h
+pmic6326_sw.h
+pmu6236_sw.h
+pmu6251_sw.h
+pmu6252_sw.h
+pmu6253_sw.h
+pmu6253el_sw.h
+pmu6255_sw.h
+pmu6276_sw.h
+pmu6573_sw.h
+pwic.h
+pmic_feature
+pmu_sw.h
+
+ are removed .
+ plz check \\glbfs14\WCP\sw_releases\Valid_Before_20110201\PMU for detail .
+
+*****************************************************************************/
diff --git a/mcu/interface/driver/peripheral/pmu_sw.h b/mcu/interface/driver/peripheral/pmu_sw.h
new file mode 100644
index 0000000..1db56d9
--- /dev/null
+++ b/mcu/interface/driver/peripheral/pmu_sw.h
@@ -0,0 +1,20 @@
+/*****************************************************************************
+pmic6318_sw.h
+pmic6326_ccci_sw.h
+pmic6326_sw.h
+pmu6236_sw.h
+pmu6251_sw.h
+pmu6252_sw.h
+pmu6253_sw.h
+pmu6253el_sw.h
+pmu6255_sw.h
+pmu6276_sw.h
+pmu6573_sw.h
+pwic.h
+pmic_feature
+pmu_sw.h
+
+ are removed .
+ plz check \\glbfs14\WCP\sw_releases\Valid_Before_20110201\PMU for detail .
+
+*****************************************************************************/
diff --git a/mcu/interface/driver/peripheral/pwic.h b/mcu/interface/driver/peripheral/pwic.h
new file mode 100644
index 0000000..28a8303
--- /dev/null
+++ b/mcu/interface/driver/peripheral/pwic.h
@@ -0,0 +1,3 @@
+/*
+Dummy File
+*/
\ No newline at end of file
diff --git a/mcu/interface/driver/peripheral/spi_hal.h b/mcu/interface/driver/peripheral/spi_hal.h
new file mode 100644
index 0000000..fed1bdd
--- /dev/null
+++ b/mcu/interface/driver/peripheral/spi_hal.h
@@ -0,0 +1,533 @@
+
+#ifndef __SPI_DRV_HAL_H__
+/* !ignore me! */
+#define __SPI_DRV_HAL_H__
+
+#include "spi.h"
+#include "drv_features.h"
+#include "kal_general_types.h"
+
+/* !ignore me! */
+#if defined(DRV_SPI_SUPPORT) && defined(DRV_SPI_HAL)
+
+/* SPI ports number. */
+#define SPI_MAX_PORT_NUM 2
+
+/* SPI Handle.
+ SPI handle can be retrieved from spi_open(). It is used for most SPI APIs.
+*/
+typedef kal_uint32 SPI_HANDLE;
+
+/* <GROUP CallBackFunctions>
+ FUNCTION
+ SPI_CALLBACK
+ DESCRIPTION
+ SPI callback function
+ SPI callback function is called when SPI interrupt has arrived. It indicates SPI has finished the last data transfer.
+ SPI callback function is called in the context of HISR.
+*/
+typedef void (*SPI_CALLBACK)(void);
+
+/* SPI result enum.
+*/
+typedef enum
+{
+ /* Indicates no error occurs in the last operation. */
+ SPI_RESULT_OK,
+
+ /* Indicates some errors have occured in the last operation. */
+ SPI_RESULT_ERROR,
+
+ /* Indicates some errors have occured in the last operation. */
+ SPI_RESULT_INVALID_ARGUMENT,
+
+ /* Indicates the function is not supported on the current platform. */
+ SPI_RESULT_NOT_SUPPORTED
+} SPI_RESULT;
+
+/*************************************************************************************************************************************
+ * SPI IOCTL code definition.
+ * For detail description and usage of SPI control codes, please refer to <xref target="SPI HAL IOCTL Code" text="SPI IOCTL Code" />.
+ *************************************************************************************************************************************/
+typedef enum
+{
+ /****************************************************************************************************************
+ * Get the current SPI configuration parameters.
+ * For detail description and usage of this control code, please refer to <xref target="SPI_IOCTL_GET_PARAM" />.
+ ****************************************************************************************************************/
+ SPI_IOCTL_GET_PARAM,
+ /****************************************************************************************************************
+ * Get the capability of current SPI hardware.
+ * For detail description and usage of this control code, please refer to <xref target="SPI_IOCTL_QUERY_CAPABILITY" />.
+ ****************************************************************************************************************/
+ SPI_IOCTL_QUERY_CAPABILITY,
+ /*************************************************************************************************************************
+ * Query supported SPI modes.
+ * For detail description and usage of this control code, please refer to <xref target="SPI_IOCTL_QUERY_MODE_SUPPORT" />.
+ *************************************************************************************************************************/
+ SPI_IOCTL_QUERY_MODE_SUPPORT,
+ /******************************************************************************************************************
+ * Query SPI base clock.
+ * For detail description and usage of this control code, please refer to <xref target="SPI_IOCTL_QUERY_CLOCK" />.
+ ******************************************************************************************************************/
+ SPI_IOCTL_QUERY_CLOCK,
+ /***************************************************************************************************************
+ * Set and configure SPI mode.
+ * For detail description and usage of this control code, please refer to <xref target="SPI_IOCTL_SET_MODE" />.
+ ***************************************************************************************************************/
+ SPI_IOCTL_SET_MODE,
+ /***************************************************************************************************************
+ * Get SPI mode settings.
+ * For detail description and usage of this control code, please refer to <xref target="SPI_IOCTL_GET_MODE" />.
+ ***************************************************************************************************************/
+ SPI_IOCTL_GET_MODE,
+ /***************************************************************************************************************
+ * Get SPI driving current.
+ * For detail description and usage of this control code, please refer to <xref target="SPI_IOCTL_GET_DRIVING_CURRENT" />.
+ ***************************************************************************************************************/
+ SPI_IOCTL_GET_DRIVING_CURRENT,
+ /***************************************************************************************************************
+ * Set SPI driving current.
+ * For detail description and usage of this control code, please refer to <xref target="SPI_IOCTL_SET_DRIVING_CURRENT" />.
+ ***************************************************************************************************************/
+ SPI_IOCTL_SET_DRIVING_CURRENT
+} SPI_IOCTL_CODE;
+
+/* SPI mode. Including special modes provided by SPI controller.
+*/
+typedef enum
+{
+ /* Deassert mode. SPI CS pin will be pulled low and high for each byte during transmission. */
+ SPI_MODE_DEASSERT,
+ /* Pause mode. SPI CS pin is pulled low and keeps until specific amount of transfers have been finished. */
+ SPI_MODE_PAUSE,
+ /* Ultra high mode. Raise DMA priority during DMA transmission. */
+ SPI_MODE_ULTRA_HIGH,
+ /* Slow down mode. Slow down SPI DMA speed during DMA transmission. */
+ SPI_MODE_SLOW_DOWN,
+ /* Get tick delay mode. This mode is used to tuning SPI timing. */
+ SPI_MODE_GET_TICK
+} SPI_HAL_MODE;
+
+/*********************************
+ * SPI get tick delay mode enums.
+ *********************************/
+typedef enum
+{
+ /* Delay SCK for one clock. */
+ SPI_GET_TICK_DELAY1 = 1,
+ /* Delay SCK for two clocks. */
+ SPI_GET_TICK_DELAY2 = 2
+} SPI_GET_TICK_E;
+
+/* SPI transimssion bit order definition. */
+typedef enum
+{
+ /* Transfer LSB first. */
+ SPI_MSBF_LSB = 0,
+ /* Transfer MSB first. */
+ SPI_MSBF_MSB = 1
+} SPI_MSBF_E;
+
+/* SPI clock polarity definition. */
+typedef enum
+{
+ /* CPOL = 0. */
+ SPI_CPOL_B0 = 0,
+ /* CPOL = 1. */
+ SPI_CPOL_B1 = 1
+} SPI_CPOL_E;
+
+/* SPI clock format definition. */
+typedef enum
+{
+ /* CPHA = 0. */
+ SPI_CPHA_B0 = 0,
+ /* CPHA = 1. */
+ SPI_CPHA_B1 = 1
+} SPI_CPHA_E;
+
+/* SPI data transfer byte order definition. */
+typedef enum
+{
+ /* Use little endian. */
+ SPI_ENDIAN_LITTLE = 0,
+ /* Use big endian. */
+ SPI_ENDIAN_BIG = 1
+} SPI_ENDIAN_E;
+
+/************************************
+ * SPI configuration parameters.
+ *
+ * Remarks
+ * <img name="spi_timing_diagram" />
+ ************************************/
+typedef struct
+{
+ /* CS setup time. Unit in count of SPI base clock. Range(0-255).
+ The chip select setup time = (cs_setup_time+1)*CLK_PERIOD, where CLK_PERIOD is the cycle time of the clock the SPI engine adopts. */
+ kal_uint32 cs_setup_time;
+ /* CS hold time. Unit in count of SPI base clock. Range(0-255).
+ The chip select hold time = (cs_hold_time+1)*CLK_PERIOD. */
+ kal_uint32 cs_hold_time;
+ /* CS idle time. Unit in count of SPI base clock. Range(0-255).
+ The chip select idle time between consecutive transaction = (cs_idle_time+1)*CLK_PERIOD. */
+ kal_uint32 cs_idle_time;
+ /* SCK clock low time. Unit in count of SPI base clock. Range(0-255).
+ The SCK clock low time = (clk_low_time+1)*CLK_PERIOD. */
+ kal_uint32 clk_low_time;
+ /* SCK clock high time. Unit in count of SPI base clock. Range(0-255).
+ The SCK clock high time = (clk_high_time+1)*CLK_PERIOD. */
+ kal_uint32 clk_high_time;
+ /* Bit order setting for SPI output. */
+ SPI_MSBF_E tx_msbf;
+ /* Bit order setting for SPI input. */
+ SPI_MSBF_E rx_msbf;
+ /* Byte order setting for SPI output. */
+ SPI_ENDIAN_E tx_endian;
+ /* Byte order setting for SPI input. */
+ SPI_ENDIAN_E rx_endian;
+ /* SPI clock polarity. */
+ SPI_CPOL_E clk_polarity;
+ /* SPI clock format. */
+ SPI_CPHA_E clk_fmt;
+} SPI_CONFIG_PARAM_T;
+
+/* This structure is used as the parameter of SPI_IOCTL_QUERY_CAPABILITY.
+*/
+typedef struct
+{
+ /* Minimum value for cs setup time. */
+ kal_uint32 cs_setup_time_min;
+ /* Maximum value for cs setup time. */
+ kal_uint32 cs_setup_time_max;
+ /* Minimum value for cs hold time. */
+ kal_uint32 cs_hold_time_min;
+ /* Maximum value for cs hold time. */
+ kal_uint32 cs_hold_time_max;
+ /* Minimum value for cs idle time. */
+ kal_uint32 cs_idle_time_min;
+ /* Maximum value for cs idle time. */
+ kal_uint32 cs_idle_time_max;
+ /* Minimum value for clock low time. */
+ kal_uint32 clk_low_time_min;
+ /* Maximum value for clock low time. */
+ kal_uint32 clk_low_time_max;
+ /* Minimum value for clock high time. */
+ kal_uint32 clk_high_time_min;
+ /* Maximum value for clock high time. */
+ kal_uint32 clk_high_time_max;
+ /* Minimum value for transfer length. */
+ kal_uint32 transfer_length_min;
+ /* Maximum value for transfer length. */
+ kal_uint32 transfer_length_max;
+ /* Minimum value for transfer count. */
+ kal_uint32 transfer_count_min;
+ /* Maximum value for transfer count. */
+ kal_uint32 transfer_count_max;
+ /* Minimum value for slow down threshold. */
+ kal_uint32 slow_down_thresh_min;
+ /* Maximum value for slow down threshold. */
+ kal_uint32 slow_down_thresh_max;
+ /* Minimum value for ultra high threshold. */
+ kal_uint32 ultra_high_thresh_min;
+ /* Maximum value for ultra high threshold. */
+ kal_uint32 ultra_high_thresh_max;
+ /* Minimum value for driving current. */
+ kal_uint32 driving_current_min;
+ /* Maximum value for driving current. */
+ kal_uint32 driving_current_max;
+} SPI_CAPABILITY_T;
+
+/* This structure is used as the parameter of SPI_IOCTL_QUERY_MODE_SUPPORT.
+*/
+typedef struct
+{
+ /* [IN] Specify a SPI mode. */
+ SPI_HAL_MODE mode;
+ /* [OUT] Return whether the specific mode is supported. */
+ kal_bool bSupport;
+} SPI_QUERY_MODE_T;
+
+/* This structure is used as the parameter of SPI_IOCTL_QUERY_CLOCK.
+ It contains the clock frequency which is used to calculate SPI timing parameters.
+*/
+typedef struct
+{
+ /* [OUT] SPI base clock. Unit in MHz. */
+ kal_uint32 clock;
+} SPI_QUERY_CLOCK_T;
+
+/********************************************************************
+ * This structure is used as the parameter of SPI_IOCTL_SET_MODE and SPI_IOCTL_GET_MODE.
+ ********************************************************************/
+typedef struct
+{
+ /* [IN] Specify a SPI mode. */
+ SPI_HAL_MODE mode;
+ /* [IN/OUT] Specify whether the mode is enabled.
+ For SPI_IOCTL_SET_MODE, it is an input parameter.
+ For SPI_IOCTL_GET_MODE, it is an output parameter.
+ */
+ kal_bool bEnable;
+ /* [IN/OUT] The parameter for the specific mode.
+ The meaning of this parameter depends on the mode to be set/get.
+ */
+ kal_uint32 Param;
+} SPI_MODE_T;
+
+/* This structure is used as the parameter of SPI_MODE_T for SPI_MODE_SLOW_DOWN.
+ If user uses SPI_IOCTL_SET_MODE or SPI_IOCTL_GET_MODE to set/get SPI DMA slow down mode, the Param in SPI_MODE_T is a pointer to this structure.
+*/
+typedef struct
+{
+ /* This parameter decides whether to enable splitting burst one 4-beat read/write access into four single read/write accesses.*/
+ kal_bool split_burst_enable;
+ /* This parameter is a counter to configure how many time units to send one request to GMC.*/
+ kal_uint32 slow_down_thresh;
+} SPI_SLOWDOWN_PARAM_T;
+
+/* This structure is used as the parameter of SPI_IOCTL_GET_DRIVING_CURRENT and SPI_IOCTL_SET_DRIVING_CURRENT.
+*/
+typedef struct
+{
+ /* Indicates whether slew rate control is enabled. */
+ kal_bool bEnableSlewRate;
+ /* Driving current value.
+ <b> <color Red>Note: This variable just indicates the value that is set in the hardware configuration register. It does not stands fot the actual driving current.
+ Refer to related hardware spec for detail information.</b></color>
+ */
+ kal_uint32 driving_current;
+} SPI_DRIVING_CURRENT_T;
+
+/**************************************************************************************************************************************
+ * Function
+ * spi_open
+ * Description
+ * Open and get SPI handle.
+ * Parameters
+ * port : [IN] SPI port. Zero based port index.
+ * For <color Blue>MT6238</color>/<color Blue>MT6268</color>/<color Blue>MT6236</color>, only one port is supported.
+ * Returns
+ * Return a SPI handle.
+ * Example
+ * <code>
+ * SPI_HANDLE handle;
+ * handle = spi_open(0);
+ * </code>
+ **************************************************************************************************************************************/
+SPI_HANDLE spi_open(kal_uint32 port);
+
+/********************************************************
+ * Function
+ * spi_close
+ * Description
+ * Release a SPI handle.
+ * Parameters
+ * handle : [IN] SPI handle. Retrieved from spi_open().
+ * Returns
+ * Return a SPI result code.
+ * Example
+ * <code>
+ * SPI_HANDLE handle;
+ * handle = spi_open(0);
+ * // SPI operations.
+ * spi_close(handle);
+ * </code>
+ ********************************************************/
+SPI_RESULT spi_close(SPI_HANDLE handle);
+
+/***********************************************************************
+ * Function
+ * spi_configure
+ * Description
+ * Configure SPI parameters including timing parameters and waveform parameters.
+ * SPI parameters must be set before any SPI transmissions.
+ * Parameters
+ * handle : [IN] SPI handle. Retrieved from spi_open().
+ * pConfigParam : [IN] SPI parameters. Refer to SPI_CONFIG_PARAM_T for details.
+ * Returns
+ * Return a SPI result code.
+ * Example
+ * <code>
+ * SPI_HANDLE handle;
+ * SPI_CONFIG_PARAM_T param;
+ * handle = spi_open(0);
+ * param.cs_setup_time = 5;
+ * param.cs_hold_time = 5;
+ * param.cs_idle_time = 5;
+ * param.clk_low_time = 5;
+ * param.clk_high_time = 5;
+ * param.tx_mlsb = SPI_LSB;
+ * param.rx_mlsb = SPI_LSB;
+ * param.clk_polarity = SPI_CPOL_0;
+ * param.clk_fmt = SPI_CPHA_0;
+ * spi_configure(handle, &param);
+ * // ...
+ * spi_close(handle);
+ * </code>
+ ***********************************************************************/
+SPI_RESULT spi_configure(SPI_HANDLE handle, SPI_CONFIG_PARAM_T* pConfigParam);
+
+/*******************************************************************************
+ * Function
+ * spi_write
+ * Description
+ * Fire a SPI transmission for output.
+ * Parameters
+ * handle : [IN] SPI handle. Retrieved from spi_open().
+ * pBuffer : [IN] Data buffer for output.
+ * length : [IN] Data length for one package. Unit in bytes. <color Red><b>If count > 1, length must be 4X.</b></color>
+ * count : [IN] Package count.<b> <color Red>If count > 1, length must be 4X.</b></color>
+ * fCB : [IN] Specifies the callback function when the transmission completes.
+ * If fCB is specified, SPI driver uses interrupt mode. This API is asynchronous.
+ * If fCB is NULL, SPI drvier uses polling mode. This API becomes synchronous.
+ * Returns
+ * Return a SPI result code.
+ * Example
+ * <code>
+ * SPI_HANDLE handle;
+ * SPI_CONFIG_PARAM_T param;
+ * handle = spi_open(0);
+ * // ...
+ * spi_configure(handle, &param);
+ *
+ * // Synchronous call.
+ * spi_write(handle, spi_test_buffer1, 1024, 1, NULL);
+ *
+ * // Asynchronous call.
+ * spi_write(handle, spi_test_buffer1, 1024, 1, spi_test_cb);
+ * // Wait for a event which is set in callback function.
+ * // ...
+ * spi_close(handle);
+ * </code>
+ *******************************************************************************/
+SPI_RESULT spi_write(SPI_HANDLE handle, void* pBuffer, kal_uint32 length, kal_uint32 count, SPI_CALLBACK fCB);
+
+/*******************************************************************************
+ * Function
+ * spi_read
+ * Description
+ * Fire a SPI transmission for input.
+ * Parameters
+ * handle : [IN] SPI handle. Retrieved from spi_open().
+ * pBuffer : [OUT] Data buffer for input.
+ * length : [IN] Data length for one package. Unit in bytes. <color Red><b>If count > 1, length must be 4X.</b></color>
+ * count : [IN] Package count. <color Red><b>If count > 1, length must be 4X.</b></color>
+ * fCB : [IN] Specifies the callback function when the transmission completes.
+ * If fCB is specified, SPI driver uses interrupt mode. This API is asynchronous.
+ * If fCB is NULL, SPI drvier uses polling mode. This API becomes synchronous.
+ * Returns
+ * Return a SPI result code.
+ * Example
+ * <code>
+ * SPI_HANDLE handle;
+ * SPI_CONFIG_PARAM_T param;
+ * handle = spi_open(0);
+ * // ...
+ * spi_configure(handle, &param);
+ *
+ * // Synchronous call.
+ * spi_read(handle, spi_test_buffer2, 1024, 1, NULL);
+ *
+ * // Asynchronous call.
+ * spi_read(handle, spi_test_buffer2, 1024, 1, spi_test_cb);
+ * // Wait for a event which is set in callback function.
+ * // ...
+ * spi_close(handle);
+ * </code>
+ *******************************************************************************/
+SPI_RESULT spi_read(SPI_HANDLE handle, void* pBuffer, kal_uint32 length, kal_uint32 count, SPI_CALLBACK fCB);
+
+/***********************************************************************************
+ * Function
+ * spi_readwrite
+ * Description
+ * Fire a SPI transmission for input and output. This transaction uses
+ * duplex mode of SPI.
+ * Parameters
+ * handle : [IN] SPI handle. Retrieved from spi_open().
+ * pOutBuffer : [IN] Data buffer for output.
+ * pInBuffer : [OUT] Data buffer for input.
+ * length : [IN] Data length for one package. Unit in bytes. <color Red><b>If count > 1, length must be 4X.</b></color>
+ * count : [IN] Package count. <color Red><b>If count > 1, length must be 4X.</b></color>
+ * fCB : [IN] Specifies the callback function when the transmission completes.
+ * If fCB is specified, SPI driver uses interrupt mode. This API is asynchronous.
+ * If fCB is NULL, SPI drvier uses polling mode. This API becomes synchronous.
+ * Returns
+ * Return a SPI result code.
+ * Example
+ * <code>
+ * SPI_HANDLE handle;
+ * SPI_CONFIG_PARAM_T param;
+ * handle = spi_open(0);
+ * // ...
+ * spi_configure(handle, &param);
+ *
+ * // Synchronous call.
+ * spi_readwrite(handle, spi_test_buffer1, spi_test_buffer2, 1024, 1, NULL);
+ *
+ * // Asynchronous call.
+ * spi_readwrite(handle, spi_test_buffer1, spi_test_buffer2, 1024, 1, spi_test_cb);
+ * // Wait for a event which is set in callback function.
+ * // ...
+ * spi_close(handle);
+ * </code>
+ ***********************************************************************************/
+SPI_RESULT spi_readwrite(SPI_HANDLE handle, void* pOutBuffer, void* pInBuffer, kal_uint32 length, kal_uint32 count, SPI_CALLBACK fCB);
+
+/*****************************************************************************
+ * Function
+ * spi_power_ctrl
+ * Description
+ * Enable or disable SPI Controller power.
+ * <textattr color="Red">This API is currently not implemented. SPI power will be turned on when calling spi_open() and turned off when calling</textattr> spi_close().
+ * Parameters
+ * handle : [IN] SPI handle. Retrieved from spi_open().
+ * bPowerOn : [IN] Set KAL_TRUE to power on SPI Controller. Set KAL_FALSE to power off SPI Controller.
+ * Returns
+ * Return a SPI result code.
+ * Example
+ * <code>
+ * SPI_HANDLE handle;
+ * handle = spi_open(0);
+ * spi_power_ctrl(handle, KAL_TRUE);
+ * // SPI operations.
+ * spi_power_ctrl(handle, KAL_FALSE);
+ * spi_close(handle);
+ * </code>
+ *****************************************************************************/
+SPI_RESULT spi_power_ctrl(SPI_HANDLE handle, kal_bool bPowerOn);
+
+/*****************************************************************************
+ * Function
+ * spi_ioctl
+ * Description
+ * IO Control for SPI driver.
+ * A series of SPI control code is defined for extension usage. Refer to SPI_IOCTL_CODE.
+ * Parameters
+ * handle : [IN] SPI handle. Retrieved from spi_open().
+ * code : [IN] SPI control code. Refer to SPI_IOCTL_CODE.
+ * pParam : [IN/OUT] Parameter for SPI IO Control. The definition depends on the specified control code. Refer to SPI_IOCTL_CODE.
+ * Returns
+ * Return a SPI result code.
+ * The return value is SPI_RESULT_NOT_SUPPORTED if the current platform does not support the sepcific control code.
+ * Example
+ * <code>
+ * SPI_HANDLE handle;
+ * SPI_MODE_T SetMode;
+ * handle = spi_open(0);
+ * // Test for deassert mode.
+ * SetMode.mode = SPI_MODE_DEASSERT;
+ * SetMode.bEnable = KAL_TRUE;
+ * spi_ioctl(handle, SPI_IOCTL_SET_MODE, &SetMode);
+ * spi_readwrite(handle, spi_test_buffer1, spi_test_buffer2, 1024, 1, NULL);
+ * SetMode.bEnable = KAL_FALSE;
+ * spi_ioctl(handle, SPI_IOCTL_SET_MODE, &SetMode);
+ * spi_close(handle);
+ * </code>
+ *****************************************************************************/
+SPI_RESULT spi_ioctl(SPI_HANDLE handle, SPI_IOCTL_CODE code, void* pParam);
+
+#endif
+#endif
diff --git a/mcu/interface/driver/peripheral/spmi.h b/mcu/interface/driver/peripheral/spmi.h
new file mode 100644
index 0000000..82e1011
--- /dev/null
+++ b/mcu/interface/driver/peripheral/spmi.h
@@ -0,0 +1,151 @@
+/* Copyright Statement:
+ *
+ * This software/firmware and related documentation ("MediaTek Software") are
+ * protected under relevant copyright laws. The information contained herein is
+ * confidential and proprietary to MediaTek Inc. and/or its licensors. Without
+ * the prior written permission of MediaTek inc. and/or its licensors, any
+ * reproduction, modification, use or disclosure of MediaTek Software, and
+ * information contained herein, in whole or in part, shall be strictly
+ * prohibited.
+ *
+ * MediaTek Inc. (C) 2019. All rights reserved.
+ *
+ * BY OPENING THIS FILE, RECEIVER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+ * THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+ * RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO RECEIVER
+ * ON AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL
+ * WARRANTIES, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR
+ * NONINFRINGEMENT. NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH
+ * RESPECT TO THE SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY,
+ * INCORPORATED IN, OR SUPPLIED WITH THE MEDIATEK SOFTWARE, AND RECEIVER AGREES
+ * TO LOOK ONLY TO SUCH THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO.
+ * RECEIVER EXPRESSLY ACKNOWLEDGES THAT IT IS RECEIVER'S SOLE RESPONSIBILITY TO
+ * OBTAIN FROM ANY THIRD PARTY ALL PROPER LICENSES CONTAINED IN MEDIATEK
+ * SOFTWARE. MEDIATEK SHALL ALSO NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE
+ * RELEASES MADE TO RECEIVER'S SPECIFICATION OR TO CONFORM TO A PARTICULAR
+ * STANDARD OR OPEN FORUM. RECEIVER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S
+ * ENTIRE AND CUMULATIVE LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE
+ * RELEASED HEREUNDER WILL BE, AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE
+ * MEDIATEK SOFTWARE AT ISSUE, OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE
+ * CHARGE PAID BY RECEIVER TO MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+ *
+ * The following software/firmware and/or related documentation ("MediaTek
+ * Software") have been modified by MediaTek Inc. All revisions are subject to
+ * any receiver's applicable license agreements with MediaTek Inc.
+ */
+#ifndef __SPMI_H__
+#define __SPMI_H__
+#define SPMI_GROUP_ID 0xB
+
+/* Maximum slave identifier */
+#define SPMI_MAX_SLAVE_ID 16
+
+/* SPMI Commands */
+#define SPMI_CMD_EXT_WRITE 0x00
+#define SPMI_CMD_RESET 0x10
+#define SPMI_CMD_SLEEP 0x11
+#define SPMI_CMD_SHUTDOWN 0x12
+#define SPMI_CMD_WAKEUP 0x13
+#define SPMI_CMD_AUTHENTICATE 0x14
+#define SPMI_CMD_MSTR_READ 0x15
+#define SPMI_CMD_MSTR_WRITE 0x16
+#define SPMI_CMD_TRANSFER_BUS_OWNERSHIP 0x1A
+#define SPMI_CMD_DDB_MASTER_READ 0x1B
+#define SPMI_CMD_DDB_SLAVE_READ 0x1C
+#define SPMI_CMD_EXT_READ 0x20
+#define SPMI_CMD_EXT_WRITEL 0x30
+#define SPMI_CMD_EXT_READL 0x38
+#define SPMI_CMD_WRITE 0x40
+#define SPMI_CMD_READ 0x60
+#define SPMI_CMD_ZERO_WRITE 0x80
+
+/* enum marco for cmd/channel */
+enum
+{
+ SPMI_MASTER_0 = 0,
+ SPMI_MASTER_1,
+ SPMI_MASTER_P_1,
+ SPMI_MASTER_MAX
+};
+
+enum
+{
+ SPMI_SLAVE_0 = 0,
+ SPMI_SLAVE_1,
+ SPMI_SLAVE_2,
+ SPMI_SLAVE_3,
+ SPMI_SLAVE_4,
+ SPMI_SLAVE_5,
+ SPMI_SLAVE_6,
+ SPMI_SLAVE_7,
+ SPMI_SLAVE_8,
+ SPMI_SLAVE_9,
+ SPMI_SLAVE_10,
+ SPMI_SLAVE_11,
+ SPMI_SLAVE_12,
+ SPMI_SLAVE_13,
+ SPMI_SLAVE_14,
+ SPMI_SLAVE_15
+};
+
+enum slv_type
+{
+ BUCK_CPU,
+ BUCK_GPU,
+ BUCK_MD,
+ BUCK_RF,
+ MAIN_PMIC,
+ BUCK_VPU,
+ SUB_PMIC,
+ SLV_TYPE_MAX
+};
+
+enum slv_type_id
+{
+ BUCK_RF_ID = 1,
+ BUCK_MD_ID = 3,
+ MAIN_PMIC_ID = 5,
+ BUCK_CPU_ID = 6,
+ BUCK_GPU_ID = 7,
+ BUCK_VPU_ID,
+ SUB_PMIC_ID = 10,
+ SLV_TYPE_ID_MAX
+};
+
+struct spmi_device {
+ int slvid;
+ int grpiden;
+ enum slv_type type;
+ enum slv_type_id type_id;
+ int mstid;
+ unsigned short hwcid_addr;
+ unsigned char hwcid_val;
+ unsigned short swcid_addr;
+ unsigned char swcid_val;
+ struct pmif *pmif_arb;
+};
+
+/* external API */
+int spmi_register_zero_write(struct spmi_device *dev,
+ unsigned int addr, unsigned char data);
+int spmi_register_read(struct spmi_device *dev,
+ unsigned int addr, unsigned char *buf);
+int spmi_register_write(struct spmi_device *dev,
+ unsigned int addr, unsigned char data);
+int spmi_ext_register_read(struct spmi_device *dev,
+ unsigned int addr, unsigned char *buf, unsigned short len);
+int spmi_ext_register_write(struct spmi_device *dev,
+ unsigned int addr, const unsigned char *buf, unsigned short len);
+int spmi_ext_register_readl(struct spmi_device *dev, unsigned int addr,
+ unsigned char *buf, unsigned short len);
+int spmi_ext_register_writel(struct spmi_device *dev, unsigned int addr,
+ const unsigned char *buf, unsigned short len);
+int spmi_ext_register_readl_field(struct spmi_device *dev, unsigned int addr,
+ unsigned char *buf, unsigned short len, unsigned short mask,
+ unsigned short shift);
+int spmi_ext_register_writel_field(struct spmi_device *dev, unsigned int addr,
+ const unsigned char *buf, unsigned short len, unsigned short mask,
+ unsigned short shift);
+
+#endif /*__SPMI_H__*/
diff --git a/mcu/interface/driver/peripheral/uart_sw.h b/mcu/interface/driver/peripheral/uart_sw.h
new file mode 100644
index 0000000..6b4c4f7
--- /dev/null
+++ b/mcu/interface/driver/peripheral/uart_sw.h
@@ -0,0 +1,660 @@
+/*****************************************************************************
+* Copyright Statement:
+* --------------------
+* This software is protected by Copyright and the information contained
+* herein is confidential. The software may not be copied and the information
+* contained herein may not be used or disclosed except with the written
+* permission of MediaTek Inc. (C) 2005
+*
+* BY OPENING THIS FILE, BUYER HEREBY UNEQUIVOCALLY ACKNOWLEDGES AND AGREES
+* THAT THE SOFTWARE/FIRMWARE AND ITS DOCUMENTATIONS ("MEDIATEK SOFTWARE")
+* RECEIVED FROM MEDIATEK AND/OR ITS REPRESENTATIVES ARE PROVIDED TO BUYER ON
+* AN "AS-IS" BASIS ONLY. MEDIATEK EXPRESSLY DISCLAIMS ANY AND ALL WARRANTIES,
+* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT.
+* NEITHER DOES MEDIATEK PROVIDE ANY WARRANTY WHATSOEVER WITH RESPECT TO THE
+* SOFTWARE OF ANY THIRD PARTY WHICH MAY BE USED BY, INCORPORATED IN, OR
+* SUPPLIED WITH THE MEDIATEK SOFTWARE, AND BUYER AGREES TO LOOK ONLY TO SUCH
+* THIRD PARTY FOR ANY WARRANTY CLAIM RELATING THERETO. MEDIATEK SHALL ALSO
+* NOT BE RESPONSIBLE FOR ANY MEDIATEK SOFTWARE RELEASES MADE TO BUYER'S
+* SPECIFICATION OR TO CONFORM TO A PARTICULAR STANDARD OR OPEN FORUM.
+*
+* BUYER'S SOLE AND EXCLUSIVE REMEDY AND MEDIATEK'S ENTIRE AND CUMULATIVE
+* LIABILITY WITH RESPECT TO THE MEDIATEK SOFTWARE RELEASED HEREUNDER WILL BE,
+* AT MEDIATEK'S OPTION, TO REVISE OR REPLACE THE MEDIATEK SOFTWARE AT ISSUE,
+* OR REFUND ANY SOFTWARE LICENSE FEES OR SERVICE CHARGE PAID BY BUYER TO
+* MEDIATEK FOR SUCH MEDIATEK SOFTWARE AT ISSUE.
+*
+* THE TRANSACTION CONTEMPLATED HEREUNDER SHALL BE CONSTRUED IN ACCORDANCE
+* WITH THE LAWS OF THE STATE OF CALIFORNIA, USA, EXCLUDING ITS CONFLICT OF
+* LAWS PRINCIPLES. ANY DISPUTES, CONTROVERSIES OR CLAIMS ARISING THEREOF AND
+* RELATED THERETO SHALL BE SETTLED BY ARBITRATION IN SAN FRANCISCO, CA, UNDER
+* THE RULES OF THE INTERNATIONAL CHAMBER OF COMMERCE (ICC).
+*
+*****************************************************************************/
+
+/*****************************************************************************
+ *
+ * Filename:
+ * ---------
+ * uart_sw.h
+ *
+ * Project:
+ * --------
+ * Maui_Software
+ *
+ * Description:
+ * ------------
+ * This file is intends for UART driver.
+ *
+ * Author:
+ * -------
+ * -------
+ *
+ *============================================================================
+ * HISTORY
+ * Below this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *------------------------------------------------------------------------------
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+ *------------------------------------------------------------------------------
+ * Upper this line, this part is controlled by PVCS VM. DO NOT MODIFY!!
+ *============================================================================
+ ****************************************************************************/
+#ifndef UART_SW_H
+#define UART_SW_H
+
+#include "drv_features.h"
+#include "kal_public_defs.h" //MSBB change #include "stack_config.h"
+#include "bmd.h"
+#include "drv_comm.h"
+#include "dcl.h"
+
+ #include "kal_general_types.h"
+ #include "kal_public_defs.h"
+
+#if 0
+#ifdef __UART3_SUPPORT__
+/* under construction !*/
+/* under construction !*/
+#else /*__UART3_SUPPORT__*/
+/* under construction !*/
+/* under construction !*/
+#endif /*__UART3_SUPPORT__*/
+#endif
+#define MAX_UART_PORT_NUM 2
+#define MAX_UART_TUNNEL_NUM 4
+
+
+typedef enum { //toy add for single tunnel vfifo.
+ uart1_rx_tunnel=0,
+ uart1_tx_tunnel,
+ uart2_rx_tunnel,
+ uart2_tx_tunnel,
+ uart3_rx_tunnel,
+ uart3_tx_tunnel,
+ uart_null_tunnel=99 /* a dummy tunnel for those who doesn't use physical port */
+} UART_TUNNEL;
+
+
+/*UART Customization */
+typedef struct{
+ kal_uint8* rx_adrs;
+ kal_uint8* tx_adrs;
+ kal_uint8* txisr_adrs;
+ kal_uint16 rx_len;
+ kal_uint16 tx_len;
+ kal_uint16 txisr_len;
+ module_type owerid; // only the specified owner can use it
+}UART_ring_buffer_struct;
+
+#if defined(__DMA_UART_VFIFO_SINGLE_TUNNEL__)
+typedef struct { // toy modify for VFIFO single tunnel
+ UART_ring_buffer_struct ring[MAX_UART_PORT_NUM];
+ #ifndef __UART_SUPPORT_6_VFIFO_CHANNEL__
+ UART_TUNNEL not_support_VFIFO_TUNNEL1;
+ UART_TUNNEL not_support_VFIFO_TUNNEL2;
+ #endif
+} UART_rings_struct;
+#else
+typedef struct {
+ UART_ring_buffer_struct ring[MAX_UART_PORT_NUM];
+ kal_uint16 not_support_VFIFO;
+} UART_rings_struct;
+#endif
+
+typedef struct {
+ const UART_rings_struct * (*UART_Get_Data)(void);
+}UART_customize_function_struct;
+
+
+/*UART customize*/
+extern void uart_customize_init(void);
+/*for VFIFO*/
+
+#endif /*UART_SW_H*/
+
+
diff --git a/mcu/interface/driver/peripheral/wdt_hw_public.h b/mcu/interface/driver/peripheral/wdt_hw_public.h
new file mode 100644
index 0000000..e4f4e58
--- /dev/null
+++ b/mcu/interface/driver/peripheral/wdt_hw_public.h
@@ -0,0 +1,26 @@
+#ifndef WDT_PUBLIC_H
+#define WDT_PUBLIC_H
+
+#include "drv_features_wdt.h"
+#include "reg_base.h"
+#include "kal_general_types.h"
+
+
+extern const kal_uint32 g_WATCHDOG_RESTART_REG;
+extern const kal_uint32 g_WATCHDOG_RESTART_VALUE;
+extern const kal_uint32 g_ABNORMAL_RST_REG;
+extern const kal_uint32 g_ABNORMAL_RST_VAL;
+
+//WDT_RESINTERVAL will be 0xfff(default) when the first bootup, then WDT_RESINTERVAL will be 0xffa when wdt_init()
+//if the value is 0xfff when bootup,we will kown this is the first bootup or normal reset
+//if the value is 0ffa when bootup,we will kown this is abnormal reset
+extern kal_bool Is_WDT_Init(void);
+
+extern kal_uint32 Get_WATCHDOG_BASE(void);
+
+extern kal_uint32 Get_WATCHDOG_RESTART_CMD(void);
+
+
+#endif
+
+